Index: /trunk/firmware_v3/.mxproject =================================================================== --- /trunk/firmware_v3/.mxproject (revision 41) +++ /trunk/firmware_v3/.mxproject (revision 41) @@ -0,0 +1,37 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_iwdg.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_usart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dmamux.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_iwdg.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_usart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\adc.c;Core\Src\dma.c;Core\Src\iwdg.c;Core\Src\tim.c;Core\Src\usart.c;Core\Src\stm32c0xx_it.c;Core\Src\stm32c0xx_hal_msp.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;;; +HeaderPath=Drivers\STM32C0xx_HAL_Driver\Inc;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32C0xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32C031xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=9 +HeaderFiles#0=..\Core\Inc\gpio.h +HeaderFiles#1=..\Core\Inc\adc.h +HeaderFiles#2=..\Core\Inc\dma.h +HeaderFiles#3=..\Core\Inc\iwdg.h +HeaderFiles#4=..\Core\Inc\tim.h +HeaderFiles#5=..\Core\Inc\usart.h +HeaderFiles#6=..\Core\Inc\stm32c0xx_it.h +HeaderFiles#7=..\Core\Inc\stm32c0xx_hal_conf.h +HeaderFiles#8=..\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Core\Inc +HeaderFiles=; +SourceFileListSize=9 +SourceFiles#0=..\Core\Src\gpio.c +SourceFiles#1=..\Core\Src\adc.c +SourceFiles#2=..\Core\Src\dma.c +SourceFiles#3=..\Core\Src\iwdg.c +SourceFiles#4=..\Core\Src\tim.c +SourceFiles#5=..\Core\Src\usart.c +SourceFiles#6=..\Core\Src\stm32c0xx_it.c +SourceFiles#7=..\Core\Src\stm32c0xx_hal_msp.c +SourceFiles#8=..\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Core\Src +SourceFiles=; + Index: /trunk/firmware_v3/Core/Inc/adc.h =================================================================== --- /trunk/firmware_v3/Core/Inc/adc.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/adc.h (revision 41) @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file adc.h + * @brief This file contains all the function prototypes for + * the adc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern ADC_HandleTypeDef hadc1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_ADC1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_H__ */ + Index: /trunk/firmware_v3/Core/Inc/dma.h =================================================================== --- /trunk/firmware_v3/Core/Inc/dma.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/dma.h (revision 41) @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + Index: /trunk/firmware_v3/Core/Inc/gpio.h =================================================================== --- /trunk/firmware_v3/Core/Inc/gpio.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/gpio.h (revision 41) @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + Index: /trunk/firmware_v3/Core/Inc/iwdg.h =================================================================== --- /trunk/firmware_v3/Core/Inc/iwdg.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/iwdg.h (revision 41) @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file iwdg.h + * @brief This file contains all the function prototypes for + * the iwdg.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __IWDG_H__ +#define __IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern IWDG_HandleTypeDef hiwdg; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_IWDG_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IWDG_H__ */ + Index: /trunk/firmware_v3/Core/Inc/main.h =================================================================== --- /trunk/firmware_v3/Core/Inc/main.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/main.h (revision 41) @@ -0,0 +1,148 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +#define SYSTEM_BOOTLOADER_START_ADDR 0x1FFF0000 +#define GOTO_SYSTEM_BOOTLOADER_MARK 0xACCE55ED +#define VREF 3300 +#define BLINK_CODE_WARN_MANUAL 1 +#define BLINK_CODE_ERROR_OVP_LVP 2 +#define BLINK_CODE_ERROR_FAULT_INPUT 3 +#define BLINK_CODE_ERROR_VOLTAGE_DROP 4 +#define BLINK_CODE_ERROR_TEMP 5 + + + +#define LED_RT_OFF_TIME 1000 +#define LED_RT_ON_TIME_WARN_MANUAL_MODE 200 +#define LED_RT_ON_TIME_WARN_FAULT_INPUT 200 +#define LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT 200 +#define LED_RT_ON_TIME_WARN_VOLTAGE_DROP 200 +#define LED_RT_ON_TIME_WARN_TEMP 200 + +#define LED_GN_OFF_TIME 1000 +#define LED_GN_ON_TIME_ON_MODE 200 + +#define BUZZER_OFF_TIME 5000 +#define BUZZER_ON_TIME_CONFIRM 200 +#define BUZZER_ON_TIME_REJECT 500 +#define BUZZER_ON_TIME_ALARM_MANUAL_MODE 200 +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define GPIO_INPUT_MODE_B3_Pin GPIO_PIN_9 +#define GPIO_INPUT_MODE_B3_GPIO_Port GPIOB +#define GPIO_OUTPUT_LED_ON_Pin GPIO_PIN_14 +#define GPIO_OUTPUT_LED_ON_GPIO_Port GPIOC +#define GPIO_OUTPUT_LED_ERROR_Pin GPIO_PIN_15 +#define GPIO_OUTPUT_LED_ERROR_GPIO_Port GPIOC +#define GPIO_INPUT_LVP_Pin GPIO_PIN_0 +#define GPIO_INPUT_LVP_GPIO_Port GPIOA +#define GPIO_INPUT_OVP_Pin GPIO_PIN_1 +#define GPIO_INPUT_OVP_GPIO_Port GPIOA +#define ADC1_IN2_TEMP_SENSOR_Pin GPIO_PIN_2 +#define ADC1_IN2_TEMP_SENSOR_GPIO_Port GPIOA +#define ADC1_IN3_U_IN_Pin GPIO_PIN_3 +#define ADC1_IN3_U_IN_GPIO_Port GPIOA +#define ADC1_IN4_U_OUT_Pin GPIO_PIN_4 +#define ADC1_IN4_U_OUT_GPIO_Port GPIOA +#define ADC1_IN5_RES1_Pin GPIO_PIN_5 +#define ADC1_IN5_RES1_GPIO_Port GPIOA +#define FAN_TACHO_Pin GPIO_PIN_6 +#define FAN_TACHO_GPIO_Port GPIOA +#define FAN_PWM_Pin GPIO_PIN_7 +#define FAN_PWM_GPIO_Port GPIOA +#define GPIO_INPUT_BTN_ON_Pin GPIO_PIN_0 +#define GPIO_INPUT_BTN_ON_GPIO_Port GPIOB +#define GPIO_INPUT_BTN_OFF_Pin GPIO_PIN_1 +#define GPIO_INPUT_BTN_OFF_GPIO_Port GPIOB +#define GPIO_INPUT_FAULT_Pin GPIO_PIN_2 +#define GPIO_INPUT_FAULT_GPIO_Port GPIOB +#define GPIO_OUTPUT_10V_EN_Pin GPIO_PIN_8 +#define GPIO_OUTPUT_10V_EN_GPIO_Port GPIOA +#define GPIO_INPUT_BMS_Pin GPIO_PIN_6 +#define GPIO_INPUT_BMS_GPIO_Port GPIOC +#define R1_Pin GPIO_PIN_12 +#define R1_GPIO_Port GPIOA +#define R2_Pin GPIO_PIN_15 +#define R2_GPIO_Port GPIOA +#define GPIO_OUTPUT_RELAIS_SET_Pin GPIO_PIN_3 +#define GPIO_OUTPUT_RELAIS_SET_GPIO_Port GPIOB +#define GPIO_OUTPUT_RELAIS_RESET_Pin GPIO_PIN_4 +#define GPIO_OUTPUT_RELAIS_RESET_GPIO_Port GPIOB +#define GPIO_OUTPUT_BUZZER_Pin GPIO_PIN_5 +#define GPIO_OUTPUT_BUZZER_GPIO_Port GPIOB +#define GPIO_INPUT_MODE_B0_Pin GPIO_PIN_6 +#define GPIO_INPUT_MODE_B0_GPIO_Port GPIOB +#define GPIO_INPUT_MODE_B1_Pin GPIO_PIN_7 +#define GPIO_INPUT_MODE_B1_GPIO_Port GPIOB +#define GPIO_INPUT_MODE_B2_Pin GPIO_PIN_8 +#define GPIO_INPUT_MODE_B2_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ +// mögliche Kommandos für das Command Register +#define COMMAND_STORE_CONFIG 1 //Parameter speichern +#define COMMAND_FULL_RESTORE 2 //Rücksetzen inkl. Kalibirerwerte --> Aktuell keine vorhanden deshalb gleich 3 +#define COMMAND_FACTORY_RESTORE 3 //Rücksetzen auf Auslieferungszustand +#define COMMAND_RESTORE_LAST_SAVED_VALUES 4 //Parameter aus EEPROm neu laden (z.B. Zum "abbrechen" bei einer versehentlicher Veränderung +#define COMMAND_RESTART 6 // Neustart und Watvhdog test +#define COMMAND_STORE_WITH_SERIAL_NUMBER 1234 // Seriennummer wird gespeichert +#define COMMAND_GOTO_SYS_BOOTLOADER 5458 // Looks like SYSB = System Bootloader +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ Index: /trunk/firmware_v3/Core/Inc/stm32c0xx_hal_conf.h =================================================================== --- /trunk/firmware_v3/Core/Inc/stm32c0xx_hal_conf.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/stm32c0xx_hal_conf.h (revision 41) @@ -0,0 +1,272 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32c0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32c0xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_CONF_H +#define STM32C0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +#define HAL_IWDG_MODULE_ENABLED +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32c0xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +#if !defined (LSI_STARTUP_TIME) +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#endif /* LSI_STARTUP_TIME */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE (12288000UL) /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32c0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32c0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32c0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32c0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32c0xx_hal_adc.h" + #include "stm32c0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32c0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32c0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32c0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32c0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32c0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32c0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32c0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32c0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32c0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32c0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32c0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32c0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32c0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32c0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32c0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32c0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_CONF_H */ Index: /trunk/firmware_v3/Core/Inc/stm32c0xx_it.h =================================================================== --- /trunk/firmware_v3/Core/Inc/stm32c0xx_it.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/stm32c0xx_it.h (revision 41) @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32c0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32C0xx_IT_H +#define __STM32C0xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA1_Channel1_IRQHandler(void); +void DMA1_Channel2_3_IRQHandler(void); +void TIM16_IRQHandler(void); +void USART1_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32C0xx_IT_H */ Index: /trunk/firmware_v3/Core/Inc/tim.h =================================================================== --- /trunk/firmware_v3/Core/Inc/tim.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/tim.h (revision 41) @@ -0,0 +1,60 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim16; + +extern TIM_HandleTypeDef htim17; + +/* USER CODE BEGIN Private defines */ + + +/* USER CODE END Private defines */ + +void MX_TIM16_Init(void); +void MX_TIM17_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* USER CODE BEGIN Prototypes */ + + + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + Index: /trunk/firmware_v3/Core/Inc/usart.h =================================================================== --- /trunk/firmware_v3/Core/Inc/usart.h (revision 41) +++ /trunk/firmware_v3/Core/Inc/usart.h (revision 41) @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USART1_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + Index: /trunk/firmware_v3/Core/Src/adc.c =================================================================== --- /trunk/firmware_v3/Core/Src/adc.c (revision 41) +++ /trunk/firmware_v3/Core/Src/adc.c (revision 41) @@ -0,0 +1,207 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file adc.c + * @brief This file provides code for the configuration + * of the ADC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "adc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +ADC_HandleTypeDef hadc1; +DMA_HandleTypeDef hdma_adc1; + +/* ADC1 init function */ +void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.ScanConvMode = ADC_SCAN_SEQ_FIXED; + hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; + hadc1.Init.LowPowerAutoWait = DISABLE; + hadc1.Init.LowPowerAutoPowerOff = DISABLE; + hadc1.Init.ContinuousConvMode = ENABLE; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.DMAContinuousRequests = ENABLE; + hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_160CYCLES_5; + hadc1.Init.OversamplingMode = ENABLE; + hadc1.Init.Oversampling.Ratio = ADC_OVERSAMPLING_RATIO_256; + hadc1.Init.Oversampling.RightBitShift = ADC_RIGHTBITSHIFT_4; + hadc1.Init.Oversampling.TriggeredMode = ADC_TRIGGEREDMODE_SINGLE_TRIGGER; + hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_2; + sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_3; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_4; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_5; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(adcHandle->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* ADC1 clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA2 ------> ADC1_IN2 + PA3 ------> ADC1_IN3 + PA4 ------> ADC1_IN4 + PA5 ------> ADC1_IN5 + */ + GPIO_InitStruct.Pin = ADC1_IN2_TEMP_SENSOR_Pin|ADC1_IN3_U_IN_Pin|ADC1_IN4_U_OUT_Pin|ADC1_IN5_RES1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA1_Channel1; + hdma_adc1.Init.Request = DMA_REQUEST_ADC1; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_adc1.Init.Mode = DMA_CIRCULAR; + hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } +} + +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) +{ + + if(adcHandle->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA2 ------> ADC1_IN2 + PA3 ------> ADC1_IN3 + PA4 ------> ADC1_IN4 + PA5 ------> ADC1_IN5 + */ + HAL_GPIO_DeInit(GPIOA, ADC1_IN2_TEMP_SENSOR_Pin|ADC1_IN3_U_IN_Pin|ADC1_IN4_U_OUT_Pin|ADC1_IN5_RES1_Pin); + + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + Index: /trunk/firmware_v3/Core/Src/dma.c =================================================================== --- /trunk/firmware_v3/Core/Src/dma.c (revision 41) +++ /trunk/firmware_v3/Core/Src/dma.c (revision 41) @@ -0,0 +1,58 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Channel1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); + /* DMA1_Channel2_3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + Index: /trunk/firmware_v3/Core/Src/gpio.c =================================================================== --- /trunk/firmware_v3/Core/Src/gpio.c (revision 41) +++ /trunk/firmware_v3/Core/Src/gpio.c (revision 41) @@ -0,0 +1,112 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_OUTPUT_LED_ON_Pin|GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIO_OUTPUT_10V_EN_GPIO_Port, GPIO_OUTPUT_10V_EN_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_OUTPUT_RELAIS_SET_Pin|GPIO_OUTPUT_RELAIS_RESET_Pin|GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : GPIO_INPUT_MODE_B3_Pin GPIO_INPUT_BTN_ON_Pin GPIO_INPUT_BTN_OFF_Pin GPIO_INPUT_FAULT_Pin + GPIO_INPUT_MODE_B0_Pin GPIO_INPUT_MODE_B1_Pin GPIO_INPUT_MODE_B2_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_MODE_B3_Pin|GPIO_INPUT_BTN_ON_Pin|GPIO_INPUT_BTN_OFF_Pin|GPIO_INPUT_FAULT_Pin + |GPIO_INPUT_MODE_B0_Pin|GPIO_INPUT_MODE_B1_Pin|GPIO_INPUT_MODE_B2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_OUTPUT_LED_ON_Pin GPIO_OUTPUT_LED_ERROR_Pin */ + GPIO_InitStruct.Pin = GPIO_OUTPUT_LED_ON_Pin|GPIO_OUTPUT_LED_ERROR_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_INPUT_LVP_Pin GPIO_INPUT_OVP_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_LVP_Pin|GPIO_INPUT_OVP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : GPIO_OUTPUT_10V_EN_Pin */ + GPIO_InitStruct.Pin = GPIO_OUTPUT_10V_EN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIO_OUTPUT_10V_EN_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : GPIO_INPUT_BMS_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_BMS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIO_INPUT_BMS_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : R1_Pin R2_Pin */ + GPIO_InitStruct.Pin = R1_Pin|R2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_OUTPUT_RELAIS_SET_Pin GPIO_OUTPUT_RELAIS_RESET_Pin GPIO_OUTPUT_BUZZER_Pin */ + GPIO_InitStruct.Pin = GPIO_OUTPUT_RELAIS_SET_Pin|GPIO_OUTPUT_RELAIS_RESET_Pin|GPIO_OUTPUT_BUZZER_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ Index: /trunk/firmware_v3/Core/Src/iwdg.c =================================================================== --- /trunk/firmware_v3/Core/Src/iwdg.c (revision 41) +++ /trunk/firmware_v3/Core/Src/iwdg.c (revision 41) @@ -0,0 +1,57 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file iwdg.c + * @brief This file provides code for the configuration + * of the IWDG instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "iwdg.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +IWDG_HandleTypeDef hiwdg; + +/* IWDG init function */ +void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_32; + hiwdg.Init.Window = 1000; + hiwdg.Init.Reload = 1000; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + Index: /trunk/firmware_v3/Core/Src/main.c =================================================================== --- /trunk/firmware_v3/Core/Src/main.c (revision 41) +++ /trunk/firmware_v3/Core/Src/main.c (revision 41) @@ -0,0 +1,187 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "adc.h" +#include "dma.h" +#include "iwdg.h" +#include "tim.h" +#include "usart.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_ADC1_Init(); + MX_TIM17_Init(); + MX_USART1_UART_Init(); + MX_TIM16_Init(); + MX_IWDG_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_0); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV4; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ Index: /trunk/firmware_v3/Core/Src/stm32c0xx_hal_msp.c =================================================================== --- /trunk/firmware_v3/Core/Src/stm32c0xx_hal_msp.c (revision 41) +++ /trunk/firmware_v3/Core/Src/stm32c0xx_hal_msp.c (revision 41) @@ -0,0 +1,81 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32c0xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ Index: /trunk/firmware_v3/Core/Src/stm32c0xx_it.c =================================================================== --- /trunk/firmware_v3/Core/Src/stm32c0xx_it.c (revision 41) +++ /trunk/firmware_v3/Core/Src/stm32c0xx_it.c (revision 41) @@ -0,0 +1,238 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32c0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32c0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +#include + +#include "tim.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef hdma_adc1; +extern TIM_HandleTypeDef htim16; +extern DMA_HandleTypeDef hdma_usart1_rx; +extern DMA_HandleTypeDef hdma_usart1_tx; +extern UART_HandleTypeDef huart1; +/* USER CODE BEGIN EV */ + uint32_t captureValue = 0; + uint32_t previousCaptureValue = 0; + uint32_t frequency = 0; + uint32_t ic_overflows = 0; +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32C0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32c0xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles DMA1 channel 1 interrupt. + */ +void DMA1_Channel1_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ + + /* USER CODE END DMA1_Channel1_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ + + /* USER CODE END DMA1_Channel1_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 channel 2 and channel 3 interrupts. + */ +void DMA1_Channel2_3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_rx); + HAL_DMA_IRQHandler(&hdma_usart1_tx); + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 1 */ +} + +/** + * @brief This function handles TIM16 global interrupt. + */ +void TIM16_IRQHandler(void) +{ + /* USER CODE BEGIN TIM16_IRQn 0 */ + + /* USER CODE END TIM16_IRQn 0 */ + HAL_TIM_IRQHandler(&htim16); + /* USER CODE BEGIN TIM16_IRQn 1 */ + + /* USER CODE END TIM16_IRQn 1 */ +} + +/** + * @brief This function handles USART1 interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef* htim) +{ + if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) { + captureValue = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_1); + frequency = HAL_RCC_GetPCLK1Freq() / (htim->Instance->PSC + 1) / (captureValue); + //previousCaptureValue = captureValue; + htim->Instance->CNT=0; //Timer zurücksetzen, damit normalerweise kein Overflow auftritt. Nur bei Drehzahl 0 oder Nahe 0 wird OVL ausgelöst + ic_overflows=0; + } +} + +//----------------------------------------------------------------------------- + +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef* htim) +{ + + + if (htim->Instance == TIM16) + { + ic_overflows++; + if (ic_overflows > 0) frequency = 0; + } +} + +/* USER CODE END 1 */ Index: /trunk/firmware_v3/Core/Src/system_stm32c0xx.c =================================================================== --- /trunk/firmware_v3/Core/Src/system_stm32c0xx.c (revision 41) +++ /trunk/firmware_v3/Core/Src/system_stm32c0xx.c (revision 41) @@ -0,0 +1,246 @@ +/** + ****************************************************************************** + * @file system_stm32c0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32c0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32c0xx_system + * @{ + */ + +/** @addtogroup STM32C0xx_System_Private_Includes + * @{ + */ + +#include "stm32c0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (48000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +#if defined(RCC_HSI48_SUPPORT) +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup STM32C0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +//#define VECT_TAB_SRAM +#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32C0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 12000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32C0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 48 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 48 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t hsidiv; + uint32_t sysdiv; +#if defined(RCC_CR_SYSDIV) + sysdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U); +#else + sysdiv = 1U; +#endif /* RCC_CR_SYSDIV */ + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = (HSE_VALUE / sysdiv); + break; + +#if defined(RCC_HSI48_SUPPORT) + case RCC_CFGR_SW_1: /* HSI48 used as system clock */ + SystemCoreClock = (HSI48_VALUE / sysdiv); + break; +#endif /* RCC_HSI48_SUPPORT */ + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = (LSI_VALUE / sysdiv); + break; + + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = (LSE_VALUE / sysdiv); + break; + + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = ((HSI_VALUE / sysdiv) / hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Core/Src/tim.c =================================================================== --- /trunk/firmware_v3/Core/Src/tim.c (revision 41) +++ /trunk/firmware_v3/Core/Src/tim.c (revision 41) @@ -0,0 +1,251 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +#include + + + + + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim16; +TIM_HandleTypeDef htim17; + +/* TIM16 init function */ +void MX_TIM16_Init(void) +{ + + /* USER CODE BEGIN TIM16_Init 0 */ + + /* USER CODE END TIM16_Init 0 */ + + TIM_IC_InitTypeDef sConfigIC = {0}; + + /* USER CODE BEGIN TIM16_Init 1 */ + + /* USER CODE END TIM16_Init 1 */ + htim16.Instance = TIM16; + htim16.Init.Prescaler = 119; + htim16.Init.CounterMode = TIM_COUNTERMODE_UP; + htim16.Init.Period = 65535; + htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim16.Init.RepetitionCounter = 0; + htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + if (HAL_TIM_Base_Init(&htim16) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_IC_Init(&htim16) != HAL_OK) + { + Error_Handler(); + } + sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING; + sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; + sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; + sConfigIC.ICFilter = 0; + if (HAL_TIM_IC_ConfigChannel(&htim16, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM16_Init 2 */ + + /* USER CODE END TIM16_Init 2 */ + +} +/* TIM17 init function */ +void MX_TIM17_Init(void) +{ + + /* USER CODE BEGIN TIM17_Init 0 */ + + // FAN PWM at 25kHz + + /* USER CODE END TIM17_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; + + /* USER CODE BEGIN TIM17_Init 1 */ + + /* USER CODE END TIM17_Init 1 */ + htim17.Instance = TIM17; + htim17.Init.Prescaler = 0; + htim17.Init.CounterMode = TIM_COUNTERMODE_UP; + htim17.Init.Period = 479; + htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim17.Init.RepetitionCounter = 0; + htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + if (HAL_TIM_Base_Init(&htim17) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim17) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_LOW; + sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + if (HAL_TIM_PWM_ConfigChannel(&htim17, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = 0; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + sBreakDeadTimeConfig.BreakFilter = 0; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + if (HAL_TIMEx_ConfigBreakDeadTime(&htim17, &sBreakDeadTimeConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM17_Init 2 */ + + + + /* USER CODE END TIM17_Init 2 */ + HAL_TIM_MspPostInit(&htim17); + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(tim_baseHandle->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspInit 0 */ + + /* USER CODE END TIM16_MspInit 0 */ + /* TIM16 clock enable */ + __HAL_RCC_TIM16_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM16 GPIO Configuration + PA6 ------> TIM16_CH1 + */ + GPIO_InitStruct.Pin = FAN_TACHO_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_TIM16; + HAL_GPIO_Init(FAN_TACHO_GPIO_Port, &GPIO_InitStruct); + + /* TIM16 interrupt Init */ + HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM16_IRQn); + /* USER CODE BEGIN TIM16_MspInit 1 */ + + /* USER CODE END TIM16_MspInit 1 */ + } + else if(tim_baseHandle->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspInit 0 */ + + /* USER CODE END TIM17_MspInit 0 */ + /* TIM17 clock enable */ + __HAL_RCC_TIM17_CLK_ENABLE(); + /* USER CODE BEGIN TIM17_MspInit 1 */ + + /* USER CODE END TIM17_MspInit 1 */ + } +} +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(timHandle->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspPostInit 0 */ + + /* USER CODE END TIM17_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM17 GPIO Configuration + PA7 ------> TIM17_CH1 + */ + GPIO_InitStruct.Pin = FAN_PWM_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_TIM17; + HAL_GPIO_Init(FAN_PWM_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM17_MspPostInit 1 */ + + if (HAL_TIM_PWM_Start(timHandle, TIM_CHANNEL_1) != HAL_OK) Error_Handler(); + + /* USER CODE END TIM17_MspPostInit 1 */ + } + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspDeInit 0 */ + + /* USER CODE END TIM16_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM16_CLK_DISABLE(); + + /**TIM16 GPIO Configuration + PA6 ------> TIM16_CH1 + */ + HAL_GPIO_DeInit(FAN_TACHO_GPIO_Port, FAN_TACHO_Pin); + + /* TIM16 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM16_IRQn); + /* USER CODE BEGIN TIM16_MspDeInit 1 */ + + /* USER CODE END TIM16_MspDeInit 1 */ + } + else if(tim_baseHandle->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspDeInit 0 */ + + /* USER CODE END TIM17_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM17_CLK_DISABLE(); + /* USER CODE BEGIN TIM17_MspDeInit 1 */ + + /* USER CODE END TIM17_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + + +/* USER CODE END 1 */ + Index: /trunk/firmware_v3/Core/Src/usart.c =================================================================== --- /trunk/firmware_v3/Core/Src/usart.c (revision 41) +++ /trunk/firmware_v3/Core/Src/usart.c (revision 41) @@ -0,0 +1,187 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart1; +DMA_HandleTypeDef hdma_usart1_rx; +DMA_HandleTypeDef hdma_usart1_tx; + +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 19200; + huart1.Init.WordLength = UART_WORDLENGTH_9B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_EVEN; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 DMA Init */ + /* USART1_RX Init */ + hdma_usart1_rx.Instance = DMA1_Channel2; + hdma_usart1_rx.Init.Request = DMA_REQUEST_USART1_RX; + hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_rx.Init.Mode = DMA_NORMAL; + hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); + + /* USART1_TX Init */ + hdma_usart1_tx.Instance = DMA1_Channel3; + hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX; + hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_tx.Init.Mode = DMA_NORMAL; + hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USART1 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + Index: /trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h (revision 41) @@ -0,0 +1,6839 @@ +/** + ****************************************************************************** + * @file stm32c031xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32c031xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32c031xx + * @{ + */ + +#ifndef STM32C031xx_H +#define STM32C031xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32C0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32C0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32c031xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32C0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMAMUX1_IRQn = 11, /*!< DMAMUX Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32c0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */ + __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */ + __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */ + __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00003000UL) /*!< maximum SRAM size (up to 12 KBytes) */ + +#define FLASH_SIZE_DEFAULT 0x8000U /*!< Flash memory default size */ + +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) + + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ + +/*!< Bootloader Firmware */ + +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF1600UL) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/********************************* DEVICE ID ********************************/ +#define DEV_ID 0x453UL + +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ + +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ + +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ + +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ + +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ + +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ + +#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ +#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ +#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk +#define FLASH_ACR_DBG_SWEN_Pos (18U) +#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ +#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x00000078 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_SEC_PROT_Pos (28U) +#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ +#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_EN_Pos (8U) +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk +#define FLASH_OPTR_BORR_LEV_Pos (9U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORF_LEV_Pos (11U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (15U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_HSE_NOT_REMAPPED_Pos (21U) +#define FLASH_OPTR_HSE_NOT_REMAPPED_Msk (0x1UL << FLASH_OPTR_HSE_NOT_REMAPPED_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_HSE_NOT_REMAPPED FLASH_OPTR_HSE_NOT_REMAPPED_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_SECURE_MUXING_EN_Pos (23U) +#define FLASH_OPTR_SECURE_MUXING_EN_Msk (0x1UL << FLASH_OPTR_SECURE_MUXING_EN_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk +#define FLASH_OPTR_NRST_MODE_Pos (27U) +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_IRHEN_Pos (29U) +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x3FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x3FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000003F */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0xFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x000F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0xFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x000F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x3FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x3FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000003F */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk + + +/****************** Bits definition for FLASH_SECR register *****************/ +#define FLASH_SECR_SEC_SIZE_Pos (0U) +#define FLASH_SECR_SEC_SIZE_Msk (0x1FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000001F */ +#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk +#define FLASH_SECR_BOOT_LOCK_Pos (16U) +#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ +#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armcc.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armcc.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armcc.h (revision 41) @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armclang.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armclang.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armclang.h (revision 41) @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armclang_ltm.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armclang_ltm.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_armclang_ltm.h (revision 41) @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_compiler.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_compiler.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_compiler.h (revision 41) @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_gcc.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_gcc.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_gcc.h (revision 41) @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_iccarm.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_iccarm.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_iccarm.h (revision 41) @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_version.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_version.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/cmsis_version.h (revision 41) @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv81mml.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv81mml.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv81mml.h (revision 41) @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv8mbl.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv8mbl.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv8mbl.h (revision 41) @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv8mml.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv8mml.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_armv8mml.h (revision 41) @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm0.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm0.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm0.h (revision 41) @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm0plus.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm0plus.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm0plus.h (revision 41) @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm1.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm1.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm1.h (revision 41) @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm23.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm23.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm23.h (revision 41) @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm3.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm3.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm3.h (revision 41) @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm33.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm33.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm33.h (revision 41) @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm35p.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm35p.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm35p.h (revision 41) @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm4.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm4.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm4.h (revision 41) @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm55.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm55.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm55.h (revision 41) @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm7.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm7.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm7.h (revision 41) @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm85.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm85.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_cm85.h (revision 41) @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_sc000.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_sc000.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_sc000.h (revision 41) @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_sc300.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_sc300.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_sc300.h (revision 41) @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/core_starmc1.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/core_starmc1.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/core_starmc1.h (revision 41) @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/mpu_armv7.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/mpu_armv7.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/mpu_armv7.h (revision 41) @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif Index: /trunk/firmware_v3/Drivers/CMSIS/Include/mpu_armv8.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/mpu_armv8.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/mpu_armv8.h (revision 41) @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + Index: /trunk/firmware_v3/Drivers/CMSIS/Include/pac_armv81.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/pac_armv81.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/pac_armv81.h (revision 41) @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ Index: /trunk/firmware_v3/Drivers/CMSIS/Include/pmu_armv8.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/pmu_armv8.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/pmu_armv8.h (revision 41) @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif Index: /trunk/firmware_v3/Drivers/CMSIS/Include/tz_context.h =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/Include/tz_context.h (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/Include/tz_context.h (revision 41) @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H Index: /trunk/firmware_v3/Drivers/CMSIS/LICENSE.txt =================================================================== --- /trunk/firmware_v3/Drivers/CMSIS/LICENSE.txt (revision 41) +++ /trunk/firmware_v3/Drivers/CMSIS/LICENSE.txt (revision 41) @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (revision 41) @@ -0,0 +1,4421 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \ + defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h (revision 41) @@ -0,0 +1,799 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_H +#define STM32C0xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_ll_system.h" +#include "stm32c0xx_hal_conf.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ + +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_BIND_CFG Bind Pin config + * @{ + */ + +#if (DEV_ID == 0x443UL) +#define HAL_BIND_SO8_PIN1_PB7 LL_PINMUX_SO8_PIN1_PB7 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */ +#define HAL_BIND_SO8_PIN1_PC14 LL_PINMUX_SO8_PIN1_PC14 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */ +#define HAL_BIND_SO8_PIN4_PF2 LL_PINMUX_SO8_PIN4_PF2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */ +#define HAL_BIND_SO8_PIN4_PA0 LL_PINMUX_SO8_PIN4_PA0 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */ +#define HAL_BIND_SO8_PIN4_PA1 LL_PINMUX_SO8_PIN4_PA1 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */ +#define HAL_BIND_SO8_PIN4_PA2 LL_PINMUX_SO8_PIN4_PA2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */ +#define HAL_BIND_SO8_PIN5_PA8 LL_PINMUX_SO8_PIN5_PA8 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8*/ +#define HAL_BIND_SO8_PIN5_PA11 LL_PINMUX_SO8_PIN5_PA11 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */ +#define HAL_BIND_SO8_PIN8_PA14 LL_PINMUX_SO8_PIN8_PA14 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */ +#define HAL_BIND_SO8_PIN8_PB6 LL_PINMUX_SO8_PIN8_PB6 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */ +#define HAL_BIND_SO8_PIN8_PC15 LL_PINMUX_SO8_PIN8_PC15 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */ +#define HAL_BIND_WLCSP12_PINE2_PA7 LL_PINMUX_WLCSP12_PINE2_PA7 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */ +#define HAL_BIND_WLCSP12_PINE2_PA12 LL_PINMUX_WLCSP12_PINE2_PA12 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12*/ +#define HAL_BIND_WLCSP12_PINF1_PA3 LL_PINMUX_WLCSP12_PINF1_PA3 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3 */ +#define HAL_BIND_WLCSP12_PINF1_PA4 LL_PINMUX_WLCSP12_PINF1_PA4 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */ +#define HAL_BIND_WLCSP12_PINF1_PA5 LL_PINMUX_WLCSP12_PINF1_PA5 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */ +#define HAL_BIND_WLCSP12_PINF1_PA6 LL_PINMUX_WLCSP12_PINF1_PA6 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */ +#elif (DEV_ID == 0x453UL) +#define HAL_BIND_WLCSP14_PINF2_PA1 LL_PINMUX_WLCSP14_PINF2_PA1 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */ +#define HAL_BIND_WLCSP14_PINF2_PA2 LL_PINMUX_WLCSP14_PINF2_PA2 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */ +#define HAL_BIND_WLCSP14_PING3_PF2 LL_PINMUX_WLCSP14_PING3_PF2 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */ +#define HAL_BIND_WLCSP14_PING3_PA0 LL_PINMUX_WLCSP14_PING3_PA0 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */ +#define HAL_BIND_WLCSP14_PINJ1_PA8 LL_PINMUX_WLCSP14_PINJ1_PA8 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */ +#define HAL_BIND_WLCSP14_PINJ1_PA11 LL_PINMUX_WLCSP14_PINJ1_PA11 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */ +#define HAL_BIND_WLCSP14_PINH2_PA5 LL_PINMUX_WLCSP14_PINH2_PA5 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */ +#define HAL_BIND_WLCSP14_PINH2_PA6 LL_PINMUX_WLCSP14_PINH2_PA6 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */ +#define HAL_BIND_WLCSP14_PING1_PA7 LL_PINMUX_WLCSP14_PING1_PA7 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */ +#define HAL_BIND_WLCSP14_PING1_PA12 LL_PINMUX_WLCSP14_PING1_PA12 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */ +#define HAL_BIND_WLCSP14_PINJ3_PA3 LL_PINMUX_WLCSP14_PINJ3_PA3 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */ +#define HAL_BIND_WLCSP14_PINJ3_PA4 LL_PINMUX_WLCSP14_PINJ3_PA4 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */ +#elif (DEV_ID == 0x493UL) +#define HAL_BIND_WLCSP19_PINH3_PF2 LL_PINMUX_WLCSP19_PINH3_PF2 /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PF2 */ +#define HAL_BIND_WLCSP19_PINH3_PA0 LL_PINMUX_WLCSP19_PINH3_PA0 /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PA0 */ +#define HAL_BIND_WLCSP19_PINB1_PA14 LL_PINMUX_WLCSP19_PINB1_PA14 /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA14 */ +#define HAL_BIND_WLCSP19_PINB1_PA15 LL_PINMUX_WLCSP19_PINB1_PA15 /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA15 */ +#define HAL_BIND_TSSOP20_PIN19_PA14 LL_PINMUX_TSSOP20_PIN19_PA14 +#define HAL_BIND_TSSOP20_PIN19_PA15 LL_PINMUX_TSSOP20_PIN19_PA15 +#define HAL_BIND_TSSOP20_PIN20_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB6 */ +#define HAL_BIND_TSSOP20_PIN20_PB3 LL_PINMUX_TSSOP20_PIN20_PB3 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB3 */ +#define HAL_BIND_TSSOP20_PIN20_PB4 LL_PINMUX_TSSOP20_PIN20_PB4 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB4 */ +#define HAL_BIND_TSSOP20_PIN20_PB5 LL_PINMUX_TSSOP20_PIN20_PB5 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB5 */ +#define HAL_BIND_WLCSP19_PINB3_PB LL_PINMUX_WLCSP19_PINB3_PB7 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB7 */ +#define HAL_BIND_WLCSP19_PINB3_PB8 LL_PINMUX_WLCSP19_PINB3_PB8 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */ +#define HAL_BIND_TSSOP20_PIN1_PB7 LL_PINMUX_TSSOP20_PIN1_PB7 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB7 */ +#define HAL_BIND_TSSOP20_PIN1_PB8 LL_PINMUX_TSSOP20_PIN1_PB8 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB8 */ +#elif (DEV_ID == 0x44CUL) +#define HAL_BIND_WLCSP15_PINH3_PF2 LL_PINMUX_WLCSP15_PINH3_PF2 /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PF2 */ +#define HAL_BIND_WLCSP15_PINH3_PA0 LL_PINMUX_WLCSP15_PINH3_PA0 /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PA0 */ +#define HAL_BIND_WLCSP15_PING2_PA1 LL_PINMUX_WLCSP15_PING2_PA1 /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA1 */ +#define HAL_BIND_WLCSP15_PING2_PA2 LL_PINMUX_WLCSP15_PING2_PA2 /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA2 */ +#define HAL_BIND_WLCSP15_PINK3_PA3 LL_PINMUX_WLCSP15_PINK3_PA3 /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA3 */ +#define HAL_BIND_WLCSP15_PINK3_PA4 LL_PINMUX_WLCSP15_PINK3_PA4 /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA4 */ +#define HAL_BIND_WLCSP15_PINJ2_PA5 LL_PINMUX_WLCSP15_PINJ2_PA5 /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA5 */ +#define HAL_BIND_WLCSP15_PINJ2_PA6 LL_PINMUX_WLCSP15_PINJ2_PA6 /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA6 */ +#define HAL_BIND_WLCSP15_PINH1_PA7 LL_PINMUX_WLCSP15_PINH1_PA7 /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA7 */ +#define HAL_BIND_WLCSP15_PINH1_PA12 LL_PINMUX_WLCSP15_PINH1_PA12 /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA12 */ +#define HAL_BIND_WLCSP15_PINE2_PA14 LL_PINMUX_WLCSP15_PINE2_PA14 /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA14 */ +#define HAL_BIND_WLCSP15_PINE2_PA15 LL_PINMUX_WLCSP15_PINE2_PA15 /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA15 */ +#define HAL_BIND_WLCSP15_PINB1_PA3 LL_PINMUX_WLCSP15_PINB1_PA3 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA3 */ +#define HAL_BIND_WLCSP15_PINB1_PA4 LL_PINMUX_WLCSP15_PINB1_PA4 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA4 */ +#define HAL_BIND_WLCSP15_PINB1_PA5 LL_PINMUX_WLCSP15_PINB1_PA5 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA5 */ +#define HAL_BIND_WLCSP15_PINB1_PA6 LL_PINMUX_WLCSP15_PINB1_PA6 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA6 */ +#define HAL_BIND_WLCSP15_PINA2_PB7 LL_PINMUX_WLCSP15_PINA2_PB7 /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB7 */ +#define HAL_BIND_WLCSP15_PINA2_PB8 LL_PINMUX_WLCSP15_PINA2_PB8 /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB8 */ +#elif (DEV_ID == 0x44DUL) +#define HAL_BIND_TSSOP20_PIN19_PA14 LL_PINMUX_TSSOP20_PIN19_PA14 /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA14 */ +#define HAL_BIND_TSSOP20_PIN19_PA15 LL_PINMUX_TSSOP20_PIN19_PA15 /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA15 */ +#define HAL_BIND_TSSOP20_PIN15_PA8 LL_PINMUX_TSSOP20_PIN15_PA8 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PA8 */ +#define HAL_BIND_TSSOP20_PIN15_PB0 LL_PINMUX_TSSOP20_PIN15_PB0 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB0 */ +#define HAL_BIND_TSSOP20_PIN15_PB1 LL_PINMUX_TSSOP20_PIN15_PB1 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB1 */ +#define HAL_BIND_TSSOP20_PIN15_PB2 LL_PINMUX_TSSOP20_PIN15_PB2 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB2 */ +#define HAL_BIND_TSSOP20_PIN20_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB6 */ +#define HAL_BIND_TSSOP20_PIN20_PB3 LL_PINMUX_TSSOP20_PIN20_PB3 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB3 */ +#define HAL_BIND_TSSOP20_PIN20_PB4 LL_PINMUX_TSSOP20_PIN20_PB4 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB4 */ +#define HAL_BIND_TSSOP20_PIN20_PB5 LL_PINMUX_TSSOP20_PIN20_PB5 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB5 */ +#define HAL_BIND_WLCSP24_PINA3_PB5 LL_PINMUX_WLCSP24_PINA3_PB5 /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB5 */ +#define HAL_BIND_WLCSP24_PINA3_PB3 LL_PINMUX_WLCSP24_PINA3_PB3 /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB3 */ +#define HAL_BIND_WLCSP24_PINB4_PB7 LL_PINMUX_WLCSP24_PINB4_PB7 /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB7 */ +#define HAL_BIND_WLCSP24_PINB4_PB8 LL_PINMUX_WLCSP24_PINB4_PB8 /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB8 */ +#endif /* DEV_ID == 0x443UL */ + +/** + * @} + */ + +/** @defgroup HAL_BIND_SCOURCE Bind Pin Source + * @{ + */ +#if (DEV_ID == 0x443UL) +#define HAL_BIND_SO8_PIN1 LL_PINMUX_SO8_PIN1 /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */ +#define HAL_BIND_SO8_PIN4 LL_PINMUX_SO8_PIN4 /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */ +#define HAL_BIND_SO8_PIN5 LL_PINMUX_SO8_PIN5 /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */ +#define HAL_BIND_SO8_PIN8 LL_PINMUX_SO8_PIN8 /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */ +#define HAL_BIND_WLCSP12_PINE2 LL_PINMUX_WLCSP12_PINE2 /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */ +#define HAL_BIND_WLCSP12_PINF1 LL_PINMUX_WLCSP12_PINF1 /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer */ +#elif (DEV_ID == 0x453UL) +#define HAL_BIND_WLCSP14_PINF2 LL_PINMUX_WLCSP14_PINF2 /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */ +#define HAL_BIND_WLCSP14_PING3 LL_PINMUX_WLCSP14_PING3 /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */ +#define HAL_BIND_WLCSP14_PINJ1 LL_PINMUX_WLCSP14_PINJ1 /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */ +#define HAL_BIND_WLCSP14_PINH2 LL_PINMUX_WLCSP14_PINH2 /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */ +#define HAL_BIND_WLCSP14_PING1 LL_PINMUX_WLCSP14_PING1 /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */ +#define HAL_BIND_WLCSP14_PINJ3 LL_PINMUX_WLCSP14_PINJ3 /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */ +#elif (DEV_ID == 0x493UL) +#define HAL_BIND_WLCSP19_PINH3 LL_PINMUX_WLCSP19_PINH3 /*!< STM32C071 WLCSP19 package, GPIO PinH3 multiplexer */ +#define HAL_BIND_WLCSP19_PINB1 LL_PINMUX_WLCSP19_PINB1 /*!< STM32C071 WLCSP19 package, GPIO PinB1 multiplexer */ +#define HAL_BIND_TSSOP20_PIN19 LL_PINMUX_TSSOP20_PIN19 /*!< STM32C071 TSSOP20 package, GPIO Pin19 multiplexer */ +#define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */ +#define HAL_BIND_WLCSP19_PINB3 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */ +#define HAL_BIND_TSSOP20_PIN1 LL_PINMUX_TSSOP20_PIN1 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */ +#elif (DEV_ID == 0x44CUL) +#define HAL_BIND_WLCSP15_PINH3 LL_PINMUX_WLCSP15_PINH3 /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */ +#define HAL_BIND_WLCSP15_PING2 LL_PINMUX_WLCSP15_PING2 /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */ +#define HAL_BIND_WLCSP15_PINK3 LL_PINMUX_WLCSP15_PINK3 /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */ +#define HAL_BIND_WLCSP15_PINJ2 LL_PINMUX_WLCSP15_PINJ2 /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */ +#define HAL_BIND_WLCSP15_PINH1 LL_PINMUX_WLCSP15_PINH1 /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */ +#define HAL_BIND_WLCSP15_PINE2 LL_PINMUX_WLCSP15_PINE2 /*!< STM32C051 WLCSP15 package, GPIO PinE2 multiplexer */ +#define HAL_BIND_WLCSP15_PINB1 LL_PINMUX_WLCSP15_PINB1 /*!< STM32C051 WLCSP15 package, GPIO PinB1 multiplexer */ +#define HAL_BIND_WLCSP15_PINA2 LL_PINMUX_WLCSP15_PINA2 /*!< STM32C051 WLCSP15 package, GPIO PinA2 multiplexer */ +#elif (DEV_ID == 0x44DUL) +#define HAL_BIND_TSSOP20_PIN19 LL_PINMUX_TSSOP20_PIN19 /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */ +#define HAL_BIND_TSSOP20_PIN15 LL_PINMUX_TSSOP20_PIN15 /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */ +#define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */ +#define HAL_BIND_WLCSP24_PINA3 LL_PINMUX_WLCSP24_PINA3 /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */ +#define HAL_BIND_WLCSP24_PINB4 LL_PINMUX_WLCSP24_PINB4 /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */ +#endif /* DEV_ID == 0x443UL */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ +#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ +#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Break Break + * @{ + */ +#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** @defgroup HAL_Pin_remapping Pin remapping + * @{ + */ +#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ +#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ +/** + * @} + */ + +/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ + +/** + * @} + */ + +/** @defgroup HAL_IR_POL_SEL IR output polarity selection + * @{ + */ +#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */ +#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */ + +/** + * @} + */ +/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO + * @{ + */ + +/** @brief Fast mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ +#define SYSCFG_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast mode Plus on PC14 */ +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx + * @{ + */ + +/** @brief Fast mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */ +#if defined(I2C2) +#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */ +#endif /* I2C2 */ +/** + * @} + */ + +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @brief ISR Wrapper + * @{ + */ +#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ +#if defined(USB_DRD_FS) +#define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ +#endif /* USB */ +#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ +#if defined(TIM2) +#define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */ +#endif /* TIM2 */ +#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ +#if defined(TIM15) +#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */ +#endif /* TIM15 */ +#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ +#if defined(I2C2) +#define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */ +#endif /* I2C2 */ +#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ +#if defined(SPI2) +#define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */ +#endif /* SPI2 */ +#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ +#if defined(USART3) +#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */ +#endif /* USART3 */ +#if defined(FDCAN1) +#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */ +#endif /* FDCAN1 */ + +#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG Interrupt */ +#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC Interrupt */ +#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */ +#if defined(CRS) +#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */ +#endif /* CRS */ +#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ +#if defined(USB_DRD_FS) +#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */ +#endif /* USB */ +#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMAMUX ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX) /*!< DMAMUX Interrupt */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */ +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */ +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */ +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ +#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ +#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */ +#if defined(TIM2) +#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2) /*!< TIM2 Interrupt */ +#endif /* TIM2 */ +#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ +#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ +#if defined(TIM15) +#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */ +#endif /* TIM15 */ +#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ +#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ +#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt */ +#if defined(I2C2) +#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C1 Interrupt */ +#endif /* I2C2 */ +#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ +#if defined(SPI2) +#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE25_SR_SPI2) /*!< SPI1 Interrupt */ +#endif /* SPI2 */ +#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt */ +#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt */ +#if defined(USART3) +#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 GLB Interrupt */ +#endif /* USART3 */ +#if defined(USART4) +#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 GLB Interrupt */ +#endif /* USART4 */ +#if defined(FDCAN1) +#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_FDCAN1_IT0_GLB) /*!< FDCAN1_IT0 GLB Interrupt */ +#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_FDCAN1_IT1_GLB) /*!< FDCAN1_IT1 GLB Interrupt */ +#endif /* FDCAN1 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + +/** @brief Freeze and Unfreeze Peripherals in Debug mode + */ + +#if defined(DBG_APB_FZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */ + +#if defined(DBG_APB_FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) +#endif /* DBG_APB_FZ1_DBG_RTC_STOP */ + +#if defined(DBG_APB_FZ1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) +#endif /* DBG_APB_FZ1_DBG_RTC_STOP */ + +#if defined(DBG_APB_FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) +#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */ + +#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** + * @brief ISR wrapper check + * @note Allow to determine interrupt source per line. + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)) + +/** + * @brief Return the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values @ref SYSCFG_BootMode + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) + +/** @brief SYSCFG Break Cortex-M0+ Lockup lock. + * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/16/17 Break input + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ + do { \ + assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0U) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ + do { \ + assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0U) + + +/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register + * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ + SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ + }while(0U) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) + +/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register + * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL + */ +#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ + SET_BIT(SYSCFG->CFGR1,(__SEL__));\ + }while(0U) + +/** + * @brief Return the IROut Polarity mode as configured by user. + * @retval The IROut polarity as configured by user. The returned value can be one + * of @ref HAL_IR_POL_SEL + */ +#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) + +/** @brief Break input to TIM1/16/17 capability enable/disable macros + * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break + */ +#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ + SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ + }while(0U) + +#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ + CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ + }while(0U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ + +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) ((__CONFIG__) == SYSCFG_BREAK_LOCKUP) + +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) + +#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ + ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) + + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PC14) == SYSCFG_FASTMODEPLUS_PC14) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ + ((RMP) == SYSCFG_REMAP_PA12) || \ + ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) +#if (DEV_ID == 0x443UL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_SO8_PIN1_PB7) || \ + ((PIN) == HAL_BIND_SO8_PIN1_PC14) || \ + ((PIN) == HAL_BIND_SO8_PIN4_PF2) || \ + ((PIN) == HAL_BIND_SO8_PIN4_PA0) || \ + ((PIN) == HAL_BIND_SO8_PIN4_PA1) || \ + ((PIN) == HAL_BIND_SO8_PIN4_PA2) || \ + ((PIN) == HAL_BIND_SO8_PIN5_PA8) || \ + ((PIN) == HAL_BIND_SO8_PIN5_PA11) || \ + ((PIN) == HAL_BIND_SO8_PIN8_PA14) || \ + ((PIN) == HAL_BIND_SO8_PIN8_PB6) || \ + ((PIN) == HAL_BIND_SO8_PIN8_PC15) || \ + ((PIN) == HAL_BIND_WLCSP12_PINE2_PA7) || \ + ((PIN) == HAL_BIND_WLCSP12_PINE2_PA12) || \ + ((PIN) == HAL_BIND_WLCSP12_PINF1_PA3) || \ + ((PIN) == HAL_BIND_WLCSP12_PINF1_PA4) || \ + ((PIN) == HAL_BIND_WLCSP12_PINF1_PA5) || \ + ((PIN) == HAL_BIND_WLCSP12_PINF1_PA6)) +#elif (DEV_ID == 0x453UL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_WLCSP14_PINF2_PA1) || \ + ((PIN) == HAL_BIND_WLCSP14_PINF2_PA2) || \ + ((PIN) == HAL_BIND_WLCSP14_PING3_PF2) || \ + ((PIN) == HAL_BIND_WLCSP14_PING3_PA0) || \ + ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA8) || \ + ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA11) || \ + ((PIN) == HAL_BIND_WLCSP14_PINH2_PA5) || \ + ((PIN) == HAL_BIND_WLCSP14_PINH2_PA6) || \ + ((PIN) == HAL_BIND_WLCSP14_PING1_PA7) || \ + ((PIN) == HAL_BIND_WLCSP14_PING1_PA12)|| \ + ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA3) || \ + ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA4)) +#elif (DEV_ID == 0x493UL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_WLCSP19_PINH3_PF2) || \ + ((PIN) == LL_PINMUX_WLCSP19_PINH3_PA0) || \ + ((PIN) == LL_PINMUX_WLCSP19_PINB1_PA14) || \ + ((PIN) == LL_PINMUX_WLCSP19_PINB1_PA15) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB6) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB3) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB4) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \ + ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB7) || \ + ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB8)) +#elif (DEV_ID == 0x44CUL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_WLCSP15_PINH3_PF2) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINH3_PA0) || \ + ((PIN) == LL_PINMUX_WLCSP15_PING2_PA1) || \ + ((PIN) == LL_PINMUX_WLCSP15_PING2_PA2) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINK3_PA3) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINK3_PA4) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINJ2_PA5) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINJ2_PA6) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINH1_PA7) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINH1_PA12) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINE2_PA14) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINE2_PA15) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA3) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA4) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA5) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA6) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINA2_PB7) || \ + ((PIN) == LL_PINMUX_WLCSP15_PINA2_PB8)) +#elif (DEV_ID == 0x44DUL) +#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_TSSOP20_PIN19_PA14) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN19_PA15) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PA8) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB0) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB1) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB2) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB6) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB3) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB4) || \ + ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINA3_PB5) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINA3_PB3) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINB4_PB7) || \ + ((PIN) == LL_PINMUX_WLCSP24_PINB4_PB8)) +#endif /* DEV_ID == 0x443UL | DEV_ID == 0x453UL | DEV_ID == 0x493UL | DEV_ID == 0x44CUL | DEV_ID == 0x44DUL */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions + * @{ + */ + +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ +void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); +void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); +void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding); +uint32_t HAL_SYSCFG_GetPinBinding(uint32_t pin_binding_source); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h (revision 41) @@ -0,0 +1,1934 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_ADC_H +#define STM32C0xx_HAL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/* Include low level driver */ +#include "stm32c0xx_ll_adc.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ + +} ADC_OversamplingTypeDef; + +/** + * @brief Structure definition of ADC instance and ADC group regular. + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC + * groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * ScanConvMode, EOCSelection, LowPowerAutoWait. + * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, + * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. + * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on + * group regular. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous + clock derived from system clock or PLL (Refer to reference manual for list of + clocks available)) and clock prescaler. + This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. + Note: The ADC clock configuration is common to all ADC instances. + Note: In case of synchronous clock mode based on HCLK/1, the configuration must + be enabled only if the system clock has a 50% duty clock cycle (APB + prescaler configured inside RCC must be bypassed and PCLK clock must have + 50% duty cycle). Refer to reference manual for details. + Note: In case of usage of asynchronous clock, the selected clock must be + preliminarily enabled at RCC top level. + Note: This parameter can be modified only if all ADC instances are disabled. */ + + uint32_t Resolution; /*!< Configure the ADC resolution. + This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ + + uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). + Refer to reference manual for alignments formats versus resolutions. + This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ + + uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. + On this STM32 series, ADC group regular sequencer both modes "fully configurable" + or "not fully configurable" are available: + - sequencer configured to fully configurable: + sequencer length and each rank affectation to a channel are configurable. + - Sequence length: Set number of ranks in the scan sequence. + - Sequence direction: Unless specified in parameters, sequencer + scan direction is forward (from rank 1 to rank n). + - sequencer configured to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by channel + HW number. + - Sequence length: Number of ranks in the scan sequence is + defined by number of channels set in the sequence, + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + - Sequence direction: Unless specified in parameters, sequencer + scan direction is forward (from lowest channel number to + highest channel number). + This parameter can be associated to parameter 'DiscontinuousConvMode' to have + main sequence subdivided in successive parts. Sequencer is automatically enabled + if several channels are set (sequencer cannot be disabled, as it can be the case + on other STM32 devices): + If only 1 channel is set: Conversion is performed in single mode. + If several channels are set: Conversions are performed in sequence mode. + This parameter can be a value of @ref ADC_Scan_mode */ + + uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and + interruption: end of unitary conversion or end of sequence conversions. + This parameter can be a value of @ref ADC_EOCSelection. */ + + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the + previous conversion (for ADC group regular) has been retrieved by user software, + using function HAL_ADC_GetValue(). + This feature automatically adapts the frequency of ADC conversions triggers to + the speed of the system that reads the data. Moreover, this avoids risk of + overrun for low frequency applications. + This parameter can be set to ENABLE or DISABLE. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), + HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC + flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended + benefit (except specific case of high load of CPU or DMA transfers which + can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, + when ADC conversion data is needed: + use HAL_ADC_PollForConversion() to ensure that conversion is completed and + HAL_ADC_GetValue() to retrieve conversion result and trig another + conversion start. */ + + FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a + conversion and automatically wakes-up when a new conversion is triggered + (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode + (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) + or continuous mode for ADC group regular, after the first ADC conversion + start trigger occurred (software start or external trigger). This parameter + can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group + sequencer. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Number of ranks in the scan sequence is configurable using this parameter. + Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to + parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. + Afterwards, when all needed sequencer ranks are set, parameter + 'NbrOfConversion' can be updated without modifying configuration of + sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). + - sequencer configured to not fully configurable: + Number of ranks in the scan sequence is defined by number of channels set in + the sequence. This parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. + Note: This parameter must be modified when no conversion is on going on regular + group (ADC disabled, or ADC enabled without continuous mode or external + trigger that could launch a conversion). */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed + in Complete-sequence/Discontinuous-sequence (main sequence subdivided in + successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: On this STM32 series, ADC group regular number of discontinuous + ranks increment is fixed to one-by-one. */ + + uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion + start. + If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger + is used instead. + This parameter can be a value of @ref ADC_regular_external_trigger_source. + Caution: external trigger source is common to all ADC instances. */ + + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start + If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_regular_external_trigger_edge */ + + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA + transfer stops when number of conversions is reached) or in continuous + mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ENABLE or DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. + Otherwise an overrun will be triggered when DMA buffer maximum + pointer is reached. */ + + uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). + This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. + Note: In case of overrun set to data preserved and usage with programming model + with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of + conversion flags, this induces the release of the preserved data. If + needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), + placed in user program code (called before end of conversion flags clear) + Note: Error reporting with respect to the conversion mode: + - Usage with ADC conversion by polling for event or interruption: Error is + reported only if overrun is set to data preserved. If overrun is set to + data overwritten, user can willingly not read all the converted data, + this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun + setting (DMA is expected to process all data from data register). */ + + uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, + each channel can use one of these two settings. On some other STM32 devices + this parameter in channel wise and is located into ADC channel + initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, + TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, + each channel can use one of these two settings. On some other STM32 devices + this parameter in channel wise and is located into ADC channel + initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, + TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is + ongoing on ADC group regular. */ + + ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration + if oversampling is already enabled. */ + + uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. + This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. + Note: ADC trigger frequency mode must be set to low frequency when + a duration is exceeded before ADC conversion start trigger event + (between ADC enable and ADC conversion start trigger event + or between two ADC conversion start trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". + Note: When ADC trigger frequency mode is set to low frequency, + some rearm cycles are inserted before performing ADC conversion + start, inducing a delay of 2 ADC clock cycles. */ + +} ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled or enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL + Note: Depending on devices and ADC instances, some channels may not be available + on device package pins. Refer to device datasheet for channels + availability. */ + + uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its + conversion rank. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Channels ordering into each rank of scan sequence: + whatever channel can be placed into whatever rank. + - sequencer configured to not fully configurable: + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Despite the channel rank is fixed, this parameter allow an additional + possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ + + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON + Note: On this STM32 family, two different sampling time settings are available + (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), + each channel can use one of these two settings. + + Note: In case of usage of internal measurement channels (VrefInt/Vbat/ + TempSensor), sampling time constraints must be respected (sampling time + can be adjusted in function of ADC clock frequency and sampling time + setting) + Refer to device datasheet for timings values. */ + +} ADC_ChannelConfTypeDef; + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion + on going on ADC groups regular. + * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. + */ +typedef struct +{ + uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels + by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls + of 'HAL_ADC_AnalogWDGConfig()' for each channel) + This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ + + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all + channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying + successively the AWD init structure. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' + is configured on single channel (only 1 channel can be + monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, + call successively the function HAL_ADC_AnalogWDGConfig() + for each channel to be added (or removed with value + 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ + + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits).*/ +} ADC_AnalogWDGConfTypeDef; + +/** @defgroup ADC_States ADC States + * @{ + */ + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + * @note ADC state machine is managed by bitfields, state must be compared + * with bit by bit. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur + (either by continuous mode, external trigger, low power + auto power-on (if feature available), multimode ADC master + control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag + raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group + injected is ongoing or can occur (either by auto-injection + mode, external trigger, low power auto power-on (if feature + available), multimode ADC master control (if feature + available))*/ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data + available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow + occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Not available on this STM32 series: Out-of-window occurrence + of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Not available on this STM32 series: Out-of-window occurrence + of ADC analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave + state, controlled by another ADC master (when feature + available) */ + + +/** + * @} + */ + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +{ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + HAL_LockTypeDef Lock; /*!< ADC locking object */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks + setting, used in mode "fully configurable" (refer to + parameter 'ScanConvMode') */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer + callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ + void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ + void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of calibration callback */ + void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Ready callback */ + void (* ChannelConfigReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Channel Configuration Ready + callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ + HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock + without prescaler. This configuration must be enabled only if PCLK has + a 50% duty clock cycle (APB prescaler configured inside the RCC must + be bypassed and the system clock must by 50% duty cycle) */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock + with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock + with prescaler division by 4 */ + +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without + prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler + division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler + division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler + division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler + division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler + division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler + division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler + division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler + division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler + division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler + division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler + division by 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment + * @{ + */ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +/* Note: On this STM32 family, ADC group regular sequencer both modes */ +/* "fully configurable" or "not fully configurable" are */ +/* available. */ +/* Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE (0x00000000UL) */ +/* ADC_SCAN_ENABLE (0x00000001UL) */ +/* Sequencer fully configurable with only rank 1 enabled is considered */ +/* as default setting equivalent to scan enable. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +/* Sequencer set to fully configurable */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: + only the rank 1 is enabled (no scan sequence on several ranks) */ +#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: + sequencer length and each rank affectation to a channel are configurable. */ + +/* Sequencer set to not fully configurable */ +#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ + | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ +#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source + * @{ + */ +/* ADC group regular trigger sources for all ADC instances */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion + trigger internal: SW start. */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 4 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#if defined(TIM2) +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ +#endif /* TIM2 */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 TRGO. + Trigger edge set to rising edge (default setting). */ +#if defined(TIM4) +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 TRGO. + Trigger edge set to rising edge (default setting). */ +#endif /* TIM4 */ +#if defined(TIM6) +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM6 TRGO. + Trigger edge set to rising edge (default setting). */ +#endif /* TIM6 */ +#if defined(TIM15) +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM15 TRGO. + Trigger edge set to rising edge (default setting). */ +#endif /* TIM15 */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 11. + Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware + trigger detection disabled */ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions + * @{ + */ +#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ +#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case + of overrun: data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set + to sequencer not fully configurable: Enable the rank of the selected + channels. Number of ranks in the sequence is defined by number of channels + enabled, rank of each channel is defined by channel number + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" + is set to sequencer not fully configurable: Disable the selected rank + (selected channel) from sequencer */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels + * @{ + */ +#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of + channels: sampling time nb 1 */ +#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of + channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ +#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< External channel (GPIO pin) ADCx_IN19 */ +#define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< External channel (GPIO pin) ADCx_IN20 */ +#define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< External channel (GPIO pin) ADCx_IN21 */ +#define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< External channel (GPIO pin) ADCx_IN22 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: + Internal voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ +#define ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_VDDA) /*!< Internal channel VDDA */ +#define ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_VSSA) /*!< Internal channel VSSA */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ +#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular + group single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular + group all channels */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +/** + * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed + * to result as the ADC oversampling conversion data (before potential shift) + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +/** + * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling + * conversion data) + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: + discontinuous mode (each conversion of OVS ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ + +/** + * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion + * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion + * start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + */ +#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ +#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +/** + * @note Analog watchdog 1 is available on all stm32 series + * Analog watchdog 2 and 3 are not available on all series + */ +#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ +#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +/** + * @} + */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility + with other STM32 devices having only one analog watchdog */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog + watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog + watchdog) */ +#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ +#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC End of Calibration interrupt flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) + +/** + * @brief Return resolution bits in CFGR1 register RES[1:0] field. + * @param __HANDLE__ ADC handle + * @retval Value of bitfield RES in CFGR1 register. + */ +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (LL_ADC_GetResolution((__HANDLE__)->Instance)) + +/** + * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +/** + * @brief Simultaneously clear and set specific bits of the handle State. + * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Enable ADC discontinuous conversion mode for regular group + * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. + * @retval None + */ +#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ + ((_REG_DISCONTINUOUS_MODE_) << 16U) + +/** + * @brief Enable the ADC auto off mode. + * @param _AUTOOFF_ Auto off bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ + ((_AUTOOFF_) << 15U) + +/** + * @brief Enable the ADC auto delay mode. + * @param _AUTOWAIT_ Auto delay bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ + ((_AUTOWAIT_) << 14U) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << 13U) + +/** + * @brief Enable ADC overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. + * @retval Overrun bit setting to be programmed into CFGR register + */ +/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* as the default case to be compliant with other STM32 devices. */ +#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ + )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ + ) + +/** + * @brief Set ADC scan mode with differentiation of sequencer setting + * fixed or configurable + * @param _SCAN_MODE_ Scan conversion mode. + * @retval None + */ +/* Note: Scan mode set using this macro (instead of parameter direct set) */ +/* due to different modes on other STM32 devices: */ +/* if scan mode is disabled, sequencer is set to fully configurable */ +/* with setting of only rank 1 enabled afterwards. */ +#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ + ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ + )? \ + ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ + : \ + (ADC_CFGR1_CHSELRMOD) \ + ) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @retval None + */ +#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ + ((_DMACONTREQ_MODE_) << 1U) + +/** + * @brief Shift the AWD threshold in function of the selected ADC resolution. + * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) + * @param __HANDLE__ ADC handle + * @param _Threshold_ Value to be shifted + * @retval None + */ +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ + ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ + ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ + ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +#if defined(TIM2) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#else +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif /* TIM2 */ + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) + +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ + ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) + +#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ + ((RANK) == ADC_RANK_NONE) ) + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ + ((RANK) == ADC_REGULAR_RANK_2 ) || \ + ((RANK) == ADC_REGULAR_RANK_3 ) || \ + ((RANK) == ADC_REGULAR_RANK_4 ) || \ + ((RANK) == ADC_REGULAR_RANK_5 ) || \ + ((RANK) == ADC_REGULAR_RANK_6 ) || \ + ((RANK) == ADC_REGULAR_RANK_7 ) || \ + ((RANK) == ADC_REGULAR_RANK_8 ) ) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) == ADC_CHANNEL_20) || \ + ((CHANNEL) == ADC_CHANNEL_21) || \ + ((CHANNEL) == ADC_CHANNEL_22) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC_CHANNEL_VDDA) || \ + ((CHANNEL) == ADC_CHANNEL_VSSA) ) + +#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ + ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_160CYCLES_5) ) + +#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) + +#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ + ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ + ((EVENT) == ADC_AWD1_EVENT) || \ + ((EVENT) == ADC_AWD2_EVENT) || \ + ((EVENT) == ADC_AWD3_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT) ) + +/** + * @brief Verify that a given value is aligned with the ADC resolution range. + * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_VALUE__ value checked against the resolution. + * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) + */ +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) + +/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification + * @{ + */ +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) + +/* Internal definition to differentiate sequencer setting fixed or configurable */ +#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. + * @{ + */ + +/** @brief Reset ADC handle state. + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @brief Enable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the specified ADC flag is set or not. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @retval State of flag (TRUE or FALSE). + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified ADC flag. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @} + */ + +/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals ADC_CHANNEL_x. + * @note Example: + * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + +/** + * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + */ +#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * ADC_CHANNEL_1, ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Value "0" if the channel corresponds to a parameter definition of a + * ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of + * a ADC internal channel. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_19 + * @arg @ref ADC_CHANNEL_20 + * @arg @ref ADC_CHANNEL_21 + * @arg @ref ADC_CHANNEL_22 + */ +#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VDDA + * @arg @ref ADC_CHANNEL_VSSA + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ + __LL_ADC_COMMON_INSTANCE((__ADCx__)) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value + */ +#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used + * to improve calculation accuracy. + * Refer to @ref TEMPSENSOR_CAL1_ADDR. + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + * (unit: uV/DegCelsius). + * On this STM32 series, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + * temperature and Vref+ defined in parameters below) (unit: mV). + * On this STM32 series, refer to device datasheet parameter "V30" + * (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see + * parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include ADC HAL Extended module */ +#include "stm32c0xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); + +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32C0xx_HAL_ADC_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h (revision 41) @@ -0,0 +1,185 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_ADC_EX_H +#define STM32C0xx_HAL_ADC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants + * @{ + */ + +/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Check whether or not ADC is independent. + * @param __HANDLE__ ADC handle. + * @note When multimode feature is not available, the macro always returns SET. + * @retval SET (ADC is independent) or RESET (ADC is not). + */ +#define ADC_IS_INDEPENDENT(__HANDLE__) (SET) + + +/** + * @brief Calibration factor size verification (7 bits maximum). + * @param __CALIBRATION_FACTOR__ Calibration factor value. + * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) + */ +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) + +/** + * @brief Verify the ADC oversampling ratio. + * @param __RATIO__ programmed ADC oversampling ratio. + * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) + */ +#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) + +/** + * @brief Verify the ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. + * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) + */ +#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) + +/** + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** @addtogroup ADCEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_ADC_EX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h (revision 41) @@ -0,0 +1,401 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_CORTEX_H +#define STM32C0xx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. + */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) +#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#if defined(STM32C091xx) || defined(STM32C092xx) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB)) +#elif defined(STM32C071xx) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB)) +#elif defined(STM32C051xx) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB)) +#else +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB)) +#endif /* STM32C071xx */ +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_CORTEX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h (revision 41) @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_DEF +#define STM32C0xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#ifndef UNUSED +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handles State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handles "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handles "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to align variable on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +/* GNU Compiler */ +#if defined (__GNUC__) +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4U))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +/* ARM Compiler */ +#if defined (__CC_ARM) +#define __ALIGN_BEGIN __align(4U) +/* IAR Compiler */ +#elif defined (__ICCARM__) +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif /* __CC_ARM */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __CC_ARM | __GNUC__ */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_DEF */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h (revision 41) @@ -0,0 +1,692 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_DMA_H +#define STM32C0xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified channel. + This parameter can be a value of @ref DMA_request */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ + +/** + * @} + */ + +/** @defgroup DMA_request DMA request + * @{ + */ +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ +#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ +#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ +#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ +#define DMA_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ +#define DMA_REQUEST_I2C1_RX 10U /*!< DMAMUX I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX 11U /*!< DMAMUX I2C1 TX request */ +#if defined(I2C2) +#define DMA_REQUEST_I2C2_RX 12U /*!< DMAMUX I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX 13U /*!< DMAMUX I2C2 TX request */ +#endif /* I2C2 */ +#define DMA_REQUEST_SPI1_RX 16U /*!< DMAMUX SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX 17U /*!< DMAMUX SPI1 TX request */ +#if defined(SPI2) +#define DMA_REQUEST_SPI2_RX 18U /*!< DMAMUX SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX 19U /*!< DMAMUX SPI2 TX request */ +#endif /* SPI2 */ +#define DMA_REQUEST_TIM1_CH1 20U /*!< DMAMUX TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 21U /*!< DMAMUX TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 22U /*!< DMAMUX TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 23U /*!< DMAMUX TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_TRIG_COM 24U /*!< DMAMUX TIM1 TRIG COM request */ +#define DMA_REQUEST_TIM1_UP 25U /*!< DMAMUX TIM1 UP request */ +#if defined(TIM2) +#define DMA_REQUEST_TIM2_CH1 26U /*!< DMAMUX TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 27U /*!< DMAMUX TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 28U /*!< DMAMUX TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 29U /*!< DMAMUX TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_TRIG 30U /*!< DMAMUX TIM2 TRIG request */ +#define DMA_REQUEST_TIM2_UP 31U /*!< DMAMUX TIM2 UP request */ +#endif /* TIM2 */ +#define DMA_REQUEST_TIM3_CH1 32U /*!< DMAMUX TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 33U /*!< DMAMUX TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 34U /*!< DMAMUX TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 35U /*!< DMAMUX TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_TRIG 36U /*!< DMAMUX TIM3 TRIG request */ +#define DMA_REQUEST_TIM3_UP 37U /*!< DMAMUX TIM3 UP request */ +#if defined(TIM15) +#define DMA_REQUEST_TIM15_CH1 40U /*!< DMAMUX TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_CH2 41U /*!< DMAMUX TIM15 CH2 request */ +#define DMA_REQUEST_TIM15_TRIG_COM 42U /*!< DMAMUX TIM15 TRIG COM request */ +#define DMA_REQUEST_TIM15_UP 43U /*!< DMAMUX TIM15 UP request */ +#endif /* TIM15 */ +#define DMA_REQUEST_TIM16_CH1 44U /*!< DMAMUX TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_TRIG_COM 45U /*!< DMAMUX TIM16 TRIG COM request */ +#define DMA_REQUEST_TIM16_UP 46U /*!< DMAMUX TIM16 UP request */ +#define DMA_REQUEST_TIM17_CH1 47U /*!< DMAMUX TIM17 CH2 request */ +#define DMA_REQUEST_TIM17_TRIG_COM 48U /*!< DMAMUX TIM17 TRIG COM request */ +#define DMA_REQUEST_TIM17_UP 49U /*!< DMAMUX TIM17 UP request */ +#define DMA_REQUEST_USART1_RX 50U /*!< DMAMUX USART1 RX request */ +#define DMA_REQUEST_USART1_TX 51U /*!< DMAMUX USART1 TX request */ +#define DMA_REQUEST_USART2_RX 52U /*!< DMAMUX USART2 RX request */ +#define DMA_REQUEST_USART2_TX 53U /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define DMA_REQUEST_USART3_RX 54U /*!< DMAMUX USART3 RX request */ +#define DMA_REQUEST_USART3_TX 55U /*!< DMAMUX USART3 TX request */ +#endif /* USART3 */ +#if defined(USART4) +#define DMA_REQUEST_USART4_RX 56U /*!< DMAMUX USART4 RX request */ +#define DMA_REQUEST_USART4_TX 57U /*!< DMAMUX USART4 TX request */ +#endif /* USART4 */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GI1 DMA_ISR_GIF1 +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 +#define DMA_FLAG_GI2 DMA_ISR_GIF2 +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 +#define DMA_FLAG_GI3 DMA_ISR_GIF3 +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 +#if defined(DMA1_Channel4) +#define DMA_FLAG_GI4 DMA_ISR_GIF4 +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 +#endif /* DMA1_Channel4 */ +#if defined(DMA1_Channel5) +#define DMA_FLAG_GI5 DMA_ISR_GIF5 +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 +#endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define DMA_FLAG_GI6 DMA_ISR_GIF6 +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define DMA_FLAG_GI7 DMA_ISR_GIF7 +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 +#endif /* DMA1_Channel7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#elif defined(DMA1_Channel5) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + DMA_FLAG_TC3) +#endif /* DMA1_Channel7 */ + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#elif defined(DMA1_Channel5) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + DMA_FLAG_HT3) +#endif /* DMA1_Channel7 */ + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#elif defined(DMA1_Channel5) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + DMA_FLAG_TE3) +#endif /* DMA1_Channel7 */ + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) +#elif defined(DMA1_Channel5) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + DMA_FLAG_GI5) +#else +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + DMA_FLAG_GI3) +#endif /* DMA1_Channel7 */ + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * @arg DMA_FLAG_GIFx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * @arg DMA_FLAG_GIFx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__ DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32c0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, + void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) +#if defined(USART4) +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART4_TX) +#else +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX) +#endif /* USART4 */ + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_DMA_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h (revision 41) @@ -0,0 +1,264 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_DMA_EX_H +#define STM32C0xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMA Synchro definition + */ + + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +} HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +} HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ +#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ +#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ +#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ +#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ +#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ +#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ +#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ +#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ +#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ +#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ +#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ +#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ +#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ +#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ +#if defined(DMAMUX1_Channel3) +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ +#endif /* DMAMUX1_Channel3 */ +#define HAL_DMAMUX1_SYNC_TIM14_OC 22U /*!< Synchronization Signal is TIM14 OC */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ +#if defined(DMAMUX1_Channel3) +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ +#endif /* DMAMUX1_Channel3 */ +#define HAL_DMAMUX1_REQ_GEN_TIM14_OC 22U /*!< Request generator Signal is TIM14 OC */ +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef \ + *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM14_OC) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM14_OC) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_DMA_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h (revision 41) @@ -0,0 +1,318 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_EXTI_H +#define STM32C0xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) +#define EXTI_LINE_16 (EXTI_RESERVED | EXTI_REG1 | 0x10U) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11U) +#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12U) +#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U) +#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14U) +#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15U) +#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16U) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17U) +#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18U) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19U) +#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1AU) +#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1BU) +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1CU) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1DU) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1EU) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1FU) +#if defined(EXTI_IMR2_IM36) +#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00U) +#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01U) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02U) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03U) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04U) +#endif /* EXTI_IMR2_IM36 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#if defined(GPIOD) +#define EXTI_GPIOD 0x00000003u +#endif /* GPIOD */ +#define EXTI_GPIOF 0x00000005u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR2_IM36) +#define EXTI_LINE_NB 37uL +#else +#define EXTI_LINE_NB 32uL +#endif /* EXTI_IMR2_IM36 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \ + EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \ + &&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U)))) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) +#if defined(GPIOD) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOF)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOF)) +#endif /* GPIOD */ +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_EXTI_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h (revision 41) @@ -0,0 +1,817 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_FLASH_H +#define STM32C0xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled + This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ + uint32_t NbPages; /*!< Number of pages to be erased. + This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_Type */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_Area */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]*/ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1] */ + uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of + @ref FLASH_OB_USER_BOR_ENABLE, + @ref FLASH_OB_USER_BOR_LEVEL, + @ref FLASH_OB_USER_nRST_STOP, + @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN, + @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, + @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, + @ref FLASH_OB_USER_SRAM_PARITY, + @ref FLASH_OB_USER_nBOOT_SEL, + @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_nBOOT0, + @ref FLASH_OB_USER_INPUT_RESET_HOLDER*/ + uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). + This parameter must be a combination of @ref FLASH_OB_PCROP_ZONE + and @ref FLASH_OB_PCROP_RDP. Note that once set, Pcrop erase on RDP level 1 + regression (PCROP_RDP bit) can not be reset. It will be reset by mass erase */ + uint32_t PCROP1AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address + of start block to protect. Make sure this parameter is multiple of PCROP + granularity: 512 Bytes.*/ + uint32_t PCROP1AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address + of end block to protect. Make sure this parameter is multiple of PCROP + granularity: 512 Bytes.*/ + uint32_t PCROP1BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address + of start block to protect. Make sure this parameter is multiple of PCROP + granularity: 512 Bytes.*/ + uint32_t PCROP1BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address + of end block to protect. Make sure this parameter is multiple of PCROP + granularity: 512 Bytes.*/ + uint32_t BootEntryPoint; /*!< Allow to force a unique boot entry point to Flash or system Flash */ + uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting + from Flash base address. This parameter must be a value between [0] + and [FLASH_PAGE_NB], [0] meaning no secure area defined, [1] meaning first page + only protected, etc... */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + uint32_t Address; /* Internal variable to save address selected for program in IT context */ + uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ + uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 + to unlock the FLASH registers access */ +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 + to allow option bytes operations */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 0x00000000UL /*!< FLASH Zero wait state */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ + +/** + * @} + */ + +/** @defgroup FLASH_Flags FLASH Flags Definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ +#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ +#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY1 /*!< FLASH Operation Busy flag */ +#define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Configuration Busy flag */ +#define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */ + +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ + FLASH_FLAG_OPTVERR) +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ +#define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ +/** + * @} + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR +#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR +#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only */ +#define FLASH_TYPEERASE_MASS FLASH_CR_MER1 /*!< Flash mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Program Type + * @{ + */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 row double-word (64-bit) + at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Type FLASH Option Bytes Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_SEC 0x00000010U /*!< SEC option byte configuration */ +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte + configuration */ + +/** + * @} + */ + +/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area + * @{ + */ +#define OB_WRPAREA_ZONE_A 0x00000001U /*!< Flash Zone A */ +#define OB_WRPAREA_ZONE_B 0x00000002U /*!< Flash Zone B */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0x000000AAU +#define OB_RDP_LEVEL_1 0x000000BBU +#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 + it is no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type + * @{ + */ +#define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /*!< BOR reset enable */ +#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */ +#define OB_USER_NRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering + the stop mode */ +#define OB_USER_NRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering + the standby mode */ +#define OB_USER_NRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering + the shutdown mode */ +#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ +#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter + freeze in stop mode */ +#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter + freeze in standby mode */ +#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ +#if defined(FLASH_OPTR_HSE_NOT_REMAPPED) +#define OB_USER_HSE_NOT_REMAPPED FLASH_OPTR_HSE_NOT_REMAPPED /*!< Remap HSE source from PF to PC */ +#endif /* FLASH_OPTR_HSE_NOT_REMAPPED */ +#define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity check control */ +#define OB_USER_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN /*!< Multiple-bonding security enable */ +#define OB_USER_NBOOT_SEL FLASH_OPTR_nBOOT_SEL /*!< Boot Selection */ +#define OB_USER_NBOOT1 FLASH_OPTR_nBOOT1 /*!< nBoot1 configuration */ +#define OB_USER_NBOOT0 FLASH_OPTR_nBOOT0 /*!< nBoot0 configuration */ +#define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE /*!< Reset pin configuration */ +#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ + +#if defined(FLASH_OPTR_HSE_NOT_REMAPPED) +#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_NRST_STOP | \ + OB_USER_NRST_STDBY | OB_USER_NRST_SHDW | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_HSE_NOT_REMAPPED | OB_USER_RAM_PARITY_CHECK | \ + OB_USER_SECURE_MUXING_EN | OB_USER_NBOOT_SEL | OB_USER_NBOOT1 | \ + OB_USER_NBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#else +#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_NRST_STOP | \ + OB_USER_NRST_STDBY | OB_USER_NRST_SHDW | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_SECURE_MUXING_EN | \ + OB_USER_NBOOT_SEL | OB_USER_NBOOT1 | \ + OB_USER_NBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#endif /* FLASH_OPTR_HSE_NOT_REMAPPED */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_ENABLE FLASH Option Bytes User BOR enable + * @{ + */ +#define OB_BOR_DISABLE 0x00000000U /*!< BOR Reset set to default */ +#define OB_BOR_ENABLE FLASH_OPTR_BOR_EN /*!< Use option byte to define BOR thresholds */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level + * @{ + */ +#define OB_BOR_LEVEL_FALLING_0 0x00000000U /*!< BOR falling level 1 with + threshold around 2.0V */ +#define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0 /*!< BOR falling level 2 with + threshold around 2.2V */ +#define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1 /*!< BOR falling level 3 with + threshold around 2.5V */ +#define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1) /*!< BOR falling level 4 with + threshold around 2.8V */ +#define OB_BOR_LEVEL_RISING_0 0x00000000U /*!< BOR rising level 1 with + threshold around 2.1V */ +#define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0 /*!< BOR rising level 2 with + threshold around 2.3V */ +#define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1 /*!< BOR rising level 3 with + threshold around 2.6V */ +#define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1) /*!< BOR rising level 4 with + threshold around 2.9V */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop + * @{ + */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ +#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby + * @{ + */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ +#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown + * @{ + */ +#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ +#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type + * @{ + */ +#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ +#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen + in Stop mode */ +#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running + in Stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen + in Standby mode */ +#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running + in Standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type + * @{ + */ +#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ +#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ +/** + * @} + */ + +#if defined(FLASH_OPTR_HSE_NOT_REMAPPED) +/** @defgroup FLASH_OB_USER_HSE_REMAP FLASH Option Bytes User HSE REMAP + * @{ + */ +#define OB_HSE_NOT_REMAPPED_ENABLE 0x00000000U /*!< HSE Remap enable */ +#define OB_HSE_NOT_REMAPPED_DISABLE FLASH_OPTR_HSE_NOT_REMAPPED /*!< HSE Remap disable */ +/** + * @} + */ +#endif /* FLASH_OPTR_HSE_NOT_REMAPPED */ + +/** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity + * @{ + */ +#define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< Sram parity enable */ +#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SECURE_MUXING_EN FLASH Option Bytes User Multiple-bonding security + * @{ + */ +#define OB_SECURE_MUXING_ENABLE FLASH_OPTR_SECURE_MUXING_EN /*!< Multiple-bonding security enable */ +#define OB_SECURE_MUXING_DISABLE 0x00000000U /*!< Multiple-bonding security disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT_SEL FLASH Option Bytes User Boot0 Selection + * @{ + */ +#define OB_BOOT0_FROM_PIN 0x00000000U /*!< BOOT0 signal is defined by PA14/BOOT0 pin value */ +#define OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL /*!< BOOT0 signal is defined by nBOOT0 option bit */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type + * @{ + */ +#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space + (if nBOOT0=0 or BOOT0_pin=1) */ +#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space + (if nBOOT0=0 or BOOT0_pin=1) */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit + * @{ + */ +#define OB_NBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ +#define OB_NBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit + * @{ + */ +#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */ +#define OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode mode only */ +#define OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit + * @{ + */ +#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler enable */ +#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset handler disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE + * @{ + */ +#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ +#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ +/** + * @} + */ + +/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 */ +#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 + (full mass erase).Once this bit is set only, + it will be reset by mass erase */ +/** + * @} + */ + +/** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock + * @{ + */ +#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000U /*!< Boot entry is free */ +#define OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK /*!< Boot entry is forced to Flash or System Flash */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @brief macros to control FLASH features + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * This parameter can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * Returned value can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Reset the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + } while (0U) +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag + * @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used. + * @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the FLASHs pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @retval None + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32c0xx_hal_flash_ex.h" +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Variables FLASH Exported Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types --------------------------------------------------------*/ +/** @defgroup FLASH_Private_types FLASH Private Types + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE + +#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */ + +#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) /*!< Number of pages per bank */ + +#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ + +#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ + +#define FLASH_FLAG_SR_ERROR (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ + FLASH_FLAG_OPTVERR) /*!< All SR error flags */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && \ + ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && \ + ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL))) + +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U) && \ + ((__ADDRESS__) <= (0x1FFF7400U - 8UL))) + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)) || \ + (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__))) + +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && \ + ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL))) + +#define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB) + +#define IS_FLASH_BANK(__BANK__) ((__BANK__) == 0x00UL) + +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ + ((__VALUE__) == FLASH_TYPEERASE_MASS)) + +#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) + +#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \ + (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U)) + +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || \ + ((__VALUE__) == OB_WRPAREA_ZONE_B)) + +#define IS_OB_RDP_LEVEL(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(__TYPE__) ((((__TYPE__) & OB_USER_ALL) != 0x00U) && \ + (((__TYPE__) & ~OB_USER_ALL) == 0x00U)) + +#define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U) + +#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \ + OB_PCROP_RDP_ERASE)) == 0x00U) + +#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE) || \ + ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH)) + +#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U)) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_FLASH_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h (revision 41) @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_FLASH_EX_H +#define STM32C0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ +/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check + * @{ + */ +#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ +#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +void HAL_FLASHEx_EnableDebugger(void); +void HAL_FLASHEx_DisableDebugger(void); +uint32_t HAL_FLASHEx_FlashEmptyCheck(void); +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); +void HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout + Protection granularity offset */ +#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout + Protection granularity, 512 Bytes */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) +void FLASH_PageErase(uint32_t Page); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_FLASH_EX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h (revision 41) @@ -0,0 +1,354 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_GPIO_H +#define STM32C0xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +/*!< Input Floating Mode */ +#define GPIO_MODE_INPUT (0x00000000U) +/*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001U) +/*!< Output Open Drain Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011U) +/*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_PP (0x00000002U) +/*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_AF_OD (0x00000012U) +/*!< Analog Mode */ +#define GPIO_MODE_ANALOG (0x00000003U) +/*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_RISING (0x10110000U) +/*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000U) +/*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) +/*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000U) +/*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000U) +/*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< Very high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line rising pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line falling pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) + +/** + * @brief Clear the EXTI line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32c0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_GPIO_H */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h (revision 41) @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_GPIO_EX_H +#define STM32C0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_I2S1 ((uint8_t)0x00) /*!< I2S1 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#if !defined(STM32C011xx) +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#endif /* !STM32C011xx */ +#if defined(STM32C031xx) || defined(STM32C071xx) || defined(STM32C091xx) || defined(STM32C092xx) +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#endif /* STM32C031xx | STM32C071xx | STM32C091xx | STM32C092xx*/ +#if defined(SPI2) +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#endif /* SPI2 */ +#if defined(CRS) +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */ +#endif /* CRS */ +#if defined(USART3) +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#if defined(USART4) +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#if !defined(STM32C011xx) +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#endif /* STM32C011xx */ +#if defined(TIM15) +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ +#if defined(USB_DRD_FS) +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< USB Alternate Function mapping */ +#endif /* USB_DRD_FS */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_MCO2 ((uint8_t)0x03) /*!< MCO2 Alternate Function mapping */ +#define GPIO_AF3_TIM3 ((uint8_t)0x03) /*!< TIM3 Alternate Function mapping */ +#if defined(SPI2) +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ +#endif /* SPI2 */ +#if defined(TIM2) +#define GPIO_AF3_TIM2 ((uint8_t)0x03) /*!< TIM2 Alternate Function mapping */ +#endif /* TIM2 */ +#if defined(STM32C051xx) +#define GPIO_AF3_USART1 ((uint8_t)0x03) /*!< USART1 Alternate Function mapping */ +#endif /* STM32C051xx */ +#if defined(FDCAN1) +#define GPIO_AF3_FDCAN1 ((uint8_t)0x03) /*!< FDCAN1 Alternate Function mapping */ +#endif /* TIM2 */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#if defined(TIM15) +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#if defined(USART3) +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#if defined(CRS) +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< CRS Alternate Function mapping */ +#endif /* CRS */ +#if defined(SPI2) +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#endif /* SPI2 */ +#if defined(FDCAN1) +#define GPIO_AF4_FDCAN1 ((uint8_t)0x04) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_I2S ((uint8_t)0x05) /*!< I2S Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#if defined(TIM2) +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /*!< TIM2 Alternate Function mapping */ +#endif /* TIM2 */ +#if defined(TIM15) +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#if defined(SPI2) +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#endif /* SPI2 */ +#if defined(I2C2) +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< I2C2 Alternate Function mapping */ +#endif /* I2C2 */ +#if defined(USART3) +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ +#if defined(USART4) +#define GPIO_AF5_USART4 ((uint8_t)0x05) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#if defined(TIM2) +#define GPIO_AF6_TIM2 ((uint8_t)0x06) /*!< TIM2 Alternate Function mapping */ +#endif /* TIM2 */ +#if defined(SPI2) +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /*!< SPI2 Alternate Function mapping */ +#endif /* SPI2 */ +#if defined(I2C2) +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#endif /* I2C2 */ +#if defined(USB_DRD_FS) +#define GPIO_AF6_USB ((uint8_t)0x06) /*!< USB Alternate Function mapping */ +#endif /* USB_DRD_FS */ +#if defined(USART4) +#define GPIO_AF6_USART4 ((uint8_t)0x06) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF7_I2C1 ((uint8_t)0x07) /*!< I2C1 Alternate Function mapping */ +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2S1 ((uint8_t)0x08) /*!< I2S1 Alternate Function mapping */ +#define GPIO_AF8_SPI1 ((uint8_t)0x08) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ +#if defined(I2C2) +#define GPIO_AF8_I2C2 ((uint8_t)0x08) /*!< I2C2 Alternate Function mapping */ +#endif /* I2C2 */ +#if defined(TIM15) +#define GPIO_AF8_TIM15 ((uint8_t)0x08) /*!< TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#if defined(USART3) +#define GPIO_AF8_USART3 ((uint8_t)0x08) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ +#if defined(FDCAN1) +#define GPIO_AF8_FDCAN1 ((uint8_t)0x08) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF9_USART2 ((uint8_t)0x09) /*!< USART2 Alternate Function mapping */ +#if defined(USART4) +#define GPIO_AF9_USART4 ((uint8_t)0x09) /*!< USART4 Alternate Function mapping */ +#endif /* USART4 */ +#define GPIO_AF9_SPI1 ((uint8_t)0x09) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF9_I2S1 ((uint8_t)0x09) /*!< I2S1 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM1 ((uint8_t)0x0A) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF10_I2C1 ((uint8_t)0x0A) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF10_SPI1 ((uint8_t)0x0A) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF10_TIM16 ((uint8_t)0x0A) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM3 ((uint8_t)0x0B) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF11_MCO2 ((uint8_t)0x0B) /*!< MCO2 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM3 ((uint8_t)0x0C) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF12_USART1 ((uint8_t)0x0C) /*!< USART1 Alternate Function mapping */ +#if defined(SPI2) +#define GPIO_AF12_SPI2 ((uint8_t)0x0C) /*!< SPI2 Alternate Function mapping */ +#endif /* SPI2 */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_TIM14 ((uint8_t)0x0D) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF13_TIM3 ((uint8_t)0x0D) /*!< TIM3 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_USART1 ((uint8_t)0x0E) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF14_I2C1 ((uint8_t)0x0E) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF15_MCO2 ((uint8_t)0x0F) /*!< MCO2 Alternate Function mapping */ +#if defined(STM32C011xx) || defined(STM32C031xx) || defined(STM32C051xx) || defined(STM32C071xx) +#define GPIO_AF15_TIM17 ((uint8_t)0x0F) /*!< TIM17 Alternate Function mapping */ +#endif /* STM32C011xx | STM32C031xx | STM32C051xx || STM32C071xx */ +#if defined(FDCAN1) +#define GPIO_AF15_FDCAN1 ((uint8_t)0x0F) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ +#if defined(GPIOD) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOF))? 5UL : 6UL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOF))? 5UL : 6UL) +#endif /* GPIOD */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_GPIO_EX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_iwdg.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_iwdg.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_iwdg.h (revision 41) @@ -0,0 +1,237 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_IWDG_H +#define STM32C0xx_HAL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup IWDG IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Types IWDG Exported Types + * @{ + */ + +/** + * @brief IWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + +} IWDG_InitTypeDef; + +/** + * @brief IWDG Handle Structure definition + */ +typedef struct +{ + IWDG_TypeDef *Instance; /*!< Register base address */ + + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ +} IWDG_HandleTypeDef; + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_Prescaler IWDG Prescaler + * @{ + */ +#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ +/** + * @} + */ + +/** @defgroup IWDG_Window_option IWDG Window option + * @{ + */ +#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** + * @brief Enable the IWDG peripheral. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) + +/** + * @brief Reload IWDG counter with value defined in the reload register + * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled). + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions + * @{ + */ + +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions + * @{ + */ +/* Initialization/Start functions ********************************************/ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_Private_Constants IWDG Private Constants + * @{ + */ + +/** + * @brief IWDG Key Register BitMask + */ +#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Macros IWDG Private Macros + * @{ + */ + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) + +/** + * @brief Check IWDG prescaler value. + * @param __PRESCALER__ IWDG prescaler value + * @retval None + */ +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)) + +/** + * @brief Check IWDG reload value. + * @param __RELOAD__ IWDG reload value + * @retval None + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) + +/** + * @brief Check IWDG window value. + * @param __WINDOW__ IWDG window value + * @retval None + */ +#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_IWDG_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h (revision 41) @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_PWR_H +#define STM32C0xx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ +#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ +#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ +#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ +#endif /* PWR_CR3_EWUP5 */ +#define PWR_WAKEUP_PIN6 PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ +#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ +#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ +#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ +#endif /* PWR_CR3_EWUP5*/ +#define PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ +#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */ +#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */ +#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */ +#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */ +#endif /* PWR_CR3_EWUP5 */ +#define PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */ +/** + * @} + */ + +/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection + * @{ + */ +#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */ +#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ +#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000u) /*!< Regulator in main mode */ + +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01u) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02u) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01u) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02u) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + + +/** @defgroup PWREx_Flag PWR Status Flags + * @brief Elements values convention: 0000 00XX 000Y YYYYb + * - Y YYYY : Flag position in the XX register (5 bits) + * - XX : Status register (2 bits) + * - 01: SR1 register + * - 10: SR2 register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +#define PWR_FLAG_WUF1 (0x00010000u | PWR_SR1_WUF1) /*!< Wakeup event on wakeup pin 1 */ +#define PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2) /*!< Wakeup event on wakeup pin 2 */ +#define PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3) /*!< Wakeup event on wakeup pin 3 */ +#define PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4) /*!< Wakeup event on wakeup pin 4 */ +#if defined(PWR_CR3_EWUP5) +#define PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5) /*!< Wakeup event on wakeup pin 5 */ +#endif /* PWR_CR3_EWUP5 */ +#define PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6) /*!< Wakeup event on wakeup pin 6 */ +#define PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF) /*!< Wakeup event on all wakeup pin */ +#define PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF) /*!< Standby flag */ +#define PWR_FLAG_WUFI (0x00010000u | PWR_SR1_WUFI) /*!< Wakeup on internal wakeup line */ +#define PWR_FLAG_FLASH_READY (0x00020000u | PWR_SR2_FLASH_RDY) /*!< Flash ready */ +#if defined(PWR_PVM_SUPPORT) +#define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_VDDIO2) /*!< Power Voltage Monitoring output */ +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one a combination of following values: + * @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. (*) + * @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event + * was received from the WKUP pin 6. + * @arg PWR_FLAG_SB: StandBy Flag. Indicates that the system + * entered StandBy mode. + * @arg PWR_FLAG_WUFI: Wake-Up Flag Internal. Set when a wakeup is + * detected on the internal wakeup line. + * OR a combination of following values: + * @arg PWR_FLAG_FLASH_READY: Flash is ready. Indicates whether flash + * can be used or not + * @arg PWR_FLAG_PVMO_USB: Peripheral Voltage Monitoring Output. Indicates whether VDDUSB voltage + * is below or above PVM threshold. (*) + * @note (*) Availability depends on devices + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) (((__FLAG__) & 0x00010000u) ?\ + ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == \ + ((__FLAG__) & ~0x00030000u)) :\ + ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == \ + ((__FLAG__) & ~0x00030000u))) + +/** @brief Clear a specific PWR flag. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be a combination of following values: + * @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. (*) + * @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event + * was received from the WKUP pin 6. + * @arg PWR_FLAG_SB: Standby Flag. Indicates that the system + * entered Standby mode. + * @note (*) Availability depends on devices + * @retval None + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->SCR = (__FLAG__)) + +/** + * @} + */ + +/* Private constants-------------------------------------------------------*/ +/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants + * @{ + */ +#define PWR_WUP_POLARITY_SHIFT 0x08u /*!< Internal constant used to retrieve wakeup pin polariry */ +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#define IS_PWR_WAKEUP_PIN(PIN) ((((PIN) & ((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) != 0x00000000u) && \ + (((PIN) & ~((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) == 0x00000000u)) + +#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR) == PWR_MAINREGULATOR_ON) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32c0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSTANDBYMode(void); +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32C0xx_HAL_PWR_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h (revision 41) @@ -0,0 +1,406 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_PWR_EX_H +#define STM32C0xx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_USB Peripheral Voltage Monitoring USB enable */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVM_Mode. */ +} PWR_PVMTypeDef; +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +#if defined(PWR_PVM_SUPPORT) +/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type + * @{ + */ +#define PWR_PVM_USB PWR_CR2_PVM_VDDIO2_0 /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep + the USB peripheral voltage monitoring under control (power domain Vddio2) */ +/** + * @} + */ +/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode + * @{ + */ +#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ +#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ +/** @defgroup PWR_PVM_EXTI_LINE PWR PVM external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVM (EXTI_IMR2_IM34) /*!< External interrupt line 34 connected to PVM */ +/** + * @} + */ + +/** @defgroup PWR_PVM_EVENT_LINE PWR PVM event line + * @{ + */ +#define PWR_EVENT_LINE_PVM (EXTI_EMR2_EM34) /*!< Event line 34 connected to PVM */ +/** + * @} + */ +#endif /* PWR_PVM_SUPPORT */ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask + * @{ + */ +#define PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */ +#define PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */ +#define PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */ +#define PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */ +#define PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */ +#define PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */ +#define PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */ +#define PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */ +#define PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */ +#define PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */ +#define PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */ +#define PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */ +#define PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */ +#define PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */ +#define PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */ +#define PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** @defgroup PWREx_Backup_Registers PWREx Backup Registers Definition + * @{ + */ +#define PWR_BKP_NUMBER 4U +#define PWR_BKP_DR0 0x00U +#define PWR_BKP_DR1 0x01U +#define PWR_BKP_DR2 0x02U +#define PWR_BKP_DR3 0x03U +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Port GPIO Port + * @{ + */ +#define PWR_GPIO_A (0x00000000u) /*!< GPIO port A */ +#define PWR_GPIO_B (0x00000001u) /*!< GPIO port B */ +#define PWR_GPIO_C (0x00000002u) /*!< GPIO port C */ +#if defined(GPIOD) +#define PWR_GPIO_D (0x00000003u) /*!< GPIO port D */ +#endif /* GPIOD */ +#define PWR_GPIO_F (0x00000005u) /*!< GPIO port F */ +/** + * @} + */ + +/** @defgroup PWREx_Flash_PowerDown Flash Power Down modes + * @{ + */ +#define PWR_FLASHPD_SLEEP PWR_CR1_FPD_SLP /*!< Enable Flash power down in sleep mode */ +#define PWR_FLASHPD_STOP PWR_CR1_FPD_STOP /*!< Enable Flash power down in stop mode */ +/** + * @} + */ + +/** @addtogroup PWR_Flag PWR Status Flags + * @brief Elements values convention: 0000 00XX 000Y YYYYb + * - Y YYYY : Flag position in the XX register (5 bits) + * - XX : Status register (2 bits) + * - 01: SR1 register + * - 10: SR2 register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +#if defined(PWR_PVM_SUPPORT) +#define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB) /*!< USB Peripheral Voltage Monitoring output */ +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Enable the PVM Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Event Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM) + +/** + * @brief Disable the PVM Event Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the PVM Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM) + +/** + * @brief Check whether or not the PVM EXTI interrupt Rising flag is set. + * @retval EXTI PVM Line Status. + */ +#define __HAL_PWR_PVM_EXTI_GET_RISING_FLAG() (EXTI->RPR2 & PWR_EXTI_LINE_PVM) + +/** + * @brief Check whether or not the PVM EXTI interrupt Falling flag is set. + * @retval EXTI PVM Line Status. + */ +#define __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() (EXTI->FPR2 & PWR_EXTI_LINE_PVM) + +/** + * @brief Clear the PVM EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Clear the PVM EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM) +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ +#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) ((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \ + (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u)) +#if defined(GPIOD) +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \ + ((__GPIO__) == PWR_GPIO_B) || \ + ((__GPIO__) == PWR_GPIO_C) || \ + ((__GPIO__) == PWR_GPIO_D) || \ + ((__GPIO__) == PWR_GPIO_F)) +#else +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \ + ((__GPIO__) == PWR_GPIO_B) || \ + ((__GPIO__) == PWR_GPIO_C) || \ + ((__GPIO__) == PWR_GPIO_F)) + +#endif /* GPIOD */ +#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_SLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \ + (((__MODE__) & ~(PWR_FLASHPD_SLEEP | PWR_FLASHPD_STOP)) == 0x00u)) + +#define IS_PWR_BKP(__BKP__) ((__BKP__) < PWR_BKP_NUMBER) + +#if defined(PWR_PVM_SUPPORT) +#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB) + +#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) +#endif /* PWR_PVM_SUPPORT */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWREx_EnableInternalWakeUpLine(void); +void HAL_PWREx_DisableInternalWakeUpLine(void); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); +void HAL_PWREx_BKUPWrite(uint32_t BackupRegister, uint16_t Data); +uint32_t HAL_PWREx_BKUPRead(uint32_t BackupRegister); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWREx_EnterSHUTDOWNMode(void); + +#if defined(PWR_PVM_SUPPORT) +/* Power voltage monitoring configuration functions ***************************/ +void HAL_PWREx_EnablePVMUSB(void); +void HAL_PWREx_DisablePVMUSB(void); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +#endif /* PWR_PVM_SUPPORT */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32C0xx_HAL_PWR_EX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h (revision 41) @@ -0,0 +1,2201 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_RCC_H +#define STM32C0xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" +#include "stm32c0xx_ll_rcc.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ +/** + * @} + */ + +/* Defines used for Flags */ +#define RCC_CR_REG_INDEX 1U +#define RCC_CSR1_REG_INDEX 2U +#define RCC_CSR2_REG_INDEX 3U +#if defined(RCC_HSI48_SUPPORT) +#define RCC_CRRCR_REG_INDEX 4U +#endif /* RCC_HSI48_SUPPORT */ + +#define RCC_FLAG_MASK 0x1FU + +/* Define used for IS_RCC_CLOCKTYPE() */ +#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#if defined(RCC_CR_HSIUSB48ON) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ + (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#else +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ + (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#endif /* RCC_CR_HSIUSB48ON */ + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#if defined(RCC_CR_HSIUSB48ON) +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) +#endif /* RCC_CR_HSIUSB48ON */ + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) + +#define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ + ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \ + ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \ + ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + + +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\ + & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSIUSB48) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)) +#else +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)) +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_CR_SYSDIV) +#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ + ((SYSCLK) == RCC_SYSCLK_DIV3) || ((SYSCLK) == RCC_SYSCLK_DIV4) || \ + ((SYSCLK) == RCC_SYSCLK_DIV5) || ((SYSCLK) == RCC_SYSCLK_DIV6) || \ + ((SYSCLK) == RCC_SYSCLK_DIV7) || ((SYSCLK) == RCC_SYSCLK_DIV8)) +#else +#define IS_RCC_SYSCLK(SYSCLK) ((SYSCLK) == RCC_SYSCLK_DIV1) +#endif /* RCC_CR_SYSDIV */ + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ + ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ + ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ + ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ + ((HCLK) == RCC_HCLK_DIV512)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_APB1_DIV1) || ((__PCLK__) == RCC_APB1_DIV2) || \ + ((__PCLK__) == RCC_APB1_DIV4) || ((__PCLK__) == RCC_APB1_DIV8) || \ + ((__PCLK__) == RCC_APB1_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#if defined(STM32C011xx) +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ + ((__MCOX__) == RCC_MCO1_PA9) || \ + ((__MCOX__) == RCC_MCO1_PF2) || \ + ((__MCOX__) == RCC_MCO2_PA8) || \ + ((__MCOX__) == RCC_MCO2_PA10) || \ + ((__MCOX__) == RCC_MCO2_PA14)) +#else +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ + ((__MCOX__) == RCC_MCO1_PA9) || \ + ((__MCOX__) == RCC_MCO1_PF2) || \ + ((__MCOX__) == RCC_MCO2_PA8) || \ + ((__MCOX__) == RCC_MCO2_PA10) || \ + ((__MCOX__) == RCC_MCO2_PA14) || \ + ((__MCOX__) == RCC_MCO2_PA15) || \ + ((__MCOX__) == RCC_MCO2_PB2)) +#endif /* STM32C011xx */ + +#if defined(RCC_CR_HSIUSB48ON) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) +#else +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) +#endif /* RCC_CR_HSIUSB48ON */ + +#if defined(RCC_CR_HSIUSB48ON) +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSE)) +#else +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSE)) +#endif /* RCC_CR_HSIUSB48ON */ + +#if defined(RCC_CFGR_MCOPRE_3) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32) || \ + ((__DIV__) == RCC_MCODIV_64)|| ((__DIV__) == RCC_MCODIV_128) || \ + ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \ + ((__DIV__) == RCC_MCODIV_1024)) +#else +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32) || \ + ((__DIV__) == RCC_MCODIV_64)|| ((__DIV__) == RCC_MCODIV_128)) +#endif /* RCC_CFGR_MCOPRE_3 */ + +#if defined(RCC_CFGR_MCO2PRE_3) +#define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ + ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ + ((__DIV__) == RCC_MCO2DIV_16)|| ((__DIV__) == RCC_MCO2DIV_32) || \ + ((__DIV__) == RCC_MCO2DIV_64)|| ((__DIV__) == RCC_MCO2DIV_128) || \ + ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512) || \ + ((__DIV__) == RCC_MCO2DIV_1024)) +#else +#define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ + ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ + ((__DIV__) == RCC_MCO2DIV_16)|| ((__DIV__) == RCC_MCO2DIV_32) || \ + ((__DIV__) == RCC_MCO2DIV_64)|| ((__DIV__) == RCC_MCO2DIV_128)) +#endif /* RCC_CFGR_MCO2PRE_3 */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSIDiv; /*!< The division factor of the HSI48. + This parameter can be a value of @ref RCC_HSI_Div */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + +#if defined(RCC_CR_HSIUSB48ON) + uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32C071xx devices). + This parameter can be a value of @ref RCC_HSI48_Config */ + +#endif /* RCC_CR_HSIUSB48ON */ +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a combination of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be + a value of @ref RCC_SYS_Clock_Divider */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_HCLK_Clock_Divider */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Divider */ + + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#if defined(RCC_CR_HSIUSB48ON) +#define RCC_OSCILLATORTYPE_HSI48 0x00000010U /*!< HSI48 to configure */ +#endif /* RCC_CR_HSIUSB48ON */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_CSR1_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR1_LSEBYP | RCC_CSR1_LSEON)) /*!< External clock source for LSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Div HSI Div + * @{ + */ +#define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ +#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ +#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ +#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ +#define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */ +#define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */ +#define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */ +#define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */ +/** + * @} + */ + + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR2_LSION /*!< LSI clock activation */ +/** + * @} + */ + +#if defined(RCC_CR_HSIUSB48ON) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CR_HSIUSB48ON /*!< HSI48 clock activation */ +/** + * @} + */ +#endif /* RCC_CR_HSIUSB48ON */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_SYSCLKSOURCE_HSIUSB48 RCC_CFGR_SW_1 /*!< HSIUSB48 selection used as system clock */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */ +#define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_SYSCLKSOURCE_STATUS_HSIUSB48 RCC_CFGR_SWS_1 /*!< HSIUSB48 used as system clock */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_SYS_Clock_Divider RCC SYS Clock Divider + * @{ + */ +#if defined(RCC_CR_SYSDIV) +#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CR_SYSDIV_0 /*!< SYSCLK is divided by 2 */ +#define RCC_SYSCLK_DIV3 RCC_CR_SYSDIV_1 /*!< SYSCLK is divided by 3 */ +#define RCC_SYSCLK_DIV4 (RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK is divided by 4 */ +#define RCC_SYSCLK_DIV5 RCC_CR_SYSDIV_2 /*!< SYSCLK is divided by 5 */ +#define RCC_SYSCLK_DIV6 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_0) /*!< SYSCLK is divided by 6 */ +#define RCC_SYSCLK_DIV7 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1) /*!< SYSCLK is divided by 7 */ +#define RCC_SYSCLK_DIV8 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK is divided by 8 */ +#else +#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ +#endif /* RCC_CR_SYSDIV */ +/** + * @} + */ + +/** @defgroup RCC_HCLK_Clock_Divider RCC HCLK Clock Divider + * @{ + */ +#define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_HPRE_3 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 16 */ +#define RCC_HCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< HCLK divided by 64 */ +#define RCC_HCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 128 */ +#define RCC_HCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 256 */ +#define RCC_HCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Divider RCC APB1 Clock Divider + * @{ + */ +#define RCC_APB1_DIV1 0x00000000U /*!< APB not divided */ +#define RCC_APB1_DIV2 RCC_CFGR_PPRE_2 /*!< APB divided by 2 */ +#define RCC_APB1_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< APB divided by 4 */ +#define RCC_APB1_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< APB divided by 4 */ +#define RCC_APB1_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< APB divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */ +#define RCC_RTCCLKSOURCE_LSE RCC_CSR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_CSR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_CSR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ + +/* @cond */ +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) + +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +#define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ +/* @endcond */ + +#define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ + (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO1_PA9 (RCC_MCO1_INDEX |\ + (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) +#define RCC_MCO1_PF2 (RCC_MCO1_INDEX |\ + (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) +#define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ + +#define RCC_MCO2_PA8 (RCC_MCO2_INDEX |\ + (GPIO_AF15_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO2_PA10 (RCC_MCO2_INDEX |\ + (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) +#define RCC_MCO2_PA14 (RCC_MCO2_INDEX |\ + (GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_14) +#if !defined(STM32C011xx) +#define RCC_MCO2_PA15 (RCC_MCO2_INDEX |\ + (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15) +#define RCC_MCO2_PB2 (RCC_MCO2_INDEX |\ + (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) +#endif /* STM32C011xx */ +#define RCC_MCO2 RCC_MCO2_PA10 /*!< Alias for compatibility */ + +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ +#define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0| RCC_CFGR_MCO2SEL_1) /*!< HSI selection as MCO2 source */ +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ +#define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */ +#define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_3 /*!< HSI48 selection as MCO2 source */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ +/** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */ +#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ +#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ +#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ +#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ +#define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */ +#define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */ +#define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */ +#if defined(RCC_CFGR_MCOPRE_3) +#define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ +#define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ +#define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024*/ +#endif /* RCC_CFGR_MCOPRE_3 */ +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler + * @{ + */ +#define RCC_MCO2DIV_1 0x00000000U /*!< MCO not divided */ +#define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO divided by 2 */ +#define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO divided by 4 */ +#define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 8 */ +#define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO divided by 16 */ +#define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 32 */ +#define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 64 */ +#define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 128 */ +#if defined(RCC_CFGR_MCO2PRE_3) +#define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO divided by 256 */ +#define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 512 */ +#define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 1024*/ +#endif /* RCC_CFGR_MCO2PRE_3 */ +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ +#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_IT_HSI48RDY RCC_CIFR_HSIUSB48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: CSR1 register + * - 011: CSR2 register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#if defined(RCC_HSI48_SUPPORT) +/* Flags in the CR register */ +#define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ +#endif /* RCC_HSI48_SUPPORT */ + +/* Flags in the CSR1 register */ +#define RCC_FLAG_LSERDY ((RCC_CSR1_REG_INDEX << 5U) | RCC_CSR1_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((RCC_CSR1_REG_INDEX << 5U) | RCC_CSR1_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ + +/* Flags in the CSR2 register */ +#define RCC_FLAG_LSIRDY ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_OBLRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_PWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LPWRRSTF_Pos) /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Configuration + * @{ + */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) + +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable + * @brief Enable or disable the IO Ports clock. + * @note After reset, the IO ports clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0U) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) + +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP1_Clock_Enable_Disable APB1_GRP1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM2 */ + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USB_DRD_FS */ + +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* FDCAN1 */ + +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI2 */ + +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRS */ + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART3 */ + +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART4 */ + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C2 */ + +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + UNUSED(tmpreg); \ + } while(0U) +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) +#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN) +#endif /* FDCAN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) +#endif /* CRS */ +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) +#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP2_Clock_Enable_Disable APB1_GRP2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1_GRP2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM15 */ + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) +#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U) +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != 0U) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U) + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U) +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == 0U) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status + * @brief Check whether the IO Port clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != 0U) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP1_Clock_Enabled_Disabled_Status APB1_GRP1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1_GRP1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN) != 0U) +#endif /* FDCAN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) +#endif /* CRS */ +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) +#if defined(I2C2) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCAN1EN) == 0U) +#endif /* FDCAN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) +#endif /* CRS */ +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) +#if defined(I2C2) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP2_Clock_Enabled_Disabled_Status APB1_GRP2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1_GRP2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) +#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU) +#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) +#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) + +#define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U) +#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) +#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset + * @brief Force or release IO Port reset. + * @{ + */ +#define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) + +#define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP1_Force_Release_Reset APB1_GRP1 Peripheral Force Release Reset + * @brief Force or release APB1_GRP1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_GRP1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU) +#if defined(TIM2) +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCAN1RST) +#endif /* FDACN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) +#endif /* CRS */ +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#if defined(USART3) +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) +#if defined(I2C2) +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) +#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) + +#define __HAL_RCC_APB1_GRP1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U) +#if defined(TIM2) +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCAN1RST) +#endif /* FDACN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) +#endif /* CRS */ +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#if defined(USART3) +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) +#if defined(I2C2) +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) +#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP2_Force_Release_Reset APB1_GRP2 Peripheral Force Release Reset + * @brief Force or release APB1_GRP2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_GRP2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) +#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) +#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) + +#define __HAL_RCC_APB1_GRP2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) +#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable + * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) +#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) +#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable + * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. + * @note IOPORT clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP1_Clock_Sleep_Enable_Disable APB1_GRP1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1_GRP1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) +#endif /* FDCAN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) +#endif /* CRS */ +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) +#endif /* FDCAN1 */ +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) +#endif /* USB_DRD_FS */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) +#endif /* CRS */ +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enable_Disable APB1_GRP2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1_GRP2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) +/** + * @} + */ + + +/** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET) +#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status + * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET) + + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) +#if defined (GPIOD) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET) +#endif /* GPIOD */ +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP1_Clock_Sleep_Enabled_Disabled_Status APB1_GRP1 Peripheral Clock Sleep Enabled or + * Disabled Status + * @brief Check whether the APB1_GRP1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) != RESET) +#endif /* FDCAN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET) +#endif /* CRS */ +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) +#if defined(I2C2) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET) +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET) +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define __HAL_RCC_FDCAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCAN1SMEN) == RESET) +#endif /* FDCAN1 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET) +#endif /* SPI2 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET) +#endif /* CRS */ +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET) +#endif /* USART4 */ +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) +#if defined(I2C2) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET) +#endif /* I2C2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enabled_Disabled_Status APB1_GRP2 Peripheral Clock Sleep Enabled or + * Disabled Status + * @brief Check whether the APB1_GRP2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) +/** + * @} + */ + +/** @defgroup RCC_RTC_Domain_Reset RCC RTC Domain Reset + * @{ + */ + +/** @brief Macros to force or release the RTC domain reset. + * @note This function resets the RTC peripheral + * and the RTC clock source selection in RCC_CSR1 register. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN) +/** + * @} + */ + +/** @defgroup RCC_Clock_Configuration RCC Clock Configuration + * @{ + */ + +/** @brief Macros to enable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macros to disable the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 127. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** @brief Macro to configure the HSISYS clock. + * @param __HSIDIV__ specifies the HSI16 division factor. + * This parameter can be one of the following values: + * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1 + * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2 + * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4 + * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8 + * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16 + * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32 + * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64 + * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128 + */ +#define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__)) + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one + * of the following: + * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 + * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 + * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 (default after reset) + * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 + * - RCC_CR_HSIDIV_16 HSI oscillator divided by 16 + * - RCC_CR_HSIDIV_32 HSI oscillator divided by 32 + * - RCC_CR_HSIDIV_64 HSI oscillator divided by 64 + * - RCC_CR_HSIDIV_128 HSI oscillator divided by 128 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR2, RCC_CSR2_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0U) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \ + SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \ + } \ + } while(0U) +#if defined(RCC_CR_HSIUSB48ON) +/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the HSI48, the application software should wait on HSI48RDY + * flag to be set indicating that HSI48 clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIUSB48ON) + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIUSB48ON) +#endif /* RCC_CR_HSIUSB48ON */ +/** + * @} + */ + +/** @addtogroup RCC_RTC_Clock_Configuration + * @{ + */ + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the RTC domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power RTC Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * RTC domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + MODIFY_REG( RCC->CSR1, RCC_CSR1_RTCSEL, (__RTC_CLKSOURCE__)) + + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL))) + +/** + * @} + */ + +/** @addtogroup RCC_Clock_Configuration + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSIUSB48 HSIUSB48 oscillator is used as system clock source.(*) + * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source. + * @note (*) peripheral not available on all devices + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSIUSB48 HSIUSB48 used as system clock.(*) + * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source. + * @note (*) peripheral not available on all devices + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, (uint32_t)(__LSEDRIVE__)) + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 (*) + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + * @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256 (*) + * @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512 (*) + * @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024 (*) + * @note (*) not available on all devices + * @retval None + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48 (*) + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2DIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCO2DIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCO2DIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCO2DIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCO2DIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCO2DIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCO2DIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCO2DIV_128 MCO clock source is divided by 128 + * @arg @ref RCC_MCO2DIV_256 MCO clock source is divided by 256 (*) + * @arg @ref RCC_MCO2DIV_512 MCO clock source is divided by 512 (*) + * @arg @ref RCC_MCO2DIV_1024 MCO clock source is divided by 1024 (*) + * @note (*) not available on all devices + * @retval None + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +/** + * @} + */ +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear RCC interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) + * @retval None + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) + * @note (*) peripheral not available on all devices + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR2 |= RCC_CSR2_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) + * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @note (*) peripheral not available on all devices + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == RCC_CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == RCC_CSR1_REG_INDEX) ? RCC->CSR1 : \ + ((((__FLAG__) >> 5U) == RCC_CSR2_REG_INDEX) ? RCC->CSR2 : RCC->CIFR))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ + ? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32c0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_EnableLSECSS(void); +void HAL_RCC_DisableLSECSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, + uint32_t *pFLatency); +/* LSE & HSE CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_LSECSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_RCC_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h (revision 41) @@ -0,0 +1,867 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_RCC_EX_H +#define STM32C0xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t HSIKerClockDivider; /*!< Specifies HSI Kernel divider. + This parameter can be a value of @ref RCCEx_HSIKER_Div */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2s1ClockSelection; /*!< Specifies I2S1 clock source + This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */ + +#if defined(USB_DRD_FS) + uint32_t UsbClockSelection; /*!< Specifies USB clock source. + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif /* USB_DRD_FS */ + +#if defined(FDCAN1) + uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 clock source. + This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ +#endif /* FDCAN1 */ + + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +} RCC_PeriphCLKInitTypeDef; + +#if defined (CRS) +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC + event. It can be calculated in using macro + @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of + @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of + @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x3F or a value of + @ref RCCEx_CRS_HSI48CalibrationDefault */ + +} RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in RC48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +} RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_CSR1_LSCOSEL /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 0x00000001U +#define RCC_PERIPHCLK_I2C1 0x00000002U +#define RCC_PERIPHCLK_I2S1 0x00000004U +#if defined(USB_DRD_FS) +#define RCC_PERIPHCLK_USB 0x00000008U +#endif /* USB_DRD_FS */ +#if defined(FDCAN1) +#define RCC_PERIPHCLK_FDCAN1 0x00000010U +#endif /* FDCAN1 */ +#define RCC_PERIPHCLK_ADC 0x00000020U +#define RCC_PERIPHCLK_RTC 0x00000040U +#define RCC_PERIPHCLK_HSIKER 0x00000080U + +/** + * @} + */ + + +/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART 1 clock */ +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK clock selected as USART 1 clock */ +#define RCC_USART1CLKSOURCE_HSIKER RCC_CCIPR_USART1SEL_1 /*!< HSI Kernel clock selected as USART 1 clock */ +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /*!< LSE clock selected as USART 1 clock */ +/** + * @} + */ + + +/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSI Kernel clock selected as I2C1 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source + * @{ + */ +#define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_HSIKER RCC_CCIPR_I2S1SEL_1 /*!< HSI Kernel clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ + +/** + * @} + */ +#if defined(USB_DRD_FS) +/** @defgroup RCCEx_USB_Clock_Source USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_HSI48 0x00000000U +#define RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL +/** + * @} + */ +#endif /* USB_DRD_FS */ + +#if defined(FDCAN1) +/** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Clock Source + * @{ + */ +#define RCC_FDCAN1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FDCAN1CLKSOURCE_HSIKER RCC_CCIPR_FDCAN1SEL_0 +#define RCC_FDCAN1CLKSOURCE_HSE RCC_CCIPR_FDCAN1SEL_1 +/** + * @} + */ +#endif /* FDCAN1 */ + +/** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source + * @{ + */ + +#define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ +#define RCC_ADCCLKSOURCE_HSIKER RCC_CCIPR_ADCSEL_1 /*!< HSI kernel used as ADC clock */ +/** + * @} + */ + +/** @defgroup RCCEx_HSIKER_Div HSIKER Div + * @{ + */ +#define RCC_HSIKER_DIV1 0x00000000U /*!< HSI Kernek clock is not divided */ +#define RCC_HSIKER_DIV2 RCC_CR_HSIKERDIV_0 /*!< HSI Kernel clock is divided by 2 */ +#define RCC_HSIKER_DIV3 RCC_CR_HSIKERDIV_1 /*!< HSI Kernel clock is divided by 3 */ +#define RCC_HSIKER_DIV4 (RCC_CR_HSIKERDIV_1|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 4 */ +#define RCC_HSIKER_DIV5 RCC_CR_HSIKERDIV_2 /*!< HSI Kernel clock is divided by 5 */ +#define RCC_HSIKER_DIV6 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 6 */ +#define RCC_HSIKER_DIV7 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_1) /*!< HSI Kernel clock is divided by 7 */ +#define RCC_HSIKER_DIV8 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_1|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 8 */ +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization + signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle + of the trimming interval. The trimming step is specified in + the product datasheet. A higher TRIM value corresponds + to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSIKER HSI Kernel selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSIKER HSI Kernel selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) + +/** @brief Macro to configure the I2S1 clock (I2S1CLK). + * + * @param __I2S1_CLKSOURCE__ specifies the I2S1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_HSIKER HSI Kernel Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock + */ +#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) + +/** @brief Macro to get the I2S1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_HSIKER HSI Kernel Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock + */ +#define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL))) + + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSIKER HSI Kernel selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSIKER HSI Kernel selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) + +#if defined(USB_DRD_FS) +/** @brief Macro to configure the CLK48 source (CLK48CLK). + * + * @param __USB_SOURCE__: specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB source + * @arg RCC_USBCLKSOURCE_HSE : HSE selected as USB source + */ +#define __HAL_RCC_USB_CONFIG(__USB_SOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_SOURCE__)) + +/** @brief macro to get the USB source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBCLKSOURCE_HSI48: HSI48 used as USB source + * @arg RCC_USBCLKSOURCE_HSE : HSE used as USB source + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL))) +#endif /* USB_DRD_FS */ + +#if defined(FDCAN1) +/** @brief Macro to configure the FDCAN1 clock (FDCAN1CLK). + * + * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_FDCAN1CLKSOURCE_PCLK1 APB Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSIKER HSI Kernel Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE clock selected as FDCAN1 clock + */ +#define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCAN1SEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCAN1CLKSOURCE_PCLK1 APB Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSIKER HSI Kernel Clock selected as FDCAN1 clock + * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE clock selected as FDCAN1 clock + */ +#define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCAN1SEL))) +#endif /* FDCAN1 */ + +/** @brief Macro to configure the ADC interface clock + * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSIKER HSI Kernel Clock selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSIKER HSI Kernel Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) + +/** @brief Macro to configure the HSIKER clock. + * @param __HSIKERDIV__ specifies the HSI Kernel division factor. + * This parameter can be one of the following values: + * @arg @ref RCC_HSIKER_DIV1 HSI clock source is divided by 1 + * @arg @ref RCC_HSIKER_DIV2 HSI clock source is divided by 2 + * @arg @ref RCC_HSIKER_DIV3 HSI clock source is divided by 3 + * @arg @ref RCC_HSIKER_DIV4 HSI clock source is divided by 4 + * @arg @ref RCC_HSIKER_DIV5 HSI clock source is divided by 5 + * @arg @ref RCC_HSIKER_DIV6 HSI clock source is divided by 6 + * @arg @ref RCC_HSIKER_DIV7 HSI clock source is divided by 7 + * @arg @ref RCC_HSIKER_DIV8 HSI clock source is divided by 8 + */ +#define __HAL_RCC_HSIKER_CONFIG(__HSIKERDIV__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, (__HSIKERDIV__)) + +/** @brief Macro to get the HSIKER divider. + * @retval The HSI Kernel divider. The returned value can be one + * of the following: + * - RCC_HSIKER_DIV1 HSI oscillator divided by 1 + * - RCC_HSIKER_DIV2 HSI oscillator divided by 2 + * - RCC_HSIKER_DIV3 HSI oscillator divided by 3 (default after reset) + * - RCC_HSIKER_DIV4 HSI oscillator divided by 4 + * - RCC_HSIKER_DIV5 HSI oscillator divided by 5 + * - RCC_HSIKER_DIV6 HSI oscillator divided by 6 + * - RCC_HSIKER_DIV7 HSI oscillator divided by 7 + * - RCC_HSIKER_DIV8 HSI oscillator divided by 8 + */ +#define __HAL_RCC_GET_HSIKER_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIKERDIV))) + +/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + + +/** + * @} + */ + +#if defined(CRS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ + ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and + * consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ + ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + + +/** + * @} + */ + + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +#endif /* CRS */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); + +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#if defined (USB_DRD_FS) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) +#elif defined (FDCAN1) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN1) == RCC_PERIPHCLK_FDCAN1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) +#else +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) +#endif /* USB_DRD_FS */ + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSIKER)) + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSIKER)) + +#define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSIKER) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) + +#if defined (FDCAN1) +#define IS_RCC_FDCAN1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSIKER)|| \ + ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PCLK1)) +#endif /* FDCAN1 */ + +#if defined (USB_DRD_FS) +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) +#endif /* USB_DRD_FS */ + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSIKER)) + +#define IS_RCC_HSIKERDIV(__DIV__) (((__DIV__) == RCC_HSIKER_DIV1) || ((__DIV__) == RCC_HSIKER_DIV2) || \ + ((__DIV__) == RCC_HSIKER_DIV3) || ((__DIV__) == RCC_HSIKER_DIV4) || \ + ((__DIV__) == RCC_HSIKER_DIV5) || ((__DIV__) == RCC_HSIKER_DIV6) || \ + ((__DIV__) == RCC_HSIKER_DIV7) || ((__DIV__) == RCC_HSIKER_DIV8)) + +#if defined(CRS) +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) +#endif /* CRS */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_RCC_EX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h (revision 41) @@ -0,0 +1,2448 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_TIM_H +#define STM32C0xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x10000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x20000000U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#define TIM_DMABASE_TISEL 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#if defined(USB_BASE) +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#endif /* USB_BASE */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#if defined(USB_BASE) +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#endif /* USB_BASE */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#if defined(USB_BASE) +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)) +#else +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) +#endif /* USB_BASE */ + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#if defined(USB_BASE) +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#else +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#endif /* USB_BASE */ + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32c0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_TIM_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h (revision 41) @@ -0,0 +1,378 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_TIM_EX_H +#define STM32C0xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ +} TIMEx_BreakInputConfigTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ + +#if defined(TIM2) +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_LSE (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ +#define TIM_TIM2_ETR_MCO TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to MCO */ +#define TIM_TIM2_ETR_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MCO2 */ +#endif /* TIM2 */ + +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ + +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM14_TI1_GPIO 0x00000000U /*!< TIM14_TI1 is connected to GPIO */ +#define TIM_TIM14_TI1_RTC 0x00000001U /*!< TIM14_TI1 is connected to RTC clock */ +#define TIM_TIM14_TI1_HSE_32 0x00000002U /*!< TIM14_TI1 is connected to HSE div 32 */ +#define TIM_TIM14_TI1_MCO 0x00000003U /*!< TIM14_TI1 is connected to MCO */ +#define TIM_TIM14_TI1_MCO2 0x00000004U /*!< TIM14_TI1 is connected to MCO2 */ + +#if defined(TIM15) +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /*!< TIM15_TI1 is connected to TIM3 CH1 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /*!< TIM15_TI2 is connected to TIM3 CH2 */ +#endif /* TIM15 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16_TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_LSI 0x00000001U /*!< TIM16_TI1 is connected to LSI */ +#define TIM_TIM16_TI1_LSE 0x00000002U /*!< TIM16_TI1 is connected to LSE */ +#define TIM_TIM16_TI1_MCO2 0x00000004U /*!< TIM16_TI1 is connected to MCO2 */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17_TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_HSE_32 0x00000002U /*!< TIM17_TI1 is connected to HSE div 32 */ +#define TIM_TIM17_TI1_MCO 0x00000003U /*!< TIM17_TI1 is connected to MCO */ +#define TIM_TIM17_TI1_MCO2 0x00000004U /*!< TIM17_TI1 is connected to MCO2 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32C0xx_HAL_TIM_EX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h (revision 41) @@ -0,0 +1,1747 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_UART_H +#define STM32C0xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) + + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on C0 (i.e. 48 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32c0xx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_UART_H */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h (revision 41) @@ -0,0 +1,385 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_UART_EX_H +#define STM32C0xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal_def.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +#if defined(USART4) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSIKER: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSIKER: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART4 */ + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_UART_EX_H */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h (revision 41) @@ -0,0 +1,5516 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_ADC_H +#define STM32C0xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (ADC1) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer rank bits position into the selected register */ + +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ + + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ + + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel identifier defined by bitfield */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) +#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to + ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, + if set to mode "fully configurable", can contain channels with a restricted channel number. + Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" + position in register */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ + ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK + >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER (0x00000000UL) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \ + ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1) + +#define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 ) +#define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) + +/* Definition of channels ID bitfield information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) +#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) +#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) +#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) +#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) +#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) +#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) +#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) +#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) +#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) +#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10) +#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) +#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) +#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13) +#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14) +#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15) +#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16) +#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17) +#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18) +#define ADC_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19) +#define ADC_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20) +#define ADC_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21) +#define ADC_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22) + +/* Internal mask for ADC channel sampling time: */ +/* To select into literals LL_ADC_SAMPLINGTIME_x */ +/* the relevant bits for: */ +/* (concatenation of multiple bits used in register SMPR) */ +/* - ADC channels sampling time: setting channel wise, to map each channel */ +/* on one of the common sampling time available. */ +/* - ADC channels common sampling time: set a sampling time into one of the */ +/* common sampling time available. */ +#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS) +#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1) +#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS) + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 series)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC group regular). */ +/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ +/* selection on groups. */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) +#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) + +/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ +/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ +#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) +#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) +#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) +#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) + +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET + in ADC_AWD_CRX_REGOFFSET_MASK */ + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) +#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) +#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS)) +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET + in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate + threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate + threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to + position to perform a shift of 4 ranks */ +#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) + + +/* ADC registers bits positions */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ +#define ADC_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL19" position in register */ +#define ADC_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL20" position in register */ +#define ADC_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL21" position in register */ +#define ADC_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL22" position in register */ +#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */ +#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */ +#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ + + +/* ADC registers bits groups */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART \ + | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property + "rs": Software can read as well as set this bit. Writing '0' has no effect + on the bit value. */ + + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) + voltage with which VrefInt has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +/* Note: On all devices of series STM32C0, calibration parameter TS_CAL2 is not available. + Therefore, macro "__LL_ADC_CALC_TEMPERATURE()" is not available, + macro "__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()" must be used and parameter TS_CAL1 can improve accuracy: + replace datasheet parameter of temperature offset (macro argument __TEMPSENSOR_TYP_CALX_V__) + by TEMPSENSOR_CAL1_ADDR + (with taking into account conversion from digital value resolution 12 bit, analog voltage reference ratio + between calibration and application environments) */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of + parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at + temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V + (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at + which temperature sensor has been calibrated in production for data into + TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage + with which temperature sensor has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetCommonClock(). */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Clock; /*!< Set ADC instance clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE + @note On this STM32 series, this parameter has some clock ratio constraints: + ADC clock synchronous (from PCLK) with prescaler 1 must be enabled + only if PCLK has a 50% duty clock cycle (APB prescaler configured + inside the RCC must be bypassed and the system clock must by 50% duty + cycle). + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetClock(). + For more details, refer to description of this function. */ + + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetDataAlignment(). */ + + uint32_t LowPowerMode; /*!< Set ADC low power mode. + This parameter can be a value of @ref ADC_LL_EC_LP_MODE + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetLowPowerMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or + from external peripheral (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge(default setting for compatibility + with some ADC on other STM32 series having this setting set by HW + default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_REG_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + @note This parameter has an effect only if group regular sequencer is set + to mode "fully configurable". Refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is + enabled (depending on the sequencer mode: scan length of 2 ranks or + more, or several ADC channels enabled in group regular sequencer. + Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC + conversions are performed in single mode (one conversion per trigger) or in + continuous mode (after the first trigger, following conversions launched + successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode + and discontinuous mode. + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer + by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetDMATransfer(). */ + + uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: + data preserved or overwritten. + This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetOverrun(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ +#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary + conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence + conversions */ +#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ +#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ +#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ +#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ +#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ +#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary + conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence + conversions */ +#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling + phase */ +#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ +#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ +#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ +#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without + prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 2. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 4. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 6. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with + prescaler division by 8. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 10. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 12. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 16. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with + prescaler division by 32. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 64. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 128. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 256. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel + temperature sensor */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock + divided by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock + divided by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \ + | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock + not divided */ +#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock + prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @{ + */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power + mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC + automatically powers-off after a ADC conversion and automatically wakes up + when a new ADC conversion is triggered (with startup time between trigger + and start of sampling). See description with function + @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait +and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ +#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ +#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode + * @{ + */ +#define LL_ADC_CLOCK_FREQ_MODE_HIGH LL_ADC_TRIGGER_FREQ_HIGH /*!< LL ADC define maintained for legacy purpose */ +#define LL_ADC_CLOCK_FREQ_MODE_LOW LL_ADC_TRIGGER_FREQ_LOW /*!< LL ADC define maintained for legacy purpose */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels + * @{ + */ +#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group + of channels: sampling time nb 1 */ +#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \ + | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group + of channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \ + | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \ + | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \ + | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \ + | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \ + | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \ + | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \ + | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \ + | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \ + | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \ + | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \ + | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \ + | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \ + | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \ + | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \ + | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \ + | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \ + | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \ + | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \ + | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ +#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER \ + | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */ +#define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER \ + | ADC_CHANNEL_20_BITFIELD) /*!< ADC channel ADCx_IN20 */ +#define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER \ + | ADC_CHANNEL_21_BITFIELD) /*!< ADC channel ADCx_IN21 */ +#define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER \ + | ADC_CHANNEL_22_BITFIELD) /*!< ADC channel ADCx_IN22 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_10 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_9 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to Temperature sensor. */ +#define LL_ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VDDA. */ +#define LL_ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VSSA. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger + from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: + TIM1 channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#if defined(TIM2) +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ +#endif /* TIM2 */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger + from external peripheral: TIM3 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ + | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 11. + Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + * @{ + */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: + one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode: + after the first trigger, following conversions launched successively + automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, + in limited mode (one shot mode): DMA transfer requests are stopped when + number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: + data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: + data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility + * @{ + */ +#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: + sequencer length and each rank affectation to a channel are fixed + by channel HW number. Refer to description of function + @ref LL_ADC_REG_SetSequencerChannels(). */ +#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: + sequencer length and each rank affectation to a channel are configurable. + Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable + with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable + with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable + with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable + with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable + with 8 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction forward: from lowest channel number to highest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer). On some other STM32 series, this setting is not available + and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction backward: from highest channel number to lowest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer + discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ + | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ +#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring + disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN19, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN20, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN21, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN22, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal voltage reference, + converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Temperature sensor, + converted by group regular only */ +#define LL_ADC_AWD_CH_VSSA_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VSSA : internal analog supply ground, + converted by group regular only */ +#define LL_ADC_AWD_CH_VDDA_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VDDA : internal analog power supply, + converted by group regular only */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \ + | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low + concatenated into the same data */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + * @{ + */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of + ADC group regular. Literal suffix "continued" is kept for compatibility + with other STM32 devices featuring ADC group injected, in this case other + oversampling scope parameters are available. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode +(all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous + mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ + | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift + * @{ + */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift + (sum of the ADC conversions data is not divided to result as oversampling + conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 + (sum of the ADC conversions data (after OVS ratio) is divided by 2 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 + (sum of the ADC conversions data (after OVS ratio) is divided by 4 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 + (sum of the ADC conversions data (after OVS ratio) is divided by 8 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 + (sum of the ADC conversions data (after OVS ratio) is divided by 16 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 + (sum of the ADC conversions data (after OVS ratio) is divided by 32 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 + (sum of the ADC conversions data (after OVS ratio) is divided by 64 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ + | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 + (sum of the ADC conversions data (after OVS ratio) is divided by 128 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 + (sum of the ADC conversions data (after OVS ratio) is divided by 256 + to result as oversampling conversion data) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro + * @{ + */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro + @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on + calibration parameters. This value is coded on 16 bits + (to fit on signed word or double word) and corresponds + to an inconsistent temperature value. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC calibration time: maximum delay is 82/fADC. */ +/* (refer to device datasheet, parameter "tCAL") */ +/* - ADC enable time: maximum delay is 1 conversion cycle. */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC disable time: maximum delay should be a few ADC clock cycles */ +/* - ADC stop conversion time: maximum delay should be a few ADC clock */ +/* cycles */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tADCVREG_STUP"). */ +/* Unit: us */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage + regulator start-up time) */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tstart_vrefint"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization + time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time + (starting from temperature sensor enable, refer to + @ref LL_ADC_SetCommonPathInternalCh()) */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization + time (starting from ADC enable, refer to + @ref LL_ADC_Enable()) */ + +/* Delay required between ADC end of calibration and ADC enable. */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ +/* are required between ADC end of calibration and ADC enable. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration + and ADC enable */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ + ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ + ) \ + : \ + ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_19_BITFIELD) == ADC_CHANNEL_19_BITFIELD) ? (19UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_20_BITFIELD) == ADC_CHANNEL_20_BITFIELD) ? (20UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_21_BITFIELD) == ADC_CHANNEL_21_BITFIELD) ? (21UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_22_BITFIELD) == ADC_CHANNEL_22_BITFIELD) ? (22UL) : \ + (0UL))))))))))))))))))))))))) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel + * (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_19 + * @arg @ref LL_ADC_CHANNEL_20 + * @arg @ref LL_ADC_CHANNEL_21 + * @arg @ref LL_ADC_CHANNEL_22 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VDDA + * @arg @ref ADC_CHANNEL_VSSA + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VDDA) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VSSA)) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VDDA_REG + * @arg @ref LL_ADC_AWD_CH_VSSA_REG + * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() + * or @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the ADC analog watchdog threshold high + * or low from raw value containing both thresholds concatenated. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, to get analog watchdog threshold high from the register raw value: + * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); + * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ + & LL_ADC_AWD_THRESHOLD_LOW) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC1) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \ +) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used + * to improve calculation accuracy. + * Refer to @ref TEMPSENSOR_CAL1_ADDR. + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12 bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On this STM32 series, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value + (at temperature and Vref+ defined in parameters below) (unit: mV). + * On this STM32 series, refer to datasheet parameter "V30" (corresponding + * to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage + (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(Register); + + /* Retrieve address of register DR */ + return (uint32_t) &(ADCx->DR); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several + * ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR PRESC LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) + * + * (1) ADC common clock asynchronous prescaler is applied to + * each ADC instance if the corresponding ADC instance clock + * is set to clock source asynchronous. + * (refer to function @ref LL_ADC_SetClock() ). + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR PRESC LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) + * + * (1) ADC common clock asynchronous prescaler is applied to + * each ADC instance if the corresponding ADC instance clock + * is set to clock source asynchronous. + * (refer to function @ref LL_ADC_SetClock() ). + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR TSEN LL_ADC_SetCommonPathInternalCh\n + * CCR VBATEN LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR TSEN LL_ADC_GetCommonPathInternalCh\n + * CCR VBATEN LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC instance clock source and prescaler. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 CKMODE LL_ADC_SetClock + * @param ADCx ADC instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) + * @arg @ref LL_ADC_CLOCK_ASYNC (1) + * + * (1) Asynchronous clock prescaler can be configured using + * function @ref LL_ADC_SetCommonClock().\n + * (2) Caution: This parameter has some clock ratio constraints: + * This configuration must be enabled only if PCLK has a 50% + * duty clock cycle (APB prescaler configured inside the RCC + * must be bypassed and the system clock must by 50% duty + * cycle). + * Refer to reference manual. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); +} + +/** + * @brief Get ADC instance clock source and prescaler. + * @rmtoll CFGR2 CKMODE LL_ADC_GetClock + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) + * @arg @ref LL_ADC_CLOCK_ASYNC (1) + * + * (1) Asynchronous clock prescaler can be retrieved using + * function @ref LL_ADC_GetCommonClock().\n + * (2) Caution: This parameter has some clock ratio constraints: + * This configuration must be enabled only if PCLK has a 50% + * duty clock cycle (APB prescaler configured inside the RCC + * must be bypassed and the system clock must by 50% duty + * cycle). + * Refer to reference manual. + */ +__STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); +} + +/** + * @brief Set ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref LL_ADC_StartCalibration(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled, without calibration on going, without conversion + * on going on group regular. + * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor + * @param ADCx ADC instance + * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor) +{ + MODIFY_REG(ADCx->CALFACT, + ADC_CALFACT_CALFACT, + CalibrationFactor); +} + +/** + * @brief Get ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref LL_ADC_StartCalibration(). + * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); +} + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); +} + +/** + * @brief Set ADC low power mode. + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * - ADC low power mode "auto power-off" (feature available on + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n + * CFGR1 AUTOFF LL_ADC_SetLowPowerMode + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @arg @ref LL_ADC_LP_AUTOPOWEROFF + * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode); +} + +/** + * @brief Get ADC low power mode: + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * - ADC low power mode "auto power-off" (feature available on + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n + * CFGR1 AUTOFF LL_ADC_GetLowPowerMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @arg @ref LL_ADC_LP_AUTOPOWEROFF + * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); +} + +/** + * @brief Set ADC trigger frequency mode. + * @note ADC trigger frequency mode must be set to low frequency when + * a duration is exceeded before ADC conversion start trigger event + * (between ADC enable and ADC conversion start trigger event + * or between two ADC conversion start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + * @note When ADC trigger frequency mode is set to low frequency, + * some rearm cycles are inserted before performing ADC conversion + * start, inducing a delay of 2 ADC clock cycles. + * @note Usage of ADC trigger frequency mode with ADC low power mode: + * - Low power mode auto wait: Only the first ADC conversion + * start trigger inserts the rearm delay. + * - Low power mode auto power-off: ADC trigger frequency mode + * is discarded. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode + * @param ADCx ADC instance + * @param TriggerFrequencyMode This parameter can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); +} + +/** + * @brief Get ADC trigger frequency mode. + * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + */ +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); +} + +/** + * @brief Set sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 series, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other STM32 families, sampling time is channel wise) + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 series, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, + uint32_t SamplingTime) +{ + MODIFY_REG(ADCx->SMPR, + ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), + SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @brief Get sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 series, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other STM32 families, sampling time is channel wise) + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +{ + return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) + >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 families having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note On this STM32 series, ADC trigger frequency mode must be set + * in function of frequency of ADC group regular conversion trigger. + * Refer to description of function + * @ref LL_ADC_SetTriggerFrequencyMode(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * (1) ADC external trigger available on STM32C071xx device only. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * (1) ADC external trigger available on STM32C071xx device only. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) +{ + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + * or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge + * @param ADCx ADC instance + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); +} + +/** + * @brief Set ADC group regular sequencer configuration flexibility. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @param Configurability This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability); +} + +/** + * @brief Get ADC group regular sequencer configuration flexibility. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); +} + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * @ref LL_ADC_REG_SetSequencerScanDirection(). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + SET_BIT(ADCx->CHSELR, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * @ref LL_ADC_REG_SetSequencerScanDirection(). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) +{ + __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; + uint32_t RankIndex; + + /* Parse register for end of sequence identifier */ + for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U) + { + if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex)) + { + SequencerLength = (ADC_CHSELR_SQ2 << RankIndex); + break; + } + } + + return SequencerLength; +} + +/** + * @brief Set ADC group regular sequencer scan direction. + * @note On this STM32 series, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 series, this setting is not available and + * the default scan direction is forward. + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection + * @param ADCx ADC instance + * @param ScanDirection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); +} + +/** + * @brief Get ADC group regular sequencer scan direction. + * @note On this STM32 series, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 families, this setting is not available and + * the default scan direction is forward. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @param Channel This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + return (uint32_t)((READ_BIT(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ); +} + +/** + * @brief Set ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by overwriting the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Add channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by adding them to the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by removing them to the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels order reading into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be retrieved. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels + * @param ADCx ADC instance + * @retval Returned value can be a combination of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) +{ + uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL19) >> ADC_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL20) >> ADC_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL21) >> ADC_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL22) >> ADC_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); +} + +/** + * @brief Set ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @note Compatibility with devices without feature overrun: + * other devices without this feature have a behavior + * equivalent to data overwritten. + * The default setting of overrun is data preserved. + * Therefore, for compatibility with all devices, parameter + * overrun should be set to data overwritten. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun + * @param ADCx ADC instance + * @param Overrun This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); +} + +/** + * @brief Get ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->SMPR, + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) + ); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 (1) + * @arg @ref ADC_CHANNEL_9 (1) + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (3) + * @arg @ref ADC_CHANNEL_18 (3) + * @arg @ref ADC_CHANNEL_19 (3) + * @arg @ref ADC_CHANNEL_20 (3) + * @arg @ref ADC_CHANNEL_21 (3) + * @arg @ref ADC_CHANNEL_22 (3) + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VDDA (2) + * @arg @ref ADC_CHANNEL_VSSA (2) + * + * (1) On STM32C0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (3) ADC channels available on STM32C031xx device only. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) +{ + __IO uint32_t smpr = READ_REG(ADCx->SMPR); + + /* Retrieve sampling time bit corresponding to the selected channel */ + /* and shift it to position 0. */ + uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) + >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + + ADC_SMPR_SMPSEL0_BITOFFSET_POS) + & 0x1FUL)); + + /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ + return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) + | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC group regular. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VDDA_REG + * @arg @ref LL_ADC_AWD_CH_VSSA_REG + * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) +{ + /* Set bits with content of parameter "AWDChannelGroup" with bits position */ + /* in register and register position depending on parameter "AWDy". */ + /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ + /* containing other bits reserved for other purpose. */ + register __IO uint32_t *preg; + + if (AWDy == LL_ADC_AWD1) + { + preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL); + } + else + { + preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)); + } + + MODIFY_REG(*preg, + (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & AWDy); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On this AWD number, monitored channel can be retrieved + * if only 1 channel is programmed (or none or all channels). + * This function cannot retrieve monitored channel if + * multiple channels are programmed simultaneously + * by bitfield. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1) + * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VDDA_REG + * @arg @ref LL_ADC_AWD_CH_VSSA_REG + * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. + */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) +{ + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if (AnalogWDMonitChannels != 0UL) + { + if (AWDy == LL_ADC_AWD1) + { + if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = ((AnalogWDMonitChannels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR1_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos)) + ); + } + } + else + { + if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK + | (ADC_CFGR1_AWD1EN) + ); + } + else + { + /* AWD monitoring a single channel */ + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos) + ); + } + } + } + + return AnalogWDMonitChannels; +} +/** + * @brief Set ADC analog watchdog thresholds value of both thresholds + * high and low. + * @note If value of only one threshold high or low must be set, + * use function @ref LL_ADC_SetAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there is only 2 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, + uint32_t AWDThresholdLowValue) +{ + /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ + /* position in register and register position depending on parameter */ + /* "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) + ); + + MODIFY_REG(*preg, + ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, + (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); +} +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note If values of both thresholds high or low must be set, + * use function @ref LL_ADC_ConfigAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there is only 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is not conditioned to + * ADC state: + * ADC can be disabled, enabled with or without conversion on going + * on ADC group regular. + * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + MODIFY_REG(*preg, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high, + * threshold low or raw data with ADC thresholds high and low + * concatenated. + * @note If raw data with ADC thresholds high and low is retrieved, + * the data of each threshold high or low can be isolated + * using helper macro: + * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + return (uint32_t)(READ_BIT(*preg, + (AWDThresholdsHighLow | ADC_AWD1TR_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~ + (AWDThresholdsHighLow & ADC_AWD1TR_LT1)) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling + * @{ + */ + +/** + * @brief Set ADC oversampling scope. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope + * @param ADCx ADC instance + * @param OvsScope This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); +} + +/** + * @brief Get ADC oversampling scope. + * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); +} + +/** + * @brief Set ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont + * @param ADCx ADC instance + * @param OverSamplingDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); +} + +/** + * @brief Get ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); +} + +/** + * @brief Set ADC oversampling + * @note This function set the 2 items of oversampling configuration: + * - ratio + * - shift + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n + * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift + * @param ADCx ADC instance + * @param Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + * @param Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) +{ + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); +} + +/** + * @brief Get ADC oversampling ratio + * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio + * @param ADCx ADC instance + * @retval Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); +} + +/** + * @brief Get ADC oversampling shift + * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift + * @param ADCx ADC instance + * @retval Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable ADC instance internal voltage regulator. + * @note On this STM32 series, there are three possibilities to enable + * the voltage regulator: + * - by enabling it manually + * using function @ref LL_ADC_EnableInternalRegulator(). + * - by launching a calibration + * using function @ref LL_ADC_StartCalibration(). + * - by enabling the ADC + * using function @ref LL_ADC_Enable(). + * @note On this STM32 series, after ADC internal voltage regulator enable, + * a delay for ADC internal voltage regulator stabilization + * is required before performing a ADC calibration or ADC enable. + * Refer to device datasheet, parameter "tADCVREG_STUP". + * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADVREGEN); +} + +/** + * @brief Disable ADC internal voltage regulator. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance internal voltage regulator state. + * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled + * @param ADCx ADC instance + * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled and ADC internal voltage regulator enabled. + * @rmtoll CR ADEN LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADEN); +} + +/** + * @brief Disable the selected ADC instance. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be not disabled. Must be enabled without conversion on going + * on group regular. + * @rmtoll CR ADDIS LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADDIS); +} + +/** + * @brief Get the selected ADC instance enable state. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll CR ADEN LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the selected ADC instance disable state. + * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing + * @param ADCx ADC instance + * @retval 0: no ADC disable command on going. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 series, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note In case of usage of ADC with DMA transfer: + * On this STM32 series, ADC DMA transfer request should be disabled + * during calibration: + * Calibration factor is available in data register + * and also transferred by DMA. + * To not insert ADC calibration factor among ADC conversion data + * in array variable, DMA transfer must be disabled during + * calibration. + * (DMA transfer setting backup and disable before calibration, + * DMA transfer setting restore after calibration. + * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), + * @ref LL_ADC_REG_SetDMATransfer() ). + * @note In case of usage of feature auto power-off: + * This mode must be disabled during calibration + * Refer to function @ref LL_ADC_SetLowPowerMode(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADCAL LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADCAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTART LL_ADC_REG_StartConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTART); +} + +/** + * @brief Stop ADC group regular conversion. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTP LL_ADC_REG_StopConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTP); +} + +/** + * @brief Get ADC group regular conversion state. + * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular command of conversion stop state + * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing + * @param ADCx ADC instance + * @retval 0: no command of conversion stop is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC channel configuration ready. + * @note On this STM32 series, after modifying sequencer + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, performing some actions (configuration update, + * ADC conversion start, ... ) will be ignored. + * Functions requiring wait for CCRDY flag are: + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks() + * @ref LL_ADC_REG_SetSequencerChannels() + * @ref LL_ADC_REG_SetSequencerChAdd() + * @ref LL_ADC_REG_SetSequencerChRem() + * @ref LL_ADC_REG_SetSequencerScanDirection() + * @ref LL_ADC_REG_SetSequencerConfigurable() + * @note Duration of ADC channel configuration ready: CCRDY handshake + * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration + * has been changed. + * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); +} + +/** + * @brief Clear flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); +} + +/** + * @brief Clear flag ADC channel configuration ready. + * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); +} + +/** + * @brief Clear flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); +} + +/** + * @brief Clear flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); +} + +/** + * @brief Clear flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); +} + +/** + * @brief Clear flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Enable interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); +} + +/** + * @brief Enable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Enable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Enable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Enable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} +/** + * @brief Enable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +/** + * @brief Disable interruption ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Disable interruption ADC channel configuration ready. + * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Disable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Disable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Disable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +/** + * @brief Get state of interruption ADC ready + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC channel configuration ready. + * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sampling + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 2 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 3 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC end of calibration + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_ADC_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_bus.h (revision 41) @@ -0,0 +1,1001 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_BUS_H +#define STM32C0xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN +#endif /* TIM2 */ +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN +#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN +#if defined (USB_DRD_FS) +#define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) +#define LL_APB1_GRP1_PERIPH_FDCAN1 RCC_APBENR1_FDCAN1EN +#endif /* FDCAN1 */ +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN +#endif /* SPI2 */ +#if defined(CRS) +#define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN +#endif /* CRS */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN +#endif /* USART3 */ +#if defined(USART4) +#define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN +#endif /* USART4 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN +#endif /* I2C2 */ +#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN +#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN + +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN +#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN +#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN +#define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN +#define LL_APB1_GRP2_PERIPH_TIM14 RCC_APBENR2_TIM14EN +#if defined(TIM15) +#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APBENR2_TIM15EN +#endif /* TIM15 */ +#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN +#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APBENR2_TIM17EN +#define LL_APB1_GRP2_PERIPH_ADC RCC_APBENR2_ADCEN +/* defines for legacy purpose */ +#define LL_APB2_GRP2_PERIPH_ALL LL_APB1_GRP2_PERIPH_ALL +#define LL_APB2_GRP1_PERIPH_SYSCFG LL_APB1_GRP2_PERIPH_SYSCFG +#define LL_APB2_GRP1_PERIPH_TIM1 LL_APB1_GRP2_PERIPH_TIM1 +#define LL_APB2_GRP1_PERIPH_SPI1 LL_APB1_GRP2_PERIPH_SPI1 +#define LL_APB2_GRP1_PERIPH_USART1 LL_APB1_GRP2_PERIPH_USART1 +#define LL_APB2_GRP1_PERIPH_TIM14 LL_APB1_GRP2_PERIPH_TIM14 +#define LL_APB2_GRP1_PERIPH_TIM16 LL_APB1_GRP2_PERIPH_TIM16 +#define LL_APB2_GRP1_PERIPH_TIM17 LL_APB1_GRP2_PERIPH_TIM17 +#define LL_APB2_GRP1_PERIPH_ADC LL_APB1_GRP2_PERIPH_ADC + +/** + * @} + */ + +/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + * @{ + */ +#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN +#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN +#define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN +#if defined(GPIOD) +#define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN +#endif /* GPIOD */ +#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBSMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBSMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP1 APB1_GRP1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n + * APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n + * APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n + * APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n + * APBENR1 DBGEN LL_APB1_GRP1_EnableClock\n + * APBENR1 PWREN LL_APB1_GRP1_EnableClock\n + * APBENR1 TIM2EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 USBEN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 FDCAN1EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 USART3EN LL_APB1_GRP1_EnableClock\n (*) + * APBENR1 USART4EN LL_APB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APBENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APBENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 GRP1 peripheral clock is enabled or not + * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n + * APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 FDCAN1EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 GRP1 peripherals clock. + * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n + * APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n + * APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n + * APBENR1 USART2EN LL_APB1_GRP1_DisableClock\n + * APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n + * APBENR1 DBGEN LL_APB1_GRP1_DisableClock\n + * APBENR1 PWREN LL_APB1_GRP1_DisableClock\n + * APBENR1 TIM2EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 USBEN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 FDACN1EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 USART3EN LL_APB1_GRP1_DisableClock\n (*) + * APBENR1 USART4EN LL_APB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBENR1, Periphs); +} + +/** + * @brief Force APB1 GRP1 peripherals reset. + * @rmtoll APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n + * APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n + * APBRSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n + * APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n + * APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset\n + * APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n + * APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 USBRST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 FDCAN1RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset\n (*) + * APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APBRSTR1, Periphs); +} + +/** + * @brief Release APB1 GRP1 peripherals reset. + * @rmtoll APBRSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n + * APBRSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset\n + * APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n + * APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 FDCAN1RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n (*) + * APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBRSTR1, Periphs); +} + +/** + * @brief Enable APB1 GRP1 peripheral clocks in Sleep and Stop modes + * @rmtoll APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 FDCAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*) + * APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APBSMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APBSMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 GRP1 peripheral clocks in Sleep and Stop modes + * @rmtoll APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 FDCAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*) + * APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBSMENR1, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP2 APB1_GRP2 + * @{ + */ + +/** + * @brief Enable APB1 GRP2 peripherals clock. + * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_EnableClock\n + * APBENR2 TIM1EN LL_APB1_GRP2_EnableClock\n + * APBENR2 SPI1EN LL_APB1_GRP2_EnableClock\n + * APBENR2 USART1EN LL_APB1_GRP2_EnableClock\n + * APBENR2 TIM14EN LL_APB1_GRP2_EnableClock\n + * APBENR2 TIM16EN LL_APB1_GRP2_EnableClock\n + * APBENR2 TIM17EN LL_APB1_GRP2_EnableClock\n + * APBENR2 ADCEN LL_APB1_GRP2_EnableClock\n + * APBENR2 TIM15EN LL_APB1_GRP2_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APBENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APBENR2, Periphs); + (void)tmpreg; +} +#define LL_APB2_GRP1_EnableClock LL_APB1_GRP2_EnableClock + +/** + * @brief Check if APB1 GRP2 peripheral clock is enabled or not + * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 TIM1EN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 SPI1EN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 USART1EN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 TIM14EN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 TIM16EN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 TIM17EN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 ADCEN LL_APB1_GRP2_IsEnabledClock\n + * APBENR2 TIM15EN LL_APB1_GRP2_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL); +} +#define LL_APB2_GRP1_IsEnabledClock LL_APB1_GRP2_IsEnabledClock + +/** + * @brief Disable APB1 GRP2 peripherals clock. + * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_DisableClock\n + * APBENR2 TIM1EN LL_APB1_GRP2_DisableClock\n + * APBENR2 SPI1EN LL_APB1_GRP2_DisableClock\n + * APBENR2 USART1EN LL_APB1_GRP2_DisableClock\n + * APBENR2 TIM14EN LL_APB1_GRP2_DisableClock\n + * APBENR2 TIM16EN LL_APB1_GRP2_DisableClock\n + * APBENR2 TIM17EN LL_APB1_GRP2_DisableClock\n + * APBENR2 ADCEN LL_APB1_GRP2_DisableClock\n + * APBENR2 TIM15EN LL_APB1_GRP2_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBENR2, Periphs); +} +#define LL_APB2_GRP1_DisableClock LL_APB1_GRP2_DisableClock + +/** + * @brief Force APB1 GRP2 peripherals reset. + * @rmtoll APBRSTR2 SYSCFGRST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 TIM1RST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 SPI1RST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 USART1RST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 TIM14RST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 TIM16RST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 TIM17RST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 ADCRST LL_APB1_GRP2_ForceReset\n + * APBRSTR2 TIM15RST LL_APB1_GRP2_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APBRSTR2, Periphs); +} +#define LL_APB2_GRP1_ForceReset LL_APB1_GRP2_ForceReset + +/** + * @brief Release APB1 GRP2 peripherals reset. + * @rmtoll APBRSTR2 SYSCFGRST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 TIM1RST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 SPI1RST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 USART1RST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 TIM14RST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 TIM16RST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 TIM17RST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 ADCRST LL_APB1_GRP2_ReleaseReset\n + * APBRSTR2 TIM15RST LL_APB1_GRP2_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBRSTR2, Periphs); +} +#define LL_APB2_GRP1_ReleaseReset LL_APB1_GRP2_ReleaseReset + +/** + * @brief Enable APB1 GRP2 peripheral clocks in Sleep and Stop modes + * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 TIM1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 SPI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 USART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 TIM14SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 TIM16SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 TIM17SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 ADCSMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APBSMENR2 TIM15SMEN LL_APB1_GRP2_EnableClockStopSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APBSMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APBSMENR2, Periphs); + (void)tmpreg; +} +#define LL_APB2_GRP1_EnableClockStopSleep LL_APB1_GRP2_EnableClockStopSleep + +/** + * @brief Disable APB1 GRP2 peripheral clocks in Sleep and Stop modes + * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 TIM1SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 SPI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 USART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 TIM14SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 TIM16SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 TIM17SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 ADCSMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APBSMENR2 TIM15SMEN LL_APB1_GRP2_DisableClockStopSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBSMENR2, Periphs); +} +#define LL_APB2_GRP1_DisableClockStopSleep LL_APB1_GRP2_DisableClockStopSleep + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_IOP IOP + * @{ + */ + +/** + * @brief Enable IOP peripherals clock. + * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOFEN LL_IOP_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->IOPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->IOPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if IOP peripheral clock is enabled or not + * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable IOP peripherals clock. + * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOFEN LL_IOP_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPENR, Periphs); +} + +/** + * @brief Disable IOP peripherals clock. + * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_ALL + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->IOPRSTR, Periphs); +} + +/** + * @brief Release IOP peripherals reset. + * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_ALL + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPRSTR, Periphs); +} + +/** + * @brief Enable IOP peripheral clocks in Sleep and Stop modes + * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n + * IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n + * IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n + * IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n + * IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->IOPSMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->IOPSMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable IOP peripheral clocks in Sleep and Stop modes + * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n + * IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n + * IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n + * IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n + * IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPSMENR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_BUS_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_cortex.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_cortex.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_cortex.h (revision 41) @@ -0,0 +1,588 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_CORTEX_H +#define STM32C0xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected + as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick + clock source. */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during + hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access + to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI + and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user + program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0+ devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC60 for Cortex-M0+ + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB + * or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB or @ref LL_MPU_REGION_SIZE_32KB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO + * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, + uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_CORTEX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dma.h (revision 41) @@ -0,0 +1,2314 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_DMA_H +#define STM32C0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" +#include "stm32c0xx_ll_dmamux.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), +#if defined(DMA1_Channel4_BASE) + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), +#endif /* DMA1_Channel4_BASE */ +#if defined(DMA1_Channel5_BASE) + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#endif /* DMA1_Channel5_BASE */ +#if defined(DMA1_Channel6_BASE) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /* DMA1_Channel6_BASE */ +#if defined(DMA1_Channel7_BASE) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), +#endif /* DMA1_Channel7_BASE */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to + memory transfer directionis incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to + memory transfer direction is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment + (byte, half word, word)in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment + (byte, half word, word) in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#if defined(DMA1_Channel4) +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#endif /* DMA1_Channel4 */ +#if defined(DMA1_Channel5) +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif /* DMA1_Channel7 */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#if defined(DMA1_Channel4) +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#endif /* DMA1_Channel4 */ +#if defined(DMA1_Channel5) +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif /* DMA1_Channel7 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#if defined(DMA1_Channel4) +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#endif /* DMA1_Channel4 */ +#if defined(DMA1_Channel5) +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#endif /* DMA1_Channel5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#endif /* DMA1_Channel7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function + @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined(LL_DMA_CHANNEL_7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined(LL_DMA_CHANNEL_5) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + LL_DMA_CHANNEL_3) +#endif /* LL_DMA_CHANNEL_7 */ + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined(LL_DMA_CHANNEL_7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#elif defined(LL_DMA_CHANNEL_5) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \ + ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + DMA1_Channel3) +#endif /* LL_DMA_CHANNEL_7 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or + * @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | \ + DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR)); +} + +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX (*) + * @arg @ref LL_DMAMUX_REQ_I2C2_TX (*) + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX (*) + * @arg @ref LL_DMAMUX_REQ_SPI2_TX (*) + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG_COM (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_UP (*) + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + (void)(DMAx); + MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1UL))))->CCR, + DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX (*) + * @arg @ref LL_DMAMUX_REQ_I2C2_TX (*) + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX (*) + * @arg @ref LL_DMAMUX_REQ_SPI2_TX (*) + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG_COM (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_UP (*) + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) + * @note (*) Availability depends on devices + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + (void)(DMAx); + return (READ_BIT(((DMAMUX_Channel_TypeDef *)(((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * \ + (Channel - 1UL)))))->CCR, + DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); +} + +#if defined(DMA_ISR_GIF4) +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_GIF4 */ + +#if defined(DMA_ISR_GIF5) +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_GIF5 */ + +#if defined(DMA_ISR_GIF6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_GIF6 */ + +#if defined(DMA_ISR_GIF7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_GIF7 */ + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +#if defined(DMA_ISR_TCIF4) +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TCIF4 */ + +#if defined(DMA_ISR_TCIF5) +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TCIF5 */ + +#if defined(DMA_ISR_TCIF6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TCIF6 */ + +#if defined(DMA_ISR_TCIF7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TCIF7 */ + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +#if defined(DMA_ISR_HTIF4) +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_HTIF4 */ + +#if defined(DMA_ISR_HTIF5) +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_HTIF5 */ + +#if defined(DMA_ISR_HTIF6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_HTIF6 */ + +#if defined(DMA_ISR_HTIF7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_HTIF7 */ + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +#if defined(DMA_ISR_TEIF4) +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TEIF4 */ + +#if defined(DMA_ISR_TEIF5) +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TEIF5 */ + +#if defined(DMA_ISR_TEIF6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TEIF6 */ + +#if defined(DMA_ISR_TEIF7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} +#endif /* DMA_ISR_TEIF7 */ + +/** + * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +#if defined(DMA_IFCR_CGIF4) +/** + * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} +#endif /* DMA_IFCR_CGIF4 */ + +#if defined(DMA_IFCR_CGIF5) +/** + * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} +#endif /* DMA_IFCR_CGIF5 */ + +#if defined(DMA_IFCR_CGIF6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} +#endif /* DMA_IFCR_CGIF6 */ + +#if defined(DMA_IFCR_CGIF7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} +#endif /* DMA_IFCR_CGIF7 */ + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +#if defined(DMA_IFCR_CTCIF4) +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} +#endif /* DMA_IFCR_CTCIF4 */ + +#if defined(DMA_IFCR_CTCIF5) +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} +#endif /* DMA_IFCR_CTCIF5 */ + +#if defined(DMA_IFCR_CTCIF6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} +#endif /* DMA_IFCR_CTCIF6 */ + +#if defined(DMA_IFCR_CTCIF7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} +#endif /* DMA_IFCR_CTCIF7 */ + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +#if defined(DMA_IFCR_CHTIF4) +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} +#endif /* DMA_IFCR_CHTIF4 */ + +#if defined(DMA_IFCR_CHTIF5) +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} +#endif /* DMA_IFCR_CHTIF5 */ + +#if defined(DMA_IFCR_CHTIF6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} +#endif /* DMA_IFCR_CHTIF6 */ + +#if defined(DMA_IFCR_CHTIF7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} +#endif /* DMA_IFCR_CHTIF7 */ + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +#if defined(DMA_IFCR_CTEIF4) +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} +#endif /* DMA_IFCR_CTEIF4 */ + +#if defined(DMA_IFCR_CTEIF5) +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} +#endif /* DMA_IFCR_CTEIF5 */ + +#if defined(DMA_IFCR_CTEIF6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} +#endif /* DMA_IFCR_CTEIF6 */ + +#if defined(DMA_IFCR_CTEIF7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} +#endif /* DMA_IFCR_CTEIF7 */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_DMA_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h (revision 41) @@ -0,0 +1,1411 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_DMAMUX_H +#define STM32C0xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004UL + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#if defined(DMAMUX1_Channel3) +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#endif /* DMAMUX1_Channel3 */ +#if defined(DMAMUX1_Channel4) +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#endif /* DMAMUX1_Channel4 */ + +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#if defined(DMAMUX1_Channel3) +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#endif /* DMAMUX1_Channel3 */ + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#if defined(DMAMUX1_Channel3) +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#endif /* DMAMUX1_Channel3 */ +#if defined(DMAMUX1_Channel4) +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#endif /* DMAMUX1_Channel4 */ + +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#if defined(DMAMUX1_Channel3) +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#endif /* DMAMUX1_Channel3 */ + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt*/ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */ +#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */ +#define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */ +#if defined(I2C2) +#define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 0x0000000DU /*!< DMAMUX I2C2 TX request */ +#endif /* I2C2 */ +#define LL_DMAMUX_REQ_SPI1_RX 0x00000010U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 0x00000011U /*!< DMAMUX SPI1 TX request */ +#if defined(SPI2) +#define LL_DMAMUX_REQ_SPI2_RX 0x00000012U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 0x00000013U /*!< DMAMUX SPI2 TX request */ +#endif /* SPI2 */ +#define LL_DMAMUX_REQ_TIM1_CH1 0x00000014U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 0x00000015U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 0x00000016U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 0x00000017U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U /*!< DMAMUX TIM1 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM1_UP 0x00000019U /*!< DMAMUX TIM1 UP request */ +#if defined(TIM2) +#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU /*!< DMAMUX TIM2 TRIG request */ +#define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU /*!< DMAMUX TIM2 UP request */ +#endif /* TIM2 */ +#define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */ +#if defined(TIM15) +#define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */ +#define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */ +#endif /* TIM15 */ +#define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_TRIG_COM 0x0000002DU /*!< DMAMUX TIM16 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_TRIG_COM 0x00000030U /*!< DMAMUX TIM17 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM17_UP 0x00000031U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQ_USART1_RX 0x00000032U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 0x00000033U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 0x00000034U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 0x00000035U /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */ +#endif /* USART3 */ +#if defined(USART4) +#define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */ +#define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */ +#endif /* USART4 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#if defined(DMAMUX1_Channel3) +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#endif /* DMAMUX1_Channel3 */ +#if defined(DMAMUX1_Channel4) +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#endif /* DMAMUX1_Channel4 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#endif /* DMAMUX1_Channel6 */ + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event + on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event + on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on + rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line1 4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ +#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from TIM14 OC */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request + generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request + generation on event on rising + edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request + generation on event on falling + edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request + generation on rising and + falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ +#define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from TIM14 OC */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX (*) + * @arg @ref LL_DMAMUX_REQ_I2C2_TX (*) + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX (*) + * @arg @ref LL_DMAMUX_REQ_SPI2_TX (*) + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG_COM (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_UP (*) + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX (*) + * @arg @ref LL_DMAMUX_REQ_I2C2_TX (*) + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX (*) + * @arg @ref LL_DMAMUX_REQ_SPI2_TX (*) + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG_COM (*) + * @arg @ref LL_DMAMUX_REQ_TIM2_UP (*) + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART3_TX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_RX (*) + * @arg @ref LL_DMAMUX_REQ_USART4_TX (*) + * @note (*) Availability depends on devices + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA + request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, + uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA + request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, + uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 (*) + * @arg @ref LL_DMAMUX_SYNC_TIM14_OC + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 (*) + * @arg @ref LL_DMAMUX_SYNC_TIM14_OC + * @note (*) Availability depends on devices + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, + uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, + DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, + uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * \ + (RequestGenChannel)))))->RGCR, + DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, + (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * \ + (RequestGenChannel)))))->RGCR, + DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (*) + * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestSignalID) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, + RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (*) + * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC + * @note (*) Availability depends on devices + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * \ + (RequestGenChannel)))))->RGCR, + DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);; +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);; +} + +#if defined(DMAMUX_CSR_SOF3) +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);; +} +#endif /* DMAMUX_CSR_SOF3 */ + +#if defined(DMAMUX_CSR_SOF4) +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);; +} +#endif /* DMAMUX_CSR_SOF4 */ + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);; +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);; +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);; +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);; +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +#if defined(DMAMUX_CFR_CSOF3) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} +#endif /* DMAMUX_CFR_CSOF3 */ + +#if defined(DMAMUX_CFR_CSOF4) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} +#endif /* DMAMUX_CFR_CSOF4 */ + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 (*) + * @arg @ref LL_DMAMUX_CHANNEL_4 (*) + * @arg @ref LL_DMAMUX_CHANNEL_5 (*) + * @arg @ref LL_DMAMUX_CHANNEL_6 (*) + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? \ + 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_DMAMUX_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_exti.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_exti.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_exti.h (revision 41) @@ -0,0 +1,1370 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_EXTI_H +#define STM32C0xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16u /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#if defined(EXTI_IMR2_IM36) + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#endif /* LL_EXTI_LINE_36 */ + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 0xFFFFFFFFU /*!< All Extended line */ +#if defined(EXTI_IMR2_IM34) +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif /* EXTI_IMR2_IM34 */ +#if defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif /* EXTI_IMR2_IM36 */ +#define LL_EXTI_LINE_ALL_32_63 0x00000014U /*!< only line 34 & line 36 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT + * @{ + */ +#define LL_EXTI_CONFIG_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#if defined(GPIOD_BASE) +#define LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#endif /*GPIOD_BASE*/ +#define LL_EXTI_CONFIG_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE + * @{ + */ +#define LL_EXTI_CONFIG_LINE0 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE1 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE2 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE3 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE4 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE5 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE6 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE7 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE8 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE9 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE10 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE11 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE12 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE13 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE14 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE15 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_36) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_36 */ + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_36) +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_36 */ + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(LL_EXTI_LINE_36) +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* LL_EXTI_LINE_36 */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +#if defined(LL_EXTI_LINE_36) +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_36 */ + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_36) +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_36 */ + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(LL_EXTI_LINE_36) +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* LL_EXTI_LINE_36 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FPR1, ExtiLine)); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR2, ExtiLine)); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Clear ExtLine Falling Flags for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RPR1, ExtiLine)); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RPR2, ExtiLine)); +} +#endif /* LL_EXTI_LINE_34 */ + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR1, ExtiLine); +} + +#if defined(LL_EXTI_LINE_34) +/** + * @brief Clear ExtLine Rising Flags for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR2, ExtiLine); +} +#endif /* LL_EXTI_LINE_34 */ +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref EXTI_LL_EC_CONFIG_PORT + * + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @arg @ref LL_EXTI_CONFIG_LINE9 + * @arg @ref LL_EXTI_CONFIG_LINE10 + * @arg @ref LL_EXTI_CONFIG_LINE11 + * @arg @ref LL_EXTI_CONFIG_LINE12 + * @arg @ref LL_EXTI_CONFIG_LINE13 + * @arg @ref LL_EXTI_CONFIG_LINE14 + * @arg @ref LL_EXTI_CONFIG_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(EXTI->EXTICR[Line & 0x03u], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << \ + (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @arg @ref LL_EXTI_CONFIG_LINE9 + * @arg @ref LL_EXTI_CONFIG_LINE10 + * @arg @ref LL_EXTI_CONFIG_LINE11 + * @arg @ref LL_EXTI_CONFIG_LINE12 + * @arg @ref LL_EXTI_CONFIG_LINE13 + * @arg @ref LL_EXTI_CONFIG_LINE14 + * @arg @ref LL_EXTI_CONFIG_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref EXTI_LL_EC_CONFIG_PORT + * + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> \ + (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_EXTI_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_gpio.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_gpio.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_gpio.h (revision 41) @@ -0,0 +1,986 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_GPIO_H +#define STM32C0xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / + ((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_GPIO_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_iwdg.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_iwdg.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_iwdg.h (revision 41) @@ -0,0 +1,338 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_IWDG_H +#define STM32C0xx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined(IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ +#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->RLR)); +} + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @rmtoll WINR WIN LL_IWDG_SetWindow + * @param IWDGx IWDG Instance + * @param Window Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) +{ + WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); +} + +/** + * @brief Get the high limit of the window value specified. + * @rmtoll WINR WIN LL_IWDG_GetWindow + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->WINR)); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Window Value Update is set or not + * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_IWDG_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_pwr.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_pwr.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_pwr.h (revision 41) @@ -0,0 +1,1090 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_PWR_H +#define STM32C0xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_SCR_CSBF PWR_SCR_CSBF +#define LL_PWR_SCR_CWUF PWR_SCR_CWUF +#define LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6 +#if defined(PWR_SCR_CWUF5) +#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 +#endif /* PWR_SCR_CWUF5 */ +#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 +#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 +#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 +#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_SR1_WUFI PWR_SR1_WUFI +#define LL_PWR_SR1_SBF PWR_SR1_SBF +#define LL_PWR_SR1_WUF6 PWR_SR1_WUF6 +#if defined(PWR_SR1_WUF5) +#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 +#endif /* PWR_SR1_WUF5 */ +#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 +#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 +#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 +#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR + * @{ + */ +#define LL_PWR_MODE_STOP0 (0x00000000UL) +#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) +#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) +/** + * @} + */ + +#if defined(PWR_PVM_SUPPORT) +/** @defgroup PWR_LL_EC_PVM_IP PVM_IP + * @{ + */ +#define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: + Enable to keep the USB peripheral voltage monitoring + under control (power domain Vddio2) */ +/** + * @} + */ +#endif /* PWR_PVM_SUPPORT */ + +/** @defgroup PWR_LL_EC_WAKEUP WAKEUP + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) +#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) +#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) +#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) +#if defined(PWR_CR3_EWUP5) +#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) +#endif /* PWR_CR3_EWUP5 */ +#define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO GPIO + * @{ + */ +#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) +#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) +#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) +#if defined(GPIOD) +#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) +#endif /* GPIOD */ +#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT + * @{ + */ +#define LL_PWR_GPIO_BIT_0 0x00000001U +#define LL_PWR_GPIO_BIT_1 0x00000002U +#define LL_PWR_GPIO_BIT_2 0x00000004U +#define LL_PWR_GPIO_BIT_3 0x00000008U +#define LL_PWR_GPIO_BIT_4 0x00000010U +#define LL_PWR_GPIO_BIT_5 0x00000020U +#define LL_PWR_GPIO_BIT_6 0x00000040U +#define LL_PWR_GPIO_BIT_7 0x00000080U +#define LL_PWR_GPIO_BIT_8 0x00000100U +#define LL_PWR_GPIO_BIT_9 0x00000200U +#define LL_PWR_GPIO_BIT_10 0x00000400U +#define LL_PWR_GPIO_BIT_11 0x00000800U +#define LL_PWR_GPIO_BIT_12 0x00001000U +#define LL_PWR_GPIO_BIT_13 0x00002000U +#define LL_PWR_GPIO_BIT_14 0x00004000U +#define LL_PWR_GPIO_BIT_15 0x00008000U +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BKP BACKUP + * @{ + */ +#define LL_PWR_BKP_NUMBER 4U +#define LL_PWR_BKP_DR0 0U +#define LL_PWR_BKP_DR1 1U +#define LL_PWR_BKP_DR2 2U +#define LL_PWR_BKP_DR3 3U + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Flash Power-down mode during sleep mode + * @rmtoll CR1 FPD_SLP LL_PWR_EnableFlashPowerDownInSleep + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInSleep(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FPD_SLP); +} + +/** + * @brief Disable Flash Power-down mode during sleep mode + * @rmtoll CR1 FPD_SLP LL_PWR_DisableFlashPowerDownInSleep + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInSleep(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_SLP); +} + +/** + * @brief Check if flash power-down mode during sleep mode domain is enabled + * @rmtoll CR1 FPD_SLP LL_PWR_IsEnableFlashPowerDownInSleep + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInSleep(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_SLP) == (PWR_CR1_FPD_SLP)) ? 1UL : 0UL); +} + +/** + * @brief Enable Flash Power-down mode during stop mode + * @rmtoll CR1 FPD_STOP LL_PWR_EnableFlashPowerDownInStop + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP); +} + +/** + * @brief Disable Flash Power-down mode during stop mode + * @rmtoll CR1 FPD_STOP LL_PWR_DisableFlashPowerDownInStop + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP); +} + +/** + * @brief Check if flash power-down mode during stop mode domain is enabled + * @rmtoll CR1 FPD_STOP LL_PWR_IsEnableFlashPowerDownInStop + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL); +} + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Enable VDDIO2 supply + * @rmtoll CR2 PVM_VDDIO2 LL_PWR_EnableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1); +} + +/** + * @brief Disable VDDIO2 supply + * @rmtoll CR2 PVM_VDDIO2 LL_PWR_DisableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1); +} + +/** + * @brief Check if VDDIO2 supply is enabled + * @rmtoll CR2 PVM_VDDIO2 LL_PWR_IsEnabledVddIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1) == (PWR_CR2_PVM_VDDIO2_1)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Power Voltage Monitoring on a peripheral + * @rmtoll CR2 PVMUSB LL_PWR_EnablePVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_USB (*) + * + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) +{ + SET_BIT(PWR->CR2, PeriphVoltage); +} + +/** + * @brief Disable the Power Voltage Monitoring on a peripheral + * @rmtoll CR2 PVMUSB LL_PWR_DisablePVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_USB (*) + * + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) +{ + CLEAR_BIT(PWR->CR2, PeriphVoltage); +} + +/** + * @brief Check if Power Voltage Monitoring is enabled on a peripheral + * @rmtoll CR2 PVMUSB LL_PWR_IsEnabledPVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_USB (*) + + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) +{ + return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); +} +#endif /* PWR_PVM_SUPPORT */ + +/** + * @brief Set Low-Power mode + * @rmtoll CR1 LPMS LL_PWR_SetPowerMode + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); +} + +/** + * @brief Get Low-Power mode + * @rmtoll CR1 LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); +} + +/** + * @brief Enable Internal Wake-up line + * @rmtoll CR3 EIWF LL_PWR_EnableInternWU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableInternWU(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Disable Internal Wake-up line + * @rmtoll CR3 EIWF LL_PWR_DisableInternWU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableInternWU(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Check if Internal Wake-up line is enabled + * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); +} + +/** + * @brief Enable pull-up and pull-down configuration + * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration + * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Check if pull-up and pull-down configuration is enabled + * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP5 LL_PWR_EnableWakeUpPin (*)\n + * CR3 EWUP6 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR3, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP5 LL_PWR_DisableWakeUpPin (*)\n + * CR3 EWUP6 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR3, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin (*)\n + * CR3 EWUP6 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow (*)\n + * CR4 WP6 LL_PWR_SetWakeUpPinPolarityLow\n + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR4, WakeUpPin); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh (*)\n + * CR4 WP6 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR4, WakeUpPin); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow (*)\n + * CR4 WP6 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes + * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp (*)\n + * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp + * @note (*) Port D availability depends on devices + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D (*) + * @arg @ref LL_PWR_GPIO_F + * @note (*) Port D availability depends on devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); +} + +/** + * @brief Disable GPIO pull-up state in Standby and Shutdown modes + * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp (*)\n + * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp + * @note (*) Port D availability depends on devices + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D (*) + * @arg @ref LL_PWR_GPIO_F + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); +} + +/** + * @brief Check if GPIO pull-up state is enabled + * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp (*)\n + * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp + * @note (*) Port D availability depends on devices + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D (*) + * @arg @ref LL_PWR_GPIO_F + * @note (*) Port D availability depends on devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes + * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown (*)\n + * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown + * @note (*) Port D availability depends on devices + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D (*) + * @arg @ref LL_PWR_GPIO_F + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); +} + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes + * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown (*)\n + * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown + * @note (*) Port D availability depends on devices + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D (*) + * @note (*) Port D availability depends on devices + * @arg @ref LL_PWR_GPIO_F + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); +} + +/** + * @brief Check if GPIO pull-down state is enabled + * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown (*)\n + * @note (*) Port D availability depends on devices + * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D (*) + * @arg @ref LL_PWR_GPIO_F + * @note (*) Port D availability depends on devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_SetRegister + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_PWR_BKP_DR0 + * @arg @ref LL_PWR_BKP_DR1 + * @arg @ref LL_PWR_BKP_DR2 + * @arg @ref LL_PWR_BKP_DR3 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_PWR_BKP_SetRegister(uint32_t BackupRegister, uint16_t Data) +{ + __IO uint32_t tmp; + + tmp = (uint32_t)(&(PWR->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint16_t)Data; +} + +/** + * @brief Reads data from the specified Backup data Register. + * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_GetRegister + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_PWR_BKP_DR0 + * @arg @ref LL_PWR_BKP_DR1 + * @arg @ref LL_PWR_BKP_DR2 + * @arg @ref LL_PWR_BKP_DR3 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_PWR_BKP_GetRegister(uint32_t BackupRegister) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(PWR->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Wake-up line Flag + * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); +} + +/** + * @brief Get Standby Flag + * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 6 + * @rmtoll SR1 WUF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL); +} + +#if defined(PWR_CR3_EWUP5) +/** + * @brief Get Wake-up Flag 5 + * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); +} +#endif /* PWR_CR3_EWUP5 */ + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); +} + +/** + * @brief Clear Standby Flag + * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF); +} + +/** + * @brief Clear Wake-up Flag 6 + * @rmtoll SCR CWUF6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF6); +} + +#if defined(PWR_CR3_EWUP5) +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); +} +#endif /* PWR_CR3_EWUP5 */ + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); +} + +#if defined (PWR_PVM_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below or above the selected PVD + * threshold + * @rmtoll SR2 PVDMO_USB LL_PWR_IsActiveFlag_PVMOUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_VDDIO2) == (PWR_SR2_PVMO_VDDIO2)) ? 1UL : 0UL); +} +#endif /* PWR_PVM_SUPPORT */ + +/** + * @brief Indicate whether or not the flash is ready to be accessed + * @rmtoll SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_PWR_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h (revision 41) @@ -0,0 +1,2136 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_RCC_H +#define STM32C0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 48000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if defined(RCC_HSI48_SUPPORT) +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CICR_HSI48CSSC RCC_CICR_HSIUSB48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSIUSB48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR2_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR2_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR2_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR2_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR2_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR2_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_PWRRSTF RCC_CSR2_PWRRSTF /*!< BOR or POR/PDR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_CSR1_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_HSIUSB48 RCC_CFGR_SW_1 /*!< HSIUSB48 selection used as system clock */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSIUSB48 RCC_CFGR_SWS_1 /*!< HSIUSB48 used as system clock */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#if defined(RCC_CR_SYSDIV) +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CR_SYSDIV_0 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_3 RCC_CR_SYSDIV_1 /*!< SYSCLK divided by 3 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_5 RCC_CR_SYSDIV_2 /*!< SYSCLK divided by 5 */ +#define LL_RCC_SYSCLK_DIV_6 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_0) /*!< SYSCLK divided by 6 */ +#define LL_RCC_SYSCLK_DIV_7 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1) /*!< SYSCLK divided by 7 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK divided by 8 */ +#else +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#endif /* RCC_CR_SYSDIV */ +/** + * @} + */ + +/** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source + * @{ + */ +#define LL_RCC_HCLK_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_HCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< HCLK divided by 2 */ +#define LL_RCC_HCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 4 */ +#define LL_RCC_HCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 8 */ +#define LL_RCC_HCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 16 */ +#define LL_RCC_HCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< HCLK divided by 64 */ +#define LL_RCC_HCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 128 */ +#define LL_RCC_HCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 256 */ +#define LL_RCC_HCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSI_DIV HSI division factor + * @{ + */ +#define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */ +#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */ +#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */ +#define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */ +#define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */ +#define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */ +#define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */ +#define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIKER_DIV HSI Kernel division factor + * @{ + */ +#define LL_RCC_HSIKER_DIV_1 0x00000000U /*!< HSI kernel not divided */ +#define LL_RCC_HSIKER_DIV_2 RCC_CR_HSIKERDIV_0 /*!< HSI kernel divided by 2 */ +#define LL_RCC_HSIKER_DIV_3 RCC_CR_HSIKERDIV_1 /*!< HSI kernel divided by 3 */ +#define LL_RCC_HSIKER_DIV_4 (RCC_CR_HSIKERDIV_1 | RCC_CR_HSIKERDIV_0) /*!< HSI kernel divided by 4 */ +#define LL_RCC_HSIKER_DIV_5 RCC_CR_HSIKERDIV_2 /*!< HSI kernel divided by 5 */ +#define LL_RCC_HSIKER_DIV_6 (RCC_CR_HSIKERDIV_2 | RCC_CR_HSIKERDIV_0) /*!< HSI kernel divided by 6 */ +#define LL_RCC_HSIKER_DIV_7 (RCC_CR_HSIKERDIV_2 | RCC_CR_HSIKERDIV_1) /*!< HSI kernel divided by 7 */ +#define LL_RCC_HSIKER_DIV_8 RCC_CR_HSIKERDIV /*!< HSI kernel divided by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO1SOURCE_HSIUSB48 RCC_CFGR_MCOSEL_3 /*!< HSIUSB48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */ +#define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */ +#define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */ +#define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */ +#if defined(RCC_CFGR_MCOPRE_3) +#define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO1 divided by 256 */ +#define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 512 */ +#define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 1024 */ +#endif /* RCC_CFGR_MCOPRE_3 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection + * @{ + */ +#define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ +#define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0| RCC_CFGR_MCO2SEL_1) /*!< HSI16 selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO2SOURCE_HSIUSB48 RCC_CFGR_MCO2SEL_3 /*!< HSIUSB48 selection as MCO2 source */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler + * @{ + */ +#define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */ +#define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */ +#define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */ +#define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */ +#define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */ +#if defined(RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO1 divided by 256 */ +#define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO1 divided by 512 */ +#define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO1 divided by 1024 */ +#endif /* RCC_CFGR_MCO2PRE_3 */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSIKER ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSIKER clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ + +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSIKER clock used as I2C1 clock source */ +#if defined(I2C2) +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSIKER clock used as I2C2 clock source */ +#endif /* I2C2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_HSIKER RCC_CCIPR_I2S1SEL_1 /*!< HSIKER clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_HSIKER RCC_CCIPR_ADCSEL_1 /*!< HSIKER kernel used as ADC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */ +#if defined(I2C2) +#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C2 Clock source selection */ +#endif /* I2C2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_CSR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ +#if defined(USB_DRD_FS) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL /*!< HSE clock used as USB clock source */ +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */ +/** + * @} + */ + +/** + * @} + */ +#endif /* USB_DRD_FS */ + +#if defined(FDCAN1) +/** @defgroup RCC_LL_EC_FDCAN1_CLKSOURCE Peripheral FDCAN1 clock source selection + * @{ + */ +#define LL_RCC_FDCAN1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FDCAN1 clock source */ +#define LL_RCC_FDCAN1_CLKSOURCE_HSIKER RCC_CCIPR_FDCAN1SEL_0 /*!< HSIKER clock used as FDCAN1 clock source */ +#define LL_RCC_FDCAN1_CLKSOURCE_HSE RCC_CCIPR_FDCAN1SEL_1 /*!< HSE clock used as FDCAN1 clock source */ +/** @defgroup RCC_LL_EC_FDCAN1 Peripheral FDCAN1 get clock source + * @{ + */ +#define LL_RCC_FDCAN1_CLKSOURCE RCC_CCIPR_FDCAN1SEL /*!< FDCAN1 Clock source selection */ +/** + * @} + */ + +/** + * @} + */ +#endif /* FDCAN1 */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/LSE/LSI) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HCLK_DIV_1 + * @arg @ref LL_RCC_HCLK_DIV_2 + * @arg @ref LL_RCC_HCLK_DIV_4 + * @arg @ref LL_RCC_HCLK_DIV_8 + * @arg @ref LL_RCC_HCLK_DIV_16 + * @arg @ref LL_RCC_HCLK_DIV_64 + * @arg @ref LL_RCC_HCLK_DIV_128 + * @arg @ref LL_RCC_HCLK_DIV_256 + * @arg @ref LL_RCC_HCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \ + ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__)\ + & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (APB1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ + ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]\ + & 0x1FU)) + +/** + * @brief Helper macro to calculate the HSISYS frequency + * @param __HSIDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval HSISYS clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))) + +/** + * @brief Helper macro to calculate the HSI Kernel frequency + * @param __HSIKERDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HSIKER_DIV_1 + * @arg @ref LL_RCC_HSIKER_DIV_2 + * @arg @ref LL_RCC_HSIKER_DIV_3 + * @arg @ref LL_RCC_HSIKER_DIV_4 + * @arg @ref LL_RCC_HSIKER_DIV_5 + * @arg @ref LL_RCC_HSIKER_DIV_6 + * @arg @ref LL_RCC_HSIKER_DIV_7 + * @arg @ref LL_RCC_HSIKER_DIV_8 + * @retval HSIKER clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HSIKER_FREQ(__HSIKERDIV__) (HSI_VALUE / (((__HSIKERDIV__)>> RCC_CR_HSIKERDIV_Pos) +1U)) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI in stop mode is enabled + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL); +} + +/** + * @brief Set HSIKER divider + * @rmtoll CR HSIKERDIV LL_RCC_HSIKER_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSIKER_DIV_1 + * @arg @ref LL_RCC_HSIKER_DIV_2 + * @arg @ref LL_RCC_HSIKER_DIV_3 + * @arg @ref LL_RCC_HSIKER_DIV_4 + * @arg @ref LL_RCC_HSIKER_DIV_5 + * @arg @ref LL_RCC_HSIKER_DIV_6 + * @arg @ref LL_RCC_HSIKER_DIV_7 + * @arg @ref LL_RCC_HSIKER_DIV_8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSIKER_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, Divider); +} + +/** + * @brief Get HSIKER divider + * @rmtoll CR HSIKERDIV LL_RCC_HSIKER_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSIKER_DIV_1 + * @arg @ref LL_RCC_HSIKER_DIV_2 + * @arg @ref LL_RCC_HSIKER_DIV_3 + * @arg @ref LL_RCC_HSIKER_DIV_4 + * @arg @ref LL_RCC_HSIKER_DIV_5 + * @arg @ref LL_RCC_HSIKER_DIV_6 + * @arg @ref LL_RCC_HSIKER_DIV_7 + * @arg @ref LL_RCC_HSIKER_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSIKER_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIKERDIV)); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + + +/** + * @brief Set HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 127 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIUSB48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIUSB48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIUSB48RDY) == RCC_CR_HSIUSB48RDY) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll CSR1 LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll CSR1 LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll CSR1 LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll CSR1 LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll CSR1 LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll CSR1 LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll CSR1 LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll CSR1 LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll CSR1 LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == (RCC_CSR1_LSERDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll CSR1 LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSECSSD) == (RCC_CSR1_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR2 LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR2, RCC_CSR2_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR2 LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR2 LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == (RCC_CSR2_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll CSR1 LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll CSR1 LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll CSR1 LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->CSR1, RCC_CSR1_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll CSR1 LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSIUSB48 (*) + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSIUSB48 (*) + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE + * @note (*) peripheral not available on all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +#if defined(RCC_CR_SYSDIV) +/** + * @brief Set SYS DIV + * @rmtoll CR SYSDIV LL_RCC_SetSYSDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_7 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSYSDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, Divider); +} +#endif /* RCC_CR_SYSDIV */ + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_HCLK_DIV_1 + * @arg @ref LL_RCC_HCLK_DIV_2 + * @arg @ref LL_RCC_HCLK_DIV_4 + * @arg @ref LL_RCC_HCLK_DIV_8 + * @arg @ref LL_RCC_HCLK_DIV_16 + * @arg @ref LL_RCC_HCLK_DIV_64 + * @arg @ref LL_RCC_HCLK_DIV_128 + * @arg @ref LL_RCC_HCLK_DIV_256 + * @arg @ref LL_RCC_HCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Set HSI48 division factor + * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @param HSIDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv); +} + +/** + * @brief Set HSIKER division factor + * @rmtoll CR HSIKERDIV LL_RCC_SetHSIKERDiv + * @param HSIKERDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_HSIKER_DIV_1 + * @arg @ref LL_RCC_HSIKER_DIV_2 + * @arg @ref LL_RCC_HSIKER_DIV_3 + * @arg @ref LL_RCC_HSIKER_DIV_4 + * @arg @ref LL_RCC_HSIKER_DIV_5 + * @arg @ref LL_RCC_HSIKER_DIV_6 + * @arg @ref LL_RCC_HSIKER_DIV_7 + * @arg @ref LL_RCC_HSIKER_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSIKERDiv(uint32_t HSIKERDiv) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, HSIKERDiv); +} + +#if defined(RCC_CR_SYSDIV) +/** + * @brief Get SYS divider + * @rmtoll CR SYSDIV LL_RCC_GetSYSDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_7 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSYSDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_SYSDIV)); +} +#endif /* RCC_CR_SYSDIV */ + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HCLK_DIV_1 + * @arg @ref LL_RCC_HCLK_DIV_2 + * @arg @ref LL_RCC_HCLK_DIV_4 + * @arg @ref LL_RCC_HCLK_DIV_8 + * @arg @ref LL_RCC_HCLK_DIV_16 + * @arg @ref LL_RCC_HCLK_DIV_64 + * @arg @ref LL_RCC_HCLK_DIV_128 + * @arg @ref LL_RCC_HCLK_DIV_256 + * @arg @ref LL_RCC_HCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @brief Get HSI48 Division factor + * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSIUSB48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @arg @ref LL_RCC_MCO1_DIV_32 + * @arg @ref LL_RCC_MCO1_DIV_64 + * @arg @ref LL_RCC_MCO1_DIV_128 + * @arg @ref LL_RCC_MCO1_DIV_256 (*) + * @arg @ref LL_RCC_MCO1_DIV_512 (*) + * @arg @ref LL_RCC_MCO1_DIV_1024 (*) + * @note (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO2 MCO2 + * @{ + */ + +/** + * @brief Configure MCO2 + * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n + * CFGR MCO2PRE LL_RCC_ConfigMCO2 + * @note feature not available in all devices. + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSI + * @arg @ref LL_RCC_MCO2SOURCE_HSIUSB48 (*) + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @arg @ref LL_RCC_MCO2SOURCE_LSE + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_16 + * @arg @ref LL_RCC_MCO2_DIV_32 + * @arg @ref LL_RCC_MCO2_DIV_64 + * @arg @ref LL_RCC_MCO2_DIV_128 + * @arg @ref LL_RCC_MCO2_DIV_256 (*) + * @arg @ref LL_RCC_MCO2_DIV_512 (*) + * @arg @ref LL_RCC_MCO2_DIV_1024 (*) + * @note (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIKER + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIKER + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, I2CxSource); +} + +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSIKER + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); +} + +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSIKER + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource); +} + +#if defined (USB_DRD_FS) +/** + * @brief Configure USB clock source + * @rmtoll CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_HSE + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource); +} +#endif /* USB_DRD_FS */ + +#if defined(FDCAN1) +/** + * @brief Configure FDCANx clock source + * @rmtoll CCIPR FDCAN1SEL LL_RCC_SetFDCANClockSource + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSIKER + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCAN1SEL, FDCANxSource); +} +#endif /* FDCAN1 */ + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIKER + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIKER + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx)); +} + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSIKER + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +} + +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR I2S LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSIKER + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); +} + +#if defined (USB_DRD_FS) +/** + * @brief Get USBx clock source + * @rmtoll CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx)); +} +#endif /* USB_DRD_FS */ + +#if defined(FDCAN1) +/** + * @brief Get FDCANx clock source + * @rmtoll CCIPR FDCAN LL_RCC_GetFDCANClockSource + * @param FDCANx This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN1_CLKSOURCE_HSIKER + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx)); +} +#endif /* FDCAN1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll CSR1 RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CSR1, RCC_CSR1_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll CSR1 RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll CSR1 RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll CSR1 RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll CSR1 RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->CSR1, RCC_CSR1_RTCEN) == (RCC_CSR1_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll CSR1 RTCRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll CSR1 RTCRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIUSB48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIUSB48RDYF) == (RCC_CIFR_HSIUSB48RDYF)) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR2 IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_IWDGRSTF) == (RCC_CSR2_IWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR2 LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_LPWRRSTF) == (RCC_CSR2_LPWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Option byte reset is set or not. + * @rmtoll CSR2 OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_OBLRSTF) == (RCC_CSR2_OBLRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR2 PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_PINRSTF) == (RCC_CSR2_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR2 SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_SFTRSTF) == (RCC_CSR2_SFTRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR2 WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_WWDGRSTF) == (RCC_CSR2_WWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR or POR/PDR reset is set or not. + * @rmtoll CSR2 PWRRSTF LL_RCC_IsActiveFlag_PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void) +{ + return ((READ_BIT(RCC->CSR2, RCC_CSR2_PWRRSTF) == (RCC_CSR2_PWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR2 RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR2, RCC_CSR2_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIUSB48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIUSB48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIUSB48RDYIE) == (RCC_CIER_HSIUSB48RDYIE)) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +uint32_t LL_RCC_GetRTCClockFreq(void); +#if defined(USB_DRD_FS) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_DRD_FS */ +#if defined(FDCAN1) +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +#endif /* FDCAN1 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_RCC_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h (revision 41) @@ -0,0 +1,1540 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_SYSTEM_H +#define STM32C0xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBG) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP + * @{ + */ +#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP + * @{ + */ +#define LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves as PA9 pin */ +#define LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves as PA10 pin */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation + * @{ + */ +#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IRDA Modulation envelope source */ +#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IRDA Modulation envelope source */ +#define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IRDA Modulation envelope source */ + +/** + * @} + */ +/** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity + * @{ + */ +#define LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U /*!< 0: Output of IRDA (IROut) not inverted */ +#define LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL) /*!< 1: Output of IRDA (IROut) inverted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_BOOSTEN SYSCFG I/O analog switch voltage booster enable + * @{ + */ +#define LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN /*!< I/O analog switch voltage booster enable */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable I2C1 Fast mode Plus */ +#if defined(I2C2) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable I2C2 Fast mode Plus */ +#endif /* I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast Mode Plus on PC14 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of + CortexM0 with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(TIM2) +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#endif /* TIM2 */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBG_APB_FZ2_DBG_TIM14_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ +#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ + +/* defines for legacy purpose */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP LL_DBGMCU_APB1_GRP2_TIM1_STOP +#define LL_DBGMCU_APB2_GRP1_TIM14_STOP LL_DBGMCU_APB1_GRP2_TIM14_STOP +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP LL_DBGMCU_APB1_GRP2_TIM16_STOP +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP LL_DBGMCU_APB1_GRP2_TIM17_STOP +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_PINMUX_CFG PINMUX Config + * @{ + */ +#if (DEV_ID == 0x443UL) +#define LL_PINMUX_SO8_PIN1_PB7 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */ +#define LL_PINMUX_SO8_PIN1_PC14 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */ +#define LL_PINMUX_SO8_PIN4_PF2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */ +#define LL_PINMUX_SO8_PIN4_PA0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */ +#define LL_PINMUX_SO8_PIN4_PA1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */ +#define LL_PINMUX_SO8_PIN4_PA2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */ +#define LL_PINMUX_SO8_PIN5_PA8 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8 */ +#define LL_PINMUX_SO8_PIN5_PA11 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */ +#define LL_PINMUX_SO8_PIN8_PA14 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */ +#define LL_PINMUX_SO8_PIN8_PB6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */ +#define LL_PINMUX_SO8_PIN8_PC15 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */ +#define LL_PINMUX_WLCSP12_PINE2_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */ +#define LL_PINMUX_WLCSP12_PINE2_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12 */ +#define LL_PINMUX_WLCSP12_PINF1_PA3 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3*/ +#define LL_PINMUX_WLCSP12_PINF1_PA4 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */ +#define LL_PINMUX_WLCSP12_PINF1_PA5 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */ +#define LL_PINMUX_WLCSP12_PINF1_PA6 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */ + +#elif (DEV_ID == 0x453UL) +#define LL_PINMUX_WLCSP14_PINF2_PA1 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */ +#define LL_PINMUX_WLCSP14_PINF2_PA2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */ +#define LL_PINMUX_WLCSP14_PING3_PF2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */ +#define LL_PINMUX_WLCSP14_PING3_PA0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */ +#define LL_PINMUX_WLCSP14_PINJ1_PA8 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */ +#define LL_PINMUX_WLCSP14_PINJ1_PA11 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */ +#define LL_PINMUX_WLCSP14_PINH2_PA5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */ +#define LL_PINMUX_WLCSP14_PINH2_PA6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */ +#define LL_PINMUX_WLCSP14_PING1_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */ +#define LL_PINMUX_WLCSP14_PING1_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */ +#define LL_PINMUX_WLCSP14_PINJ3_PA3 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */ +#define LL_PINMUX_WLCSP14_PINJ3_PA4 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */ + +#elif (DEV_ID == 0x493UL) +#define LL_PINMUX_WLCSP19_PINH3_PF2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PF2 */ +#define LL_PINMUX_WLCSP19_PINH3_PA0 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PA0 */ +#define LL_PINMUX_WLCSP19_PINB1_PA14 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA14 */ +#define LL_PINMUX_WLCSP19_PINB1_PA15 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA15 */ +#define LL_PINMUX_TSSOP20_PIN19_PA14 LL_PINMUX_WLCSP19_PINB1_PA14 +#define LL_PINMUX_TSSOP20_PIN19_PA15 LL_PINMUX_WLCSP19_PINB1_PA15 +#define LL_PINMUX_TSSOP20_PIN20_PB6 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB6 */ +#define LL_PINMUX_TSSOP20_PIN20_PB3 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB3 */ +#define LL_PINMUX_TSSOP20_PIN20_PB4 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB4 */ +#define LL_PINMUX_TSSOP20_PIN20_PB5 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB5 */ +#define LL_PINMUX_WLCSP19_PINB3_PB7 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB7 */ +#define LL_PINMUX_WLCSP19_PINB3_PB8 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */ +#define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP19_PINB3_PB7 +#define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP19_PINB3_PB8 + +#elif (DEV_ID == 0x44CUL) +#define LL_PINMUX_WLCSP15_PINH3_PF2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PF2 */ +#define LL_PINMUX_WLCSP15_PINH3_PA0 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PA0 */ +#define LL_PINMUX_WLCSP15_PING2_PA1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA1 */ +#define LL_PINMUX_WLCSP15_PING2_PA2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA2 */ +#define LL_PINMUX_WLCSP15_PINK3_PA3 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA3 */ +#define LL_PINMUX_WLCSP15_PINK3_PA4 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA4 */ +#define LL_PINMUX_WLCSP15_PINJ2_PA5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA5 */ +#define LL_PINMUX_WLCSP15_PINJ2_PA6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA6 */ +#define LL_PINMUX_WLCSP15_PINH1_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA7 */ +#define LL_PINMUX_WLCSP15_PINH1_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA12 */ +#define LL_PINMUX_WLCSP15_PINE2_PA14 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA14 */ +#define LL_PINMUX_WLCSP15_PINE2_PA15 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA15 */ +#define LL_PINMUX_WLCSP15_PINB1_PA3 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA3 */ +#define LL_PINMUX_WLCSP15_PINB1_PA4 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX6_0) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA4 */ +#define LL_PINMUX_WLCSP15_PINB1_PA5 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX6_1) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA5 */ +#define LL_PINMUX_WLCSP15_PINB1_PA6 (((SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX6_1 | SYSCFG_CFGR3_PINMUX6_0) /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA6 */ +#define LL_PINMUX_TSSOP20_PIN20_PA3 LL_PINMUX_WLCSP15_PINB1_PA3 +#define LL_PINMUX_TSSOP20_PIN20_PA4 LL_PINMUX_WLCSP15_PINB1_PA4 +#define LL_PINMUX_TSSOP20_PIN20_PA5 LL_PINMUX_WLCSP15_PINB1_PA5 +#define LL_PINMUX_TSSOP20_PIN20_PA6 LL_PINMUX_WLCSP15_PINB1_PA6 +#define LL_PINMUX_WLCSP15_PINA2_PB7 (((SYSCFG_CFGR3_PINMUX7_0 | SYSCFG_CFGR3_PINMUX7_1) << 16U) | 0x00000000U) /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB7 */ +#define LL_PINMUX_WLCSP15_PINA2_PB8 (((SYSCFG_CFGR3_PINMUX7_0 | SYSCFG_CFGR3_PINMUX7_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX7_0) /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB8 */ +#define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP15_PINB1_PB7 +#define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP15_PINB1_PB8 + +#elif (DEV_ID == 0x44DUL) +#define LL_PINMUX_TSSOP20_PIN19_PA14 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA14 */ +#define LL_PINMUX_TSSOP20_PIN19_PA15 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA15 */ +#define LL_PINMUX_TSSOP20_PIN15_PA8 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PA8 */ +#define LL_PINMUX_TSSOP20_PIN15_PB0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB0 */ +#define LL_PINMUX_TSSOP20_PIN15_PB1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB1 */ +#define LL_PINMUX_TSSOP20_PIN15_PB2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \ + (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1)) /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB2 */ +#define LL_PINMUX_WLCSP24_PING1_PA8 LL_PINMUX_TSSOP20_PIN15_PA8 +#define LL_PINMUX_WLCSP24_PING1_PB2 LL_PINMUX_TSSOP20_PIN15_PB0 +#define LL_PINMUX_TSSOP20_PIN20_PB6 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB6 */ +#define LL_PINMUX_TSSOP20_PIN20_PB3 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB3 */ +#define LL_PINMUX_TSSOP20_PIN20_PB4 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB4 */ +#define LL_PINMUX_TSSOP20_PIN20_PB5 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB5 */ +#define LL_PINMUX_WLCSP24_PINA5_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 +#define LL_PINMUX_WLCSP24_PINA5_PB4 LL_PINMUX_TSSOP20_PIN20_PB3 +#define LL_PINMUX_WLCSP24_PINA3_PB5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB5 */ +#define LL_PINMUX_WLCSP24_PINA3_PB3 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB3 */ +#define LL_PINMUX_WLCSP24_PINB4_PB7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB7 */ +#define LL_PINMUX_WLCSP24_PINB4_PB8 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \ + SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB8 */ +#define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP24_PINB4_PB7 +#define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP24_PINB4_PB8 +#endif /* DEV_ID == 0x443UL */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_PINMUX_SOURCE PINMUX Config Source + * @{ + */ +#if (DEV_ID == 0x443UL) +#define LL_PINMUX_SO8_PIN1 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */ +#define LL_PINMUX_SO8_PIN4 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */ +#define LL_PINMUX_SO8_PIN5 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */ +#define LL_PINMUX_SO8_PIN8 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */ +#define LL_PINMUX_WLCSP12_PINE2 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */ +#define LL_PINMUX_WLCSP12_PINF1 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer */ +#elif (DEV_ID == 0x453UL) +#define LL_PINMUX_WLCSP14_PINF2 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */ +#define LL_PINMUX_WLCSP14_PING3 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */ +#define LL_PINMUX_WLCSP14_PINJ1 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */ +#define LL_PINMUX_WLCSP14_PINH2 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */ +#define LL_PINMUX_WLCSP14_PING1 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */ +#define LL_PINMUX_WLCSP14_PINJ3 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */ +#elif (DEV_ID == 0x493UL) +#define LL_PINMUX_WLCSP19_PINH3 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C071 WLCSP19 package, GPIO PinH3 multiplexer */ +#define LL_PINMUX_WLCSP19_PINB1 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C071 WLCSP19 package, GPIO PinB1 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN19 LL_PINMUX_WLCSP19_PINB1 /*!< STM32C071 TSSOP20 package, GPIO Pin19 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN20 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */ +#define LL_PINMUX_WLCSP19_PINB3 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */ +#elif (DEV_ID == 0x44CUL) +#define LL_PINMUX_WLCSP15_PINH3 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */ +#define LL_PINMUX_WLCSP15_PING2 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */ +#define LL_PINMUX_WLCSP15_PINK3 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */ +#define LL_PINMUX_WLCSP15_PINJ2 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */ +#define LL_PINMUX_WLCSP15_PINH1 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */ +#define LL_PINMUX_WLCSP15_PINE2 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C051 WLCSP15 package, GPIO PinE2 multiplexer */ +#define LL_PINMUX_WLCSP15_PINB1 (SYSCFG_CFGR3_PINMUX6_0 | SYSCFG_CFGR3_PINMUX6_1) /*!< STM32C051 WLCSP15 package, GPIO PinB1 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN20 LL_PINMUX_WLCSP15_PINB1 +#define LL_PINMUX_WLCSP15_PINA2 (SYSCFG_CFGR3_PINMUX7_0 | SYSCFG_CFGR3_PINMUX7_1) /*!< STM32C051 WLCSP15 package, GPIO PinA2 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP15_PINB1 +#elif (DEV_ID == 0x44DUL) +#define LL_PINMUX_TSSOP20_PIN19 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C091/92 TSSOP20 package, GPIO Pin19 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN15 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C091/92 TSSOP20 package, GPIO Pin15 multiplexer */ +#define LL_PINMUX_WLCSP24_PING1 LL_PINMUX_TSSOP20_PIN15 +#define LL_PINMUX_TSSOP20_PIN20 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C091/92 TSSOP20 package, GPIO Pin20 multiplexer */ +#define LL_PINMUX_WLCSP24_PINA5 LL_PINMUX_TSSOP20_PIN20 +#define LL_PINMUX_WLCSP24_PINA3 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C091/92 WLCSP24 package, GPIO PinA3 multiplexer */ +#define LL_PINMUX_WLCSP24_PINB4 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C091/92 WLCSP24 package, GPIO PinB4 multiplexer */ +#define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP24_PINB4 +#endif /* DEV_ID == 0x443UL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +/** + * @brief Enable remap of a pin on different pad + * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_EnablePinRemap\n + * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_EnablePinRemap\n + * @param PinRemap This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_PIN_RMP_PA11 + * @arg @ref LL_SYSCFG_PIN_RMP_PA12 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap) +{ + SET_BIT(SYSCFG->CFGR1, PinRemap); +} + +/** + * @brief Enable remap of a pin on different pad + * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_DisablePinRemap\n + * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_DisablePinRemap\n + * @param PinRemap This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_PIN_RMP_PA11 + * @arg @ref LL_SYSCFG_PIN_RMP_PA12 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap) +{ + CLEAR_BIT(SYSCFG->CFGR1, PinRemap); +} + +/** + * @brief Set IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); +} + +/** + * @brief Get IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); +} + +/** + * @brief Set IR Output polarity. + * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_SetIRPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_IR_POL_INVERTED + * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity); +} + +/** + * @brief Get IR Output polarity. + * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_GetIRPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IR_POL_INVERTED + * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)); +} + + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus + * SYSCFG_CFGR1 I2C_FMP_PC14 LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PC14 + * + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus + * SYSCFG_CFGR1 I2C_FMP_PC14 LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PC14 + * + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Set connections to TIM1/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL, Break); +} + +/** + * @brief Get connections to TIM1/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)); +} + +/** + * @brief Config PinMux + * @rmtoll SYSCFG_CFGR3 CLL LL_SYSCFG_ConfigPinMux\n + * @param mux_cfg This parameter can be a value of @ref SYSTEM_LL_PINMUX_CFG + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ConfigPinMux(uint32_t mux_cfg) +{ + MODIFY_REG(SYSCFG->CFGR3, (mux_cfg >> 16U), (mux_cfg & 0x0000FFFFU)); +} + +/** + * @brief Get PinMux configuration + * @rmtoll SYSCFG_CFGR3 CLL LL_SYSCFG_GetConfigPinMux\n + * @param LL_PINMUX_PACKx_PINy This parameter can be a value of @ref SYSTEM_LL_PINMUX_SOURCE + * @retval Returned value can be one of SYSTEM_LL_PINMUX_CFG defines + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigPinMux(uint32_t LL_PINMUX_PACKx_PINy) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR3, LL_PINMUX_PACKx_PINy) | (LL_PINMUX_PACKx_PINy << 16U)); +} + +#if defined(SYSCFG_ITLINE0_SR_WWDG) +/** + * @brief Check if Window watchdog interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_WWDG) == (SYSCFG_ITLINE0_SR_WWDG)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE0_SR_WWDG */ + +#if defined(SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT) +/** + * @brief Check if VDDIO2 supply monitoring interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT LL_SYSCFG_IsActiveFlag_PVM_VDDIO2_OUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVM_VDDIO2_OUT(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[1], + SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT) == (SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT */ + +#if defined(SYSCFG_ITLINE2_SR_RTC) +/** + * @brief Check if RTC interrupt occurred or not (EXTI line 19). + * @rmtoll SYSCFG_ITLINE2 SR_RTC LL_SYSCFG_IsActiveFlag_RTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE2_SR_RTC */ + +#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) +/** + * @brief Check if Flash interface interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ + +#if defined(SYSCFG_ITLINE4_SR_RCC) +/** + * @brief Check if Reset and clock control interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4_SR_RCC LL_SYSCFG_IsActiveFlag_CLK_CTRL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_RCC) == (SYSCFG_ITLINE4_SR_RCC)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE4_SR_RCC */ + +#if defined(SYSCFG_ITLINE4_SR_CRS) +/** + * @brief Check if CRS interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE4_SR_CRS */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI0) +/** + * @brief Check if EXTI line 0 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI0 */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI1) +/** + * @brief Check if EXTI line 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI1 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI2) +/** + * @brief Check if EXTI line 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI2 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI3) +/** + * @brief Check if EXTI line 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI3 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI4) +/** + * @brief Check if EXTI line 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI4 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI5) +/** + * @brief Check if EXTI line 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI5 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI6) +/** + * @brief Check if EXTI line 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI6 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI7) +/** + * @brief Check if EXTI line 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI7 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI8) +/** + * @brief Check if EXTI line 8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI8 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI9) +/** + * @brief Check if EXTI line 9 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI9 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI10) +/** + * @brief Check if EXTI line 10 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI10 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI11) +/** + * @brief Check if EXTI line 11 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI11 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI12) +/** + * @brief Check if EXTI line 12 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI12 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI13) +/** + * @brief Check if EXTI line 13 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI13 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI14) +/** + * @brief Check if EXTI line 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI14 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI15) +/** + * @brief Check if EXTI line 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI15 */ + +#if defined(SYSCFG_ITLINE8_SR_USB) +/** + * @brief Check if USB interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8_SR_USB LL_SYSCFG_IsActiveFlag_USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_USB) == (SYSCFG_ITLINE8_SR_USB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE8_SR_USB */ + +#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) +/** + * @brief Check if DMA1 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) +/** + * @brief Check if DMA1 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) +/** + * @brief Check if DMA1 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ + +#if defined(SYSCFG_ITLINE11_SR_DMAMUX1) +/** + * @brief Check if DMAMUX interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1 LL_SYSCFG_IsActiveFlag_DMAMUX + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX1) == (SYSCFG_ITLINE11_SR_DMAMUX1)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMAMUX */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +/** + * @brief Check if DMA1_CH4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +/** + * @brief Check if DMA1_CH5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +/** + * @brief Check if DMA1_CH6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +/** + * @brief Check if DMA1_CH7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ + +#if defined(SYSCFG_ITLINE12_SR_ADC) +/** + * @brief Check if ADC interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE12_SR_ADC */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) +/** + * @brief Check if Timer 1 break interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) +/** + * @brief Check if Timer 1 update interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) +/** + * @brief Check if Timer 1 trigger interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) +/** + * @brief Check if Timer 1 commutation interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ + +#if defined(SYSCFG_ITLINE14_SR_TIM1_CC) +/** + * @brief Check if Timer 1 capture compare interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ + +#if defined(SYSCFG_ITLINE15_SR_TIM2) +/** + * @brief Check if Timer 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2) == (SYSCFG_ITLINE15_SR_TIM2)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE15_SR_TIM2 */ + +#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) +/** + * @brief Check if Timer 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ + +#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) +/** + * @brief Check if Timer 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == \ + (SYSCFG_ITLINE19_SR_TIM14_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ + +#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +/** + * @brief Check if Timer 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == \ + (SYSCFG_ITLINE20_SR_TIM15_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ + +#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) +/** + * @brief Check if Timer 16 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == \ + (SYSCFG_ITLINE21_SR_TIM16_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ + +#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) +/** + * @brief Check if Timer 17 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == \ + (SYSCFG_ITLINE22_SR_TIM17_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ + +#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) +/** + * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. + * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ + +#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) +/** + * @brief Check if I2C2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ + +#if defined(SYSCFG_ITLINE25_SR_SPI1) +/** + * @brief Check if SPI1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE25_SR_SPI1 */ + +#if defined(SYSCFG_ITLINE26_SR_SPI2) +/** + * @brief Check if SPI2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE26_SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE26_SR_SPI2 */ + +#if defined(SYSCFG_ITLINE27_SR_USART1_GLB) +/** + * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. + * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == \ + (SYSCFG_ITLINE27_SR_USART1_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ + +#if defined(SYSCFG_ITLINE28_SR_USART2_GLB) +/** + * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == \ + (SYSCFG_ITLINE28_SR_USART2_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +/** + * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == \ + (SYSCFG_ITLINE29_SR_USART3_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +/** + * @brief Check if USART4 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == \ + (SYSCFG_ITLINE29_SR_USART4_GLB)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ + +#if defined(SYSCFG_ITLINE30_SR_FDCAN1_IT0) +/** + * @brief Check if FDCAN1_IT0 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE30 SR_FDCAN1_IT0 LL_SYSCFG_IsActiveFlag_FDCAN1_IT0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT0(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_FDCAN1_IT0) == \ + (SYSCFG_ITLINE30_SR_FDCAN1_IT0)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE30_SR_FDCAN1_IT0 */ + +#if defined(SYSCFG_ITLINE31_SR_FDCAN1_IT1) +/** + * @brief Check if FDCAN1_IT1 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE31 SR_FDCAN1_IT1 LL_SYSCFG_IsActiveFlag_FDCAN1_IT1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT1(void) +{ + return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_FDCAN1_IT1) == \ + (SYSCFG_ITLINE31_SR_FDCAN1_IT1)) ? 1UL : 0UL); +} +#endif /* SYSCFG_ITLINE31_SR_FDCAN1_IT1 */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBG_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBG_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_REV_ID) >> DBG_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBG_APB_FZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBG->APBFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBG_APB_FZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBG->APBFZ1, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBG->APBFZ2, Periphs); +} + +#define LL_DBGMCU_APB2_GRP1_FreezePeriph LL_DBGMCU_APB1_GRP2_FreezePeriph /* define for legacy purpose */ +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBG->APBFZ2, Periphs); +} + +#define LL_DBGMCU_APB2_GRP1_UnFreezePeriph LL_DBGMCU_APB1_GRP2_UnFreezePeriph /* define for legacy purpose */ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Instruction cache + * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_EnableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Disable Instruction cache + * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_DisableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Enable Instruction cache reset + * @note bit can be written only when the instruction cache is disabled + * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_EnableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Disable Instruction cache reset + * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_DisableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBG) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_SYSTEM_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h (revision 41) @@ -0,0 +1,4965 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32C0xx_LL_TIM_H +#define __STM32C0xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x3CU, /* 7: TIMx_CH5 */ + 0x3CU /* 8: TIMx_CH6 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: OC5M, OC5FE, OC5PE */ + 8U /* 8: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U /* 8: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 16U, /* 7: CC5P */ + 20U /* 8: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 8U, /* 7: OIS5 */ + 10U /* 8: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */ +#define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */ + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +/** +@endcond + */ + +#define OCREF_CLEAR_SELECT_POS (16U) +#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x00010000 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +/** +@endcond + */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 (*) + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_ITR7 (*) + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * + * (*) Value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @brief Select the external trigger (ETR) input source. + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource + * @param TIMx Timer instance + * @param ETRSource This parameter can be one of the following values: + * TIM1 + * + * @arg @ref LL_TIM_ETRSOURCE_GPIO + * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1 + * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2 + * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3 + * + * TIM2 (*) + * + * @arg @ref LL_TIM_ETRSOURCE_GPIO + * @arg @ref LL_TIM_ETRSOURCE_LSE + * @arg @ref LL_TIM_ETRSOURCE_MCO + * @arg @ref LL_TIM_ETRSOURCE_MCO2 + * + * (*) Timer instance not available on all devices \n + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) +{ + MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); +} + +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); +} + +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM1_TISEL TI3SEL LL_TIM_SetRemap\n + * TIM1_TISEL TI4SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI4SEL LL_TIM_SetRemap\n + * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM17_TISEL TI1SEL LL_TIM_SetRemap + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of TISEL registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM14: one of the following values + * + * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK + * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32 + * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO + * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2 + * + * TIM15: one of the following values (*) + * + * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1 + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1 + * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2 + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2 + * + * TIM16: one of the following values + * + * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI + * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE + * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2 + * + * TIM17: one of the following values + * + * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 + * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO + * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2 + * + * (*) Timer instance not available on all devices \n + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management + * @{ + */ +/** + * @brief Set the OCREF clear input source + * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT + * @note This function can only be used in Output compare and PWM modes. + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @param TIMx Timer instance + * @param OCRefClearInputSource This parameter can be one of the following values: + * @arg @ref LL_TIM_OCREF_CLR_INT_ETR + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, + ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32C0xx_LL_TIM_H */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h (revision 41) @@ -0,0 +1,4403 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_USART_H +#define STM32C0xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART4) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL, + 256UL, + 256UL, + 256UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART4 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_USART_H */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_utils.h (revision 41) @@ -0,0 +1,276 @@ +/** + ****************************************************************************** + * @file stm32c0xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_LL_UTILS_H +#define STM32C0xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx.h" + +/** @addtogroup STM32C0xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#if defined(STM32C011xx) +#define LL_UTILS_PACKAGETYPE_SO8 0x0001U /*!< SO8 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP12 0x0002U /*!< WLCSP12 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN20 0x0003U /*!< UFQFPN20 package type */ +#define LL_UTILS_PACKAGETYPE_TSSOP20 0x0004U /*!< TSSOP20 package type */ +#elif defined(STM32C031xx) +#define LL_UTILS_PACKAGETYPE_TSSOP20 0x0002U /*!< TSSOP20 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28 0x0003U /*!< UFQFPN28 package type */ +#define LL_UTILS_PACKAGETYPE_QFN32 0x0004U /*!< UFQFPN32 / LQFP32 package type */ +#define LL_UTILS_PACKAGETYPE_QFN48 0x0005U /*!< UFQFPN48 / LQFP48 package type */ +#elif defined(STM32C071xx) +#define LL_UTILS_PACKAGETYPE_WLCSP19_GP 0x0001U /*!< WLCSP19 (GP) package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP19_N 0x0002U /*!< WLCSP19 (N) package type */ +#define LL_UTILS_PACKAGETYPE_TSSOP20_GP 0x0003U /*!< TSSOP20 (GP) package type */ +#define LL_UTILS_PACKAGETYPE_TSSOP20_N 0x0004U /*!< TSSOP20 (N) package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28_GP 0x0005U /*!< UFQFPN28 (GP) package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28_N 0x0006U /*!< UFQFPN28 (GP) package type */ +#define LL_UTILS_PACKAGETYPE_QFN32_GP 0x0007U /*!< UFQFPN32 / LQFP32 general purpose (GP) package type */ +#define LL_UTILS_PACKAGETYPE_QFN32_N 0x0008U /*!< UFQFPN32 / LQFP32 general purpose (N) package type */ +#define LL_UTILS_PACKAGETYPE_QFN48_GP 0x0009U /*!< UFQFPN48 / LQFP48 general purpose (GP) package type */ +#define LL_UTILS_PACKAGETYPE_QFN48_N 0x000AU /*!< UFQFPN32 / LQFP48 general purpose (N) package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64_GP 0x000BU /*!< UFQFPN64 / LQFP64 general purpose (GP) package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64_N 0x0008U /*!< UFQFPN64 / LQFP64 general purpose (N) package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA64_GP 0x000DU /*!< UFBGA64 (GP) package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA64_N 0x000EU /*!< UFBGA64 (N) package type */ +#elif defined(STM32C051xx) +#define LL_UTILS_PACKAGETYPE_WLCSP15 0x0001U /*!< WLCSP15 package type */ +#define LL_UTILS_PACKAGETYPE_TSSOP20 0x0002U /*!< TSSOP20 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28 0x0003U /*!< UFQFPN28 package type */ +#define LL_UTILS_PACKAGETYPE_QFN32 0x0004U /*!< UFQFPN32 / LQFP32 package type */ +#define LL_UTILS_PACKAGETYPE_QFN48 0x0005U /*!< UFQFPN48 / LQFP48 package type */ +#elif defined(STM32C091xx) || defined(STM32C092xx) +#define LL_UTILS_PACKAGETYPE_TSSOP20 0x0001U /*!< TSSOP20 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP24 0x0002U /*!< WLCSP24 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN28 0x0003U /*!< UFQFPN28 package type */ +#define LL_UTILS_PACKAGETYPE_QFN32 0x0004U /*!< UFQFPN32 / LQFP32 package type */ +#define LL_UTILS_PACKAGETYPE_QFN48 0x0005U /*!< UFQFPN48 / LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_QFN64 0x0006U /*!< UFQFPN64 / LQFP64 package type */ +#endif /* STM32C0xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_SO8 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP12 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN20 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TSSOP20 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN28 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_QFN32 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_QFN48 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP19 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP15 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP24 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) + * + * @note (*) Availability depends on devices. + * + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +/* alias for backward compatibility */ +#define UTILS_SetFlashLatency LL_SetFlashLatency + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_LL_UTILS_H */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/LICENSE.txt =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/LICENSE.txt (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/LICENSE.txt (revision 41) @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c (revision 41) @@ -0,0 +1,615 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32C0xx HAL Driver version number + */ +#define __STM32C0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32C0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32C0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32C0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32C0xx_HAL_VERSION ((__STM32C0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32C0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32C0xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32C0xx_HAL_VERSION_RC)) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @brief HAL Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### HAL Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the Flash prefetch and the Instruction cache, + * the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file + * stm32c0xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (Systick) is used as source of time base. + * The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Configure Flash prefetch, Instruction cache */ + /* Default configuration at reset is: */ + /* - Prefetch disabled */ + /* - Instruction cache enabled */ + +#if (INSTRUCTION_CACHE_ENABLE == 0U) + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_GRP1_FORCE_RESET(); + __HAL_RCC_APB1_GRP1_RELEASE_RESET(); + + __HAL_RCC_APB1_GRP2_FORCE_RESET(); + __HAL_RCC_APB1_GRP2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + __HAL_RCC_IOP_FORCE_RESET(); + __HAL_RCC_IOP_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((uint32_t)uwTickFreq != 0UL) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status == HAL_OK) + { + uwTickFreq = Freq; + } + } + + return status; +} + +/** + * @brief return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32C0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @brief SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Pin remap +@endverbatim + * @{ + */ +/** + * @brief Enable the remap on PA11_PA12 + * @param PinRemap specifies which pins have to be remapped + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_REMAP_PA11 + * @arg @ref SYSCFG_REMAP_PA12 + * @retval None + */ +void HAL_SYSCFG_EnableRemap(uint32_t PinRemap) +{ + /* Check the parameter */ + assert_param(IS_HAL_REMAP_PIN(PinRemap)); + SET_BIT(SYSCFG->CFGR1, PinRemap); +} + +/** + * @brief Disable the remap on PA11_PA12 + * @param PinRemap specifies which pins will behave normally + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_REMAP_PA11 + * @arg @ref SYSCFG_REMAP_PA12 + * @retval None + */ +void HAL_SYSCFG_DisableRemap(uint32_t PinRemap) +{ + /* Check the parameter */ + assert_param(IS_HAL_REMAP_PIN(PinRemap)); + CLEAR_BIT(SYSCFG->CFGR1, PinRemap); +} +/** + * @brief Set Pin Binding + * @param pin_binding specifies which pin will bind a specific GPIO + * for each die package + * This parameter can be a value of @ref HAL_BIND_CFG + * @retval None + */ +void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding) +{ + /* Check the parameter */ + assert_param(IS_HAL_SYSCFG_PINBINDING(pin_binding)); + LL_SYSCFG_ConfigPinMux(pin_binding); +} + +/** + * @brief return Pin Binding configuration + * @param pin_binding_source + * This parameter can be a value of @ref HAL_BIND_SCOURCE + * @retval PinMux configuration + */ +uint32_t HAL_SYSCFG_GetPinBinding(uint32_t pin_binding_source) +{ + return LL_SYSCFG_GetConfigPinMux(pin_binding_source); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c (revision 41) @@ -0,0 +1,3066 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Initialization and de-initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of regular + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on regular group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * Other functions (extended functions) are available in file + * "stm32c0xx_hal_adc_ex.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ADC peripheral features ##### + ============================================================================== + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + + (+) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (+) Single and continuous conversion modes. + + (+) Scan mode for conversion of several channels sequentially. + + (+) Data alignment with in-built data coherency. + + (+) Programmable sampling time (common to group of channels) + + (+) External trigger (timer or EXTI) with configurable polarity + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) ADC calibration + + (+) ADC conversion of regular group. + + (+) ADC supply requirements: 1.62 V to 3.6 V. + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On STM32C0, ADC clock frequency max is 35MHz (refer + to device datasheet). + Therefore, ADC clock source from RCC and ADC clock + prescaler must be configured to remain below + this maximum frequency. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock, also possibly conversion clock). + + (+++) ADC clock (conversions clock). + Four possible clock sources: synchronous clock from APB clock (same as ADC core clock) + or asynchronous clock from RCC level: SYSCLK, HSI48. + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock) + + (++) ADC clock source and clock prescaler are configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, group regular, channels parameters *** + ================================================================ + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Fixed timeout values for ADC calibration, enable settling time, disable */ +/* settling time. */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescaler. */ +/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ +/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ +/* Unit: ms */ +#define ADC_ENABLE_TIMEOUT (2UL) +#define ADC_DISABLE_TIMEOUT (2UL) +#define ADC_STOP_CONVERSION_TIMEOUT (2UL) +#define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL) + +/* Register CHSELR bits corresponding to ranks 2 to 8 . */ +#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \ + ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief ADC Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * (refer to description of RCC configuration for ADC + * in header of this file). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmpCFGR1 = 0UL; + uint32_t tmpCFGR2 = 0UL; + uint32_t tmp_adc_reg_is_conversion_on_going; + __IO uint32_t wait_loop_index = 0UL; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); + + assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + } + } + + /* ADC group regular discontinuous mode can be enabled only if */ + /* continuous mode is disabled. */ + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + hadc->CalibrationCpltCallback = HAL_ADC_CalibrationCpltCallback; /* Legacy weak callback */ + hadc->ADCReadyCallback = HAL_ADC_ADCReadyCallback; /* Legacy weak callback */ + hadc->ChannelConfigReadyCallback = HAL_ADCEx_ChannelConfigReadyCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Initialize Lock */ + hadc->Lock = HAL_UNLOCKED; + } + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(hadc->Instance); + + /* Delay for ADC stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* Verification that ADC voltage regulator is correctly enabled, whether */ + /* or not ADC is coming from state reset (if any potential problem of */ + /* clocking, voltage regulator would not be enabled). */ + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed and if there is no conversion on going on regular */ + /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ + /* called to update a parameter on the fly). */ + tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) + ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Configuration of common ADC parameters */ + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Internal voltage regulator (no parameter in HAL ADC init structure) */ + /* - Clock configuration */ + /* - ADC resolution */ + /* - Oversampling */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + /* - Trigger frequency mode */ + /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ + /* and disable phases are performed automatically by hardware */ + /* (in this case, flag ADC_FLAG_RDY is not set). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths: temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + tmpCFGR1 |= (hadc->Init.Resolution | + ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + + /* Update setting of discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + } + else + { + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + hadc->Init.ExternalTrigConvEdge); + } + + /* Update ADC configuration register with previous settings */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_RES | + ADC_CFGR1_DISCEN | + ADC_CFGR1_CHSELRMOD | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG, + tmpCFGR1); + + tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.TriggerFrequencyMode + ); + + if (hadc->Init.OversamplingMode == ENABLE) + { + tmpCFGR2 |= (ADC_CFGR2_OVSE | + (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode + ); + } + + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_CKMODE | + ADC_CFGR2_LFTRIG | + ADC_CFGR2_OVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TOVS, + tmpCFGR2); + + /* Configuration of ADC clock mode: asynchronous clock source */ + /* with selectable prescaler. */ + if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) + { + MODIFY_REG(ADC1_COMMON->CCR, + ADC_CCR_PRESC, + hadc->Init.ClockPrescaler & ADC_CCR_PRESC); + } + } + + /* Channel sampling time configuration */ + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is not present by hardware on this device, but */ + /* emulated by software for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion". */ + /* Channels must be configured into each rank using function */ + /* "HAL_ADC_ConfigChannel()". */ + if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + { + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + ADC_CHSELR_SQ2_TO_SQ8); + } + else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + /* Set ADC group regular sequencer: */ + /* - Set ADC group regular sequencer to value memorized */ + /* in HAL ADC handle */ + /* Note: This value maybe be initialized at a unknown value, */ + /* therefore after the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + ADC_CHSELR_SQ_ALL, + (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) + | (hadc->ADCGroupRegularSequencerRanks) + ); + } + else + { + /* Nothing to do */ + } + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core peripheral clocking. */ + if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + == hadc->Init.SamplingTimeCommon1) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: + * all ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behavior in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: + * this saves more power by reducing leakage currents + * and is particularly interesting before entering MCU low-power modes. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + + /* Disable ADC internal voltage regulator */ + LL_ADC_DisableInternalRegulator(hadc->Instance); + } + + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ + /* and disable return status. In case of status fail, attempt to */ + /* perform deinitialization anyway and it is up user code in */ + /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ + /* system RCC hard reset. */ + + /* ========== Reset ADC registers ========== */ + + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | + ADC_IT_AWD1 | ADC_IT_OVR | + ADC_IT_EOS | ADC_IT_EOC | + ADC_IT_EOCAL | ADC_IT_EOSMP | ADC_IT_RDY)); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | + ADC_FLAG_AWD1 | ADC_FLAG_OVR | + ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOCAL | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + + /* Reset register CFGR1 */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | + ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; + + /* Reset register SMPR */ + hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; + + /* Reset registers AWDxTR */ + hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); + hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); + hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); + + /* Reset register CHSELR */ + hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CCR */ + ADC1_COMMON->CCR &= ~(ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* If needed, copy-paste and uncomment the following reset code into */ + /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ + /* */ + /* __HAL_RCC_ADC1_FORCE_RESET() */ + /* __HAL_RCC_ADC1_RELEASE_RESET() */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Reset HAL ADC handle variable */ + hadc->ADCGroupRegularSequencerRanks = 0x00000000UL; + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Initialize the ADC MSP. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the ADC MSP. + * @param hadc ADC handle + * @note All ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = pCallback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions + * @brief ADC IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enable ADC, start conversion of regular group. + * @note Interruptions enabled in this function: None. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_Flag_End; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of conversion selected to end of sequence conversions */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_Flag_End = ADC_FLAG_EOS; + } + /* If end of conversion selected to end of unitary conversion */ + else /* ADC_EOC_SINGLE_CONV */ + { + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until End of unitary conversion or sequence conversions flag is raised */ + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* Check whether end of sequence is reached */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Clear end of conversion flag of regular group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + /* until data register is read using function HAL_ADC_GetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for ADC event. + * @param hadc ADC handle + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on + * all STM32 devices) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on + * all STM32 families) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on + * all STM32 families) + * @arg @ref ADC_OVR_EVENT ADC Overrun event + * @param Timeout Timeout value in millisecond. + * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * by a new converted data as soon as OVR is cleared. + * To reset OVR flag once the preserved data is retrieved, the user can resort + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + switch (EventType) + { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable ADC, start conversion of regular group with interruption. + * @note Interruptions enabled in this function according to initialization + * setting : EOC (end of conversion), EOS (end of sequence), + * OVR overrun. + * Each of these interruptions has its dedicated callback function. + * @note To guarantee a proper reset of all interruptions once all the needed + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * a correct stop of the IT-based conversions. + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * interruption. If required (e.g. in case of oversampling with trigger + * mode), the user must: + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * before calling HAL_ADC_Start_IT(). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* Enable ADC end of conversion interrupt */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; + } + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is + ADC_IT_OVR enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enable ADC, start conversion of regular group and transfer result through DMA. + * @note Interruptions enabled in this function: + * overrun (if applicable), DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @param hadc ADC handle + * @param pData Destination Buffer address. + * @param Length Number of data to be transferred from ADC peripheral to memory + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL) + { + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + /* Disable ADC */ + LL_ADC_Disable(hadc->Instance); + } + + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; + } + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential ADC group regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Disable(hadc); + } + else + { + (void)ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Handle ADC interrupt request. + * @param hadc ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) +{ + uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t tmp_isr = hadc->Instance->ISR; + uint32_t tmp_ier = hadc->Instance->IER; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Sampling flag for ADC group regular ========== */ + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + { + /* Update state machine on end of sampling status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + } + + /* End Of Sampling callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->EndOfSamplingCallback(hadc); +#else + HAL_ADCEx_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + } + + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) + { + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ + /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ + /* to determine if conversion has been triggered from EOC or EOS, */ + /* possibility to use: */ + /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* ========== Check Analog watchdog 1 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window 1 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + } + + /* ========== Check analog watchdog 2 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Level out of window 2 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow2Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow2Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + } + + /* ========== Check analog watchdog 3 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Level out of window 3 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow3Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow3Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + } + /* ========== Check Overrun flag ========== */ + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + { + /* If overrun is set to overwrite previous data (default setting), */ + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + overrun_error = 1UL; + } + else + { + /* Check DMA configuration */ + if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE) + { + overrun_error = 1UL; + } + } + + if (overrun_error == 1UL) + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Error callback */ + /* Note: In case of overrun, ADC conversion data is preserved until */ + /* flag OVR is reset. */ + /* Therefore, old ADC conversion data can be retrieved in */ + /* function "HAL_ADC_ErrorCallback()". */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* ========== Check ADC Ready flag ========== */ + if (((tmp_isr & ADC_FLAG_RDY) == ADC_FLAG_RDY) && ((tmp_ier & ADC_IT_RDY) == ADC_IT_RDY)) + { + /* Update state machine on end of sampling status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + + /* ADC Ready callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ADCReadyCallback(hadc); +#else + HAL_ADC_ADCReadyCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Leave ADRDY flag up (used by HAL), disable interrupt source instead */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_RDY); + } + + /* ========== Check End of Calibration flag ========== */ + if (((tmp_isr & ADC_FLAG_EOCAL) == ADC_FLAG_EOCAL) && ((tmp_ier & ADC_IT_EOCAL) == ADC_IT_EOCAL)) + { + /* End Of Calibration callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->CalibrationCpltCallback(hadc); +#else + HAL_ADC_CalibrationCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear end of calibration flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOCAL); + } + + /* ========== Check channel configuration ready flag ========== */ + if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY)) + { + /* Channel configuration ready callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ChannelConfigReadyCallback(hadc); +#else + HAL_ADCEx_ChannelConfigReadyCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY); + } +} + +/** + * @brief Conversion complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 1 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non-blocking mode + * (ADC conversion with interruption or transfer by DMA). + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + +/** + * @brief Calibration complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_CalibrationCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC Ready callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ADCReadyCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configure a channel to be assigned to ADC group regular. + * @note In case of usage of internal measurement channels: + * VrefInt/TempSensor. + * These internal paths can be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into ADC group regular, + * following calls to this function can be used to reconfigure + * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, + * without resetting the ADC. + * The setting of these parameters is conditioned to ADC state: + * Refer to comments of structure "ADC_ChannelConfTypeDef". + * @param hadc ADC handle + * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_config_internal_channel; + __IO uint32_t wait_loop_index = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime)); + + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank)); + } + else + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: VrefInt/TempSensor */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC sequencer. */ + /* If sequencer set to not fully configurable with channel rank set to */ + /* none, remove the channel from the sequencer. */ + /* Otherwise (sequencer set to fully configurable or to to not fully */ + /* configurable with channel rank to be set), configure the selected */ + /* channel. */ + if (sConfig->Rank != ADC_RANK_NONE) + { + /* Regular sequence configuration */ + /* Note: ADC channel configuration requires few ADC clock cycles */ + /* to be ready. Processing of ADC settings in this function */ + /* induce that a specific wait time is not necessary. */ + /* For more details on ADC channel configuration ready, */ + /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */ + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + /* Sequencer set to not fully configurable: */ + /* Set the channel by enabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel); + } + else + { + /* Sequencer set to fully configurable: */ + /* Set the channel by entering it into the selected rank. */ + + /* Memorize the channel set into variable in HAL ADC handle */ + MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, + ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL), + __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL)); + + /* If the selected rank is below ADC group regular sequencer length, */ + /* apply the configuration in ADC register. */ + /* Note: Otherwise, configuration is not applied. */ + /* To apply it, parameter'NbrOfConversion' must be increased. */ + if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) + { + LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + } + } + + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + + /* Management of internal measurement channels: VrefInt/TempSensor */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && + ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + else + { + /* Regular sequencer configuration */ + /* Note: Case of sequencer set to fully configurable: */ + /* Sequencer rank cannot be disabled, only affected to */ + /* another channel. */ + /* To remove a rank, use parameter 'NbrOfConversion". */ + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + /* Sequencer set to not fully configurable: */ + /* Reset the channel by disabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel); + } + + /* Management of internal measurement channels: VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); + } + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + } + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Configure the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @note On this STM32 series, analog watchdog thresholds can be modified + * while ADC conversion is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmpAWDHighThresholdShifted; + uint32_t tmpAWDLowThresholdShifted; + uint32_t backup_setting_adc_enable_state = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + + if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) + { + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + } + + /* Verify thresholds range */ + if (hadc->Init.OversamplingMode == ENABLE) + { + /* Case of oversampling enabled: depending on ratio and shift configuration, + analog watchdog thresholds can be higher than ADC resolution. + Verify if thresholds are within maximum thresholds range. */ + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + } + else + { + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on ADC group regular: */ + /* - Analog watchdog channels */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Analog watchdog configuration */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Constraint of ADC on this STM32 series: ADC must be disable + to modify bitfields of register ADC_CFGR1 */ + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + backup_setting_adc_enable_state = 1UL; + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels. */ + switch (AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); + break; + } + + if (backup_setting_adc_enable_state == 1UL) + { + tmp_hal_status = ADC_Enable(hadc); + } + + /* Update state, clear previous result related to AWD1 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD1(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD1(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD1(hadc->Instance); + } + } + /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ + else + { + switch (AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + /* Update AWD by bitfield to keep the possibility to monitor */ + /* several channels by successive calls of this function. */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + else + { + SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + break; + } + + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + /* Update state, clear previous result related to AWD2 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD2(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD2(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD2(hadc->Instance); + } + } + /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + else + { + /* Update state, clear previous result related to AWD3 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD3(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD3(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD3(hadc->Instance); + } + } + } + + } + + /* Analog watchdog thresholds configuration */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); + tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + } + /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ + else + { + /* No need to shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold; + tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold; + } + + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, + tmpAWDLowThresholdShifted); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral state and errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the ADC handle state. + * @note ADC state machine is managed by bitfields, ADC status must be + * compared with states bits. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + * @param hadc ADC handle + * @retval ADC handle state (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return ADC handle state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code. + * @param hadc ADC handle + * @retval ADC error code (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Stop ADC conversion. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification if ADC is not already stopped on regular group to bypass */ + /* this function if not needed. */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + /* Stop potential conversion on going on regular group */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } + + /* Wait for conversion effectively stopped */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + __IO uint32_t wait_loop_index = 0UL; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Check if conditions to enable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Enable the ADC peripheral */ + LL_ADC_Enable(hadc->Instance); + + if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) + != 0UL) + { + /* Delay for temperature sensor buffer stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) + * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware and flag ADC ready is not set. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + /* Wait for ADC effectively enabled */ + tickstart = HAL_GetTick(); + + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the + calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this + 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_Enable(hadc->Instance); + } + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Disable the selected ADC. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); + + /* Verification if ADC is not already disabled: */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) + { + /* Check if conditions to disable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) + { + /* Disable the ADC peripheral */ + LL_ADC_Disable(hadc->Instance); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Wait for ADC effectively disabled */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call ADC DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c (revision 41) @@ -0,0 +1,419 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Operation functions + * ++ Calibration + * +++ ADC automatic self-calibration + * +++ Calibration factors get or set + * Other functions (generic functions) are available in file + * "stm32c0xx_hal_adc.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32c0xx_hal_adc.c". + [..] + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants + * @{ + */ + +/* Fixed timeout value for ADC calibration. */ +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ +/* source 8MHz, ADC clock prescaler 256), CPU frequency 48MHz. */ +/* Calibration time max = 116 / fADC (refer to datasheet) */ +/* = 178 176 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (178176UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ +#define ADC_DISABLE_TIMEOUT (2UL) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Perform the ADC self-calibration. + (+) Get calibration factors. + (+) Set calibration factors. + +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * @note Calibration factor can be read after calibration, using function + * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + __IO uint32_t wait_loop_index = 0UL; + uint32_t backup_setting_cfgr1; + uint32_t calibration_index; + uint32_t calibration_factor_accumulated = 0; + uint32_t tickstart; + uint32_t adc_clk_async_presc; + __IO uint32_t delay_cpu_cycles; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Calibration prerequisite: ADC must be disabled. */ + + /* Disable the ADC (if not already disabled) */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Manage settings impacting calibration */ + /* - Disable ADC mode auto power-off */ + /* - Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 series: Calibration factor is */ + /* available in data register and also transferred by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); + + /* ADC calibration procedure */ + /* Note: Perform an averaging of 8 calibrations for optimized accuracy */ + for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++) + { + /* Start ADC calibration */ + LL_ADC_StartCalibration(hadc->Instance); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + /* Read the calibration factor and increment by one */ + calibration_factor_accumulated += (LL_ADC_GetCalibrationFactor(hadc->Instance) + 1UL); + } + /* Compute average (rounded up to the nearest integer) */ + calibration_factor_accumulated += (calibration_index / 2UL); + calibration_factor_accumulated /= calibration_index; + + /* Apply calibration factor (requires ADC enable and disable process) */ + LL_ADC_Enable(hadc->Instance); + + /* Case of ADC clocked at low frequency: Delay required between ADC enable and disable actions */ + if (LL_ADC_GetClock(hadc->Instance) == LL_ADC_CLOCK_ASYNC) + { + adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + if (adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16) + { + /* Delay loop initialization and execution */ + /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */ + delay_cpu_cycles = (1UL << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3UL)); + /* Divide variable by 2 to compensate partially CPU processing cycles */ + delay_cpu_cycles >>= 1UL; + + while (delay_cpu_cycles != 0UL) + { + delay_cpu_cycles--; + } + } + } + + LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated); + LL_ADC_Disable(hadc->Instance); + + /* Wait for ADC effectively disabled before changing configuration */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + + /* Restore configuration after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Note: No need to update variable "tmp_hal_status" here: already set */ + /* to state "HAL_ERROR" by function disabling the ADC. */ + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get the calibration factor. + * @param hadc ADC handle. + * @retval Calibration value. + */ +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return the selected ADC calibration value */ + return ((hadc->Instance->CALFACT) & 0x0000007FU); +} + +/** + * @brief Set the calibration factor to overwrite automatic conversion result. + * ADC must be enabled and no conversion is ongoing. + * @param hadc ADC handle + * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) + * @retval HAL state + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_adc_is_conversion_on_going_regular; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CALFACT(CalibrationFactor)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Verification of hardware constraints before modifying the calibration */ + /* factors register: ADC must be enabled, no conversion on going. */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + ) + { + hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; + hadc->Instance->CALFACT |= CalibrationFactor; + } + else + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + /* Update ADC error code */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + /* Update ADC state machine to error */ + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Analog watchdog 2 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 3 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. + */ +} + + +/** + * @brief End Of Sampling callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC channel configuration ready callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** + * @brief Disable ADC voltage regulator. + * @note Disabling voltage regulator allows to save power. This operation can + * be carried out only when ADC is disabled. + * @note To enable again the voltage regulator, the user is expected to + * resort to HAL_ADC_Init() API. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_DisableInternalRegulator(hadc->Instance); + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c (revision 41) @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex M0+ exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. + + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32c0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32c0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(SubPriority); + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn, PreemptPriority); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if (__MPU_PRESENT == 1U) +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c (revision 41) @@ -0,0 +1,1076 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + Prior to HAL_DMA_Init the CLK shall be enabled for both DMA & DMAMUX + thanks to: + DMA1 : __HAL_RCC_DMA1_CLK_ENABLE(); + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e. a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* calculation of the channel index */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ + (uint32_t)DMA1_Channel1)) << 2U; + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + hdma->Init.PeriphInc | hdma->Init.MemInc | \ + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \ + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* calculation of the channel index */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ + (uint32_t)DMA1_Channel1)) << 2U; + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } + + /* Process locked */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral handle */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU))); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Unlocked/locked */ + __HAL_UNLOCK(hdma); + __HAL_LOCK(hdma); + + if (HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU))); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + if (HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU); + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while (0U == __HAL_DMA_GET_FLAG(hdma, temp)) + { + if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU))); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + /*Check for DMAMUX Request generator (if used) overrun status */ + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = DMA1->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + return; +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, + void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA handle state. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Peripheral to Memory */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t channel_number; + + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ + ((hdma->ChannelIndex >> 2U) * \ + ((uint32_t)DMAMUX1_Channel1 - \ + (uint32_t)DMAMUX1_Channel0))); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \ + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c (revision 41) @@ -0,0 +1,295 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler + should be called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + /*Check if the DMA state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG(hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID), \ + ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << \ + DMAMUX_CxCR_NBREQ_Pos) | \ + pSyncConfig->SyncPolarity | \ + ((uint32_t)pSyncConfig->SyncEnable << \ + DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << \ + DMAMUX_CxCR_EGE_Pos)); + + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /*DMA State not Ready*/ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters*/ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \ + pRequestGeneratorConfig->Polarity; + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if (hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c (revision 41) @@ -0,0 +1,662 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configiguration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & EXTI_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c (revision 41) @@ -0,0 +1,699 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) Prefetch on I-Code + (+) 32 cache lines of 4*64 bits on I-Code + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32C0xx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: double word and fast program (full row programming) + (++) There are two modes of programming: + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions: + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache + (+) Reset the Instruction cache + (+) Enable/Disable the Flash power-down during low-power modes + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = FLASH_TYPENONE, \ + .Address = 0U, \ + .Page = 0U, \ + .NbPagesToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program double word or fast program of a row at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 row double-word (64-bit) at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG or FSTPG Bit */ + CLEAR_BIT(FLASH->CR, TypeProgram); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program double word or fast program of a row at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Enable End of Operation and Error interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); + + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 row double-word (64-bit) at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + } + + /* return status */ + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param = 0xFFFFFFFFU; + uint32_t error; + + /* Save flash errors */ + error = (FLASH->SR & FLASH_FLAG_SR_ERROR); + + CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing); + + /* A] Set parameter for user or error callbacks */ + /* check operation was a program or erase */ + if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U) + { + /* return address being programmed */ + param = pFlash.Address; + } + else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASS | FLASH_TYPEERASE_PAGES)) != 0x00U) + { + /* return page number being erased (0 for mass erase) */ + param = pFlash.Page; + } + else + { + /* Nothing to do */ + } + + /* B] Check errors */ + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* clear error flags */ + __HAL_FLASH_CLEAR_FLAG(error); + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + + /* Error callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* C] Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0x00U) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES) + { + /* Nb of pages to erased can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase*/ + if (pFlash.NbPagesToErase != 0x00U) + { + /* Increment page number */ + pFlash.Page++; + FLASH_PageErase(pFlash.Page); + } + else + { + /* No more pages to erase: stop erase pages procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + } + else + { + /*Stop the ongoing procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + + /* User callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == FLASH_TYPENONE) + { + /* Disable End of Operation and Error interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page which has been erased + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* verify Flash is unlock */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* verify option bytes are unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U) + { + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); + + /* verify option bytes are locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* We should not reach here : Option byte launch generates Option byte reset + so return error */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be + * @arg @ref HAL_FLASH_ERROR_NONE No error set + * @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error + * @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error + * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error + * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error + * @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error + * @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error + * @arg @ref HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error + * @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP) + * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t error; + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + uint32_t timeout = HAL_GetTick() + Timeout; + + /* Wait if any operation is ongoing */ + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0x00U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + /* check flash errors */ + error = (FLASH->SR & FLASH_FLAG_SR_ERROR); + + /* clear error flags */ + __HAL_FLASH_CLEAR_FLAG(error); + + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode = error; + + return HAL_ERROR; + } + + /* Wait for control register to be written */ + timeout = HAL_GetTick() + Timeout; + + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) != 0x00U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Program double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Program first word */ + *(uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); +} + +/** + * @brief Fast program a 32 row double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address where the data are stored. + * @retval None + */ +static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 0; + uint32_t dest = Address; + uint32_t src = DataAddress; + uint32_t primask_bit; + + /* Set FSTPG bit */ + SET_BIT(FLASH->CR, FLASH_CR_FSTPG); + + /* Enter critical section: row programming should not be longer than 7 ms */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Fast Program : 64 words */ + while (index < 64U) + { + *(uint32_t *)dest = *(uint32_t *)src; + src += 4U; + dest += 4U; + index++; + } + + /* wait for BSY1 in order to be sure that flash operation is ended befoire + allowing prefetch in flash. Timeout does not return status, as it will + be anyway done later */ + while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) + { + } + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c (revision 41) @@ -0,0 +1,876 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32C0xx + devices contains the following additional features + + (+) Capacity up to 128 Kbytes with single bank architecture supporting read-while-write + capability (RWW) + (+) Single bank memory organization + (+) PCROP protection + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32C0xx devices. It includes + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase page, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the PCROP protection + (++) Set Securable memory area and boot entry point + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get Securable memory area and boot entry point information + + (#) Enable or disable debugger usage using HAL_FLASHEx_EnableDebugger and + HAL_FLASHEx_DisableDebugger. + + (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck. + and modify this setting (for flash loader purpose e.g.) using + HAL_FLASHEx_ForceFlashEmpty. + + (#) Enable securable memory area protectionusing HAL_FLASHEx_EnableSecMemProtection + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(void); +void FLASH_FlushCaches(void); +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel); +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr); +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize); +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); +static uint32_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetUser(void); +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr); +static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize); +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @param[out] PageError Pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all + * the pages have been correctly erased) + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + { + /* Mass erase to be done */ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) + { + /* Start erase page */ + FLASH_PageErase(index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = index; + break; + } + } + + /* If operation is completed or interrupted, disable the Page Erase Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* save procedure for interrupt treatment */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Enable End of Operation and Error interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + { + /* Set Page to 0 for Interrupt callback management */ + pFlash.Page = 0; + + /* Proceed to Mass Erase */ + FLASH_MassErase(); + } + else + { + /* Erase by page to be done */ + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->Page; + + /*Erase 1st page and wait for IT */ + FLASH_PageErase(pEraseInit->Page); + } + } + + /* return status */ + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account only + * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() + * - a Power On Reset + * - an exit from Standby or Shutdown mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + uint32_t optr; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); + } + + /* Option register */ + if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER)) + { + /* Fully modify OPTR register with RDP & user data */ + FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U) + { + /* Only modify RDP so get current user data */ + optr = FLASH_OB_GetUser(); + FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U) + { + /* Only modify user so get current RDP level */ + optr = FLASH_OB_GetRDP(); + FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr); + } + else + { + /* nothing to do */ + } + + /* PCROP Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U) + { + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); + + if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U) + { + /* Configure the 1A Proprietary code readout protection */ + FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr); + } + + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U) + { + /* Configure the 1B Proprietary code readout protection */ + FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); + } + } + + /* Securable Memory Area Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U) + { + /* Configure the securable memory area protection */ + FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize); + } + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the option byte program operation is completed, disable the OPTSTRT Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @note warning: this API only read flash register, it does not reflect any + * change that would have been programmed between previous Option byte + * loading and current call. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the + * configuration information. The fields pOBInit->WRPArea and + * pOBInit->PCROPConfig should indicate which area is requested + * for the WRP and PCROP. + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_ALL; + + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + pOBInit->USERType = OB_USER_ALL; + + /* Get the Proprietary code readout protection */ + FLASH_OB_GetPCROP1A(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr)); + FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); + + /* Get the Securable Memory Area protection */ + FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize)); +} + +/** + * @brief Enable Debugger. + * @note After calling this API, flash interface allow debugger intrusion. + * @retval None + */ +void HAL_FLASHEx_EnableDebugger(void) +{ + FLASH->ACR |= FLASH_ACR_DBG_SWEN; +} + +/** + * @brief Disable Debugger. + * @note After calling this API, Debugger is disabled: it is no more possible to + * break, see CPU register, etc... + * @retval None + */ +void HAL_FLASHEx_DisableDebugger(void) +{ + FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; +} + +/** + * @brief Flash Empty check + * @note This API checks if first location in Flash is programmed or not. + * This check is done once by Option Byte Loader. + * @retval 0 if 1st location is not programmed else + */ +uint32_t HAL_FLASHEx_FlashEmptyCheck(void) +{ + return ((FLASH->ACR & FLASH_ACR_PROGEMPTY)); +} + + +/** + * @brief Force Empty check value. + * @note Allows to modify program empty check value in order to force this + * infrmation in Flash Interface, for all next reset that do not launch + * Option Byte Loader. + * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check + * @retval None + */ +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty) +{ + uint32_t acr; + assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty)); + + acr = (FLASH->ACR & ~FLASH_ACR_PROGEMPTY); + FLASH->ACR = (acr | FlashEmpty); +} + +/** + * @brief Securable memory area protection enable + * @param Bank Select Bank to be secured. On C0, there is only 1 bank so + * parameter has to be set to 0. + * @note This API locks Securable memory area which is defined in SEC_SIZE option byte + * (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking + * Secsize). + * @note SEC_PROT bit can only be set, it will be reset by system reset. + * @retval None + */ +void HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) +{ + assert_param(IS_FLASH_BANK(Bank)); + FLASH->CR |= FLASH_CR_SEC_PROT; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory. + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Set the Mass Erase Bit and start bit */ + FLASH->CR |= (FLASH_CR_STRT | FLASH_CR_MER1); +} + +/** + * @brief Erase the specified FLASH memory page. + * @param Page FLASH page to erase + * This parameter must be a value between 0 and (max number of pages in Flash - 1) + * @retval None + */ +void FLASH_PageErase(uint32_t Page) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_FLASH_PAGE(Page)); + + /* Get configuration register, then clear page number */ + tmp = (FLASH->CR & ~FLASH_CR_PNB); + + /* Set page number, Page Erase bit & Start bit */ + FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); +} + +/** + * @brief Flush the instruction cache. + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } +} + + +/** + * @brief Configure the write protection of the desired pages. + * @note When WRP is active in a zone, it cannot be erased or programmed. + * Consequently, a software mass erase cannot be performed if one zone + * is write-protected. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @param WRPArea Specifies the area to be configured. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @param WRPStartOffset Specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the Flash - 1) + * @param WRDPEndOffset Specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1) + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + assert_param(IS_FLASH_PAGE(WRPStartOffset)); + assert_param(IS_FLASH_PAGE(WRDPEndOffset)); + + /* Configure the write protected area */ + if (WRPArea != OB_WRPAREA_ZONE_A) + { + FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset); + } + else + { + FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); + } +} + +/** + * @brief Set user & RDP configuration + * @note !!! Warning : When enabling OB_RDP level 2 it is no more possible + * to go back to level 1 or 0 !!! + * @param UserType The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_Type + * @param UserConfig The FLASH User Option Bytes values. + * This parameter can be a combination of: + * @arg @ref OB_USER_BOR_ENABLE, + * @arg @ref OB_USER_BOR_LEVEL, + * @arg @ref OB_USER_nRST_STOP, + * @arg @ref OB_USER_nRST_STANDBY, + * @arg @ref OB_USER_nRST_SHUTDOWN, + * @arg @ref OB_USER_IWDG_SW, + * @arg @ref OB_USER_IWDG_STOP, + * @arg @ref OB_USER_IWDG_STANDBY, + * @arg @ref OB_USER_WWDG_SW, + * @arg @ref OB_USER_SRAM_PARITY, + * @arg @ref OB_USER_nBOOT_SEL, + * @arg @ref OB_USER_nBOOT1, + * @arg @ref OB_USER_nBOOT0, + * @arg @ref OB_USER_INPUT_RESET_HOLDER + * @arg @ref OB_USER_SECURE_MUXING_EN + * @arg @ref OB_USER_HSE_NOT_REMAPPED (*) + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Memory Read protection + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @retval None + * + * @note (*) available only on STM32C071xx, STM32C051xx and STM32C091/92xx devices. + */ +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) +{ + uint32_t optr; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + assert_param(IS_OB_USER_CONFIG(UserType, UserConfig)); + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + optr = FLASH->OPTR; + optr &= ~(UserType | FLASH_OPTR_RDP); + FLASH->OPTR = (optr | UserConfig | RDPLevel); +} + +/** + * @brief Configure the 1A Proprietary code readout protection & erase configuration on RDP regression. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROPConfig specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) + * on RDP level 1 regression. + * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1AStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t pcrop1aend; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(PCROPConfig)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr)); + + /* get pcrop 1A end register */ + pcrop1aend = FLASH->PCROP1AER; + + /* Configure the Proprietary code readout protection offset */ + if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U) + { + /* Compute offset depending on pcrop granularity */ + startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP1AEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone A start offset */ + FLASH->PCROP1ASR = startoffset; + + /* Set Zone A end offset */ + pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END; + pcrop1aend |= endoffset; + } + + /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */ + if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U) + { + pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP; + } + + /* set 1A End register */ + FLASH->PCROP1AER = pcrop1aend; +} + +/** + * @brief Configure the 1B Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1BStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr)); + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP1BStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP1BEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone B start offset */ + FLASH->PCROP1BSR = startoffset; + /* Set Zone B end offset */ + FLASH->PCROP1BER = endoffset; +} + +/** + * @brief Configure Securable Memory area feature. + * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced + * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot + * @param SecSize specifies number of pages to protect as securable memory area, starting from + * beginning of the Flash (page 0). + * @retval None + */ +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize) +{ + uint32_t secmem; + + /* Check the parameters */ + assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); + assert_param(IS_OB_SEC_SIZE(SecSize)); + + /* Set securable memory area configuration */ + secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE)); + FLASH->SECR = (secmem | BootEntry | SecSize); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @param[in] WRPArea Specifies the area to be returned. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @param[out] WRPStartOffset Specifies the address where to copied the start page + * of the write protected area + * @param[out] WRDPEndOffset Dpecifies the address where to copied the end page of + * the write protected area + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + + /* Get the configuration of the write protected area */ + if (WRPArea == OB_WRPAREA_ZONE_A) + { + *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos); + } + else + { + *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); + } +} + +/** + * @brief Return the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This return value can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdplvl; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values. It will be a combination of all the following values: + * @arg @ref OB_USER_BOR_ENABLE, + * @ref OB_USER_BOR_LEVEL, + * @ref OB_USER_nRST_STOP, + * @ref OB_USER_nRST_STANDBY, + * @ref OB_USER_nRST_SHUTDOWN, + * @ref OB_USER_IWDG_SW, + * @ref OB_USER_IWDG_STOP, + * @ref OB_USER_IWDG_STANDBY, + * @ref OB_USER_WWDG_SW, + * @ref OB_USER_SRAM_PARITY, + * @ref OB_USER_nBOOT_SEL, + * @ref OB_USER_nBOOT1, + * @ref OB_USER_nBOOT0, + * @ref OB_USER_INPUT_RESET_HOLDER + * @ref OB_USER_SECURE_MUXING_EN + * @ref OB_USER_HSE_NOT_REMAPPED (*) + * + * @note (*) available only on STM32C071xx, STM32C051xx and STM32C091/92xx devices. + */ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t user = ((FLASH->OPTR & ~FLASH_OPTR_RDP) & OB_USER_ALL); + return user; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROPConfig [out] specifies the configuration of PCROP_RDP option. + * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address + * of the 1A Proprietary code readout protection + * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of + * the 1A Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr) +{ + uint32_t pcrop; + + pcrop = (FLASH->PCROP1ASR & FLASH_PCROP1ASR_PCROP1A_STRT); + *PCROP1AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1AStartAddr += FLASH_BASE; + + pcrop = FLASH->PCROP1AER; + *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1AEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1U); + + *PCROPConfig &= ~OB_PCROP_RDP_ERASE; + *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP); +} + + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address + * of the 1B Proprietary code readout protection + * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of + * the 1B Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) +{ + uint32_t pcrop; + + pcrop = (FLASH->PCROP1BSR & FLASH_PCROP1BSR_PCROP1B_STRT); + *PCROP1BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1BStartAddr += FLASH_BASE; + + pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END); + *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1BEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1U); +} + +/** + * @brief Return the FLASH Securable memory area protection Option Bytes value. + * @param BootEntry specifies boot scheme configuration + * @param SecSize specifies number of pages to protect as secure memory area, starting from + * beginning of the Flash (page 0). + * @retval None + */ +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize) +{ + uint32_t secmem = FLASH->SECR; + + *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + *SecSize = (secmem & FLASH_SECR_SEC_SIZE); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c (revision 41) @@ -0,0 +1,585 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines + * @{ + */ +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) +#define GPIO_NUMBER (16U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family + * @param pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t position = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); + + /* Configure the port pins */ + while (((pGPIO_Init->Pin) >> position) != 0U) + { + /* Get current io position */ + iocurrent = (pGPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + tmp = GPIOx->AFR[position >> 3U]; + tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3U] = tmp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + tmp = GPIOx->MODER; + tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); + GPIOx->MODER = tmp; + + /* In case of Output or Alternate function mode selection */ + if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || + (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); + + /* Configure the IO Speed */ + tmp = GPIOx->OSPEEDR; + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + GPIOx->OSPEEDR = tmp; + + /* Configure the IO Output Type */ + tmp = GPIOx->OTYPER; + tmp &= ~(GPIO_OTYPER_OT0 << position) ; + tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->OTYPER = tmp; + } + + if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) + { + /* Check the Pull parameters */ + assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + tmp = GPIOx->PUPDR; + tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); + GPIOx->PUPDR = tmp; + } + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + EXTI->EXTICR[position >> 2U] = tmp; + + /* Clear EXTI line configuration */ + tmp = EXTI->IMR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + tmp |= iocurrent; + } + EXTI->IMR1 = tmp; + + tmp = EXTI->EMR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + tmp |= iocurrent; + } + EXTI->EMR1 = tmp; + + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + tmp |= iocurrent; + } + EXTI->RTSR1 = tmp; + + tmp = EXTI->FTSR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + tmp |= iocurrent; + } + EXTI->FTSR1 = tmp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t position = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1UL << position); + + if (iocurrent != 0U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = (0x0FUL) << (8U * (position & 0x03U)); + EXTI->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32C0 family + * @param GPIO_Pin: specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c (revision 41) @@ -0,0 +1,282 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_iwdg.c + * @author MCD Application Team + * @brief IWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Independent Watchdog (IWDG) peripheral: + * + Initialization and Start functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### IWDG Generic features ##### + ============================================================================== + [..] + (+) The IWDG can be started by either software or hardware (configurable + through option byte). + + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. + + (+) Once the IWDG is started, the LSI is forced ON and both cannot be + disabled. The counter starts counting down from the reset value (0xFFF). + When it reaches the end of count value (0x000) a reset signal is + generated (IWDG reset). + + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. + + (+) The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + + (+) Debug mode: When the microcontroller enters debug mode (core halted), + the IWDG counter either continues to work normally or stops, depending + on DBG_IWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. + + [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32C0xx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM16 CH1 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts counting down. + (++) Enable write access to configuration registers: + IWDG_PR, IWDG_RLR and IWDG_WINR. + (++) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is + reloaded, then the IWDG will start counting down from this value. + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, + nothing more is done but reload counter value in order to exit + function with exact time base. + (+++) Else modify Window register. This will automatically reload + watchdog counter. + (++) Wait for status flags to be reset. + + (#) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + + *** IWDG HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IWDG HAL driver: + (+) __HAL_IWDG_START: Enable the IWDG peripheral + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + the reload register + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_IWDG_MODULE_ENABLED +/** @addtogroup IWDG + * @brief IWDG HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Defines IWDG Private Defines + * @{ + */ +/* Status register needs up to 5 LSI clock periods divided by the clock + prescaler to be updated. The number of LSI clock periods is upper-rounded to + 6 for the timeout value calculation. + The timeout value is calculated using the highest prescaler (256) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIME + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +/** @addtogroup IWDG_Exported_Functions_Group1 + * @brief Initialization and Start functions. + * +@verbatim + =============================================================================== + ##### Initialization and Start functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters in the + IWDG_InitTypeDef of associated handle. + (+) Manage Window option. + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + is reloaded in order to exit function with correct time base. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, + * watchdog is refreshed in order to have correct time base. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) +{ + uint32_t tickstart; + + /* Check the IWDG handle allocation */ + if (hiwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); + assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); + assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); + assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); + + /* Enable IWDG. LSI is turned on automatically */ + __HAL_IWDG_START(hiwdg); + + /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing + 0x5555 in KR */ + IWDG_ENABLE_WRITE_ACCESS(hiwdg); + + /* Write to IWDG registers the Prescaler & Reload values to work with */ + hiwdg->Instance->PR = hiwdg->Init.Prescaler; + hiwdg->Instance->RLR = hiwdg->Init.Reload; + + /* Check pending flag, if previous update not done, return timeout */ + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } + } + } + + /* If window parameter is different than current value, modify window + register */ + if (hiwdg->Instance->WINR != hiwdg->Init.Window) + { + /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, + even if window feature is disabled, Watchdog will be reloaded by writing + windows register */ + hiwdg->Instance->WINR = hiwdg->Init.Window; + } + else + { + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + } + + /* Return function status */ + return HAL_OK; +} + + +/** + * @} + */ + + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Refresh the IWDG. + +@endverbatim + * @{ + */ + +/** + * @brief Refresh the IWDG. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) +{ + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_IWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c (revision 41) @@ -0,0 +1,423 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + [..] + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pins are used to wakeup the system from Standby mode or + Shutdown mode. WakeUp pins polarity can be set to configure event + detection on high level (rising edge) or low level (falling edge). + + *** Low Power mode configuration *** + ===================================== + [..] + The devices feature 4 low-power modes: + (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running, + regulator is main mode. + (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is + main mode. + (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is + disable. + (+) Shutdown mode: all clocks are stopped except LSE, regulator is + disable. + + + *** Sleep mode *** + ========================================= + [..] + (+) Entry: + The Sleep is entered through HAL_PWR_EnterSLEEPMode() API specifying + the main regulator per default and if exit is interrupt or event + triggered. + (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction + (+) WFI Exit: + (++) Any interrupt enabled in nested vectored interrupt controller (NVIC) + (+) WFE Exit: + (++) Any wakeup event if cortex is configured with SEVONPEND = 0 + (++) Interrupt even when disabled in NVIC if cortex is configured with + SEVONPEND = 1 + + *** Stop 0 mode *** + ============================= + [..] + (+) Entry: + The Stop modes are entered through the following APIs: + (++) HAL_PWR_EnterSTOPMode() with following settings: + (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode. + (+) Exit (interrupt or event-triggered, specified when entering STOP mode): + (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction + (+) WFI Exit: + (++) Any EXTI line (internal or external) configured in interrupt mode + with corresponding interrupt enable in NVIC + (+) WFE Exit: + (++) Any EXTI line (internal or external) configured in event mode if + cortex is configured with SEVONPEND = 0 + (++) Any EXTI line configured in interrupt mode (even if the + corresponding EXTI Interrupt vector is disabled in the NVIC) if + cortex is configured with SEVONPEND = 0. The interrupt source can + be external interrupts or peripherals with wakeup capability. + + *** Standby mode *** + ==================== + [..] + (+) Entry: + (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by + setting SLEEPDEEP in Cortex control register. + (+) Exit: + (++) WKUP pin edge detection, RTC event (alarm, timestamp), + LSE CSS detection, reset on NRST pin, IWDG reset & BOR reset. + [..] Exiting Standby generates a power reset: Cortex is reset and execute + Reset handler vector, all registers in the Vcore domain are set to + their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG, + and Standby/Shutdown modes control) are not impacted. + + *** Shutdown mode *** + ====================== + [..] + In Shutdown mode, + voltage regulator is disabled, all clocks are off except LSE, RRS bit is + cleared. SRAM and registers contents are lost except for backup domain + registers. + (+) Entry: + (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API, + by setting SLEEPDEEP in Cortex control register. + (+) Exit: + (++) WKUP pin edge detection, RTC event (alarm, timestamp), + LSE CSS detection, reset on NRST pin. + [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute + Reset handler vector, all registers are set to their reset value but ones + in backup domain. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values which set + * the default polarity i.e. detection on high level (rising edge): + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 (Only on STM32C071xx), PWR_WAKEUP_PIN6 + * or one of the following value where the user can explicitly specify + * the enabled pin and the chosen polarity: + * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*) + * @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note (*) Availability depends on devices + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + + /* Enable wake-up pin */ + SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 (*), PWR_WAKEUP_PIN6 + * @note (*) Availability depends on devices + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); +} + +/** + * @brief Enter Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as + * in Run mode. + * @param Regulator Specifies the regulator state in Sleep mode. + * This parameter can be the following value: + * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) + * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE + * instruction. This parameter can be one of the following values: + * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep + * mode with WFI instruction + * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep + * mode with WFE instruction + * @note When WFI entry is used, tick interrupt have to be disabled if not + * desired as the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enter Stop mode + * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with + * legacy code running on devices where only "Stop mode" is mentioned + * with main regulator ON. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the HSI and the + * HSE oscillators are disabled. Some peripherals with the wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. + * SRAM and register contents are preserved. + * @note When exiting Stop 0 mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock + * @param Regulator Specifies the regulator state in Stop mode + * This parameter can be of the following value: + * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) + * @param STOPEntry Specifies Stop 0 mode is entered with WFI or + * WFE instruction. This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 mode with WFI + * instruction. + * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 mode with WFE + * instruction. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter Standby mode. + * @note In Standby mode,the HSI and the HSE oscillators are + * switched off. SRAM and register contents are lost except + * for registers in the Backup domain and Standby circuitry. + * @note The I/Os can be configured either with a pull-up or pull-down or can + * be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + * respectively enable Pull Up and PullDown state. + * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + * disable the same. These states are effective in Standby mode only if + * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Set Stand-by mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Enable Sleep-On-Exit Cortex feature + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor enters SLEEP or DEEPSLEEP mode when an interruption + * handling is over returning to thread mode. Setting this bit is + * useful when the processor is expected to run only on interruptions + * handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disable Sleep-On-Exit Cortex feature + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor enters SLEEP or DEEPSLEEP mode when an interruption + * handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enable Cortex Sev On Pending feature. + * @note Set SEVONPEND bit of SCR register. When this bit is set, enabled + * events and all interrupts, including disabled ones can wakeup + * processor from WFE. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disable Cortex Sev On Pending feature. + * @note Clear SEVONPEND bit of SCR register. When this bit is clear, only + * enable interrupts or events can wakeup processor from WFE + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c (revision 41) @@ -0,0 +1,575 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +/** @defgroup PWREx_Gpio_Pin_Number PWREx Gpio Pin Number + * @{ + */ +#define PWR_GPIO_PIN_NB 16u /*!< Number of gpio pin in bank */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +#if defined (PWR_PVM_SUPPORT) +/** + * @brief Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @retval None + */ +void HAL_PWREx_EnablePVMUSB(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_0); +} + +/** + * @brief Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @retval None + */ +void HAL_PWREx_DisablePVMUSB(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_0); +} + +/** + * @brief Configure the Peripheral Voltage Monitoring (PVM). + * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information. + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly + * called for each PVM used. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level and to each monitored supply. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + + /* Configure EXTI 34 interrupts if so required: + scan through PVMType to detect which PVMx is set and + configure the corresponding EXTI line accordingly. */ + switch (sConfigPVM->PVMType) + { + case PWR_PVM_USB: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM_EXTI_DISABLE_IT(); + __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); + } + + if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* PWR_PVM_SUPPORT */ +/** + * @brief Enable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_EnableInternalWakeUpLine(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + + +/** + * @brief Disable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_DisableInternalWakeUpLine(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + * @note Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PUCRA, GPIONumber); + CLEAR_BIT(PWR->PDCRA, GPIONumber); + break; + + case PWR_GPIO_B: + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + + case PWR_GPIO_C: + SET_BIT(PWR->PUCRC, GPIONumber); + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; +#if defined (GPIOD) + case PWR_GPIO_D: + SET_BIT(PWR->PUCRD, GPIONumber); + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; +#endif /* GPIOD */ + case PWR_GPIO_F: + SET_BIT(PWR->PUCRF, GPIONumber); + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + * @note Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O + * in pull-up state in Standby and Shutdown modes. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PUCRA, GPIONumber); + break; + + case PWR_GPIO_B: + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + + case PWR_GPIO_C: + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; +#if defined (GPIOD) + case PWR_GPIO_D: + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; +#endif /* GPIOD */ + case PWR_GPIO_F: + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PDCRA, GPIONumber); + CLEAR_BIT(PWR->PUCRA, GPIONumber); + break; + + case PWR_GPIO_B: + SET_BIT(PWR->PDCRB, GPIONumber); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + + case PWR_GPIO_C: + SET_BIT(PWR->PDCRC, GPIONumber); + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; +#if defined (GPIOD) + case PWR_GPIO_D: + SET_BIT(PWR->PDCRD, GPIONumber); + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; +#endif /* GPIOD */ + case PWR_GPIO_F: + SET_BIT(PWR->PDCRF, GPIONumber); + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + * @note Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PDCRA, GPIONumber); + break; + + case PWR_GPIO_B: + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + + case PWR_GPIO_C: + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; +#if defined (GPIOD) + case PWR_GPIO_D: + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; +#endif /* GPIOD */ + case PWR_GPIO_F: + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there + * is no conflict when setting PUy or PDy bit. + * @retval None + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @retval None + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + + +/** + * @brief Enable Flash Power Down. + * @note This API allows to enable flash power down capabilities in sleep and stop modes. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_SLEEP + * @arg @ref PWR_FLASHPD_STOP + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + + PWR->CR1 |= PowerMode; +} + + +/** + * @brief Disable Flash Power Down. + * @note This API allows to disable flash power down capabilities in sleep and stop modes. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_SLEEP + * @arg @ref PWR_FLASHPD_STOP + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + + PWR->CR1 &= ~PowerMode; +} + + +/** + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. + * SRAM and registers contents are lost except for registers in the Backup domain. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can + * be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + * respectively enable Pull Up and PullDown state. + * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + * disable the same. These states are effective in Standby mode only if + * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @retval None + + * @retval None + */ +void HAL_PWREx_EnterSHUTDOWNMode(void) +{ + /* Set Shutdown mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif /* __CC_ARM */ + + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Extended PWR Backup register functions + * @brief Extended PWR Backup register functions + * +@verbatim + =============================================================================== + ##### Extended PWR Backup register functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified PWR Backup data register + (+) Read a data in a specified PWR Backup data register +@endverbatim + * @{ + */ + + +/** + * @brief Write a data in a specified PWR Backup data register. + * @param BackupRegister PWR Backup data Register number. + * This parameter can be PWR_BKP_DRx where x can be from 0 to PWR_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_PWREx_BKUPWrite(uint32_t BackupRegister, uint16_t Data) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_PWR_BKP(BackupRegister)); + + tmp = (uint32_t) &(PWR->BKP0R); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint16_t)Data; +} + + +/** + * @brief Reads data from the specified PWR Backup data Register. + * @param BackupRegister PWR Backup data Register number. + * This parameter can be PWR_BKP_DRx where x can be from 0 to PWR_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_PWREx_BKUPRead(uint32_t BackupRegister) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_PWR_BKP(BackupRegister)); + + tmp = (uint32_t) &(PWR->BKP0R); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c (revision 41) @@ -0,0 +1,1218 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from High Speed Internal oscillator + divided by 4 that is the default system clock with Flash 0 wait state. + + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses: + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (RTC, ADC, USART, I2C, I2S) + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define RCC_HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#if defined(RCC_CR_HSIUSB48ON) +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_CR_HSIUSB48ON */ +#define RCC_CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (IOPORT_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__)))) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, LSI, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB) + + [..] Internal/external clock + (+) HSI (high-speed internal): 48 MHz factory-trimmed RC used directly as System clock source. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + + (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs, + the System clock is automatically switched respectively to HSI or LSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt) + exception vector. + + (+) MCOx (microcontroller clock output): used to output LSI, HSI, LSE, HSE and SYSCLK on different pins. + + [..] System, AHB and APB busses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE, LSI and LSE. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. + You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + + (+@) ADC: the ADC clock can be derived either from system clock or HSI + + (+@) USART: the USART clock can be derived either from APB clock or HSI or LSE + (+@) I2C: the I2C clock can be derived either from system clock or HSI + + (+@) I2S: the I2S clock can be derived either from system clock or HSI or external clock source + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 48 MHz. + + (+) When the HSI48 oscillator is selected as the System clock (SYSCLK), the number of CPU wait states must + be adjusted before any eventual update on the HSI48 clock division factor. + + @endverbatim + + (++) Table 1. HCLK clock frequency. + (++) +------------------------------------+ + (++) | Latency | HCLK clock | + (++) | | frequency (MHz) | + (++) | |------------------| + (++) | | voltage range | + (++) | | VDD33 2V - 3.6V | + (++) | | VDD12 1V - 1.32V| + (++) |-----------------|------------------| + (++) |0WS(1 CPU cycles)| HCLK <= 24 | + (++) |-----------------|------------------| + (++) |1WS(2 CPU cycles)| HCLK <= 48 | + (++) +------------------------------------+ + (++) + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE OFF + * - SYSDIV, AHB and APB prescaler set to 1. + * - CSS, MCO1, MCO2 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + RCC->ICSCR = RCC_ICSCR_HSITRIM_6; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR register (HSI is selected as system clock source) */ + RCC->CFGR = 0x00000000u; + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ + RCC->CR &= ~RCC_CR_HSEON; + + /* Wait till HSEON is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Then again to HSEBYP in case bypass was enabled */ + RCC->CR &= ~RCC_CR_HSEBYP; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000u; + + /* Clear all flags */ + RCC->CICR = 0xFFFFFFFFu; + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * @ref RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then to HSE On or HSE Bypass. + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then to LSE On or LSE Bypass. + * @note When the HSI48 oscillator is selected as the System clock (SYSCLK), the user + must adjust the number of CPU wait states in their application (SystemClock_Config() API) + before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp_sysclksrc; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + + /* When the HSE is used as system clock in these cases it is not allowed to be disabled */ + if (temp_sysclksrc == RCC_CFGR_SWS_HSE) + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + + /* Check if HSI48 is used as system clock */ + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + + if (temp_sysclksrc == RCC_CFGR_SWS_HSI) + { + /* When HSI is used as system clock it can not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + + if (temp_sysclksrc == RCC_CFGR_SWS_HSI) + { + /* Adjust the HSI48 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + + /* Update the SystemCoreClock global variable with HSISYS value */ + SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); + } + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Configure the HSI48 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check if LSI is used as system clock */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) + { + /* When LSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* When the LSE is used as system clock, it is not allowed disable it */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) + { + if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Update LSE configuration in RTC Domain control register */ + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + } +#if defined(RCC_CR_HSIUSB48ON) + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIUSB48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIUSB48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } +#endif /* RCC_CR_HSIUSB48ON */ + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + * the HSI frequency is set to 12 Mhz, as HSI divider is set to 4. + * + * @note The HSI can be selected as system clock source after + * from STOP modes or in case of failure of the HSE used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * + * @note The LSI can be selected as system clock source after + * in case of failure of the LSE used directly or indirectly + * as system clock (if the Clock Security System LSECSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * + * @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + +#if defined(RCC_CR_SYSDIV) + MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider); +#endif /* RCC_CR_SYSDIV */ + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } +#if defined(RCC_HSI48_SUPPORT) + /* HSIUSB48 is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSIUSB48) + { + /* Check the HSIUSB48 ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIUSB48RDY) == 0U) + { + return HAL_ERROR; + } + } +#endif /* RCC_HSI48_SUPPORT */ + /* LSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) + { + /* Check the LSI ready flag */ + if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* LSE is selected as System Clock Source */ + else + { + /* Check the LSE ready flag */ + if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ + >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCOx pin. + * @note PA8 for MCO1 and PB2 for MCO2 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pins. + * @arg @ref RCC_MCO2 Clock source to output on MCO2 pins. + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO1 output disabled, no clock on MCO1 + * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO1 source (*) + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source + * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2 + * @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source (*) + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @note (*) peripheral not available on all devices + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio_initstruct; + uint32_t mcoindex; + uint32_t mco_gpio_index; + GPIO_TypeDef *mco_gpio_port; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + + /* Common GPIO init parameters */ + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; + + /* Get MCOx selection */ + mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; + + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); + + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->IOPENR, (1UL << mco_gpio_index)); + + /* Configure the MCOx pin in alternate function mode */ + gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); + + if (mcoindex == RCC_MCO1_INDEX) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); + } + else if (mcoindex == RCC_MCO2_INDEX) + { + assert_param(IS_RCC_MCO2DIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + LL_RCC_ConfigMCO2(RCC_MCOSource, RCC_MCODiv); + } + else + { + /* unexpected case: added to resolve MISRA 15.7 rule */ + } +} + +/** + * @brief Return the SYSCLK frequency. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is LSI, function returns values based on LSI_VALUE(***) + * @note If SYSCLK source is LSE, function returns values based on LSE_VALUE(****) + * @note (*) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 48 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 48 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note (***) LSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 32768 Hz). + * @note (****) LSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 32000 Hz). + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t hsidiv; + uint32_t sysclockfreq; +#if defined(RCC_CR_SYSDIV) + uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U); +#endif /* RCC_CR_SYSDIV */ + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + { + /* HSISYS can be derived for HSI48 */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + + /* HSI used as system clock source */ + sysclockfreq = (HSI_VALUE / hsidiv); + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) + { + /* LSE used as system clock source */ + sysclockfreq = LSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) + { + /* LSI used as system clock source */ + sysclockfreq = LSI_VALUE; + } +#if defined(RCC_HSI48_SUPPORT) + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI48) + { + /* HSI48 used as system clock source */ + sysclockfreq = HSI48_VALUE; + } +#endif /* RCC_HSI48_SUPPORT */ + else + { + sysclockfreq = 0U; + } +#if defined(RCC_CR_SYSDIV) + sysclockfreq = sysclockfreq / sysclockdiv; +#endif /* RCC_CR_SYSDIV */ + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ + >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU)); +} + +/** + * @brief Configure the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t regval; + + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; +#else + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +#endif /* RCC_HSI48_SUPPORT */ + /* Get Control register */ + regval = RCC->CR; + + /* Get the HSE configuration -----------------------------------------------*/ + RCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP)); + + /* Get the HSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->HSIState = regval & RCC_CR_HSION; + RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); + RCC_OscInitStruct->HSIDiv = ((regval & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + + /* Get CSR1 register */ + regval = RCC->CSR1; + + /* Get the LSE configuration -----------------------------------------------*/ + RCC_OscInitStruct->LSEState = (regval & (RCC_CSR1_LSEON | RCC_CSR1_LSEBYP)); + + /* Get CSR2 register */ + regval = RCC->CSR2; + + /* Get the LSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->LSIState = regval & RCC_CSR2_LSION; + +#if defined(RCC_HSI48_SUPPORT) + /* Get the HSI48 configuration ---------------------------------------------*/ + if (READ_BIT(RCC->CR, RCC_CR_HSIUSB48ON) == RCC_CR_HSIUSB48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } +#endif /* RCC_HSI48_SUPPORT */ + +} + +/** + * @brief Configure the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + +#if defined(RCC_CR_SYSDIV) + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CR & RCC_CR_SYSDIV); +#else + RCC_ClkInitStruct->SYSCLKDivider = RCC_SYSCLK_DIV1; +#endif /* RCC_CR_SYSDIV */ + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Enable the LSE Clock Security System. + * @note If a failure is detected on the LSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. + * @note The LSE Clock Security System Detection bit (LSECSSD in CSR1) can only be + * cleared by a backup domain reset. + * @retval None + */ +void HAL_RCC_EnableLSECSS(void) +{ + SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON) ; +} + +/** + * @brief Disable the LSE Clock Security System. + * @note After LSE failure detection, the software must disable LSECSSON + * @note The Clock Security System can only be cleared by reset otherwise. + * @retval None + */ +void HAL_RCC_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON) ; +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + uint32_t itflag = RCC->CIFR; + + /* Clear interrupt flags related to CSS */ + RCC->CICR = (itflag & (RCC_CIFR_CSSF | RCC_CIFR_LSECSSF)); + + /* Check RCC CSSF interrupt flag */ + if ((itflag & RCC_CIFR_CSSF) != 0x00u) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } + + /* Check RCC LSECSSF interrupt flag */ + if ((itflag & RCC_CIFR_LSECSSF) != 0x00u) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_LSECSSCallback(); + } +} + +/** + * @brief Handle the RCC HSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @brief RCC LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_LSECSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_LSECSSCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c (revision 41) @@ -0,0 +1,928 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LSCO_GPIO_PORT GPIOA +#define LSCO_PIN GPIO_PIN_2 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; as consequence RTC registers and RCC_CSR1 register are + set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the @ref RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock (*) + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to RTC domain is enabled. + * @note (*) not available on all devices + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpregister; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + FlagStatus pwrclkchanged = RESET; + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + + /* Reset the RTC domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL); + + /* Reset the RTC domain only if the RTC Clock source selection is modified */ + if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) + { + /* Store the content of CSR1 register before the reset of RTC Domain */ + tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL)); + /* RTC Clock selection can be changed only if the RTC Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of CSR1 register */ + RCC->CSR1 = tmpregister; + } + + /* Wait for LSE reactivation if LSE was enable prior to RTC Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + + } +#if defined (USB_DRD_FS) + /*-------------------------- USB clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + + } +#endif /* USB_DRD_FS */ +#if defined (FDCAN1) + /*-------------------------- FDCAN1 clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == RCC_PERIPHCLK_FDCAN1) + { + /* Check the parameters */ + assert_param(IS_RCC_FDCAN1CLKSOURCE(PeriphClkInit->Fdcan1ClockSelection)); + + /* Configure the FDCAN1 clock source */ + __HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection); + + } +#endif /* FDCAN1 */ + /*-------------------------- I2S1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); + + /* Configure the I2S1 clock source */ + __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); + } + /*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER) + { + /* Check the parameters */ + assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider)); + + /* Configure the HSI Kernel clock source Divider */ + __HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider); + } + return status; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals + * clocks: I2C1, I2S1, USART1, RTC, ADC, + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2S1 | \ + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_HSIKER ; + +#if defined(USB_DRD_FS) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif /* USB_DRD_FS */ +#if defined(FDCAN1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN1; +#endif /* FDCAN1 */ + /* Get the USART1 clock source ---------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + + /* Get the ADC clock source -----------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + +#if defined (USB_DRD_FS) + /* Get the USB clock source -------------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* USB_DRD_FS */ + +#if defined (FDCAN1) + /* Get the FDCAN1 clock source -------------------------------------------------*/ + PeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE(); +#endif /* FDCAN1 */ + + /* Get the I2S1 clock source -----------------------------------------------*/ + PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE(); + + /* Get the HSI Kernel clock divider -----------------------------------------------*/ + PeriphClkInit->HSIKerClockDivider = __HAL_RCC_GET_HSIKER_DIVIDER(); +} + +/** + * @brief Return the peripheral clock frequency for peripherals + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock (*) + * @note (*) not available on all devices + * @retval Frequency in Hz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0U; + uint32_t srcclk; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + if (PeriphClk == RCC_PERIPHCLK_RTC) + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->CSR1, RCC_CSR1_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->CSR2, RCC_CSR2_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) + { + frequency = HSE_VALUE / 32U; + } + /* Clock not enabled for RTC*/ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + } + else + { + /* Other external peripheral clock source than RTC */ + + switch (PeriphClk) + { + + case RCC_PERIPHCLK_USART1: + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) /* PCLK1 */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) /* SYSCLK */ + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSIKER)) + { + frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + else if ((HAL_IS_BIT_SET(RCC->CSR1, RCC_CSR1_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case RCC_PERIPHCLK_ADC: + + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + if (srcclk == RCC_ADCCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCCLKSOURCE_HSIKER)) + { + frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + /* Clock not enabled for ADC */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case RCC_PERIPHCLK_I2C1: + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSIKER)) + { + frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + /* Clock not enabled for I2C1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case RCC_PERIPHCLK_I2S1: + /* Get the current I2S1 source */ + srcclk = __HAL_RCC_GET_I2S1_SOURCE(); + + if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSIKER)) + { + frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + else if (srcclk == RCC_I2S1CLKSOURCE_EXT) + { + /* External clock used.*/ + frequency = EXTERNAL_I2S1_CLOCK_VALUE; + } + /* Clock not enabled for I2S1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#if defined(FDCAN1) + case RCC_PERIPHCLK_FDCAN1: + /* Get the current FDCAN1 source */ + srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + + if (srcclk == RCC_FDCAN1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSIKER)) + { + frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_HSE) + { + /* External clock used.*/ + frequency = HSE_VALUE; + } + /* Clock not enabled for FDCAN1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* FDCAN1 */ +#if defined (USB_DRD_FS) + case RCC_PERIPHCLK_USB: + /* Get the current USB source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + if (srcclk == RCC_USBCLKSOURCE_HSI48) + { + frequency = HSI48_VALUE; + } + else if (srcclk == RCC_USBCLKSOURCE_HSE) + { + frequency = HSE_VALUE; + } + /* Clock not enabled for USB */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } +#endif /* USB_DRD_FS */ + default: + break; + } + } + + return (frequency); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of LSE CSS, Low speed clock output and + clock after wake-up from STOP mode. +@endverbatim + * @{ + */ + +/** + * @brief Select the Low Speed clock source to output on LSCO pin (PA2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* LSCO Pin Clock Enable */ + LSCO_CLK_ENABLE(); + + /* configure the LSCO pin in analog mode */ + GPIO_InitStruct.Pin = LSCO_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); + + MODIFY_REG(RCC->CSR1, RCC_CSR1_LSCOSEL | RCC_CSR1_LSCOEN, LSCOSource | RCC_CSR1_LSCOEN); + +} + +/** + * @brief Disable the Low Speed clock output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + + CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSCOEN); + +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; /* no init needed */ + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c (revision 41) @@ -0,0 +1,7900 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup TIM_Private_Constants + * @{ + */ +#define TIMx_OR1_OCREF_CLR 0x00000001U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c (revision 41) @@ -0,0 +1,2807 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Time OCRef clear configuration + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected (*) + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + +#if defined(USB_BASE) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR7)) +#else + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) +#endif /* USB_BASE */ + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + +#if defined(USB_BASE) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR7)) +#else + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) +#endif /* USB_BASE */ + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + +#if defined(USB_BASE) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR7)) +#else + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) +#endif /* USB_BASE */ + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM_AF1_BKINE; + bkin_enable_bitpos = TIM_AF1_BKINE_Pos; + bkin_polarity_mask = TIM_AF1_BKINP; + bkin_polarity_bitpos = TIM_AF1_BKINP_Pos; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can take one of the following values: + * @arg TIM_TIM1_ETR_GPIO: TIM1 ETR is is connected to GPIO + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1 ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1 ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1 ETR is connected to ADC1 AWD3 + * + * For TIM2, the parameter can take one of the following values: (*) + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_MCO: TIM2_ETR is connected to MCO + * @arg TIM_TIM2_ETR_MCO2: TIM2_ETR is connected to MCO2 + * + * For TIM3, the parameter can take one of the following values: + * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is connected to GPIO + * + * (*) Timer instance not available on all devices \n + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @param TISelection specifies the timer input source + * + * For TIM14, the parameter is one of the following values: + * @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_TI1_RTC: TIM14 TI1 is connected to RTC clock + * @arg TIM_TIM14_TI1_HSE_32: TIM14 TI1 is connected to HSE div 32 + * @arg TIM_TIM14_TI1_MCO: TIM14 TI1 is connected to MCO + * @arg TIM_TIM14_TI1_MCO2: TIM14 TI1 is connected to MCO2 + * + * For TIM15, the parameter is one of the following values: (*) + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2 + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_MCO2: TIM16 TI1 is connected to MCO2 + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 + * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO + * @arg TIM_TIM17_TI1_MCO2: TIM17 TI1 is connected to MCO2 + * + * (*) Timer instance not available on all devices \n + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c (revision 41) @@ -0,0 +1,4737 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { +#endif /* HAL_DMA_MODULE_ENABLED */ + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; +#if defined(HAL_DMA_MODULE_ENABLED) + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + tmpreg |= huart->Init.OneBitSampling; + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + Index: /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c =================================================================== --- /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c (revision 41) +++ /trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c (revision 41) @@ -0,0 +1,1088 @@ +/** + ****************************************************************************** + * @file stm32c0xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + [..] + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/** @addtogroup STM32C0xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of Wakeup and FIFO mode related callback functions. + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + (#) TX/RX Fifos Callbacks: + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (+++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (++) Detection that a specific character has been received. + + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (++) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (++) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (++) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper + * alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data copy from RDR will be + handled by DMA from a uint16_t frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h (revision 41) @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h (revision 41) @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h (revision 41) @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h (revision 41) @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h (revision 41) @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h (revision 41) @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h (revision 41) @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_version.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_version.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/cmsis_version.h (revision 41) @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h (revision 41) @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h (revision 41) @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h (revision 41) @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm0.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm0.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm0.h (revision 41) @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h (revision 41) @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm1.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm1.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm1.h (revision 41) @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm23.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm23.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm23.h (revision 41) @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm3.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm3.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm3.h (revision 41) @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm33.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm33.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm33.h (revision 41) @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm35p.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm35p.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm35p.h (revision 41) @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm4.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm4.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm4.h (revision 41) @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm55.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm55.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm55.h (revision 41) @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm7.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm7.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm7.h (revision 41) @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm85.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm85.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_cm85.h (revision 41) @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_sc000.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_sc000.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_sc000.h (revision 41) @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_sc300.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_sc300.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_sc300.h (revision 41) @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_starmc1.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_starmc1.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/core_starmc1.h (revision 41) @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h (revision 41) @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h (revision 41) @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/pac_armv81.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/pac_armv81.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/pac_armv81.h (revision 41) @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h (revision 41) @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif Index: /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/tz_context.h =================================================================== --- /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/tz_context.h (revision 41) +++ /trunk/firmware_v3/SES/CMSIS_5/CMSIS/Core/Include/tz_context.h (revision 41) @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H Index: /trunk/firmware_v3/SES/Output/Debug/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1986 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44.2 compiled Apr 14 2025 15:08:43 + Copyright (c) 2017-2024 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 23 966 2 088 9 584 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 218 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 24 212 2 088 9 584 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_small.a 2 164 32 + mbops_timeops_v6m_t_le_eabi_small.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_small.a 476 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_small.a 74 + strops_v6m_t_le_eabi_small.a 34 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 2 938 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 80 2 048 + ============================================= ========== ========== ========== ========== + Total: 27 150 2 767 41 3 856 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + 836 + fileops.o (libc_v6m_t_le_eabi_small.a) 50 + floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 598 + intasmops_arm.o (libc_v6m_t_le_eabi_small.a) 308 + mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_small.a) 372 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 62 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 414 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 34 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (10 members from 5 archives) 2 938 599 32 1 224 + Objects (4 files) 24 212 2 088 9 584 + Linker created (shared data, fills, blocks): 80 2 048 + ============================================= ========== ========== ========== ========== + Total: 27 150 2 767 41 3 856 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 80 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 80 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 24 212 2 088 9 584 + Archives (5 files) 2 938 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 27 150 2 767 41 3 856 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000b3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000b4-08000197 MX_ADC1_Init 228 4 Code RX PowerPro_lto.o + 08000198-0800026f HAL_ADC_MspInit 216 4 Code RX PowerPro_lto.o + 08000270-0800029f MX_DMA_Init 48 4 Code RX PowerPro_lto.o + 080002a0-0800039b MX_GPIO_Init 252 4 Code RX PowerPro_lto.o + 0800039c-080003cf HAL_MspInit 52 4 Code RX PowerPro_lto.o + 080003d0-080003df DMA1_Channel1_IRQHandler 16 4 Code RX PowerPro_lto.o + 080003e0-080003ef TIM16_IRQHandler 16 4 Code RX PowerPro_lto.o + 080003f0-08000447 HAL_TIM_IC_CaptureCallback + 88 4 Code RX PowerPro_lto.o + 08000448-0800047b HAL_TIM_PeriodElapsedCallback + 52 4 Code RX PowerPro_lto.o + 0800047c-0800048b SystemInit 16 4 Code RX PowerPro_lto.o + 0800048c-080005b7 SystemCoreClockUpdate 300 4 Code RX PowerPro_lto.o + 080005b8-08000627 MX_TIM16_Init 112 4 Code RX PowerPro_lto.o + 08000628-080006d7 MX_TIM17_Init 176 4 Code RX PowerPro_lto.o + 080006d8-0800073f HAL_TIM_MspPostInit 104 4 Code RX PowerPro_lto.o + 08000740-080007e7 HAL_TIM_Base_MspInit 168 4 Code RX PowerPro_lto.o + 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+*** SYMBOL LIST *** +*** *** +*********************************************************************************************** + +Function symbols by name: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + ADC1_IRQHandler 0x080060AD 2 Code Wk stm32c031xx_Vectors.o + ADC_DMAConvCplt 0x08006519 168 2 Code Lc PowerPro_lto.o + ADC_DMAError 0x08005BAF 42 2 Code Lc PowerPro_lto.o + ADC_DMAHalfConvCplt 0x08005B99 22 2 Code Lc PowerPro_lto.o + ADC_Disable 0x08006475 164 2 Code Lc PowerPro_lto.o + ADC_Enable 0x08000C01 224 4 Code Lc PowerPro_lto.o + BUTTON_Exec 0x08003451 204 4 Code Lc PowerPro_lto.o + BUTTON_GetMode 0x0800351D 12 4 Code Lc PowerPro_lto.o + BUTTON_SetModeOff 0x08003529 12 4 Code Lc PowerPro_lto.o + BUZZER_Alarm_Start 0x080035CD 64 4 Code Lc PowerPro_lto.o + BUZZER_Alarm_Stop 0x0800360D 52 4 Code Lc PowerPro_lto.o + BUZZER_Beep 0x080035A9 36 4 Code Lc PowerPro_lto.o + BUZZER_Exec 0x08003535 116 4 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_Calibration + 0x08003641 64 4 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_Exec 0x08003681 84 4 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_GetTemp 0x080036D5 12 4 Code Lc PowerPro_lto.o + DMA1_Channel1_IRQHandler 0x080003D1 16 4 Code Gb PowerPro_lto.o + DMA1_Channel2_3_IRQHandler + 0x080060A9 2 Code Wk stm32c031xx_Vectors.o + DMAMUX1_IRQHandler 0x080060AB 2 Code Wk stm32c031xx_Vectors.o + DMA_CalcDMAMUXChannelBaseAndMask + 0x08001645 68 4 Code Lc PowerPro_lto.o + DMA_CalcDMAMUXRequestGenBaseAndMask + 0x08001689 56 4 Code Lc PowerPro_lto.o + DMA_SetConfig 0x080016C1 112 4 Code Lc PowerPro_lto.o + EXTI0_1_IRQHandler 0x080060A3 2 Code Wk stm32c031xx_Vectors.o + EXTI2_3_IRQHandler 0x080060A5 2 Code Wk stm32c031xx_Vectors.o + EXTI4_15_IRQHandler 0x080060A7 2 Code Wk stm32c031xx_Vectors.o + Error_Handler 0x08006815 4 2 Code Lc PowerPro_lto.o + FAN_SetSpeed 0x080036E1 72 4 Code Lc PowerPro_lto.o + FLASH_IRQHandler 0x0800609F 2 Code Wk stm32c031xx_Vectors.o + HAL_ADCEx_Calibration_Start + 0x08001261 456 4 Code Lc PowerPro_lto.o + HAL_ADC_ConfigChannel 0x08000E15 1 000 4 Code Lc PowerPro_lto.o + HAL_ADC_ConvCpltCallback 0x080065D1 8 2 Code Lc PowerPro_lto.o + HAL_ADC_ConvHalfCpltCallback + 0x080065C9 8 2 Code Lc PowerPro_lto.o + HAL_ADC_ErrorCallback 0x080065C1 8 2 Code Lc PowerPro_lto.o + HAL_ADC_Init 0x080008C1 772 4 Code Lc PowerPro_lto.o + HAL_ADC_MspInit 0x08000199 216 4 Code Lc PowerPro_lto.o + HAL_ADC_Start_DMA 0x08000D19 252 4 Code Lc PowerPro_lto.o + HAL_DMA_IRQHandler 0x08001731 320 4 Code Lc PowerPro_lto.o + HAL_DMA_Init 0x08001555 240 4 Code Lc PowerPro_lto.o + HAL_DMA_Start_IT 0x0800664D 236 2 Code Lc PowerPro_lto.o + HAL_Delay 0x08000885 60 4 Code Lc PowerPro_lto.o + HAL_GPIO_Init 0x08001871 704 4 Code Lc PowerPro_lto.o + HAL_GPIO_ReadPin 0x08005C7B 46 2 Code Lc PowerPro_lto.o + HAL_GPIO_WritePin 0x08006739 40 2 Code Lc PowerPro_lto.o + HAL_GetTick 0x08000879 12 4 Code Lc PowerPro_lto.o + HAL_IWDG_Init 0x08003395 164 4 Code Lc PowerPro_lto.o + HAL_IWDG_Refresh 0x08003439 24 4 Code Lc PowerPro_lto.o + HAL_IncTick 0x08000861 24 4 Code Lc PowerPro_lto.o + HAL_Init 0x0800640D 40 2 Code Lc PowerPro_lto.o + HAL_InitTick 0x080007E9 120 4 Code Lc PowerPro_lto.o + HAL_MspInit 0x0800039D 52 4 Code Lc PowerPro_lto.o + HAL_NVIC_EnableIRQ 0x08005C65 22 2 Code Lc PowerPro_lto.o + HAL_NVIC_SetPriority 0x08006621 28 2 Code Lc PowerPro_lto.o + HAL_RCCEx_PeriphCLKConfig 0x080021AD 396 4 Code Lc PowerPro_lto.o + HAL_RCC_ClockConfig 0x08001ECD 512 4 Code Lc PowerPro_lto.o + HAL_RCC_GetHCLKFreq 0x08002151 52 4 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 0x08002185 40 4 Code Lc PowerPro_lto.o + HAL_RCC_GetSysClockFreq 0x080020CD 132 4 Code Lc PowerPro_lto.o + HAL_RCC_OscConfig 0x08001B31 924 4 Code Lc PowerPro_lto.o + HAL_SYSTICK_Config 0x0800663D 16 2 Code Lc PowerPro_lto.o + HAL_TIMEx_Break2Callback 0x0800680D 8 2 Code Lc PowerPro_lto.o + HAL_TIMEx_BreakCallback 0x08006805 8 2 Code Lc PowerPro_lto.o + HAL_TIMEx_CommutCallback 0x080067FD 8 2 Code Lc PowerPro_lto.o + HAL_TIMEx_ConfigBreakDeadTime + 0x08003255 276 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 0x08005CA9 154 2 Code Lc PowerPro_lto.o + HAL_TIM_Base_MspInit 0x08000741 168 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Start_IT 0x08002411 144 4 Code Lc PowerPro_lto.o + HAL_TIM_IC_CaptureCallback + 0x080003F1 88 4 Code Lc PowerPro_lto.o + HAL_TIM_IC_ConfigChannel 0x08005EA9 278 2 Code Lc PowerPro_lto.o + HAL_TIM_IC_Init 0x08005E0F 154 2 Code Lc PowerPro_lto.o + HAL_TIM_IC_MspInit 0x08006771 8 2 Code Lc PowerPro_lto.o + HAL_TIM_IC_Start_IT 0x08002649 652 4 Code Lc PowerPro_lto.o + HAL_TIM_IRQHandler 0x080028D5 520 4 Code Lc PowerPro_lto.o + HAL_TIM_MspPostInit 0x080006D9 104 4 Code Lc PowerPro_lto.o + HAL_TIM_OC_DelayElapsedCallback + 0x08006779 8 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_ConfigChannel 0x0800306D 488 4 Code Lc PowerPro_lto.o + HAL_TIM_PWM_Init 0x08005D75 154 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_MspInit 0x08006769 8 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_PulseFinishedCallback + 0x08006761 8 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_Start 0x080024A1 424 4 Code Lc PowerPro_lto.o + HAL_TIM_PeriodElapsedCallback + 0x08000449 52 4 Code Lc PowerPro_lto.o + HAL_TIM_ReadCapturedValue 0x08005AA1 126 4 Code Lc PowerPro_lto.o + HAL_TIM_TriggerCallback 0x08006781 8 2 Code Lc PowerPro_lto.o + HardFault_Handler 0x08005B21 2 2 Code Gb PowerPro_lto.o + I2C1_IRQHandler 0x080060B9 2 Code Wk stm32c031xx_Vectors.o + LEDS_Exec 0x08003729 280 4 Code Lc PowerPro_lto.o + LEDS_GN_Blink_Start 0x0800386D 64 4 Code Lc PowerPro_lto.o + LEDS_GN_Off 0x080038AD 52 4 Code Lc PowerPro_lto.o + LEDS_GN_On 0x08003841 44 4 Code Lc PowerPro_lto.o + LEDS_RT_BlinkCode_Start 0x080038E1 100 4 Code Lc PowerPro_lto.o + LEDS_RT_Off 0x08003945 52 4 Code Lc PowerPro_lto.o + LL_ADC_Disable 0x08000BE5 28 4 Code Lc PowerPro_lto.o + LL_ADC_Disable.11 0x08001445 28 4 Code Lc PowerPro_lto.o + LL_ADC_Enable 0x08000CFD 28 4 Code Lc PowerPro_lto.o + LL_ADC_Enable.10 0x08001429 28 4 Code Lc PowerPro_lto.o + LL_ADC_EnableInternalRegulator + 0x08000BC5 32 4 Code Lc PowerPro_lto.o + LL_ADC_GetCalibrationFactor + 0x08005C2F 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetClock 0x08005C41 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetCommonClock 0x08005C53 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetCommonPathInternalCh + 0x08005B71 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetSamplingTimeCommonChannels + 0x08006459 28 2 Code Lc PowerPro_lto.o + LL_ADC_IsCalibrationOnGoing + 0x08005C21 14 2 Code Lc PowerPro_lto.o + LL_ADC_IsDisableOngoing 0x08005B5F 18 2 Code Lc PowerPro_lto.o + LL_ADC_IsEnabled 0x08006449 16 2 Code Lc PowerPro_lto.o + LL_ADC_IsEnabled.9 0x080065F5 16 2 Code Lc PowerPro_lto.o + LL_ADC_IsInternalRegulatorEnabled + 0x08006435 20 2 Code Lc PowerPro_lto.o + LL_ADC_REG_IsConversionOngoing + 0x08005B27 18 2 Code Lc PowerPro_lto.o + LL_ADC_REG_IsTriggerSourceSWStart + 0x08005B83 22 2 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerChAdd + 0x080011FD 28 4 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerChRem + 0x08001241 32 4 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerRanks + 0x08005BD9 46 2 Code Lc PowerPro_lto.o + LL_ADC_REG_StartConversion + 0x08000CE1 28 4 Code Lc PowerPro_lto.o + LL_ADC_SetCalibrationFactor + 0x08006605 28 2 Code Lc PowerPro_lto.o + LL_ADC_SetChannelSamplingTime + 0x08001219 40 4 Code Lc PowerPro_lto.o + LL_ADC_SetCommonPathInternalCh + 0x080065D9 28 2 Code Lc PowerPro_lto.o + LL_ADC_SetSamplingTimeCommonChannels + 0x08005B39 38 2 Code Lc PowerPro_lto.o + LL_ADC_StartCalibration 0x08005C07 26 2 Code Lc PowerPro_lto.o + LVP_OVP_SM_Error 0x08004329 176 4 Code Lc PowerPro_lto.o + LVP_OVP_SM_ManualOn 0x080042F9 48 4 Code Lc PowerPro_lto.o + LVP_OVP_SM_Off 0x0800403D 200 4 Code Lc PowerPro_lto.o + LVP_OVP_SM_On 0x08004105 500 4 Code Lc PowerPro_lto.o + LVP_SM_Error 0x08003F45 176 4 Code Lc PowerPro_lto.o + LVP_SM_ManualOn 0x08003F15 48 4 Code Lc PowerPro_lto.o + LVP_SM_Off 0x08003C69 200 4 Code Lc PowerPro_lto.o + LVP_SM_On 0x08003D31 484 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_Error 0x0800459D 176 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_ManualOn 0x0800456D 48 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_Off 0x080043D9 200 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_On 0x080044A1 204 4 Code Lc PowerPro_lto.o + MODESWITCH_GetMode 0x08005259 12 4 Code Lc PowerPro_lto.o + MODESWITCH_ReadMode 0x080051E1 120 4 Code Lc PowerPro_lto.o + MODE_LVP_Exec 0x08003C21 72 4 Code Lc PowerPro_lto.o + MODE_LVP_OVP_Exec 0x08003FF5 72 4 Code Lc PowerPro_lto.o + MODE_MAINSWITCH_Exec 0x0800464D 72 4 Code Lc PowerPro_lto.o + MODE_OVP_Exec 0x08004695 72 4 Code Lc PowerPro_lto.o + MODE_SECONDARYPROTECTION_Exec + 0x08004A59 72 4 Code Lc PowerPro_lto.o + MODE_SECONDARYPROTECTION_PLUS_Exec + 0x08004EC5 56 4 Code Lc PowerPro_lto.o + MX_ADC1_Init 0x080000B5 228 4 Code Lc PowerPro_lto.o + MX_DMA_Init 0x08000271 48 4 Code Lc PowerPro_lto.o + MX_GPIO_Init 0x080002A1 252 4 Code Lc PowerPro_lto.o + MX_IWDG_Init 0x08003369 44 4 Code Lc PowerPro_lto.o + MX_TIM16_Init 0x080005B9 112 4 Code Lc PowerPro_lto.o + MX_TIM17_Init 0x08000629 176 4 Code Lc PowerPro_lto.o + NMI_Handler 0x08005B1F 2 2 Code Gb PowerPro_lto.o + OVP_SM_Error 0x080049A9 176 4 Code Lc PowerPro_lto.o + OVP_SM_ManualOn 0x08004979 48 4 Code Lc PowerPro_lto.o + OVP_SM_Off 0x080046DD 200 4 Code Lc PowerPro_lto.o + OVP_SM_On 0x080047A5 468 4 Code Lc PowerPro_lto.o + PendSV_Handler 0x08005B25 2 2 Code Gb PowerPro_lto.o + RCC_IRQHandler 0x080060A1 2 Code Wk stm32c031xx_Vectors.o + RELAIS_Exec 0x08005265 80 4 Code Lc PowerPro_lto.o + RELAIS_GetState 0x08005325 12 4 Code Lc PowerPro_lto.o + RELAIS_ResetPuls 0x080052ED 56 4 Code Lc PowerPro_lto.o + RELAIS_SetPuls 0x080052B5 56 4 Code Lc PowerPro_lto.o + RTC_IRQHandler 0x0800609D 2 Code Wk stm32c031xx_Vectors.o + Reset_Handler 0x08006819 2 Code Gb STM32C0xx_Startup.o + SECONDARYPROTECTION_SM_Error + 0x08004E15 176 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Error.160 + 0x08005175 108 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_ManualOn + 0x08004D65 176 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Off + 0x08004AA1 240 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Off.158 + 0x08004EFD 180 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On 0x08004B91 468 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.159 + 0x08004FB1 452 4 Code Lc PowerPro_lto.o + SEGGER_RTT_Write 0x08005999 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + SEGGER_RTT_WriteNoLock 0x08005931 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + SPI1_IRQHandler 0x080060BB 2 Code Wk stm32c031xx_Vectors.o + SVC_Handler 0x08005B23 2 2 Code Gb PowerPro_lto.o + SysTick_Config 0x08001509 76 4 Code Lc PowerPro_lto.o + SysTick_Handler 0x08006405 8 2 Code Gb PowerPro_lto.o + SystemClock_Config 0x08003BB1 112 4 Code Lc PowerPro_lto.o + SystemCoreClockUpdate 0x0800048D 300 4 Code Gb PowerPro_lto.o + SystemInit 0x0800047D 16 4 Code Gb PowerPro_lto.o + TIM14_IRQHandler 0x080060B5 2 Code Wk stm32c031xx_Vectors.o + TIM16_IRQHandler 0x080003E1 16 4 Code Gb PowerPro_lto.o + TIM17_IRQHandler 0x080060B7 2 Code Wk stm32c031xx_Vectors.o + TIM1_BRK_UP_TRG_COM_IRQHandler + 0x080060AF 2 Code Wk stm32c031xx_Vectors.o + TIM1_CC_IRQHandler 0x080060B1 2 Code Wk stm32c031xx_Vectors.o + TIM3_IRQHandler 0x080060B3 2 Code Wk stm32c031xx_Vectors.o + TIM_Base_SetConfig 0x08002339 216 4 Code Lc PowerPro_lto.o + TIM_CCxChannelCmd 0x08005D43 50 2 Code Lc PowerPro_lto.o + TIM_OC1_SetConfig 0x08002ADD 236 4 Code Lc PowerPro_lto.o + TIM_OC2_SetConfig 0x08002BC9 260 4 Code Lc PowerPro_lto.o + TIM_OC3_SetConfig 0x08002CCD 260 4 Code Lc PowerPro_lto.o + TIM_OC4_SetConfig 0x08002DD1 180 4 Code Lc PowerPro_lto.o + TIM_OC5_SetConfig 0x08002E85 168 4 Code Lc PowerPro_lto.o + TIM_OC6_SetConfig 0x08002F2D 168 4 Code Lc PowerPro_lto.o + TIM_TI1_SetConfig 0x08002FD5 152 4 Code Lc PowerPro_lto.o + TIM_TI2_SetConfig 0x08005FBF 110 2 Code Lc PowerPro_lto.o + TIM_TI3_SetConfig 0x0800602D 110 2 Code Lc PowerPro_lto.o + TIM_TI4_SetConfig 0x08006789 116 2 Code Lc PowerPro_lto.o + USART1_IRQHandler 0x080060BD 2 Code Wk stm32c031xx_Vectors.o + USART2_IRQHandler 0x080060BF 2 Code Wk stm32c031xx_Vectors.o + VOLTAGE_MEAS_Exec 0x08005331 204 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetLimitAlarm + 0x080053FD 36 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetUin 0x0800542D 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetUout 0x08005439 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_ResetCounter 0x08005421 12 4 Code Lc PowerPro_lto.o + WWDG_IRQHandler 0x0800609B 2 Code Wk stm32c031xx_Vectors.o + _DoInit 0x080058DD 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + _GetAvailWriteSpace 0x08006303 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + _WriteBlocking 0x08006353 90 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + _WriteNoCheck 0x08006319 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + __NVIC_EnableIRQ 0x080014E1 40 4 Code Lc PowerPro_lto.o + __NVIC_SetPriority 0x08001461 128 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_X_file_bufsize + 0x08006A69 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + __SEGGER_RTL_X_file_stat 0x080058AD 48 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + __SEGGER_RTL_X_file_write 0x080062F9 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_isctype + 0x080059E5 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_iswctype + 0x08005A01 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_mbtowc 0x080063BB 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_tolower + 0x080063E9 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_toupper + 0x08006A91 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_towlower + 0x080063F7 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_towupper + 0x08006A9D 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_wctomb 0x08006A81 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_current_locale + 0x080059D1 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_init_prin_l 0x080062CD 18 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_prin_flush 0x080062B3 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_putc 0x08006229 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_stream_write 0x08006A59 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_vfprintf 0x08005569 836 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_vfprintf_int_nwp + 0x08005569 836 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_init_copy 0x080074CF 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + __SEGGER_init_ctors 0x08007449 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + __SEGGER_init_done 0x080054AF 4 Code Gb SEGGER_THUMB_Startup.o + __SEGGER_init_zero 0x080074BD 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + __aeabi_d2iz 0x080068E5 52 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_d2uiz 0x080061A9 46 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_ddiv 0x08006821 196 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_f2uiz 0x08006919 36 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_fmul 0x080060F3 182 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_i2d 0x080054B9 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_idiv 0x08006959 64 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_idiv0 0x08006223 6 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_lmul 0x080061F5 46 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memclr 0x08006A6D 20 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memclr4 0x08006A6D 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memclr8 0x08006A6D 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memcpy 0x080063AD 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memcpy4 0x080063AD 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memcpy8 0x080063AD 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memset 0x08006A6F 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memset4 0x08006A6F 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memset8 0x08006A6F 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_ui2d 0x0800693D 28 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_ui2f 0x080061D7 30 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_uidiv 0x08006999 56 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_uldivmod 0x080069D1 136 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __startup_complete 0x080054AF 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x080054A5 14 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x080054B3 2 4 Code Gb SEGGER_THUMB_Startup.o + fwrite 0x080060C1 50 2 Code Wk fileops.o (libc_v6m_t_le_eabi_small.a) + main 0x08003979 568 4 Code Gb PowerPro_lto.o + memcpy 0x080063AD 14 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + memset 0x08006A75 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + printf 0x08005541 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + reset_handler 0x08006819 2 Code Gb STM32C0xx_Startup.o + vfprintf 0x080062DF 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + vfprintf_l 0x080054D5 108 4 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 MX_ADC1_Init 228 4 Code Lc PowerPro_lto.o + 0x08000199 HAL_ADC_MspInit 216 4 Code Lc PowerPro_lto.o + 0x08000271 MX_DMA_Init 48 4 Code Lc PowerPro_lto.o + 0x080002A1 MX_GPIO_Init 252 4 Code Lc PowerPro_lto.o + 0x0800039D HAL_MspInit 52 4 Code Lc PowerPro_lto.o + 0x080003D1 DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080003E1 TIM16_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080003F1 HAL_TIM_IC_CaptureCallback + 88 4 Code Lc PowerPro_lto.o + 0x08000449 HAL_TIM_PeriodElapsedCallback + 52 4 Code Lc PowerPro_lto.o + 0x0800047D SystemInit 16 4 Code Gb PowerPro_lto.o + 0x0800048D SystemCoreClockUpdate 300 4 Code Gb PowerPro_lto.o + 0x080005B9 MX_TIM16_Init 112 4 Code Lc PowerPro_lto.o + 0x08000629 MX_TIM17_Init 176 4 Code Lc PowerPro_lto.o + 0x080006D9 HAL_TIM_MspPostInit 104 4 Code Lc PowerPro_lto.o + 0x08000741 HAL_TIM_Base_MspInit 168 4 Code Lc PowerPro_lto.o + 0x080007E9 HAL_InitTick 120 4 Code Lc PowerPro_lto.o + 0x08000861 HAL_IncTick 24 4 Code Lc PowerPro_lto.o + 0x08000879 HAL_GetTick 12 4 Code Lc PowerPro_lto.o + 0x08000885 HAL_Delay 60 4 Code Lc PowerPro_lto.o + 0x080008C1 HAL_ADC_Init 772 4 Code Lc PowerPro_lto.o + 0x08000BC5 LL_ADC_EnableInternalRegulator + 32 4 Code Lc PowerPro_lto.o + 0x08000BE5 LL_ADC_Disable 28 4 Code Lc PowerPro_lto.o + 0x08000C01 ADC_Enable 224 4 Code Lc PowerPro_lto.o + 0x08000CE1 LL_ADC_REG_StartConversion + 28 4 Code Lc PowerPro_lto.o + 0x08000CFD LL_ADC_Enable 28 4 Code Lc PowerPro_lto.o + 0x08000D19 HAL_ADC_Start_DMA 252 4 Code Lc PowerPro_lto.o + 0x08000E15 HAL_ADC_ConfigChannel 1 000 4 Code Lc PowerPro_lto.o + 0x080011FD LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc PowerPro_lto.o + 0x08001219 LL_ADC_SetChannelSamplingTime + 40 4 Code Lc PowerPro_lto.o + 0x08001241 LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc PowerPro_lto.o + 0x08001261 HAL_ADCEx_Calibration_Start + 456 4 Code Lc PowerPro_lto.o + 0x08001429 LL_ADC_Enable.10 28 4 Code Lc PowerPro_lto.o + 0x08001445 LL_ADC_Disable.11 28 4 Code Lc PowerPro_lto.o + 0x08001461 __NVIC_SetPriority 128 4 Code Lc PowerPro_lto.o + 0x080014E1 __NVIC_EnableIRQ 40 4 Code Lc PowerPro_lto.o + 0x08001509 SysTick_Config 76 4 Code Lc PowerPro_lto.o + 0x08001555 HAL_DMA_Init 240 4 Code Lc PowerPro_lto.o + 0x08001645 DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc PowerPro_lto.o + 0x08001689 DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc PowerPro_lto.o + 0x080016C1 DMA_SetConfig 112 4 Code Lc PowerPro_lto.o + 0x08001731 HAL_DMA_IRQHandler 320 4 Code Lc PowerPro_lto.o + 0x08001871 HAL_GPIO_Init 704 4 Code Lc PowerPro_lto.o + 0x08001B31 HAL_RCC_OscConfig 924 4 Code Lc PowerPro_lto.o + 0x08001ECD HAL_RCC_ClockConfig 512 4 Code Lc PowerPro_lto.o + 0x080020CD HAL_RCC_GetSysClockFreq 132 4 Code Lc PowerPro_lto.o + 0x08002151 HAL_RCC_GetHCLKFreq 52 4 Code Lc PowerPro_lto.o + 0x08002185 HAL_RCC_GetPCLK1Freq 40 4 Code Lc PowerPro_lto.o + 0x080021AD HAL_RCCEx_PeriphCLKConfig 396 4 Code Lc PowerPro_lto.o + 0x08002339 TIM_Base_SetConfig 216 4 Code Lc PowerPro_lto.o + 0x08002411 HAL_TIM_Base_Start_IT 144 4 Code Lc PowerPro_lto.o + 0x080024A1 HAL_TIM_PWM_Start 424 4 Code Lc PowerPro_lto.o + 0x08002649 HAL_TIM_IC_Start_IT 652 4 Code Lc PowerPro_lto.o + 0x080028D5 HAL_TIM_IRQHandler 520 4 Code Lc PowerPro_lto.o + 0x08002ADD TIM_OC1_SetConfig 236 4 Code Lc PowerPro_lto.o + 0x08002BC9 TIM_OC2_SetConfig 260 4 Code Lc PowerPro_lto.o + 0x08002CCD TIM_OC3_SetConfig 260 4 Code Lc PowerPro_lto.o + 0x08002DD1 TIM_OC4_SetConfig 180 4 Code Lc PowerPro_lto.o + 0x08002E85 TIM_OC5_SetConfig 168 4 Code Lc PowerPro_lto.o + 0x08002F2D TIM_OC6_SetConfig 168 4 Code Lc PowerPro_lto.o + 0x08002FD5 TIM_TI1_SetConfig 152 4 Code Lc PowerPro_lto.o + 0x0800306D HAL_TIM_PWM_ConfigChannel 488 4 Code Lc PowerPro_lto.o + 0x08003255 HAL_TIMEx_ConfigBreakDeadTime + 276 4 Code Lc PowerPro_lto.o + 0x08003369 MX_IWDG_Init 44 4 Code Lc PowerPro_lto.o + 0x08003395 HAL_IWDG_Init 164 4 Code Lc PowerPro_lto.o + 0x08003439 HAL_IWDG_Refresh 24 4 Code Lc PowerPro_lto.o + 0x08003451 BUTTON_Exec 204 4 Code Lc PowerPro_lto.o + 0x0800351D BUTTON_GetMode 12 4 Code Lc PowerPro_lto.o + 0x08003529 BUTTON_SetModeOff 12 4 Code Lc PowerPro_lto.o + 0x08003535 BUZZER_Exec 116 4 Code Lc PowerPro_lto.o + 0x080035A9 BUZZER_Beep 36 4 Code Lc PowerPro_lto.o + 0x080035CD BUZZER_Alarm_Start 64 4 Code Lc PowerPro_lto.o + 0x0800360D BUZZER_Alarm_Stop 52 4 Code Lc PowerPro_lto.o + 0x08003641 CHIP_TEMPERATURE_Calibration + 64 4 Code Lc PowerPro_lto.o + 0x08003681 CHIP_TEMPERATURE_Exec 84 4 Code Lc PowerPro_lto.o + 0x080036D5 CHIP_TEMPERATURE_GetTemp 12 4 Code Lc PowerPro_lto.o + 0x080036E1 FAN_SetSpeed 72 4 Code Lc PowerPro_lto.o + 0x08003729 LEDS_Exec 280 4 Code Lc PowerPro_lto.o + 0x08003841 LEDS_GN_On 44 4 Code Lc PowerPro_lto.o + 0x0800386D LEDS_GN_Blink_Start 64 4 Code Lc PowerPro_lto.o + 0x080038AD LEDS_GN_Off 52 4 Code Lc PowerPro_lto.o + 0x080038E1 LEDS_RT_BlinkCode_Start 100 4 Code Lc PowerPro_lto.o + 0x08003945 LEDS_RT_Off 52 4 Code Lc PowerPro_lto.o + 0x08003979 main 568 4 Code Gb PowerPro_lto.o + 0x08003BB1 SystemClock_Config 112 4 Code Lc PowerPro_lto.o + 0x08003C21 MODE_LVP_Exec 72 4 Code Lc PowerPro_lto.o + 0x08003C69 LVP_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x08003D31 LVP_SM_On 484 4 Code Lc PowerPro_lto.o + 0x08003F15 LVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x08003F45 LVP_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x08003FF5 MODE_LVP_OVP_Exec 72 4 Code Lc PowerPro_lto.o + 0x0800403D LVP_OVP_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x08004105 LVP_OVP_SM_On 500 4 Code Lc PowerPro_lto.o + 0x080042F9 LVP_OVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x08004329 LVP_OVP_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x080043D9 MAINSWITCH_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x080044A1 MAINSWITCH_SM_On 204 4 Code Lc PowerPro_lto.o + 0x0800456D MAINSWITCH_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x0800459D MAINSWITCH_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x0800464D MODE_MAINSWITCH_Exec 72 4 Code Lc PowerPro_lto.o + 0x08004695 MODE_OVP_Exec 72 4 Code Lc PowerPro_lto.o + 0x080046DD OVP_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x080047A5 OVP_SM_On 468 4 Code Lc PowerPro_lto.o + 0x08004979 OVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x080049A9 OVP_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x08004A59 MODE_SECONDARYPROTECTION_Exec + 72 4 Code Lc PowerPro_lto.o + 0x08004AA1 SECONDARYPROTECTION_SM_Off + 240 4 Code Lc PowerPro_lto.o + 0x08004B91 SECONDARYPROTECTION_SM_On 468 4 Code Lc PowerPro_lto.o + 0x08004D65 SECONDARYPROTECTION_SM_ManualOn + 176 4 Code Lc PowerPro_lto.o + 0x08004E15 SECONDARYPROTECTION_SM_Error + 176 4 Code Lc PowerPro_lto.o + 0x08004EC5 MODE_SECONDARYPROTECTION_PLUS_Exec + 56 4 Code Lc PowerPro_lto.o + 0x08004EFD SECONDARYPROTECTION_SM_Off.158 + 180 4 Code Lc PowerPro_lto.o + 0x08004FB1 SECONDARYPROTECTION_SM_On.159 + 452 4 Code Lc PowerPro_lto.o + 0x08005175 SECONDARYPROTECTION_SM_Error.160 + 108 4 Code Lc PowerPro_lto.o + 0x080051E1 MODESWITCH_ReadMode 120 4 Code Lc PowerPro_lto.o + 0x08005259 MODESWITCH_GetMode 12 4 Code Lc PowerPro_lto.o + 0x08005265 RELAIS_Exec 80 4 Code Lc PowerPro_lto.o + 0x080052B5 RELAIS_SetPuls 56 4 Code Lc PowerPro_lto.o + 0x080052ED RELAIS_ResetPuls 56 4 Code Lc PowerPro_lto.o + 0x08005325 RELAIS_GetState 12 4 Code Lc PowerPro_lto.o + 0x08005331 VOLTAGE_MEAS_Exec 204 4 Code Lc PowerPro_lto.o + 0x080053FD VOLTAGE_MEAS_GetLimitAlarm + 36 4 Code Lc PowerPro_lto.o + 0x08005421 VOLTAGE_MEAS_ResetCounter 12 4 Code Lc PowerPro_lto.o + 0x0800542D VOLTAGE_MEAS_GetUin 12 4 Code Lc PowerPro_lto.o + 0x08005439 VOLTAGE_MEAS_GetUout 12 4 Code Lc PowerPro_lto.o + 0x080054A5 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054AF __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054AF __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054B3 exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054B9 __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080054D5 vfprintf_l 108 4 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + 0x08005541 printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + 0x08005569 __SEGGER_RTL_vfprintf_int_nwp + 836 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + 0x08005569 __SEGGER_RTL_vfprintf 836 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + 0x080058AD __SEGGER_RTL_X_file_stat 48 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x080058DD _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x08005931 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x08005999 SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x080059D1 __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x080059E5 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x08005A01 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x08005AA1 HAL_TIM_ReadCapturedValue 126 4 Code Lc PowerPro_lto.o + 0x08005B1F NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005B21 HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005B23 SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005B25 PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005B27 LL_ADC_REG_IsConversionOngoing + 18 2 Code Lc PowerPro_lto.o + 0x08005B39 LL_ADC_SetSamplingTimeCommonChannels + 38 2 Code Lc PowerPro_lto.o + 0x08005B5F LL_ADC_IsDisableOngoing 18 2 Code Lc PowerPro_lto.o + 0x08005B71 LL_ADC_GetCommonPathInternalCh + 18 2 Code Lc PowerPro_lto.o + 0x08005B83 LL_ADC_REG_IsTriggerSourceSWStart + 22 2 Code Lc PowerPro_lto.o + 0x08005B99 ADC_DMAHalfConvCplt 22 2 Code Lc PowerPro_lto.o + 0x08005BAF ADC_DMAError 42 2 Code Lc PowerPro_lto.o + 0x08005BD9 LL_ADC_REG_SetSequencerRanks + 46 2 Code Lc PowerPro_lto.o + 0x08005C07 LL_ADC_StartCalibration 26 2 Code Lc PowerPro_lto.o + 0x08005C21 LL_ADC_IsCalibrationOnGoing + 14 2 Code Lc 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0x080060A3 EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060A5 EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060A7 EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060A9 DMA1_Channel2_3_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x080060AB DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060AD ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060AF TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x080060B1 TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060B3 TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060B5 TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060B7 TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060B9 I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060BB SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060BD USART1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060BF USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080060C1 fwrite 50 2 Code Wk fileops.o (libc_v6m_t_le_eabi_small.a) + 0x080060F3 __aeabi_fmul 182 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080061A9 __aeabi_d2uiz 46 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080061D7 __aeabi_ui2f 30 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080061F5 __aeabi_lmul 46 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08006223 __aeabi_idiv0 6 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08006229 __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + 0x080062B3 __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + 0x080062CD __SEGGER_RTL_init_prin_l 18 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + 0x080062DF vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + 0x080062F9 __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x08006303 _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x08006319 _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x08006353 _WriteBlocking 90 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x080063AD memcpy 14 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x080063AD __aeabi_memcpy8 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x080063AD __aeabi_memcpy4 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x080063AD __aeabi_memcpy 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x080063BB __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x080063E9 __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x080063F7 __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x08006405 SysTick_Handler 8 2 Code Gb PowerPro_lto.o + 0x0800640D HAL_Init 40 2 Code Lc PowerPro_lto.o + 0x08006435 LL_ADC_IsInternalRegulatorEnabled + 20 2 Code Lc PowerPro_lto.o + 0x08006449 LL_ADC_IsEnabled 16 2 Code Lc PowerPro_lto.o + 0x08006459 LL_ADC_GetSamplingTimeCommonChannels + 28 2 Code Lc PowerPro_lto.o + 0x08006475 ADC_Disable 164 2 Code Lc PowerPro_lto.o + 0x08006519 ADC_DMAConvCplt 168 2 Code Lc PowerPro_lto.o + 0x080065C1 HAL_ADC_ErrorCallback 8 2 Code Lc PowerPro_lto.o + 0x080065C9 HAL_ADC_ConvHalfCpltCallback + 8 2 Code Lc PowerPro_lto.o + 0x080065D1 HAL_ADC_ConvCpltCallback 8 2 Code Lc PowerPro_lto.o + 0x080065D9 LL_ADC_SetCommonPathInternalCh + 28 2 Code Lc PowerPro_lto.o + 0x080065F5 LL_ADC_IsEnabled.9 16 2 Code Lc PowerPro_lto.o + 0x08006605 LL_ADC_SetCalibrationFactor + 28 2 Code Lc PowerPro_lto.o + 0x08006621 HAL_NVIC_SetPriority 28 2 Code Lc PowerPro_lto.o + 0x0800663D HAL_SYSTICK_Config 16 2 Code Lc PowerPro_lto.o + 0x0800664D HAL_DMA_Start_IT 236 2 Code Lc PowerPro_lto.o + 0x08006739 HAL_GPIO_WritePin 40 2 Code Lc PowerPro_lto.o + 0x08006761 HAL_TIM_PWM_PulseFinishedCallback + 8 2 Code Lc PowerPro_lto.o + 0x08006769 HAL_TIM_PWM_MspInit 8 2 Code Lc PowerPro_lto.o + 0x08006771 HAL_TIM_IC_MspInit 8 2 Code Lc PowerPro_lto.o + 0x08006779 HAL_TIM_OC_DelayElapsedCallback + 8 2 Code Lc PowerPro_lto.o + 0x08006781 HAL_TIM_TriggerCallback 8 2 Code Lc PowerPro_lto.o + 0x08006789 TIM_TI4_SetConfig 116 2 Code Lc PowerPro_lto.o + 0x080067FD HAL_TIMEx_CommutCallback 8 2 Code Lc PowerPro_lto.o + 0x08006805 HAL_TIMEx_BreakCallback 8 2 Code Lc PowerPro_lto.o + 0x0800680D HAL_TIMEx_Break2Callback 8 2 Code Lc PowerPro_lto.o + 0x08006815 Error_Handler 4 2 Code Lc PowerPro_lto.o + 0x08006819 reset_handler 2 Code Gb STM32C0xx_Startup.o + 0x08006819 Reset_Handler 2 Code Gb STM32C0xx_Startup.o + 0x08006821 __aeabi_ddiv 196 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080068E5 __aeabi_d2iz 52 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08006919 __aeabi_f2uiz 36 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x0800693D __aeabi_ui2d 28 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08006959 __aeabi_idiv 64 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08006999 __aeabi_uidiv 56 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080069D1 __aeabi_uldivmod 136 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08006A59 __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_small.a) + 0x08006A69 __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x08006A6D __aeabi_memclr8 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A6D __aeabi_memclr4 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A6D __aeabi_memclr 20 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A6F __aeabi_memset8 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A6F __aeabi_memset4 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A6F __aeabi_memset 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A75 memset 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + 0x08006A81 __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x08006A91 __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x08006A9D __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x08007449 __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + 0x080074BD __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + 0x080074CF __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + +Function symbols by descending size: + + Symbol name Size Align Type Bd Object File + ------------------------- ---------- ----- ---- -- ----------- + HAL_ADC_ConfigChannel 1 000 4 Code Lc PowerPro_lto.o + HAL_RCC_OscConfig 924 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_vfprintf 836 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_vfprintf_int_nwp + 836 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a) + HAL_ADC_Init 772 4 Code Lc PowerPro_lto.o + HAL_GPIO_Init 704 4 Code Lc PowerPro_lto.o + HAL_TIM_IC_Start_IT 652 4 Code Lc PowerPro_lto.o + main 568 4 Code Gb PowerPro_lto.o + HAL_TIM_IRQHandler 520 4 Code Lc PowerPro_lto.o + HAL_RCC_ClockConfig 512 4 Code Lc PowerPro_lto.o + LVP_OVP_SM_On 500 4 Code Lc PowerPro_lto.o + HAL_TIM_PWM_ConfigChannel 488 4 Code Lc PowerPro_lto.o + LVP_SM_On 484 4 Code Lc PowerPro_lto.o + OVP_SM_On 468 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On 468 4 Code Lc PowerPro_lto.o + HAL_ADCEx_Calibration_Start + 456 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.159 + 452 4 Code Lc PowerPro_lto.o + HAL_TIM_PWM_Start 424 4 Code Lc PowerPro_lto.o + HAL_RCCEx_PeriphCLKConfig 396 4 Code Lc PowerPro_lto.o + HAL_DMA_IRQHandler 320 4 Code Lc PowerPro_lto.o + SystemCoreClockUpdate 300 4 Code Gb PowerPro_lto.o + LEDS_Exec 280 4 Code Lc PowerPro_lto.o + HAL_TIM_IC_ConfigChannel 278 2 Code Lc PowerPro_lto.o + HAL_TIMEx_ConfigBreakDeadTime + 276 4 Code Lc PowerPro_lto.o + TIM_OC2_SetConfig 260 4 Code Lc PowerPro_lto.o + TIM_OC3_SetConfig 260 4 Code Lc PowerPro_lto.o + HAL_ADC_Start_DMA 252 4 Code Lc PowerPro_lto.o + MX_GPIO_Init 252 4 Code Lc PowerPro_lto.o + HAL_DMA_Init 240 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Off + 240 4 Code Lc PowerPro_lto.o + HAL_DMA_Start_IT 236 2 Code Lc PowerPro_lto.o + TIM_OC1_SetConfig 236 4 Code Lc PowerPro_lto.o + MX_ADC1_Init 228 4 Code Lc PowerPro_lto.o + ADC_Enable 224 4 Code Lc PowerPro_lto.o + HAL_ADC_MspInit 216 4 Code Lc PowerPro_lto.o + TIM_Base_SetConfig 216 4 Code Lc PowerPro_lto.o + BUTTON_Exec 204 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_On 204 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_Exec 204 4 Code Lc PowerPro_lto.o + LVP_OVP_SM_Off 200 4 Code Lc PowerPro_lto.o + LVP_SM_Off 200 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_Off 200 4 Code Lc PowerPro_lto.o + OVP_SM_Off 200 4 Code Lc PowerPro_lto.o + __aeabi_ddiv 196 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_fmul 182 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + SECONDARYPROTECTION_SM_Off.158 + 180 4 Code Lc PowerPro_lto.o + TIM_OC4_SetConfig 180 4 Code Lc PowerPro_lto.o + LVP_OVP_SM_Error 176 4 Code Lc PowerPro_lto.o + LVP_SM_Error 176 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_Error 176 4 Code Lc PowerPro_lto.o + MX_TIM17_Init 176 4 Code Lc PowerPro_lto.o + OVP_SM_Error 176 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Error + 176 4 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_ManualOn + 176 4 Code Lc PowerPro_lto.o + ADC_DMAConvCplt 168 2 Code Lc PowerPro_lto.o + HAL_TIM_Base_MspInit 168 4 Code Lc PowerPro_lto.o + TIM_OC5_SetConfig 168 4 Code Lc PowerPro_lto.o + TIM_OC6_SetConfig 168 4 Code Lc PowerPro_lto.o + ADC_Disable 164 2 Code Lc PowerPro_lto.o + HAL_IWDG_Init 164 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 154 2 Code Lc PowerPro_lto.o + HAL_TIM_IC_Init 154 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_Init 154 2 Code Lc PowerPro_lto.o + TIM_TI1_SetConfig 152 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Start_IT 144 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __aeabi_uldivmod 136 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + HAL_RCC_GetSysClockFreq 132 4 Code Lc PowerPro_lto.o + __NVIC_SetPriority 128 4 Code Lc PowerPro_lto.o + HAL_TIM_ReadCapturedValue 126 4 Code Lc PowerPro_lto.o + HAL_InitTick 120 4 Code Lc PowerPro_lto.o + MODESWITCH_ReadMode 120 4 Code Lc PowerPro_lto.o + BUZZER_Exec 116 4 Code Lc PowerPro_lto.o + TIM_TI4_SetConfig 116 2 Code Lc PowerPro_lto.o + DMA_SetConfig 112 4 Code Lc PowerPro_lto.o + MX_TIM16_Init 112 4 Code Lc PowerPro_lto.o + SystemClock_Config 112 4 Code Lc PowerPro_lto.o + TIM_TI2_SetConfig 110 2 Code Lc PowerPro_lto.o + TIM_TI3_SetConfig 110 2 Code Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Error.160 + 108 4 Code Lc PowerPro_lto.o + vfprintf_l 108 4 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + HAL_TIM_MspPostInit 104 4 Code Lc PowerPro_lto.o + SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + LEDS_RT_BlinkCode_Start 100 4 Code Lc PowerPro_lto.o + _WriteBlocking 90 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + HAL_TIM_IC_CaptureCallback + 88 4 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_Exec 84 4 Code Lc PowerPro_lto.o + _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + RELAIS_Exec 80 4 Code Lc PowerPro_lto.o + SysTick_Config 76 4 Code Lc PowerPro_lto.o + FAN_SetSpeed 72 4 Code Lc PowerPro_lto.o + MODE_LVP_Exec 72 4 Code Lc PowerPro_lto.o + MODE_LVP_OVP_Exec 72 4 Code Lc PowerPro_lto.o + MODE_MAINSWITCH_Exec 72 4 Code Lc PowerPro_lto.o + MODE_OVP_Exec 72 4 Code Lc PowerPro_lto.o + MODE_SECONDARYPROTECTION_Exec + 72 4 Code Lc PowerPro_lto.o + DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc PowerPro_lto.o + BUZZER_Alarm_Start 64 4 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_Calibration + 64 4 Code Lc PowerPro_lto.o + LEDS_GN_Blink_Start 64 4 Code Lc PowerPro_lto.o + __aeabi_idiv 64 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + HAL_Delay 60 4 Code Lc PowerPro_lto.o + _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc PowerPro_lto.o + MODE_SECONDARYPROTECTION_PLUS_Exec + 56 4 Code Lc PowerPro_lto.o + RELAIS_ResetPuls 56 4 Code Lc PowerPro_lto.o + RELAIS_SetPuls 56 4 Code Lc PowerPro_lto.o + SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + __aeabi_uidiv 56 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + BUZZER_Alarm_Stop 52 4 Code Lc PowerPro_lto.o + HAL_MspInit 52 4 Code Lc PowerPro_lto.o + HAL_RCC_GetHCLKFreq 52 4 Code Lc PowerPro_lto.o + HAL_TIM_PeriodElapsedCallback + 52 4 Code Lc PowerPro_lto.o + LEDS_GN_Off 52 4 Code Lc PowerPro_lto.o + LEDS_RT_Off 52 4 Code Lc PowerPro_lto.o + __aeabi_d2iz 52 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + TIM_CCxChannelCmd 50 2 Code Lc PowerPro_lto.o + fwrite 50 2 Code Wk fileops.o (libc_v6m_t_le_eabi_small.a) + LVP_OVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + LVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + MAINSWITCH_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + MX_DMA_Init 48 4 Code Lc PowerPro_lto.o + OVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_X_file_stat 48 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + HAL_GPIO_ReadPin 46 2 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerRanks + 46 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __aeabi_d2uiz 46 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_lmul 46 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + LEDS_GN_On 44 4 Code Lc PowerPro_lto.o + MX_IWDG_Init 44 4 Code Lc PowerPro_lto.o + ADC_DMAError 42 2 Code Lc PowerPro_lto.o + HAL_GPIO_WritePin 40 2 Code Lc PowerPro_lto.o + HAL_Init 40 2 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 40 4 Code Lc PowerPro_lto.o + LL_ADC_SetChannelSamplingTime + 40 4 Code Lc PowerPro_lto.o + __NVIC_EnableIRQ 40 4 Code Lc PowerPro_lto.o + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + LL_ADC_SetSamplingTimeCommonChannels + 38 2 Code Lc PowerPro_lto.o + BUZZER_Beep 36 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetLimitAlarm + 36 4 Code Lc PowerPro_lto.o + __aeabi_f2uiz 36 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + LL_ADC_EnableInternalRegulator + 32 4 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc PowerPro_lto.o + __aeabi_ui2f 30 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + HAL_NVIC_SetPriority 28 2 Code Lc PowerPro_lto.o + LL_ADC_Disable 28 4 Code Lc PowerPro_lto.o + LL_ADC_Disable.11 28 4 Code Lc PowerPro_lto.o + LL_ADC_Enable 28 4 Code Lc PowerPro_lto.o + LL_ADC_Enable.10 28 4 Code Lc PowerPro_lto.o + LL_ADC_GetSamplingTimeCommonChannels + 28 2 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc PowerPro_lto.o + LL_ADC_REG_StartConversion + 28 4 Code Lc PowerPro_lto.o + LL_ADC_SetCalibrationFactor + 28 2 Code Lc PowerPro_lto.o + LL_ADC_SetCommonPathInternalCh + 28 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __aeabi_ui2d 28 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + LL_ADC_StartCalibration 26 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_small.a) + HAL_IWDG_Refresh 24 4 Code Lc PowerPro_lto.o + HAL_IncTick 24 4 Code Lc PowerPro_lto.o + ADC_DMAHalfConvCplt 22 2 Code Lc PowerPro_lto.o + HAL_NVIC_EnableIRQ 22 2 Code Lc PowerPro_lto.o + LL_ADC_REG_IsTriggerSourceSWStart + 22 2 Code Lc PowerPro_lto.o + _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_small.a) + LL_ADC_IsInternalRegulatorEnabled + 20 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + __aeabi_memclr 20 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + LL_ADC_GetCalibrationFactor + 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetClock 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetCommonClock 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetCommonPathInternalCh + 18 2 Code Lc PowerPro_lto.o + LL_ADC_IsDisableOngoing 18 2 Code Lc PowerPro_lto.o + LL_ADC_REG_IsConversionOngoing + 18 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_init_prin_l 18 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a) + DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + HAL_SYSTICK_Config 16 2 Code Lc PowerPro_lto.o + LL_ADC_IsEnabled 16 2 Code Lc PowerPro_lto.o + LL_ADC_IsEnabled.9 16 2 Code Lc PowerPro_lto.o + SystemInit 16 4 Code Gb PowerPro_lto.o + TIM16_IRQHandler 16 4 Code Gb PowerPro_lto.o + __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_small.a) + LL_ADC_IsCalibrationOnGoing + 14 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + _start 14 4 Code Gb SEGGER_THUMB_Startup.o + memcpy 14 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + BUTTON_GetMode 12 4 Code Lc PowerPro_lto.o + BUTTON_SetModeOff 12 4 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_GetTemp 12 4 Code Lc PowerPro_lto.o + HAL_GetTick 12 4 Code Lc PowerPro_lto.o + MODESWITCH_GetMode 12 4 Code Lc PowerPro_lto.o + RELAIS_GetState 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetUin 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetUout 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_ResetCounter 12 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + HAL_ADC_ConvCpltCallback 8 2 Code Lc PowerPro_lto.o + HAL_ADC_ConvHalfCpltCallback + 8 2 Code Lc PowerPro_lto.o + HAL_ADC_ErrorCallback 8 2 Code Lc PowerPro_lto.o + HAL_TIMEx_Break2Callback 8 2 Code Lc PowerPro_lto.o + HAL_TIMEx_BreakCallback 8 2 Code Lc PowerPro_lto.o + HAL_TIMEx_CommutCallback 8 2 Code Lc PowerPro_lto.o + HAL_TIM_IC_MspInit 8 2 Code Lc PowerPro_lto.o + HAL_TIM_OC_DelayElapsedCallback + 8 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_MspInit 8 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_PulseFinishedCallback + 8 2 Code Lc PowerPro_lto.o + HAL_TIM_TriggerCallback 8 2 Code Lc PowerPro_lto.o + SysTick_Handler 8 2 Code Gb PowerPro_lto.o + __aeabi_idiv0 6 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + Error_Handler 4 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + HardFault_Handler 2 2 Code Gb PowerPro_lto.o + NMI_Handler 2 2 Code Gb PowerPro_lto.o + PendSV_Handler 2 2 Code Gb PowerPro_lto.o + SVC_Handler 2 2 Code Gb PowerPro_lto.o + exit 2 4 Code Gb SEGGER_THUMB_Startup.o + ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + DMA1_Channel2_3_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + Reset_Handler 2 Code Gb STM32C0xx_Startup.o + SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + USART1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + __aeabi_memclr4 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memclr8 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memcpy 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memcpy4 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memcpy8 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memset 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memset4 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __aeabi_memset8 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + memset 2 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_small.a) + reset_handler 2 Code Gb STM32C0xx_Startup.o + +Read-write data symbols by name: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + LVP_OVP_SM_On.lvpAndOvpInputTimeCounter + 0x200002F4 4 4 Zero Lc PowerPro_lto.o + LVP_OVP_SM_On.lvpOROvpInput + 0x200002F0 4 4 Zero Lc PowerPro_lto.o + LVP_OVP_SM_On.oldtime 0x200002EC 4 4 Zero Lc PowerPro_lto.o + LVP_SM_On.lvpInput 0x200002E8 4 4 Zero Lc PowerPro_lto.o + LVP_SM_On.lvpTimeCounter 0x200002E4 4 4 Zero Lc PowerPro_lto.o + LVP_SM_On.oldtime 0x200002E0 4 4 Zero Lc PowerPro_lto.o + OVP_SM_On.oldtime 0x200002DC 4 4 Zero Lc PowerPro_lto.o + OVP_SM_On.ovpInput 0x200002D8 4 4 Zero Lc PowerPro_lto.o + OVP_SM_On.ovpTimeCounter 0x200002D4 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter + 0x200002D0 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.163 + 0x200002CC 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.oldtime + 0x200002C8 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.oldtime.162 + 0x200002C4 4 4 Zero Lc PowerPro_lto.o + SystemCoreClock 0x20000734 4 4 Init Lc PowerPro_lto.o + _SEGGER_RTT 0x20000000 168 4 Zero Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + __RAL_global_locale 0x20000710 20 4 Init Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_global_locale + 0x20000710 20 4 Init Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_locale_ptr 0x20000298 4 4 Zero Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + __SEGGER_RTL_stderr_file 0x20000294 4 4 Zero Lc prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + __SEGGER_RTL_stdin_file 0x20000290 4 4 Zero Lc prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + __SEGGER_RTL_stdout_file 0x2000028C 4 4 Zero Lc prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + _acDownBuffer 0x200006F8 16 Zero Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + _acUpBuffer 0x200002F8 1 024 Zero Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + adcData 0x20000200 20 4 Zero Lc PowerPro_lto.o + alarmMode 0x200002C0 4 4 Zero Lc PowerPro_lto.o + blinkCounter 0x200002BC 4 4 Zero Lc PowerPro_lto.o + blinkModeGN 0x200002B8 4 4 Zero Lc PowerPro_lto.o + blinkModeRT 0x200002B4 4 4 Zero Lc PowerPro_lto.o + buttonState 0x2000070F 1 Zero Lc PowerPro_lto.o + calTemperatureSensor30Value + 0x200002B0 4 4 Zero Lc PowerPro_lto.o + captureValue 0x200002AC 4 4 Zero Lc PowerPro_lto.o + dropLimitCounter 0x200002A8 4 4 Zero Lc PowerPro_lto.o + frequency 0x200002A4 4 4 Zero Lc PowerPro_lto.o + hadc1 0x200000A8 100 4 Zero Lc PowerPro_lto.o + hdma_adc1 0x2000010C 92 4 Zero Lc PowerPro_lto.o + hiwdg 0x20000214 16 4 Zero Lc PowerPro_lto.o + htim16 0x200001B4 76 4 Zero Lc PowerPro_lto.o + htim17 0x20000168 76 4 Zero Lc PowerPro_lto.o + ic_overflows 0x200002A0 4 4 Zero Lc PowerPro_lto.o + lastSpeed 0x2000029C 4 4 Zero Lc PowerPro_lto.o + longPressCounterButtonOff 0x20000288 4 4 Zero Lc PowerPro_lto.o + longPressCounterButtonOn 0x20000284 4 4 Zero Lc PowerPro_lto.o + mode 0x2000070E 1 Zero Lc PowerPro_lto.o + msCounter 0x20000280 4 4 Zero Lc PowerPro_lto.o + numberOfBlinks 0x2000027C 4 4 Zero Lc PowerPro_lto.o + offTime 0x20000278 4 4 Zero Lc PowerPro_lto.o + offTimeCounter 0x20000274 4 4 Zero Lc PowerPro_lto.o + offTimeCounterGN 0x20000270 4 4 Zero Lc PowerPro_lto.o + offTimeCounterRT 0x2000026C 4 4 Zero Lc PowerPro_lto.o + offTimeGN 0x20000268 4 4 Zero Lc PowerPro_lto.o + offTimeRT 0x20000264 4 4 Zero Lc PowerPro_lto.o + oldTimeMSTick 0x20000260 4 4 Zero Lc PowerPro_lto.o + onTime 0x2000025C 4 4 Zero Lc PowerPro_lto.o + onTimeCounter 0x20000258 4 4 Zero Lc PowerPro_lto.o + onTimeCounterGN 0x20000254 4 4 Zero Lc PowerPro_lto.o + onTimeCounterRESET 0x20000250 4 4 Zero Lc PowerPro_lto.o + onTimeCounterRT 0x2000024C 4 4 Zero Lc PowerPro_lto.o + onTimeCounterSET 0x20000248 4 4 Zero Lc PowerPro_lto.o + onTimeGN 0x20000244 4 4 Zero Lc PowerPro_lto.o + onTimeRT 0x20000240 4 4 Zero Lc PowerPro_lto.o + pauseTime 0x2000023C 4 4 Zero Lc PowerPro_lto.o + relaisState 0x20000238 4 4 Zero Lc PowerPro_lto.o + smState 0x2000070D 1 Zero Lc PowerPro_lto.o + smState.108 0x2000070C 1 Zero Lc PowerPro_lto.o + smState.122 0x2000070B 1 Zero Lc PowerPro_lto.o + smState.131 0x2000070A 1 Zero Lc PowerPro_lto.o + smState.146 0x20000709 1 Zero Lc PowerPro_lto.o + smState.157 0x20000708 1 Zero Lc PowerPro_lto.o + stderr 0x20000730 4 4 Init Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + stdin 0x2000072C 4 4 Init Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + stdout 0x20000728 4 4 Init Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + temp 0x20000234 4 4 Zero Lc PowerPro_lto.o + uwTick 0x20000230 4 4 Zero Lc PowerPro_lto.o + uwTickFreq 0x20000738 1 Init Lc PowerPro_lto.o + uwTickPrio 0x20000724 4 4 Init Lc PowerPro_lto.o + voltageDrop 0x2000022C 4 4 Zero Lc PowerPro_lto.o + voltageUin 0x20000228 4 4 Zero Lc PowerPro_lto.o + voltageUout 0x20000224 4 4 Zero Lc PowerPro_lto.o + +Read-write data symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x20000000 _SEGGER_RTT 168 4 Zero Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x200000A8 hadc1 100 4 Zero Lc PowerPro_lto.o + 0x2000010C hdma_adc1 92 4 Zero Lc PowerPro_lto.o + 0x20000168 htim17 76 4 Zero Lc PowerPro_lto.o + 0x200001B4 htim16 76 4 Zero Lc PowerPro_lto.o + 0x20000200 adcData 20 4 Zero Lc PowerPro_lto.o + 0x20000214 hiwdg 16 4 Zero Lc PowerPro_lto.o + 0x20000224 voltageUout 4 4 Zero Lc PowerPro_lto.o + 0x20000228 voltageUin 4 4 Zero Lc PowerPro_lto.o + 0x2000022C voltageDrop 4 4 Zero Lc PowerPro_lto.o + 0x20000230 uwTick 4 4 Zero Lc PowerPro_lto.o + 0x20000234 temp 4 4 Zero Lc PowerPro_lto.o + 0x20000238 relaisState 4 4 Zero Lc PowerPro_lto.o + 0x2000023C pauseTime 4 4 Zero Lc PowerPro_lto.o + 0x20000240 onTimeRT 4 4 Zero Lc PowerPro_lto.o + 0x20000244 onTimeGN 4 4 Zero Lc PowerPro_lto.o + 0x20000248 onTimeCounterSET 4 4 Zero Lc PowerPro_lto.o + 0x2000024C onTimeCounterRT 4 4 Zero Lc PowerPro_lto.o + 0x20000250 onTimeCounterRESET 4 4 Zero Lc PowerPro_lto.o + 0x20000254 onTimeCounterGN 4 4 Zero Lc PowerPro_lto.o + 0x20000258 onTimeCounter 4 4 Zero Lc PowerPro_lto.o + 0x2000025C onTime 4 4 Zero Lc PowerPro_lto.o + 0x20000260 oldTimeMSTick 4 4 Zero Lc PowerPro_lto.o + 0x20000264 offTimeRT 4 4 Zero Lc PowerPro_lto.o + 0x20000268 offTimeGN 4 4 Zero Lc PowerPro_lto.o + 0x2000026C offTimeCounterRT 4 4 Zero Lc PowerPro_lto.o + 0x20000270 offTimeCounterGN 4 4 Zero Lc PowerPro_lto.o + 0x20000274 offTimeCounter 4 4 Zero Lc PowerPro_lto.o + 0x20000278 offTime 4 4 Zero Lc PowerPro_lto.o + 0x2000027C numberOfBlinks 4 4 Zero Lc PowerPro_lto.o + 0x20000280 msCounter 4 4 Zero Lc PowerPro_lto.o + 0x20000284 longPressCounterButtonOn 4 4 Zero Lc PowerPro_lto.o + 0x20000288 longPressCounterButtonOff 4 4 Zero Lc PowerPro_lto.o + 0x2000028C __SEGGER_RTL_stdout_file 4 4 Zero Lc prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x20000290 __SEGGER_RTL_stdin_file 4 4 Zero Lc prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x20000294 __SEGGER_RTL_stderr_file 4 4 Zero Lc prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a) + 0x20000298 __SEGGER_RTL_locale_ptr 4 4 Zero Gb mbops.o (mbops_timeops_v6m_t_le_eabi_small.a) + 0x2000029C lastSpeed 4 4 Zero Lc PowerPro_lto.o + 0x200002A0 ic_overflows 4 4 Zero Lc PowerPro_lto.o + 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Files/SEGGER/SEGGER Embedded Studio 8.24/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/prinops_rtt_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/heapops_basic_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/strops_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/mbops_timeops_v6m_t_le_eabi_small.a" Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,65 @@ +Output/Debug/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Debug/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Debug/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,48 @@ +Output/Debug/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.htm =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.htm (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.htm (revision 41) @@ -0,0 +1,6146 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ +
+SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49
+Copyright (c) 2017-2025 SEGGER Microcontroller GmbH    www.segger.com
+
+ +
+--add-region:FLASH1=0x00007800@0x08000000
+--add-region:RAM1=0x00003000@0x20000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Debug_12V/Exe/PowerPro.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=6-M
+--silent
+-TD:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf
+--defsym=__STACKSIZE__=2048
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=1024
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_int_nwp
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.elf
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_lto.o
+Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o
+Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.o
+Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf'

+
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32C0xx_Flash.icf
+Purpose : STM32C0xx linker script for application placement in Flash,
+          for use with the SEGGER Linker.
+Maps    : STM32C011D6Yx, STM32C011F4Px, STM32C011F4Ux, STM32C011F6Px, 
+          STM32C011F6Ux, STM32C011J4Mx, STM32C011J6Mx, STM32C031C4Tx, 
+          STM32C031C4Ux, STM32C031C6Tx, STM32C031C6Ux, STM32C031F4Px, 
+          STM32C031F6Px, STM32C031G4Ux, STM32C031G6Ux, STM32C031K4Tx, 
+          STM32C031K4Ux, STM32C031K6Tx, STM32C031K6Ux
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM   = RAM1;
+
+//
+// Block definitions
+//
+define block vectors                        { section .vectors };                                   // Vector table section
+define block vectors_ram                    { section .vectors_ram };                               // Vector table section
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { block vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1                             { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { block vectors };                                      // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1                               { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM                       { block vectors_ram };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x08000000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x08000000180256stm32c031xx_Vectors.o
+

"<#5> at line 111, col 45": place in [0x08000000 to 0x080077ff] with maximum packing

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
MX_ADC1_InitCode0x080000B41 4804PowerPro_lto.o
MX_DMA_InitCode0x0800067C684PowerPro_lto.o
MX_GPIO_InitCode0x080006C02364PowerPro_lto.o
SysTick_HandlerCode0x080007AC164PowerPro_lto.o
DMA1_Channel1_IRQHandlerCode0x080007BC164PowerPro_lto.o
DMA1_Channel2_3_IRQHandlerCode0x080007CC244PowerPro_lto.o
TIM16_IRQHandlerCode0x080007E44364PowerPro_lto.o
USART1_IRQHandlerCode0x080009981 1204PowerPro_lto.o
HAL_TIM_IC_CaptureCallbackCode0x08000DF81444PowerPro_lto.o
SystemInitCode0x08000E88164PowerPro_lto.o
SystemCoreClockUpdateCode0x08000E98844PowerPro_lto.o
MX_TIM16_InitCode0x08000EEC4524PowerPro_lto.o
MX_TIM17_InitCode0x080010B07804PowerPro_lto.o
MX_USART1_UART_InitCode0x080013BC3044PowerPro_lto.o
MX_IWDG_InitCode0x080014EC884PowerPro_lto.o
HAL_InitCode0x08001544604PowerPro_lto.o
HAL_InitTickCode0x080015801004PowerPro_lto.o
HAL_GetTickCode0x080015E4124PowerPro_lto.o
HAL_DelayCode0x080015F0204PowerPro_lto.o
HAL_ADC_Start_DMACode0x080016043524PowerPro_lto.o
HAL_ADC_ConfigChannelCode0x080017641 0884PowerPro_lto.o
HAL_ADCEx_Calibration_StartCode0x08001BA44364PowerPro_lto.o
HAL_NVIC_SetPriorityCode0x08001D58964PowerPro_lto.o
HAL_NVIC_SystemResetCode0x08001DB8284PowerPro_lto.o
HAL_DMA_InitCode0x08001DD44444PowerPro_lto.o
HAL_DMA_Start_ITCode0x08001F902324PowerPro_lto.o
HAL_DMA_IRQHandlerCode0x080020782324PowerPro_lto.o
FLASH_WaitForLastOperationCode0x08002160804PowerPro_lto.o
HAL_FLASH_UnlockCode0x080021B0364PowerPro_lto.o
HAL_FLASH_OB_UnlockCode0x080021D4324PowerPro_lto.o
HAL_FLASH_OB_LaunchCode0x080021F4204PowerPro_lto.o
HAL_GPIO_InitCode0x080022086324PowerPro_lto.o
HAL_GPIO_WritePinCode0x08002480484PowerPro_lto.o
HAL_IWDG_RefreshCode0x080024B0164PowerPro_lto.o
HAL_RCC_OscConfigCode0x080024C07084PowerPro_lto.o
HAL_RCC_ClockConfigCode0x080027844124PowerPro_lto.o
HAL_RCC_GetSysClockFreqCode0x08002920844PowerPro_lto.o
HAL_RCC_GetPCLK1FreqCode0x08002974644PowerPro_lto.o
HAL_RCCEx_PeriphCLKConfigCode0x080029B44764PowerPro_lto.o
HAL_TIM_Base_InitCode0x08002B903964PowerPro_lto.o
TIM_Base_SetConfigCode0x08002D1C1564PowerPro_lto.o
HAL_TIM_Base_Start_ITCode0x08002DB81484PowerPro_lto.o
TIM_CCxChannelCmdCode0x08002E4C1044PowerPro_lto.o
HAL_TIM_IC_Start_ITCode0x08002EB41764PowerPro_lto.o
HAL_UART_InitCode0x08002F641 5844PowerPro_lto.o
UART_WaitOnFlagUntilTimeoutCode0x080035941084PowerPro_lto.o
UART_EndRxTransferCode0x08003600964PowerPro_lto.o
HAL_UART_Transmit_DMACode0x080036601644PowerPro_lto.o
HAL_UART_Receive_DMACode0x080037042604PowerPro_lto.o
HAL_UART_ReceiverTimeout_ConfigCode0x08003808444PowerPro_lto.o
UARTEx_SetNbDataToProcessCode0x08003834804PowerPro_lto.o
BUTTON_ExecCode0x080038841604PowerPro_lto.o
BUZZER_ExecCode0x080039241084PowerPro_lto.o
CHIP_TEMPERATURE_CalibrationCode0x08003990484PowerPro_lto.o
CHIP_TEMPERATURE_ExecCode0x080039C0604PowerPro_lto.o
CHIP_TEMPERATURE_GetTempCode0x080039FC124PowerPro_lto.o
EEPROM_WriteCode0x08003A084044PowerPro_lto.o
EEPROM_WriteDefaultsCode0x08003B9C484PowerPro_lto.o
EEPROM_ReadFirstStartCode0x08003BCC124PowerPro_lto.o
EEPROM_ReadDeviceParameterCode0x08003BD8364PowerPro_lto.o
EEPROM_StoreConfigCode0x08003BFC764PowerPro_lto.o
FAN_SetSpeedCode0x08003C48364PowerPro_lto.o
LEDS_ExecCode0x08003C6C2644PowerPro_lto.o
mainCode0x08003D749884PowerPro_lto.o
JumpToBootloaderCode0x08004150204PowerPro_lto.o
SystemClock_ConfigCode0x080041641084PowerPro_lto.o
assert_failedCode0x080041D0284PowerPro_lto.o
mbInitCode0x080041EC1364PowerPro_lto.o
mbUartInitCode0x080042742764PowerPro_lto.o
HAL_UART_ErrorCallbackCode0x080043882004PowerPro_lto.o
HAL_UART_TxCpltCallbackCode0x08004450204PowerPro_lto.o
mbCrc16Code0x080044641164PowerPro_lto.o
mbGetFrameCompleteCode0x080044D8244PowerPro_lto.o
mbSlaveCheckModbusRtuQueryCode0x080044F01284PowerPro_lto.o
mbSlaveProcessRtuQueryCode0x080045701004PowerPro_lto.o
mbSlaveReadHoldingRegistersCode0x080045D42364PowerPro_lto.o
mbSlaveWriteSingleRegisterCode0x080046C01924PowerPro_lto.o
mbSlaveWriteMultipleRegistersCode0x080047802764PowerPro_lto.o
MODE_LVP_ExecCode0x080048941 4924PowerPro_lto.o
MODE_LVP_OVP_ExecCode0x08004E681 4924PowerPro_lto.o
MODE_MAINSWITCH_ExecCode0x0800543C1 0484PowerPro_lto.o
MODE_OVP_ExecCode0x080058541 4644PowerPro_lto.o
MODE_SECONDARYPROTECTION_ExecCode0x08005E0C1 6884PowerPro_lto.o
MODE_SECONDARYPROTECTION_PLUS_ExecCode0x080064A41 1524PowerPro_lto.o
MODESWITCH_ReadModeCode0x08006924684PowerPro_lto.o
MODESWITCH_GetModeCode0x08006968124PowerPro_lto.o
RELAIS_GetTempCode0x08006974124PowerPro_lto.o
RELAIS_ExecCode0x080069801004PowerPro_lto.o
RELAIS_GetStateCode0x080069E4124PowerPro_lto.o
SYS_DATA_InitCode0x080069F0244PowerPro_lto.o
VOLTAGE_MEAS_ExecCode0x08006A081364PowerPro_lto.o
VOLTAGE_MEAS_GetUinCode0x08006A90124PowerPro_lto.o
VOLTAGE_MEAS_GetUoutCode0x08006A9C124PowerPro_lto.o
AHBPrescTableCnst0x08006AA8644PowerPro_lto.o
APBPrescTableCnst0x08006AE8324PowerPro_lto.o
[.rodata..Lswitch.table.UART_SetConfig]Cnst0x08006B08164PowerPro_lto.o
_startCode0x08006B18204SEGGER_THUMB_Startup.o
putcharCode0x08006B2C164fileops.o (libc_v6m_t_le_eabi_small.a)
putsCode0x08006B3C444fileops.o (libc_v6m_t_le_eabi_small.a)
__aeabi_i2dCode0x08006B68284floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
vfprintf_lCode0x08006B841084prinops.o (libc_v6m_t_le_eabi_small.a)
printfCode0x08006BF0404prinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf_int_nwpCode0x08006C188404__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_statCode0x08006F60444prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
_DoInitCode0x08006F8C844SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteNoLockCode0x08006FE01044SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteCode0x08007048564SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_current_localeCode0x08007080204mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_isctypeCode0x08007094284mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_iswctypeCode0x080070B0284mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_localeCnst0x080070CC124mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_codeset_asciiCnst0x080070D8324mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_dataCnst0x080070F8884mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
NMI_HandlerCode0x0800715022PowerPro_lto.o
HardFault_HandlerCode0x0800715222PowerPro_lto.o
SVC_HandlerCode0x0800715422PowerPro_lto.o
PendSV_HandlerCode0x0800715622PowerPro_lto.o
ADC_DMAConvCpltCode0x080071581022PowerPro_lto.o
ADC_DMAHalfConvCpltCode0x080071BE22PowerPro_lto.o
HAL_GPIO_ReadPinCode0x080071C0102PowerPro_lto.o
UART_DMATransmitCpltCode0x080071CA742PowerPro_lto.o
UART_DMATxHalfCpltCode0x0800721422PowerPro_lto.o
UART_DMAErrorCode0x080072161302PowerPro_lto.o
HAL_UART_EnableReceiverTimeoutCode0x08007298422PowerPro_lto.o
mbSendCode0x080072C2382PowerPro_lto.o
mbClearTxBufferCode0x080072E8182PowerPro_lto.o
mbCheckCrc16Code0x080072FA702PowerPro_lto.o
mbAppendCrc16Code0x08007340662PowerPro_lto.o
mbClearRxFrameCode0x08007382222PowerPro_lto.o
mbSlaveProcessPduCode0x080073981102PowerPro_lto.o
mbSlaveResponseExceptionCode0x08007406502PowerPro_lto.o
WWDG_IRQHandlerCode0x0800743822stm32c031xx_Vectors.o
RTC_IRQHandlerCode0x0800743A22stm32c031xx_Vectors.o
FLASH_IRQHandlerCode0x0800743C22stm32c031xx_Vectors.o
RCC_IRQHandlerCode0x0800743E22stm32c031xx_Vectors.o
EXTI0_1_IRQHandlerCode0x0800744022stm32c031xx_Vectors.o
EXTI2_3_IRQHandlerCode0x0800744222stm32c031xx_Vectors.o
EXTI4_15_IRQHandlerCode0x0800744422stm32c031xx_Vectors.o
DMAMUX1_IRQHandlerCode0x0800744622stm32c031xx_Vectors.o
ADC1_IRQHandlerCode0x0800744822stm32c031xx_Vectors.o
TIM1_BRK_UP_TRG_COM_IRQHandlerCode0x0800744A22stm32c031xx_Vectors.o
TIM1_CC_IRQHandlerCode0x0800744C22stm32c031xx_Vectors.o
TIM3_IRQHandlerCode0x0800744E22stm32c031xx_Vectors.o
TIM14_IRQHandlerCode0x0800745022stm32c031xx_Vectors.o
TIM17_IRQHandlerCode0x0800745222stm32c031xx_Vectors.o
I2C1_IRQHandlerCode0x0800745422stm32c031xx_Vectors.o
SPI1_IRQHandlerCode0x0800745622stm32c031xx_Vectors.o
USART2_IRQHandlerCode0x0800745822stm32c031xx_Vectors.o
fputcCode0x0800745A342fileops.o (libc_v6m_t_le_eabi_small.a)
fwriteCode0x0800747C502fileops.o (libc_v6m_t_le_eabi_small.a)
__aeabi_fmulCode0x080074AE1822floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_dmul_auxCode0x080075643942floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_d2uizCode0x080076EE462floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_ui2fCode0x0800771C302floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_lmulCode0x0800773A462intasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_idiv0Code0x0800776862intasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_putcCode0x0800776E1382prinops.o (libc_v6m_t_le_eabi_small.a)
Error_HandlerCode0x080077F842PowerPro_lto.o
__SEGGER_RTL_X_file_bufsizeCode0x080077FC42prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
+

"<#6> at line 122, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
modbusDataZero0x200000005644PowerPro_lto.o
+

"<#9> at line 128, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
sys_dataZero0x200002342244PowerPro_lto.o
_SEGGER_RTTZero0x200003141684SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
huart1Zero0x200003BC1484PowerPro_lto.o
hadc1Zero0x200004501004PowerPro_lto.o
hdma_usart1_txZero0x200004B4924PowerPro_lto.o
hdma_usart1_rxZero0x20000510924PowerPro_lto.o
hdma_adc1Zero0x2000056C924PowerPro_lto.o
htim17Zero0x200005C8764PowerPro_lto.o
htim16Zero0x20000614764PowerPro_lto.o
adcDataZero0x20000660204PowerPro_lto.o
flash_device_parameter_defaultZero0x20000674164PowerPro_lto.o
voltageUoutZero0x2000068444PowerPro_lto.o
voltageUinZero0x2000068844PowerPro_lto.o
uwTickZero0x2000068C44PowerPro_lto.o
tempZero0x2000069044PowerPro_lto.o
relais_temperatureZero0x2000069444PowerPro_lto.o
onTimeCounterSETZero0x2000069844PowerPro_lto.o
onTimeCounterRTZero0x2000069C44PowerPro_lto.o
onTimeCounterRESETZero0x200006A044PowerPro_lto.o
onTimeCounterGNZero0x200006A444PowerPro_lto.o
onTimeCounterZero0x200006A844PowerPro_lto.o
oldTimeMSTickZero0x200006AC44PowerPro_lto.o
offTimeCounterRTZero0x200006B044PowerPro_lto.o
offTimeCounterGNZero0x200006B444PowerPro_lto.o
offTimeCounterZero0x200006B844PowerPro_lto.o
numberOfBlinksZero0x200006BC44PowerPro_lto.o
msCounterZero0x200006C044PowerPro_lto.o
longPressCounterButtonOnZero0x200006C444PowerPro_lto.o
longPressCounterButtonOffZero0x200006C844PowerPro_lto.o
__SEGGER_RTL_stdout_fileZero0x200006CC44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_fileZero0x200006D044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_fileZero0x200006D444prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_locale_ptrZero0x200006D844mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
ic_overflowsZero0x200006DC44PowerPro_lto.o
frequencyZero0x200006E044PowerPro_lto.o
dropLimitCounterZero0x200006E444PowerPro_lto.o
calTemperatureSensor30ValueZero0x200006E844PowerPro_lto.o
blinkCounterZero0x200006EC44PowerPro_lto.o
autoRetryMode.190Zero0x200006F044PowerPro_lto.o
autoRetryModeZero0x200006F444PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.195Zero0x200006F844PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtimeZero0x200006FC44PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.196Zero0x2000070044PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounterZero0x2000070444PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.201Zero0x2000070844PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counterZero0x2000070C44PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.202Zero0x2000071044PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTickZero0x2000071444PowerPro_lto.o
OVP_SM_On.ovpTimeCounterZero0x2000071844PowerPro_lto.o
OVP_SM_On.oldtimeZero0x2000071C44PowerPro_lto.o
LVP_SM_On.oldtimeZero0x2000072044PowerPro_lto.o
LVP_SM_On.lvpTimeCounterZero0x2000072444PowerPro_lto.o
LVP_OVP_SM_On.oldtimeZero0x2000072844PowerPro_lto.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounterZero0x2000072C44PowerPro_lto.o
relaisStateZero0x2000073014PowerPro_lto.o
smState.191Zero0x2000073111PowerPro_lto.o
smState.181Zero0x2000073211PowerPro_lto.o
smState.166Zero0x2000073311PowerPro_lto.o
pauseTimeZero0x2000073414PowerPro_lto.o
smState.160Zero0x2000073511PowerPro_lto.o
smState.147Zero0x2000073611PowerPro_lto.o
smStateZero0x2000073711PowerPro_lto.o
pFlash.0Zero0x2000073814PowerPro_lto.o
modeZero0x2000073911PowerPro_lto.o
buttonStateZero0x2000073A11PowerPro_lto.o
onTimeRTZero0x2000073C14PowerPro_lto.o
onTimeGNZero0x2000074014PowerPro_lto.o
onTimeZero0x2000074414PowerPro_lto.o
offTimeRTZero0x2000074814PowerPro_lto.o
offTimeGNZero0x2000074C14PowerPro_lto.o
offTimeZero0x2000075014PowerPro_lto.o
blinkModeRTZero0x2000075414PowerPro_lto.o
blinkModeGNZero0x2000075814PowerPro_lto.o
alarmModeZero0x2000075C14PowerPro_lto.o
OVP_SM_On.ovpInputZero0x2000076014PowerPro_lto.o
LVP_SM_On.lvpInputZero0x2000076414PowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInputZero0x2000076814PowerPro_lto.o
_acUpBufferZero0x200007691 0241SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBufferZero0x20000B69161SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
bootLoaderMarkNone0x20000B7C14PowerPro_lto.o
__SEGGER_RTL_global_locale----0x20000B80204mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
uwTickPrio----0x20000B9444PowerPro_lto.o
stdout----0x20000B9844prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdin----0x20000B9C44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stderr----0x20000BA044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
SystemCoreClock----0x20000BA444PowerPro_lto.o
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
PowerPro_lto.o28 1083 14381 680
SEGGER_THUMB_Startup.o20
stm32c031xx_Vectors.o214
STM32C0xx_Startup.o8
Subtotal (4 objects)28 3503 14381 680
libc_v6m_t_le_eabi_small.a2 65632
mbops_timeops_v6m_t_le_eabi_small.a190541204
prinops_rtt_v6m_t_le_eabi_small.a47026121 220
strops_v6m_t_le_eabi_small.a94
Subtotal (4 archives)3 410599321 224
Total:31 7603 742402 904
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)840
fileops.o (libc_v6m_t_le_eabi_small.a)144
floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)992
intasmops_arm.o (libc_v6m_t_le_eabi_small.a)308
mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)190541204
prinops.o (libc_v6m_t_le_eabi_small.a)37232
prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)581212
SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)412261 208
strasmops_arm.o (strops_v6m_t_le_eabi_small.a)34
strops.o (strops_v6m_t_le_eabi_small.a)60
Subtotal (10 members from 4 archives)3 410599321 224
Objects (4 files)28 3503 14381 680
Total:31 7603 742402 904
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Objects (4 files)28 3503 14381 680
Archives (4 files)3 410599321 224
Total:31 7603 742402 904
+

MODULE DETAIL

+

Module PowerPro_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODE_SECONDARYPROTECTION_Exec1 688
HAL_UART_Init1 584
MODE_LVP_Exec1 492
MODE_LVP_OVP_Exec1 492
MX_ADC1_Init1 480
MODE_OVP_Exec1 464
MODE_SECONDARYPROTECTION_PLUS_Exec1 152
USART1_IRQHandler1 120
HAL_ADC_ConfigChannel1 088
MODE_MAINSWITCH_Exec1 048
main988
MX_TIM17_Init780
HAL_RCC_OscConfig708
HAL_GPIO_Init632
HAL_RCCEx_PeriphCLKConfig476
MX_TIM16_Init452
HAL_DMA_Init444
TIM16_IRQHandler436
HAL_ADCEx_Calibration_Start436
HAL_RCC_ClockConfig412
EEPROM_Write404
HAL_TIM_Base_Init396
HAL_ADC_Start_DMA352
MX_USART1_UART_Init304
mbUartInit276
mbSlaveWriteMultipleRegisters276
LEDS_Exec264
HAL_UART_Receive_DMA260
MX_GPIO_Init236
mbSlaveReadHoldingRegisters236
HAL_DMA_Start_IT232
HAL_DMA_IRQHandler232
HAL_UART_ErrorCallback200
mbSlaveWriteSingleRegister192
HAL_TIM_IC_Start_IT176
HAL_UART_Transmit_DMA164
UART_DMAReceiveCplt164
BUTTON_Exec160
TIM_Base_SetConfig156
HAL_TIM_Base_Start_IT148
HAL_TIM_IC_CaptureCallback144
mbInit136
VOLTAGE_MEAS_Exec136
UART_DMAError130
mbSlaveCheckModbusRtuQuery128
mbCrc16116
mbSlaveProcessPdu110
UART_WaitOnFlagUntilTimeout108
BUZZER_Exec108
SystemClock_Config108
TIM_CCxChannelCmd104
ADC_DMAConvCplt102
HAL_InitTick100
mbSlaveProcessRtuQuery100
RELAIS_Exec100
HAL_NVIC_SetPriority96
UART_EndRxTransfer96
MX_IWDG_Init88
SystemCoreClockUpdate84
HAL_RCC_GetSysClockFreq84
FLASH_WaitForLastOperation80
UARTEx_SetNbDataToProcess80
EEPROM_StoreConfig76
UART_DMATransmitCplt74
mbCheckCrc1670
MX_DMA_Init68
MODESWITCH_ReadMode68
mbAppendCrc1666
HAL_RCC_GetPCLK1Freq64
HAL_Init60
CHIP_TEMPERATURE_Exec60
mbSlaveResponseException50
HAL_GPIO_WritePin48
CHIP_TEMPERATURE_Calibration48
EEPROM_WriteDefaults48
HAL_UART_ReceiverTimeout_Config44
HAL_UART_EnableReceiverTimeout42
mbSend38
HAL_FLASH_Unlock36
UART_DMARxHalfCplt36
EEPROM_ReadDeviceParameter36
FAN_SetSpeed36
HAL_FLASH_OB_Unlock32
HAL_NVIC_SystemReset28
assert_failed28
DMA1_Channel2_3_IRQHandler24
mbGetFrameComplete24
SYS_DATA_Init24
mbClearRxFrame22
HAL_Delay20
ADC_DMAError20
HAL_FLASH_OB_Launch20
JumpToBootloader20
HAL_UART_TxCpltCallback20
mbClearTxBuffer18
SysTick_Handler16
DMA1_Channel1_IRQHandler16
SystemInit16
HAL_IWDG_Refresh16
UART_DMAAbortOnError16
HAL_GetTick12
CHIP_TEMPERATURE_GetTemp12
EEPROM_ReadFirstStart12
MODESWITCH_GetMode12
RELAIS_GetTemp12
RELAIS_GetState12
VOLTAGE_MEAS_GetUin12
VOLTAGE_MEAS_GetUout12
HAL_GPIO_ReadPin10
Error_Handler4
NMI_Handler2
HardFault_Handler2
SVC_Handler2
PendSV_Handler2
ADC_DMAHalfConvCplt2
UART_DMATxHalfCplt2
[.rodata..L.str.48]101
[.rodata..L.str.104]100
[.rodata..L.str.16]99
[.rodata..L.str.27]99
[.rodata..L.str.68]99
[.rodata..L.str.86]99
[.rodata..L.str.47]98
[.rodata..L.str.53]97
[.rodata..L.str.101]97
[.rodata..L.str.13]96
[.rodata..L.str.36]96
[.rodata..L.str.63]96
[.rodata..L.str.71]96
AHBPrescTable64
[.rodata..L.str.2]60
[.rodata..Lstr.11.199]60
[.rodata..Lstr.148]53
[.rodata..L.str.1]47
[.rodata..L.str.8]45
[.rodata..Lstr.144]45
[.rodata..Lstr.167]45
[.rodata..Lstr.13.200]43
[.rodata..Lstr.22.183]41
[.rodata..L.str.7.133]39
[.rodata..Lstr.18.155]39
[.rodata..Lstr.12.149]38
[.rodata..Lstr.20.157]38
[.rodata..Lstr.20.176]38
[.rodata..Lstr.15.193]37
[.rodata..Lstr.18]35
[.rodata..Lstr.18.174]35
[.rodata..Lstr.8.197]35
[.rodata..L.str.224]35
[.rodata..Lstr.16.192]34
APBPrescTable32
[.rodata..Lstr.12.161]32
[.rodata..Lstr.12]30
[.rodata..Lstr.12.168]30
[.rodata..Lstr.24.150]29
[.rodata..Lstr.9.198]29
[.rodata..Lstr.3]28
[.rodata..L.str.7]28
[.rodata..Lstr.8]28
[.rodata..Lstr.14.194]28
[.rodata..L.str.5]26
[.rodata..Lstr.10]26
[.rodata..Lstr.24]25
[.rodata..Lstr.15.152]25
[.rodata..Lstr.11]25
[.rodata..Lstr.24.169]25
UARTPrescTable24
[.rodata..Lstr.22.158]23
[.rodata..Lstr.23.159]22
[.rodata..L.str.4]21
[.rodata..Lstr.15]21
[.rodata..Lstr.15.171]21
[.rodata..L.str.117]20
[.rodata..L.str.3]19
[.rodata..Lstr.22]19
[.rodata..Lstr.22.177]19
[.rodata..Lstr]18
[.rodata..L.str.124]18
[.rodata..Lstr.23]18
[.rodata..Lstr.23.178]18
[.rodata..Lstr.4]17
[.rodata..L.str.6]17
[.rodata..L.str.5.131]17
[.rodata..L.str.6.132]17
[.rodata..Lswitch.table.UART_SetConfig]16
[.rodata..L.str.2.128]16
[.rodata..L.str.3.129]16
[.rodata..L.str.4.130]16
[.rodata..Lstr.17.154]16
[.rodata..Lstr.19.156]16
[.rodata..L.str.1.125]14
[.rodata..Lstr.17]9
[.rodata..Lstr.17.173]9
[.rodata..L.str.205]9
UARTEx_SetNbDataToProcess.numerator8
UARTEx_SetNbDataToProcess.denominator8
[.rodata..Lstr.19]8
[.rodata..Lstr.19.175]8
SystemCoreClock4
uwTickPrio4
modbusData564
sys_data224
huart1148
hadc1100
hdma_adc192
hdma_usart1_rx92
hdma_usart1_tx92
htim1776
htim1676
adcData20
flash_device_parameter_default16
uwTick4
longPressCounterButtonOn4
longPressCounterButtonOff4
onTimeCounter4
offTimeCounter4
calTemperatureSensor30Value4
temp4
onTimeCounterGN4
offTimeCounterGN4
onTimeCounterRT4
offTimeCounterRT4
blinkCounter4
numberOfBlinks4
ic_overflows4
oldTimeMSTick4
msCounter4
frequency4
LVP_SM_On.lvpTimeCounter4
LVP_SM_On.oldtime4
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter4
LVP_OVP_SM_On.oldtime4
OVP_SM_On.ovpTimeCounter4
OVP_SM_On.oldtime4
autoRetryMode4
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter4
SECONDARYPROTECTION_SM_On.oldtime4
SECONDARYPROTECTION_SM_Error.retry_counter4
SECONDARYPROTECTION_SM_Error.oldTimeMSTick4
autoRetryMode.1904
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1964
SECONDARYPROTECTION_SM_On.oldtime.1954
SECONDARYPROTECTION_SM_Error.retry_counter.2014
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.2024
relais_temperature4
onTimeCounterSET4
onTimeCounterRESET4
dropLimitCounter4
voltageUin4
voltageUout4
pFlash.01
buttonState1
alarmMode1
offTime1
onTime1
blinkModeGN1
offTimeGN1
onTimeGN1
blinkModeRT1
offTimeRT1
pauseTime1
onTimeRT1
bootLoaderMark1
smState1
LVP_SM_On.lvpInput1
smState.1471
LVP_OVP_SM_On.lvpOROvpInput1
smState.1601
smState.1661
OVP_SM_On.ovpInput1
smState.1811
smState.1911
mode1
relaisState1
Total:28 1083 14381 680
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32c031xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors180
WWDG_IRQHandler2
RTC_IRQHandler2
FLASH_IRQHandler2
RCC_IRQHandler2
EXTI0_1_IRQHandler2
EXTI2_3_IRQHandler2
EXTI4_15_IRQHandler2
DMAMUX1_IRQHandler2
ADC1_IRQHandler2
TIM1_BRK_UP_TRG_COM_IRQHandler2
TIM1_CC_IRQHandler2
TIM3_IRQHandler2
TIM14_IRQHandler2
TIM17_IRQHandler2
I2C1_IRQHandler2
SPI1_IRQHandler2
USART2_IRQHandler2
Total:214
+

Module STM32C0xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler8
Total:8
+

Module fileops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
fwrite50
puts44
fputc34
putchar16
Total:144
+

Module floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_dmul_aux394
__aeabi_ddiv196
__aeabi_fmul182
__aeabi_d2iz52
__aeabi_d2uiz46
__aeabi_f2uiz36
__aeabi_ui2f30
__aeabi_i2d28
__aeabi_ui2d28
Total:992
+

Module intasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_uldivmod136
__aeabi_idiv64
__aeabi_uidiv56
__aeabi_lmul46
__aeabi_idiv06
Total:308
+

Module prinops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_putc138
vfprintf_l108
printf40
__SEGGER_RTL_prin_flush26
vfprintf26
__SEGGER_RTL_init_prin_l18
__SEGGER_RTL_stream_write16
__SEGGER_RTL_hex_uc16
__SEGGER_RTL_hex_lc16
Total:37232
+

Module __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp840
Total:840
+

Module prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_X_file_stat44
__SEGGER_RTL_X_file_write10
__SEGGER_RTL_X_file_bufsize4
stdin4
stdout4
stderr4
__SEGGER_RTL_stdin_file4
__SEGGER_RTL_stdout_file4
__SEGGER_RTL_stderr_file4
Total:581212
+

Module SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SEGGER_RTT_WriteNoLock104
_WriteBlocking88
_DoInit84
_WriteNoCheck58
SEGGER_RTT_Write56
_GetAvailWriteSpace22
_DoInit._aInitStr17
[.rodata.libc..L.str]9
_acUpBuffer1 024
_SEGGER_RTT168
_acDownBuffer16
Total:412261 208
+

Module strops.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
memcmp46
strlen14
Total:60
+

Module strasmops_arm.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr20
memcpy14
Total:34
+

Module mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_ascii_mbtowc46
__SEGGER_RTL_ascii_isctype28
__SEGGER_RTL_ascii_iswctype28
__SEGGER_RTL_current_locale20
__SEGGER_RTL_ascii_wctomb16
__SEGGER_RTL_ascii_tolower14
__SEGGER_RTL_ascii_towlower14
__SEGGER_RTL_ascii_toupper12
__SEGGER_RTL_ascii_towupper12
__SEGGER_RTL_ascii_ctype_map128
__SEGGER_RTL_c_locale_data88
__SEGGER_RTL_c_locale_month_names87
__SEGGER_RTL_c_locale_day_names58
__SEGGER_RTL_c_locale_abbrev_month_names49
__SEGGER_RTL_codeset_ascii32
__SEGGER_RTL_c_locale_abbrev_day_names29
__SEGGER_RTL_c_locale_date_time_format15
__SEGGER_RTL_ascii_ctype_mask13
__SEGGER_RTL_c_locale12
__SEGGER_RTL_c_locale_date_format9
__SEGGER_RTL_c_locale_time_format9
__SEGGER_RTL_c_locale_am_pm_indicator7
[.rodata.libc..L.str]2
__SEGGER_RTL_data_utf8_period2
__SEGGER_RTL_data_empty_string1
__SEGGER_RTL_global_locale20
__SEGGER_RTL_locale_ptr4
Total:190541204
+

All modules

+ + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:31 7603 742402 904
+

UNPLACED SECTIONS AND BLOCKS

+

Unplaced sections

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.rodata..Lstr.148351PowerPro_lto.o
.rodata..Lstr.12.149261PowerPro_lto.o
.rodata..Lstr.15.152191PowerPro_lto.o
.rodata..Lstr.17.154101PowerPro_lto.o
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.rodata..L.str.224231PowerPro_lto.o
.init.Reset_Handler82STM32C0xx_Startup.o
.init_array44STM32C0xx_Startup.o
.text.libc.__aeabi_ddivC42floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_d2iz342floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_f2uiz242floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_ui2d1C2floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_idiv402intasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_uidiv382intasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_uldivmod882intasmops_arm.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_prin_flush1A2prinops.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_init_prin_l122prinops.o (libc_v6m_t_le_eabi_small.a)
.text.libc.vfprintf1A2prinops.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_stream_write102prinops.o (libc_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_hex_uc101prinops.o (libc_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_hex_lc101prinops.o (libc_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_X_file_writeA2prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
.text.libc._GetAvailWriteSpace162SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
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.rodata.libc._DoInit._aInitStr111SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
.rodata.libc..L.str91SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
.text.libc.memcmp2E2strops.o (strops_v6m_t_le_eabi_small.a)
.text.libc.strlenE2strops.o (strops_v6m_t_le_eabi_small.a)
.text.libc.memcpyE2strasmops_arm.o (strops_v6m_t_le_eabi_small.a)
.text.libc.__aeabi_memclr142strasmops_arm.o (strops_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_ascii_mbtowc2E2mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_ascii_wctomb102mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_ascii_toupperC2mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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.text.libc.__SEGGER_RTL_ascii_towupperC2mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.text.libc.__SEGGER_RTL_ascii_towlowerE2mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_c_locale_day_names3A1mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_c_locale_month_names571mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_c_locale_am_pm_indicator71mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_c_locale_date_format91mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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.rodata.libc.__SEGGER_RTL_c_locale_date_time_formatF1mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc..L.str21mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_c_locale_abbrev_day_names1D1mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_c_locale_abbrev_month_names311mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_data_utf8_period21mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_data_empty_string11mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_ascii_ctype_map801mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
.rodata.libc.__SEGGER_RTL_ascii_ctype_maskD1mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
Total:4786
+

LINK SUMMARY

+ +
+Link complete: 58 error.
+
+ Index: /trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1632 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49 + Copyright (c) 2017-2025 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 22 484 2 386 8 1 629 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 214 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 22 726 2 386 8 1 629 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_balanced.a 2 812 32 + mbops_timeops_v6m_t_le_eabi_balanced.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 478 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 74 + strops_v6m_t_le_eabi_balanced.a 414 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 3 968 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 196 2 048 + ============================================= ========== ========== ========== ========== + Total: 26 694 3 181 40 4 901 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 960 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 146 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 992 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 348 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 412 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 34 + strops.o (strops_v6m_t_le_eabi_balanced.a) 380 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (11 members from 5 archives) 3 968 599 32 1 224 + Objects (4 files) 22 726 2 386 8 1 629 + Linker created (shared data, fills, blocks): 196 2 048 + ============================================= ========== ========== ========== ========== + Total: 26 694 3 181 40 4 901 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 196 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 196 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 22 726 2 386 8 1 629 + Archives (5 files) 3 968 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 26 694 3 181 40 4 901 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000B3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000B4-0800067B MX_ADC1_Init 1 480 4 Code RX PowerPro_lto.o + 0800067C-080006BF MX_DMA_Init 68 4 Code RX PowerPro_lto.o + 080006C0-080007AB MX_GPIO_Init 236 4 Code RX PowerPro_lto.o + 080007AC-080007BB SysTick_Handler 16 4 Code RX PowerPro_lto.o + 080007BC-080007CB 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strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset 0x08005DE3 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 0x08005DE3 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 0x08005DE3 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 0x080056A9 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 0x08005FAD 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 0x08005705 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 0x0800573D 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uldivmod 0x0800574D 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __startup_complete 0x0800552B 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x08005521 14 4 Code Gb SEGGER_THUMB_Startup.o + assert_failed 0x080041B9 28 4 Code Lc PowerPro_lto.o + exit 0x0800552F 2 4 Code Gb SEGGER_THUMB_Startup.o + fputc 0x08006313 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 0x08006731 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x08003D75 964 4 Code Gb PowerPro_lto.o + mbAppendCrc16 0x080061F9 66 2 Code Lc PowerPro_lto.o + mbCheckCrc16 0x080061B3 70 2 Code Lc PowerPro_lto.o + mbClearRxFrame 0x0800623B 22 2 Code Lc PowerPro_lto.o + mbClearTxBuffer 0x080061A1 18 2 Code Lc PowerPro_lto.o + mbCrc16 0x0800444D 116 4 Code Lc PowerPro_lto.o + mbGetFrameComplete 0x080044C1 24 4 Code Lc PowerPro_lto.o + mbInit 0x080041D5 136 4 Code Lc PowerPro_lto.o + mbSend 0x0800617B 38 2 Code Lc PowerPro_lto.o + mbSlaveCheckModbusRtuQuery + 0x080044D9 128 4 Code Lc PowerPro_lto.o + mbSlaveProcessPdu 0x08006251 110 2 Code Lc PowerPro_lto.o + mbSlaveProcessRtuQuery 0x08004559 100 4 Code Lc PowerPro_lto.o + mbSlaveReadHoldingRegisters + 0x080045BD 236 4 Code Lc PowerPro_lto.o + mbSlaveResponseException 0x080062BF 50 2 Code Lc PowerPro_lto.o + mbSlaveWriteMultipleRegisters + 0x08004769 276 4 Code Lc PowerPro_lto.o + mbSlaveWriteSingleRegister + 0x080046A9 192 4 Code Lc PowerPro_lto.o + mbUartInit 0x0800425D 276 4 Code Lc PowerPro_lto.o + memcmp 0x080067D1 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + memcpy 0x08006069 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + memset 0x08005DE9 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + printf 0x08005865 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + putchar 0x08005535 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + puts 0x08005545 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x08006729 2 Code Gb STM32C0xx_Startup.o + strlen 0x08005D75 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + vfprintf 0x08006563 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x080057ED 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 MX_ADC1_Init 1 480 4 Code Lc PowerPro_lto.o + 0x0800067D MX_DMA_Init 68 4 Code Lc PowerPro_lto.o + 0x080006C1 MX_GPIO_Init 236 4 Code Lc PowerPro_lto.o + 0x080007AD SysTick_Handler 16 4 Code Gb PowerPro_lto.o + 0x080007BD DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080007CD DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + 0x080007E5 TIM16_IRQHandler 436 4 Code Gb PowerPro_lto.o + 0x08000999 USART1_IRQHandler 1 120 4 Code Gb PowerPro_lto.o + 0x08000DF9 HAL_TIM_IC_CaptureCallback + 144 4 Code Lc PowerPro_lto.o + 0x08000E89 SystemInit 16 4 Code Gb PowerPro_lto.o + 0x08000E99 SystemCoreClockUpdate 84 4 Code Gb PowerPro_lto.o + 0x08000EED MX_TIM16_Init 452 4 Code Lc PowerPro_lto.o + 0x080010B1 MX_TIM17_Init 780 4 Code Lc PowerPro_lto.o + 0x080013BD MX_USART1_UART_Init 304 4 Code Lc PowerPro_lto.o + 0x080014ED MX_IWDG_Init 88 4 Code Lc PowerPro_lto.o + 0x08001545 HAL_Init 60 4 Code Lc PowerPro_lto.o + 0x08001581 HAL_InitTick 100 4 Code Lc PowerPro_lto.o + 0x080015E5 HAL_GetTick 12 4 Code Lc PowerPro_lto.o + 0x080015F1 HAL_Delay 20 4 Code Lc PowerPro_lto.o + 0x08001605 HAL_ADC_Start_DMA 352 4 Code Lc PowerPro_lto.o + 0x08001765 HAL_ADC_ConfigChannel 1 088 4 Code Lc PowerPro_lto.o + 0x08001BA5 HAL_ADCEx_Calibration_Start + 436 4 Code Lc PowerPro_lto.o + 0x08001D59 HAL_NVIC_SetPriority 96 4 Code Lc PowerPro_lto.o + 0x08001DB9 HAL_NVIC_SystemReset 28 4 Code Lc PowerPro_lto.o + 0x08001DD5 HAL_DMA_Init 444 4 Code Lc PowerPro_lto.o + 0x08001F91 HAL_DMA_Start_IT 232 4 Code Lc PowerPro_lto.o + 0x08002079 HAL_DMA_IRQHandler 232 4 Code Lc PowerPro_lto.o + 0x08002161 FLASH_WaitForLastOperation + 80 4 Code Lc PowerPro_lto.o + 0x080021B1 HAL_FLASH_Unlock 36 4 Code Lc PowerPro_lto.o + 0x080021D5 HAL_FLASH_OB_Unlock 32 4 Code Lc PowerPro_lto.o + 0x080021F5 HAL_FLASH_OB_Launch 20 4 Code Lc PowerPro_lto.o + 0x08002209 HAL_GPIO_Init 632 4 Code Lc PowerPro_lto.o + 0x08002481 HAL_GPIO_WritePin 48 4 Code Lc PowerPro_lto.o + 0x080024B1 HAL_IWDG_Refresh 16 4 Code Lc PowerPro_lto.o + 0x080024C1 HAL_RCC_OscConfig 708 4 Code Lc PowerPro_lto.o + 0x08002785 HAL_RCC_ClockConfig 412 4 Code Lc PowerPro_lto.o + 0x08002921 HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + 0x08002975 HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + 0x080029B5 HAL_RCCEx_PeriphCLKConfig 476 4 Code Lc PowerPro_lto.o + 0x08002B91 HAL_TIM_Base_Init 396 4 Code Lc PowerPro_lto.o + 0x08002D1D TIM_Base_SetConfig 156 4 Code Lc PowerPro_lto.o + 0x08002DB9 HAL_TIM_Base_Start_IT 148 4 Code Lc PowerPro_lto.o + 0x08002E4D TIM_CCxChannelCmd 104 4 Code Lc PowerPro_lto.o + 0x08002EB5 HAL_TIM_IC_Start_IT 176 4 Code Lc PowerPro_lto.o + 0x08002F65 HAL_UART_Init 1 584 4 Code Lc PowerPro_lto.o + 0x08003595 UART_WaitOnFlagUntilTimeout + 108 4 Code Lc PowerPro_lto.o + 0x08003601 UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + 0x08003661 HAL_UART_Transmit_DMA 164 4 Code Lc PowerPro_lto.o + 0x08003705 HAL_UART_Receive_DMA 260 4 Code Lc PowerPro_lto.o + 0x08003809 HAL_UART_ReceiverTimeout_Config + 44 4 Code Lc PowerPro_lto.o + 0x08003835 UARTEx_SetNbDataToProcess 80 4 Code Lc PowerPro_lto.o + 0x08003885 BUTTON_Exec 160 4 Code Lc PowerPro_lto.o + 0x08003925 BUZZER_Exec 108 4 Code Lc PowerPro_lto.o + 0x08003991 CHIP_TEMPERATURE_Calibration + 48 4 Code Lc PowerPro_lto.o + 0x080039C1 CHIP_TEMPERATURE_Exec 60 4 Code Lc PowerPro_lto.o + 0x080039FD CHIP_TEMPERATURE_GetTemp 12 4 Code Lc PowerPro_lto.o + 0x08003A09 EEPROM_Write 404 4 Code Lc PowerPro_lto.o + 0x08003B9D EEPROM_WriteDefaults 48 4 Code Lc PowerPro_lto.o + 0x08003BCD EEPROM_ReadFirstStart 12 4 Code Lc PowerPro_lto.o + 0x08003BD9 EEPROM_ReadDeviceParameter + 36 4 Code Lc PowerPro_lto.o + 0x08003BFD EEPROM_StoreConfig 76 4 Code Lc PowerPro_lto.o + 0x08003C49 FAN_SetSpeed 36 4 Code Lc PowerPro_lto.o + 0x08003C6D LEDS_Exec 264 4 Code Lc PowerPro_lto.o + 0x08003D75 main 964 4 Code Gb PowerPro_lto.o + 0x08004139 JumpToBootloader 20 4 Code Lc PowerPro_lto.o + 0x0800414D SystemClock_Config 108 4 Code Lc PowerPro_lto.o + 0x080041B9 assert_failed 28 4 Code Lc PowerPro_lto.o + 0x080041D5 mbInit 136 4 Code Lc PowerPro_lto.o + 0x0800425D mbUartInit 276 4 Code Lc PowerPro_lto.o + 0x08004371 HAL_UART_ErrorCallback 200 4 Code Lc PowerPro_lto.o + 0x08004439 HAL_UART_TxCpltCallback 20 4 Code Lc PowerPro_lto.o + 0x0800444D mbCrc16 116 4 Code Lc PowerPro_lto.o + 0x080044C1 mbGetFrameComplete 24 4 Code Lc PowerPro_lto.o + 0x080044D9 mbSlaveCheckModbusRtuQuery + 128 4 Code Lc PowerPro_lto.o + 0x08004559 mbSlaveProcessRtuQuery 100 4 Code Lc PowerPro_lto.o + 0x080045BD mbSlaveReadHoldingRegisters + 236 4 Code Lc PowerPro_lto.o + 0x080046A9 mbSlaveWriteSingleRegister + 192 4 Code Lc PowerPro_lto.o + 0x08004769 mbSlaveWriteMultipleRegisters + 276 4 Code Lc PowerPro_lto.o + 0x0800487D MODE_MAINSWITCH_Exec 1 048 4 Code Lc PowerPro_lto.o + 0x08004C95 MODE_SECONDARYPROTECTION_Exec + 1 688 4 Code Lc PowerPro_lto.o + 0x0800532D MODESWITCH_ReadMode 68 4 Code Lc PowerPro_lto.o + 0x08005371 MODESWITCH_GetMode 12 4 Code Lc PowerPro_lto.o + 0x0800537D RELAIS_GetTemp 12 4 Code Lc PowerPro_lto.o + 0x08005389 RELAIS_Exec 100 4 Code Lc PowerPro_lto.o + 0x080053ED RELAIS_GetState 12 4 Code Lc PowerPro_lto.o + 0x080053F9 SYS_DATA_Init 24 4 Code Lc PowerPro_lto.o + 0x08005411 VOLTAGE_MEAS_Exec 136 4 Code Lc PowerPro_lto.o + 0x08005499 VOLTAGE_MEAS_GetUin 12 4 Code Lc PowerPro_lto.o + 0x080054A5 VOLTAGE_MEAS_GetUout 12 4 Code Lc PowerPro_lto.o + 0x08005521 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x0800552B __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x0800552B __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x0800552F exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08005535 putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005545 puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005571 __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005635 __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005669 __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800568D __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080056A9 __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080056C5 __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005705 __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800573D __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800574D __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080057ED vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005865 printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800588D __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800588D __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005C4D __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005C81 _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005CD5 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005D3D SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005D75 strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE1 __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE1 __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE1 __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE3 __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE3 __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE3 __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DE9 memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005DF5 __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005E09 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005E25 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005EC5 __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005F7B NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005F7D __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005FAB HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005FAD __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005FCB SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005FCD __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005FFB PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005FFD __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08006003 ADC_DMAConvCplt 102 2 Code Lc PowerPro_lto.o + 0x08006069 memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08006069 __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08006069 __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08006069 __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08006077 ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + 0x08006079 HAL_GPIO_ReadPin 10 2 Code Lc PowerPro_lto.o + 0x08006083 UART_DMATransmitCplt 74 2 Code Lc PowerPro_lto.o + 0x080060CD UART_DMATxHalfCplt 2 2 Code Lc PowerPro_lto.o + 0x080060CF UART_DMAError 130 2 Code Lc PowerPro_lto.o + 0x08006151 HAL_UART_EnableReceiverTimeout + 42 2 Code Lc PowerPro_lto.o + 0x0800617B mbSend 38 2 Code Lc PowerPro_lto.o + 0x080061A1 mbClearTxBuffer 18 2 Code Lc PowerPro_lto.o + 0x080061B3 mbCheckCrc16 70 2 Code Lc PowerPro_lto.o + 0x080061F9 mbAppendCrc16 66 2 Code Lc PowerPro_lto.o + 0x0800623B mbClearRxFrame 22 2 Code Lc PowerPro_lto.o + 0x08006251 mbSlaveProcessPdu 110 2 Code Lc PowerPro_lto.o + 0x080062BF mbSlaveResponseException 50 2 Code Lc PowerPro_lto.o + 0x080062F1 WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062F3 RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062F5 FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062F7 RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062F9 EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062FB EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062FD EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080062FF DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006301 ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006303 TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x08006305 TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006307 TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006309 TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800630B TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800630D I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800630F SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006311 USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006313 fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08006335 __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800636D __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080064BF __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08006549 __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08006563 vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800657D __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08006587 _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x0800659D _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080065D7 __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08006605 __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08006613 __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08006621 ADC_DMAError 20 2 Code Lc PowerPro_lto.o + 0x08006635 UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + 0x080066D9 UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + 0x080066FD UART_DMAAbortOnError 16 2 Code Lc PowerPro_lto.o + 0x0800670D Error_Handler 4 2 Code Lc PowerPro_lto.o + 0x08006729 reset_handler 2 Code Gb STM32C0xx_Startup.o + 0x08006729 Reset_Handler 2 Code Gb STM32C0xx_Startup.o + 0x08006731 fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08006765 __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08006775 __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08006779 _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080067D1 memcmp 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x080068E1 __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080068F1 __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080068FD __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080073AD __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0x08007495 __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0x080074A7 __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + +Function symbols by descending size: + + Symbol name Size Align Type Bd Object File + ------------------------- ---------- ----- ---- -- ----------- + MODE_SECONDARYPROTECTION_Exec + 1 688 4 Code Lc PowerPro_lto.o + HAL_UART_Init 1 584 4 Code Lc PowerPro_lto.o + MX_ADC1_Init 1 480 4 Code Lc PowerPro_lto.o + USART1_IRQHandler 1 120 4 Code Gb PowerPro_lto.o + HAL_ADC_ConfigChannel 1 088 4 Code Lc PowerPro_lto.o + MODE_MAINSWITCH_Exec 1 048 4 Code Lc PowerPro_lto.o + main 964 4 Code Gb PowerPro_lto.o + __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + MX_TIM17_Init 780 4 Code Lc PowerPro_lto.o + HAL_RCC_OscConfig 708 4 Code Lc PowerPro_lto.o + HAL_GPIO_Init 632 4 Code Lc PowerPro_lto.o + HAL_RCCEx_PeriphCLKConfig 476 4 Code Lc PowerPro_lto.o + MX_TIM16_Init 452 4 Code Lc PowerPro_lto.o + HAL_DMA_Init 444 4 Code Lc PowerPro_lto.o + HAL_ADCEx_Calibration_Start + 436 4 Code Lc PowerPro_lto.o + TIM16_IRQHandler 436 4 Code Gb PowerPro_lto.o + HAL_RCC_ClockConfig 412 4 Code Lc PowerPro_lto.o + EEPROM_Write 404 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 396 4 Code Lc PowerPro_lto.o + __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_ADC_Start_DMA 352 4 Code Lc PowerPro_lto.o + MX_USART1_UART_Init 304 4 Code Lc PowerPro_lto.o + mbSlaveWriteMultipleRegisters + 276 4 Code Lc PowerPro_lto.o + mbUartInit 276 4 Code Lc PowerPro_lto.o + memcmp 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + LEDS_Exec 264 4 Code Lc PowerPro_lto.o + HAL_UART_Receive_DMA 260 4 Code Lc PowerPro_lto.o + MX_GPIO_Init 236 4 Code Lc PowerPro_lto.o + mbSlaveReadHoldingRegisters + 236 4 Code Lc PowerPro_lto.o + HAL_DMA_IRQHandler 232 4 Code Lc PowerPro_lto.o + HAL_DMA_Start_IT 232 4 Code Lc PowerPro_lto.o + HAL_UART_ErrorCallback 200 4 Code Lc PowerPro_lto.o + __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbSlaveWriteSingleRegister + 192 4 Code Lc PowerPro_lto.o + __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_TIM_IC_Start_IT 176 4 Code Lc PowerPro_lto.o + HAL_UART_Transmit_DMA 164 4 Code Lc PowerPro_lto.o + UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + BUTTON_Exec 160 4 Code Lc PowerPro_lto.o + __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + TIM_Base_SetConfig 156 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Start_IT 148 4 Code Lc PowerPro_lto.o + HAL_TIM_IC_CaptureCallback + 144 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + VOLTAGE_MEAS_Exec 136 4 Code Lc PowerPro_lto.o + mbInit 136 4 Code Lc PowerPro_lto.o + UART_DMAError 130 2 Code Lc PowerPro_lto.o + mbSlaveCheckModbusRtuQuery + 128 4 Code Lc PowerPro_lto.o + vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + mbCrc16 116 4 Code Lc PowerPro_lto.o + mbSlaveProcessPdu 110 2 Code Lc PowerPro_lto.o + BUZZER_Exec 108 4 Code Lc PowerPro_lto.o + SystemClock_Config 108 4 Code Lc PowerPro_lto.o + UART_WaitOnFlagUntilTimeout + 108 4 Code Lc PowerPro_lto.o + strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + TIM_CCxChannelCmd 104 4 Code Lc PowerPro_lto.o + ADC_DMAConvCplt 102 2 Code Lc PowerPro_lto.o + HAL_InitTick 100 4 Code Lc PowerPro_lto.o + RELAIS_Exec 100 4 Code Lc PowerPro_lto.o + mbSlaveProcessRtuQuery 100 4 Code Lc PowerPro_lto.o + HAL_NVIC_SetPriority 96 4 Code Lc PowerPro_lto.o + UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + MX_IWDG_Init 88 4 Code Lc PowerPro_lto.o + _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + SystemCoreClockUpdate 84 4 Code Gb PowerPro_lto.o + _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + FLASH_WaitForLastOperation + 80 4 Code Lc PowerPro_lto.o + UARTEx_SetNbDataToProcess 80 4 Code Lc PowerPro_lto.o + EEPROM_StoreConfig 76 4 Code Lc PowerPro_lto.o + UART_DMATransmitCplt 74 2 Code Lc PowerPro_lto.o + mbCheckCrc16 70 2 Code Lc PowerPro_lto.o + MODESWITCH_ReadMode 68 4 Code Lc PowerPro_lto.o + MX_DMA_Init 68 4 Code Lc PowerPro_lto.o + mbAppendCrc16 66 2 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + CHIP_TEMPERATURE_Exec 60 4 Code Lc PowerPro_lto.o + HAL_Init 60 4 Code Lc PowerPro_lto.o + _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + mbSlaveResponseException 50 2 Code Lc PowerPro_lto.o + CHIP_TEMPERATURE_Calibration + 48 4 Code Lc PowerPro_lto.o + EEPROM_WriteDefaults 48 4 Code Lc PowerPro_lto.o + HAL_GPIO_WritePin 48 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_UART_ReceiverTimeout_Config + 44 4 Code Lc PowerPro_lto.o + puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + HAL_UART_EnableReceiverTimeout + 42 2 Code Lc PowerPro_lto.o + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + mbSend 38 2 Code Lc PowerPro_lto.o + EEPROM_ReadDeviceParameter + 36 4 Code Lc PowerPro_lto.o + FAN_SetSpeed 36 4 Code Lc PowerPro_lto.o + HAL_FLASH_Unlock 36 4 Code Lc PowerPro_lto.o + UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + HAL_FLASH_OB_Unlock 32 4 Code Lc PowerPro_lto.o + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_NVIC_SystemReset 28 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + assert_failed 28 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + SYS_DATA_Init 24 4 Code Lc PowerPro_lto.o + mbGetFrameComplete 24 4 Code Lc PowerPro_lto.o + _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbClearRxFrame 22 2 Code Lc PowerPro_lto.o + ADC_DMAError 20 2 Code Lc PowerPro_lto.o + HAL_Delay 20 4 Code Lc PowerPro_lto.o + HAL_FLASH_OB_Launch 20 4 Code Lc PowerPro_lto.o + HAL_UART_TxCpltCallback 20 4 Code Lc PowerPro_lto.o + JumpToBootloader 20 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + mbClearTxBuffer 18 2 Code Lc PowerPro_lto.o + DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + HAL_IWDG_Refresh 16 4 Code Lc PowerPro_lto.o + SysTick_Handler 16 4 Code Gb PowerPro_lto.o + SystemInit 16 4 Code Gb PowerPro_lto.o + UART_DMAAbortOnError 16 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + _start 14 4 Code Gb SEGGER_THUMB_Startup.o + memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + CHIP_TEMPERATURE_GetTemp 12 4 Code Lc PowerPro_lto.o + EEPROM_ReadFirstStart 12 4 Code Lc PowerPro_lto.o + HAL_GetTick 12 4 Code Lc PowerPro_lto.o + MODESWITCH_GetMode 12 4 Code Lc PowerPro_lto.o + RELAIS_GetState 12 4 Code Lc PowerPro_lto.o + RELAIS_GetTemp 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetUin 12 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetUout 12 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + HAL_GPIO_ReadPin 10 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + Error_Handler 4 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + HardFault_Handler 2 2 Code Gb PowerPro_lto.o + NMI_Handler 2 2 Code Gb PowerPro_lto.o + PendSV_Handler 2 2 Code Gb PowerPro_lto.o + SVC_Handler 2 2 Code Gb PowerPro_lto.o + UART_DMATxHalfCplt 2 2 Code Lc PowerPro_lto.o + exit 2 4 Code Gb SEGGER_THUMB_Startup.o + ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + Reset_Handler 2 Code Gb STM32C0xx_Startup.o + SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + reset_handler 2 Code Gb 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Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/FEE.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/FEE.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/FEE.d (revision 41) @@ -0,0 +1,49 @@ +Output/Debug_12V/Obj/PowerPro/FEE.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\FEE.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\FEE.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\string.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_files.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_files.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_files.ind (revision 41) @@ -0,0 +1,56 @@ +"Output/Debug_12V/Obj/PowerPro/adc.bc" +"Output/Debug_12V/Obj/PowerPro/dma.bc" +"Output/Debug_12V/Obj/PowerPro/gpio.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_msp.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_it.bc" +"Output/Debug_12V/Obj/PowerPro/system_stm32c0xx.bc" +"Output/Debug_12V/Obj/PowerPro/tim.bc" +"Output/Debug_12V/Obj/PowerPro/usart.bc" +"Output/Debug_12V/Obj/PowerPro/iwdg.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_cortex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_exti.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_gpio.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart.bc" +"Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc" +"Output/Debug_12V/Obj/PowerPro/button.bc" +"Output/Debug_12V/Obj/PowerPro/buzzer.bc" +"Output/Debug_12V/Obj/PowerPro/chip_temperature.bc" +"Output/Debug_12V/Obj/PowerPro/eeprom.bc" +"Output/Debug_12V/Obj/PowerPro/fan.bc" +"Output/Debug_12V/Obj/PowerPro/leds.bc" +"Output/Debug_12V/Obj/PowerPro/main.bc" +"Output/Debug_12V/Obj/PowerPro/modbus.bc" +"Output/Debug_12V/Obj/PowerPro/mode_lvp.bc" +"Output/Debug_12V/Obj/PowerPro/mode_lvp_ovp.bc" +"Output/Debug_12V/Obj/PowerPro/mode_mainswitch.bc" +"Output/Debug_12V/Obj/PowerPro/mode_ovp.bc" +"Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection.bc" +"Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection_plus.bc" +"Output/Debug_12V/Obj/PowerPro/modeswitch.bc" +"Output/Debug_12V/Obj/PowerPro/relais.bc" +"Output/Debug_12V/Obj/PowerPro/sysdata.bc" +"Output/Debug_12V/Obj/PowerPro/voltage_meas.bc" +"Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o" +"Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.o" +"Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a" Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_link.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_link.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/PowerPro_link.ind (revision 41) @@ -0,0 +1,10 @@ +Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o +Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.o +Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.o +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a" Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_12V/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_12V/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_12V/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/eeprom.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/eeprom.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/eeprom.d (revision 41) @@ -0,0 +1,49 @@ +Output/Debug_12V/Obj/PowerPro/eeprom.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\eeprom.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\string.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_12V/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,70 @@ +Output/Debug_12V/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/modbus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/modbus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/modbus.d (revision 41) @@ -0,0 +1,48 @@ +Output/Debug_12V/Obj/PowerPro/modbus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modbus.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_12V/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_12V/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_12V/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_12V/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,53 @@ +Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,53 @@ +Output/Debug_12V/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_12V/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_12V/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_12V/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Debug_12V/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/sysdata.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/sysdata.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/sysdata.d (revision 41) @@ -0,0 +1,46 @@ +Output/Debug_12V/Obj/PowerPro/sysdata.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\sysdata.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Debug_12V/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_12V/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_12V/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_12V/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,49 @@ +Output/Debug_12V/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.htm =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.htm (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.htm (revision 41) @@ -0,0 +1,8991 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ +
+SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49
+Copyright (c) 2017-2025 SEGGER Microcontroller GmbH    www.segger.com
+
+ +
+--add-region:FLASH1=0x00007800@0x08000000
+--add-region:RAM1=0x00003000@0x20000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Debug_24V/Exe/PowerPro.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=6-M
+--silent
+-TD:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf
+--defsym=__STACKSIZE__=2048
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=1024
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_int_nwp
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.elf
+Output/Debug_24V/Obj/PowerPro/adc.o
+Output/Debug_24V/Obj/PowerPro/dma.o
+Output/Debug_24V/Obj/PowerPro/gpio.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.o
+Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.o
+Output/Debug_24V/Obj/PowerPro/tim.o
+Output/Debug_24V/Obj/PowerPro/usart.o
+Output/Debug_24V/Obj/PowerPro/iwdg.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.o
+Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.o
+Output/Debug_24V/Obj/PowerPro/button.o
+Output/Debug_24V/Obj/PowerPro/buzzer.o
+Output/Debug_24V/Obj/PowerPro/chip_temperature.o
+Output/Debug_24V/Obj/PowerPro/eeprom.o
+Output/Debug_24V/Obj/PowerPro/fan.o
+Output/Debug_24V/Obj/PowerPro/leds.o
+Output/Debug_24V/Obj/PowerPro/main.o
+Output/Debug_24V/Obj/PowerPro/modbus.o
+Output/Debug_24V/Obj/PowerPro/mode_lvp.o
+Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.o
+Output/Debug_24V/Obj/PowerPro/mode_mainswitch.o
+Output/Debug_24V/Obj/PowerPro/mode_ovp.o
+Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.o
+Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.o
+Output/Debug_24V/Obj/PowerPro/modeswitch.o
+Output/Debug_24V/Obj/PowerPro/relais.o
+Output/Debug_24V/Obj/PowerPro/sysdata.o
+Output/Debug_24V/Obj/PowerPro/voltage_meas.o
+Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o
+Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o
+Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_balanced.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf'

+
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32C0xx_Flash.icf
+Purpose : STM32C0xx linker script for application placement in Flash,
+          for use with the SEGGER Linker.
+Maps    : STM32C011D6Yx, STM32C011F4Px, STM32C011F4Ux, STM32C011F6Px, 
+          STM32C011F6Ux, STM32C011J4Mx, STM32C011J6Mx, STM32C031C4Tx, 
+          STM32C031C4Ux, STM32C031C6Tx, STM32C031C6Ux, STM32C031F4Px, 
+          STM32C031F6Px, STM32C031G4Ux, STM32C031G6Ux, STM32C031K4Tx, 
+          STM32C031K4Ux, STM32C031K6Tx, STM32C031K6Ux
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM   = RAM1;
+
+//
+// Block definitions
+//
+define block vectors                        { section .vectors };                                   // Vector table section
+define block vectors_ram                    { section .vectors_ram };                               // Vector table section
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { block vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1                             { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { block vectors };                                      // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1                               { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM                       { block vectors_ram };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x08000000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x08000000180256stm32c031xx_Vectors.o
+

place at 0x20003000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#5> at line 111, col 45": place in [0x08000000 to 0x080077ff] with maximum packing

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
MX_ADC1_InitCode0x080000B42204adc.o
HAL_ADC_MspInitCode0x080001901884adc.o
MX_DMA_InitCode0x0800024C684dma.o
MX_GPIO_InitCode0x080002902524gpio.o
HAL_MspInitCode0x0800038C444stm32c0xx_hal_msp.o
DMA1_Channel1_IRQHandlerCode0x080003B8164stm32c0xx_it.o
DMA1_Channel2_3_IRQHandlerCode0x080003C8244stm32c0xx_it.o
TIM16_IRQHandlerCode0x080003E0164stm32c0xx_it.o
USART1_IRQHandlerCode0x080003F0164stm32c0xx_it.o
HAL_TIM_IC_CaptureCallbackCode0x08000400684stm32c0xx_it.o
HAL_TIM_PeriodElapsedCallbackCode0x08000444404stm32c0xx_it.o
SystemInitCode0x0800046C164system_stm32c0xx.o
SystemCoreClockUpdateCode0x0800047C844system_stm32c0xx.o
AHBPrescTableCnst0x080004D0644system_stm32c0xx.o
APBPrescTableCnst0x08000510324system_stm32c0xx.o
MX_TIM16_InitCode0x080005301124tim.o
MX_TIM17_InitCode0x080005A01684tim.o
HAL_TIM_MspPostInitCode0x080006481044tim.o
HAL_TIM_Base_MspInitCode0x080006B01484tim.o
MX_USART1_UART_InitCode0x080007441124usart.o
HAL_UART_MspInitCode0x080007B42564usart.o
MX_IWDG_InitCode0x080008B4444iwdg.o
HAL_InitTickCode0x080008E0764stm32c0xx_hal.o
HAL_IncTickCode0x0800092C244stm32c0xx_hal.o
HAL_GetTickCode0x08000944124stm32c0xx_hal.o
HAL_DelayCode0x08000950364stm32c0xx_hal.o
HAL_ADC_InitCode0x080009745484stm32c0xx_hal_adc.o
ADC_DisableCode0x08000B98964stm32c0xx_hal_adc.o
ADC_EnableCode0x08000BF81644stm32c0xx_hal_adc.o
HAL_ADC_Start_DMACode0x08000C9C1724stm32c0xx_hal_adc.o
HAL_ADC_ConfigChannelCode0x08000D486204stm32c0xx_hal_adc.o
HAL_ADCEx_Calibration_StartCode0x08000FB43604stm32c0xx_hal_adc_ex.o
HAL_NVIC_SetPriorityCode0x0800111C764stm32c0xx_hal_cortex.o
HAL_NVIC_EnableIRQCode0x08001168244stm32c0xx_hal_cortex.o
HAL_NVIC_SystemResetCode0x08001180284stm32c0xx_hal_cortex.o
HAL_SYSTICK_ConfigCode0x0800119C524stm32c0xx_hal_cortex.o
HAL_DMA_InitCode0x080011D01804stm32c0xx_hal_dma.o
DMA_CalcDMAMUXChannelBaseAndMaskCode0x08001284524stm32c0xx_hal_dma.o
DMA_CalcDMAMUXRequestGenBaseAndMaskCode0x080012B8364stm32c0xx_hal_dma.o
DMA_SetConfigCode0x080012DC764stm32c0xx_hal_dma.o
HAL_DMA_AbortCode0x080013281164stm32c0xx_hal_dma.o
HAL_DMA_Abort_ITCode0x0800139C1244stm32c0xx_hal_dma.o
HAL_DMA_IRQHandlerCode0x080014182324stm32c0xx_hal_dma.o
HAL_FLASH_ProgramCode0x080015001204stm32c0xx_hal_flash.o
FLASH_WaitForLastOperationCode0x08001578884stm32c0xx_hal_flash.o
FLASH_Program_FastCode0x080015D0524stm32c0xx_hal_flash.o
HAL_FLASH_UnlockCode0x08001604404stm32c0xx_hal_flash.o
HAL_FLASH_LockCode0x0800162C244stm32c0xx_hal_flash.o
HAL_FLASH_OB_UnlockCode0x08001644404stm32c0xx_hal_flash.o
HAL_FLASH_OB_LaunchCode0x0800166C204stm32c0xx_hal_flash.o
HAL_FLASHEx_EraseCode0x080016801764stm32c0xx_hal_flash_ex.o
HAL_GPIO_InitCode0x080017303764stm32c0xx_hal_gpio.o
HAL_IWDG_InitCode0x080018A81004stm32c0xx_hal_iwdg.o
HAL_IWDG_RefreshCode0x0800190C164stm32c0xx_hal_iwdg.o
HAL_RCC_OscConfigCode0x0800191C5924stm32c0xx_hal_rcc.o
HAL_RCC_ClockConfigCode0x08001B6C3604stm32c0xx_hal_rcc.o
HAL_RCC_GetSysClockFreqCode0x08001CD4844stm32c0xx_hal_rcc.o
HAL_RCC_GetHCLKFreqCode0x08001D28444stm32c0xx_hal_rcc.o
HAL_RCC_GetPCLK1FreqCode0x08001D54364stm32c0xx_hal_rcc.o
HAL_RCCEx_PeriphCLKConfigCode0x08001D783164stm32c0xx_hal_rcc_ex.o
TIM_Base_SetConfigCode0x08001EB41564stm32c0xx_hal_tim.o
HAL_TIM_Base_Start_ITCode0x08001F50844stm32c0xx_hal_tim.o
HAL_TIM_PWM_StartCode0x08001FA42164stm32c0xx_hal_tim.o
HAL_TIM_IC_Start_ITCode0x0800207C2684stm32c0xx_hal_tim.o
HAL_TIM_IRQHandlerCode0x080021884764stm32c0xx_hal_tim.o
TIM_OC1_SetConfigCode0x080023641404stm32c0xx_hal_tim.o
TIM_OC2_SetConfigCode0x080023F01364stm32c0xx_hal_tim.o
TIM_OC3_SetConfigCode0x080024781444stm32c0xx_hal_tim.o
TIM_OC4_SetConfigCode0x080025081084stm32c0xx_hal_tim.o
TIM_OC5_SetConfigCode0x080025741044stm32c0xx_hal_tim.o
TIM_OC6_SetConfigCode0x080025DC1084stm32c0xx_hal_tim.o
HAL_TIM_IC_ConfigChannelCode0x080026482964stm32c0xx_hal_tim.o
TIM_TI1_SetConfigCode0x08002770684stm32c0xx_hal_tim.o
TIM_TI2_SetConfigCode0x080027B4564stm32c0xx_hal_tim.o
[.rodata..Lswitch.table.HAL_TIM_IC_Start_IT]Cnst0x080027EC164stm32c0xx_hal_tim.o
HAL_TIMEx_ConfigBreakDeadTimeCode0x080027FC2004stm32c0xx_hal_tim_ex.o
UART_SetConfigCode0x080028C44124stm32c0xx_hal_uart.o
UART_CheckIdleStateCode0x08002A601964stm32c0xx_hal_uart.o
HAL_UART_Transmit_DMACode0x08002B241764stm32c0xx_hal_uart.o
UART_Start_Receive_DMACode0x08002BD41684stm32c0xx_hal_uart.o
UART_EndRxTransferCode0x08002C7C964stm32c0xx_hal_uart.o
HAL_UART_IRQHandlerCode0x08002CDC1 0084stm32c0xx_hal_uart.o
[.rodata..Lswitch.table.UART_SetConfig]Cnst0x080030CC164stm32c0xx_hal_uart.o
UARTEx_SetNbDataToProcessCode0x080030DC724stm32c0xx_hal_uart_ex.o
BUTTON_ExecCode0x080031241884button.o
BUTTON_GetModeCode0x080031E0124button.o
BUTTON_SetModeOffCode0x080031EC124button.o
BUTTON_SetModeAutoCode0x080031F8124button.o
BUZZER_ExecCode0x080032041004buzzer.o
BUZZER_BeepCode0x08003268284buzzer.o
BUZZER_Alarm_StartCode0x08003284524buzzer.o
BUZZER_Alarm_StopCode0x080032B8444buzzer.o
CHIP_TEMPERATURE_CalibrationCode0x080032E4484chip_temperature.o
CHIP_TEMPERATURE_ExecCode0x08003314604chip_temperature.o
CHIP_TEMPERATURE_GetTempCode0x08003350124chip_temperature.o
EEPROM_WriteCode0x0800335C1604eeprom.o
EEPROM_WriteDefaultsCode0x080033FC484eeprom.o
EEPROM_ReadFirstStartCode0x0800342C124eeprom.o
EEPROM_ReadDeviceParameterCode0x08003438364eeprom.o
EEPROM_StoreConfigCode0x0800345C804eeprom.o
FAN_SetSpeedCode0x080034AC444fan.o
LEDS_ExecCode0x080034D82404leds.o
LEDS_GN_OnCode0x080035C8444leds.o
LEDS_GN_Blink_StartCode0x080035F4524leds.o
LEDS_GN_OffCode0x08003628484leds.o
LEDS_RT_BlinkCode_StartCode0x08003658764leds.o
LEDS_RT_OffCode0x080036A4484leds.o
mainCode0x080036D49924main.o
JumpToBootloaderCode0x08003AB4964main.o
SystemClock_ConfigCode0x08003B141084main.o
mbUartInitCode0x08003B801884modbus.o
HAL_UART_ErrorCallbackCode0x08003C3C1684modbus.o
HAL_UART_TxCpltCallbackCode0x08003CE4164modbus.o
mbCrc16Code0x08003CF4644modbus.o
mbSlaveCheckModbusRtuQueryCode0x08003D34604modbus.o
mbSlaveReadHoldingRegistersCode0x08003D701604modbus.o
mbSlaveWriteSingleRegisterCode0x08003E101004modbus.o
mbSlaveWriteMultipleRegistersCode0x08003E741764modbus.o
MODE_LVP_ExecCode0x08003F247764mode_lvp.o
MODE_LVP_OVP_ExecCode0x0800422C7884mode_lvp_ovp.o
MAINSWITCH_SM_OffCode0x080045401684mode_mainswitch.o
MAINSWITCH_SM_OnCode0x080045E81844mode_mainswitch.o
MAINSWITCH_SM_ManualOnCode0x080046A0524mode_mainswitch.o
MAINSWITCH_SM_ErrorCode0x080046D41564mode_mainswitch.o
MODE_MAINSWITCH_ExecCode0x08004770484mode_mainswitch.o
MODE_OVP_ExecCode0x080047A07604mode_ovp.o
MODE_SECONDARYPROTECTION_ExecCode0x08004A988924mode_secondaryprotection.o
MODE_SECONDARYPROTECTION_PLUS_ExecCode0x08004E146884mode_secondaryprotection_plus.o
MODESWITCH_ReadModeCode0x080050C4884modeswitch.o
MODESWITCH_GetModeCode0x0800511C124modeswitch.o
RELAIS_GetTempCode0x08005128124relais.o
RELAIS_ExecCode0x080051341084relais.o
RELAIS_SetPulsCode0x080051A0524relais.o
RELAIS_ResetPulsCode0x080051D4524relais.o
RELAIS_GetStateCode0x08005208124relais.o
SYS_DATA_InitCode0x08005214244sysdata.o
VOLTAGE_MEAS_ExecCode0x0800522C1444voltage_meas.o
VOLTAGE_MEAS_GetLimitAlarmCode0x080052BC244voltage_meas.o
VOLTAGE_MEAS_ResetCounterCode0x080052D4124voltage_meas.o
VOLTAGE_MEAS_GetUinCode0x080052E0124voltage_meas.o
VOLTAGE_MEAS_GetUoutCode0x080052EC124voltage_meas.o
_startCode0x080052F8204SEGGER_THUMB_Startup.o
putcharCode0x0800530C164fileops.o (libc_v6m_t_le_eabi_balanced.a)
putsCode0x0800531C444fileops.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_ddivCode0x080053481964floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_d2izCode0x0800540C524floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_f2uizCode0x08005440364floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_i2dCode0x08005464284floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_ui2dCode0x08005480284floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_idivCode0x0800549C644intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_uidivCode0x080054DC564intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_uidivmodCode0x08005514164intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
__aeabi_uldivmodCode0x080055241604intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
vfprintf_lCode0x080055C41204prinops.o (libc_v6m_t_le_eabi_balanced.a)
printfCode0x0800563C404prinops.o (libc_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_vfprintf_int_nwpCode0x080056649604__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_X_file_statCode0x08005A24524prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
_DoInitCode0x08005A58844SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
SEGGER_RTT_WriteNoLockCode0x08005AAC1044SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
SEGGER_RTT_WriteCode0x08005B14564SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
strlenCode0x08005B4C1084strops.o (strops_v6m_t_le_eabi_balanced.a)
__aeabi_memclrCode0x08005BB8204strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_current_localeCode0x08005BCC204mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_ascii_isctypeCode0x08005BE0284mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_ascii_iswctypeCode0x08005BFC284mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_c_localeCnst0x08005C18124mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_codeset_asciiCnst0x08005C24324mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
__SEGGER_RTL_c_locale_dataCnst0x08005C44884mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
HAL_TIM_PWM_ConfigChannelCode0x08005C9C3064stm32c0xx_hal_tim.o
NMI_HandlerCode0x08005DCE22stm32c0xx_it.o
__aeabi_fmulCode0x08005DD01824floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
HardFault_HandlerCode0x08005E8622stm32c0xx_it.o
__aeabi_d2uizCode0x08005E88464floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
SVC_HandlerCode0x08005EB622stm32c0xx_it.o
__aeabi_ui2fCode0x08005EB8304floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
PendSV_HandlerCode0x08005ED622stm32c0xx_it.o
__aeabi_lmulCode0x08005ED8464intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
ADC_DMAHalfConvCpltCode0x08005F06102stm32c0xx_hal_adc.o
__aeabi_idiv0Code0x08005F1064intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)
ADC_DMAErrorCode0x08005F16262stm32c0xx_hal_adc.o
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captureValueZero0x2000073C44stm32c0xx_it.o
calTemperatureSensor30ValueZero0x2000074044chip_temperature.o
blinkModeRTZero0x2000074444leds.o
blinkModeGNZero0x2000074844leds.o
blinkCounterZero0x2000074C44leds.o
autoRetryModeZero0x2000075044mode_secondaryprotection.o
autoRetryModeZero0x2000075444mode_secondaryprotection_plus.o
alarmModeZero0x2000075844buzzer.o
SECONDARYPROTECTION_SM_On.oldtimeZero0x2000075C44mode_secondaryprotection.o
SECONDARYPROTECTION_SM_On.oldtimeZero0x2000076044mode_secondaryprotection_plus.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounterZero0x2000076444mode_secondaryprotection.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounterZero0x2000076844mode_secondaryprotection_plus.o
SECONDARYPROTECTION_SM_Error.retry_counterZero0x2000076C44mode_secondaryprotection.o
SECONDARYPROTECTION_SM_Error.retry_counterZero0x2000077044mode_secondaryprotection_plus.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTickZero0x2000077444mode_secondaryprotection.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTickZero0x2000077844mode_secondaryprotection_plus.o
OVP_SM_On.ovpTimeCounterZero0x2000077C44mode_ovp.o
OVP_SM_On.oldtimeZero0x2000078044mode_ovp.o
LVP_SM_On.oldtimeZero0x2000078444mode_lvp.o
LVP_SM_On.lvpTimeCounterZero0x2000078844mode_lvp.o
LVP_OVP_SM_On.oldtimeZero0x2000078C44mode_lvp_ovp.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounterZero0x2000079044mode_lvp_ovp.o
OVP_SM_On.ovpInputZero0x2000079414mode_ovp.o
smStateZero0x2000079511mode_lvp.o
smStateZero0x2000079611mode_lvp_ovp.o
smStateZero0x2000079711mode_mainswitch.o
LVP_SM_On.lvpInputZero0x2000079814mode_lvp.o
smStateZero0x2000079911mode_ovp.o
smStateZero0x2000079A11mode_secondaryprotection.o
smStateZero0x2000079B11mode_secondaryprotection_plus.o
LVP_OVP_SM_On.lvpOROvpInputZero0x2000079C14mode_lvp_ovp.o
_acUpBufferZero0x2000079D1 0241SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
_acDownBufferZero0x20000B9D161SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
modeZero0x20000BAD11modeswitch.o
buttonStateZero0x20000BAE11button.o
uwTickFreqInit0x20000BAF11stm32c0xx_hal.o
bootLoaderMarkNone0x20000BB044main.o
__SEGGER_RTL_global_localeInit0x20000BB4204mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)
uwTickPrioInit0x20000BC844stm32c0xx_hal.o
stdoutInit0x20000BCC44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
stdinInit0x20000BD044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
stderrInit0x20000BD444prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a)
SystemCoreClockInit0x20000BD844system_stm32c0xx.o
[.bss.block.heap]None0x20000BE08[ Linker created ]
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#10> at line 132, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x20000BE08[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
adc.o408192
button.o224639
buzzer.o22420
chip_temperature.o1208
dma.o68
eeprom.o36816
fan.o444
gpio.o252
iwdg.o4416
leds.o50852
main.o1 200220600
modbus.o1 210152
mode_lvp.o77631910
mode_lvp_ovp.o78837010
mode_mainswitch.o6081541
mode_ovp.o76031910
mode_secondaryprotection.o89230721
mode_secondaryprotection_plus.o68826621
modeswitch.o10091
relais.o23616
SEGGER_THUMB_Startup.o20
stm32c031xx_Vectors.o214
stm32c0xx_hal.o17254
stm32c0xx_hal_adc.o1 766
stm32c0xx_hal_adc_ex.o360
stm32c0xx_hal_cortex.o180
stm32c0xx_hal_dma.o954
stm32c0xx_hal_flash.o38424
stm32c0xx_hal_flash_ex.o176
stm32c0xx_hal_gpio.o402
stm32c0xx_hal_iwdg.o116
stm32c0xx_hal_msp.o44
stm32c0xx_hal_rcc.o1 116
stm32c0xx_hal_rcc_ex.o316
stm32c0xx_hal_tim.o2 92016
stm32c0xx_hal_tim_ex.o206
stm32c0xx_hal_uart.o3 18840
stm32c0xx_hal_uart_ex.o26816
stm32c0xx_it.o19612
STM32C0xx_Startup.o8
sysdata.o24224
system_stm32c0xx.o100964
tim.o532152
usart.o368332
voltage_meas.o2043516
Subtotal (45 objects)23 7522 38291 771
libc_v6m_t_le_eabi_balanced.a2 81232
mbops_timeops_v6m_t_le_eabi_balanced.a190541204
prinops_rtt_v6m_t_le_eabi_balanced.a47826121 220
SEGGER_crtinit_v6m_t_le_eabi_balanced.a74
strops_v6m_t_le_eabi_balanced.a414
Subtotal (5 archives)3 968599321 224
Linker created (shared data, fills, blocks):962 048
Total:27 7203 077415 043
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a)960
fileops.o (libc_v6m_t_le_eabi_balanced.a)146
floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)992
intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)348
mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)190541204
prinops.o (libc_v6m_t_le_eabi_balanced.a)36632
prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a)661212
SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a)74
SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)412261 208
strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a)34
strops.o (strops_v6m_t_le_eabi_balanced.a)380
Subtotal (11 members from 5 archives)3 968599321 224
Objects (45 files)23 7522 38291 771
Linker created (shared data, fills, blocks):962 048
Total:27 7203 077415 043
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table96
Memory for block 'stack'2 048
Subtotal (linker created):962 048
Objects (45 files)23 7522 38291 771
Archives (5 files)3 968599321 224
Total:27 7203 077415 043
+

MODULE DETAIL

+

Module adc.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MX_ADC1_Init220
HAL_ADC_MspInit188
hadc1100
hdma_adc192
Total:408192
+

Module dma.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MX_DMA_Init68
Total:68
+

Module gpio.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MX_GPIO_Init252
Total:252
+

Module stm32c0xx_hal_msp.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_MspInit44
Total:44
+

Module stm32c0xx_it.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_TIM_IC_CaptureCallback68
HAL_TIM_PeriodElapsedCallback40
DMA1_Channel2_3_IRQHandler24
DMA1_Channel1_IRQHandler16
TIM16_IRQHandler16
USART1_IRQHandler16
SysTick_Handler8
NMI_Handler2
HardFault_Handler2
SVC_Handler2
PendSV_Handler2
captureValue4
frequency4
ic_overflows4
Total:19612
+

Module system_stm32c0xx.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SystemCoreClockUpdate84
SystemInit16
AHBPrescTable64
APBPrescTable32
SystemCoreClock4
Total:100964
+

Module tim.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MX_TIM17_Init168
HAL_TIM_Base_MspInit148
MX_TIM16_Init112
HAL_TIM_MspPostInit104
htim1676
htim1776
Total:532152
+

Module usart.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_UART_MspInit256
MX_USART1_UART_Init112
huart1148
hdma_usart1_rx92
hdma_usart1_tx92
Total:368332
+

Module iwdg.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MX_IWDG_Init44
hiwdg16
Total:4416
+

Module stm32c0xx_hal.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_InitTick76
HAL_Delay36
HAL_Init24
HAL_IncTick24
HAL_GetTick12
uwTickPrio4
uwTickFreq1
uwTick4
Total:17254
+

Module stm32c0xx_hal_adc.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_ADC_ConfigChannel620
HAL_ADC_Init548
HAL_ADC_Start_DMA172
ADC_Enable164
ADC_DMAConvCplt124
ADC_Disable96
ADC_DMAError26
ADC_DMAHalfConvCplt10
HAL_ADC_ConvCpltCallback2
HAL_ADC_ErrorCallback2
HAL_ADC_ConvHalfCpltCallback2
Total:1 766
+

Module stm32c0xx_hal_adc_ex.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_ADCEx_Calibration_Start360
Total:360
+

Module stm32c0xx_hal_cortex.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_NVIC_SetPriority76
HAL_SYSTICK_Config52
HAL_NVIC_SystemReset28
HAL_NVIC_EnableIRQ24
Total:180
+

Module stm32c0xx_hal_dma.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_DMA_IRQHandler232
HAL_DMA_Init180
HAL_DMA_Start_IT138
HAL_DMA_Abort_IT124
HAL_DMA_Abort116
DMA_SetConfig76
DMA_CalcDMAMUXChannelBaseAndMask52
DMA_CalcDMAMUXRequestGenBaseAndMask36
Total:954
+

Module stm32c0xx_hal_flash.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_FLASH_Program120
FLASH_WaitForLastOperation88
FLASH_Program_Fast52
HAL_FLASH_Unlock40
HAL_FLASH_OB_Unlock40
HAL_FLASH_Lock24
HAL_FLASH_OB_Launch20
pFlash24
Total:38424
+

Module stm32c0xx_hal_flash_ex.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_FLASHEx_Erase176
Total:176
+

Module stm32c0xx_hal_gpio.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_GPIO_Init376
HAL_GPIO_WritePin16
HAL_GPIO_ReadPin10
Total:402
+

Module stm32c0xx_hal_iwdg.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_IWDG_Init100
HAL_IWDG_Refresh16
Total:116
+

Module stm32c0xx_hal_rcc.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_RCC_OscConfig592
HAL_RCC_ClockConfig360
HAL_RCC_GetSysClockFreq84
HAL_RCC_GetHCLKFreq44
HAL_RCC_GetPCLK1Freq36
Total:1 116
+

Module stm32c0xx_hal_rcc_ex.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_RCCEx_PeriphCLKConfig316
Total:316
+

Module stm32c0xx_hal_tim.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_TIM_IRQHandler476
HAL_TIM_PWM_ConfigChannel306
HAL_TIM_IC_ConfigChannel296
HAL_TIM_IC_Start_IT268
HAL_TIM_PWM_Start216
TIM_Base_SetConfig156
TIM_OC3_SetConfig144
TIM_OC1_SetConfig140
TIM_OC2_SetConfig136
TIM_OC4_SetConfig108
TIM_OC6_SetConfig108
TIM_OC5_SetConfig104
HAL_TIM_Base_Start_IT84
HAL_TIM_Base_Init74
HAL_TIM_PWM_Init74
HAL_TIM_IC_Init74
TIM_TI1_SetConfig68
TIM_TI2_SetConfig56
HAL_TIM_ReadCapturedValue22
HAL_TIM_PWM_MspInit2
HAL_TIM_IC_MspInit2
HAL_TIM_OC_DelayElapsedCallback2
HAL_TIM_PWM_PulseFinishedCallback2
HAL_TIM_TriggerCallback2
[.rodata..Lswitch.table.HAL_TIM_IC_Start_IT]16
Total:2 92016
+

Module stm32c0xx_hal_tim_ex.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_TIMEx_ConfigBreakDeadTime200
HAL_TIMEx_CommutCallback2
HAL_TIMEx_BreakCallback2
HAL_TIMEx_Break2Callback2
Total:206
+

Module stm32c0xx_hal_uart.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_UART_IRQHandler1 008
UART_SetConfig412
UART_AdvFeatureConfig210
UART_CheckIdleState196
UART_DMAReceiveCplt182
HAL_UART_Transmit_DMA176
UART_WaitOnFlagUntilTimeout172
UART_Start_Receive_DMA168
HAL_UART_Init112
UART_EndRxTransfer96
HAL_UART_Receive_DMA92
UART_DMAError82
UART_DMATransmitCplt74
UART_EndTxTransfer56
UART_DMARxHalfCplt56
HAL_UART_EnableReceiverTimeout46
UART_DMAAbortOnError16
HAL_UART_ReceiverTimeout_Config16
UART_DMATxHalfCplt10
HAL_UARTEx_RxEventCallback2
HAL_UART_TxHalfCpltCallback2
HAL_UART_RxCpltCallback2
HAL_UART_RxHalfCpltCallback2
UARTPrescTable24
[.rodata..Lswitch.table.UART_SetConfig]16
Total:3 18840
+

Module stm32c0xx_hal_uart_ex.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
UARTEx_SetNbDataToProcess72
HAL_UARTEx_SetTxFifoThreshold68
HAL_UARTEx_SetRxFifoThreshold68
HAL_UARTEx_DisableFifoMode54
HAL_UARTEx_WakeupCallback2
HAL_UARTEx_RxFifoFullCallback2
HAL_UARTEx_TxFifoEmptyCallback2
UARTEx_SetNbDataToProcess.numerator8
UARTEx_SetNbDataToProcess.denominator8
Total:26816
+

Module button.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
BUTTON_Exec188
BUTTON_GetMode12
BUTTON_SetModeOff12
BUTTON_SetModeAuto12
[.rodata..Lstr.3]28
[.rodata..Lstr]18
[.rodata..Lstr.4]17
longPressCounterButtonOn4
longPressCounterButtonOff4
buttonState1
Total:224639
+

Module buzzer.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
BUZZER_Exec100
BUZZER_Alarm_Start52
BUZZER_Alarm_Stop44
BUZZER_Beep28
onTimeCounter4
alarmMode4
offTime4
offTimeCounter4
onTime4
Total:22420
+

Module chip_temperature.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
CHIP_TEMPERATURE_Exec60
CHIP_TEMPERATURE_Calibration48
CHIP_TEMPERATURE_GetTemp12
calTemperatureSensor30Value4
temp4
Total:1208
+

Module eeprom.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
EEPROM_Write160
EEPROM_StoreConfig80
EEPROM_WriteDefaults48
EEPROM_ReadDeviceParameter36
EEPROM_ErasePage32
EEPROM_ReadFirstStart12
flash_device_parameter_default16
Total:36816
+

Module fan.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
FAN_SetSpeed44
lastSpeed4
Total:444
+

Module leds.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
LEDS_Exec240
LEDS_RT_BlinkCode_Start76
LEDS_GN_Blink_Start52
LEDS_GN_Off48
LEDS_RT_Off48
LEDS_GN_On44
onTimeCounterGN4
blinkModeGN4
offTimeGN4
offTimeCounterGN4
onTimeGN4
onTimeCounterRT4
blinkModeRT4
offTimeRT4
offTimeCounterRT4
blinkCounter4
pauseTime4
numberOfBlinks4
onTimeRT4
Total:50852
+

Module main.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
main992
SystemClock_Config108
JumpToBootloader96
Error_Handler4
[.rodata..Lstr.9]59
[.rodata..Lstr.10]46
[.rodata..Lstr.12]25
[.rodata..Lstr.11]20
[.rodata..Lstr]19
[.rodata..Lstr.8]18
[.rodata..Lstr.14]17
[.rodata..Lstr.13]16
modbusData564
adcData20
silentmode4
bootLoaderMark4
oldTimeMSTick4
msCounter4
Total:1 200220600
+

Module modbus.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
mbUartInit188
mbSlaveWriteMultipleRegisters176
HAL_UART_ErrorCallback168
mbSlaveReadHoldingRegisters160
mbSlaveWriteSingleRegister100
mbInit68
mbSlaveProcessRtuQuery68
mbCrc1664
mbSlaveCheckModbusRtuQuery60
mbSlaveProcessPdu50
mbCheckCrc1638
mbSend28
mbAppendCrc1622
HAL_UART_TxCpltCallback16
mbGetFrameComplete4
[.rodata..L.str.7]39
[.rodata..L.str.5]17
[.rodata..L.str.6]17
[.rodata..Lstr]17
[.rodata..L.str.2]16
[.rodata..L.str.3]16
[.rodata..L.str.4]16
[.rodata..L.str.1]14
Total:1 210152
+

Module mode_lvp.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODE_LVP_Exec776
[.rodata..Lstr]45
[.rodata..Lstr.16]43
[.rodata..Lstr.20]38
[.rodata..Lstr.18]35
[.rodata..Lstr.12]30
[.rodata..Lstr.14]28
[.rodata..Lstr.24]25
[.rodata..Lstr.15]21
[.rodata..Lstr.22]19
[.rodata..Lstr.23]18
[.rodata..Lstr.17]9
[.rodata..Lstr.19]8
LVP_SM_On.lvpTimeCounter4
LVP_SM_On.oldtime4
smState1
LVP_SM_On.lvpInput1
Total:77631910
+

Module mode_lvp_ovp.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODE_LVP_OVP_Exec788
[.rodata..Lstr]53
[.rodata..Lstr.16]43
[.rodata..Lstr.18]39
[.rodata..Lstr.12]38
[.rodata..Lstr.20]38
[.rodata..Lstr.24]29
[.rodata..Lstr.14]28
[.rodata..Lstr.15]25
[.rodata..Lstr.22]23
[.rodata..Lstr.23]22
[.rodata..Lstr.17]16
[.rodata..Lstr.19]16
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter4
LVP_OVP_SM_On.oldtime4
smState1
LVP_OVP_SM_On.lvpOROvpInput1
Total:78837010
+

Module mode_mainswitch.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MAINSWITCH_SM_On184
MAINSWITCH_SM_Off168
MAINSWITCH_SM_Error156
MAINSWITCH_SM_ManualOn52
MODE_MAINSWITCH_Exec48
[.rodata..Lstr.9]43
[.rodata..Lstr.12]32
[.rodata..Lstr.8]28
[.rodata..Lstr.10]26
[.rodata..Lstr.11]25
smState1
Total:6081541
+

Module mode_ovp.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODE_OVP_Exec760
[.rodata..Lstr]45
[.rodata..Lstr.16]43
[.rodata..Lstr.20]38
[.rodata..Lstr.18]35
[.rodata..Lstr.12]30
[.rodata..Lstr.14]28
[.rodata..Lstr.24]25
[.rodata..Lstr.15]21
[.rodata..Lstr.22]19
[.rodata..Lstr.23]18
[.rodata..Lstr.17]9
[.rodata..Lstr.19]8
OVP_SM_On.ovpTimeCounter4
OVP_SM_On.oldtime4
smState1
OVP_SM_On.ovpInput1
Total:76031910
+

Module mode_secondaryprotection.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODE_SECONDARYPROTECTION_Exec892
[.rodata..Lstr.13]60
[.rodata..Lstr.15]43
[.rodata..Lstr.22]41
[.rodata..Lstr.19]37
[.rodata..Lstr.20]35
[.rodata..Lstr.21]34
[.rodata..Lstr.11]29
[.rodata..Lstr.18]28
autoRetryMode4
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter4
SECONDARYPROTECTION_SM_On.oldtime4
SECONDARYPROTECTION_SM_Error.retry_counter4
SECONDARYPROTECTION_SM_Error.oldTimeMSTick4
smState1
Total:89230721
+

Module mode_secondaryprotection_plus.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODE_SECONDARYPROTECTION_PLUS_Exec688
[.rodata..Lstr.11]60
[.rodata..Lstr.13]43
[.rodata..Lstr.15]37
[.rodata..Lstr.8]35
[.rodata..Lstr.16]34
[.rodata..Lstr.9]29
[.rodata..Lstr.14]28
autoRetryMode4
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter4
SECONDARYPROTECTION_SM_On.oldtime4
SECONDARYPROTECTION_SM_Error.retry_counter4
SECONDARYPROTECTION_SM_Error.oldTimeMSTick4
smState1
Total:68826621
+

Module modeswitch.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
MODESWITCH_ReadMode88
MODESWITCH_GetMode12
[.rodata..L.str]9
mode1
Total:10091
+

Module relais.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
RELAIS_Exec108
RELAIS_SetPuls52
RELAIS_ResetPuls52
RELAIS_GetTemp12
RELAIS_GetState12
relais_temperature4
onTimeCounterSET4
onTimeCounterRESET4
relaisState4
Total:23616
+

Module sysdata.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SYS_DATA_Init24
sys_data224
Total:24224
+

Module voltage_meas.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
VOLTAGE_MEAS_Exec144
VOLTAGE_MEAS_GetLimitAlarm24
VOLTAGE_MEAS_ResetCounter12
VOLTAGE_MEAS_GetUin12
VOLTAGE_MEAS_GetUout12
[.rodata..L.str]35
dropLimitCounter4
voltageUin4
voltageUout4
voltageDrop4
Total:2043516
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32c031xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors180
WWDG_IRQHandler2
RTC_IRQHandler2
FLASH_IRQHandler2
RCC_IRQHandler2
EXTI0_1_IRQHandler2
EXTI2_3_IRQHandler2
EXTI4_15_IRQHandler2
DMAMUX1_IRQHandler2
ADC1_IRQHandler2
TIM1_BRK_UP_TRG_COM_IRQHandler2
TIM1_CC_IRQHandler2
TIM3_IRQHandler2
TIM14_IRQHandler2
TIM17_IRQHandler2
I2C1_IRQHandler2
SPI1_IRQHandler2
USART2_IRQHandler2
Total:214
+

Module STM32C0xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler8
Total:8
+

Module fileops.o (libc_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
fwrite52
puts44
fputc34
putchar16
Total:146
+

Module floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_dmul_aux394
__aeabi_ddiv196
__aeabi_fmul182
__aeabi_d2iz52
__aeabi_d2uiz46
__aeabi_f2uiz36
__aeabi_ui2f30
__aeabi_i2d28
__aeabi_ui2d28
Total:992
+

Module intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_uldivmod160
__aeabi_idiv64
__aeabi_uidiv56
__aeabi_lmul46
__aeabi_uidivmod16
__aeabi_idiv06
Total:348
+

Module prinops.o (libc_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_putc138
vfprintf_l120
printf40
__SEGGER_RTL_prin_flush26
vfprintf26
__SEGGER_RTL_stream_write16
__SEGGER_RTL_hex_uc16
__SEGGER_RTL_hex_lc16
Total:36632
+

Module __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp960
Total:960
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_X_file_stat52
__SEGGER_RTL_X_file_write10
__SEGGER_RTL_X_file_bufsize4
stdin4
stdout4
stderr4
__SEGGER_RTL_stdin_file4
__SEGGER_RTL_stdout_file4
__SEGGER_RTL_stderr_file4
Total:661212
+

Module SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SEGGER_RTT_WriteNoLock104
_WriteBlocking88
_DoInit84
_WriteNoCheck58
SEGGER_RTT_Write56
_GetAvailWriteSpace22
_DoInit._aInitStr17
[.rodata.libc..L.str]9
_acUpBuffer1 024
_SEGGER_RTT168
_acDownBuffer16
Total:412261 208
+

Module strops.o (strops_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
memcmp272
strlen108
Total:380
+

Module strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr20
memcpy14
Total:34
+

Module mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_ascii_mbtowc46
__SEGGER_RTL_ascii_isctype28
__SEGGER_RTL_ascii_iswctype28
__SEGGER_RTL_current_locale20
__SEGGER_RTL_ascii_wctomb16
__SEGGER_RTL_ascii_tolower14
__SEGGER_RTL_ascii_towlower14
__SEGGER_RTL_ascii_toupper12
__SEGGER_RTL_ascii_towupper12
__SEGGER_RTL_ascii_ctype_map128
__SEGGER_RTL_c_locale_data88
__SEGGER_RTL_c_locale_month_names87
__SEGGER_RTL_c_locale_day_names58
__SEGGER_RTL_c_locale_abbrev_month_names49
__SEGGER_RTL_codeset_ascii32
__SEGGER_RTL_c_locale_abbrev_day_names29
__SEGGER_RTL_c_locale_date_time_format15
__SEGGER_RTL_ascii_ctype_mask13
__SEGGER_RTL_c_locale12
__SEGGER_RTL_c_locale_date_format9
__SEGGER_RTL_c_locale_time_format9
__SEGGER_RTL_c_locale_am_pm_indicator7
[.rodata.libc..L.str]2
__SEGGER_RTL_data_utf8_period2
__SEGGER_RTL_data_empty_string1
__SEGGER_RTL_global_locale20
__SEGGER_RTL_locale_ptr4
Total:190541204
+

All modules

+ + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:27 7202 981412 995
+

UNPLACED SECTIONS AND BLOCKS

+

Unplaced sections

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SectionSizeAlignObject
.segger.init.__SEGGER_init_zero122SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a)
.segger.init.__SEGGER_init_copy142SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a)
.segger.init.data2C4[ Linker created ]
Total:82
+

LINK SUMMARY

+ +
+Link complete: 9 error.
+
+ Index: /trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1329 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49 + Copyright (c) 2017-2025 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 16 872 1 049 8 1 629 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 214 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 17 114 1 049 8 1 629 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_balanced.a 2 812 32 + mbops_timeops_v6m_t_le_eabi_balanced.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 478 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 74 + strops_v6m_t_le_eabi_balanced.a 414 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 3 968 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 196 2 048 + ============================================= ========== ========== ========== ========== + Total: 21 082 1 844 40 4 901 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 960 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 146 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 992 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 348 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 412 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 34 + strops.o (strops_v6m_t_le_eabi_balanced.a) 380 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (11 members from 5 archives) 3 968 599 32 1 224 + Objects (4 files) 17 114 1 049 8 1 629 + Linker created (shared data, fills, blocks): 196 2 048 + ============================================= ========== ========== ========== ========== + Total: 21 082 1 844 40 4 901 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 196 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 196 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 17 114 1 049 8 1 629 + Archives (5 files) 3 968 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 21 082 1 844 40 4 901 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000B3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000B4-080000C3 SysTick_Handler 16 4 Code RX PowerPro_lto.o + 080000C4-080000D3 DMA1_Channel1_IRQHandler 16 4 Code RX PowerPro_lto.o + 080000D4-080000EB DMA1_Channel2_3_IRQHandler + 24 4 Code RX PowerPro_lto.o + 080000EC-0800029F TIM16_IRQHandler 436 4 Code RX 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(strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 0x080049EF 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 0x080042B5 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 0x08004BB9 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 0x08004311 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 0x08004349 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uldivmod 0x08004359 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __startup_complete 0x08004137 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x0800412D 14 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x0800413B 2 4 Code Gb SEGGER_THUMB_Startup.o + fputc 0x08004D2B 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 0x08005145 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x08001AE1 7 676 4 Code Gb PowerPro_lto.o + mbCrc16 0x080039E5 64 4 Code Lc PowerPro_lto.o + memcmp 0x080051E5 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + memcpy 0x08004C75 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + memset 0x080049F5 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + printf 0x08004471 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + putchar 0x08004141 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + puts 0x08004151 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x0800513D 2 Code Gb STM32C0xx_Startup.o + strlen 0x08004981 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + vfprintf 0x08004F7B 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x080043F9 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 SysTick_Handler 16 4 Code Gb PowerPro_lto.o + 0x080000C5 DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080000D5 DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + 0x080000ED TIM16_IRQHandler 436 4 Code Gb PowerPro_lto.o + 0x080002A1 USART1_IRQHandler 1 124 4 Code Gb PowerPro_lto.o + 0x08000705 HAL_TIM_IC_CaptureCallback + 56 4 Code Lc PowerPro_lto.o + 0x0800073D SystemInit 16 4 Code Gb PowerPro_lto.o + 0x0800074D SystemCoreClockUpdate 84 4 Code Gb PowerPro_lto.o + 0x080007A1 HAL_InitTick 104 4 Code Lc PowerPro_lto.o + 0x08000809 HAL_ADC_ConfigChannel 636 4 Code Lc PowerPro_lto.o + 0x08000A85 HAL_DMA_Init 244 4 Code Lc PowerPro_lto.o + 0x08000B79 HAL_DMA_Start_IT 204 4 Code Lc PowerPro_lto.o + 0x08000C45 HAL_DMA_IRQHandler 232 4 Code Lc PowerPro_lto.o + 0x08000D2D FLASH_WaitForLastOperation + 80 4 Code Lc PowerPro_lto.o + 0x08000D7D HAL_FLASH_Unlock 36 4 Code Lc PowerPro_lto.o + 0x08000DA1 HAL_GPIO_Init 400 4 Code Lc PowerPro_lto.o + 0x08000F31 HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + 0x08000F85 HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + 0x08000FC5 HAL_RCCEx_PeriphCLKConfig 324 4 Code Lc PowerPro_lto.o + 0x08001109 HAL_TIM_Base_Init 220 4 Code Lc PowerPro_lto.o + 0x080011E5 TIM_Base_SetConfig 156 4 Code Lc PowerPro_lto.o + 0x08001281 HAL_UART_Init 1 080 4 Code Lc PowerPro_lto.o + 0x080016B9 UART_WaitOnFlagUntilTimeout + 116 4 Code Lc PowerPro_lto.o + 0x0800172D UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + 0x0800178D UART_DMATransmitCplt 80 4 Code Lc PowerPro_lto.o + 0x080017DD HAL_UART_Receive_DMA 260 4 Code Lc PowerPro_lto.o + 0x080018E1 UARTEx_SetNbDataToProcess 80 4 Code Lc PowerPro_lto.o + 0x08001931 EEPROM_Write 272 4 Code Lc PowerPro_lto.o + 0x08001A41 EEPROM_WriteDefaults 48 4 Code Lc PowerPro_lto.o + 0x08001A71 EEPROM_ReadDeviceParameter + 36 4 Code Lc PowerPro_lto.o + 0x08001A95 EEPROM_StoreConfig 76 4 Code Lc PowerPro_lto.o + 0x08001AE1 main 7 676 4 Code Gb PowerPro_lto.o + 0x080038DD JumpToBootloader 96 4 Code Lc PowerPro_lto.o + 0x0800393D HAL_UART_ErrorCallback 168 4 Code Lc PowerPro_lto.o + 0x080039E5 mbCrc16 64 4 Code Lc PowerPro_lto.o + 0x08003A25 MODE_SECONDARYPROTECTION_Exec + 1 688 4 Code Lc PowerPro_lto.o + 0x0800412D _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004137 __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004137 __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x0800413B exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004141 putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004151 puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800417D __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004241 __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004275 __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004299 __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080042B5 __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080042D1 __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004311 __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004349 __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004359 __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080043F9 vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004471 printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004499 __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004499 __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004859 __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x0800488D _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080048E1 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004949 SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004981 strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049ED __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049ED __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049ED __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049EF __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049EF __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049EF __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080049F5 memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004A01 __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004A15 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004A31 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004AD1 __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004B87 NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004B89 __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004BB7 HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004BB9 __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004BD7 SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004BD9 __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004C07 PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004C09 __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004C0F ADC_DMAConvCplt 102 2 Code Lc PowerPro_lto.o + 0x08004C75 memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004C75 __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004C75 __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004C75 __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004C83 ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + 0x08004C85 UART_DMATxHalfCplt 2 2 Code Lc PowerPro_lto.o + 0x08004C87 UART_DMAError 130 2 Code Lc PowerPro_lto.o + 0x08004D09 WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D0B RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D0D FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D0F RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D11 EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D13 EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D15 EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D17 DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D19 ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D1B TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x08004D1D TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D1F TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D21 TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D23 TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D25 I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D27 SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D29 USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004D2B fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D4D __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D85 __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004ED7 __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004F61 __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004F7B vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004F95 __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004F9F _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004FB5 _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004FEF __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x0800501D __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x0800502B __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005039 ADC_DMAError 20 2 Code Lc PowerPro_lto.o + 0x0800504D UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + 0x080050F1 UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + 0x08005115 UART_DMAAbortOnError 16 2 Code Lc PowerPro_lto.o + 0x0800513D reset_handler 2 Code Gb STM32C0xx_Startup.o + 0x0800513D Reset_Handler 2 Code Gb STM32C0xx_Startup.o + 0x08005145 fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005179 __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005189 __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x0800518D _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080051E5 memcmp 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x080052F5 __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005305 __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005311 __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005885 __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0x0800596D __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0x0800597F __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + +Function symbols by descending size: + + Symbol name Size Align Type Bd Object File + ------------------------- ---------- ----- ---- -- ----------- + main 7 676 4 Code Gb PowerPro_lto.o + MODE_SECONDARYPROTECTION_Exec + 1 688 4 Code Lc PowerPro_lto.o + USART1_IRQHandler 1 124 4 Code Gb PowerPro_lto.o + HAL_UART_Init 1 080 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + HAL_ADC_ConfigChannel 636 4 Code Lc PowerPro_lto.o + TIM16_IRQHandler 436 4 Code Gb PowerPro_lto.o + HAL_GPIO_Init 400 4 Code Lc PowerPro_lto.o + __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_RCCEx_PeriphCLKConfig 324 4 Code Lc PowerPro_lto.o + EEPROM_Write 272 4 Code Lc PowerPro_lto.o + memcmp 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + HAL_UART_Receive_DMA 260 4 Code Lc PowerPro_lto.o + HAL_DMA_Init 244 4 Code Lc PowerPro_lto.o + HAL_DMA_IRQHandler 232 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 220 4 Code Lc PowerPro_lto.o + HAL_DMA_Start_IT 204 4 Code Lc PowerPro_lto.o + __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_UART_ErrorCallback 168 4 Code Lc PowerPro_lto.o + UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + TIM_Base_SetConfig 156 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_DMAError 130 2 Code Lc PowerPro_lto.o + vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_WaitOnFlagUntilTimeout + 116 4 Code Lc PowerPro_lto.o + strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + HAL_InitTick 104 4 Code Lc PowerPro_lto.o + SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + ADC_DMAConvCplt 102 2 Code Lc PowerPro_lto.o + JumpToBootloader 96 4 Code Lc PowerPro_lto.o + UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + SystemCoreClockUpdate 84 4 Code Gb PowerPro_lto.o + _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + FLASH_WaitForLastOperation + 80 4 Code Lc PowerPro_lto.o + UARTEx_SetNbDataToProcess 80 4 Code Lc PowerPro_lto.o + UART_DMATransmitCplt 80 4 Code Lc PowerPro_lto.o + EEPROM_StoreConfig 76 4 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbCrc16 64 4 Code Lc PowerPro_lto.o + _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_TIM_IC_CaptureCallback + 56 4 Code Lc PowerPro_lto.o + SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + EEPROM_WriteDefaults 48 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + EEPROM_ReadDeviceParameter + 36 4 Code Lc PowerPro_lto.o + HAL_FLASH_Unlock 36 4 Code Lc PowerPro_lto.o + UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ADC_DMAError 20 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + SysTick_Handler 16 4 Code Gb PowerPro_lto.o + SystemInit 16 4 Code Gb PowerPro_lto.o + UART_DMAAbortOnError 16 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o 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Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_link.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_link.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_link.ind (revision 41) @@ -0,0 +1,10 @@ +Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o +Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o +Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_balanced.a" Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/adc.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_24V/Obj/PowerPro/button.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/buzzer.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_24V/Obj/PowerPro/chip_temperature.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/dma.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/eeprom.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/eeprom.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/eeprom.d (revision 41) @@ -0,0 +1,49 @@ +Output/Debug_24V/Obj/PowerPro/eeprom.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\eeprom.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\string.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_24V/Obj/PowerPro/fan.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/gpio.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/iwdg.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/leds.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,70 @@ +Output/Debug_24V/Obj/PowerPro/main.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modbus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modbus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modbus.d (revision 41) @@ -0,0 +1,48 @@ +Output/Debug_24V/Obj/PowerPro/modbus.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modbus.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_24V/Obj/PowerPro/mode_lvp.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_24V/Obj/PowerPro/mode_mainswitch.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_24V/Obj/PowerPro/mode_ovp.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,53 @@ +Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,53 @@ +Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_24V/Obj/PowerPro/modeswitch.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_24V/Obj/PowerPro/relais.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/sysdata.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/sysdata.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/sysdata.d (revision 41) @@ -0,0 +1,46 @@ +Output/Debug_24V/Obj/PowerPro/sysdata.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\sysdata.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_24V/Obj/PowerPro/tim.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_24V/Obj/PowerPro/usart.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,49 @@ +Output/Debug_24V/Obj/PowerPro/voltage_meas.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Exe/PowerPro.map (revision 41) @@ -0,0 +1,2009 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44.2 compiled Apr 14 2025 15:08:43 + Copyright (c) 2017-2024 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 24 034 2 088 9 593 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 218 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 24 280 2 088 9 593 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_balanced.a 2 278 32 + mbops_timeops_v6m_t_le_eabi_balanced.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 484 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 74 + strops_v6m_t_le_eabi_balanced.a 36 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 3 062 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 96 2 048 + ============================================= ========== ========== ========== ========== + Total: 27 342 2 783 41 3 865 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 904 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 52 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 604 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 352 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 418 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 36 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (10 members from 5 archives) 3 062 599 32 1 224 + Objects (4 files) 24 280 2 088 9 593 + Linker created (shared data, fills, blocks): 96 2 048 + ============================================= ========== ========== ========== ========== + Total: 27 342 2 783 41 3 865 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 96 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 96 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 24 280 2 088 9 593 + Archives (5 files) 3 062 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 27 342 2 783 41 3 865 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000b3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000b4-08000197 MX_ADC1_Init 228 4 Code RX PowerPro_lto.o + 08000198-0800026f HAL_ADC_MspInit 216 4 Code RX PowerPro_lto.o + 08000270-0800029f MX_DMA_Init 48 4 Code RX PowerPro_lto.o + 080002a0-0800039b MX_GPIO_Init 252 4 Code RX PowerPro_lto.o + 0800039c-080003cf HAL_MspInit 52 4 Code RX PowerPro_lto.o + 080003d0-080003df DMA1_Channel1_IRQHandler 16 4 Code RX PowerPro_lto.o + 080003e0-080003ef TIM16_IRQHandler 16 4 Code RX PowerPro_lto.o + 080003f0-08000447 HAL_TIM_IC_CaptureCallback + 88 4 Code RX PowerPro_lto.o + 08000448-0800047b HAL_TIM_PeriodElapsedCallback + 52 4 Code RX PowerPro_lto.o + 0800047c-0800048b SystemInit 16 4 Code RX PowerPro_lto.o + 0800048c-080005b7 SystemCoreClockUpdate 300 4 Code RX PowerPro_lto.o + 080005b8-08000627 MX_TIM16_Init 112 4 Code RX PowerPro_lto.o + 08000628-080006d7 MX_TIM17_Init 176 4 Code RX PowerPro_lto.o + 080006d8-0800073f HAL_TIM_MspPostInit 104 4 Code RX PowerPro_lto.o + 08000740-080007e7 HAL_TIM_Base_MspInit 168 4 Code RX PowerPro_lto.o + 080007e8-08000813 MX_IWDG_Init 44 4 Code RX PowerPro_lto.o + 08000814-0800088b HAL_InitTick 120 4 Code RX PowerPro_lto.o + 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TIM_OC5_SetConfig 168 4 Code RX PowerPro_lto.o + 08003014-080030bb TIM_OC6_SetConfig 168 4 Code RX PowerPro_lto.o + 080030bc-08003153 TIM_TI1_SetConfig 152 4 Code RX PowerPro_lto.o + 08003154-0800333b HAL_TIM_PWM_ConfigChannel 488 4 Code RX PowerPro_lto.o + 0800333c-0800344f HAL_TIMEx_ConfigBreakDeadTime + 276 4 Code RX PowerPro_lto.o + 08003450-0800351b BUTTON_Exec 204 4 Code RX PowerPro_lto.o + 0800351c-08003527 BUTTON_GetMode 12 4 Code RX PowerPro_lto.o + 08003528-08003533 BUTTON_SetModeOff 12 4 Code RX PowerPro_lto.o + 08003534-080035a7 BUZZER_Exec 116 4 Code RX PowerPro_lto.o + 080035a8-080035cb BUZZER_Beep 36 4 Code RX PowerPro_lto.o + 080035cc-0800360b BUZZER_Alarm_Start 64 4 Code RX PowerPro_lto.o + 0800360c-0800363f BUZZER_Alarm_Stop 52 4 Code RX PowerPro_lto.o + 08003640-0800367f CHIP_TEMPERATURE_Calibration + 64 4 Code RX PowerPro_lto.o + 08003680-080036d3 CHIP_TEMPERATURE_Exec 84 4 Code RX PowerPro_lto.o + 080036d4-080036df CHIP_TEMPERATURE_GetTemp 12 4 Code RX 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RX PowerPro_lto.o + 08004b90-08004d4b SECONDARYPROTECTION_SM_On 444 4 Code RX PowerPro_lto.o + 08004d4c-08004de7 SECONDARYPROTECTION_SM_ManualOn + 156 4 Code RX PowerPro_lto.o + 08004de8-08004e97 SECONDARYPROTECTION_SM_Error + 176 4 Code RX PowerPro_lto.o + 08004e98-08004ecf MODE_SECONDARYPROTECTION_PLUS_Exec + 56 4 Code RX PowerPro_lto.o + 08004ed0-08004f8b SECONDARYPROTECTION_SM_Off.158 + 188 4 Code RX PowerPro_lto.o + 08004f8c-0800516b SECONDARYPROTECTION_SM_On.159 + 480 4 Code RX PowerPro_lto.o + 0800516c-08005223 SECONDARYPROTECTION_SM_Error.160 + 184 4 Code RX PowerPro_lto.o + 08005224-0800529b MODESWITCH_ReadMode 120 4 Code RX PowerPro_lto.o + 0800529c-080052a7 MODESWITCH_GetMode 12 4 Code RX PowerPro_lto.o + 080052a8-080052f7 RELAIS_Exec 80 4 Code RX PowerPro_lto.o + 080052f8-0800532f RELAIS_SetPuls 56 4 Code RX PowerPro_lto.o + 08005330-08005367 RELAIS_ResetPuls 56 4 Code RX PowerPro_lto.o + 08005368-08005373 RELAIS_GetState 12 4 Code RX PowerPro_lto.o + 08005374-0800543f VOLTAGE_MEAS_Exec 204 4 Code RX PowerPro_lto.o + 08005440-08005463 VOLTAGE_MEAS_GetLimitAlarm + 36 4 Code RX PowerPro_lto.o + 08005464-0800546f VOLTAGE_MEAS_ResetCounter 12 4 Code RX PowerPro_lto.o + 08005470-0800547b VOLTAGE_MEAS_GetUin 12 4 Code RX PowerPro_lto.o + 0800547c-08005487 VOLTAGE_MEAS_GetUout 12 4 Code RX PowerPro_lto.o + 08005488-080054c7 AHBPrescTable 64 4 Cnst RO PowerPro_lto.o + 080054c8-080054e7 APBPrescTable 32 4 Cnst RO PowerPro_lto.o + 080054e8-080054fb _start 20 4 Code RX SEGGER_THUMB_Startup.o + 080054fc-080055b3 __aeabi_fmul 184 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080055b4-08005677 __aeabi_ddiv 196 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08005678-080056ab __aeabi_d2iz 52 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080056ac-080056cf __aeabi_f2uiz 36 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080056d0-080056ff __aeabi_d2uiz 48 4 Code RX floatasmops_arm.o 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196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_f2uiz 0x080056AD 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fmul 0x080054FD 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 0x08005701 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv 0x08005789 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv0 0x080058B1 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 0x08005759 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 0x08005E19 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr4 0x08005E19 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr8 0x08005E19 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy 0x08005E09 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy4 0x08005E09 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy8 0x08005E09 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset 0x08005E1B 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 0x08005E1B 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 0x08005E1B 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 0x0800573D 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 0x0800571D 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 0x080057C9 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 0x08005801 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uldivmod 0x08005811 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __startup_complete 0x080054F3 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x080054E9 14 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x080054F7 2 4 Code Gb SEGGER_THUMB_Startup.o + fwrite 0x08006AF9 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x08003979 568 4 Code Gb PowerPro_lto.o + memcpy 0x08005E09 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + memset 0x08005E21 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + printf 0x08005931 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x08006AF1 2 Code Gb STM32C0xx_Startup.o + vfprintf 0x080065C1 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x080058B9 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 MX_ADC1_Init 228 4 Code Lc PowerPro_lto.o + 0x08000199 HAL_ADC_MspInit 216 4 Code Lc PowerPro_lto.o + 0x08000271 MX_DMA_Init 48 4 Code Lc PowerPro_lto.o + 0x080002A1 MX_GPIO_Init 252 4 Code Lc PowerPro_lto.o + 0x0800039D HAL_MspInit 52 4 Code Lc PowerPro_lto.o + 0x080003D1 DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080003E1 TIM16_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080003F1 HAL_TIM_IC_CaptureCallback + 88 4 Code Lc PowerPro_lto.o + 0x08000449 HAL_TIM_PeriodElapsedCallback + 52 4 Code Lc PowerPro_lto.o + 0x0800047D SystemInit 16 4 Code Gb PowerPro_lto.o + 0x0800048D SystemCoreClockUpdate 300 4 Code Gb PowerPro_lto.o + 0x080005B9 MX_TIM16_Init 112 4 Code Lc PowerPro_lto.o + 0x08000629 MX_TIM17_Init 176 4 Code Lc PowerPro_lto.o + 0x080006D9 HAL_TIM_MspPostInit 104 4 Code Lc PowerPro_lto.o + 0x08000741 HAL_TIM_Base_MspInit 168 4 Code Lc PowerPro_lto.o + 0x080007E9 MX_IWDG_Init 44 4 Code Lc PowerPro_lto.o + 0x08000815 HAL_InitTick 120 4 Code Lc PowerPro_lto.o + 0x0800088D HAL_IncTick 24 4 Code Lc PowerPro_lto.o + 0x080008A5 HAL_GetTick 12 4 Code Lc PowerPro_lto.o + 0x080008B1 HAL_Delay 60 4 Code Lc PowerPro_lto.o + 0x080008ED HAL_ADC_Init 772 4 Code Lc PowerPro_lto.o + 0x08000BF1 LL_ADC_EnableInternalRegulator + 32 4 Code Lc PowerPro_lto.o + 0x08000C11 LL_ADC_Disable 28 4 Code Lc PowerPro_lto.o + 0x08000C2D ADC_Enable 224 4 Code Lc PowerPro_lto.o + 0x08000D0D LL_ADC_REG_StartConversion + 28 4 Code Lc PowerPro_lto.o + 0x08000D29 LL_ADC_Enable 28 4 Code Lc PowerPro_lto.o + 0x08000D45 HAL_ADC_Start_DMA 252 4 Code Lc PowerPro_lto.o + 0x08000E41 HAL_ADC_ConfigChannel 1 000 4 Code Lc PowerPro_lto.o + 0x08001229 LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc PowerPro_lto.o + 0x08001245 LL_ADC_SetChannelSamplingTime + 40 4 Code Lc PowerPro_lto.o + 0x0800126D LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc PowerPro_lto.o + 0x0800128D HAL_ADCEx_Calibration_Start + 456 4 Code Lc PowerPro_lto.o + 0x08001455 LL_ADC_Enable.10 28 4 Code Lc PowerPro_lto.o + 0x08001471 LL_ADC_Disable.11 28 4 Code Lc PowerPro_lto.o + 0x0800148D __NVIC_SetPriority 128 4 Code Lc PowerPro_lto.o + 0x0800150D __NVIC_EnableIRQ 40 4 Code Lc PowerPro_lto.o + 0x08001535 SysTick_Config 76 4 Code Lc PowerPro_lto.o + 0x08001581 HAL_DMA_Init 240 4 Code Lc PowerPro_lto.o + 0x08001671 DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc PowerPro_lto.o + 0x080016B5 DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc PowerPro_lto.o + 0x080016ED DMA_SetConfig 112 4 Code Lc PowerPro_lto.o + 0x0800175D HAL_DMA_IRQHandler 320 4 Code Lc PowerPro_lto.o + 0x0800189D HAL_GPIO_Init 704 4 Code Lc PowerPro_lto.o + 0x08001B5D HAL_IWDG_Init 164 4 Code Lc PowerPro_lto.o + 0x08001C01 HAL_IWDG_Refresh 24 4 Code Lc PowerPro_lto.o + 0x08001C19 HAL_RCC_OscConfig 924 4 Code Lc PowerPro_lto.o + 0x08001FB5 HAL_RCC_ClockConfig 512 4 Code Lc PowerPro_lto.o + 0x080021B5 HAL_RCC_GetSysClockFreq 132 4 Code Lc PowerPro_lto.o + 0x08002239 HAL_RCC_GetHCLKFreq 52 4 Code Lc PowerPro_lto.o + 0x0800226D HAL_RCC_GetPCLK1Freq 40 4 Code Lc PowerPro_lto.o + 0x08002295 HAL_RCCEx_PeriphCLKConfig 396 4 Code Lc PowerPro_lto.o + 0x08002421 TIM_Base_SetConfig 216 4 Code Lc PowerPro_lto.o + 0x080024F9 HAL_TIM_Base_Start_IT 144 4 Code Lc PowerPro_lto.o + 0x08002589 HAL_TIM_PWM_Start 424 4 Code Lc PowerPro_lto.o + 0x08002731 HAL_TIM_IC_Start_IT 652 4 Code Lc PowerPro_lto.o + 0x080029BD HAL_TIM_IRQHandler 520 4 Code Lc PowerPro_lto.o + 0x08002BC5 TIM_OC1_SetConfig 236 4 Code Lc PowerPro_lto.o + 0x08002CB1 TIM_OC2_SetConfig 260 4 Code Lc PowerPro_lto.o + 0x08002DB5 TIM_OC3_SetConfig 260 4 Code Lc PowerPro_lto.o + 0x08002EB9 TIM_OC4_SetConfig 180 4 Code Lc PowerPro_lto.o + 0x08002F6D TIM_OC5_SetConfig 168 4 Code Lc PowerPro_lto.o + 0x08003015 TIM_OC6_SetConfig 168 4 Code Lc PowerPro_lto.o + 0x080030BD TIM_TI1_SetConfig 152 4 Code Lc PowerPro_lto.o + 0x08003155 HAL_TIM_PWM_ConfigChannel 488 4 Code Lc PowerPro_lto.o + 0x0800333D HAL_TIMEx_ConfigBreakDeadTime + 276 4 Code Lc PowerPro_lto.o + 0x08003451 BUTTON_Exec 204 4 Code Lc PowerPro_lto.o + 0x0800351D BUTTON_GetMode 12 4 Code Lc PowerPro_lto.o + 0x08003529 BUTTON_SetModeOff 12 4 Code Lc PowerPro_lto.o + 0x08003535 BUZZER_Exec 116 4 Code Lc PowerPro_lto.o + 0x080035A9 BUZZER_Beep 36 4 Code Lc PowerPro_lto.o + 0x080035CD BUZZER_Alarm_Start 64 4 Code Lc PowerPro_lto.o + 0x0800360D BUZZER_Alarm_Stop 52 4 Code Lc PowerPro_lto.o + 0x08003641 CHIP_TEMPERATURE_Calibration + 64 4 Code Lc PowerPro_lto.o + 0x08003681 CHIP_TEMPERATURE_Exec 84 4 Code Lc PowerPro_lto.o + 0x080036D5 CHIP_TEMPERATURE_GetTemp 12 4 Code Lc PowerPro_lto.o + 0x080036E1 FAN_SetSpeed 72 4 Code Lc PowerPro_lto.o + 0x08003729 LEDS_Exec 280 4 Code Lc PowerPro_lto.o + 0x08003841 LEDS_GN_On 44 4 Code Lc PowerPro_lto.o + 0x0800386D LEDS_GN_Blink_Start 64 4 Code Lc PowerPro_lto.o + 0x080038AD LEDS_GN_Off 52 4 Code Lc PowerPro_lto.o + 0x080038E1 LEDS_RT_BlinkCode_Start 100 4 Code Lc PowerPro_lto.o + 0x08003945 LEDS_RT_Off 52 4 Code Lc PowerPro_lto.o + 0x08003979 main 568 4 Code Gb PowerPro_lto.o + 0x08003BB1 SystemClock_Config 112 4 Code Lc PowerPro_lto.o + 0x08003C21 MODE_LVP_Exec 72 4 Code Lc PowerPro_lto.o + 0x08003C69 LVP_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x08003D31 LVP_SM_On 484 4 Code Lc PowerPro_lto.o + 0x08003F15 LVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x08003F45 LVP_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x08003FF5 MODE_LVP_OVP_Exec 72 4 Code Lc PowerPro_lto.o + 0x0800403D LVP_OVP_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x08004105 LVP_OVP_SM_On 500 4 Code Lc PowerPro_lto.o + 0x080042F9 LVP_OVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x08004329 LVP_OVP_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x080043D9 MAINSWITCH_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x080044A1 MAINSWITCH_SM_On 204 4 Code Lc PowerPro_lto.o + 0x0800456D MAINSWITCH_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x0800459D MAINSWITCH_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x0800464D MODE_MAINSWITCH_Exec 72 4 Code Lc PowerPro_lto.o + 0x08004695 MODE_OVP_Exec 72 4 Code Lc PowerPro_lto.o + 0x080046DD OVP_SM_Off 200 4 Code Lc PowerPro_lto.o + 0x080047A5 OVP_SM_On 468 4 Code Lc PowerPro_lto.o + 0x08004979 OVP_SM_ManualOn 48 4 Code Lc PowerPro_lto.o + 0x080049A9 OVP_SM_Error 176 4 Code Lc PowerPro_lto.o + 0x08004A59 MODE_SECONDARYPROTECTION_Exec + 72 4 Code Lc PowerPro_lto.o + 0x08004AA1 SECONDARYPROTECTION_SM_Off + 240 4 Code Lc PowerPro_lto.o + 0x08004B91 SECONDARYPROTECTION_SM_On 444 4 Code Lc PowerPro_lto.o + 0x08004D4D SECONDARYPROTECTION_SM_ManualOn + 156 4 Code Lc PowerPro_lto.o + 0x08004DE9 SECONDARYPROTECTION_SM_Error + 176 4 Code Lc PowerPro_lto.o + 0x08004E99 MODE_SECONDARYPROTECTION_PLUS_Exec + 56 4 Code Lc PowerPro_lto.o + 0x08004ED1 SECONDARYPROTECTION_SM_Off.158 + 188 4 Code Lc PowerPro_lto.o + 0x08004F8D SECONDARYPROTECTION_SM_On.159 + 480 4 Code Lc PowerPro_lto.o + 0x0800516D SECONDARYPROTECTION_SM_Error.160 + 184 4 Code Lc PowerPro_lto.o + 0x08005225 MODESWITCH_ReadMode 120 4 Code Lc PowerPro_lto.o + 0x0800529D MODESWITCH_GetMode 12 4 Code Lc PowerPro_lto.o + 0x080052A9 RELAIS_Exec 80 4 Code Lc PowerPro_lto.o + 0x080052F9 RELAIS_SetPuls 56 4 Code Lc PowerPro_lto.o + 0x08005331 RELAIS_ResetPuls 56 4 Code Lc PowerPro_lto.o + 0x08005369 RELAIS_GetState 12 4 Code Lc PowerPro_lto.o + 0x08005375 VOLTAGE_MEAS_Exec 204 4 Code Lc PowerPro_lto.o + 0x08005441 VOLTAGE_MEAS_GetLimitAlarm + 36 4 Code Lc PowerPro_lto.o + 0x08005465 VOLTAGE_MEAS_ResetCounter 12 4 Code Lc PowerPro_lto.o + 0x08005471 VOLTAGE_MEAS_GetUin 12 4 Code Lc PowerPro_lto.o + 0x0800547D VOLTAGE_MEAS_GetUout 12 4 Code Lc PowerPro_lto.o + 0x080054E9 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054F3 __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054F3 __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054F7 exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x080054FD __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080055B5 __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005679 __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080056AD __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080056D1 __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005701 __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800571D __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800573D __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005759 __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005789 __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080057C9 __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005801 __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005811 __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080058B1 __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080058B9 vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005931 printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005959 __SEGGER_RTL_vfprintf_int_nwp + 904 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005959 __SEGGER_RTL_vfprintf 904 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005CE1 __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005D15 _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005D69 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005DD1 SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005E09 memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E09 __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E09 __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E09 __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E19 __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E19 __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E19 __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E1B __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E1B __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E1B __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E21 memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005E2D __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005E41 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005E5D __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005EFD HAL_TIM_ReadCapturedValue 126 4 Code Lc PowerPro_lto.o + 0x08005F7B NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005F7D HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005F7F SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005F81 PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005F83 LL_ADC_REG_IsConversionOngoing + 18 2 Code Lc PowerPro_lto.o + 0x08005F95 LL_ADC_SetSamplingTimeCommonChannels + 38 2 Code Lc PowerPro_lto.o + 0x08005FBB LL_ADC_IsDisableOngoing 18 2 Code Lc PowerPro_lto.o + 0x08005FCD LL_ADC_GetCommonPathInternalCh + 18 2 Code Lc PowerPro_lto.o + 0x08005FDF LL_ADC_REG_IsTriggerSourceSWStart + 22 2 Code Lc PowerPro_lto.o + 0x08005FF5 ADC_DMAHalfConvCplt 22 2 Code Lc PowerPro_lto.o + 0x0800600B ADC_DMAError 42 2 Code Lc PowerPro_lto.o + 0x08006035 LL_ADC_REG_SetSequencerRanks + 46 2 Code Lc PowerPro_lto.o + 0x08006063 LL_ADC_StartCalibration 26 2 Code Lc PowerPro_lto.o + 0x0800607D LL_ADC_IsCalibrationOnGoing + 14 2 Code Lc PowerPro_lto.o + 0x0800608B LL_ADC_GetCalibrationFactor + 18 2 Code Lc PowerPro_lto.o + 0x0800609D LL_ADC_GetClock 18 2 Code Lc PowerPro_lto.o + 0x080060AF LL_ADC_GetCommonClock 18 2 Code Lc PowerPro_lto.o + 0x080060C1 HAL_NVIC_EnableIRQ 22 2 Code Lc PowerPro_lto.o + 0x080060D7 HAL_GPIO_ReadPin 46 2 Code Lc PowerPro_lto.o + 0x08006105 HAL_TIM_Base_Init 154 2 Code Lc PowerPro_lto.o + 0x0800619F TIM_CCxChannelCmd 50 2 Code Lc PowerPro_lto.o + 0x080061D1 HAL_TIM_PWM_Init 154 2 Code Lc PowerPro_lto.o + 0x0800626B HAL_TIM_IC_Init 154 2 Code Lc PowerPro_lto.o + 0x08006305 HAL_TIM_IC_ConfigChannel 278 2 Code Lc PowerPro_lto.o + 0x0800641B TIM_TI2_SetConfig 110 2 Code Lc PowerPro_lto.o + 0x08006489 TIM_TI3_SetConfig 110 2 Code Lc PowerPro_lto.o + 0x080064F7 WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080064F9 RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080064FB FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080064FD RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080064FF EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006501 EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006503 EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006505 DMA1_Channel2_3_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x08006507 DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006509 ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800650B TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x0800650D TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800650F TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006511 TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006513 TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006515 I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006517 SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08006519 USART1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800651B USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800651D __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x080065A7 __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o 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SECONDARYPROTECTION_SM_ManualOn + 156 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 154 2 Code Lc PowerPro_lto.o + HAL_TIM_IC_Init 154 2 Code Lc PowerPro_lto.o + HAL_TIM_PWM_Init 154 2 Code Lc PowerPro_lto.o + TIM_TI1_SetConfig 152 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Start_IT 144 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + HAL_RCC_GetSysClockFreq 132 4 Code Lc PowerPro_lto.o + __NVIC_SetPriority 128 4 Code Lc PowerPro_lto.o + HAL_TIM_ReadCapturedValue 126 4 Code Lc PowerPro_lto.o + HAL_InitTick 120 4 Code Lc PowerPro_lto.o + MODESWITCH_ReadMode 120 4 Code Lc PowerPro_lto.o + vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + BUZZER_Exec 116 4 Code Lc PowerPro_lto.o + TIM_TI4_SetConfig 116 2 Code Lc PowerPro_lto.o + DMA_SetConfig 112 4 Code Lc PowerPro_lto.o + MX_TIM16_Init 112 4 Code Lc PowerPro_lto.o + SystemClock_Config 112 4 Code Lc PowerPro_lto.o + TIM_TI2_SetConfig 110 2 Code Lc PowerPro_lto.o + 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HAL_GPIO_WritePin 40 2 Code Lc PowerPro_lto.o + HAL_Init 40 2 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 40 4 Code Lc PowerPro_lto.o + LL_ADC_SetChannelSamplingTime + 40 4 Code Lc PowerPro_lto.o + __NVIC_EnableIRQ 40 4 Code Lc PowerPro_lto.o + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_SetSamplingTimeCommonChannels + 38 2 Code Lc PowerPro_lto.o + BUZZER_Beep 36 4 Code Lc PowerPro_lto.o + VOLTAGE_MEAS_GetLimitAlarm + 36 4 Code Lc PowerPro_lto.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_EnableInternalRegulator + 32 4 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc PowerPro_lto.o + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_NVIC_SetPriority 28 2 Code Lc PowerPro_lto.o + LL_ADC_Disable 28 4 Code Lc PowerPro_lto.o + LL_ADC_Disable.11 28 4 Code Lc PowerPro_lto.o + LL_ADC_Enable 28 4 Code Lc PowerPro_lto.o + LL_ADC_Enable.10 28 4 Code Lc PowerPro_lto.o + LL_ADC_GetSamplingTimeCommonChannels + 28 2 Code Lc PowerPro_lto.o + LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc PowerPro_lto.o + LL_ADC_REG_StartConversion + 28 4 Code Lc PowerPro_lto.o + LL_ADC_SetCalibrationFactor + 28 2 Code Lc PowerPro_lto.o + LL_ADC_SetCommonPathInternalCh + 28 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_StartCalibration 26 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + HAL_IWDG_Refresh 24 4 Code Lc PowerPro_lto.o + HAL_IncTick 24 4 Code Lc PowerPro_lto.o + ADC_DMAHalfConvCplt 22 2 Code Lc PowerPro_lto.o + HAL_NVIC_EnableIRQ 22 2 Code Lc PowerPro_lto.o + LL_ADC_REG_IsTriggerSourceSWStart + 22 2 Code Lc PowerPro_lto.o + _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_IsInternalRegulatorEnabled + 20 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + LL_ADC_GetCalibrationFactor + 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetClock 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetCommonClock 18 2 Code Lc PowerPro_lto.o + LL_ADC_GetCommonPathInternalCh + 18 2 Code Lc PowerPro_lto.o + LL_ADC_IsDisableOngoing 18 2 Code Lc PowerPro_lto.o + LL_ADC_REG_IsConversionOngoing + 18 2 Code Lc PowerPro_lto.o + __SEGGER_init_zero 18 2 Code Wk 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8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_48V/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_48V/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_48V/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,65 @@ +Output/Debug_48V/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug_48V/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug_48V/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug_48V/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Debug_48V/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,52 @@ +Output/Debug_48V/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_48V/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Debug_48V/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Debug_48V/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Debug_48V/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Debug_48V/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Debug_48V/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Debug_48V/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,48 @@ +Output/Debug_48V/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1221 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44.2 compiled Apr 14 2025 15:08:43 + Copyright (c) 2017-2024 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** 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599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 208 2 048 + ============================================= ========== ========== ========== ========== + Total: 18 304 2 274 40 3 786 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 904 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 146 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 604 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 352 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o 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(libc_v6m_t_le_eabi_balanced.a) + putchar 0x08003A6D 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + puts 0x08003A7D 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x080047A3 2 Code Gb STM32C0xx_Startup.o + strlen 0x080043B5 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + vfprintf 0x0800460B 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x08003E65 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 SysTick_Handler 16 4 Code Gb PowerPro_lto.o + 0x080000C5 DMA1_Channel1_IRQHandler 176 4 Code Gb PowerPro_lto.o + 0x08000175 TIM16_IRQHandler 288 4 Code Gb PowerPro_lto.o + 0x08000295 HAL_TIM_IC_CaptureCallback + 112 4 Code Lc PowerPro_lto.o + 0x08000305 SystemInit 16 4 Code Gb PowerPro_lto.o + 0x08000315 SystemCoreClockUpdate 80 4 Code Gb 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+*********************************************************************************************** +*** *** +*** LINK SUMMARY *** +*** *** +*********************************************************************************************** + +Memory breakdown: + + 18 304 bytes read-only code + + 2 274 bytes read-only data = 20 578 bytes read-only (total) + 3 826 bytes read-write data + +Region summary: + + Name Range Size Used Unused Alignment Loss + ---------- ----------------- ----------- ------------------- ------------------- ------------------- + FLASH 08000000-08007fff 32 768 20 582 62.81% 12 186 37.19% 0 0.00% + RAM 20000000-20002fff 12 288 3 826 31.14% 8 432 68.62% 30 0.24% + +Link complete: 0 errors, 0 warnings, 0 remarks Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/PowerPro_link.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/PowerPro_link.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/PowerPro_link.ind (revision 41) @@ -0,0 +1,10 @@ +Output/Release/Obj/PowerPro/SEGGER_THUMB_Startup.o +Output/Release/Obj/PowerPro/stm32c031xx_Vectors.o +Output/Release/Obj/PowerPro/STM32C0xx_Startup.o +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/libc_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/SEGGER_crtinit_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/prinops_rtt_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/heapops_basic_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/strops_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.24/lib/mbops_timeops_v6m_t_le_eabi_balanced.a" Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + 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D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,65 @@ +Output/Release/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Release/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Release/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,51 @@ +Output/Release/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,51 @@ +Output/Release/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Release/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,48 @@ +Output/Release/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.24\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.htm =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.htm (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.htm (revision 41) @@ -0,0 +1,37741 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ +
+SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49
+Copyright (c) 2017-2025 SEGGER Microcontroller GmbH    www.segger.com
+
+ +
+--add-region:FLASH1=0x00007800@0x08000000
+--add-region:RAM1=0x00003000@0x20000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Release_12V/Exe/PowerPro.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=6-M
+--silent
+-TD:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf
+--defsym=__STACKSIZE__=2048
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=1024
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_int_nwp
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.elf
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/PowerPro_lto.o
+Output/Release_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o
+Output/Release_12V/Obj/PowerPro/stm32c031xx_Vectors.o
+Output/Release_12V/Obj/PowerPro/STM32C0xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf'

+
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32C0xx_Flash.icf
+Purpose : STM32C0xx linker script for application placement in Flash,
+          for use with the SEGGER Linker.
+Maps    : STM32C011D6Yx, STM32C011F4Px, STM32C011F4Ux, STM32C011F6Px, 
+          STM32C011F6Ux, STM32C011J4Mx, STM32C011J6Mx, STM32C031C4Tx, 
+          STM32C031C4Ux, STM32C031C6Tx, STM32C031C6Ux, STM32C031F4Px, 
+          STM32C031F6Px, STM32C031G4Ux, STM32C031G6Ux, STM32C031K4Tx, 
+          STM32C031K4Ux, STM32C031K6Tx, STM32C031K6Ux
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM   = RAM1;
+
+//
+// Block definitions
+//
+define block vectors                        { section .vectors };                                   // Vector table section
+define block vectors_ram                    { section .vectors_ram };                               // Vector table section
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { block vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1                             { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { block vectors };                                      // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1                               { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM                       { block vectors_ram };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x08000000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x08000000180256stm32c031xx_Vectors.o
+

place at 0x20003000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#5> at line 111, col 45": place in [0x08000000 to 0x080077ff] with maximum packing

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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[.rodata..Lstr.22.133]Cnst0x080062BC231PowerPro_lto.o
[.rodata..Lstr.18.153]Cnst0x080062D3351PowerPro_lto.o
[.rodata..Lstr.22.156]Cnst0x080062F6191PowerPro_lto.o
[.rodata..Lstr.8.177]Cnst0x08006309351PowerPro_lto.o
[.rodata..Lstr.13.180]Cnst0x0800632C431PowerPro_lto.o
[.rodata..L.str.203]Cnst0x08006357351PowerPro_lto.o
__SEGGER_RTL_c_locale_month_namesCnst0x0800637A871mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_am_pm_indicatorCnst0x080063D171mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_date_time_formatCnst0x080063D8151mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
[.rodata..Lstr]Cnst0x080063E7181PowerPro_lto.o
[.rodata..Lstr.8]Cnst0x080063F9181PowerPro_lto.o
[.rodata..Lstr.10]Cnst0x0800640B461PowerPro_lto.o
[.rodata..L.str.1]Cnst0x08006439141PowerPro_lto.o
[.rodata..Lstr.12.117]Cnst0x08006447301PowerPro_lto.o
[.rodata..Lstr.23]Cnst0x08006465181PowerPro_lto.o
[.rodata..Lstr.12.123]Cnst0x08006477381PowerPro_lto.o
[.rodata..Lstr.20.132]Cnst0x0800649D381PowerPro_lto.o
[.rodata..Lstr.23.134]Cnst0x080064C3221PowerPro_lto.o
[.rodata..Lstr.10.139]Cnst0x080064D9261PowerPro_lto.o
[.rodata..Lstr.12.146]Cnst0x080064F3301PowerPro_lto.o
[.rodata..Lstr.20.155]Cnst0x08006511381PowerPro_lto.o
[.rodata..Lstr.23.157]Cnst0x08006537181PowerPro_lto.o
[.rodata..Lstr.16.172]Cnst0x08006549341PowerPro_lto.o
__SEGGER_RTL_c_locale_day_namesCnst0x0800656B581mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
[.rodata.libc..L.str]Cnst0x080065A521mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_data_utf8_periodCnst0x080065A721mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
[.rodata..Lstr.4]Cnst0x080065A9171PowerPro_lto.o
[.rodata..Lstr.12]Cnst0x080065BA251PowerPro_lto.o
[.rodata..Lstr.14]Cnst0x080065D3171PowerPro_lto.o
[.rodata..L.str.5]Cnst0x080065E4171PowerPro_lto.o
[.rodata..L.str.6]Cnst0x080065F5171PowerPro_lto.o
[.rodata..Lstr.104]Cnst0x08006606171PowerPro_lto.o
[.rodata..Lstr.118]Cnst0x08006617451PowerPro_lto.o
[.rodata..Lstr.15]Cnst0x08006644211PowerPro_lto.o
[.rodata..Lstr.17]Cnst0x0800665991PowerPro_lto.o
[.rodata..Lstr.24]Cnst0x08006662251PowerPro_lto.o
[.rodata..Lstr.124]Cnst0x0800667B531PowerPro_lto.o
[.rodata..Lstr.15.127]Cnst0x080066B0251PowerPro_lto.o
[.rodata..Lstr.24.125]Cnst0x080066C9291PowerPro_lto.o
[.rodata..Lstr.11.135]Cnst0x080066E6251PowerPro_lto.o
[.rodata..Lstr.147]Cnst0x080066FF451PowerPro_lto.o
[.rodata..Lstr.15.150]Cnst0x0800672C211PowerPro_lto.o
[.rodata..Lstr.17.152]Cnst0x0800674191PowerPro_lto.o
[.rodata..Lstr.24.148]Cnst0x0800674A251PowerPro_lto.o
[.rodata..Lstr.22.162]Cnst0x08006763411PowerPro_lto.o
[.rodata..Lstr.9.178]Cnst0x0800678C291PowerPro_lto.o
[.rodata..Lstr.15.173]Cnst0x080067A9371PowerPro_lto.o
[.rodata..L.str]Cnst0x080067CE91PowerPro_lto.o
_DoInit._aInitStrCnst0x080067D7171SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
[.rodata.libc..L.str]Cnst0x080067E891SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_date_formatCnst0x080067F191mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_time_formatCnst0x080067FA91mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_abbrev_day_namesCnst0x08006803291mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_abbrev_month_namesCnst0x08006820491mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_data_empty_stringCnst0x0800685111mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_ctype_maskCnst0x08006852131mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
[.rodata.block.tdata.copy]Cnst0x0800685F1[ Linker created ]
[.init_array]----0x0800686044STM32C0xx_Startup.o
UARTEx_SetNbDataToProcess.numeratorCnst0x0800686481PowerPro_lto.o
UARTEx_SetNbDataToProcess.denominatorCnst0x0800686C81PowerPro_lto.o
[.rodata..Lstr.3]Cnst0x08006874281PowerPro_lto.o
[.rodata..Lstr.11]Cnst0x08006890201PowerPro_lto.o
[.rodata..Lstr.13]Cnst0x080068A4161PowerPro_lto.o
[.rodata..L.str.2]Cnst0x080068B4161PowerPro_lto.o
[.rodata..L.str.3]Cnst0x080068C4161PowerPro_lto.o
[.rodata..L.str.4]Cnst0x080068D4161PowerPro_lto.o
[.rodata..Lstr.19]Cnst0x080068E481PowerPro_lto.o
[.rodata..Lstr.17.129]Cnst0x080068EC161PowerPro_lto.o
[.rodata..Lstr.19.131]Cnst0x080068FC161PowerPro_lto.o
[.rodata..Lstr.8.136]Cnst0x0800690C281PowerPro_lto.o
[.rodata..Lstr.12.138]Cnst0x08006928321PowerPro_lto.o
[.rodata..Lstr.19.154]Cnst0x0800694881PowerPro_lto.o
[.rodata..Lstr.11.179]Cnst0x08006950601PowerPro_lto.o
[.rodata..Lstr.14.174]Cnst0x0800698C281PowerPro_lto.o
__SEGGER_RTL_hex_ucCnst0x080069A8161prinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_hex_lcCnst0x080069B8161prinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_ctype_mapCnst0x080069C81281mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_init_ctorsCode0x08006A48364SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_table__Cnst0x08006A6C1804[ Linker created ]
__SEGGER_init_data__Cnst0x08006B20404[ Linker created ]
__SEGGER_init_zeroCode0x08006B48182SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_copyCode0x08006B5A202SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
+

"<#6> at line 122, col 45": place in [0x20000000 to 0x20002fff] with auto order

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Symbol or [section] nameTypeAddressSizeAlignObject File
modbusDataZero0x200000005644PowerPro_lto.o
+

"<#9> at line 128, col 45": place in [0x20000000 to 0x20002fff] with auto order

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Symbol or [section] nameTypeAddressSizeAlignObject File
sys_dataZero0x200002342244PowerPro_lto.o
_SEGGER_RTTZero0x200003141684SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
huart1Zero0x200003BC1484PowerPro_lto.o
hadc1Zero0x200004501004PowerPro_lto.o
hdma_usart1_txZero0x200004B4924PowerPro_lto.o
hdma_usart1_rxZero0x20000510924PowerPro_lto.o
hdma_adc1Zero0x2000056C924PowerPro_lto.o
htim17Zero0x200005C8764PowerPro_lto.o
htim16Zero0x20000614764PowerPro_lto.o
adcDataZero0x20000660204PowerPro_lto.o
flash_device_parameter_defaultZero0x20000674164PowerPro_lto.o
voltageUoutZero0x2000068444PowerPro_lto.o
voltageUinZero0x2000068844PowerPro_lto.o
uwTickZero0x2000068C44PowerPro_lto.o
tempZero0x2000069044PowerPro_lto.o
relais_temperatureZero0x2000069444PowerPro_lto.o
onTimeCounterSETZero0x2000069844PowerPro_lto.o
onTimeCounterRTZero0x2000069C44PowerPro_lto.o
onTimeCounterRESETZero0x200006A044PowerPro_lto.o
onTimeCounterGNZero0x200006A444PowerPro_lto.o
onTimeCounterZero0x200006A844PowerPro_lto.o
oldTimeMSTickZero0x200006AC44PowerPro_lto.o
offTimeCounterRTZero0x200006B044PowerPro_lto.o
offTimeCounterGNZero0x200006B444PowerPro_lto.o
offTimeCounterZero0x200006B844PowerPro_lto.o
numberOfBlinksZero0x200006BC44PowerPro_lto.o
msCounterZero0x200006C044PowerPro_lto.o
longPressCounterButtonOnZero0x200006C444PowerPro_lto.o
longPressCounterButtonOffZero0x200006C844PowerPro_lto.o
__SEGGER_RTL_stdout_fileZero0x200006CC44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_fileZero0x200006D044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_fileZero0x200006D444prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_locale_ptrZero0x200006D844mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
ic_overflowsZero0x200006DC44PowerPro_lto.o
frequencyZero0x200006E044PowerPro_lto.o
dropLimitCounterZero0x200006E444PowerPro_lto.o
calTemperatureSensor30ValueZero0x200006E844PowerPro_lto.o
blinkCounterZero0x200006EC44PowerPro_lto.o
autoRetryMode.170Zero0x200006F044PowerPro_lto.o
autoRetryModeZero0x200006F444PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.175Zero0x200006F844PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtimeZero0x200006FC44PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176Zero0x2000070044PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounterZero0x2000070444PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.181Zero0x2000070844PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counterZero0x2000070C44PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182Zero0x2000071044PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTickZero0x2000071444PowerPro_lto.o
OVP_SM_On.ovpTimeCounterZero0x2000071844PowerPro_lto.o
OVP_SM_On.oldtimeZero0x2000071C44PowerPro_lto.o
LVP_SM_On.oldtimeZero0x2000072044PowerPro_lto.o
LVP_SM_On.lvpTimeCounterZero0x2000072444PowerPro_lto.o
LVP_OVP_SM_On.oldtimeZero0x2000072844PowerPro_lto.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounterZero0x2000072C44PowerPro_lto.o
relaisStateZero0x2000073014PowerPro_lto.o
smState.171Zero0x2000073111PowerPro_lto.o
smState.160Zero0x2000073211PowerPro_lto.o
smState.145Zero0x2000073311PowerPro_lto.o
pauseTimeZero0x2000073414PowerPro_lto.o
smState.137Zero0x2000073511PowerPro_lto.o
smState.122Zero0x2000073611PowerPro_lto.o
smStateZero0x2000073711PowerPro_lto.o
pFlash.0Zero0x2000073814PowerPro_lto.o
modeZero0x2000073911PowerPro_lto.o
buttonStateZero0x2000073A11PowerPro_lto.o
onTimeRTZero0x2000073C14PowerPro_lto.o
onTimeGNZero0x2000074014PowerPro_lto.o
[.bss.block.heap]None0x200007408[ Linker created ]
onTimeZero0x2000074414PowerPro_lto.o
offTimeRTZero0x2000074814PowerPro_lto.o
offTimeGNZero0x2000074C14PowerPro_lto.o
offTimeZero0x2000075014PowerPro_lto.o
blinkModeRTZero0x2000075414PowerPro_lto.o
blinkModeGNZero0x2000075814PowerPro_lto.o
alarmModeZero0x2000075C14PowerPro_lto.o
OVP_SM_On.ovpInputZero0x2000076014PowerPro_lto.o
LVP_SM_On.lvpInputZero0x2000076414PowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInputZero0x2000076814PowerPro_lto.o
_acUpBufferZero0x200007691 0241SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBufferZero0x20000B69161SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
bootLoaderMarkNone0x20000B7C14PowerPro_lto.o
__SEGGER_RTL_global_localeInit0x20000B80204mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
uwTickPrioInit0x20000B9444PowerPro_lto.o
stdoutInit0x20000B9844prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdinInit0x20000B9C44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stderrInit0x20000BA044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
SystemCoreClockInit0x20000BA444PowerPro_lto.o
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#10> at line 132, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x200007408[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
PowerPro_lto.o21 1461 80681 680
SEGGER_THUMB_Startup.o20
stm32c031xx_Vectors.o214
STM32C0xx_Startup.o8
Subtotal (4 objects)21 3881 80681 680
libc_v6m_t_le_eabi_small.a2 65632
mbops_timeops_v6m_t_le_eabi_small.a190541204
prinops_rtt_v6m_t_le_eabi_small.a47026121 220
SEGGER_crtinit_v6m_t_le_eabi_small.a74
strops_v6m_t_le_eabi_small.a94
Subtotal (5 archives)3 484599321 224
Linker created (shared data, fills, blocks):2202 048
Total:24 8722 625404 952
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)840
fileops.o (libc_v6m_t_le_eabi_small.a)144
floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)992
intasmops_arm.o (libc_v6m_t_le_eabi_small.a)308
mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)190541204
prinops.o (libc_v6m_t_le_eabi_small.a)37232
prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)581212
SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)74
SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)412261 208
strasmops_arm.o (strops_v6m_t_le_eabi_small.a)34
strops.o (strops_v6m_t_le_eabi_small.a)60
Subtotal (11 members from 5 archives)3 484599321 224
Objects (4 files)21 3881 80681 680
Linker created (shared data, fills, blocks):2202 048
Total:24 8722 625404 952
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table220
Memory for block 'stack'2 048
Subtotal (linker created):2202 048
Objects (4 files)21 3881 80681 680
Archives (5 files)3 484599321 224
Total:24 8722 625404 952
+

MODULE DETAIL

+

Module PowerPro_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
main11 532
MODE_SECONDARYPROTECTION_Exec1 660
MODE_SECONDARYPROTECTION_PLUS_Exec1 108
HAL_UART_Init972
USART1_IRQHandler944
HAL_ADC_ConfigChannel608
HAL_GPIO_Init380
TIM16_IRQHandler288
EEPROM_Write280
HAL_RCCEx_PeriphCLKConfig268
HAL_UART_Receive_DMA248
HAL_DMA_Init224
HAL_TIM_Base_Init204
HAL_DMA_Start_IT196
UART_DMAReceiveCplt168
HAL_UART_ErrorCallback168
HAL_DMA_IRQHandler164
TIM_Base_SetConfig144
UART_DMAError138
ADC_DMAConvCplt100
HAL_InitTick96
UART_WaitOnFlagUntilTimeout96
UART_EndRxTransfer96
JumpToBootloader92
HAL_RCC_GetSysClockFreq84
UARTEx_SetNbDataToProcess84
SystemCoreClockUpdate80
FLASH_WaitForLastOperation80
UART_DMATransmitCplt80
HAL_RCC_GetPCLK1Freq64
EEPROM_StoreConfig60
HAL_TIM_IC_CaptureCallback56
mbCrc1656
EEPROM_WriteDefaults48
UART_DMARxHalfCplt36
EEPROM_ReadDeviceParameter36
HAL_FLASH_Unlock32
__NVIC_SystemReset28
DMA1_Channel2_3_IRQHandler24
HAL_Delay20
ADC_DMAError20
SysTick_Handler16
DMA1_Channel1_IRQHandler16
SystemInit16
UART_DMAAbortOnError16
HAL_NVIC_SystemReset4
Error_Handler4
NMI_Handler2
HardFault_Handler2
SVC_Handler2
PendSV_Handler2
ADC_DMAHalfConvCplt2
UART_DMATxHalfCplt2
AHBPrescTable64
[.rodata..Lstr.11.179]60
[.rodata..Lstr.9]59
[.rodata..Lstr.124]53
[.rodata..Lstr.10]46
[.rodata..Lstr.118]45
[.rodata..Lstr.147]45
[.rodata..Lstr.13.180]43
[.rodata..Lstr.22.162]41
[.rodata..L.str.7]39
[.rodata..Lstr.18.130]39
[.rodata..Lstr.12.123]38
[.rodata..Lstr.20.132]38
[.rodata..Lstr.20.155]38
[.rodata..Lstr.15.173]37
[.rodata..Lstr.18]35
[.rodata..Lstr.18.153]35
[.rodata..Lstr.8.177]35
[.rodata..L.str.203]35
[.rodata..Lstr.16.172]34
APBPrescTable32
[.rodata..Lstr.12.138]32
[.rodata..Lstr.12.117]30
[.rodata..Lstr.12.146]30
[.rodata..Lstr.24.125]29
[.rodata..Lstr.9.178]29
[.rodata..Lstr.3]28
[.rodata..Lstr.8.136]28
[.rodata..Lstr.14.174]28
[.rodata..Lstr.10.139]26
[.rodata..Lstr.12]25
[.rodata..Lstr.24]25
[.rodata..Lstr.15.127]25
[.rodata..Lstr.11.135]25
[.rodata..Lstr.24.148]25
UARTPrescTable24
[.rodata..Lstr.22.133]23
[.rodata..Lstr.23.134]22
[.rodata..Lstr.15]21
[.rodata..Lstr.15.150]21
[.rodata..Lstr.11]20
[.rodata..Lstr.99]19
[.rodata..Lstr.22]19
[.rodata..Lstr.22.156]19
[.rodata..Lstr]18
[.rodata..Lstr.8]18
[.rodata..Lstr.23]18
[.rodata..Lstr.23.157]18
[.rodata..Lstr.4]17
[.rodata..Lstr.14]17
[.rodata..L.str.5]17
[.rodata..L.str.6]17
[.rodata..Lstr.104]17
[.rodata..Lswitch.table.UART_SetConfig]16
[.rodata..Lstr.13]16
[.rodata..L.str.2]16
[.rodata..L.str.3]16
[.rodata..L.str.4]16
[.rodata..Lstr.17.129]16
[.rodata..Lstr.19.131]16
[.rodata..L.str.1]14
[.rodata..Lstr.17]9
[.rodata..Lstr.17.152]9
[.rodata..L.str]9
UARTEx_SetNbDataToProcess.numerator8
UARTEx_SetNbDataToProcess.denominator8
[.rodata..Lstr.19]8
[.rodata..Lstr.19.154]8
SystemCoreClock4
uwTickPrio4
modbusData564
sys_data224
huart1148
hadc1100
hdma_adc192
hdma_usart1_rx92
hdma_usart1_tx92
htim1776
htim1676
adcData20
flash_device_parameter_default16
uwTick4
longPressCounterButtonOn4
longPressCounterButtonOff4
onTimeCounter4
offTimeCounter4
calTemperatureSensor30Value4
temp4
onTimeCounterGN4
offTimeCounterGN4
onTimeCounterRT4
offTimeCounterRT4
blinkCounter4
numberOfBlinks4
ic_overflows4
oldTimeMSTick4
msCounter4
frequency4
LVP_SM_On.lvpTimeCounter4
LVP_SM_On.oldtime4
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter4
LVP_OVP_SM_On.oldtime4
OVP_SM_On.ovpTimeCounter4
OVP_SM_On.oldtime4
autoRetryMode4
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter4
SECONDARYPROTECTION_SM_On.oldtime4
SECONDARYPROTECTION_SM_Error.retry_counter4
SECONDARYPROTECTION_SM_Error.oldTimeMSTick4
autoRetryMode.1704
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1764
SECONDARYPROTECTION_SM_On.oldtime.1754
SECONDARYPROTECTION_SM_Error.retry_counter.1814
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.1824
relais_temperature4
onTimeCounterSET4
onTimeCounterRESET4
dropLimitCounter4
voltageUin4
voltageUout4
pFlash.01
buttonState1
alarmMode1
offTime1
onTime1
blinkModeGN1
offTimeGN1
onTimeGN1
blinkModeRT1
offTimeRT1
pauseTime1
onTimeRT1
bootLoaderMark1
smState1
LVP_SM_On.lvpInput1
smState.1221
LVP_OVP_SM_On.lvpOROvpInput1
smState.1371
smState.1451
OVP_SM_On.ovpInput1
smState.1601
smState.1711
mode1
relaisState1
Total:21 1461 80681 680
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32c031xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors180
WWDG_IRQHandler2
RTC_IRQHandler2
FLASH_IRQHandler2
RCC_IRQHandler2
EXTI0_1_IRQHandler2
EXTI2_3_IRQHandler2
EXTI4_15_IRQHandler2
DMAMUX1_IRQHandler2
ADC1_IRQHandler2
TIM1_BRK_UP_TRG_COM_IRQHandler2
TIM1_CC_IRQHandler2
TIM3_IRQHandler2
TIM14_IRQHandler2
TIM17_IRQHandler2
I2C1_IRQHandler2
SPI1_IRQHandler2
USART2_IRQHandler2
Total:214
+

Module STM32C0xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler8
Total:8
+

Module fileops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
fwrite50
puts44
fputc34
putchar16
Total:144
+

Module floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_dmul_aux394
__aeabi_ddiv196
__aeabi_fmul182
__aeabi_d2iz52
__aeabi_d2uiz46
__aeabi_f2uiz36
__aeabi_ui2f30
__aeabi_i2d28
__aeabi_ui2d28
Total:992
+

Module intasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_uldivmod136
__aeabi_idiv64
__aeabi_uidiv56
__aeabi_lmul46
__aeabi_idiv06
Total:308
+

Module prinops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_putc138
vfprintf_l108
printf40
__SEGGER_RTL_prin_flush26
vfprintf26
__SEGGER_RTL_init_prin_l18
__SEGGER_RTL_stream_write16
__SEGGER_RTL_hex_uc16
__SEGGER_RTL_hex_lc16
Total:37232
+

Module __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp840
Total:840
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_X_file_stat44
__SEGGER_RTL_X_file_write10
__SEGGER_RTL_X_file_bufsize4
stdin4
stdout4
stderr4
__SEGGER_RTL_stdin_file4
__SEGGER_RTL_stdout_file4
__SEGGER_RTL_stderr_file4
Total:581212
+

Module SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SEGGER_RTT_WriteNoLock104
_WriteBlocking88
_DoInit84
_WriteNoCheck58
SEGGER_RTT_Write56
_GetAvailWriteSpace22
_DoInit._aInitStr17
[.rodata.libc..L.str]9
_acUpBuffer1 024
_SEGGER_RTT168
_acDownBuffer16
Total:412261 208
+

Module strops.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
memcmp46
strlen14
Total:60
+

Module strasmops_arm.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr20
memcpy14
Total:34
+

Module mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_ascii_mbtowc46
__SEGGER_RTL_ascii_isctype28
__SEGGER_RTL_ascii_iswctype28
__SEGGER_RTL_current_locale20
__SEGGER_RTL_ascii_wctomb16
__SEGGER_RTL_ascii_tolower14
__SEGGER_RTL_ascii_towlower14
__SEGGER_RTL_ascii_toupper12
__SEGGER_RTL_ascii_towupper12
__SEGGER_RTL_ascii_ctype_map128
__SEGGER_RTL_c_locale_data88
__SEGGER_RTL_c_locale_month_names87
__SEGGER_RTL_c_locale_day_names58
__SEGGER_RTL_c_locale_abbrev_month_names49
__SEGGER_RTL_codeset_ascii32
__SEGGER_RTL_c_locale_abbrev_day_names29
__SEGGER_RTL_c_locale_date_time_format15
__SEGGER_RTL_ascii_ctype_mask13
__SEGGER_RTL_c_locale12
__SEGGER_RTL_c_locale_date_format9
__SEGGER_RTL_c_locale_time_format9
__SEGGER_RTL_c_locale_am_pm_indicator7
[.rodata.libc..L.str]2
__SEGGER_RTL_data_utf8_period2
__SEGGER_RTL_data_empty_string1
__SEGGER_RTL_global_locale20
__SEGGER_RTL_locale_ptr4
Total:190541204
+

All modules

+ + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:24 8722 405402 904
+

SECTION DETAIL

+

Sections by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0800698C-080069A7[.rodata..Lstr.14.174]281CnstROPowerPro_lto.o
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080069B8-080069C7__SEGGER_RTL_hex_lc161CnstROprinops.o (libc_v6m_t_le_eabi_small.a)
080069C8-08006A47__SEGGER_RTL_ascii_ctype_map1281CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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08006B6E-1FFFFFFF( UNUSED .=.+402625682 )402 625 682-------
20000000-20000233modbusData5644ZeroZIPowerPro_lto.o
20000234-20000313sys_data2244ZeroZIPowerPro_lto.o
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2000056C-200005C7hdma_adc1924ZeroZIPowerPro_lto.o
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20000614-2000065Fhtim16764ZeroZIPowerPro_lto.o
20000660-20000673adcData204ZeroZIPowerPro_lto.o
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20000684-20000687voltageUout44ZeroZIPowerPro_lto.o
20000688-2000068BvoltageUin44ZeroZIPowerPro_lto.o
2000068C-2000068FuwTick44ZeroZIPowerPro_lto.o
20000690-20000693temp44ZeroZIPowerPro_lto.o
20000694-20000697relais_temperature44ZeroZIPowerPro_lto.o
20000698-2000069BonTimeCounterSET44ZeroZIPowerPro_lto.o
2000069C-2000069FonTimeCounterRT44ZeroZIPowerPro_lto.o
200006A0-200006A3onTimeCounterRESET44ZeroZIPowerPro_lto.o
200006A4-200006A7onTimeCounterGN44ZeroZIPowerPro_lto.o
200006A8-200006ABonTimeCounter44ZeroZIPowerPro_lto.o
200006AC-200006AFoldTimeMSTick44ZeroZIPowerPro_lto.o
200006B0-200006B3offTimeCounterRT44ZeroZIPowerPro_lto.o
200006B4-200006B7offTimeCounterGN44ZeroZIPowerPro_lto.o
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200006BC-200006BFnumberOfBlinks44ZeroZIPowerPro_lto.o
200006C0-200006C3msCounter44ZeroZIPowerPro_lto.o
200006C4-200006C7longPressCounterButtonOn44ZeroZIPowerPro_lto.o
200006C8-200006CBlongPressCounterButtonOff44ZeroZIPowerPro_lto.o
200006CC-200006CF__SEGGER_RTL_stdout_file44ZeroZIprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
200006D0-200006D3__SEGGER_RTL_stdin_file44ZeroZIprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
200006D4-200006D7__SEGGER_RTL_stderr_file44ZeroZIprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
200006D8-200006DB__SEGGER_RTL_locale_ptr44ZeroZImbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
200006DC-200006DFic_overflows44ZeroZIPowerPro_lto.o
200006E0-200006E3frequency44ZeroZIPowerPro_lto.o
200006E4-200006E7dropLimitCounter44ZeroZIPowerPro_lto.o
200006E8-200006EBcalTemperatureSensor30Value44ZeroZIPowerPro_lto.o
200006EC-200006EFblinkCounter44ZeroZIPowerPro_lto.o
200006F0-200006F3autoRetryMode.17044ZeroZIPowerPro_lto.o
200006F4-200006F7autoRetryMode44ZeroZIPowerPro_lto.o
200006F8-200006FBSECONDARYPROTECTION_SM_On.oldtime.17544ZeroZIPowerPro_lto.o
200006FC-200006FFSECONDARYPROTECTION_SM_On.oldtime44ZeroZIPowerPro_lto.o
20000700-20000703SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.17644ZeroZIPowerPro_lto.o
20000704-20000707SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter44ZeroZIPowerPro_lto.o
20000708-2000070BSECONDARYPROTECTION_SM_Error.retry_counter.18144ZeroZIPowerPro_lto.o
2000070C-2000070FSECONDARYPROTECTION_SM_Error.retry_counter44ZeroZIPowerPro_lto.o
20000710-20000713SECONDARYPROTECTION_SM_Error.oldTimeMSTick.18244ZeroZIPowerPro_lto.o
20000714-20000717SECONDARYPROTECTION_SM_Error.oldTimeMSTick44ZeroZIPowerPro_lto.o
20000718-2000071BOVP_SM_On.ovpTimeCounter44ZeroZIPowerPro_lto.o
2000071C-2000071FOVP_SM_On.oldtime44ZeroZIPowerPro_lto.o
20000720-20000723LVP_SM_On.oldtime44ZeroZIPowerPro_lto.o
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20000728-2000072BLVP_OVP_SM_On.oldtime44ZeroZIPowerPro_lto.o
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20000730-20000730relaisState14ZeroZIPowerPro_lto.o
20000731-20000731smState.17111ZeroZIPowerPro_lto.o
20000732-20000732smState.16011ZeroZIPowerPro_lto.o
20000733-20000733smState.14511ZeroZIPowerPro_lto.o
20000734-20000734pauseTime14ZeroZIPowerPro_lto.o
20000735-20000735smState.13711ZeroZIPowerPro_lto.o
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20000737-20000737smState11ZeroZIPowerPro_lto.o
20000738-20000738pFlash.014ZeroZIPowerPro_lto.o
20000739-20000739mode11ZeroZIPowerPro_lto.o
2000073A-2000073AbuttonState11ZeroZIPowerPro_lto.o
2000073B-2000073B( UNUSED .=.+1 )1-------
2000073C-2000073ConTimeRT14ZeroZIPowerPro_lto.o
2000073D-2000073F( ALIGN .=.+3 )3-------
20000740-20000740onTimeGN14ZeroZIPowerPro_lto.o
20000741-20000743( ALIGN .=.+3 )3-------
20000744-20000744onTime14ZeroZIPowerPro_lto.o
20000745-20000747( ALIGN .=.+3 )3-------
20000748-20000748offTimeRT14ZeroZIPowerPro_lto.o
20000749-2000074B( ALIGN .=.+3 )3-------
2000074C-2000074CoffTimeGN14ZeroZIPowerPro_lto.o
2000074D-2000074F( ALIGN .=.+3 )3-------
20000750-20000750offTime14ZeroZIPowerPro_lto.o
20000751-20000753( ALIGN .=.+3 )3-------
20000754-20000754blinkModeRT14ZeroZIPowerPro_lto.o
20000755-20000757( ALIGN .=.+3 )3-------
20000758-20000758blinkModeGN14ZeroZIPowerPro_lto.o
20000759-2000075B( ALIGN .=.+3 )3-------
2000075C-2000075CalarmMode14ZeroZIPowerPro_lto.o
2000075D-2000075F( ALIGN .=.+3 )3-------
20000760-20000760OVP_SM_On.ovpInput14ZeroZIPowerPro_lto.o
20000761-20000763( ALIGN .=.+3 )3-------
20000764-20000764LVP_SM_On.lvpInput14ZeroZIPowerPro_lto.o
20000765-20000767( ALIGN .=.+3 )3-------
20000768-20000768LVP_OVP_SM_On.lvpOROvpInput14ZeroZIPowerPro_lto.o
20000769-20000B68_acUpBuffer1 0241ZeroZISEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B69-20000B78_acDownBuffer161ZeroZISEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B79-20000B7B( UNUSED .=.+3 )3-------
20000B7C-20000B7CbootLoaderMark14NoneZIPowerPro_lto.o
20000B7D-20000B7F( ALIGN .=.+3 )3-------
20000B80-20000B93__SEGGER_RTL_global_locale204InitRWmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
20000B94-20000B97uwTickPrio44InitRWPowerPro_lto.o
20000B98-20000B9Bstdout44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B9C-20000B9Fstdin44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000BA0-20000BA3stderr44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000BA4-20000BA7SystemCoreClock44InitRWPowerPro_lto.o
20000BA8-200027FF( UNUSED .=.+7256 )7 256-------
20002800-20002FFF[.bss.block.stack]2 0488NoneZI[ Linker created ]
+

UNUSED MEMORY SUMMARY

+

Detail

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeReason
0800685F-0800685F1Unused memory between sections '.rodata.libc.__SEGGER_RTL_ascii_ctype_mask' and '.init_array'
08006B6E-1FFFFFFF402 625 682Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.RAM1'
2000073B-2000073B1Unused memory between sections '.bss.buttonState' and '.bss.onTimeRT'
2000073D-2000073F3Filler between sections '.bss.onTimeRT' and '.bss.onTimeGN' as align=4
NOTE: section '.bss.onTimeRT' has size 1 that is not a multiple of its alignment 4
20000741-200007433Filler between sections '.bss.onTimeGN' and '.bss.onTime' as align=4
NOTE: section '.bss.onTimeGN' has size 1 that is not a multiple of its alignment 4
20000745-200007473Filler between sections '.bss.onTime' and '.bss.offTimeRT' as align=4
NOTE: section '.bss.onTime' has size 1 that is not a multiple of its alignment 4
20000749-2000074B3Filler between sections '.bss.offTimeRT' and '.bss.offTimeGN' as align=4
NOTE: section '.bss.offTimeRT' has size 1 that is not a multiple of its alignment 4
2000074D-2000074F3Filler between sections '.bss.offTimeGN' and '.bss.offTime' as align=4
NOTE: section '.bss.offTimeGN' has size 1 that is not a multiple of its alignment 4
20000751-200007533Filler between sections '.bss.offTime' and '.bss.blinkModeRT' as align=4
NOTE: section '.bss.offTime' has size 1 that is not a multiple of its alignment 4
20000755-200007573Filler between sections '.bss.blinkModeRT' and '.bss.blinkModeGN' as align=4
NOTE: section '.bss.blinkModeRT' has size 1 that is not a multiple of its alignment 4
20000759-2000075B3Filler between sections '.bss.blinkModeGN' and '.bss.alarmMode' as align=4
NOTE: section '.bss.blinkModeGN' has size 1 that is not a multiple of its alignment 4
2000075D-2000075F3Filler between sections '.bss.alarmMode' and '.bss.OVP_SM_On.ovpInput' as align=4
NOTE: section '.bss.alarmMode' has size 1 that is not a multiple of its alignment 4
20000761-200007633Filler between sections '.bss.OVP_SM_On.ovpInput' and '.bss.LVP_SM_On.lvpInput' as align=4
NOTE: section '.bss.OVP_SM_On.ovpInput' has size 1 that is not a multiple of its alignment 4
20000765-200007673Filler between sections '.bss.LVP_SM_On.lvpInput' and '.bss.LVP_OVP_SM_On.lvpOROvpInput' as align=4
NOTE: section '.bss.LVP_SM_On.lvpInput' has size 1 that is not a multiple of its alignment 4
20000B79-20000B7B3Unused memory between sections '.bss.libc._acDownBuffer' and '.no_init'
20000B7D-20000B7F3Filler between sections '.no_init' and '.data.libc.__SEGGER_RTL_global_locale' as align=4
NOTE: section '.no_init' has size 1 that is not a multiple of its alignment 4
20000BA8-200027FF7 256Unused memory between sections '.data.SystemCoreClock' and '.bss.block.stack'
+

INITIALIZATION TABLE

+

Constructor list

+ + + + + + + + + + + +
Table
Address		Called
Address		Called
Symbol or [section] name
0x080068600x08000605SystemCoreClockUpdate
+

Initialize by zero

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000000-20000233564modbusData
20000234-20000313224sys_data
20000314-200003BB168_SEGGER_RTT
200003BC-2000044F148huart1
20000450-200004B3100hadc1
200004B4-2000050F92hdma_usart1_tx
20000510-2000056B92hdma_usart1_rx
2000056C-200005C792hdma_adc1
200005C8-2000061376htim17
20000614-2000065F76htim16
20000660-2000067320adcData
20000674-2000068316flash_device_parameter_default
20000684-200006874voltageUout
20000688-2000068B4voltageUin
2000068C-2000068F4uwTick
20000690-200006934temp
20000694-200006974relais_temperature
20000698-2000069B4onTimeCounterSET
2000069C-2000069F4onTimeCounterRT
200006A0-200006A34onTimeCounterRESET
200006A4-200006A74onTimeCounterGN
200006A8-200006AB4onTimeCounter
200006AC-200006AF4oldTimeMSTick
200006B0-200006B34offTimeCounterRT
200006B4-200006B74offTimeCounterGN
200006B8-200006BB4offTimeCounter
200006BC-200006BF4numberOfBlinks
200006C0-200006C34msCounter
200006C4-200006C74longPressCounterButtonOn
200006C8-200006CB4longPressCounterButtonOff
200006CC-200006CF4__SEGGER_RTL_stdout_file
200006D0-200006D34__SEGGER_RTL_stdin_file
200006D4-200006D74__SEGGER_RTL_stderr_file
200006D8-200006DB4__SEGGER_RTL_locale_ptr
200006DC-200006DF4ic_overflows
200006E0-200006E34frequency
200006E4-200006E74dropLimitCounter
200006E8-200006EB4calTemperatureSensor30Value
200006EC-200006EF4blinkCounter
200006F0-200006F34autoRetryMode.170
200006F4-200006F74autoRetryMode
200006F8-200006FB4SECONDARYPROTECTION_SM_On.oldtime.175
200006FC-200006FF4SECONDARYPROTECTION_SM_On.oldtime
20000700-200007034SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176
20000704-200007074SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
20000708-2000070B4SECONDARYPROTECTION_SM_Error.retry_counter.181
2000070C-2000070F4SECONDARYPROTECTION_SM_Error.retry_counter
20000710-200007134SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182
20000714-200007174SECONDARYPROTECTION_SM_Error.oldTimeMSTick
20000718-2000071B4OVP_SM_On.ovpTimeCounter
2000071C-2000071F4OVP_SM_On.oldtime
20000720-200007234LVP_SM_On.oldtime
20000724-200007274LVP_SM_On.lvpTimeCounter
20000728-2000072B4LVP_OVP_SM_On.oldtime
2000072C-2000072F4LVP_OVP_SM_On.lvpAndOvpInputTimeCounter
20000730-200007301relaisState
20000731-200007311smState.171
20000732-200007321smState.160
20000733-200007331smState.145
20000734-200007341pauseTime
20000735-200007351smState.137
20000736-200007361smState.122
20000737-200007371smState
20000738-200007381pFlash.0
20000739-200007391mode
2000073A-2000073A1buttonState
20000000-2000073A1 851Total (66 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000073C-2000073C1onTimeRT
2000073C-2000073C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000740-200007401onTimeGN
20000740-200007401Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000744-200007441onTime
20000744-200007441Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000748-200007481offTimeRT
20000748-200007481Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000074C-2000074C1offTimeGN
2000074C-2000074C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000750-200007501offTime
20000750-200007501Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000754-200007541blinkModeRT
20000754-200007541Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000758-200007581blinkModeGN
20000758-200007581Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000075C-2000075C1alarmMode
2000075C-2000075C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000760-200007601OVP_SM_On.ovpInput
20000760-200007601Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000764-200007641LVP_SM_On.lvpInput
20000764-200007641Total (1 sections)
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+
RangeSizeSymbol or [section] name
20000768-200007681LVP_OVP_SM_On.lvpOROvpInput
20000769-20000B681 024_acUpBuffer
20000B69-20000B7816_acDownBuffer
20000768-20000B781 041Total (3 sections)
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Summary

+
RangeSizeSymbol or [section] name
20000B80-20000B9320__SEGGER_RTL_global_locale
20000B94-20000B974uwTickPrio
20000B98-20000B9B4stdout
20000B9C-20000B9F4stdin
20000BA0-20000BA34stderr
20000BA4-20000BA74SystemCoreClock
20000B80-20000BA740Total (6 sections)
+ + + + + + + + + + + + + + + + + + + + +
DescriptionSize
Initialization table180 bytes
Source image40 bytes
Destination image2 943 bytes
Saving2 723 bytes
+

LINKER-CREATED VENEERS

+

Arm-Arm range extension veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Thumb range extension veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Arm-Thumb mode switch veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Arm mode switch veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Veneer TypeSize
Thumb-Arm mode switch0
Arm-Thumb mode switch0
Thumb-Thumb range extension0
Arm-Arm range extension0
Total:0
+

SYMBOL LIST

+

Function symbols by name

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Symbol nameAddressSizeAlignTypeBdObject File
ADC1_IRQHandler0x080058AB2CodeWkstm32c031xx_Vectors.o
ADC_DMAConvCplt0x08005D8F1002CodeLcPowerPro_lto.o
ADC_DMAError0x08005DF3202CodeLcPowerPro_lto.o
ADC_DMAHalfConvCplt0x0800580D22CodeLcPowerPro_lto.o
DMA1_Channel1_IRQHandler0x080000C5164CodeGbPowerPro_lto.o
DMA1_Channel2_3_IRQHandler0x080000D5244CodeGbPowerPro_lto.o
DMAMUX1_IRQHandler0x080058A92CodeWkstm32c031xx_Vectors.o
EEPROM_ReadDeviceParameter0x080017E5364CodeLcPowerPro_lto.o
EEPROM_StoreConfig0x08001809604CodeLcPowerPro_lto.o
EEPROM_Write0x0800169D2804CodeLcPowerPro_lto.o
EEPROM_WriteDefaults0x080017B5484CodeLcPowerPro_lto.o
EXTI0_1_IRQHandler0x080058A32CodeWkstm32c031xx_Vectors.o
EXTI2_3_IRQHandler0x080058A52CodeWkstm32c031xx_Vectors.o
EXTI4_15_IRQHandler0x080058A72CodeWkstm32c031xx_Vectors.o
Error_Handler0x08005EE742CodeLcPowerPro_lto.o
FLASH_IRQHandler0x0800589F2CodeWkstm32c031xx_Vectors.o
FLASH_WaitForLastOperation0x08000B8D804CodeLcPowerPro_lto.o
HAL_ADC_ConfigChannel0x080006C96084CodeLcPowerPro_lto.o
HAL_DMA_IRQHandler0x08000AE91644CodeLcPowerPro_lto.o
HAL_DMA_Init0x080009452244CodeLcPowerPro_lto.o
HAL_DMA_Start_IT0x08000A251964CodeLcPowerPro_lto.o
HAL_Delay0x080006B5204CodeLcPowerPro_lto.o
HAL_FLASH_Unlock0x08000BDD324CodeLcPowerPro_lto.o
HAL_GPIO_Init0x08000BFD3804CodeLcPowerPro_lto.o
HAL_InitTick0x08000655964CodeLcPowerPro_lto.o
HAL_NVIC_SystemReset0x08005E0742CodeLcPowerPro_lto.o
HAL_RCCEx_PeriphCLKConfig0x08000E0D2684CodeLcPowerPro_lto.o
HAL_RCC_GetPCLK1Freq0x08000DCD644CodeLcPowerPro_lto.o
HAL_RCC_GetSysClockFreq0x08000D79844CodeLcPowerPro_lto.o
HAL_TIM_Base_Init0x08000F192044CodeLcPowerPro_lto.o
HAL_TIM_IC_CaptureCallback0x080005BD564CodeLcPowerPro_lto.o
HAL_UART_ErrorCallback0x080045AD1684CodeLcPowerPro_lto.o
HAL_UART_Init0x080010759724CodeLcPowerPro_lto.o
HAL_UART_Receive_DMA0x080015512484CodeLcPowerPro_lto.o
HardFault_Handler0x0800580722CodeGbPowerPro_lto.o
I2C1_IRQHandler0x080058B72CodeWkstm32c031xx_Vectors.o
JumpToBootloader0x08004551924CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_Exec0x0800468D1 6604CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_PLUS_Exec0x08004D091 1084CodeLcPowerPro_lto.o
NMI_Handler0x0800580522CodeGbPowerPro_lto.o
PendSV_Handler0x0800580B22CodeGbPowerPro_lto.o
RCC_IRQHandler0x080058A12CodeWkstm32c031xx_Vectors.o
RTC_IRQHandler0x0800589D2CodeWkstm32c031xx_Vectors.o
Reset_Handler0x08005F032CodeGbSTM32C0xx_Startup.o
SEGGER_RTT_Write0x080056FD564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteNoLock0x080056951044CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SPI1_IRQHandler0x080058B92CodeWkstm32c031xx_Vectors.o
SVC_Handler0x0800580922CodeGbPowerPro_lto.o
SysTick_Handler0x080000B5164CodeGbPowerPro_lto.o
SystemCoreClockUpdate0x08000605804CodeGbPowerPro_lto.o
SystemInit0x080005F5164CodeGbPowerPro_lto.o
TIM14_IRQHandler0x080058B32CodeWkstm32c031xx_Vectors.o
TIM16_IRQHandler0x080000ED2884CodeGbPowerPro_lto.o
TIM17_IRQHandler0x080058B52CodeWkstm32c031xx_Vectors.o
TIM1_BRK_UP_TRG_COM_IRQHandler0x080058AD2CodeWkstm32c031xx_Vectors.o
TIM1_CC_IRQHandler0x080058AF2CodeWkstm32c031xx_Vectors.o
TIM3_IRQHandler0x080058B12CodeWkstm32c031xx_Vectors.o
TIM_Base_SetConfig0x08000FE51444CodeLcPowerPro_lto.o
UARTEx_SetNbDataToProcess0x08001649844CodeLcPowerPro_lto.o
UART_DMAAbortOnError0x08005ED7162CodeLcPowerPro_lto.o
UART_DMAError0x080058111382CodeLcPowerPro_lto.o
UART_DMAReceiveCplt0x08005E0B1682CodeLcPowerPro_lto.o
UART_DMARxHalfCplt0x08005EB3362CodeLcPowerPro_lto.o
UART_DMATransmitCplt0x08001501804CodeLcPowerPro_lto.o
UART_DMATxHalfCplt0x0800580F22CodeLcPowerPro_lto.o
UART_EndRxTransfer0x080014A1964CodeLcPowerPro_lto.o
UART_WaitOnFlagUntilTimeout0x08001441964CodeLcPowerPro_lto.o
USART1_IRQHandler0x0800020D9444CodeGbPowerPro_lto.o
USART2_IRQHandler0x080058BB2CodeWkstm32c031xx_Vectors.o
WWDG_IRQHandler0x0800589B2CodeWkstm32c031xx_Vectors.o
_DoInit0x08005641844CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
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_WriteBlocking0x08006157882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_WriteNoCheck0x08005CC1582CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__NVIC_SystemReset0x08000929284CodeLcPowerPro_lto.o
__SEGGER_RTL_X_file_bufsize0x0800615342CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_stat0x08005615444CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_write0x08005CA1102CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_isctype0x08005749284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_iswctype0x08005765284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_mbtowc0x08005D45462CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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__SEGGER_RTL_ascii_towupper0x080061DF122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_wctomb0x080061C3162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_current_locale0x08005735204CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_init_prin_l0x08005C75182CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_prin_flush0x08005C5B262CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_putc0x08005BD11382CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stream_write0x08006143162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf0x080052CD8404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf_int_nwp0x080052CD8404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_copy0x08006B5B202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_ctors0x08006A49264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_done0x080051D74CodeGbSEGGER_THUMB_Startup.o
__SEGGER_init_zero0x08006B49182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__aeabi_d2iz0x08005FCF522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
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__aeabi_ddiv0x08005F0B1962CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_dmul0x080059FF2CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_dmul_aux0x080059C73942CodeLcfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_f2uiz0x08006003362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_fmul0x080059111822CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_i2d0x0800521D224CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_idiv0x08006043642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_idiv00x08005BCB62CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_lmul0x08005B9D462CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_memclr0x080061AF202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr40x080061AF2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr80x080061AF2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy0x08005D372CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy40x08005D372CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy80x08005D372CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset0x080061B12CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset40x080061B12CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset80x080061B12CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_ui2d0x08006027282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_ui2f0x08005B7F302CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_uidiv0x08006083562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_uldivmod0x080060BB1362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__startup_complete0x080051D74CodeGbSEGGER_THUMB_Startup.o
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exit0x080051DB24CodeGbSEGGER_THUMB_Startup.o
fputc0x080058BD342CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
fwrite0x080058DF502CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
main0x0800184511 5324CodeGbPowerPro_lto.o
mbCrc160x08004655564CodeLcPowerPro_lto.o
memcmp0x08005CFB462CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
memcpy0x08005D37142CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
memset0x080061B72CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
printf0x080052A5404CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
putchar0x080051E1164CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
puts0x080051F1444CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
reset_handler0x08005F032CodeGbSTM32C0xx_Startup.o
strlen0x08005D29142CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
vfprintf0x08005C87262CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
vfprintf_l0x080052391084CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
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Function symbols by address

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JumpToBootloader924CodeLcPowerPro_lto.o
_WriteBlocking882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
HAL_RCC_GetSysClockFreq844CodeLcPowerPro_lto.o
UARTEx_SetNbDataToProcess844CodeLcPowerPro_lto.o
_DoInit844CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
FLASH_WaitForLastOperation804CodeLcPowerPro_lto.o
SystemCoreClockUpdate804CodeGbPowerPro_lto.o
UART_DMATransmitCplt804CodeLcPowerPro_lto.o
HAL_RCC_GetPCLK1Freq644CodeLcPowerPro_lto.o
__aeabi_idiv642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
EEPROM_StoreConfig604CodeLcPowerPro_lto.o
_WriteNoCheck582CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
HAL_TIM_IC_CaptureCallback564CodeLcPowerPro_lto.o
SEGGER_RTT_Write564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_uidiv562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
mbCrc16564CodeLcPowerPro_lto.o
__aeabi_d2iz522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
fwrite502CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
EEPROM_WriteDefaults484CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_mbtowc462CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__aeabi_d2uiz462CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_lmul462CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
memcmp462CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_stat444CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
puts444CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
printf404CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
EEPROM_ReadDeviceParameter364CodeLcPowerPro_lto.o
UART_DMARxHalfCplt362CodeLcPowerPro_lto.o
__aeabi_f2uiz362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
fputc342CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
HAL_FLASH_Unlock324CodeLcPowerPro_lto.o
__aeabi_ui2f302CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__NVIC_SystemReset284CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_isctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_iswctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__aeabi_ui2d282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_prin_flush262CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
vfprintf262CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
DMA1_Channel2_3_IRQHandler244CodeGbPowerPro_lto.o
_GetAvailWriteSpace222CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_i2d224CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
ADC_DMAError202CodeLcPowerPro_lto.o
HAL_Delay204CodeLcPowerPro_lto.o
__SEGGER_RTL_current_locale204CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__aeabi_memclr202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_init_prin_l182CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
DMA1_Channel1_IRQHandler164CodeGbPowerPro_lto.o
SysTick_Handler164CodeGbPowerPro_lto.o
SystemInit164CodeGbPowerPro_lto.o
UART_DMAAbortOnError162CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_wctomb162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stream_write162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
putchar164CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_tolower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towlower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
_start144CodeGbSEGGER_THUMB_Startup.o
memcpy142CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
strlen142CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_toupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_write102CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_idiv062CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
Error_Handler42CodeLcPowerPro_lto.o
HAL_NVIC_SystemReset42CodeLcPowerPro_lto.o
__SEGGER_RTL_X_file_bufsize42CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
ADC_DMAHalfConvCplt22CodeLcPowerPro_lto.o
HardFault_Handler22CodeGbPowerPro_lto.o
NMI_Handler22CodeGbPowerPro_lto.o
PendSV_Handler22CodeGbPowerPro_lto.o
SVC_Handler22CodeGbPowerPro_lto.o
UART_DMATxHalfCplt22CodeLcPowerPro_lto.o
exit24CodeGbSEGGER_THUMB_Startup.o
ADC1_IRQHandler2CodeWkstm32c031xx_Vectors.o
DMAMUX1_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI0_1_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI2_3_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI4_15_IRQHandler2CodeWkstm32c031xx_Vectors.o
FLASH_IRQHandler2CodeWkstm32c031xx_Vectors.o
I2C1_IRQHandler2CodeWkstm32c031xx_Vectors.o
RCC_IRQHandler2CodeWkstm32c031xx_Vectors.o
RTC_IRQHandler2CodeWkstm32c031xx_Vectors.o
Reset_Handler2CodeGbSTM32C0xx_Startup.o
SPI1_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM14_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM17_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM1_BRK_UP_TRG_COM_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM1_CC_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM3_IRQHandler2CodeWkstm32c031xx_Vectors.o
USART2_IRQHandler2CodeWkstm32c031xx_Vectors.o
WWDG_IRQHandler2CodeWkstm32c031xx_Vectors.o
__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
__aeabi_dmul2CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_memclr42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__startup_complete4CodeGbSEGGER_THUMB_Startup.o
memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
reset_handler2CodeGbSTM32C0xx_Startup.o
+

Read-write data symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter0x2000072C44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInput0x2000076814ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.oldtime0x2000072844ZeroLcPowerPro_lto.o
LVP_SM_On.lvpInput0x2000076414ZeroLcPowerPro_lto.o
LVP_SM_On.lvpTimeCounter0x2000072444ZeroLcPowerPro_lto.o
LVP_SM_On.oldtime0x2000072044ZeroLcPowerPro_lto.o
OVP_SM_On.oldtime0x2000071C44ZeroLcPowerPro_lto.o
OVP_SM_On.ovpInput0x2000076014ZeroLcPowerPro_lto.o
OVP_SM_On.ovpTimeCounter0x2000071844ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick0x2000071444ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.1820x2000071044ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter0x2000070C44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.1810x2000070844ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter0x2000070444ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1760x2000070044ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime0x200006FC44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.1750x200006F844ZeroLcPowerPro_lto.o
SystemCoreClock0x20000BA444InitLcPowerPro_lto.o
_SEGGER_RTT0x200003141684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__RAL_global_locale0x20000B80204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_global_locale0x20000B80204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_locale_ptr0x200006D844ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_file0x200006D444ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_file0x200006D044ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdout_file0x200006CC44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBuffer0x20000B6916ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acUpBuffer0x200007691 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
adcData0x20000660204ZeroLcPowerPro_lto.o
alarmMode0x2000075C14ZeroLcPowerPro_lto.o
autoRetryMode0x200006F444ZeroLcPowerPro_lto.o
autoRetryMode.1700x200006F044ZeroLcPowerPro_lto.o
blinkCounter0x200006EC44ZeroLcPowerPro_lto.o
blinkModeGN0x2000075814ZeroLcPowerPro_lto.o
blinkModeRT0x2000075414ZeroLcPowerPro_lto.o
bootLoaderMark0x20000B7C14NoneLcPowerPro_lto.o
buttonState0x2000073A1ZeroLcPowerPro_lto.o
calTemperatureSensor30Value0x200006E844ZeroLcPowerPro_lto.o
dropLimitCounter0x200006E444ZeroLcPowerPro_lto.o
flash_device_parameter_default0x20000674164ZeroLcPowerPro_lto.o
frequency0x200006E044ZeroLcPowerPro_lto.o
hadc10x200004501004ZeroLcPowerPro_lto.o
hdma_adc10x2000056C924ZeroLcPowerPro_lto.o
hdma_usart1_rx0x20000510924ZeroLcPowerPro_lto.o
hdma_usart1_tx0x200004B4924ZeroLcPowerPro_lto.o
htim160x20000614764ZeroLcPowerPro_lto.o
htim170x200005C8764ZeroLcPowerPro_lto.o
huart10x200003BC1484ZeroLcPowerPro_lto.o
ic_overflows0x200006DC44ZeroLcPowerPro_lto.o
longPressCounterButtonOff0x200006C844ZeroLcPowerPro_lto.o
longPressCounterButtonOn0x200006C444ZeroLcPowerPro_lto.o
modbusData0x200000005644ZeroLcPowerPro_lto.o
mode0x200007391ZeroLcPowerPro_lto.o
msCounter0x200006C044ZeroLcPowerPro_lto.o
numberOfBlinks0x200006BC44ZeroLcPowerPro_lto.o
offTime0x2000075014ZeroLcPowerPro_lto.o
offTimeCounter0x200006B844ZeroLcPowerPro_lto.o
offTimeCounterGN0x200006B444ZeroLcPowerPro_lto.o
offTimeCounterRT0x200006B044ZeroLcPowerPro_lto.o
offTimeGN0x2000074C14ZeroLcPowerPro_lto.o
offTimeRT0x2000074814ZeroLcPowerPro_lto.o
oldTimeMSTick0x200006AC44ZeroLcPowerPro_lto.o
onTime0x2000074414ZeroLcPowerPro_lto.o
onTimeCounter0x200006A844ZeroLcPowerPro_lto.o
onTimeCounterGN0x200006A444ZeroLcPowerPro_lto.o
onTimeCounterRESET0x200006A044ZeroLcPowerPro_lto.o
onTimeCounterRT0x2000069C44ZeroLcPowerPro_lto.o
onTimeCounterSET0x2000069844ZeroLcPowerPro_lto.o
onTimeGN0x2000074014ZeroLcPowerPro_lto.o
onTimeRT0x2000073C14ZeroLcPowerPro_lto.o
pFlash.00x2000073814ZeroLcPowerPro_lto.o
pauseTime0x2000073414ZeroLcPowerPro_lto.o
relaisState0x2000073014ZeroLcPowerPro_lto.o
relais_temperature0x2000069444ZeroLcPowerPro_lto.o
smState0x200007371ZeroLcPowerPro_lto.o
smState.1220x200007361ZeroLcPowerPro_lto.o
smState.1370x200007351ZeroLcPowerPro_lto.o
smState.1450x200007331ZeroLcPowerPro_lto.o
smState.1600x200007321ZeroLcPowerPro_lto.o
smState.1710x200007311ZeroLcPowerPro_lto.o
stderr0x20000BA044InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdin0x20000B9C44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdout0x20000B9844InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
sys_data0x200002342244ZeroLcPowerPro_lto.o
temp0x2000069044ZeroLcPowerPro_lto.o
uwTick0x2000068C44ZeroLcPowerPro_lto.o
uwTickPrio0x20000B9444InitLcPowerPro_lto.o
voltageUin0x2000068844ZeroLcPowerPro_lto.o
voltageUout0x2000068444ZeroLcPowerPro_lto.o
+

Read-write data symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
0x20000000modbusData5644ZeroLcPowerPro_lto.o
0x20000234sys_data2244ZeroLcPowerPro_lto.o
0x20000314_SEGGER_RTT1684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200003BChuart11484ZeroLcPowerPro_lto.o
0x20000450hadc11004ZeroLcPowerPro_lto.o
0x200004B4hdma_usart1_tx924ZeroLcPowerPro_lto.o
0x20000510hdma_usart1_rx924ZeroLcPowerPro_lto.o
0x2000056Chdma_adc1924ZeroLcPowerPro_lto.o
0x200005C8htim17764ZeroLcPowerPro_lto.o
0x20000614htim16764ZeroLcPowerPro_lto.o
0x20000660adcData204ZeroLcPowerPro_lto.o
0x20000674flash_device_parameter_default164ZeroLcPowerPro_lto.o
0x20000684voltageUout44ZeroLcPowerPro_lto.o
0x20000688voltageUin44ZeroLcPowerPro_lto.o
0x2000068CuwTick44ZeroLcPowerPro_lto.o
0x20000690temp44ZeroLcPowerPro_lto.o
0x20000694relais_temperature44ZeroLcPowerPro_lto.o
0x20000698onTimeCounterSET44ZeroLcPowerPro_lto.o
0x2000069ConTimeCounterRT44ZeroLcPowerPro_lto.o
0x200006A0onTimeCounterRESET44ZeroLcPowerPro_lto.o
0x200006A4onTimeCounterGN44ZeroLcPowerPro_lto.o
0x200006A8onTimeCounter44ZeroLcPowerPro_lto.o
0x200006AColdTimeMSTick44ZeroLcPowerPro_lto.o
0x200006B0offTimeCounterRT44ZeroLcPowerPro_lto.o
0x200006B4offTimeCounterGN44ZeroLcPowerPro_lto.o
0x200006B8offTimeCounter44ZeroLcPowerPro_lto.o
0x200006BCnumberOfBlinks44ZeroLcPowerPro_lto.o
0x200006C0msCounter44ZeroLcPowerPro_lto.o
0x200006C4longPressCounterButtonOn44ZeroLcPowerPro_lto.o
0x200006C8longPressCounterButtonOff44ZeroLcPowerPro_lto.o
0x200006CC__SEGGER_RTL_stdout_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
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0x200006D4__SEGGER_RTL_stderr_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
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__RAM_segment_used_start__0x20000000----Gb[ Linker created ]
__STACKSIZE_PROCESS__0x00000000----Gb[ Linker created ]
__STACKSIZE__0x00000800----Gb[ Linker created ]
__ctors_end__0x08006864----Gb[ Linker created ]
__ctors_start__0x08006860----Gb[ Linker created ]
__stack_end__0x20003000----Gb[ Linker created ]
__thread_pointer$0x00000000----Gb[ Linker created ]
_vectors0x08000000[180]256CodeGbstm32c031xx_Vectors.o
_vectors_end0x080000B4256CodeLcstm32c031xx_Vectors.o
+

Untyped symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ValueSymbol nameSizeAlignTypeBdObject File
0x00000000__thread_pointer$----Gb[ Linker created ]
0x00000000__STACKSIZE_PROCESS__----Gb[ Linker created ]
0x00000400__HEAPSIZE__----Gb[ Linker created ]
0x00000800__STACKSIZE__----Gb[ Linker created ]
0x00003000__RAM_segment_used_size__----Gb[ Linker created ]
0x00003000__RAM_segment_size__----Gb[ Linker created ]
0x00003000__RAM1_segment_used_size__----Gb[ Linker created ]
0x00003000__RAM1_segment_size__----Gb[ Linker created ]
0x00006B6E__FLASH_segment_used_size__----Gb[ Linker created ]
0x00006B6E__FLASH1_segment_used_size__----Gb[ Linker created ]
0x00007800__FLASH_segment_size__----Gb[ Linker created ]
0x00007800__FLASH1_segment_size__----Gb[ Linker created ]
0x08000000_vectors[180]256CodeGbstm32c031xx_Vectors.o
0x08000000__FLASH_segment_used_start__----Gb[ Linker created ]
0x08000000__FLASH_segment_start__----Gb[ Linker created ]
0x08000000__FLASH1_segment_used_start__----Gb[ Linker created ]
0x08000000__FLASH1_segment_start__----Gb[ Linker created ]
0x080000B4_vectors_end256CodeLcstm32c031xx_Vectors.o
0x08006860__ctors_start__----Gb[ Linker created ]
0x08006864__ctors_end__----Gb[ Linker created ]
0x08006B6E__FLASH_segment_used_end__----Gb[ Linker created ]
0x08006B6E__FLASH1_segment_used_end__----Gb[ Linker created ]
0x08007800__FLASH_segment_end__----Gb[ Linker created ]
0x08007800__FLASH1_segment_end__----Gb[ Linker created ]
0x20000000__RAM_segment_used_start__----Gb[ Linker created ]
0x20000000__RAM_segment_start__----Gb[ Linker created ]
0x20000000__RAM1_segment_used_start__----Gb[ Linker created ]
0x20000000__RAM1_segment_start__----Gb[ Linker created ]
0x20003000__stack_end__----Gb[ Linker created ]
0x20003000__RAM_segment_used_end__----Gb[ Linker created ]
0x20003000__RAM_segment_end__----Gb[ Linker created ]
0x20003000__RAM1_segment_used_end__----Gb[ Linker created ]
0x20003000__RAM1_segment_end__----Gb[ Linker created ]
+

REGION LIST

+

Regions by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSize
FLASH08000000-080077FF30 720
FLASH108000000-080077FF30 720
RAM20000000-20002FFF12 288
RAM120000000-20002FFF12 288
+

Analysis

+FLASH: + Identical to region FLASH1 + +FLASH1: + Identical to region FLASH + +RAM: + Identical to region RAM1 + +RAM1: + Identical to region RAM +

BLOCK LIST

+

Blocks by name

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSizeOrdering
ctors08006860-080068634Auto
stack20002800-20002FFF2 048Auto
vectors08000000-080000B3180Auto
+

Blocks by address

+ + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeNameOrdering
08000000-080000B3180vectorsAuto
08006860-080068634ctorsAuto
20002800-20002FFF2 048stackAuto
+

STACK SIZES

+

Functions by stack size

+ + + + + + +
Function nameStackObject File
+

Functions without stack size information

+ HAL_DMA_IRQHandler + HAL_TIM_IC_CaptureCallback + HAL_UART_ErrorCallback + UART_EndRxTransfer + UART_DMAAbortOnError + HAL_RCC_GetPCLK1Freq + HAL_InitTick + HAL_Delay + ADC_DMAConvCplt + ADC_DMAHalfConvCplt + ADC_DMAError + HAL_ADC_ConfigChannel + HAL_NVIC_SystemReset + __NVIC_SystemReset + HAL_DMA_Init + HAL_DMA_Start_IT + FLASH_WaitForLastOperation + HAL_FLASH_Unlock + HAL_GPIO_Init + HAL_RCC_GetSysClockFreq + HAL_RCCEx_PeriphCLKConfig + HAL_TIM_Base_Init + TIM_Base_SetConfig + HAL_UART_Init + UART_WaitOnFlagUntilTimeout + Error_Handler + UART_DMATransmitCplt + UART_DMATxHalfCplt + UART_DMAError + HAL_UART_Receive_DMA + UART_DMARxHalfCplt + UART_DMAReceiveCplt + UARTEx_SetNbDataToProcess + EEPROM_Write + EEPROM_WriteDefaults + EEPROM_ReadDeviceParameter + EEPROM_StoreConfig + mbCrc16 + MODE_SECONDARYPROTECTION_PLUS_Exec + MODE_SECONDARYPROTECTION_Exec + JumpToBootloader + NMI_Handler + HardFault_Handler + SVC_Handler + PendSV_Handler + SysTick_Handler + DMA1_Channel1_IRQHandler + DMA1_Channel2_3_IRQHandler + TIM16_IRQHandler + USART1_IRQHandler + SystemInit + SystemCoreClockUpdate + main + _start + __SEGGER_init_done + __startup_complete + exit + WWDG_IRQHandler + RTC_IRQHandler + FLASH_IRQHandler + RCC_IRQHandler + EXTI0_1_IRQHandler + EXTI2_3_IRQHandler + EXTI4_15_IRQHandler + DMAMUX1_IRQHandler + ADC1_IRQHandler + TIM1_BRK_UP_TRG_COM_IRQHandler + TIM1_CC_IRQHandler + TIM3_IRQHandler + TIM14_IRQHandler + TIM17_IRQHandler + I2C1_IRQHandler + SPI1_IRQHandler + USART2_IRQHandler + reset_handler + Reset_Handler + putchar + fputc + fwrite + puts + __aeabi_dmul_aux + .L__aeabi_d2uiz_fast_entry + __aeabi_fmul + __aeabi_dmul + __aeabi_ddiv + __aeabi_d2iz + __aeabi_f2uiz + __aeabi_d2uiz + __aeabi_i2d + __aeabi_ui2f + __aeabi_ui2d + __aeabi_lmul + __aeabi_idiv + __aeabi_idiv0 + __aeabi_uidiv + __aeabi_uldivmod + __SEGGER_RTL_stream_write + __SEGGER_RTL_putc + __SEGGER_RTL_prin_flush + __SEGGER_RTL_init_prin_l + vfprintf + vfprintf_l + printf + __SEGGER_RTL_vfprintf_int_nwp + __SEGGER_init_zero + __SEGGER_init_copy + __SEGGER_init_ctors + __SEGGER_RTL_X_file_stat + __SEGGER_RTL_X_file_bufsize + __SEGGER_RTL_X_file_write + _DoInit + _GetAvailWriteSpace + _WriteNoCheck + _WriteBlocking + SEGGER_RTT_WriteNoLock + SEGGER_RTT_Write + memcmp + strlen + memcpy + __aeabi_memcpy + __aeabi_memcpy4 + __aeabi_memcpy8 + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset + __SEGGER_RTL_ascii_isctype + __SEGGER_RTL_ascii_toupper + __SEGGER_RTL_ascii_tolower + __SEGGER_RTL_ascii_iswctype + __SEGGER_RTL_ascii_towupper + __SEGGER_RTL_ascii_towlower + __SEGGER_RTL_current_locale + __SEGGER_RTL_ascii_mbtowc + __SEGGER_RTL_ascii_wctomb + __SEGGER_RTL_vfprintf +

UNUSED INPUTS

+

Unused object files

+No unused object files +

ABSOLUTE LISTING

+

Section .vectors from stm32c031xx_Vectors.o, size=180, align=256

+
+
_vectors:
+  0x08000000:  20003000     DC.W       20003000               ; R_ARM_ABS32
+  0x08000004:  08005F03     DC.W       reset_handler
+  0x08000008:  08005805     DC.W       NMI_Handler
+  0x0800000C:  08005807     DC.W       HardFault_Handler
+  0x08000010:  00           DC.B       0x00                     ; '\0'
+  0x08000011:  00           DC.B       0x00                     ; '\0'
+  0x08000012:  00           DC.B       0x00                     ; '\0'
+  0x08000013:  00           DC.B       0x00                     ; '\0'
+  0x08000014:  00           DC.B       0x00                     ; '\0'
+  0x08000015:  00           DC.B       0x00                     ; '\0'
+  0x08000016:  00           DC.B       0x00                     ; '\0'
+  0x08000017:  00           DC.B       0x00                     ; '\0'
+  0x08000018:  00           DC.B       0x00                     ; '\0'
+  0x08000019:  00           DC.B       0x00                     ; '\0'
+  0x0800001A:  00           DC.B       0x00                     ; '\0'
+  0x0800001B:  00           DC.B       0x00                     ; '\0'
+  0x0800001C:  00           DC.B       0x00                     ; '\0'
+  0x0800001D:  00           DC.B       0x00                     ; '\0'
+  0x0800001E:  00           DC.B       0x00                     ; '\0'
+  0x0800001F:  00           DC.B       0x00                     ; '\0'
+  0x08000020:  00           DC.B       0x00                     ; '\0'
+  0x08000021:  00           DC.B       0x00                     ; '\0'
+  0x08000022:  00           DC.B       0x00                     ; '\0'
+  0x08000023:  00           DC.B       0x00                     ; '\0'
+  0x08000024:  00           DC.B       0x00                     ; '\0'
+  0x08000025:  00           DC.B       0x00                     ; '\0'
+  0x08000026:  00           DC.B       0x00                     ; '\0'
+  0x08000027:  00           DC.B       0x00                     ; '\0'
+  0x08000028:  00           DC.B       0x00                     ; '\0'
+  0x08000029:  00           DC.B       0x00                     ; '\0'
+  0x0800002A:  00           DC.B       0x00                     ; '\0'
+  0x0800002B:  00           DC.B       0x00                     ; '\0'
+  0x0800002C:  08005809     DC.W       SVC_Handler
+  0x08000030:  00           DC.B       0x00                     ; '\0'
+  0x08000031:  00           DC.B       0x00                     ; '\0'
+  0x08000032:  00           DC.B       0x00                     ; '\0'
+  0x08000033:  00           DC.B       0x00                     ; '\0'
+  0x08000034:  00           DC.B       0x00                     ; '\0'
+  0x08000035:  00           DC.B       0x00                     ; '\0'
+  0x08000036:  00           DC.B       0x00                     ; '\0'
+  0x08000037:  00           DC.B       0x00                     ; '\0'
+  0x08000038:  0800580B     DC.W       PendSV_Handler
+  0x0800003C:  080000B5     DC.W       SysTick_Handler
+  0x08000040:  0800589B     DC.W       WWDG_IRQHandler
+  0x08000044:  00           DC.B       0x00                     ; '\0'
+  0x08000045:  00           DC.B       0x00                     ; '\0'
+  0x08000046:  00           DC.B       0x00                     ; '\0'
+  0x08000047:  00           DC.B       0x00                     ; '\0'
+  0x08000048:  0800589D     DC.W       RTC_IRQHandler
+  0x0800004C:  0800589F     DC.W       FLASH_IRQHandler
+  0x08000050:  080058A1     DC.W       RCC_IRQHandler
+  0x08000054:  080058A3     DC.W       EXTI0_1_IRQHandler
+  0x08000058:  080058A5     DC.W       EXTI2_3_IRQHandler
+  0x0800005C:  080058A7     DC.W       EXTI4_15_IRQHandler
+  0x08000060:  00           DC.B       0x00                     ; '\0'
+  0x08000061:  00           DC.B       0x00                     ; '\0'
+  0x08000062:  00           DC.B       0x00                     ; '\0'
+  0x08000063:  00           DC.B       0x00                     ; '\0'
+  0x08000064:  080000C5     DC.W       DMA1_Channel1_IRQHandler
+  0x08000068:  080000D5     DC.W       DMA1_Channel2_3_IRQHandler
+  0x0800006C:  080058A9     DC.W       DMAMUX1_IRQHandler
+  0x08000070:  080058AB     DC.W       ADC1_IRQHandler
+  0x08000074:  080058AD     DC.W       TIM1_BRK_UP_TRG_COM_IRQHandler
+  0x08000078:  080058AF     DC.W       TIM1_CC_IRQHandler
+  0x0800007C:  00           DC.B       0x00                     ; '\0'
+  0x0800007D:  00           DC.B       0x00                     ; '\0'
+  0x0800007E:  00           DC.B       0x00                     ; '\0'
+  0x0800007F:  00           DC.B       0x00                     ; '\0'
+  0x08000080:  080058B1     DC.W       TIM3_IRQHandler
+  0x08000084:  00           DC.B       0x00                     ; '\0'
+  0x08000085:  00           DC.B       0x00                     ; '\0'
+  0x08000086:  00           DC.B       0x00                     ; '\0'
+  0x08000087:  00           DC.B       0x00                     ; '\0'
+  0x08000088:  00           DC.B       0x00                     ; '\0'
+  0x08000089:  00           DC.B       0x00                     ; '\0'
+  0x0800008A:  00           DC.B       0x00                     ; '\0'
+  0x0800008B:  00           DC.B       0x00                     ; '\0'
+  0x0800008C:  080058B3     DC.W       TIM14_IRQHandler
+  0x08000090:  00           DC.B       0x00                     ; '\0'
+  0x08000091:  00           DC.B       0x00                     ; '\0'
+  0x08000092:  00           DC.B       0x00                     ; '\0'
+  0x08000093:  00           DC.B       0x00                     ; '\0'
+  0x08000094:  080000ED     DC.W       TIM16_IRQHandler
+  0x08000098:  080058B5     DC.W       TIM17_IRQHandler
+  0x0800009C:  080058B7     DC.W       I2C1_IRQHandler
+  0x080000A0:  00           DC.B       0x00                     ; '\0'
+  0x080000A1:  00           DC.B       0x00                     ; '\0'
+  0x080000A2:  00           DC.B       0x00                     ; '\0'
+  0x080000A3:  00           DC.B       0x00                     ; '\0'
+  0x080000A4:  080058B9     DC.W       SPI1_IRQHandler
+  0x080000A8:  00           DC.B       0x00                     ; '\0'
+  0x080000A9:  00           DC.B       0x00                     ; '\0'
+  0x080000AA:  00           DC.B       0x00                     ; '\0'
+  0x080000AB:  00           DC.B       0x00                     ; '\0'
+  0x080000AC:  0800020D     DC.W       USART1_IRQHandler
+  0x080000B0:  080058BB     DC.W       USART2_IRQHandler
+
+

Section .text.SysTick_Handler from PowerPro_lto.o, size=16, align=4

+
+
SysTick_Handler:
+_vectors_end:
+  0x080000B4:  4802         LDR        R0, =uwTick              ; [PC, #8] [0x080000C0] =0x2000068C 
+  0x080000B6:  6801         LDR        R1, [R0]
+  0x080000B8:  1C49         ADDS       R1, R1, #1
+  0x080000BA:  6001         STR        R1, [R0]
+  0x080000BC:  4770         BX         LR
+  0x080000BE:  46C0         NOP
+  0x080000C0:  2000068C     DC.W       uwTick
+
+

Section .text.DMA1_Channel1_IRQHandler from PowerPro_lto.o, size=16, align=4

+
+
DMA1_Channel1_IRQHandler:
+  0x080000C4:  B580         PUSH       {R7, LR}
+  0x080000C6:  4802         LDR        R0, =hdma_adc1           ; [PC, #8] [0x080000D0] =0x2000056C 
+  0x080000C8:  F000 FD0E    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000CC:  BD80         POP        {R7, PC}
+  0x080000CE:  46C0         NOP
+  0x080000D0:  2000056C     DC.W       hdma_adc1
+
+

Section .text.DMA1_Channel2_3_IRQHandler from PowerPro_lto.o, size=24, align=4

+
+
DMA1_Channel2_3_IRQHandler:
+  0x080000D4:  B580         PUSH       {R7, LR}
+  0x080000D6:  4803         LDR        R0, =hdma_usart1_rx      ; [PC, #12] [0x080000E4] =0x20000510 
+  0x080000D8:  F000 FD06    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000DC:  4802         LDR        R0, =hdma_usart1_tx      ; [PC, #8] [0x080000E8] =0x200004B4 
+  0x080000DE:  F000 FD03    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000E2:  BD80         POP        {R7, PC}
+  0x080000E4:  20000510     DC.W       hdma_usart1_rx
+  0x080000E8:  200004B4     DC.W       hdma_usart1_tx
+
+

Section .text.TIM16_IRQHandler from PowerPro_lto.o, size=288, align=4

+
+
TIM16_IRQHandler:
+  0x080000EC:  B5F0         PUSH       {R4-R7, LR}
+  0x080000EE:  B081         SUB        SP, SP, #4
+  0x080000F0:  4C40         LDR        R4, =htim16              ; [PC, #0x0100] [0x080001F4] =0x20000614 
+  0x080000F2:  6820         LDR        R0, [R4]
+  0x080000F4:  68C6         LDR        R6, [R0, #12]
+  0x080000F6:  6907         LDR        R7, [R0, #16]
+  0x080000F8:  07B9         LSLS       R1, R7, #30
+  0x080000FA:  4D3F         LDR        R5, =0xFFFFFEFF          ; [PC, #252] [0x080001F8] 
+  0x080000FC:  D50E         BPL        .L2                      ; 0x0800011C
+  0x080000FE:  07B1         LSLS       R1, R6, #30
+  0x08000100:  D50C         BPL        .L2                      ; 0x0800011C
+  0x08000102:  4629         MOV        R1, R5
+  0x08000104:  31FE         ADDS       R1, #254
+  0x08000106:  6101         STR        R1, [R0, #16]
+  0x08000108:  2101         MOVS       R1, #1
+  0x0800010A:  7721         STRB       R1, [R4, #28]
+  0x0800010C:  6980         LDR        R0, [R0, #24]
+  0x0800010E:  0780         LSLS       R0, R0, #30
+  0x08000110:  D002         BEQ        .L1                      ; 0x08000118
+  0x08000112:  4620         MOV        R0, R4
+  0x08000114:  F000 FA52    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L1:
+  0x08000118:  2000         MOVS       R0, #0
+  0x0800011A:  7720         STRB       R0, [R4, #28]
+
.L2:
+  0x0800011C:  0778         LSLS       R0, R7, #29
+  0x0800011E:  D510         BPL        .L4                      ; 0x08000142
+  0x08000120:  0770         LSLS       R0, R6, #29
+  0x08000122:  D50E         BPL        .L4                      ; 0x08000142
+  0x08000124:  6820         LDR        R0, [R4]
+  0x08000126:  4629         MOV        R1, R5
+  0x08000128:  31FC         ADDS       R1, #252
+  0x0800012A:  6101         STR        R1, [R0, #16]
+  0x0800012C:  2102         MOVS       R1, #2
+  0x0800012E:  7721         STRB       R1, [R4, #28]
+  0x08000130:  6980         LDR        R0, [R0, #24]
+  0x08000132:  0580         LSLS       R0, R0, #22
+  0x08000134:  0F80         LSRS       R0, R0, #30
+  0x08000136:  D002         BEQ        .L3                      ; 0x0800013E
+  0x08000138:  4620         MOV        R0, R4
+  0x0800013A:  F000 FA3F    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L3:
+  0x0800013E:  2000         MOVS       R0, #0
+  0x08000140:  7720         STRB       R0, [R4, #28]
+
.L4:
+  0x08000142:  0738         LSLS       R0, R7, #28
+  0x08000144:  D50F         BPL        .L6                      ; 0x08000166
+  0x08000146:  0730         LSLS       R0, R6, #28
+  0x08000148:  D50D         BPL        .L6                      ; 0x08000166
+  0x0800014A:  6820         LDR        R0, [R4]
+  0x0800014C:  4629         MOV        R1, R5
+  0x0800014E:  31F8         ADDS       R1, #248
+  0x08000150:  6101         STR        R1, [R0, #16]
+  0x08000152:  2104         MOVS       R1, #4
+  0x08000154:  7721         STRB       R1, [R4, #28]
+  0x08000156:  69C0         LDR        R0, [R0, #28]
+  0x08000158:  0780         LSLS       R0, R0, #30
+  0x0800015A:  D002         BEQ        .L5                      ; 0x08000162
+  0x0800015C:  4620         MOV        R0, R4
+  0x0800015E:  F000 FA2D    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L5:
+  0x08000162:  2000         MOVS       R0, #0
+  0x08000164:  7720         STRB       R0, [R4, #28]
+
.L6:
+  0x08000166:  06F8         LSLS       R0, R7, #27
+  0x08000168:  D510         BPL        .L8                      ; 0x0800018C
+  0x0800016A:  06F0         LSLS       R0, R6, #27
+  0x0800016C:  D50E         BPL        .L8                      ; 0x0800018C
+  0x0800016E:  6820         LDR        R0, [R4]
+  0x08000170:  4629         MOV        R1, R5
+  0x08000172:  31F0         ADDS       R1, #240
+  0x08000174:  6101         STR        R1, [R0, #16]
+  0x08000176:  2108         MOVS       R1, #8
+  0x08000178:  7721         STRB       R1, [R4, #28]
+  0x0800017A:  69C0         LDR        R0, [R0, #28]
+  0x0800017C:  0580         LSLS       R0, R0, #22
+  0x0800017E:  0F80         LSRS       R0, R0, #30
+  0x08000180:  D002         BEQ        .L7                      ; 0x08000188
+  0x08000182:  4620         MOV        R0, R4
+  0x08000184:  F000 FA1A    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L7:
+  0x08000188:  2000         MOVS       R0, #0
+  0x0800018A:  7720         STRB       R0, [R4, #28]
+
.L8:
+  0x0800018C:  07F8         LSLS       R0, R7, #31
+  0x0800018E:  D010         BEQ        .L9                      ; 0x080001B2
+  0x08000190:  07F0         LSLS       R0, R6, #31
+  0x08000192:  D00E         BEQ        .L9                      ; 0x080001B2
+  0x08000194:  6820         LDR        R0, [R4]
+  0x08000196:  4629         MOV        R1, R5
+  0x08000198:  31FF         ADDS       R1, #255
+  0x0800019A:  6101         STR        R1, [R0, #16]
+  0x0800019C:  4917         LDR        R1, =0x40014400          ; [PC, #92] [0x080001FC] 
+  0x0800019E:  4288         CMP        R0, R1
+  0x080001A0:  D107         BNE        .L9                      ; 0x080001B2
+  0x080001A2:  4817         LDR        R0, =ic_overflows        ; [PC, #92] [0x08000200] =0x200006DC 
+  0x080001A4:  6801         LDR        R1, [R0]
+  0x080001A6:  1C49         ADDS       R1, R1, #1
+  0x080001A8:  6001         STR        R1, [R0]
+  0x080001AA:  D202         BCS        .L9                      ; 0x080001B2
+  0x080001AC:  4815         LDR        R0, =frequency           ; [PC, #84] [0x08000204] =0x200006E0 
+  0x080001AE:  2100         MOVS       R1, #0
+  0x080001B0:  6001         STR        R1, [R0]
+
.L9:
+  0x080001B2:  2041         MOVS       R0, #65
+  0x080001B4:  01C0         LSLS       R0, R0, #7
+  0x080001B6:  4207         TST        R7, R0
+  0x080001B8:  D004         BEQ        .L10                     ; 0x080001C4
+  0x080001BA:  0630         LSLS       R0, R6, #24
+  0x080001BC:  D502         BPL        .L10                     ; 0x080001C4
+  0x080001BE:  6820         LDR        R0, [R4]
+  0x080001C0:  4911         LDR        R1, =0xFFFFDF7F          ; [PC, #68] [0x08000208] 
+  0x080001C2:  6101         STR        R1, [R0, #16]
+
.L10:
+  0x080001C4:  05F8         LSLS       R0, R7, #23
+  0x080001C6:  D503         BPL        .L11                     ; 0x080001D0
+  0x080001C8:  0630         LSLS       R0, R6, #24
+  0x080001CA:  D501         BPL        .L11                     ; 0x080001D0
+  0x080001CC:  6820         LDR        R0, [R4]
+  0x080001CE:  6105         STR        R5, [R0, #16]
+
.L11:
+  0x080001D0:  0678         LSLS       R0, R7, #25
+  0x080001D2:  D505         BPL        .L12                     ; 0x080001E0
+  0x080001D4:  0670         LSLS       R0, R6, #25
+  0x080001D6:  D503         BPL        .L12                     ; 0x080001E0
+  0x080001D8:  6820         LDR        R0, [R4]
+  0x080001DA:  4629         MOV        R1, R5
+  0x080001DC:  31C0         ADDS       R1, #192
+  0x080001DE:  6101         STR        R1, [R0, #16]
+
.L12:
+  0x080001E0:  06B8         LSLS       R0, R7, #26
+  0x080001E2:  D504         BPL        .L13                     ; 0x080001EE
+  0x080001E4:  06B0         LSLS       R0, R6, #26
+  0x080001E6:  D502         BPL        .L13                     ; 0x080001EE
+  0x080001E8:  6820         LDR        R0, [R4]
+  0x080001EA:  35E0         ADDS       R5, #224
+  0x080001EC:  6105         STR        R5, [R0, #16]
+
.L13:
+  0x080001EE:  B001         ADD        SP, SP, #4
+  0x080001F0:  BDF0         POP        {R4-R7, PC}
+  0x080001F2:  46C0         NOP
+  0x080001F4:  20000614     DC.W       htim16
+  0x080001F8:  FFFFFEFF     DC.W       0xFFFFFEFF
+  0x080001FC:  40014400     DC.W       0x40014400
+  0x08000200:  200006DC     DC.W       ic_overflows
+  0x08000204:  200006E0     DC.W       frequency
+  0x08000208:  FFFFDF7F     DC.W       0xFFFFDF7F
+
+

Section .text.USART1_IRQHandler from PowerPro_lto.o, size=944, align=4

+
+
USART1_IRQHandler:
+  0x0800020C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800020E:  B085         SUB        SP, SP, #20
+  0x08000210:  4CE3         LDR        R4, =huart1              ; [PC, #0x038C] [0x080005A0] =0x200003BC 
+  0x08000212:  2101         MOVS       R1, #1
+  0x08000214:  6820         LDR        R0, [R4]
+  0x08000216:  9104         STR        R1, [SP, #16]
+  0x08000218:  02CE         LSLS       R6, R1, #11
+  0x0800021A:  69C3         LDR        R3, [R0, #28]
+  0x0800021C:  4631         MOV        R1, R6
+  0x0800021E:  310F         ADDS       R1, #15
+  0x08000220:  420B         TST        R3, R1
+  0x08000222:  6801         LDR        R1, [R0]
+  0x08000224:  6882         LDR        R2, [R0, #8]
+  0x08000226:  D067         BEQ        .L7                      ; 0x080002F8
+  0x08000228:  9603         STR        R6, [SP, #12]
+  0x0800022A:  4FDE         LDR        R7, =0x04000120          ; [PC, #0x0378] [0x080005A4] 
+  0x0800022C:  400F         ANDS       R7, R1
+  0x0800022E:  9D04         LDR        R5, [SP, #16]
+  0x08000230:  072E         LSLS       R6, R5, #28
+  0x08000232:  9602         STR        R6, [SP, #8]
+  0x08000234:  1C76         ADDS       R6, R6, #1
+  0x08000236:  4016         ANDS       R6, R2
+  0x08000238:  19F7         ADDS       R7, R6, R7
+  0x0800023A:  D066         BEQ        .L8                      ; 0x0800030A
+  0x0800023C:  07DF         LSLS       R7, R3, #31
+  0x0800023E:  D009         BEQ        .L1                      ; 0x08000254
+  0x08000240:  05CF         LSLS       R7, R1, #23
+  0x08000242:  D507         BPL        .L1                      ; 0x08000254
+  0x08000244:  6205         STR        R5, [R0, #32]
+  0x08000246:  2590         MOVS       R5, #144
+  0x08000248:  9501         STR        R5, [SP, #4]
+  0x0800024A:  5967         LDR        R7, [R4, R5]
+  0x0800024C:  9D04         LDR        R5, [SP, #16]
+  0x0800024E:  432F         ORRS       R7, R5
+  0x08000250:  9D01         LDR        R5, [SP, #4]
+  0x08000252:  5167         STR        R7, [R4, R5]
+
.L1:
+  0x08000254:  079F         LSLS       R7, R3, #30
+  0x08000256:  D50A         BPL        .L2                      ; 0x0800026E
+  0x08000258:  07D7         LSLS       R7, R2, #31
+  0x0800025A:  D008         BEQ        .L2                      ; 0x0800026E
+  0x0800025C:  2702         MOVS       R7, #2
+  0x0800025E:  6207         STR        R7, [R0, #32]
+  0x08000260:  2790         MOVS       R7, #144
+  0x08000262:  9701         STR        R7, [SP, #4]
+  0x08000264:  59E5         LDR        R5, [R4, R7]
+  0x08000266:  2704         MOVS       R7, #4
+  0x08000268:  432F         ORRS       R7, R5
+  0x0800026A:  9D01         LDR        R5, [SP, #4]
+  0x0800026C:  5167         STR        R7, [R4, R5]
+
.L2:
+  0x0800026E:  075F         LSLS       R7, R3, #29
+  0x08000270:  D50B         BPL        .L3                      ; 0x0800028A
+  0x08000272:  07D7         LSLS       R7, R2, #31
+  0x08000274:  D009         BEQ        .L3                      ; 0x0800028A
+  0x08000276:  2704         MOVS       R7, #4
+  0x08000278:  6207         STR        R7, [R0, #32]
+  0x0800027A:  2590         MOVS       R5, #144
+  0x0800027C:  9500         STR        R5, [SP, #0]
+  0x0800027E:  5965         LDR        R5, [R4, R5]
+  0x08000280:  9501         STR        R5, [SP, #4]
+  0x08000282:  2702         MOVS       R7, #2
+  0x08000284:  432F         ORRS       R7, R5
+  0x08000286:  9D00         LDR        R5, [SP, #0]
+  0x08000288:  5167         STR        R7, [R4, R5]
+
.L3:
+  0x0800028A:  071F         LSLS       R7, R3, #28
+  0x0800028C:  D509         BPL        .L4                      ; 0x080002A2
+  0x0800028E:  2720         MOVS       R7, #32
+  0x08000290:  400F         ANDS       R7, R1
+  0x08000292:  433E         ORRS       R6, R7
+  0x08000294:  D005         BEQ        .L4                      ; 0x080002A2
+  0x08000296:  2508         MOVS       R5, #8
+  0x08000298:  6205         STR        R5, [R0, #32]
+  0x0800029A:  2790         MOVS       R7, #144
+  0x0800029C:  59E6         LDR        R6, [R4, R7]
+  0x0800029E:  432E         ORRS       R6, R5
+  0x080002A0:  51E6         STR        R6, [R4, R7]
+
.L4:
+  0x080002A2:  9F03         LDR        R7, [SP, #12]
+  0x080002A4:  423B         TST        R3, R7
+  0x080002A6:  D007         BEQ        .L5                      ; 0x080002B8
+  0x080002A8:  014E         LSLS       R6, R1, #5
+  0x080002AA:  D505         BPL        .L5                      ; 0x080002B8
+  0x080002AC:  6207         STR        R7, [R0, #32]
+  0x080002AE:  2690         MOVS       R6, #144
+  0x080002B0:  59A5         LDR        R5, [R4, R6]
+  0x080002B2:  2720         MOVS       R7, #32
+  0x080002B4:  432F         ORRS       R7, R5
+  0x080002B6:  51A7         STR        R7, [R4, R6]
+
.L5:
+  0x080002B8:  2690         MOVS       R6, #144
+  0x080002BA:  59A7         LDR        R7, [R4, R6]
+  0x080002BC:  2F00         CMP        R7, #0
+  0x080002BE:  D065         BEQ        .L17                     ; 0x0800038C
+  0x080002C0:  069B         LSLS       R3, R3, #26
+  0x080002C2:  D50B         BPL        .L6                      ; 0x080002DC
+  0x080002C4:  2320         MOVS       R3, #32
+  0x080002C6:  4019         ANDS       R1, R3
+  0x080002C8:  9B02         LDR        R3, [SP, #8]
+  0x080002CA:  401A         ANDS       R2, R3
+  0x080002CC:  430A         ORRS       R2, R1
+  0x080002CE:  D005         BEQ        .L6                      ; 0x080002DC
+  0x080002D0:  6F61         LDR        R1, [R4, #116]
+  0x080002D2:  2900         CMP        R1, #0
+  0x080002D4:  D002         BEQ        .L6                      ; 0x080002DC
+  0x080002D6:  4620         MOV        R0, R4
+  0x080002D8:  4788         BLX        R1
+  0x080002DA:  6820         LDR        R0, [R4]
+
.L6:
+  0x080002DC:  59A1         LDR        R1, [R4, R6]
+  0x080002DE:  2228         MOVS       R2, #40
+  0x080002E0:  400A         ANDS       R2, R1
+  0x080002E2:  6880         LDR        R0, [R0, #8]
+  0x080002E4:  2740         MOVS       R7, #64
+  0x080002E6:  4038         ANDS       R0, R7
+  0x080002E8:  1880         ADDS       R0, R0, R2
+  0x080002EA:  4620         MOV        R0, R4
+  0x080002EC:  D13D         BNE        .L13                     ; 0x0800036A
+  0x080002EE:  F004 F95D    BL         HAL_UART_ErrorCallback   ; 0x080045AC
+  0x080002F2:  2000         MOVS       R0, #0
+  0x080002F4:  51A0         STR        R0, [R4, R6]
+  0x080002F6:  E049         B          .L17                     ; 0x0800038C
+
.L7:
+  0x080002F8:  069E         LSLS       R6, R3, #26
+  0x080002FA:  D506         BPL        .L8                      ; 0x0800030A
+  0x080002FC:  2620         MOVS       R6, #32
+  0x080002FE:  400E         ANDS       R6, R1
+  0x08000300:  9D04         LDR        R5, [SP, #16]
+  0x08000302:  072F         LSLS       R7, R5, #28
+  0x08000304:  4017         ANDS       R7, R2
+  0x08000306:  19F6         ADDS       R6, R6, R7
+  0x08000308:  D13B         BNE        .L15                     ; 0x08000382
+
.L8:
+  0x0800030A:  6EE6         LDR        R6, [R4, #108]
+  0x0800030C:  2E01         CMP        R6, #1
+  0x0800030E:  D103         BNE        .L9                      ; 0x08000318
+  0x08000310:  06DE         LSLS       R6, R3, #27
+  0x08000312:  D501         BPL        .L9                      ; 0x08000318
+  0x08000314:  06CE         LSLS       R6, R1, #27
+  0x08000316:  D43B         BMI        .L18                     ; 0x08000390
+
.L9:
+  0x08000318:  02DE         LSLS       R6, R3, #11
+  0x0800031A:  D501         BPL        .L10                     ; 0x08000320
+  0x0800031C:  0256         LSLS       R6, R2, #9
+  0x0800031E:  D420         BMI        .L12                     ; 0x08000362
+
.L10:
+  0x08000320:  0618         LSLS       R0, R3, #24
+  0x08000322:  D506         BPL        .L11                     ; 0x08000332
+  0x08000324:  2080         MOVS       R0, #128
+  0x08000326:  4008         ANDS       R0, R1
+  0x08000328:  9D04         LDR        R5, [SP, #16]
+  0x0800032A:  05EE         LSLS       R6, R5, #23
+  0x0800032C:  4032         ANDS       R2, R6
+  0x0800032E:  1880         ADDS       R0, R0, R2
+  0x08000330:  D125         BNE        .L14                     ; 0x0800037E
+
.L11:
+  0x08000332:  0658         LSLS       R0, R3, #25
+  0x08000334:  D52A         BPL        .L17                     ; 0x0800038C
+  0x08000336:  0648         LSLS       R0, R1, #25
+  0x08000338:  D528         BPL        .L17                     ; 0x0800038C
+  0x0800033A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800033E:  9904         LDR        R1, [SP, #16]
+  0x08000340:  F381 8810    MSR        PRIMASK, R1
+  0x08000344:  6821         LDR        R1, [R4]
+  0x08000346:  680A         LDR        R2, [R1]
+  0x08000348:  2340         MOVS       R3, #64
+  0x0800034A:  439A         BICS       R2, R3
+  0x0800034C:  600A         STR        R2, [R1]
+  0x0800034E:  F380 8810    MSR        PRIMASK, R0
+  0x08000352:  2088         MOVS       R0, #136
+  0x08000354:  2120         MOVS       R1, #32
+  0x08000356:  5021         STR        R1, [R4, R0]
+  0x08000358:  4897         LDR        R0, =0x20000026          ; [PC, #0x025C] [0x080005B8] 
+  0x0800035A:  2100         MOVS       R1, #0
+  0x0800035C:  7001         STRB       R1, [R0]
+  0x0800035E:  67A1         STR        R1, [R4, #120]
+  0x08000360:  E014         B          .L17                     ; 0x0800038C
+
.L12:
+  0x08000362:  9904         LDR        R1, [SP, #16]
+  0x08000364:  0509         LSLS       R1, R1, #20
+  0x08000366:  6201         STR        R1, [R0, #32]
+  0x08000368:  E010         B          .L17                     ; 0x0800038C
+
.L13:
+  0x0800036A:  F001 F899    BL         UART_EndRxTransfer       ; 0x080014A0
+  0x0800036E:  6820         LDR        R0, [R4]
+  0x08000370:  6880         LDR        R0, [R0, #8]
+  0x08000372:  0640         LSLS       R0, R0, #25
+  0x08000374:  D446         BMI        .L21                     ; 0x08000404
+  0x08000376:  4620         MOV        R0, R4
+  0x08000378:  F004 F918    BL         HAL_UART_ErrorCallback   ; 0x080045AC
+  0x0800037C:  E006         B          .L17                     ; 0x0800038C
+
.L14:
+  0x0800037E:  6FA1         LDR        R1, [R4, #120]
+  0x08000380:  E000         B          .L16                     ; 0x08000384
+
.L15:
+  0x08000382:  6F61         LDR        R1, [R4, #116]
+
.L16:
+  0x08000384:  2900         CMP        R1, #0
+  0x08000386:  D001         BEQ        .L17                     ; 0x0800038C
+  0x08000388:  4620         MOV        R0, R4
+  0x0800038A:  4788         BLX        R1
+
.L17:
+  0x0800038C:  B005         ADD        SP, SP, #20
+  0x0800038E:  BDF0         POP        {R4-R7, PC}
+
.L18:
+  0x08000390:  2110         MOVS       R1, #16
+  0x08000392:  6201         STR        R1, [R0, #32]
+  0x08000394:  6880         LDR        R0, [R0, #8]
+  0x08000396:  0640         LSLS       R0, R0, #25
+  0x08000398:  D500         BPL        .L19                     ; 0x0800039C
+  0x0800039A:  E076         B          .L25                     ; 0x0800048A
+
.L19:
+  0x0800039C:  235E         MOVS       R3, #94
+  0x0800039E:  5AE0         LDRH       R0, [R4, R3]
+  0x080003A0:  225C         MOVS       R2, #92
+  0x080003A2:  5AA2         LDRH       R2, [R4, R2]
+  0x080003A4:  5AE3         LDRH       R3, [R4, R3]
+  0x080003A6:  2B00         CMP        R3, #0
+  0x080003A8:  D0F0         BEQ        .L17                     ; 0x0800038C
+  0x080003AA:  4282         CMP        R2, R0
+  0x080003AC:  D0EE         BEQ        .L17                     ; 0x0800038C
+  0x080003AE:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003B2:  9D04         LDR        R5, [SP, #16]
+  0x080003B4:  F385 8810    MSR        PRIMASK, R5
+  0x080003B8:  4A7C         LDR        R2, =0xFFFFFEFF          ; [PC, #0x01F0] [0x080005AC] 
+  0x080003BA:  3A20         SUBS       R2, #32
+  0x080003BC:  6823         LDR        R3, [R4]
+  0x080003BE:  681E         LDR        R6, [R3]
+  0x080003C0:  4016         ANDS       R6, R2
+  0x080003C2:  601E         STR        R6, [R3]
+  0x080003C4:  F380 8810    MSR        PRIMASK, R0
+  0x080003C8:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003CC:  F385 8810    MSR        PRIMASK, R5
+  0x080003D0:  6822         LDR        R2, [R4]
+  0x080003D2:  6893         LDR        R3, [R2, #8]
+  0x080003D4:  4E77         LDR        R6, =0xEFFFFFFE          ; [PC, #0x01DC] [0x080005B4] 
+  0x080003D6:  401E         ANDS       R6, R3
+  0x080003D8:  6096         STR        R6, [R2, #8]
+  0x080003DA:  F380 8810    MSR        PRIMASK, R0
+  0x080003DE:  208C         MOVS       R0, #140
+  0x080003E0:  2220         MOVS       R2, #32
+  0x080003E2:  5022         STR        R2, [R4, R0]
+  0x080003E4:  2000         MOVS       R0, #0
+  0x080003E6:  6760         STR        R0, [R4, #116]
+  0x080003E8:  66E0         STR        R0, [R4, #108]
+  0x080003EA:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003EE:  F385 8810    MSR        PRIMASK, R5
+  0x080003F2:  6822         LDR        R2, [R4]
+  0x080003F4:  6813         LDR        R3, [R2]
+  0x080003F6:  438B         BICS       R3, R1
+  0x080003F8:  6013         STR        R3, [R2]
+  0x080003FA:  F380 8810    MSR        PRIMASK, R0
+
.L20:
+  0x080003FE:  2002         MOVS       R0, #2
+  0x08000400:  6720         STR        R0, [R4, #112]
+  0x08000402:  E7C3         B          .L17                     ; 0x0800038C
+
.L21:
+  0x08000404:  F3EF 8010    MRS        R0, PRIMASK
+  0x08000408:  9904         LDR        R1, [SP, #16]
+  0x0800040A:  F381 8810    MSR        PRIMASK, R1
+  0x0800040E:  6821         LDR        R1, [R4]
+  0x08000410:  688A         LDR        R2, [R1, #8]
+  0x08000412:  43BA         BICS       R2, R7
+  0x08000414:  608A         STR        R2, [R1, #8]
+  0x08000416:  F380 8810    MSR        PRIMASK, R0
+  0x0800041A:  2080         MOVS       R0, #128
+  0x0800041C:  5820         LDR        R0, [R4, R0]
+  0x0800041E:  2800         CMP        R0, #0
+  0x08000420:  D100         BNE        .L22                     ; 0x08000424
+  0x08000422:  E0AC         B          .L31                     ; 0x0800057E
+
.L22:
+  0x08000424:  4601         MOV        R1, R0
+  0x08000426:  3124         ADDS       R1, #36
+  0x08000428:  9A04         LDR        R2, [SP, #16]
+  0x0800042A:  700A         STRB       R2, [R1]
+  0x0800042C:  4A5E         LDR        R2, =UART_DMAAbortOnError ; [PC, #0x0178] [0x080005A8] =0x08005ED7 
+  0x0800042E:  6382         STR        R2, [R0, #56]
+  0x08000430:  784A         LDRB       R2, [R1, #1]
+  0x08000432:  2A02         CMP        R2, #2
+  0x08000434:  D000         BEQ        .L23                     ; 0x08000438
+  0x08000436:  E0A6         B          .L32                     ; 0x08000586
+
.L23:
+  0x08000438:  6802         LDR        R2, [R0]
+  0x0800043A:  6813         LDR        R3, [R2]
+  0x0800043C:  240E         MOVS       R4, #14
+  0x0800043E:  43A3         BICS       R3, R4
+  0x08000440:  6013         STR        R3, [R2]
+  0x08000442:  6813         LDR        R3, [R2]
+  0x08000444:  9D04         LDR        R5, [SP, #16]
+  0x08000446:  43AB         BICS       R3, R5
+  0x08000448:  6013         STR        R3, [R2]
+  0x0800044A:  6C43         LDR        R3, [R0, #68]
+  0x0800044C:  681C         LDR        R4, [R3]
+  0x0800044E:  4A57         LDR        R2, =0xFFFFFEFF          ; [PC, #0x015C] [0x080005AC] 
+  0x08000450:  4014         ANDS       R4, R2
+  0x08000452:  601C         STR        R4, [R3]
+  0x08000454:  6C03         LDR        R3, [R0, #64]
+  0x08000456:  241C         MOVS       R4, #28
+  0x08000458:  401C         ANDS       R4, R3
+  0x0800045A:  462B         MOV        R3, R5
+  0x0800045C:  40A3         LSLS       R3, R4
+  0x0800045E:  4C54         LDR        R4, =0x40020004          ; [PC, #0x0150] [0x080005B0] 
+  0x08000460:  6826         LDR        R6, [R4]
+  0x08000462:  431E         ORRS       R6, R3
+  0x08000464:  6026         STR        R6, [R4]
+  0x08000466:  6C83         LDR        R3, [R0, #72]
+  0x08000468:  6CC4         LDR        R4, [R0, #76]
+  0x0800046A:  605C         STR        R4, [R3, #4]
+  0x0800046C:  6D03         LDR        R3, [R0, #80]
+  0x0800046E:  2B00         CMP        R3, #0
+  0x08000470:  D005         BEQ        .L24                     ; 0x0800047E
+  0x08000472:  681C         LDR        R4, [R3]
+  0x08000474:  4014         ANDS       R4, R2
+  0x08000476:  601C         STR        R4, [R3]
+  0x08000478:  6D42         LDR        R2, [R0, #84]
+  0x0800047A:  6D83         LDR        R3, [R0, #88]
+  0x0800047C:  6053         STR        R3, [R2, #4]
+
.L24:
+  0x0800047E:  2200         MOVS       R2, #0
+  0x08000480:  700A         STRB       R2, [R1]
+  0x08000482:  704D         STRB       R5, [R1, #1]
+  0x08000484:  F005 FD27    BL         UART_DMAAbortOnError     ; 0x08005ED6
+  0x08000488:  E780         B          .L17                     ; 0x0800038C
+
.L25:
+  0x0800048A:  205C         MOVS       R0, #92
+  0x0800048C:  5A20         LDRH       R0, [R4, R0]
+  0x0800048E:  2680         MOVS       R6, #128
+  0x08000490:  59A2         LDR        R2, [R4, R6]
+  0x08000492:  6812         LDR        R2, [R2]
+  0x08000494:  6853         LDR        R3, [R2, #4]
+  0x08000496:  B29F         UXTH       R7, R3
+  0x08000498:  2F00         CMP        R7, #0
+  0x0800049A:  D068         BEQ        .L28                     ; 0x0800056E
+  0x0800049C:  4287         CMP        R7, R0
+  0x0800049E:  D266         BCS        .L28                     ; 0x0800056E
+  0x080004A0:  275E         MOVS       R7, #94
+  0x080004A2:  53E3         STRH       R3, [R4, R7]
+  0x080004A4:  6812         LDR        R2, [R2]
+  0x080004A6:  0692         LSLS       R2, R2, #26
+  0x080004A8:  D500         BPL        .L26                     ; 0x080004AC
+  0x080004AA:  E074         B          .L35                     ; 0x08000596
+
.L26:
+  0x080004AC:  F3EF 8310    MRS        R3, PRIMASK
+  0x080004B0:  9D04         LDR        R5, [SP, #16]
+  0x080004B2:  F385 8810    MSR        PRIMASK, R5
+  0x080004B6:  9703         STR        R7, [SP, #12]
+  0x080004B8:  6827         LDR        R7, [R4]
+  0x080004BA:  683A         LDR        R2, [R7]
+  0x080004BC:  483B         LDR        R0, =0xFFFFFEFF          ; [PC, #236] [0x080005AC] 
+  0x080004BE:  4002         ANDS       R2, R0
+  0x080004C0:  603A         STR        R2, [R7]
+  0x080004C2:  F383 8810    MSR        PRIMASK, R3
+  0x080004C6:  F3EF 8210    MRS        R2, PRIMASK
+  0x080004CA:  F385 8810    MSR        PRIMASK, R5
+  0x080004CE:  6823         LDR        R3, [R4]
+  0x080004D0:  689F         LDR        R7, [R3, #8]
+  0x080004D2:  43AF         BICS       R7, R5
+  0x080004D4:  609F         STR        R7, [R3, #8]
+  0x080004D6:  F382 8810    MSR        PRIMASK, R2
+  0x080004DA:  F3EF 8210    MRS        R2, PRIMASK
+  0x080004DE:  F385 8810    MSR        PRIMASK, R5
+  0x080004E2:  6823         LDR        R3, [R4]
+  0x080004E4:  689F         LDR        R7, [R3, #8]
+  0x080004E6:  2040         MOVS       R0, #64
+  0x080004E8:  4387         BICS       R7, R0
+  0x080004EA:  609F         STR        R7, [R3, #8]
+  0x080004EC:  F382 8810    MSR        PRIMASK, R2
+  0x080004F0:  208C         MOVS       R0, #140
+  0x080004F2:  2220         MOVS       R2, #32
+  0x080004F4:  5022         STR        R2, [R4, R0]
+  0x080004F6:  2300         MOVS       R3, #0
+  0x080004F8:  66E3         STR        R3, [R4, #108]
+  0x080004FA:  F3EF 8010    MRS        R0, PRIMASK
+  0x080004FE:  F385 8810    MSR        PRIMASK, R5
+  0x08000502:  6822         LDR        R2, [R4]
+  0x08000504:  6817         LDR        R7, [R2]
+  0x08000506:  438F         BICS       R7, R1
+  0x08000508:  6017         STR        R7, [R2]
+  0x0800050A:  9F03         LDR        R7, [SP, #12]
+  0x0800050C:  F380 8810    MSR        PRIMASK, R0
+  0x08000510:  59A6         LDR        R6, [R4, R6]
+  0x08000512:  2E00         CMP        R6, #0
+  0x08000514:  D03F         BEQ        .L35                     ; 0x08000596
+  0x08000516:  4631         MOV        R1, R6
+  0x08000518:  3124         ADDS       R1, #36
+  0x0800051A:  7848         LDRB       R0, [R1, #1]
+  0x0800051C:  2802         CMP        R0, #2
+  0x0800051E:  D137         BNE        .L33                     ; 0x08000590
+  0x08000520:  9302         STR        R3, [SP, #8]
+  0x08000522:  6830         LDR        R0, [R6]
+  0x08000524:  6802         LDR        R2, [R0]
+  0x08000526:  270E         MOVS       R7, #14
+  0x08000528:  43BA         BICS       R2, R7
+  0x0800052A:  6002         STR        R2, [R0]
+  0x0800052C:  6C72         LDR        R2, [R6, #68]
+  0x0800052E:  6817         LDR        R7, [R2]
+  0x08000530:  4B1E         LDR        R3, =0xFFFFFEFF          ; [PC, #120] [0x080005AC] 
+  0x08000532:  401F         ANDS       R7, R3
+  0x08000534:  6017         STR        R7, [R2]
+  0x08000536:  6802         LDR        R2, [R0]
+  0x08000538:  43AA         BICS       R2, R5
+  0x0800053A:  6002         STR        R2, [R0]
+  0x0800053C:  6C30         LDR        R0, [R6, #64]
+  0x0800053E:  221C         MOVS       R2, #28
+  0x08000540:  4002         ANDS       R2, R0
+  0x08000542:  4628         MOV        R0, R5
+  0x08000544:  4090         LSLS       R0, R2
+  0x08000546:  4A1A         LDR        R2, =0x40020004          ; [PC, #104] [0x080005B0] 
+  0x08000548:  6817         LDR        R7, [R2]
+  0x0800054A:  4307         ORRS       R7, R0
+  0x0800054C:  6017         STR        R7, [R2]
+  0x0800054E:  6CB0         LDR        R0, [R6, #72]
+  0x08000550:  6CF2         LDR        R2, [R6, #76]
+  0x08000552:  6042         STR        R2, [R0, #4]
+  0x08000554:  6D37         LDR        R7, [R6, #80]
+  0x08000556:  2F00         CMP        R7, #0
+  0x08000558:  D005         BEQ        .L27                     ; 0x08000566
+  0x0800055A:  6838         LDR        R0, [R7]
+  0x0800055C:  4018         ANDS       R0, R3
+  0x0800055E:  6038         STR        R0, [R7]
+  0x08000560:  6D70         LDR        R0, [R6, #84]
+  0x08000562:  6DB2         LDR        R2, [R6, #88]
+  0x08000564:  6042         STR        R2, [R0, #4]
+
.L27:
+  0x08000566:  704D         STRB       R5, [R1, #1]
+  0x08000568:  9F03         LDR        R7, [SP, #12]
+  0x0800056A:  9B02         LDR        R3, [SP, #8]
+  0x0800056C:  E012         B          .L34                     ; 0x08000594
+
.L28:
+  0x0800056E:  42B8         CMP        R0, R7
+  0x08000570:  D000         BEQ        .L29                     ; 0x08000574
+  0x08000572:  E70B         B          .L17                     ; 0x0800038C
+
.L29:
+  0x08000574:  6810         LDR        R0, [R2]
+  0x08000576:  0680         LSLS       R0, R0, #26
+  0x08000578:  D400         BMI        .L30                     ; 0x0800057C
+  0x0800057A:  E707         B          .L17                     ; 0x0800038C
+
.L30:
+  0x0800057C:  E73F         B          .L20                     ; 0x080003FE
+
.L31:
+  0x0800057E:  4808         LDR        R0, =huart1              ; [PC, #32] [0x080005A0] =0x200003BC 
+  0x08000580:  F004 F814    BL         HAL_UART_ErrorCallback   ; 0x080045AC
+  0x08000584:  E702         B          .L17                     ; 0x0800038C
+
.L32:
+  0x08000586:  2104         MOVS       R1, #4
+  0x08000588:  63C1         STR        R1, [R0, #60]
+  0x0800058A:  F005 FCA4    BL         UART_DMAAbortOnError     ; 0x08005ED6
+  0x0800058E:  E6FD         B          .L17                     ; 0x0800038C
+
.L33:
+  0x08000590:  2004         MOVS       R0, #4
+  0x08000592:  63F0         STR        R0, [R6, #60]
+
.L34:
+  0x08000594:  700B         STRB       R3, [R1]
+
.L35:
+  0x08000596:  2002         MOVS       R0, #2
+  0x08000598:  6720         STR        R0, [R4, #112]
+  0x0800059A:  5BE0         LDRH       R0, [R4, R7]
+  0x0800059C:  E6F6         B          .L17                     ; 0x0800038C
+  0x0800059E:  46C0         NOP
+  0x080005A0:  200003BC     DC.W       huart1
+  0x080005A4:  04000120     DC.W       0x04000120
+  0x080005A8:  08005ED7     DC.W       UART_DMAAbortOnError
+  0x080005AC:  FFFFFEFF     DC.W       0xFFFFFEFF
+  0x080005B0:  40020004     DC.W       0x40020004
+  0x080005B4:  EFFFFFFE     DC.W       0xEFFFFFFE
+  0x080005B8:  20000026     DC.W       20000026               ; R_ARM_ABS32
+
+

Section .text.HAL_TIM_IC_CaptureCallback from PowerPro_lto.o, size=56, align=4

+
+
HAL_TIM_IC_CaptureCallback:
+  0x080005BC:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080005BE:  4605         MOV        R5, R0
+  0x080005C0:  7F00         LDRB       R0, [R0, #28]
+  0x080005C2:  2801         CMP        R0, #1
+  0x080005C4:  D111         BNE        .L1                      ; 0x080005EA
+  0x080005C6:  6828         LDR        R0, [R5]
+  0x080005C8:  6B44         LDR        R4, [R0, #52]
+  0x080005CA:  F000 FBFF    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x080005CE:  4907         LDR        R1, =ic_overflows        ; [PC, #28] [0x080005EC] =0x200006DC 
+  0x080005D0:  2200         MOVS       R2, #0
+  0x080005D2:  600A         STR        R2, [R1]
+  0x080005D4:  6829         LDR        R1, [R5]
+  0x080005D6:  6A8B         LDR        R3, [R1, #40]
+  0x080005D8:  624A         STR        R2, [R1, #36]
+  0x080005DA:  1C59         ADDS       R1, R3, #1
+  0x080005DC:  F005 FD51    BL         __aeabi_uidiv            ; 0x08006082
+  0x080005E0:  4621         MOV        R1, R4
+  0x080005E2:  F005 FD4E    BL         __aeabi_uidiv            ; 0x08006082
+  0x080005E6:  4902         LDR        R1, =frequency           ; [PC, #8] [0x080005F0] =0x200006E0 
+  0x080005E8:  6008         STR        R0, [R1]
+
.L1:
+  0x080005EA:  BDB0         POP        {R4-R5, R7, PC}
+  0x080005EC:  200006DC     DC.W       ic_overflows
+  0x080005F0:  200006E0     DC.W       frequency
+
+

Section .text.SystemInit from PowerPro_lto.o, size=16, align=4

+
+
SystemInit:
+  0x080005F4:  2001         MOVS       R0, #1
+  0x080005F6:  06C0         LSLS       R0, R0, #27
+  0x080005F8:  4901         LDR        R1, =0xE000ED08          ; [PC, #4] [0x08000600] 
+  0x080005FA:  6008         STR        R0, [R1]
+  0x080005FC:  4770         BX         LR
+  0x080005FE:  46C0         NOP
+  0x08000600:  E000ED08     DC.W       0xE000ED08
+
+

Section .text.SystemCoreClockUpdate from PowerPro_lto.o, size=80, align=4

+
+
SystemCoreClockUpdate:
+  0x08000604:  490F         LDR        R1, =0x40021000          ; [PC, #60] [0x08000644] 
+  0x08000606:  6888         LDR        R0, [R1, #8]
+  0x08000608:  0680         LSLS       R0, R0, #26
+  0x0800060A:  0F42         LSRS       R2, R0, #29
+  0x0800060C:  480E         LDR        R0, =0x02DC6C00          ; [PC, #56] [0x08000648] 
+  0x0800060E:  2A01         CMP        R2, #1
+  0x08000610:  D00D         BEQ        .L3                      ; 0x0800062E
+  0x08000612:  2A04         CMP        R2, #4
+  0x08000614:  D004         BEQ        .L1                      ; 0x08000620
+  0x08000616:  2A03         CMP        R2, #3
+  0x08000618:  D105         BNE        .L2                      ; 0x08000626
+  0x0800061A:  207D         MOVS       R0, #125
+  0x0800061C:  0200         LSLS       R0, R0, #8
+  0x0800061E:  E006         B          .L3                      ; 0x0800062E
+
.L1:
+  0x08000620:  2001         MOVS       R0, #1
+  0x08000622:  03C0         LSLS       R0, R0, #15
+  0x08000624:  E003         B          .L3                      ; 0x0800062E
+
.L2:
+  0x08000626:  680A         LDR        R2, [R1]
+  0x08000628:  0492         LSLS       R2, R2, #18
+  0x0800062A:  0F52         LSRS       R2, R2, #29
+  0x0800062C:  40D0         LSRS       R0, R2
+
.L3:
+  0x0800062E:  4A07         LDR        R2, =SystemCoreClock     ; [PC, #28] [0x0800064C] =0x20000BA4 
+  0x08000630:  6010         STR        R0, [R2]
+  0x08000632:  6889         LDR        R1, [R1, #8]
+  0x08000634:  0989         LSRS       R1, R1, #6
+  0x08000636:  233C         MOVS       R3, #60
+  0x08000638:  400B         ANDS       R3, R1
+  0x0800063A:  4905         LDR        R1, =AHBPrescTable       ; [PC, #20] [0x08000650] =0x0800515C 
+  0x0800063C:  58C9         LDR        R1, [R1, R3]
+  0x0800063E:  40C8         LSRS       R0, R1
+  0x08000640:  6010         STR        R0, [R2]
+  0x08000642:  4770         BX         LR
+  0x08000644:  40021000     DC.W       0x40021000
+  0x08000648:  02DC6C00     DC.W       0x02DC6C00
+  0x0800064C:  20000BA4     DC.W       SystemCoreClock
+  0x08000650:  0800515C     DC.W       AHBPrescTable
+
+

Section .text.HAL_InitTick from PowerPro_lto.o, size=96, align=4

+
+
HAL_InitTick:
+  0x08000654:  B5F0         PUSH       {R4-R7, LR}
+  0x08000656:  B081         SUB        SP, SP, #4
+  0x08000658:  4604         MOV        R4, R0
+  0x0800065A:  4811         LDR        R0, =SystemCoreClock     ; [PC, #68] [0x080006A0] =0x20000BA4 
+  0x0800065C:  6800         LDR        R0, [R0]
+  0x0800065E:  217D         MOVS       R1, #125
+  0x08000660:  00C9         LSLS       R1, R1, #3
+  0x08000662:  F005 FD0E    BL         __aeabi_uidiv            ; 0x08006082
+  0x08000666:  1E42         SUBS       R2, R0, #1
+  0x08000668:  2001         MOVS       R0, #1
+  0x0800066A:  0E11         LSRS       R1, R2, #24
+  0x0800066C:  D116         BNE        .L1                      ; 0x0800069C
+  0x0800066E:  490D         LDR        R1, =0x00FFFFFF          ; [PC, #52] [0x080006A4] 
+  0x08000670:  4E0D         LDR        R6, =0xE000E010          ; [PC, #52] [0x080006A8] 
+  0x08000672:  6072         STR        R2, [R6, #4]
+  0x08000674:  4A0D         LDR        R2, =0xE000ED20          ; [PC, #52] [0x080006AC] 
+  0x08000676:  6813         LDR        R3, [R2]
+  0x08000678:  400B         ANDS       R3, R1
+  0x0800067A:  2503         MOVS       R5, #3
+  0x0800067C:  07AD         LSLS       R5, R5, #30
+  0x0800067E:  195B         ADDS       R3, R3, R5
+  0x08000680:  6013         STR        R3, [R2]
+  0x08000682:  2300         MOVS       R3, #0
+  0x08000684:  60B3         STR        R3, [R6, #8]
+  0x08000686:  2707         MOVS       R7, #7
+  0x08000688:  6037         STR        R7, [R6]
+  0x0800068A:  2C03         CMP        R4, #3
+  0x0800068C:  D806         BHI        .L1                      ; 0x0800069C
+  0x0800068E:  6810         LDR        R0, [R2]
+  0x08000690:  4008         ANDS       R0, R1
+  0x08000692:  4328         ORRS       R0, R5
+  0x08000694:  6010         STR        R0, [R2]
+  0x08000696:  4806         LDR        R0, =uwTickPrio          ; [PC, #24] [0x080006B0] =0x20000B94 
+  0x08000698:  6004         STR        R4, [R0]
+  0x0800069A:  2000         MOVS       R0, #0
+
.L1:
+  0x0800069C:  B001         ADD        SP, SP, #4
+  0x0800069E:  BDF0         POP        {R4-R7, PC}
+  0x080006A0:  20000BA4     DC.W       SystemCoreClock
+  0x080006A4:  00FFFFFF     DC.W       0x00FFFFFF
+  0x080006A8:  E000E010     DC.W       0xE000E010
+  0x080006AC:  E000ED20     DC.W       0xE000ED20
+  0x080006B0:  20000B94     DC.W       uwTickPrio
+
+

Section .text.HAL_Delay from PowerPro_lto.o, size=20, align=4

+
+
HAL_Delay:
+  0x080006B4:  4903         LDR        R1, =uwTick              ; [PC, #12] [0x080006C4] =0x2000068C 
+  0x080006B6:  680A         LDR        R2, [R1]
+
.L1:
+  0x080006B8:  680B         LDR        R3, [R1]
+  0x080006BA:  1A9B         SUBS       R3, R3, R2
+  0x080006BC:  4283         CMP        R3, R0
+  0x080006BE:  D9FB         BLS        .L1                      ; 0x080006B8
+  0x080006C0:  4770         BX         LR
+  0x080006C2:  46C0         NOP
+  0x080006C4:  2000068C     DC.W       uwTick
+
+

Section .text.HAL_ADC_ConfigChannel from PowerPro_lto.o, size=608, align=4

+
+
HAL_ADC_ConfigChannel:
+  0x080006C8:  B5F0         PUSH       {R4-R7, LR}
+  0x080006CA:  B089         SUB        SP, SP, #36
+  0x080006CC:  2500         MOVS       R5, #0
+  0x080006CE:  9508         STR        R5, [SP, #32]
+  0x080006D0:  2654         MOVS       R6, #84
+  0x080006D2:  4F8C         LDR        R7, =hadc1               ; [PC, #0x0230] [0x08000904] =0x20000450 
+  0x080006D4:  5DB9         LDRB       R1, [R7, R6]
+  0x080006D6:  2901         CMP        R1, #1
+  0x080006D8:  D101         BNE        .L1                      ; 0x080006DE
+  0x080006DA:  2402         MOVS       R4, #2
+  0x080006DC:  E102         B          .L38                     ; 0x080008E4
+
.L1:
+  0x080006DE:  2401         MOVS       R4, #1
+  0x080006E0:  55BC         STRB       R4, [R7, R6]
+  0x080006E2:  6839         LDR        R1, [R7]
+  0x080006E4:  688A         LDR        R2, [R1, #8]
+  0x080006E6:  0752         LSLS       R2, R2, #29
+  0x080006E8:  D422         BMI        .L5                      ; 0x08000730
+  0x080006EA:  9507         STR        R5, [SP, #28]
+  0x080006EC:  693B         LDR        R3, [R7, #16]
+  0x080006EE:  6844         LDR        R4, [R0, #4]
+  0x080006F0:  2C02         CMP        R4, #2
+  0x080006F2:  4D86         LDR        R5, =0x80000004          ; [PC, #0x0218] [0x0800090C] 
+  0x080006F4:  D121         BNE        .L6                      ; 0x0800073A
+  0x080006F6:  2204         MOVS       R2, #4
+  0x080006F8:  4313         ORRS       R3, R2
+  0x080006FA:  42AB         CMP        R3, R5
+  0x080006FC:  6802         LDR        R2, [R0]
+  0x080006FE:  D106         BNE        .L2                      ; 0x0800070E
+  0x08000700:  4881         LDR        R0, =0x007FFFFF          ; [PC, #0x0204] [0x08000908] 
+  0x08000702:  43C0         MVNS       R0, R0
+  0x08000704:  43D3         MVNS       R3, R2
+  0x08000706:  4303         ORRS       R3, R0
+  0x08000708:  6A88         LDR        R0, [R1, #40]
+  0x0800070A:  4018         ANDS       R0, R3
+  0x0800070C:  6288         STR        R0, [R1, #40]
+
.L2:
+  0x0800070E:  9D07         LDR        R5, [SP, #28]
+  0x08000710:  2400         MOVS       R4, #0
+  0x08000712:  2A00         CMP        R2, #0
+  0x08000714:  D400         BMI        .L3                      ; 0x08000718
+  0x08000716:  E0E4         B          .L37                     ; 0x080008E2
+
.L3:
+  0x08000718:  487E         LDR        R0, =0x40012708          ; [PC, #0x01F8] [0x08000914] 
+  0x0800071A:  6801         LDR        R1, [R0]
+  0x0800071C:  4B7F         LDR        R3, =0xA8000400          ; [PC, #0x01FC] [0x0800091C] 
+  0x0800071E:  429A         CMP        R2, R3
+  0x08000720:  D064         BEQ        .L14                     ; 0x080007EC
+  0x08000722:  4B7D         LDR        R3, =0xA4000200          ; [PC, #0x01F4] [0x08000918] 
+  0x08000724:  429A         CMP        R2, R3
+  0x08000726:  D000         BEQ        .L4                      ; 0x0800072A
+  0x08000728:  E0DB         B          .L37                     ; 0x080008E2
+
.L4:
+  0x0800072A:  2201         MOVS       R2, #1
+  0x0800072C:  0592         LSLS       R2, R2, #22
+  0x0800072E:  E05F         B          .L15                     ; 0x080007F0
+
.L5:
+  0x08000730:  6DB8         LDR        R0, [R7, #88]
+  0x08000732:  2120         MOVS       R1, #32
+  0x08000734:  4301         ORRS       R1, R0
+  0x08000736:  65B9         STR        R1, [R7, #88]
+  0x08000738:  E0D3         B          .L37                     ; 0x080008E2
+
.L6:
+  0x0800073A:  2204         MOVS       R2, #4
+  0x0800073C:  4313         ORRS       R3, R2
+  0x0800073E:  42AB         CMP        R3, R5
+  0x08000740:  4D71         LDR        R5, =0x007FFFFF          ; [PC, #0x01C4] [0x08000908] 
+  0x08000742:  6803         LDR        R3, [R0]
+  0x08000744:  D105         BNE        .L7                      ; 0x08000752
+  0x08000746:  461A         MOV        R2, R3
+  0x08000748:  402A         ANDS       R2, R5
+  0x0800074A:  6A8C         LDR        R4, [R1, #40]
+  0x0800074C:  4314         ORRS       R4, R2
+  0x0800074E:  628C         STR        R4, [R1, #40]
+  0x08000750:  E087         B          .L33                     ; 0x08000862
+
.L7:
+  0x08000752:  9604         STR        R6, [SP, #16]
+  0x08000754:  9201         STR        R2, [SP, #4]
+  0x08000756:  4622         MOV        R2, R4
+  0x08000758:  241F         MOVS       R4, #31
+  0x0800075A:  9205         STR        R2, [SP, #20]
+  0x0800075C:  4014         ANDS       R4, R2
+  0x0800075E:  220F         MOVS       R2, #15
+  0x08000760:  9200         STR        R2, [SP, #0]
+  0x08000762:  9406         STR        R4, [SP, #24]
+  0x08000764:  40A2         LSLS       R2, R4
+  0x08000766:  6E3C         LDR        R4, [R7, #96]
+  0x08000768:  9203         STR        R2, [SP, #12]
+  0x0800076A:  4394         BICS       R4, R2
+  0x0800076C:  422B         TST        R3, R5
+  0x0800076E:  9402         STR        R4, [SP, #8]
+  0x08000770:  9E05         LDR        R6, [SP, #20]
+  0x08000772:  D045         BEQ        .L16                     ; 0x08000800
+  0x08000774:  4622         MOV        R2, R4
+  0x08000776:  07DD         LSLS       R5, R3, #31
+  0x08000778:  9D07         LDR        R5, [SP, #28]
+  0x0800077A:  D15F         BNE        .L31                     ; 0x0800083C
+  0x0800077C:  079D         LSLS       R5, R3, #30
+  0x0800077E:  D443         BMI        .L17                     ; 0x08000808
+  0x08000780:  075D         LSLS       R5, R3, #29
+  0x08000782:  D443         BMI        .L18                     ; 0x0800080C
+  0x08000784:  071D         LSLS       R5, R3, #28
+  0x08000786:  D443         BMI        .L19                     ; 0x08000810
+  0x08000788:  06DD         LSLS       R5, R3, #27
+  0x0800078A:  9D01         LDR        R5, [SP, #4]
+  0x0800078C:  D456         BMI        .L31                     ; 0x0800083C
+  0x0800078E:  069A         LSLS       R2, R3, #26
+  0x08000790:  D440         BMI        .L20                     ; 0x08000814
+  0x08000792:  065A         LSLS       R2, R3, #25
+  0x08000794:  D440         BMI        .L21                     ; 0x08000818
+  0x08000796:  061A         LSLS       R2, R3, #24
+  0x08000798:  D440         BMI        .L22                     ; 0x0800081C
+  0x0800079A:  05DA         LSLS       R2, R3, #23
+  0x0800079C:  D440         BMI        .L23                     ; 0x08000820
+  0x0800079E:  059A         LSLS       R2, R3, #22
+  0x080007A0:  D440         BMI        .L24                     ; 0x08000824
+  0x080007A2:  055A         LSLS       R2, R3, #21
+  0x080007A4:  D440         BMI        .L25                     ; 0x08000828
+  0x080007A6:  051A         LSLS       R2, R3, #20
+  0x080007A8:  D440         BMI        .L26                     ; 0x0800082C
+  0x080007AA:  04DA         LSLS       R2, R3, #19
+  0x080007AC:  D440         BMI        .L27                     ; 0x08000830
+  0x080007AE:  049A         LSLS       R2, R3, #18
+  0x080007B0:  D440         BMI        .L28                     ; 0x08000834
+  0x080007B2:  045A         LSLS       R2, R3, #17
+  0x080007B4:  D440         BMI        .L29                     ; 0x08000838
+  0x080007B6:  041A         LSLS       R2, R3, #16
+  0x080007B8:  9D00         LDR        R5, [SP, #0]
+  0x080007BA:  9A02         LDR        R2, [SP, #8]
+  0x080007BC:  D43E         BMI        .L31                     ; 0x0800083C
+  0x080007BE:  03DA         LSLS       R2, R3, #15
+  0x080007C0:  D500         BPL        .L8                      ; 0x080007C4
+  0x080007C2:  E092         B          .L39                     ; 0x080008EA
+
.L8:
+  0x080007C4:  039A         LSLS       R2, R3, #14
+  0x080007C6:  D500         BPL        .L9                      ; 0x080007CA
+  0x080007C8:  E091         B          .L40                     ; 0x080008EE
+
.L9:
+  0x080007CA:  035A         LSLS       R2, R3, #13
+  0x080007CC:  D500         BPL        .L10                     ; 0x080007D0
+  0x080007CE:  E090         B          .L41                     ; 0x080008F2
+
.L10:
+  0x080007D0:  031A         LSLS       R2, R3, #12
+  0x080007D2:  D500         BPL        .L11                     ; 0x080007D6
+  0x080007D4:  E08F         B          .L42                     ; 0x080008F6
+
.L11:
+  0x080007D6:  02DA         LSLS       R2, R3, #11
+  0x080007D8:  D500         BPL        .L12                     ; 0x080007DC
+  0x080007DA:  E08E         B          .L43                     ; 0x080008FA
+
.L12:
+  0x080007DC:  029A         LSLS       R2, R3, #10
+  0x080007DE:  D500         BPL        .L13                     ; 0x080007E2
+  0x080007E0:  E08D         B          .L44                     ; 0x080008FE
+
.L13:
+  0x080007E2:  025A         LSLS       R2, R3, #9
+  0x080007E4:  17D2         ASRS       R2, R2, #31
+  0x080007E6:  2516         MOVS       R5, #22
+  0x080007E8:  4015         ANDS       R5, R2
+  0x080007EA:  E026         B          .L30                     ; 0x0800083A
+
.L14:
+  0x080007EC:  4A46         LDR        R2, =0x007FFFFF          ; [PC, #0x0118] [0x08000908] 
+  0x080007EE:  1C52         ADDS       R2, R2, #1
+
.L15:
+  0x080007F0:  4011         ANDS       R1, R2
+  0x080007F2:  2203         MOVS       R2, #3
+  0x080007F4:  0592         LSLS       R2, R2, #22
+  0x080007F6:  6803         LDR        R3, [R0]
+  0x080007F8:  4393         BICS       R3, R2
+  0x080007FA:  1859         ADDS       R1, R3, R1
+  0x080007FC:  6001         STR        R1, [R0]
+  0x080007FE:  E070         B          .L37                     ; 0x080008E2
+
.L16:
+  0x08000800:  005A         LSLS       R2, R3, #1
+  0x08000802:  0ED5         LSRS       R5, R2, #27
+  0x08000804:  4622         MOV        R2, R4
+  0x08000806:  E019         B          .L31                     ; 0x0800083C
+
.L17:
+  0x08000808:  2501         MOVS       R5, #1
+  0x0800080A:  E017         B          .L31                     ; 0x0800083C
+
.L18:
+  0x0800080C:  2502         MOVS       R5, #2
+  0x0800080E:  E015         B          .L31                     ; 0x0800083C
+
.L19:
+  0x08000810:  2503         MOVS       R5, #3
+  0x08000812:  E013         B          .L31                     ; 0x0800083C
+
.L20:
+  0x08000814:  2505         MOVS       R5, #5
+  0x08000816:  E010         B          .L30                     ; 0x0800083A
+
.L21:
+  0x08000818:  2506         MOVS       R5, #6
+  0x0800081A:  E00E         B          .L30                     ; 0x0800083A
+
.L22:
+  0x0800081C:  2507         MOVS       R5, #7
+  0x0800081E:  E00C         B          .L30                     ; 0x0800083A
+
.L23:
+  0x08000820:  2508         MOVS       R5, #8
+  0x08000822:  E00A         B          .L30                     ; 0x0800083A
+
.L24:
+  0x08000824:  2509         MOVS       R5, #9
+  0x08000826:  E008         B          .L30                     ; 0x0800083A
+
.L25:
+  0x08000828:  250A         MOVS       R5, #10
+  0x0800082A:  E006         B          .L30                     ; 0x0800083A
+
.L26:
+  0x0800082C:  250B         MOVS       R5, #11
+  0x0800082E:  E004         B          .L30                     ; 0x0800083A
+
.L27:
+  0x08000830:  250C         MOVS       R5, #12
+  0x08000832:  E002         B          .L30                     ; 0x0800083A
+
.L28:
+  0x08000834:  250D         MOVS       R5, #13
+  0x08000836:  E000         B          .L30                     ; 0x0800083A
+
.L29:
+  0x08000838:  250E         MOVS       R5, #14
+
.L30:
+  0x0800083A:  9A02         LDR        R2, [SP, #8]
+
.L31:
+  0x0800083C:  9C06         LDR        R4, [SP, #24]
+  0x0800083E:  40A5         LSLS       R5, R4
+  0x08000840:  4315         ORRS       R5, R2
+  0x08000842:  663D         STR        R5, [R7, #96]
+  0x08000844:  08B2         LSRS       R2, R6, #2
+  0x08000846:  69FC         LDR        R4, [R7, #28]
+  0x08000848:  4294         CMP        R4, R2
+  0x0800084A:  D909         BLS        .L32                     ; 0x08000860
+  0x0800084C:  9A03         LDR        R2, [SP, #12]
+  0x0800084E:  43D2         MVNS       R2, R2
+  0x08000850:  6A8C         LDR        R4, [R1, #40]
+  0x08000852:  4014         ANDS       R4, R2
+  0x08000854:  009A         LSLS       R2, R3, #2
+  0x08000856:  0F12         LSRS       R2, R2, #28
+  0x08000858:  9D06         LDR        R5, [SP, #24]
+  0x0800085A:  40AA         LSLS       R2, R5
+  0x0800085C:  4322         ORRS       R2, R4
+  0x0800085E:  628A         STR        R2, [R1, #40]
+
.L32:
+  0x08000860:  9E04         LDR        R6, [SP, #16]
+
.L33:
+  0x08000862:  9D07         LDR        R5, [SP, #28]
+  0x08000864:  021A         LSLS       R2, R3, #8
+  0x08000866:  694C         LDR        R4, [R1, #20]
+  0x08000868:  4394         BICS       R4, R2
+  0x0800086A:  6880         LDR        R0, [R0, #8]
+  0x0800086C:  4010         ANDS       R0, R2
+  0x0800086E:  4A28         LDR        R2, =0x7FFFFF00          ; [PC, #160] [0x08000910] 
+  0x08000870:  4002         ANDS       R2, R0
+  0x08000872:  4322         ORRS       R2, R4
+  0x08000874:  614A         STR        R2, [R1, #20]
+  0x08000876:  2400         MOVS       R4, #0
+  0x08000878:  2B00         CMP        R3, #0
+  0x0800087A:  D532         BPL        .L37                     ; 0x080008E2
+  0x0800087C:  2003         MOVS       R0, #3
+  0x0800087E:  0582         LSLS       R2, R0, #22
+  0x08000880:  4824         LDR        R0, =0x40012708          ; [PC, #144] [0x08000914] 
+  0x08000882:  6805         LDR        R5, [R0]
+  0x08000884:  4629         MOV        R1, R5
+  0x08000886:  4011         ANDS       R1, R2
+  0x08000888:  4823         LDR        R0, =0xA4000200          ; [PC, #140] [0x08000918] 
+  0x0800088A:  4283         CMP        R3, R0
+  0x0800088C:  D11B         BNE        .L35                     ; 0x080008C6
+  0x0800088E:  481E         LDR        R0, =0x007FFFFF          ; [PC, #120] [0x08000908] 
+  0x08000890:  1C40         ADDS       R0, R0, #1
+  0x08000892:  4281         CMP        R1, R0
+  0x08000894:  D217         BCS        .L35                     ; 0x080008C6
+  0x08000896:  4B1F         LDR        R3, =0x40012708          ; [PC, #124] [0x08000914] 
+  0x08000898:  6818         LDR        R0, [R3]
+  0x0800089A:  4390         BICS       R0, R2
+  0x0800089C:  4301         ORRS       R1, R0
+  0x0800089E:  481A         LDR        R0, =0x007FFFFF          ; [PC, #104] [0x08000908] 
+  0x080008A0:  1840         ADDS       R0, R0, R1
+  0x080008A2:  1C40         ADDS       R0, R0, #1
+  0x080008A4:  6018         STR        R0, [R3]
+  0x080008A6:  481E         LDR        R0, =SystemCoreClock     ; [PC, #120] [0x08000920] =0x20000BA4 
+  0x080008A8:  6800         LDR        R0, [R0]
+  0x080008AA:  491E         LDR        R1, =0x00030D40          ; [PC, #120] [0x08000924] 
+  0x080008AC:  F005 FBE9    BL         __aeabi_uidiv            ; 0x08006082
+  0x080008B0:  210C         MOVS       R1, #12
+  0x080008B2:  4341         MULS       R1, R0, R1
+  0x080008B4:  1C48         ADDS       R0, R1, #1
+  0x080008B6:  9D07         LDR        R5, [SP, #28]
+
.L34:
+  0x080008B8:  9008         STR        R0, [SP, #32]
+  0x080008BA:  9808         LDR        R0, [SP, #32]
+  0x080008BC:  2800         CMP        R0, #0
+  0x080008BE:  D010         BEQ        .L37                     ; 0x080008E2
+  0x080008C0:  9808         LDR        R0, [SP, #32]
+  0x080008C2:  1E40         SUBS       R0, R0, #1
+  0x080008C4:  E7F8         B          .L34                     ; 0x080008B8
+
.L35:
+  0x080008C6:  4815         LDR        R0, =0xA8000400          ; [PC, #84] [0x0800091C] 
+  0x080008C8:  4283         CMP        R3, R0
+  0x080008CA:  D109         BNE        .L36                     ; 0x080008E0
+  0x080008CC:  2001         MOVS       R0, #1
+  0x080008CE:  0583         LSLS       R3, R0, #22
+  0x080008D0:  401D         ANDS       R5, R3
+  0x080008D2:  D105         BNE        .L36                     ; 0x080008E0
+  0x080008D4:  4D0F         LDR        R5, =0x40012708          ; [PC, #60] [0x08000914] 
+  0x080008D6:  6828         LDR        R0, [R5]
+  0x080008D8:  4390         BICS       R0, R2
+  0x080008DA:  4301         ORRS       R1, R0
+  0x080008DC:  4319         ORRS       R1, R3
+  0x080008DE:  6029         STR        R1, [R5]
+
.L36:
+  0x080008E0:  9D07         LDR        R5, [SP, #28]
+
.L37:
+  0x080008E2:  55BD         STRB       R5, [R7, R6]
+
.L38:
+  0x080008E4:  4620         MOV        R0, R4
+  0x080008E6:  B009         ADD        SP, SP, #36
+  0x080008E8:  BDF0         POP        {R4-R7, PC}
+
.L39:
+  0x080008EA:  2510         MOVS       R5, #16
+  0x080008EC:  E7A5         B          .L30                     ; 0x0800083A
+
.L40:
+  0x080008EE:  2511         MOVS       R5, #17
+  0x080008F0:  E7A3         B          .L30                     ; 0x0800083A
+
.L41:
+  0x080008F2:  2512         MOVS       R5, #18
+  0x080008F4:  E7A1         B          .L30                     ; 0x0800083A
+
.L42:
+  0x080008F6:  2513         MOVS       R5, #19
+  0x080008F8:  E79F         B          .L30                     ; 0x0800083A
+
.L43:
+  0x080008FA:  2514         MOVS       R5, #20
+  0x080008FC:  E79D         B          .L30                     ; 0x0800083A
+
.L44:
+  0x080008FE:  2515         MOVS       R5, #21
+  0x08000900:  E79B         B          .L30                     ; 0x0800083A
+  0x08000902:  46C0         NOP
+  0x08000904:  20000450     DC.W       hadc1
+  0x08000908:  007FFFFF     DC.W       0x007FFFFF
+  0x0800090C:  80000004     DC.W       0x80000004
+  0x08000910:  7FFFFF00     DC.W       0x7FFFFF00
+  0x08000914:  40012708     DC.W       0x40012708
+  0x08000918:  A4000200     DC.W       0xA4000200
+  0x0800091C:  A8000400     DC.W       0xA8000400
+  0x08000920:  20000BA4     DC.W       SystemCoreClock
+  0x08000924:  00030D40     DC.W       0x00030D40
+
+

Section .text.__NVIC_SystemReset from PowerPro_lto.o, size=28, align=4

+
+
__NVIC_SystemReset:
+  0x08000928:  F3BF 8F4F    DSB        SY
+  0x0800092C:  4803         LDR        R0, =0xE000ED0C          ; [PC, #12] [0x0800093C] 
+  0x0800092E:  4904         LDR        R1, =0x05FA0004          ; [PC, #16] [0x08000940] 
+  0x08000930:  6001         STR        R1, [R0]
+  0x08000932:  F3BF 8F4F    DSB        SY
+
.L1:
+  0x08000936:  BF00         NOP
+  0x08000938:  E7FD         B          .L1                      ; 0x08000936
+  0x0800093A:  46C0         NOP
+  0x0800093C:  E000ED0C     DC.W       0xE000ED0C
+  0x08000940:  05FA0004     DC.W       0x05FA0004
+
+

Section .text.HAL_DMA_Init from PowerPro_lto.o, size=224, align=4

+
+
HAL_DMA_Init:
+  0x08000944:  B5F0         PUSH       {R4-R7, LR}
+  0x08000946:  B083         SUB        SP, SP, #12
+  0x08000948:  2800         CMP        R0, #0
+  0x0800094A:  D03A         BEQ        .L1                      ; 0x080009C2
+  0x0800094C:  4604         MOV        R4, R0
+  0x0800094E:  4601         MOV        R1, R0
+  0x08000950:  3124         ADDS       R1, #36
+  0x08000952:  2002         MOVS       R0, #2
+  0x08000954:  9102         STR        R1, [SP, #8]
+  0x08000956:  7048         STRB       R0, [R1, #1]
+  0x08000958:  6827         LDR        R7, [R4]
+  0x0800095A:  6838         LDR        R0, [R7]
+  0x0800095C:  492C         LDR        R1, =0xFFFF800F          ; [PC, #176] [0x08000A10] 
+  0x0800095E:  4001         ANDS       R1, R0
+  0x08000960:  6039         STR        R1, [R7]
+  0x08000962:  4E2C         LDR        R6, =0x40020800          ; [PC, #176] [0x08000A14] 
+  0x08000964:  4630         MOV        R0, R6
+  0x08000966:  3080         ADDS       R0, #128
+  0x08000968:  64A0         STR        R0, [R4, #72]
+  0x0800096A:  482B         LDR        R0, =0xBFFDFFF8          ; [PC, #172] [0x08000A18] 
+  0x0800096C:  1838         ADDS       R0, R7, R0
+  0x0800096E:  2114         MOVS       R1, #20
+  0x08000970:  F005 FB87    BL         __aeabi_uidiv            ; 0x08006082
+  0x08000974:  0080         LSLS       R0, R0, #2
+  0x08000976:  1981         ADDS       R1, R0, R6
+  0x08000978:  6420         STR        R0, [R4, #64]
+  0x0800097A:  9101         STR        R1, [SP, #4]
+  0x0800097C:  6461         STR        R1, [R4, #68]
+  0x0800097E:  20FC         MOVS       R0, #252
+  0x08000980:  4038         ANDS       R0, R7
+  0x08000982:  3808         SUBS       R0, #8
+  0x08000984:  2114         MOVS       R1, #20
+  0x08000986:  F005 FB7C    BL         __aeabi_uidiv            ; 0x08006082
+  0x0800098A:  211C         MOVS       R1, #28
+  0x0800098C:  4001         ANDS       R1, R0
+  0x0800098E:  2601         MOVS       R6, #1
+  0x08000990:  4630         MOV        R0, R6
+  0x08000992:  4088         LSLS       R0, R1
+  0x08000994:  64E0         STR        R0, [R4, #76]
+  0x08000996:  68E1         LDR        R1, [R4, #12]
+  0x08000998:  6922         LDR        R2, [R4, #16]
+  0x0800099A:  430A         ORRS       R2, R1
+  0x0800099C:  6961         LDR        R1, [R4, #20]
+  0x0800099E:  4311         ORRS       R1, R2
+  0x080009A0:  69A2         LDR        R2, [R4, #24]
+  0x080009A2:  430A         ORRS       R2, R1
+  0x080009A4:  69E1         LDR        R1, [R4, #28]
+  0x080009A6:  4311         ORRS       R1, R2
+  0x080009A8:  6A22         LDR        R2, [R4, #32]
+  0x080009AA:  430A         ORRS       R2, R1
+  0x080009AC:  68A1         LDR        R1, [R4, #8]
+  0x080009AE:  683B         LDR        R3, [R7]
+  0x080009B0:  4313         ORRS       R3, R2
+  0x080009B2:  430B         ORRS       R3, R1
+  0x080009B4:  603B         STR        R3, [R7]
+  0x080009B6:  03B2         LSLS       R2, R6, #14
+  0x080009B8:  4291         CMP        R1, R2
+  0x080009BA:  D104         BNE        .L2                      ; 0x080009C6
+  0x080009BC:  2100         MOVS       R1, #0
+  0x080009BE:  6061         STR        R1, [R4, #4]
+  0x080009C0:  E002         B          .L3                      ; 0x080009C8
+
.L1:
+  0x080009C2:  2001         MOVS       R0, #1
+  0x080009C4:  E021         B          .L5                      ; 0x08000A0A
+
.L2:
+  0x080009C6:  6861         LDR        R1, [R4, #4]
+
.L3:
+  0x080009C8:  B2CF         UXTB       R7, R1
+  0x080009CA:  9A01         LDR        R2, [SP, #4]
+  0x080009CC:  6017         STR        R7, [R2]
+  0x080009CE:  1E49         SUBS       R1, R1, #1
+  0x080009D0:  4A12         LDR        R2, =0x40020884          ; [PC, #72] [0x08000A1C] 
+  0x080009D2:  6010         STR        R0, [R2]
+  0x080009D4:  2000         MOVS       R0, #0
+  0x080009D6:  2903         CMP        R1, #3
+  0x080009D8:  4603         MOV        R3, R0
+  0x080009DA:  4601         MOV        R1, R0
+  0x080009DC:  4605         MOV        R5, R0
+  0x080009DE:  D80D         BHI        .L4                      ; 0x080009FC
+  0x080009E0:  1E79         SUBS       R1, R7, #1
+  0x080009E2:  008B         LSLS       R3, R1, #2
+  0x080009E4:  18D3         ADDS       R3, R2, R3
+  0x080009E6:  67DD         STR        R5, [R3, #124]
+  0x080009E8:  2501         MOVS       R5, #1
+  0x080009EA:  2603         MOVS       R6, #3
+  0x080009EC:  400E         ANDS       R6, R1
+  0x080009EE:  40B5         LSLS       R5, R6
+  0x080009F0:  2601         MOVS       R6, #1
+  0x080009F2:  490B         LDR        R1, =0x40020944          ; [PC, #44] [0x08000A20] 
+  0x080009F4:  600D         STR        R5, [R1]
+  0x080009F6:  337C         ADDS       R3, #124
+  0x080009F8:  32BC         ADDS       R2, #188
+  0x080009FA:  4611         MOV        R1, R2
+
.L4:
+  0x080009FC:  63E0         STR        R0, [R4, #60]
+  0x080009FE:  6523         STR        R3, [R4, #80]
+  0x08000A00:  6561         STR        R1, [R4, #84]
+  0x08000A02:  65A5         STR        R5, [R4, #88]
+  0x08000A04:  9902         LDR        R1, [SP, #8]
+  0x08000A06:  7008         STRB       R0, [R1]
+  0x08000A08:  704E         STRB       R6, [R1, #1]
+
.L5:
+  0x08000A0A:  B003         ADD        SP, SP, #12
+  0x08000A0C:  BDF0         POP        {R4-R7, PC}
+  0x08000A0E:  46C0         NOP
+  0x08000A10:  FFFF800F     DC.W       0xFFFF800F
+  0x08000A14:  40020800     DC.W       0x40020800
+  0x08000A18:  BFFDFFF8     DC.W       0xBFFDFFF8
+  0x08000A1C:  40020884     DC.W       0x40020884
+  0x08000A20:  40020944     DC.W       0x40020944
+
+

Section .text.HAL_DMA_Start_IT from PowerPro_lto.o, size=196, align=4

+
+
HAL_DMA_Start_IT:
+  0x08000A24:  B5F0         PUSH       {R4-R7, LR}
+  0x08000A26:  B084         SUB        SP, SP, #16
+  0x08000A28:  4604         MOV        R4, R0
+  0x08000A2A:  2024         MOVS       R0, #36
+  0x08000A2C:  5C20         LDRB       R0, [R4, R0]
+  0x08000A2E:  2801         CMP        R0, #1
+  0x08000A30:  D101         BNE        .L1                      ; 0x08000A36
+  0x08000A32:  2002         MOVS       R0, #2
+  0x08000A34:  E053         B          .L11                     ; 0x08000ADE
+
.L1:
+  0x08000A36:  4625         MOV        R5, R4
+  0x08000A38:  3524         ADDS       R5, #36
+  0x08000A3A:  7868         LDRB       R0, [R5, #1]
+  0x08000A3C:  2801         CMP        R0, #1
+  0x08000A3E:  D130         BNE        .L5                      ; 0x08000AA2
+  0x08000A40:  9300         STR        R3, [SP, #0]
+  0x08000A42:  9201         STR        R2, [SP, #4]
+  0x08000A44:  2002         MOVS       R0, #2
+  0x08000A46:  7068         STRB       R0, [R5, #1]
+  0x08000A48:  2000         MOVS       R0, #0
+  0x08000A4A:  63E0         STR        R0, [R4, #60]
+  0x08000A4C:  6826         LDR        R6, [R4]
+  0x08000A4E:  6832         LDR        R2, [R6]
+  0x08000A50:  2301         MOVS       R3, #1
+  0x08000A52:  9303         STR        R3, [SP, #12]
+  0x08000A54:  439A         BICS       R2, R3
+  0x08000A56:  6032         STR        R2, [R6]
+  0x08000A58:  6CA2         LDR        R2, [R4, #72]
+  0x08000A5A:  6CE7         LDR        R7, [R4, #76]
+  0x08000A5C:  6057         STR        R7, [R2, #4]
+  0x08000A5E:  6D22         LDR        R2, [R4, #80]
+  0x08000A60:  9202         STR        R2, [SP, #8]
+  0x08000A62:  2A00         CMP        R2, #0
+  0x08000A64:  D002         BEQ        .L2                      ; 0x08000A6C
+  0x08000A66:  6D62         LDR        R2, [R4, #84]
+  0x08000A68:  6DA7         LDR        R7, [R4, #88]
+  0x08000A6A:  6057         STR        R7, [R2, #4]
+
.L2:
+  0x08000A6C:  6C22         LDR        R2, [R4, #64]
+  0x08000A6E:  271C         MOVS       R7, #28
+  0x08000A70:  4017         ANDS       R7, R2
+  0x08000A72:  2201         MOVS       R2, #1
+  0x08000A74:  40BA         LSLS       R2, R7
+  0x08000A76:  4F1B         LDR        R7, =0x40020004          ; [PC, #108] [0x08000AE4] 
+  0x08000A78:  683B         LDR        R3, [R7]
+  0x08000A7A:  4313         ORRS       R3, R2
+  0x08000A7C:  603B         STR        R3, [R7]
+  0x08000A7E:  9A00         LDR        R2, [SP, #0]
+  0x08000A80:  6072         STR        R2, [R6, #4]
+  0x08000A82:  68A2         LDR        R2, [R4, #8]
+  0x08000A84:  2A10         CMP        R2, #16
+  0x08000A86:  9B01         LDR        R3, [SP, #4]
+  0x08000A88:  461A         MOV        R2, R3
+  0x08000A8A:  D000         BEQ        .L3                      ; 0x08000A8E
+  0x08000A8C:  460A         MOV        R2, R1
+
.L3:
+  0x08000A8E:  60B2         STR        R2, [R6, #8]
+  0x08000A90:  D000         BEQ        .L4                      ; 0x08000A94
+  0x08000A92:  4619         MOV        R1, R3
+
.L4:
+  0x08000A94:  60F1         STR        R1, [R6, #12]
+  0x08000A96:  6831         LDR        R1, [R6]
+  0x08000A98:  6B22         LDR        R2, [R4, #48]
+  0x08000A9A:  2A00         CMP        R2, #0
+  0x08000A9C:  D003         BEQ        .L6                      ; 0x08000AA6
+  0x08000A9E:  220E         MOVS       R2, #14
+  0x08000AA0:  E006         B          .L7                      ; 0x08000AB0
+
.L5:
+  0x08000AA2:  2002         MOVS       R0, #2
+  0x08000AA4:  E019         B          .L10                     ; 0x08000ADA
+
.L6:
+  0x08000AA6:  2204         MOVS       R2, #4
+  0x08000AA8:  4391         BICS       R1, R2
+  0x08000AAA:  6031         STR        R1, [R6]
+  0x08000AAC:  6832         LDR        R2, [R6]
+  0x08000AAE:  210A         MOVS       R1, #10
+
.L7:
+  0x08000AB0:  4311         ORRS       R1, R2
+  0x08000AB2:  6031         STR        R1, [R6]
+  0x08000AB4:  9903         LDR        R1, [SP, #12]
+  0x08000AB6:  0209         LSLS       R1, R1, #8
+  0x08000AB8:  6C62         LDR        R2, [R4, #68]
+  0x08000ABA:  6813         LDR        R3, [R2]
+  0x08000ABC:  03DB         LSLS       R3, R3, #15
+  0x08000ABE:  D502         BPL        .L8                      ; 0x08000AC6
+  0x08000AC0:  6813         LDR        R3, [R2]
+  0x08000AC2:  430B         ORRS       R3, R1
+  0x08000AC4:  6013         STR        R3, [R2]
+
.L8:
+  0x08000AC6:  9B02         LDR        R3, [SP, #8]
+  0x08000AC8:  2B00         CMP        R3, #0
+  0x08000ACA:  D002         BEQ        .L9                      ; 0x08000AD2
+  0x08000ACC:  681A         LDR        R2, [R3]
+  0x08000ACE:  430A         ORRS       R2, R1
+  0x08000AD0:  601A         STR        R2, [R3]
+
.L9:
+  0x08000AD2:  6831         LDR        R1, [R6]
+  0x08000AD4:  9A03         LDR        R2, [SP, #12]
+  0x08000AD6:  4311         ORRS       R1, R2
+  0x08000AD8:  6031         STR        R1, [R6]
+
.L10:
+  0x08000ADA:  2100         MOVS       R1, #0
+  0x08000ADC:  7029         STRB       R1, [R5]
+
.L11:
+  0x08000ADE:  B004         ADD        SP, SP, #16
+  0x08000AE0:  BDF0         POP        {R4-R7, PC}
+  0x08000AE2:  46C0         NOP
+  0x08000AE4:  40020004     DC.W       0x40020004
+
+

Section .text.HAL_DMA_IRQHandler from PowerPro_lto.o, size=164, align=4

+
+
HAL_DMA_IRQHandler:
+  0x08000AE8:  B5F0         PUSH       {R4-R7, LR}
+  0x08000AEA:  B081         SUB        SP, SP, #4
+  0x08000AEC:  6C01         LDR        R1, [R0, #64]
+  0x08000AEE:  241C         MOVS       R4, #28
+  0x08000AF0:  400C         ANDS       R4, R1
+  0x08000AF2:  2604         MOVS       R6, #4
+  0x08000AF4:  4633         MOV        R3, R6
+  0x08000AF6:  40A3         LSLS       R3, R4
+  0x08000AF8:  4923         LDR        R1, =0x40020004          ; [PC, #140] [0x08000B88] 
+  0x08000AFA:  1F0A         SUBS       R2, R1, #4
+  0x08000AFC:  6817         LDR        R7, [R2]
+  0x08000AFE:  6802         LDR        R2, [R0]
+  0x08000B00:  6815         LDR        R5, [R2]
+  0x08000B02:  423B         TST        R3, R7
+  0x08000B04:  D001         BEQ        .L1                      ; 0x08000B0A
+  0x08000B06:  0769         LSLS       R1, R5, #29
+  0x08000B08:  D41D         BMI        .L3                      ; 0x08000B46
+
.L1:
+  0x08000B0A:  4603         MOV        R3, R0
+  0x08000B0C:  3324         ADDS       R3, #36
+  0x08000B0E:  2602         MOVS       R6, #2
+  0x08000B10:  40A6         LSLS       R6, R4
+  0x08000B12:  423E         TST        R6, R7
+  0x08000B14:  D001         BEQ        .L2                      ; 0x08000B1A
+  0x08000B16:  07A9         LSLS       R1, R5, #30
+  0x08000B18:  D421         BMI        .L5                      ; 0x08000B5E
+
.L2:
+  0x08000B1A:  40E7         LSRS       R7, R4
+  0x08000B1C:  0739         LSLS       R1, R7, #28
+  0x08000B1E:  D531         BPL        .L8                      ; 0x08000B84
+  0x08000B20:  0729         LSLS       R1, R5, #28
+  0x08000B22:  D52F         BPL        .L8                      ; 0x08000B84
+  0x08000B24:  6811         LDR        R1, [R2]
+  0x08000B26:  250E         MOVS       R5, #14
+  0x08000B28:  43A9         BICS       R1, R5
+  0x08000B2A:  6011         STR        R1, [R2]
+  0x08000B2C:  2101         MOVS       R1, #1
+  0x08000B2E:  460A         MOV        R2, R1
+  0x08000B30:  40A2         LSLS       R2, R4
+  0x08000B32:  4D15         LDR        R5, =0x40020004          ; [PC, #84] [0x08000B88] 
+  0x08000B34:  682C         LDR        R4, [R5]
+  0x08000B36:  4314         ORRS       R4, R2
+  0x08000B38:  602C         STR        R4, [R5]
+  0x08000B3A:  63C1         STR        R1, [R0, #60]
+  0x08000B3C:  2200         MOVS       R2, #0
+  0x08000B3E:  701A         STRB       R2, [R3]
+  0x08000B40:  7059         STRB       R1, [R3, #1]
+  0x08000B42:  6B41         LDR        R1, [R0, #52]
+  0x08000B44:  E01B         B          .L7                      ; 0x08000B7E
+
.L3:
+  0x08000B46:  6811         LDR        R1, [R2]
+  0x08000B48:  0689         LSLS       R1, R1, #26
+  0x08000B4A:  D402         BMI        .L4                      ; 0x08000B52
+  0x08000B4C:  6811         LDR        R1, [R2]
+  0x08000B4E:  43B1         BICS       R1, R6
+  0x08000B50:  6011         STR        R1, [R2]
+
.L4:
+  0x08000B52:  4A0D         LDR        R2, =0x40020004          ; [PC, #52] [0x08000B88] 
+  0x08000B54:  6811         LDR        R1, [R2]
+  0x08000B56:  4319         ORRS       R1, R3
+  0x08000B58:  6011         STR        R1, [R2]
+  0x08000B5A:  6B01         LDR        R1, [R0, #48]
+  0x08000B5C:  E00F         B          .L7                      ; 0x08000B7E
+
.L5:
+  0x08000B5E:  6811         LDR        R1, [R2]
+  0x08000B60:  0689         LSLS       R1, R1, #26
+  0x08000B62:  D405         BMI        .L6                      ; 0x08000B70
+  0x08000B64:  6811         LDR        R1, [R2]
+  0x08000B66:  240A         MOVS       R4, #10
+  0x08000B68:  43A1         BICS       R1, R4
+  0x08000B6A:  6011         STR        R1, [R2]
+  0x08000B6C:  2101         MOVS       R1, #1
+  0x08000B6E:  7059         STRB       R1, [R3, #1]
+
.L6:
+  0x08000B70:  2100         MOVS       R1, #0
+  0x08000B72:  7019         STRB       R1, [R3]
+  0x08000B74:  4A04         LDR        R2, =0x40020004          ; [PC, #16] [0x08000B88] 
+  0x08000B76:  6811         LDR        R1, [R2]
+  0x08000B78:  4331         ORRS       R1, R6
+  0x08000B7A:  6011         STR        R1, [R2]
+  0x08000B7C:  6AC1         LDR        R1, [R0, #44]
+
.L7:
+  0x08000B7E:  2900         CMP        R1, #0
+  0x08000B80:  D000         BEQ        .L8                      ; 0x08000B84
+  0x08000B82:  4788         BLX        R1
+
.L8:
+  0x08000B84:  B001         ADD        SP, SP, #4
+  0x08000B86:  BDF0         POP        {R4-R7, PC}
+  0x08000B88:  40020004     DC.W       0x40020004
+
+

Section .text.FLASH_WaitForLastOperation from PowerPro_lto.o, size=80, align=4

+
+
FLASH_WaitForLastOperation:
+  0x08000B8C:  B510         PUSH       {R4, LR}
+  0x08000B8E:  207D         MOVS       R0, #125
+  0x08000B90:  00C2         LSLS       R2, R0, #3
+  0x08000B92:  480F         LDR        R0, =uwTick              ; [PC, #60] [0x08000BD0] =0x2000068C 
+  0x08000B94:  6801         LDR        R1, [R0]
+  0x08000B96:  188B         ADDS       R3, R1, R2
+  0x08000B98:  490E         LDR        R1, =0x40022010          ; [PC, #56] [0x08000BD4] 
+
.L1:
+  0x08000B9A:  680C         LDR        R4, [R1]
+  0x08000B9C:  03E4         LSLS       R4, R4, #15
+  0x08000B9E:  D504         BPL        .L3                      ; 0x08000BAA
+  0x08000BA0:  6804         LDR        R4, [R0]
+  0x08000BA2:  429C         CMP        R4, R3
+  0x08000BA4:  D3F9         BCC        .L1                      ; 0x08000B9A
+
.L2:
+  0x08000BA6:  2003         MOVS       R0, #3
+  0x08000BA8:  BD10         POP        {R4, PC}
+
.L3:
+  0x08000BAA:  680B         LDR        R3, [R1]
+  0x08000BAC:  4C0A         LDR        R4, =0x0000C3FA          ; [PC, #40] [0x08000BD8] 
+  0x08000BAE:  401C         ANDS       R4, R3
+  0x08000BB0:  600C         STR        R4, [R1]
+  0x08000BB2:  D001         BEQ        .L4                      ; 0x08000BB8
+  0x08000BB4:  2001         MOVS       R0, #1
+  0x08000BB6:  BD10         POP        {R4, PC}
+
.L4:
+  0x08000BB8:  6803         LDR        R3, [R0]
+  0x08000BBA:  189A         ADDS       R2, R3, R2
+
.L5:
+  0x08000BBC:  680B         LDR        R3, [R1]
+  0x08000BBE:  035B         LSLS       R3, R3, #13
+  0x08000BC0:  D503         BPL        .L6                      ; 0x08000BCA
+  0x08000BC2:  6803         LDR        R3, [R0]
+  0x08000BC4:  4293         CMP        R3, R2
+  0x08000BC6:  D3F9         BCC        .L5                      ; 0x08000BBC
+  0x08000BC8:  E7ED         B          .L2                      ; 0x08000BA6
+
.L6:
+  0x08000BCA:  2000         MOVS       R0, #0
+  0x08000BCC:  BD10         POP        {R4, PC}
+  0x08000BCE:  46C0         NOP
+  0x08000BD0:  2000068C     DC.W       uwTick
+  0x08000BD4:  40022010     DC.W       0x40022010
+  0x08000BD8:  0000C3FA     DC.W       0x0000C3FA
+
+

Section .text.HAL_FLASH_Unlock from PowerPro_lto.o, size=32, align=4

+
+
HAL_FLASH_Unlock:
+  0x08000BDC:  4804         LDR        R0, =0x40022008          ; [PC, #16] [0x08000BF0] 
+  0x08000BDE:  68C1         LDR        R1, [R0, #12]
+  0x08000BE0:  2900         CMP        R1, #0
+  0x08000BE2:  D504         BPL        .L1                      ; 0x08000BEE
+  0x08000BE4:  4903         LDR        R1, =0x45670123          ; [PC, #12] [0x08000BF4] 
+  0x08000BE6:  6001         STR        R1, [R0]
+  0x08000BE8:  4903         LDR        R1, =0xCDEF89AB          ; [PC, #12] [0x08000BF8] 
+  0x08000BEA:  6001         STR        R1, [R0]
+  0x08000BEC:  68C0         LDR        R0, [R0, #12]
+
.L1:
+  0x08000BEE:  4770         BX         LR
+  0x08000BF0:  40022008     DC.W       0x40022008
+  0x08000BF4:  45670123     DC.W       0x45670123
+  0x08000BF8:  CDEF89AB     DC.W       0xCDEF89AB
+
+

Section .text.HAL_GPIO_Init from PowerPro_lto.o, size=380, align=4

+
+
HAL_GPIO_Init:
+  0x08000BFC:  B5F0         PUSH       {R4-R7, LR}
+  0x08000BFE:  B08A         SUB        SP, SP, #40
+  0x08000C00:  4A59         LDR        R2, =0x50001400          ; [PC, #0x0164] [0x08000D68] 
+  0x08000C02:  9005         STR        R0, [SP, #20]
+  0x08000C04:  4290         CMP        R0, R2
+  0x08000C06:  D001         BEQ        .L1                      ; 0x08000C0C
+  0x08000C08:  2006         MOVS       R0, #6
+  0x08000C0A:  E000         B          .L2                      ; 0x08000C0E
+
.L1:
+  0x08000C0C:  2005         MOVS       R0, #5
+
.L2:
+  0x08000C0E:  220B         MOVS       R2, #11
+  0x08000C10:  0712         LSLS       R2, R2, #28
+  0x08000C12:  9B05         LDR        R3, [SP, #20]
+  0x08000C14:  189B         ADDS       R3, R3, R2
+  0x08000C16:  220A         MOVS       R2, #10
+  0x08000C18:  41D3         RORS       R3, R2
+  0x08000C1A:  9300         STR        R3, [SP, #0]
+  0x08000C1C:  2B04         CMP        R3, #4
+  0x08000C1E:  D300         BCC        .L3                      ; 0x08000C22
+  0x08000C20:  9000         STR        R0, [SP, #0]
+
.L3:
+  0x08000C22:  9805         LDR        R0, [SP, #20]
+  0x08000C24:  3020         ADDS       R0, #32
+  0x08000C26:  9001         STR        R0, [SP, #4]
+  0x08000C28:  2200         MOVS       R2, #0
+  0x08000C2A:  4617         MOV        R7, R2
+  0x08000C2C:  9207         STR        R2, [SP, #28]
+  0x08000C2E:  9208         STR        R2, [SP, #32]
+
.L4:
+  0x08000C30:  680D         LDR        R5, [R1]
+  0x08000C32:  4628         MOV        R0, R5
+  0x08000C34:  40D0         LSRS       R0, R2
+  0x08000C36:  D100         BNE        .L5                      ; 0x08000C3A
+  0x08000C38:  E093         B          .L19                     ; 0x08000D62
+
.L5:
+  0x08000C3A:  2301         MOVS       R3, #1
+  0x08000C3C:  4618         MOV        R0, R3
+  0x08000C3E:  9209         STR        R2, [SP, #36]
+  0x08000C40:  4090         LSLS       R0, R2
+  0x08000C42:  9004         STR        R0, [SP, #16]
+  0x08000C44:  4005         ANDS       R5, R0
+  0x08000C46:  D100         BNE        .L6                      ; 0x08000C4A
+  0x08000C48:  E081         B          .L18                     ; 0x08000D4E
+
.L6:
+  0x08000C4A:  684A         LDR        R2, [R1, #4]
+  0x08000C4C:  2010         MOVS       R0, #16
+  0x08000C4E:  4310         ORRS       R0, R2
+  0x08000C50:  2812         CMP        R0, #18
+  0x08000C52:  460E         MOV        R6, R1
+  0x08000C54:  9706         STR        R7, [SP, #24]
+  0x08000C56:  D116         BNE        .L7                      ; 0x08000C86
+  0x08000C58:  211C         MOVS       R1, #28
+  0x08000C5A:  9808         LDR        R0, [SP, #32]
+  0x08000C5C:  4001         ANDS       R1, R0
+  0x08000C5E:  270F         MOVS       R7, #15
+  0x08000C60:  463A         MOV        R2, R7
+  0x08000C62:  408A         LSLS       R2, R1
+  0x08000C64:  9809         LDR        R0, [SP, #36]
+  0x08000C66:  08C4         LSRS       R4, R0, #3
+  0x08000C68:  00A4         LSLS       R4, R4, #2
+  0x08000C6A:  9303         STR        R3, [SP, #12]
+  0x08000C6C:  4633         MOV        R3, R6
+  0x08000C6E:  9E01         LDR        R6, [SP, #4]
+  0x08000C70:  5930         LDR        R0, [R6, R4]
+  0x08000C72:  4390         BICS       R0, R2
+  0x08000C74:  691A         LDR        R2, [R3, #16]
+  0x08000C76:  403A         ANDS       R2, R7
+  0x08000C78:  9F06         LDR        R7, [SP, #24]
+  0x08000C7A:  408A         LSLS       R2, R1
+  0x08000C7C:  4302         ORRS       R2, R0
+  0x08000C7E:  5132         STR        R2, [R6, R4]
+  0x08000C80:  461E         MOV        R6, R3
+  0x08000C82:  9B03         LDR        R3, [SP, #12]
+  0x08000C84:  6872         LDR        R2, [R6, #4]
+
.L7:
+  0x08000C86:  2403         MOVS       R4, #3
+  0x08000C88:  4610         MOV        R0, R2
+  0x08000C8A:  4020         ANDS       R0, R4
+  0x08000C8C:  40B8         LSLS       R0, R7
+  0x08000C8E:  9402         STR        R4, [SP, #8]
+  0x08000C90:  40BC         LSLS       R4, R7
+  0x08000C92:  9905         LDR        R1, [SP, #20]
+  0x08000C94:  680F         LDR        R7, [R1]
+  0x08000C96:  43A7         BICS       R7, R4
+  0x08000C98:  4307         ORRS       R7, R0
+  0x08000C9A:  600F         STR        R7, [R1]
+  0x08000C9C:  9F06         LDR        R7, [SP, #24]
+  0x08000C9E:  43E0         MVNS       R0, R4
+  0x08000CA0:  9003         STR        R0, [SP, #12]
+  0x08000CA2:  2A12         CMP        R2, #18
+  0x08000CA4:  4631         MOV        R1, R6
+  0x08000CA6:  D815         BHI        .L9                      ; 0x08000CD4
+  0x08000CA8:  4093         LSLS       R3, R2
+  0x08000CAA:  4832         LDR        R0, =0x00060006          ; [PC, #200] [0x08000D74] 
+  0x08000CAC:  4203         TST        R3, R0
+  0x08000CAE:  D00F         BEQ        .L8                      ; 0x08000CD0
+  0x08000CB0:  9C05         LDR        R4, [SP, #20]
+  0x08000CB2:  68A0         LDR        R0, [R4, #8]
+  0x08000CB4:  9B03         LDR        R3, [SP, #12]
+  0x08000CB6:  4018         ANDS       R0, R3
+  0x08000CB8:  68CB         LDR        R3, [R1, #12]
+  0x08000CBA:  40BB         LSLS       R3, R7
+  0x08000CBC:  4303         ORRS       R3, R0
+  0x08000CBE:  60A3         STR        R3, [R4, #8]
+  0x08000CC0:  0910         LSRS       R0, R2, #4
+  0x08000CC2:  9B09         LDR        R3, [SP, #36]
+  0x08000CC4:  4098         LSLS       R0, R3
+  0x08000CC6:  6863         LDR        R3, [R4, #4]
+  0x08000CC8:  9E04         LDR        R6, [SP, #16]
+  0x08000CCA:  43B3         BICS       R3, R6
+  0x08000CCC:  4303         ORRS       R3, R0
+  0x08000CCE:  6063         STR        R3, [R4, #4]
+
.L8:
+  0x08000CD0:  2A03         CMP        R2, #3
+  0x08000CD2:  D03C         BEQ        .L18                     ; 0x08000D4E
+
.L9:
+  0x08000CD4:  9C05         LDR        R4, [SP, #20]
+  0x08000CD6:  68E0         LDR        R0, [R4, #12]
+  0x08000CD8:  9B03         LDR        R3, [SP, #12]
+  0x08000CDA:  4018         ANDS       R0, R3
+  0x08000CDC:  688B         LDR        R3, [R1, #8]
+  0x08000CDE:  40BB         LSLS       R3, R7
+  0x08000CE0:  4303         ORRS       R3, R0
+  0x08000CE2:  60E3         STR        R3, [R4, #12]
+  0x08000CE4:  00D0         LSLS       R0, R2, #3
+  0x08000CE6:  D532         BPL        .L18                     ; 0x08000D4E
+  0x08000CE8:  2018         MOVS       R0, #24
+  0x08000CEA:  9A07         LDR        R2, [SP, #28]
+  0x08000CEC:  4010         ANDS       R0, R2
+  0x08000CEE:  220F         MOVS       R2, #15
+  0x08000CF0:  4082         LSLS       R2, R0
+  0x08000CF2:  9B09         LDR        R3, [SP, #36]
+  0x08000CF4:  9C02         LDR        R4, [SP, #8]
+  0x08000CF6:  43A3         BICS       R3, R4
+  0x08000CF8:  4C1C         LDR        R4, =0x40021800          ; [PC, #112] [0x08000D6C] 
+  0x08000CFA:  18E4         ADDS       R4, R4, R3
+  0x08000CFC:  6E23         LDR        R3, [R4, #96]
+  0x08000CFE:  4393         BICS       R3, R2
+  0x08000D00:  9A00         LDR        R2, [SP, #0]
+  0x08000D02:  4082         LSLS       R2, R0
+  0x08000D04:  431A         ORRS       R2, R3
+  0x08000D06:  6622         STR        R2, [R4, #96]
+  0x08000D08:  4819         LDR        R0, =0x40021880          ; [PC, #100] [0x08000D70] 
+  0x08000D0A:  6802         LDR        R2, [R0]
+  0x08000D0C:  684B         LDR        R3, [R1, #4]
+  0x08000D0E:  03D8         LSLS       R0, R3, #15
+  0x08000D10:  D501         BPL        .L10                     ; 0x08000D16
+  0x08000D12:  432A         ORRS       R2, R5
+  0x08000D14:  E000         B          .L11                     ; 0x08000D18
+
.L10:
+  0x08000D16:  43AA         BICS       R2, R5
+
.L11:
+  0x08000D18:  4815         LDR        R0, =0x40021880          ; [PC, #84] [0x08000D70] 
+  0x08000D1A:  6002         STR        R2, [R0]
+  0x08000D1C:  6842         LDR        R2, [R0, #4]
+  0x08000D1E:  0398         LSLS       R0, R3, #14
+  0x08000D20:  D501         BPL        .L12                     ; 0x08000D26
+  0x08000D22:  432A         ORRS       R2, R5
+  0x08000D24:  E000         B          .L13                     ; 0x08000D28
+
.L12:
+  0x08000D26:  43AA         BICS       R2, R5
+
.L13:
+  0x08000D28:  4811         LDR        R0, =0x40021880          ; [PC, #68] [0x08000D70] 
+  0x08000D2A:  6042         STR        R2, [R0, #4]
+  0x08000D2C:  480F         LDR        R0, =0x40021800          ; [PC, #60] [0x08000D6C] 
+  0x08000D2E:  6802         LDR        R2, [R0]
+  0x08000D30:  02D8         LSLS       R0, R3, #11
+  0x08000D32:  D501         BPL        .L14                     ; 0x08000D38
+  0x08000D34:  432A         ORRS       R2, R5
+  0x08000D36:  E000         B          .L15                     ; 0x08000D3A
+
.L14:
+  0x08000D38:  43AA         BICS       R2, R5
+
.L15:
+  0x08000D3A:  480C         LDR        R0, =0x40021800          ; [PC, #48] [0x08000D6C] 
+  0x08000D3C:  6002         STR        R2, [R0]
+  0x08000D3E:  6842         LDR        R2, [R0, #4]
+  0x08000D40:  0298         LSLS       R0, R3, #10
+  0x08000D42:  D501         BPL        .L16                     ; 0x08000D48
+  0x08000D44:  432A         ORRS       R2, R5
+  0x08000D46:  E000         B          .L17                     ; 0x08000D4A
+
.L16:
+  0x08000D48:  43AA         BICS       R2, R5
+
.L17:
+  0x08000D4A:  4808         LDR        R0, =0x40021800          ; [PC, #32] [0x08000D6C] 
+  0x08000D4C:  6042         STR        R2, [R0, #4]
+
.L18:
+  0x08000D4E:  9808         LDR        R0, [SP, #32]
+  0x08000D50:  1D00         ADDS       R0, R0, #4
+  0x08000D52:  9008         STR        R0, [SP, #32]
+  0x08000D54:  1CBF         ADDS       R7, R7, #2
+  0x08000D56:  9807         LDR        R0, [SP, #28]
+  0x08000D58:  3008         ADDS       R0, #8
+  0x08000D5A:  9007         STR        R0, [SP, #28]
+  0x08000D5C:  9A09         LDR        R2, [SP, #36]
+  0x08000D5E:  1C52         ADDS       R2, R2, #1
+  0x08000D60:  E766         B          .L4                      ; 0x08000C30
+
.L19:
+  0x08000D62:  B00A         ADD        SP, SP, #40
+  0x08000D64:  BDF0         POP        {R4-R7, PC}
+  0x08000D66:  46C0         NOP
+  0x08000D68:  50001400     DC.W       0x50001400
+  0x08000D6C:  40021800     DC.W       0x40021800
+  0x08000D70:  40021880     DC.W       0x40021880
+  0x08000D74:  00060006     DC.W       0x00060006
+
+

Section .text.HAL_RCC_GetSysClockFreq from PowerPro_lto.o, size=84, align=4

+
+
HAL_RCC_GetSysClockFreq:
+  0x08000D78:  4811         LDR        R0, =0x40021008          ; [PC, #68] [0x08000DC0] 
+  0x08000D7A:  6801         LDR        R1, [R0]
+  0x08000D7C:  0689         LSLS       R1, R1, #26
+  0x08000D7E:  0F49         LSRS       R1, R1, #29
+  0x08000D80:  D006         BEQ        .L1                      ; 0x08000D90
+  0x08000D82:  6802         LDR        R2, [R0]
+  0x08000D84:  2138         MOVS       R1, #56
+  0x08000D86:  400A         ANDS       R2, R1
+  0x08000D88:  2A08         CMP        R2, #8
+  0x08000D8A:  D108         BNE        .L2                      ; 0x08000D9E
+  0x08000D8C:  480D         LDR        R0, =0x007A1200          ; [PC, #52] [0x08000DC4] 
+  0x08000D8E:  4770         BX         LR
+
.L1:
+  0x08000D90:  3808         SUBS       R0, #8
+  0x08000D92:  6800         LDR        R0, [R0]
+  0x08000D94:  0480         LSLS       R0, R0, #18
+  0x08000D96:  0F41         LSRS       R1, R0, #29
+  0x08000D98:  480B         LDR        R0, =0x02DC6C00          ; [PC, #44] [0x08000DC8] 
+  0x08000D9A:  40C8         LSRS       R0, R1
+  0x08000D9C:  4770         BX         LR
+
.L2:
+  0x08000D9E:  6802         LDR        R2, [R0]
+  0x08000DA0:  400A         ANDS       R2, R1
+  0x08000DA2:  2A20         CMP        R2, #32
+  0x08000DA4:  D102         BNE        .L3                      ; 0x08000DAC
+  0x08000DA6:  2001         MOVS       R0, #1
+  0x08000DA8:  03C0         LSLS       R0, R0, #15
+  0x08000DAA:  4770         BX         LR
+
.L3:
+  0x08000DAC:  6800         LDR        R0, [R0]
+  0x08000DAE:  4008         ANDS       R0, R1
+  0x08000DB0:  2818         CMP        R0, #24
+  0x08000DB2:  D001         BEQ        .L4                      ; 0x08000DB8
+  0x08000DB4:  2000         MOVS       R0, #0
+  0x08000DB6:  4770         BX         LR
+
.L4:
+  0x08000DB8:  207D         MOVS       R0, #125
+  0x08000DBA:  0200         LSLS       R0, R0, #8
+  0x08000DBC:  4770         BX         LR
+  0x08000DBE:  46C0         NOP
+  0x08000DC0:  40021008     DC.W       0x40021008
+  0x08000DC4:  007A1200     DC.W       0x007A1200
+  0x08000DC8:  02DC6C00     DC.W       0x02DC6C00
+
+

Section .text.HAL_RCC_GetPCLK1Freq from PowerPro_lto.o, size=64, align=4

+
+
HAL_RCC_GetPCLK1Freq:
+  0x08000DCC:  B580         PUSH       {R7, LR}
+  0x08000DCE:  F7FF FFD3    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+  0x08000DD2:  490A         LDR        R1, =0x40021008          ; [PC, #40] [0x08000DFC] 
+  0x08000DD4:  680A         LDR        R2, [R1]
+  0x08000DD6:  0992         LSRS       R2, R2, #6
+  0x08000DD8:  233C         MOVS       R3, #60
+  0x08000DDA:  4013         ANDS       R3, R2
+  0x08000DDC:  4A08         LDR        R2, =AHBPrescTable       ; [PC, #32] [0x08000E00] =0x0800515C 
+  0x08000DDE:  58D2         LDR        R2, [R2, R3]
+  0x08000DE0:  231F         MOVS       R3, #31
+  0x08000DE2:  401A         ANDS       R2, R3
+  0x08000DE4:  40D0         LSRS       R0, R2
+  0x08000DE6:  4A07         LDR        R2, =SystemCoreClock     ; [PC, #28] [0x08000E04] =0x20000BA4 
+  0x08000DE8:  6010         STR        R0, [R2]
+  0x08000DEA:  6809         LDR        R1, [R1]
+  0x08000DEC:  0A89         LSRS       R1, R1, #10
+  0x08000DEE:  221C         MOVS       R2, #28
+  0x08000DF0:  400A         ANDS       R2, R1
+  0x08000DF2:  4905         LDR        R1, =APBPrescTable       ; [PC, #20] [0x08000E08] =0x0800519C 
+  0x08000DF4:  5889         LDR        R1, [R1, R2]
+  0x08000DF6:  4019         ANDS       R1, R3
+  0x08000DF8:  40C8         LSRS       R0, R1
+  0x08000DFA:  BD80         POP        {R7, PC}
+  0x08000DFC:  40021008     DC.W       0x40021008
+  0x08000E00:  0800515C     DC.W       AHBPrescTable
+  0x08000E04:  20000BA4     DC.W       SystemCoreClock
+  0x08000E08:  0800519C     DC.W       APBPrescTable
+
+

Section .text.HAL_RCCEx_PeriphCLKConfig from PowerPro_lto.o, size=268, align=4

+
+
HAL_RCCEx_PeriphCLKConfig:
+  0x08000E0C:  B5F0         PUSH       {R4-R7, LR}
+  0x08000E0E:  B084         SUB        SP, SP, #16
+  0x08000E10:  6803         LDR        R3, [R0]
+  0x08000E12:  0659         LSLS       R1, R3, #25
+  0x08000E14:  4A3C         LDR        R2, =0x4002103C          ; [PC, #240] [0x08000F08] 
+  0x08000E16:  D401         BMI        .L1                      ; 0x08000E1C
+  0x08000E18:  2500         MOVS       R5, #0
+  0x08000E1A:  E034         B          .L6                      ; 0x08000E86
+
.L1:
+  0x08000E1C:  2601         MOVS       R6, #1
+  0x08000E1E:  0734         LSLS       R4, R6, #28
+  0x08000E20:  6811         LDR        R1, [R2]
+  0x08000E22:  4021         ANDS       R1, R4
+  0x08000E24:  9102         STR        R1, [SP, #8]
+  0x08000E26:  D106         BNE        .L2                      ; 0x08000E36
+  0x08000E28:  6811         LDR        R1, [R2]
+  0x08000E2A:  4321         ORRS       R1, R4
+  0x08000E2C:  6011         STR        R1, [R2]
+  0x08000E2E:  6811         LDR        R1, [R2]
+  0x08000E30:  4021         ANDS       R1, R4
+  0x08000E32:  9103         STR        R1, [SP, #12]
+  0x08000E34:  9903         LDR        R1, [SP, #12]
+
.L2:
+  0x08000E36:  2103         MOVS       R1, #3
+  0x08000E38:  9101         STR        R1, [SP, #4]
+  0x08000E3A:  020D         LSLS       R5, R1, #8
+  0x08000E3C:  6A17         LDR        R7, [R2, #32]
+  0x08000E3E:  402F         ANDS       R7, R5
+  0x08000E40:  6985         LDR        R5, [R0, #24]
+  0x08000E42:  4932         LDR        R1, =0xFFFFFCFF          ; [PC, #200] [0x08000F0C] 
+  0x08000E44:  D012         BEQ        .L3                      ; 0x08000E6C
+  0x08000E46:  42AF         CMP        R7, R5
+  0x08000E48:  D011         BEQ        .L4                      ; 0x08000E6E
+  0x08000E4A:  9400         STR        R4, [SP, #0]
+  0x08000E4C:  6A17         LDR        R7, [R2, #32]
+  0x08000E4E:  0436         LSLS       R6, R6, #16
+  0x08000E50:  6A14         LDR        R4, [R2, #32]
+  0x08000E52:  4334         ORRS       R4, R6
+  0x08000E54:  6214         STR        R4, [R2, #32]
+  0x08000E56:  6A14         LDR        R4, [R2, #32]
+  0x08000E58:  43B4         BICS       R4, R6
+  0x08000E5A:  6214         STR        R4, [R2, #32]
+  0x08000E5C:  463C         MOV        R4, R7
+  0x08000E5E:  400C         ANDS       R4, R1
+  0x08000E60:  6214         STR        R4, [R2, #32]
+  0x08000E62:  07FC         LSLS       R4, R7, #31
+  0x08000E64:  D13E         BNE        .L12                     ; 0x08000EE4
+  0x08000E66:  462F         MOV        R7, R5
+  0x08000E68:  9C00         LDR        R4, [SP, #0]
+  0x08000E6A:  E000         B          .L4                      ; 0x08000E6E
+
.L3:
+  0x08000E6C:  462F         MOV        R7, R5
+
.L4:
+  0x08000E6E:  460D         MOV        R5, R1
+  0x08000E70:  6A11         LDR        R1, [R2, #32]
+  0x08000E72:  4029         ANDS       R1, R5
+  0x08000E74:  4339         ORRS       R1, R7
+  0x08000E76:  6211         STR        R1, [R2, #32]
+  0x08000E78:  2500         MOVS       R5, #0
+
.L5:
+  0x08000E7A:  9902         LDR        R1, [SP, #8]
+  0x08000E7C:  2900         CMP        R1, #0
+  0x08000E7E:  D102         BNE        .L6                      ; 0x08000E86
+  0x08000E80:  6811         LDR        R1, [R2]
+  0x08000E82:  43A1         BICS       R1, R4
+  0x08000E84:  6011         STR        R1, [R2]
+
.L6:
+  0x08000E86:  07D9         LSLS       R1, R3, #31
+  0x08000E88:  D005         BEQ        .L7                      ; 0x08000E96
+  0x08000E8A:  6991         LDR        R1, [R2, #24]
+  0x08000E8C:  2403         MOVS       R4, #3
+  0x08000E8E:  43A1         BICS       R1, R4
+  0x08000E90:  6884         LDR        R4, [R0, #8]
+  0x08000E92:  430C         ORRS       R4, R1
+  0x08000E94:  6194         STR        R4, [R2, #24]
+
.L7:
+  0x08000E96:  0799         LSLS       R1, R3, #30
+  0x08000E98:  D506         BPL        .L8                      ; 0x08000EA8
+  0x08000E9A:  2103         MOVS       R1, #3
+  0x08000E9C:  0309         LSLS       R1, R1, #12
+  0x08000E9E:  6994         LDR        R4, [R2, #24]
+  0x08000EA0:  438C         BICS       R4, R1
+  0x08000EA2:  68C1         LDR        R1, [R0, #12]
+  0x08000EA4:  4321         ORRS       R1, R4
+  0x08000EA6:  6191         STR        R1, [R2, #24]
+
.L8:
+  0x08000EA8:  0699         LSLS       R1, R3, #26
+  0x08000EAA:  D506         BPL        .L9                      ; 0x08000EBA
+  0x08000EAC:  2103         MOVS       R1, #3
+  0x08000EAE:  0789         LSLS       R1, R1, #30
+  0x08000EB0:  6994         LDR        R4, [R2, #24]
+  0x08000EB2:  438C         BICS       R4, R1
+  0x08000EB4:  6941         LDR        R1, [R0, #20]
+  0x08000EB6:  4321         ORRS       R1, R4
+  0x08000EB8:  6191         STR        R1, [R2, #24]
+
.L9:
+  0x08000EBA:  0759         LSLS       R1, R3, #29
+  0x08000EBC:  D506         BPL        .L10                     ; 0x08000ECC
+  0x08000EBE:  2103         MOVS       R1, #3
+  0x08000EC0:  0389         LSLS       R1, R1, #14
+  0x08000EC2:  6994         LDR        R4, [R2, #24]
+  0x08000EC4:  438C         BICS       R4, R1
+  0x08000EC6:  6901         LDR        R1, [R0, #16]
+  0x08000EC8:  4321         ORRS       R1, R4
+  0x08000ECA:  6191         STR        R1, [R2, #24]
+
.L10:
+  0x08000ECC:  0619         LSLS       R1, R3, #24
+  0x08000ECE:  D506         BPL        .L11                     ; 0x08000EDE
+  0x08000ED0:  3A3C         SUBS       R2, #60
+  0x08000ED2:  6811         LDR        R1, [R2]
+  0x08000ED4:  23E0         MOVS       R3, #224
+  0x08000ED6:  4399         BICS       R1, R3
+  0x08000ED8:  6840         LDR        R0, [R0, #4]
+  0x08000EDA:  4308         ORRS       R0, R1
+  0x08000EDC:  6010         STR        R0, [R2]
+
.L11:
+  0x08000EDE:  4628         MOV        R0, R5
+  0x08000EE0:  B004         ADD        SP, SP, #16
+  0x08000EE2:  BDF0         POP        {R4-R7, PC}
+
.L12:
+  0x08000EE4:  4E0A         LDR        R6, =uwTick              ; [PC, #40] [0x08000F10] =0x2000068C 
+  0x08000EE6:  6837         LDR        R7, [R6]
+
.L13:
+  0x08000EE8:  6A14         LDR        R4, [R2, #32]
+  0x08000EEA:  07A4         LSLS       R4, R4, #30
+  0x08000EEC:  D407         BMI        .L14                     ; 0x08000EFE
+  0x08000EEE:  6834         LDR        R4, [R6]
+  0x08000EF0:  1BE4         SUBS       R4, R4, R7
+  0x08000EF2:  4908         LDR        R1, =0x00001388          ; [PC, #32] [0x08000F14] 
+  0x08000EF4:  428C         CMP        R4, R1
+  0x08000EF6:  D9F7         BLS        .L13                     ; 0x08000EE8
+  0x08000EF8:  9D01         LDR        R5, [SP, #4]
+  0x08000EFA:  9C00         LDR        R4, [SP, #0]
+  0x08000EFC:  E7BD         B          .L5                      ; 0x08000E7A
+
.L14:
+  0x08000EFE:  462F         MOV        R7, R5
+  0x08000F00:  9C00         LDR        R4, [SP, #0]
+  0x08000F02:  4902         LDR        R1, =0xFFFFFCFF          ; [PC, #8] [0x08000F0C] 
+  0x08000F04:  E7B3         B          .L4                      ; 0x08000E6E
+  0x08000F06:  46C0         NOP
+  0x08000F08:  4002103C     DC.W       0x4002103C
+  0x08000F0C:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08000F10:  2000068C     DC.W       uwTick
+  0x08000F14:  00001388     DC.W       0x00001388
+
+

Section .text.HAL_TIM_Base_Init from PowerPro_lto.o, size=204, align=4

+
+
HAL_TIM_Base_Init:
+  0x08000F18:  B570         PUSH       {R4-R6, LR}
+  0x08000F1A:  B086         SUB        SP, SP, #24
+  0x08000F1C:  2800         CMP        R0, #0
+  0x08000F1E:  D01A         BEQ        .L2                      ; 0x08000F56
+  0x08000F20:  4604         MOV        R4, R0
+  0x08000F22:  4605         MOV        R5, R0
+  0x08000F24:  353C         ADDS       R5, #60
+  0x08000F26:  7868         LDRB       R0, [R5, #1]
+  0x08000F28:  2800         CMP        R0, #0
+  0x08000F2A:  D017         BEQ        .L4                      ; 0x08000F5C
+
.L1:
+  0x08000F2C:  2002         MOVS       R0, #2
+  0x08000F2E:  7068         STRB       R0, [R5, #1]
+  0x08000F30:  CC01         LDM        R4!, {R0}
+  0x08000F32:  4621         MOV        R1, R4
+  0x08000F34:  F000 F856    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08000F38:  2001         MOVS       R0, #1
+  0x08000F3A:  7328         STRB       R0, [R5, #12]
+  0x08000F3C:  70A8         STRB       R0, [R5, #2]
+  0x08000F3E:  70E8         STRB       R0, [R5, #3]
+  0x08000F40:  7128         STRB       R0, [R5, #4]
+  0x08000F42:  7168         STRB       R0, [R5, #5]
+  0x08000F44:  71A8         STRB       R0, [R5, #6]
+  0x08000F46:  71E8         STRB       R0, [R5, #7]
+  0x08000F48:  7228         STRB       R0, [R5, #8]
+  0x08000F4A:  7268         STRB       R0, [R5, #9]
+  0x08000F4C:  72A8         STRB       R0, [R5, #10]
+  0x08000F4E:  72E8         STRB       R0, [R5, #11]
+  0x08000F50:  7068         STRB       R0, [R5, #1]
+  0x08000F52:  2000         MOVS       R0, #0
+  0x08000F54:  E000         B          .L3                      ; 0x08000F58
+
.L2:
+  0x08000F56:  2001         MOVS       R0, #1
+
.L3:
+  0x08000F58:  B006         ADD        SP, SP, #24
+  0x08000F5A:  BD70         POP        {R4-R6, PC}
+
.L4:
+  0x08000F5C:  7028         STRB       R0, [R5]
+  0x08000F5E:  6821         LDR        R1, [R4]
+  0x08000F60:  4A1B         LDR        R2, =0x40014800          ; [PC, #108] [0x08000FD0] 
+  0x08000F62:  4291         CMP        R1, R2
+  0x08000F64:  D029         BEQ        .L5                      ; 0x08000FBA
+  0x08000F66:  4A1B         LDR        R2, =0x40014400          ; [PC, #108] [0x08000FD4] 
+  0x08000F68:  4291         CMP        R1, R2
+  0x08000F6A:  D1DF         BNE        .L1                      ; 0x08000F2C
+  0x08000F6C:  491A         LDR        R1, =0x40021034          ; [PC, #104] [0x08000FD8] 
+  0x08000F6E:  68CA         LDR        R2, [R1, #12]
+  0x08000F70:  2601         MOVS       R6, #1
+  0x08000F72:  9603         STR        R6, [SP, #12]
+  0x08000F74:  0473         LSLS       R3, R6, #17
+  0x08000F76:  431A         ORRS       R2, R3
+  0x08000F78:  60CA         STR        R2, [R1, #12]
+  0x08000F7A:  68CA         LDR        R2, [R1, #12]
+  0x08000F7C:  401A         ANDS       R2, R3
+  0x08000F7E:  9200         STR        R2, [SP, #0]
+  0x08000F80:  9A00         LDR        R2, [SP, #0]
+  0x08000F82:  680A         LDR        R2, [R1]
+  0x08000F84:  4332         ORRS       R2, R6
+  0x08000F86:  600A         STR        R2, [R1]
+  0x08000F88:  6809         LDR        R1, [R1]
+  0x08000F8A:  4031         ANDS       R1, R6
+  0x08000F8C:  9100         STR        R1, [SP, #0]
+  0x08000F8E:  9004         STR        R0, [SP, #16]
+  0x08000F90:  2002         MOVS       R0, #2
+  0x08000F92:  9002         STR        R0, [SP, #8]
+  0x08000F94:  2040         MOVS       R0, #64
+  0x08000F96:  9001         STR        R0, [SP, #4]
+  0x08000F98:  9800         LDR        R0, [SP, #0]
+  0x08000F9A:  2005         MOVS       R0, #5
+  0x08000F9C:  9005         STR        R0, [SP, #20]
+  0x08000F9E:  0700         LSLS       R0, R0, #28
+  0x08000FA0:  A901         ADD        R1, SP, #4
+  0x08000FA2:  F7FF FE2B    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x08000FA6:  20FF         MOVS       R0, #255
+  0x08000FA8:  0200         LSLS       R0, R0, #8
+  0x08000FAA:  490C         LDR        R1, =0xE000E414          ; [PC, #48] [0x08000FDC] 
+  0x08000FAC:  680A         LDR        R2, [R1]
+  0x08000FAE:  4382         BICS       R2, R0
+  0x08000FB0:  600A         STR        R2, [R1]
+  0x08000FB2:  0570         LSLS       R0, R6, #21
+  0x08000FB4:  490A         LDR        R1, =0xE000E100          ; [PC, #40] [0x08000FE0] 
+  0x08000FB6:  6008         STR        R0, [R1]
+  0x08000FB8:  E7B8         B          .L1                      ; 0x08000F2C
+
.L5:
+  0x08000FBA:  2001         MOVS       R0, #1
+  0x08000FBC:  0480         LSLS       R0, R0, #18
+  0x08000FBE:  4906         LDR        R1, =0x40021034          ; [PC, #24] [0x08000FD8] 
+  0x08000FC0:  68CA         LDR        R2, [R1, #12]
+  0x08000FC2:  4302         ORRS       R2, R0
+  0x08000FC4:  60CA         STR        R2, [R1, #12]
+  0x08000FC6:  68C9         LDR        R1, [R1, #12]
+  0x08000FC8:  4001         ANDS       R1, R0
+  0x08000FCA:  9101         STR        R1, [SP, #4]
+  0x08000FCC:  9801         LDR        R0, [SP, #4]
+  0x08000FCE:  E7AD         B          .L1                      ; 0x08000F2C
+  0x08000FD0:  40014800     DC.W       0x40014800
+  0x08000FD4:  40014400     DC.W       0x40014400
+  0x08000FD8:  40021034     DC.W       0x40021034
+  0x08000FDC:  E000E414     DC.W       0xE000E414
+  0x08000FE0:  E000E100     DC.W       0xE000E100
+
+

Section .text.TIM_Base_SetConfig from PowerPro_lto.o, size=144, align=4

+
+
TIM_Base_SetConfig:
+  0x08000FE4:  B530         PUSH       {R4-R5, LR}
+  0x08000FE6:  6804         LDR        R4, [R0]
+  0x08000FE8:  4A1D         LDR        R2, =0x40012C00          ; [PC, #116] [0x08001060] 
+  0x08000FEA:  4290         CMP        R0, R2
+  0x08000FEC:  D004         BEQ        .L1                      ; 0x08000FF8
+  0x08000FEE:  4D1D         LDR        R5, =0x40000400          ; [PC, #116] [0x08001064] 
+  0x08000FF0:  42A8         CMP        R0, R5
+  0x08000FF2:  D006         BEQ        .L2                      ; 0x08001002
+  0x08000FF4:  4623         MOV        R3, R4
+  0x08000FF6:  E008         B          .L3                      ; 0x0800100A
+
.L1:
+  0x08000FF8:  2370         MOVS       R3, #112
+  0x08000FFA:  439C         BICS       R4, R3
+  0x08000FFC:  684B         LDR        R3, [R1, #4]
+  0x08000FFE:  4323         ORRS       R3, R4
+  0x08001000:  E00F         B          .L4                      ; 0x08001022
+
.L2:
+  0x08001002:  2370         MOVS       R3, #112
+  0x08001004:  439C         BICS       R4, R3
+  0x08001006:  684B         LDR        R3, [R1, #4]
+  0x08001008:  4323         ORRS       R3, R4
+
.L3:
+  0x0800100A:  42A8         CMP        R0, R5
+  0x0800100C:  D009         BEQ        .L4                      ; 0x08001022
+  0x0800100E:  4C16         LDR        R4, =0x40002000          ; [PC, #88] [0x08001068] 
+  0x08001010:  42A0         CMP        R0, R4
+  0x08001012:  D006         BEQ        .L4                      ; 0x08001022
+  0x08001014:  4C15         LDR        R4, =0x40014800          ; [PC, #84] [0x0800106C] 
+  0x08001016:  42A0         CMP        R0, R4
+  0x08001018:  D003         BEQ        .L4                      ; 0x08001022
+  0x0800101A:  4C15         LDR        R4, =0x40014400          ; [PC, #84] [0x08001070] 
+  0x0800101C:  42A0         CMP        R0, R4
+  0x0800101E:  461C         MOV        R4, R3
+  0x08001020:  D104         BNE        .L5                      ; 0x0800102C
+
.L4:
+  0x08001022:  2403         MOVS       R4, #3
+  0x08001024:  0224         LSLS       R4, R4, #8
+  0x08001026:  43A3         BICS       R3, R4
+  0x08001028:  68CC         LDR        R4, [R1, #12]
+  0x0800102A:  431C         ORRS       R4, R3
+
.L5:
+  0x0800102C:  4290         CMP        R0, R2
+  0x0800102E:  688A         LDR        R2, [R1, #8]
+  0x08001030:  62C2         STR        R2, [R0, #44]
+  0x08001032:  680A         LDR        R2, [R1]
+  0x08001034:  6282         STR        R2, [R0, #40]
+  0x08001036:  694A         LDR        R2, [R1, #20]
+  0x08001038:  D005         BEQ        .L6                      ; 0x08001046
+  0x0800103A:  4B0C         LDR        R3, =0x40014800          ; [PC, #48] [0x0800106C] 
+  0x0800103C:  4298         CMP        R0, R3
+  0x0800103E:  D002         BEQ        .L6                      ; 0x08001046
+  0x08001040:  4B0B         LDR        R3, =0x40014400          ; [PC, #44] [0x08001070] 
+  0x08001042:  4298         CMP        R0, R3
+  0x08001044:  D101         BNE        .L7                      ; 0x0800104A
+
.L6:
+  0x08001046:  6909         LDR        R1, [R1, #16]
+  0x08001048:  6301         STR        R1, [R0, #48]
+
.L7:
+  0x0800104A:  6801         LDR        R1, [R0]
+  0x0800104C:  2304         MOVS       R3, #4
+  0x0800104E:  430B         ORRS       R3, R1
+  0x08001050:  6003         STR        R3, [R0]
+  0x08001052:  2101         MOVS       R1, #1
+  0x08001054:  6141         STR        R1, [R0, #20]
+  0x08001056:  2180         MOVS       R1, #128
+  0x08001058:  438C         BICS       R4, R1
+  0x0800105A:  4314         ORRS       R4, R2
+  0x0800105C:  6004         STR        R4, [R0]
+  0x0800105E:  BD30         POP        {R4-R5, PC}
+  0x08001060:  40012C00     DC.W       0x40012C00
+  0x08001064:  40000400     DC.W       0x40000400
+  0x08001068:  40002000     DC.W       0x40002000
+  0x0800106C:  40014800     DC.W       0x40014800
+  0x08001070:  40014400     DC.W       0x40014400
+
+

Section .text.HAL_UART_Init from PowerPro_lto.o, size=972, align=4

+
+
HAL_UART_Init:
+  0x08001074:  B5F0         PUSH       {R4-R7, LR}
+  0x08001076:  B091         SUB        SP, SP, #68
+  0x08001078:  4EE0         LDR        R6, =huart1              ; [PC, #0x0380] [0x080013FC] =0x200003BC 
+  0x0800107A:  2488         MOVS       R4, #136
+  0x0800107C:  5930         LDR        R0, [R6, R4]
+  0x0800107E:  2800         CMP        R0, #0
+  0x08001080:  6835         LDR        R5, [R6]
+  0x08001082:  9403         STR        R4, [SP, #12]
+  0x08001084:  D168         BNE        .L4                      ; 0x08001158
+  0x08001086:  2084         MOVS       R0, #132
+  0x08001088:  2700         MOVS       R7, #0
+  0x0800108A:  5437         STRB       R7, [R6, R0]
+  0x0800108C:  A805         ADD        R0, SP, #20
+  0x0800108E:  1D00         ADDS       R0, R0, #4
+  0x08001090:  2118         MOVS       R1, #24
+  0x08001092:  F005 F88C    BL         __aeabi_memclr           ; 0x080061AE
+  0x08001096:  48DA         LDR        R0, =0x40013800          ; [PC, #0x0368] [0x08001400] 
+  0x08001098:  4285         CMP        R5, R0
+  0x0800109A:  D15D         BNE        .L4                      ; 0x08001158
+  0x0800109C:  2401         MOVS       R4, #1
+  0x0800109E:  9405         STR        R4, [SP, #20]
+  0x080010A0:  A805         ADD        R0, SP, #20
+  0x080010A2:  F7FF FEB3    BL         HAL_RCCEx_PeriphCLKConfig ; 0x08000E0C
+  0x080010A6:  2800         CMP        R0, #0
+  0x080010A8:  D000         BEQ        .L1                      ; 0x080010AC
+  0x080010AA:  E1A5         B          .L31                     ; 0x080013F8
+
.L1:
+  0x080010AC:  48D5         LDR        R0, =0x40021000          ; [PC, #0x0354] [0x08001404] 
+  0x080010AE:  6C01         LDR        R1, [R0, #64]
+  0x080010B0:  9410         STR        R4, [SP, #64]
+  0x080010B2:  03A2         LSLS       R2, R4, #14
+  0x080010B4:  4311         ORRS       R1, R2
+  0x080010B6:  6401         STR        R1, [R0, #64]
+  0x080010B8:  6C01         LDR        R1, [R0, #64]
+  0x080010BA:  4011         ANDS       R1, R2
+  0x080010BC:  9104         STR        R1, [SP, #16]
+  0x080010BE:  9904         LDR        R1, [SP, #16]
+  0x080010C0:  6B41         LDR        R1, [R0, #52]
+  0x080010C2:  4321         ORRS       R1, R4
+  0x080010C4:  6341         STR        R1, [R0, #52]
+  0x080010C6:  6B40         LDR        R0, [R0, #52]
+  0x080010C8:  9401         STR        R4, [SP, #4]
+  0x080010CA:  4020         ANDS       R0, R4
+  0x080010CC:  9004         STR        R0, [SP, #16]
+  0x080010CE:  970F         STR        R7, [SP, #60]
+  0x080010D0:  970E         STR        R7, [SP, #56]
+  0x080010D2:  2002         MOVS       R0, #2
+  0x080010D4:  900D         STR        R0, [SP, #52]
+  0x080010D6:  2003         MOVS       R0, #3
+  0x080010D8:  0240         LSLS       R0, R0, #9
+  0x080010DA:  900C         STR        R0, [SP, #48]
+  0x080010DC:  9804         LDR        R0, [SP, #16]
+  0x080010DE:  2005         MOVS       R0, #5
+  0x080010E0:  0700         LSLS       R0, R0, #28
+  0x080010E2:  A90C         ADD        R1, SP, #48
+  0x080010E4:  F7FF FD8A    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x080010E8:  4CC7         LDR        R4, =hdma_usart1_rx      ; [PC, #0x031C] [0x08001408] =0x20000510 
+  0x080010EA:  2180         MOVS       R1, #128
+  0x080010EC:  2032         MOVS       R0, #50
+  0x080010EE:  4DC7         LDR        R5, =0x4002001C          ; [PC, #0x031C] [0x0800140C] 
+  0x080010F0:  6025         STR        R5, [R4]
+  0x080010F2:  6060         STR        R0, [R4, #4]
+  0x080010F4:  60A7         STR        R7, [R4, #8]
+  0x080010F6:  60E7         STR        R7, [R4, #12]
+  0x080010F8:  9102         STR        R1, [SP, #8]
+  0x080010FA:  6121         STR        R1, [R4, #16]
+  0x080010FC:  6167         STR        R7, [R4, #20]
+  0x080010FE:  61A7         STR        R7, [R4, #24]
+  0x08001100:  61E7         STR        R7, [R4, #28]
+  0x08001102:  6227         STR        R7, [R4, #32]
+  0x08001104:  4620         MOV        R0, R4
+  0x08001106:  F7FF FC1D    BL         HAL_DMA_Init             ; 0x08000944
+  0x0800110A:  2800         CMP        R0, #0
+  0x0800110C:  D000         BEQ        .L2                      ; 0x08001110
+  0x0800110E:  E173         B          .L31                     ; 0x080013F8
+
.L2:
+  0x08001110:  9A02         LDR        R2, [SP, #8]
+  0x08001112:  50B4         STR        R4, [R6, R2]
+  0x08001114:  62A6         STR        R6, [R4, #40]
+  0x08001116:  4CBE         LDR        R4, =hdma_usart1_tx      ; [PC, #0x02F8] [0x08001410] =0x200004B4 
+  0x08001118:  2010         MOVS       R0, #16
+  0x0800111A:  2133         MOVS       R1, #51
+  0x0800111C:  6227         STR        R7, [R4, #32]
+  0x0800111E:  3514         ADDS       R5, #20
+  0x08001120:  6025         STR        R5, [R4]
+  0x08001122:  6061         STR        R1, [R4, #4]
+  0x08001124:  60A0         STR        R0, [R4, #8]
+  0x08001126:  60E7         STR        R7, [R4, #12]
+  0x08001128:  6122         STR        R2, [R4, #16]
+  0x0800112A:  6167         STR        R7, [R4, #20]
+  0x0800112C:  61A7         STR        R7, [R4, #24]
+  0x0800112E:  61E7         STR        R7, [R4, #28]
+  0x08001130:  4620         MOV        R0, R4
+  0x08001132:  F7FF FC07    BL         HAL_DMA_Init             ; 0x08000944
+  0x08001136:  2800         CMP        R0, #0
+  0x08001138:  D000         BEQ        .L3                      ; 0x0800113C
+  0x0800113A:  E15D         B          .L31                     ; 0x080013F8
+
.L3:
+  0x0800113C:  62A6         STR        R6, [R4, #40]
+  0x0800113E:  67F4         STR        R4, [R6, #124]
+  0x08001140:  20FF         MOVS       R0, #255
+  0x08001142:  0600         LSLS       R0, R0, #24
+  0x08001144:  49B3         LDR        R1, =0xE000E418          ; [PC, #0x02CC] [0x08001414] 
+  0x08001146:  680A         LDR        R2, [R1]
+  0x08001148:  4382         BICS       R2, R0
+  0x0800114A:  600A         STR        R2, [R1]
+  0x0800114C:  9801         LDR        R0, [SP, #4]
+  0x0800114E:  06C0         LSLS       R0, R0, #27
+  0x08001150:  49B1         LDR        R1, =0xE000E100          ; [PC, #0x02C4] [0x08001418] 
+  0x08001152:  6008         STR        R0, [R1]
+  0x08001154:  6835         LDR        R5, [R6]
+  0x08001156:  9C03         LDR        R4, [SP, #12]
+
.L4:
+  0x08001158:  2024         MOVS       R0, #36
+  0x0800115A:  5130         STR        R0, [R6, R4]
+  0x0800115C:  6828         LDR        R0, [R5]
+  0x0800115E:  2401         MOVS       R4, #1
+  0x08001160:  43A0         BICS       R0, R4
+  0x08001162:  6028         STR        R0, [R5]
+  0x08001164:  6AB0         LDR        R0, [R6, #40]
+  0x08001166:  2800         CMP        R0, #0
+  0x08001168:  D048         BEQ        .L12                     ; 0x080011FC
+  0x0800116A:  0701         LSLS       R1, R0, #28
+  0x0800116C:  D505         BPL        .L5                      ; 0x0800117A
+  0x0800116E:  03E1         LSLS       R1, R4, #15
+  0x08001170:  686A         LDR        R2, [R5, #4]
+  0x08001172:  438A         BICS       R2, R1
+  0x08001174:  6BB1         LDR        R1, [R6, #56]
+  0x08001176:  4311         ORRS       R1, R2
+  0x08001178:  6069         STR        R1, [R5, #4]
+
.L5:
+  0x0800117A:  07C1         LSLS       R1, R0, #31
+  0x0800117C:  D005         BEQ        .L6                      ; 0x0800118A
+  0x0800117E:  0461         LSLS       R1, R4, #17
+  0x08001180:  686A         LDR        R2, [R5, #4]
+  0x08001182:  438A         BICS       R2, R1
+  0x08001184:  6AF1         LDR        R1, [R6, #44]
+  0x08001186:  4311         ORRS       R1, R2
+  0x08001188:  6069         STR        R1, [R5, #4]
+
.L6:
+  0x0800118A:  0781         LSLS       R1, R0, #30
+  0x0800118C:  D505         BPL        .L7                      ; 0x0800119A
+  0x0800118E:  0421         LSLS       R1, R4, #16
+  0x08001190:  686A         LDR        R2, [R5, #4]
+  0x08001192:  438A         BICS       R2, R1
+  0x08001194:  6B31         LDR        R1, [R6, #48]
+  0x08001196:  4311         ORRS       R1, R2
+  0x08001198:  6069         STR        R1, [R5, #4]
+
.L7:
+  0x0800119A:  0741         LSLS       R1, R0, #29
+  0x0800119C:  D505         BPL        .L8                      ; 0x080011AA
+  0x0800119E:  04A1         LSLS       R1, R4, #18
+  0x080011A0:  686A         LDR        R2, [R5, #4]
+  0x080011A2:  438A         BICS       R2, R1
+  0x080011A4:  6B71         LDR        R1, [R6, #52]
+  0x080011A6:  4311         ORRS       R1, R2
+  0x080011A8:  6069         STR        R1, [R5, #4]
+
.L8:
+  0x080011AA:  06C1         LSLS       R1, R0, #27
+  0x080011AC:  D505         BPL        .L9                      ; 0x080011BA
+  0x080011AE:  0321         LSLS       R1, R4, #12
+  0x080011B0:  68AA         LDR        R2, [R5, #8]
+  0x080011B2:  438A         BICS       R2, R1
+  0x080011B4:  6BF1         LDR        R1, [R6, #60]
+  0x080011B6:  4311         ORRS       R1, R2
+  0x080011B8:  60A9         STR        R1, [R5, #8]
+
.L9:
+  0x080011BA:  0681         LSLS       R1, R0, #26
+  0x080011BC:  D505         BPL        .L10                     ; 0x080011CA
+  0x080011BE:  0361         LSLS       R1, R4, #13
+  0x080011C0:  68AA         LDR        R2, [R5, #8]
+  0x080011C2:  438A         BICS       R2, R1
+  0x080011C4:  6C31         LDR        R1, [R6, #64]
+  0x080011C6:  4311         ORRS       R1, R2
+  0x080011C8:  60A9         STR        R1, [R5, #8]
+
.L10:
+  0x080011CA:  0641         LSLS       R1, R0, #25
+  0x080011CC:  D50E         BPL        .L11                     ; 0x080011EC
+  0x080011CE:  0521         LSLS       R1, R4, #20
+  0x080011D0:  686A         LDR        R2, [R5, #4]
+  0x080011D2:  438A         BICS       R2, R1
+  0x080011D4:  6C73         LDR        R3, [R6, #68]
+  0x080011D6:  431A         ORRS       R2, R3
+  0x080011D8:  606A         STR        R2, [R5, #4]
+  0x080011DA:  428B         CMP        R3, R1
+  0x080011DC:  D106         BNE        .L11                     ; 0x080011EC
+  0x080011DE:  2103         MOVS       R1, #3
+  0x080011E0:  0549         LSLS       R1, R1, #21
+  0x080011E2:  686A         LDR        R2, [R5, #4]
+  0x080011E4:  438A         BICS       R2, R1
+  0x080011E6:  6CB1         LDR        R1, [R6, #72]
+  0x080011E8:  4311         ORRS       R1, R2
+  0x080011EA:  6069         STR        R1, [R5, #4]
+
.L11:
+  0x080011EC:  0600         LSLS       R0, R0, #24
+  0x080011EE:  D505         BPL        .L12                     ; 0x080011FC
+  0x080011F0:  04E0         LSLS       R0, R4, #19
+  0x080011F2:  6869         LDR        R1, [R5, #4]
+  0x080011F4:  4381         BICS       R1, R0
+  0x080011F6:  6CF0         LDR        R0, [R6, #76]
+  0x080011F8:  4308         ORRS       R0, R1
+  0x080011FA:  6068         STR        R0, [R5, #4]
+
.L12:
+  0x080011FC:  6828         LDR        R0, [R5]
+  0x080011FE:  4987         LDR        R1, =0xCFFF69F3          ; [PC, #0x021C] [0x0800141C] 
+  0x08001200:  4001         ANDS       R1, R0
+  0x08001202:  68B0         LDR        R0, [R6, #8]
+  0x08001204:  6932         LDR        R2, [R6, #16]
+  0x08001206:  4302         ORRS       R2, R0
+  0x08001208:  6970         LDR        R0, [R6, #20]
+  0x0800120A:  4310         ORRS       R0, R2
+  0x0800120C:  4308         ORRS       R0, R1
+  0x0800120E:  69F1         LDR        R1, [R6, #28]
+  0x08001210:  4308         ORRS       R0, R1
+  0x08001212:  6028         STR        R0, [R5]
+  0x08001214:  2003         MOVS       R0, #3
+  0x08001216:  9002         STR        R0, [SP, #8]
+  0x08001218:  0300         LSLS       R0, R0, #12
+  0x0800121A:  686A         LDR        R2, [R5, #4]
+  0x0800121C:  4382         BICS       R2, R0
+  0x0800121E:  68F0         LDR        R0, [R6, #12]
+  0x08001220:  4310         ORRS       R0, R2
+  0x08001222:  6068         STR        R0, [R5, #4]
+  0x08001224:  69B0         LDR        R0, [R6, #24]
+  0x08001226:  6A32         LDR        R2, [R6, #32]
+  0x08001228:  4302         ORRS       R2, R0
+  0x0800122A:  68A8         LDR        R0, [R5, #8]
+  0x0800122C:  4B7C         LDR        R3, =0x11FFF4FF          ; [PC, #0x01F0] [0x08001420] 
+  0x0800122E:  4003         ANDS       R3, R0
+  0x08001230:  4313         ORRS       R3, R2
+  0x08001232:  60AB         STR        R3, [R5, #8]
+  0x08001234:  6AE8         LDR        R0, [R5, #44]
+  0x08001236:  220F         MOVS       R2, #15
+  0x08001238:  4390         BICS       R0, R2
+  0x0800123A:  6A77         LDR        R7, [R6, #36]
+  0x0800123C:  4338         ORRS       R0, R7
+  0x0800123E:  62E8         STR        R0, [R5, #44]
+  0x08001240:  4878         LDR        R0, =0x40004400          ; [PC, #0x01E0] [0x08001424] 
+  0x08001242:  4285         CMP        R5, R0
+  0x08001244:  D009         BEQ        .L13                     ; 0x0800125A
+  0x08001246:  486E         LDR        R0, =0x40013800          ; [PC, #0x01B8] [0x08001400] 
+  0x08001248:  4285         CMP        R5, R0
+  0x0800124A:  D108         BNE        .L14                     ; 0x0800125E
+  0x0800124C:  486D         LDR        R0, =0x40021000          ; [PC, #0x01B4] [0x08001404] 
+  0x0800124E:  6D40         LDR        R0, [R0, #84]
+  0x08001250:  0780         LSLS       R0, R0, #30
+  0x08001252:  0F00         LSRS       R0, R0, #28
+  0x08001254:  4A74         LDR        R2, =0x080051BC          ; [PC, #0x01D0] [0x08001428] 
+  0x08001256:  5812         LDR        R2, [R2, R0]
+  0x08001258:  E002         B          .L15                     ; 0x08001260
+
.L13:
+  0x0800125A:  2200         MOVS       R2, #0
+  0x0800125C:  E000         B          .L15                     ; 0x08001260
+
.L14:
+  0x0800125E:  2210         MOVS       R2, #16
+
.L15:
+  0x08001260:  03E0         LSLS       R0, R4, #15
+  0x08001262:  4281         CMP        R1, R0
+  0x08001264:  D10E         BNE        .L17                     ; 0x08001284
+  0x08001266:  2A08         CMP        R2, #8
+  0x08001268:  D900         BLS        .L16                     ; 0x0800126C
+  0x0800126A:  E08C         B          .L25                     ; 0x08001386
+
.L16:
+  0x0800126C:  447A         ADD        R2, PC
+  0x0800126E:  7912         LDRB       R2, [R2, #4]
+  0x08001270:  0052         LSLS       R2, R2, #1
+  0x08001272:  4497         ADD        PC, R2
+  0x08001274:  04           DC.B       0x04                     ; '\x04'
+  0x08001275:  88           DC.B       0x88                     ; '\x88'
+  0x08001276:  17           DC.B       0x17                     ; '\x17'
+  0x08001277:  88           DC.B       0x88                     ; '\x88'
+  0x08001278:  29           DC.B       0x29                     ; ')'
+  0x08001279:  88           DC.B       0x88                     ; '\x88'
+  0x0800127A:  88           DC.B       0x88                     ; '\x88'
+  0x0800127B:  88           DC.B       0x88                     ; '\x88'
+  0x0800127C:  2E           DC.B       0x2E                     ; '.'
+  0x0800127D:  00           DC.B       0x00                     ; '\0'
+  0x0800127E:  F7FF FDA5    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x08001282:  E023         B          .L19                     ; 0x080012CC
+
.L17:
+  0x08001284:  2A08         CMP        R2, #8
+  0x08001286:  D900         BLS        .L18                     ; 0x0800128A
+  0x08001288:  E07D         B          .L25                     ; 0x08001386
+
.L18:
+  0x0800128A:  46C0         NOP
+  0x0800128C:  447A         ADD        R2, PC
+  0x0800128E:  7912         LDRB       R2, [R2, #4]
+  0x08001290:  0052         LSLS       R2, R2, #1
+  0x08001292:  4497         ADD        PC, R2
+  0x08001294:  04           DC.B       0x04                     ; '\x04'
+  0x08001295:  78           DC.B       0x78                     ; 'x'
+  0x08001296:  10           DC.B       0x10                     ; '\x10'
+  0x08001297:  78           DC.B       0x78                     ; 'x'
+  0x08001298:  33           DC.B       0x33                     ; '3'
+  0x08001299:  78           DC.B       0x78                     ; 'x'
+  0x0800129A:  78           DC.B       0x78                     ; 'x'
+  0x0800129B:  78           DC.B       0x78                     ; 'x'
+  0x0800129C:  38           DC.B       0x38                     ; '8'
+  0x0800129D:  00           DC.B       0x00                     ; '\0'
+  0x0800129E:  F7FF FD95    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x080012A2:  E02D         B          .L21                     ; 0x08001300
+  0x080012A4:  4857         LDR        R0, =0x40021000          ; [PC, #0x015C] [0x08001404] 
+  0x080012A6:  6800         LDR        R0, [R0]
+  0x080012A8:  0600         LSLS       R0, R0, #24
+  0x080012AA:  0F40         LSRS       R0, R0, #29
+  0x080012AC:  1C41         ADDS       R1, R0, #1
+  0x080012AE:  485F         LDR        R0, =0x02DC6C00          ; [PC, #0x017C] [0x0800142C] 
+  0x080012B0:  F004 FEE7    BL         __aeabi_uidiv            ; 0x08006082
+  0x080012B4:  E00D         B          .L20                     ; 0x080012D2
+  0x080012B6:  4853         LDR        R0, =0x40021000          ; [PC, #0x014C] [0x08001404] 
+  0x080012B8:  6800         LDR        R0, [R0]
+  0x080012BA:  0600         LSLS       R0, R0, #24
+  0x080012BC:  0F40         LSRS       R0, R0, #29
+  0x080012BE:  1C41         ADDS       R1, R0, #1
+  0x080012C0:  485A         LDR        R0, =0x02DC6C00          ; [PC, #0x0168] [0x0800142C] 
+  0x080012C2:  F004 FEDE    BL         __aeabi_uidiv            ; 0x08006082
+  0x080012C6:  E01E         B          .L22                     ; 0x08001306
+  0x080012C8:  F7FF FD56    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+
.L19:
+  0x080012CC:  2800         CMP        R0, #0
+  0x080012CE:  D02B         BEQ        .L24                     ; 0x08001328
+  0x080012D0:  6A77         LDR        R7, [R6, #36]
+
.L20:
+  0x080012D2:  0079         LSLS       R1, R7, #1
+  0x080012D4:  4A56         LDR        R2, =UARTPrescTable      ; [PC, #0x0158] [0x08001430] =0x08005EEA 
+  0x080012D6:  5A51         LDRH       R1, [R2, R1]
+  0x080012D8:  F004 FED3    BL         __aeabi_uidiv            ; 0x08006082
+  0x080012DC:  0040         LSLS       R0, R0, #1
+  0x080012DE:  6871         LDR        R1, [R6, #4]
+  0x080012E0:  084A         LSRS       R2, R1, #1
+  0x080012E2:  1810         ADDS       R0, R2, R0
+  0x080012E4:  F004 FECD    BL         __aeabi_uidiv            ; 0x08006082
+  0x080012E8:  4602         MOV        R2, R0
+  0x080012EA:  3A10         SUBS       R2, #16
+  0x080012EC:  4951         LDR        R1, =0x0000FFF0          ; [PC, #0x0144] [0x08001434] 
+  0x080012EE:  428A         CMP        R2, R1
+  0x080012F0:  D249         BCS        .L25                     ; 0x08001386
+  0x080012F2:  4001         ANDS       R1, R0
+  0x080012F4:  0700         LSLS       R0, R0, #28
+  0x080012F6:  0F40         LSRS       R0, R0, #29
+  0x080012F8:  4308         ORRS       R0, R1
+  0x080012FA:  E013         B          .L23                     ; 0x08001324
+  0x080012FC:  F7FF FD3C    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+
.L21:
+  0x08001300:  2800         CMP        R0, #0
+  0x08001302:  D011         BEQ        .L24                     ; 0x08001328
+  0x08001304:  6A77         LDR        R7, [R6, #36]
+
.L22:
+  0x08001306:  0079         LSLS       R1, R7, #1
+  0x08001308:  4A49         LDR        R2, =UARTPrescTable      ; [PC, #0x0124] [0x08001430] =0x08005EEA 
+  0x0800130A:  5A51         LDRH       R1, [R2, R1]
+  0x0800130C:  F004 FEB9    BL         __aeabi_uidiv            ; 0x08006082
+  0x08001310:  6871         LDR        R1, [R6, #4]
+  0x08001312:  084A         LSRS       R2, R1, #1
+  0x08001314:  1810         ADDS       R0, R2, R0
+  0x08001316:  F004 FEB4    BL         __aeabi_uidiv            ; 0x08006082
+  0x0800131A:  4601         MOV        R1, R0
+  0x0800131C:  3910         SUBS       R1, #16
+  0x0800131E:  4A45         LDR        R2, =0x0000FFF0          ; [PC, #0x0114] [0x08001434] 
+  0x08001320:  4291         CMP        R1, R2
+  0x08001322:  D230         BCS        .L25                     ; 0x08001386
+
.L23:
+  0x08001324:  6831         LDR        R1, [R6]
+  0x08001326:  60C8         STR        R0, [R1, #12]
+
.L24:
+  0x08001328:  2009         MOVS       R0, #9
+  0x0800132A:  9001         STR        R0, [SP, #4]
+  0x0800132C:  02C1         LSLS       R1, R0, #11
+  0x0800132E:  6830         LDR        R0, [R6]
+  0x08001330:  6842         LDR        R2, [R0, #4]
+  0x08001332:  438A         BICS       R2, R1
+  0x08001334:  6042         STR        R2, [R0, #4]
+  0x08001336:  6881         LDR        R1, [R0, #8]
+  0x08001338:  222A         MOVS       R2, #42
+  0x0800133A:  4391         BICS       R1, R2
+  0x0800133C:  6081         STR        R1, [R0, #8]
+  0x0800133E:  6801         LDR        R1, [R0]
+  0x08001340:  4321         ORRS       R1, R4
+  0x08001342:  6001         STR        R1, [R0]
+  0x08001344:  2190         MOVS       R1, #144
+  0x08001346:  2700         MOVS       R7, #0
+  0x08001348:  5077         STR        R7, [R6, R1]
+  0x0800134A:  6777         STR        R7, [R6, #116]
+  0x0800134C:  67B7         STR        R7, [R6, #120]
+  0x0800134E:  493A         LDR        R1, =0x00010001          ; [PC, #232] [0x08001438] 
+  0x08001350:  66B1         STR        R1, [R6, #104]
+  0x08001352:  493A         LDR        R1, =uwTick              ; [PC, #232] [0x0800143C] =0x2000068C 
+  0x08001354:  680D         LDR        R5, [R1]
+  0x08001356:  6801         LDR        R1, [R0]
+  0x08001358:  0709         LSLS       R1, R1, #28
+  0x0800135A:  D51B         BPL        .L27                     ; 0x08001394
+  0x0800135C:  0560         LSLS       R0, R4, #21
+  0x0800135E:  4629         MOV        R1, R5
+  0x08001360:  F000 F86E    BL         UART_WaitOnFlagUntilTimeout ; 0x08001440
+  0x08001364:  2800         CMP        R0, #0
+  0x08001366:  D014         BEQ        .L26                     ; 0x08001392
+  0x08001368:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800136C:  F384 8810    MSR        PRIMASK, R4
+  0x08001370:  6831         LDR        R1, [R6]
+  0x08001372:  680A         LDR        R2, [R1]
+  0x08001374:  2380         MOVS       R3, #128
+  0x08001376:  439A         BICS       R2, R3
+  0x08001378:  600A         STR        R2, [R1]
+  0x0800137A:  F380 8810    MSR        PRIMASK, R0
+  0x0800137E:  2020         MOVS       R0, #32
+  0x08001380:  9C02         LDR        R4, [SP, #8]
+  0x08001382:  9A03         LDR        R2, [SP, #12]
+  0x08001384:  E032         B          .L29                     ; 0x080013EC
+
.L25:
+  0x08001386:  2000         MOVS       R0, #0
+  0x08001388:  6770         STR        R0, [R6, #116]
+  0x0800138A:  67B0         STR        R0, [R6, #120]
+  0x0800138C:  482A         LDR        R0, =0x00010001          ; [PC, #168] [0x08001438] 
+  0x0800138E:  66B0         STR        R0, [R6, #104]
+  0x08001390:  E02F         B          .L30                     ; 0x080013F2
+
.L26:
+  0x08001392:  6830         LDR        R0, [R6]
+
.L27:
+  0x08001394:  6800         LDR        R0, [R0]
+  0x08001396:  0740         LSLS       R0, R0, #29
+  0x08001398:  D51F         BPL        .L28                     ; 0x080013DA
+  0x0800139A:  05A0         LSLS       R0, R4, #22
+  0x0800139C:  4629         MOV        R1, R5
+  0x0800139E:  F000 F84F    BL         UART_WaitOnFlagUntilTimeout ; 0x08001440
+  0x080013A2:  2800         CMP        R0, #0
+  0x080013A4:  D019         BEQ        .L28                     ; 0x080013DA
+  0x080013A6:  F3EF 8010    MRS        R0, PRIMASK
+  0x080013AA:  F384 8810    MSR        PRIMASK, R4
+  0x080013AE:  9901         LDR        R1, [SP, #4]
+  0x080013B0:  0149         LSLS       R1, R1, #5
+  0x080013B2:  6832         LDR        R2, [R6]
+  0x080013B4:  6813         LDR        R3, [R2]
+  0x080013B6:  438B         BICS       R3, R1
+  0x080013B8:  6013         STR        R3, [R2]
+  0x080013BA:  F380 8810    MSR        PRIMASK, R0
+  0x080013BE:  F3EF 8010    MRS        R0, PRIMASK
+  0x080013C2:  F384 8810    MSR        PRIMASK, R4
+  0x080013C6:  6831         LDR        R1, [R6]
+  0x080013C8:  688A         LDR        R2, [R1, #8]
+  0x080013CA:  43A2         BICS       R2, R4
+  0x080013CC:  608A         STR        R2, [R1, #8]
+  0x080013CE:  F380 8810    MSR        PRIMASK, R0
+  0x080013D2:  2020         MOVS       R0, #32
+  0x080013D4:  228C         MOVS       R2, #140
+  0x080013D6:  9C02         LDR        R4, [SP, #8]
+  0x080013D8:  E008         B          .L29                     ; 0x080013EC
+
.L28:
+  0x080013DA:  2088         MOVS       R0, #136
+  0x080013DC:  2120         MOVS       R1, #32
+  0x080013DE:  5031         STR        R1, [R6, R0]
+  0x080013E0:  208C         MOVS       R0, #140
+  0x080013E2:  5031         STR        R1, [R6, R0]
+  0x080013E4:  66F7         STR        R7, [R6, #108]
+  0x080013E6:  2270         MOVS       R2, #112
+  0x080013E8:  4638         MOV        R0, R7
+  0x080013EA:  463C         MOV        R4, R7
+
.L29:
+  0x080013EC:  2184         MOVS       R1, #132
+  0x080013EE:  5477         STRB       R7, [R6, R1]
+  0x080013F0:  50B0         STR        R0, [R6, R2]
+
.L30:
+  0x080013F2:  4620         MOV        R0, R4
+  0x080013F4:  B011         ADD        SP, SP, #68
+  0x080013F6:  BDF0         POP        {R4-R7, PC}
+
.L31:
+  0x080013F8:  F004 FD75    BL         Error_Handler            ; 0x08005EE6
+  0x080013FC:  200003BC     DC.W       huart1
+  0x08001400:  40013800     DC.W       0x40013800
+  0x08001404:  40021000     DC.W       0x40021000
+  0x08001408:  20000510     DC.W       hdma_usart1_rx
+  0x0800140C:  4002001C     DC.W       0x4002001C
+  0x08001410:  200004B4     DC.W       hdma_usart1_tx
+  0x08001414:  E000E418     DC.W       0xE000E418
+  0x08001418:  E000E100     DC.W       0xE000E100
+  0x0800141C:  CFFF69F3     DC.W       0xCFFF69F3
+  0x08001420:  11FFF4FF     DC.W       0x11FFF4FF
+  0x08001424:  40004400     DC.W       0x40004400
+  0x08001428:  080051BC     DC.W       080051BC               ; R_ARM_ABS32
+  0x0800142C:  02DC6C00     DC.W       0x02DC6C00
+  0x08001430:  08005EEA     DC.W       UARTPrescTable
+  0x08001434:  0000FFF0     DC.W       0x0000FFF0
+  0x08001438:  00010001     DC.W       0x00010001
+  0x0800143C:  2000068C     DC.W       uwTick
+
+

Section .text.UART_WaitOnFlagUntilTimeout from PowerPro_lto.o, size=96, align=4

+
+
UART_WaitOnFlagUntilTimeout:
+  0x08001440:  B570         PUSH       {R4-R6, LR}
+  0x08001442:  4D15         LDR        R5, =huart1              ; [PC, #84] [0x08001498] =0x200003BC 
+  0x08001444:  682A         LDR        R2, [R5]
+  0x08001446:  2401         MOVS       R4, #1
+  0x08001448:  02E3         LSLS       R3, R4, #11
+
.L1:
+  0x0800144A:  69D6         LDR        R6, [R2, #28]
+  0x0800144C:  4006         ANDS       R6, R0
+  0x0800144E:  4286         CMP        R6, R0
+  0x08001450:  D010         BEQ        .L2                      ; 0x08001474
+  0x08001452:  4E12         LDR        R6, =uwTick              ; [PC, #72] [0x0800149C] =0x2000068C 
+  0x08001454:  6836         LDR        R6, [R6]
+  0x08001456:  1A76         SUBS       R6, R6, R1
+  0x08001458:  0E76         LSRS       R6, R6, #25
+  0x0800145A:  D10D         BNE        .L3                      ; 0x08001478
+  0x0800145C:  6816         LDR        R6, [R2]
+  0x0800145E:  0776         LSLS       R6, R6, #29
+  0x08001460:  D5F3         BPL        .L1                      ; 0x0800144A
+  0x08001462:  69D6         LDR        R6, [R2, #28]
+  0x08001464:  0736         LSLS       R6, R6, #28
+  0x08001466:  D409         BMI        .L4                      ; 0x0800147C
+  0x08001468:  69D6         LDR        R6, [R2, #28]
+  0x0800146A:  421E         TST        R6, R3
+  0x0800146C:  D0ED         BEQ        .L1                      ; 0x0800144A
+  0x0800146E:  2403         MOVS       R4, #3
+  0x08001470:  2620         MOVS       R6, #32
+  0x08001472:  E005         B          .L5                      ; 0x08001480
+
.L2:
+  0x08001474:  2400         MOVS       R4, #0
+  0x08001476:  E00C         B          .L6                      ; 0x08001492
+
.L3:
+  0x08001478:  2403         MOVS       R4, #3
+  0x0800147A:  E00A         B          .L6                      ; 0x08001492
+
.L4:
+  0x0800147C:  2308         MOVS       R3, #8
+  0x0800147E:  461E         MOV        R6, R3
+
.L5:
+  0x08001480:  6213         STR        R3, [R2, #32]
+  0x08001482:  4628         MOV        R0, R5
+  0x08001484:  F000 F80C    BL         UART_EndRxTransfer       ; 0x080014A0
+  0x08001488:  2084         MOVS       R0, #132
+  0x0800148A:  2100         MOVS       R1, #0
+  0x0800148C:  5429         STRB       R1, [R5, R0]
+  0x0800148E:  2090         MOVS       R0, #144
+  0x08001490:  502E         STR        R6, [R5, R0]
+
.L6:
+  0x08001492:  4620         MOV        R0, R4
+  0x08001494:  BD70         POP        {R4-R6, PC}
+  0x08001496:  46C0         NOP
+  0x08001498:  200003BC     DC.W       huart1
+  0x0800149C:  2000068C     DC.W       uwTick
+
+

Section .text.UART_EndRxTransfer from PowerPro_lto.o, size=96, align=4

+
+
UART_EndRxTransfer:
+  0x080014A0:  B530         PUSH       {R4-R5, LR}
+  0x080014A2:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014A6:  2101         MOVS       R1, #1
+  0x080014A8:  F381 8810    MSR        PRIMASK, R1
+  0x080014AC:  2309         MOVS       R3, #9
+  0x080014AE:  015B         LSLS       R3, R3, #5
+  0x080014B0:  6804         LDR        R4, [R0]
+  0x080014B2:  6825         LDR        R5, [R4]
+  0x080014B4:  439D         BICS       R5, R3
+  0x080014B6:  6025         STR        R5, [R4]
+  0x080014B8:  F382 8810    MSR        PRIMASK, R2
+  0x080014BC:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014C0:  F381 8810    MSR        PRIMASK, R1
+  0x080014C4:  6803         LDR        R3, [R0]
+  0x080014C6:  689C         LDR        R4, [R3, #8]
+  0x080014C8:  4D0C         LDR        R5, =0xEFFFFFFE          ; [PC, #48] [0x080014FC] 
+  0x080014CA:  4025         ANDS       R5, R4
+  0x080014CC:  609D         STR        R5, [R3, #8]
+  0x080014CE:  F382 8810    MSR        PRIMASK, R2
+  0x080014D2:  6EC2         LDR        R2, [R0, #108]
+  0x080014D4:  2A01         CMP        R2, #1
+  0x080014D6:  D10A         BNE        .L1                      ; 0x080014EE
+  0x080014D8:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014DC:  F381 8810    MSR        PRIMASK, R1
+  0x080014E0:  6801         LDR        R1, [R0]
+  0x080014E2:  680B         LDR        R3, [R1]
+  0x080014E4:  2410         MOVS       R4, #16
+  0x080014E6:  43A3         BICS       R3, R4
+  0x080014E8:  600B         STR        R3, [R1]
+  0x080014EA:  F382 8810    MSR        PRIMASK, R2
+
.L1:
+  0x080014EE:  218C         MOVS       R1, #140
+  0x080014F0:  2220         MOVS       R2, #32
+  0x080014F2:  5042         STR        R2, [R0, R1]
+  0x080014F4:  2100         MOVS       R1, #0
+  0x080014F6:  6741         STR        R1, [R0, #116]
+  0x080014F8:  66C1         STR        R1, [R0, #108]
+  0x080014FA:  BD30         POP        {R4-R5, PC}
+  0x080014FC:  EFFFFFFE     DC.W       0xEFFFFFFE
+
+

Section .text.UART_DMATransmitCplt from PowerPro_lto.o, size=80, align=4

+
+
UART_DMATransmitCplt:
+  0x08001500:  B530         PUSH       {R4-R5, LR}
+  0x08001502:  6A81         LDR        R1, [R0, #40]
+  0x08001504:  6800         LDR        R0, [R0]
+  0x08001506:  6800         LDR        R0, [R0]
+  0x08001508:  0680         LSLS       R0, R0, #26
+  0x0800150A:  D41A         BMI        .L1                      ; 0x08001542
+  0x0800150C:  2056         MOVS       R0, #86
+  0x0800150E:  2200         MOVS       R2, #0
+  0x08001510:  520A         STRH       R2, [R1, R0]
+  0x08001512:  F3EF 8010    MRS        R0, PRIMASK
+  0x08001516:  2201         MOVS       R2, #1
+  0x08001518:  F382 8810    MSR        PRIMASK, R2
+  0x0800151C:  680B         LDR        R3, [R1]
+  0x0800151E:  689C         LDR        R4, [R3, #8]
+  0x08001520:  2580         MOVS       R5, #128
+  0x08001522:  43AC         BICS       R4, R5
+  0x08001524:  609C         STR        R4, [R3, #8]
+  0x08001526:  F380 8810    MSR        PRIMASK, R0
+  0x0800152A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800152E:  F382 8810    MSR        PRIMASK, R2
+  0x08001532:  6809         LDR        R1, [R1]
+  0x08001534:  680A         LDR        R2, [R1]
+  0x08001536:  2340         MOVS       R3, #64
+  0x08001538:  4313         ORRS       R3, R2
+  0x0800153A:  600B         STR        R3, [R1]
+  0x0800153C:  F380 8810    MSR        PRIMASK, R0
+  0x08001540:  BD30         POP        {R4-R5, PC}
+
.L1:
+  0x08001542:  4802         LDR        R0, =0x20000026          ; [PC, #8] [0x0800154C] 
+  0x08001544:  2100         MOVS       R1, #0
+  0x08001546:  7001         STRB       R1, [R0]
+  0x08001548:  BD30         POP        {R4-R5, PC}
+  0x0800154A:  46C0         NOP
+  0x0800154C:  20000026     DC.W       20000026               ; R_ARM_ABS32
+
+

Section .text.HAL_UART_Receive_DMA from PowerPro_lto.o, size=248, align=4

+
+
HAL_UART_Receive_DMA:
+  0x08001550:  B5F0         PUSH       {R4-R7, LR}
+  0x08001552:  B083         SUB        SP, SP, #12
+  0x08001554:  4604         MOV        R4, R0
+  0x08001556:  4607         MOV        R7, R0
+  0x08001558:  3780         ADDS       R7, #128
+  0x0800155A:  68F8         LDR        R0, [R7, #12]
+  0x0800155C:  2820         CMP        R0, #32
+  0x0800155E:  D142         BNE        .L3                      ; 0x080015E6
+  0x08001560:  000A         MOVS       R2, R1
+  0x08001562:  D042         BEQ        .L4                      ; 0x080015EA
+  0x08001564:  2301         MOVS       R3, #1
+  0x08001566:  0318         LSLS       R0, R3, #12
+  0x08001568:  68A1         LDR        R1, [R4, #8]
+  0x0800156A:  4281         CMP        R1, R0
+  0x0800156C:  D104         BNE        .L1                      ; 0x08001578
+  0x0800156E:  6920         LDR        R0, [R4, #16]
+  0x08001570:  2800         CMP        R0, #0
+  0x08001572:  D101         BNE        .L1                      ; 0x08001578
+  0x08001574:  07D0         LSLS       R0, R2, #31
+  0x08001576:  D138         BNE        .L4                      ; 0x080015EA
+
.L1:
+  0x08001578:  4620         MOV        R0, R4
+  0x0800157A:  305C         ADDS       R0, #92
+  0x0800157C:  2500         MOVS       R5, #0
+  0x0800157E:  66E5         STR        R5, [R4, #108]
+  0x08001580:  6821         LDR        R1, [R4]
+  0x08001582:  6849         LDR        R1, [R1, #4]
+  0x08001584:  0209         LSLS       R1, R1, #8
+  0x08001586:  9302         STR        R3, [SP, #8]
+  0x08001588:  D50D         BPL        .L2                      ; 0x080015A6
+  0x0800158A:  F3EF 8110    MRS        R1, PRIMASK
+  0x0800158E:  9101         STR        R1, [SP, #4]
+  0x08001590:  F383 8810    MSR        PRIMASK, R3
+  0x08001594:  069B         LSLS       R3, R3, #26
+  0x08001596:  6826         LDR        R6, [R4]
+  0x08001598:  6831         LDR        R1, [R6]
+  0x0800159A:  4319         ORRS       R1, R3
+  0x0800159C:  9B02         LDR        R3, [SP, #8]
+  0x0800159E:  6031         STR        R1, [R6]
+  0x080015A0:  9901         LDR        R1, [SP, #4]
+  0x080015A2:  F381 8810    MSR        PRIMASK, R1
+
.L2:
+  0x080015A6:  613D         STR        R5, [R7, #16]
+  0x080015A8:  65A2         STR        R2, [R4, #88]
+  0x080015AA:  021E         LSLS       R6, R3, #8
+  0x080015AC:  8006         STRH       R6, [R0]
+  0x080015AE:  2022         MOVS       R0, #34
+  0x080015B0:  60F8         STR        R0, [R7, #12]
+  0x080015B2:  6838         LDR        R0, [R7]
+  0x080015B4:  2800         CMP        R0, #0
+  0x080015B6:  D01A         BEQ        .L5                      ; 0x080015EE
+  0x080015B8:  4B21         LDR        R3, =UART_DMARxHalfCplt  ; [PC, #132] [0x08001640] =0x08005EB3 
+  0x080015BA:  4631         MOV        R1, R6
+  0x080015BC:  4E21         LDR        R6, =UART_DMAReceiveCplt ; [PC, #132] [0x08001644] =0x08005E0B 
+  0x080015BE:  62C6         STR        R6, [R0, #44]
+  0x080015C0:  460E         MOV        R6, R1
+  0x080015C2:  6303         STR        R3, [R0, #48]
+  0x080015C4:  491D         LDR        R1, =UART_DMAError       ; [PC, #116] [0x0800163C] =0x08005811 
+  0x080015C6:  6341         STR        R1, [R0, #52]
+  0x080015C8:  6385         STR        R5, [R0, #56]
+  0x080015CA:  6821         LDR        R1, [R4]
+  0x080015CC:  3124         ADDS       R1, #36
+  0x080015CE:  4633         MOV        R3, R6
+  0x080015D0:  F7FF FA28    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080015D4:  9902         LDR        R1, [SP, #8]
+  0x080015D6:  2800         CMP        R0, #0
+  0x080015D8:  D009         BEQ        .L5                      ; 0x080015EE
+  0x080015DA:  2010         MOVS       R0, #16
+  0x080015DC:  6138         STR        R0, [R7, #16]
+  0x080015DE:  2020         MOVS       R0, #32
+  0x080015E0:  60F8         STR        R0, [R7, #12]
+  0x080015E2:  460D         MOV        R5, R1
+  0x080015E4:  E027         B          .L7                      ; 0x08001636
+
.L3:
+  0x080015E6:  2502         MOVS       R5, #2
+  0x080015E8:  E025         B          .L7                      ; 0x08001636
+
.L4:
+  0x080015EA:  2501         MOVS       R5, #1
+  0x080015EC:  E023         B          .L7                      ; 0x08001636
+
.L5:
+  0x080015EE:  6920         LDR        R0, [R4, #16]
+  0x080015F0:  2800         CMP        R0, #0
+  0x080015F2:  D00A         BEQ        .L6                      ; 0x0800160A
+  0x080015F4:  F3EF 8010    MRS        R0, PRIMASK
+  0x080015F8:  2101         MOVS       R1, #1
+  0x080015FA:  F381 8810    MSR        PRIMASK, R1
+  0x080015FE:  6821         LDR        R1, [R4]
+  0x08001600:  680A         LDR        R2, [R1]
+  0x08001602:  4332         ORRS       R2, R6
+  0x08001604:  600A         STR        R2, [R1]
+  0x08001606:  F380 8810    MSR        PRIMASK, R0
+
.L6:
+  0x0800160A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800160E:  2101         MOVS       R1, #1
+  0x08001610:  F381 8810    MSR        PRIMASK, R1
+  0x08001614:  6822         LDR        R2, [R4]
+  0x08001616:  6893         LDR        R3, [R2, #8]
+  0x08001618:  430B         ORRS       R3, R1
+  0x0800161A:  6093         STR        R3, [R2, #8]
+  0x0800161C:  F380 8810    MSR        PRIMASK, R0
+  0x08001620:  F3EF 8010    MRS        R0, PRIMASK
+  0x08001624:  F381 8810    MSR        PRIMASK, R1
+  0x08001628:  6821         LDR        R1, [R4]
+  0x0800162A:  688A         LDR        R2, [R1, #8]
+  0x0800162C:  2340         MOVS       R3, #64
+  0x0800162E:  4313         ORRS       R3, R2
+  0x08001630:  608B         STR        R3, [R1, #8]
+  0x08001632:  F380 8810    MSR        PRIMASK, R0
+
.L7:
+  0x08001636:  4628         MOV        R0, R5
+  0x08001638:  B003         ADD        SP, SP, #12
+  0x0800163A:  BDF0         POP        {R4-R7, PC}
+  0x0800163C:  08005811     DC.W       UART_DMAError
+  0x08001640:  08005EB3     DC.W       UART_DMARxHalfCplt
+  0x08001644:  08005E0B     DC.W       UART_DMAReceiveCplt
+
+

Section .text.UARTEx_SetNbDataToProcess from PowerPro_lto.o, size=84, align=4

+
+
UARTEx_SetNbDataToProcess:
+  0x08001648:  B5F0         PUSH       {R4-R7, LR}
+  0x0800164A:  B081         SUB        SP, SP, #4
+  0x0800164C:  4D10         LDR        R5, =huart1              ; [PC, #64] [0x08001690] =0x200003BC 
+  0x0800164E:  6E68         LDR        R0, [R5, #100]
+  0x08001650:  2800         CMP        R0, #0
+  0x08001652:  D015         BEQ        .L1                      ; 0x08001680
+  0x08001654:  6828         LDR        R0, [R5]
+  0x08001656:  6881         LDR        R1, [R0, #8]
+  0x08001658:  9100         STR        R1, [SP, #0]
+  0x0800165A:  6880         LDR        R0, [R0, #8]
+  0x0800165C:  0F40         LSRS       R0, R0, #29
+  0x0800165E:  4F0D         LDR        R7, =UARTEx_SetNbDataToProcess.denominator ; [PC, #52] [0x08001694] =0x0800686C 
+  0x08001660:  5C39         LDRB       R1, [R7, R0]
+  0x08001662:  4E0D         LDR        R6, =UARTEx_SetNbDataToProcess.numerator ; [PC, #52] [0x08001698] =0x08006864 
+  0x08001664:  5C30         LDRB       R0, [R6, R0]
+  0x08001666:  00C0         LSLS       R0, R0, #3
+  0x08001668:  F004 FD0B    BL         __aeabi_uidiv            ; 0x08006082
+  0x0800166C:  4604         MOV        R4, R0
+  0x0800166E:  9800         LDR        R0, [SP, #0]
+  0x08001670:  0100         LSLS       R0, R0, #4
+  0x08001672:  0F40         LSRS       R0, R0, #29
+  0x08001674:  5C39         LDRB       R1, [R7, R0]
+  0x08001676:  5C30         LDRB       R0, [R6, R0]
+  0x08001678:  00C0         LSLS       R0, R0, #3
+  0x0800167A:  F004 FD02    BL         __aeabi_uidiv            ; 0x08006082
+  0x0800167E:  E001         B          .L2                      ; 0x08001684
+
.L1:
+  0x08001680:  2401         MOVS       R4, #1
+  0x08001682:  4620         MOV        R0, R4
+
.L2:
+  0x08001684:  2168         MOVS       R1, #104
+  0x08001686:  5268         STRH       R0, [R5, R1]
+  0x08001688:  206A         MOVS       R0, #106
+  0x0800168A:  522C         STRH       R4, [R5, R0]
+  0x0800168C:  B001         ADD        SP, SP, #4
+  0x0800168E:  BDF0         POP        {R4-R7, PC}
+  0x08001690:  200003BC     DC.W       huart1
+  0x08001694:  0800686C     DC.W       UARTEx_SetNbDataToProcess.denominator
+  0x08001698:  08006864     DC.W       UARTEx_SetNbDataToProcess.numerator
+
+

Section .text.EEPROM_Write from PowerPro_lto.o, size=280, align=4

+
+
EEPROM_Write:
+  0x0800169C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800169E:  B08B         SUB        SP, SP, #44
+  0x080016A0:  493F         LDR        R1, =0x08007800          ; [PC, #252] [0x080017A0] 
+  0x080016A2:  2210         MOVS       R2, #16
+  0x080016A4:  9009         STR        R0, [SP, #36]
+  0x080016A6:  F004 FB28    BL         memcmp                   ; 0x08005CFA
+  0x080016AA:  2800         CMP        R0, #0
+  0x080016AC:  D029         BEQ        .L4                      ; 0x08001702
+  0x080016AE:  F7FF FA95    BL         HAL_FLASH_Unlock         ; 0x08000BDC
+  0x080016B2:  4F3C         LDR        R7, =pFlash.0            ; [PC, #240] [0x080017A4] =0x20000738 
+  0x080016B4:  7838         LDRB       R0, [R7]
+  0x080016B6:  2800         CMP        R0, #0
+  0x080016B8:  4E3B         LDR        R6, =0x40022014          ; [PC, #236] [0x080017A8] 
+  0x080016BA:  D11C         BNE        .L3                      ; 0x080016F6
+  0x080016BC:  2501         MOVS       R5, #1
+  0x080016BE:  703D         STRB       R5, [R7]
+  0x080016C0:  F7FF FA64    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x080016C4:  2800         CMP        R0, #0
+  0x080016C6:  D114         BNE        .L2                      ; 0x080016F2
+  0x080016C8:  200F         MOVS       R0, #15
+  0x080016CA:  43C0         MVNS       R0, R0
+  0x080016CC:  4604         MOV        R4, R0
+
.L1:
+  0x080016CE:  6831         LDR        R1, [R6]
+  0x080016D0:  3408         ADDS       R4, #8
+  0x080016D2:  D018         BEQ        .L5                      ; 0x08001706
+  0x080016D4:  4A35         LDR        R2, =0xFFFEFF85          ; [PC, #212] [0x080017AC] 
+  0x080016D6:  4011         ANDS       R1, R2
+  0x080016D8:  1840         ADDS       R0, R0, R1
+  0x080016DA:  4935         LDR        R1, =0x0001008A          ; [PC, #212] [0x080017B0] 
+  0x080016DC:  1840         ADDS       R0, R0, R1
+  0x080016DE:  6030         STR        R0, [R6]
+  0x080016E0:  F7FF FA54    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x080016E4:  2800         CMP        R0, #0
+  0x080016E6:  4620         MOV        R0, R4
+  0x080016E8:  D0F1         BEQ        .L1                      ; 0x080016CE
+  0x080016EA:  6830         LDR        R0, [R6]
+  0x080016EC:  2102         MOVS       R1, #2
+  0x080016EE:  4388         BICS       R0, R1
+  0x080016F0:  6030         STR        R0, [R6]
+
.L2:
+  0x080016F2:  2000         MOVS       R0, #0
+  0x080016F4:  7038         STRB       R0, [R7]
+
.L3:
+  0x080016F6:  2001         MOVS       R0, #1
+  0x080016F8:  07C0         LSLS       R0, R0, #31
+  0x080016FA:  6831         LDR        R1, [R6]
+  0x080016FC:  4301         ORRS       R1, R0
+  0x080016FE:  6031         STR        R1, [R6]
+  0x08001700:  6830         LDR        R0, [R6]
+
.L4:
+  0x08001702:  B00B         ADD        SP, SP, #44
+  0x08001704:  BDF0         POP        {R4-R7, PC}
+
.L5:
+  0x08001706:  2002         MOVS       R0, #2
+  0x08001708:  4381         BICS       R1, R0
+  0x0800170A:  6031         STR        R1, [R6]
+  0x0800170C:  2200         MOVS       R2, #0
+  0x0800170E:  703A         STRB       R2, [R7]
+  0x08001710:  4823         LDR        R0, =0x08007800          ; [PC, #140] [0x080017A0] 
+  0x08001712:  1D00         ADDS       R0, R0, #4
+
.L6:
+  0x08001714:  900A         STR        R0, [SP, #40]
+  0x08001716:  2A0F         CMP        R2, #15
+  0x08001718:  D8ED         BHI        .L3                      ; 0x080016F6
+  0x0800171A:  703D         STRB       R5, [R7]
+  0x0800171C:  9909         LDR        R1, [SP, #36]
+  0x0800171E:  1888         ADDS       R0, R1, R2
+  0x08001720:  7903         LDRB       R3, [R0, #4]
+  0x08001722:  9304         STR        R3, [SP, #16]
+  0x08001724:  462C         MOV        R4, R5
+  0x08001726:  7945         LDRB       R5, [R0, #5]
+  0x08001728:  7983         LDRB       R3, [R0, #6]
+  0x0800172A:  9302         STR        R3, [SP, #8]
+  0x0800172C:  79C3         LDRB       R3, [R0, #7]
+  0x0800172E:  9301         STR        R3, [SP, #4]
+  0x08001730:  9208         STR        R2, [SP, #32]
+  0x08001732:  5C89         LDRB       R1, [R1, R2]
+  0x08001734:  9107         STR        R1, [SP, #28]
+  0x08001736:  7841         LDRB       R1, [R0, #1]
+  0x08001738:  9103         STR        R1, [SP, #12]
+  0x0800173A:  7881         LDRB       R1, [R0, #2]
+  0x0800173C:  9106         STR        R1, [SP, #24]
+  0x0800173E:  78C0         LDRB       R0, [R0, #3]
+  0x08001740:  9005         STR        R0, [SP, #20]
+  0x08001742:  F7FF FA23    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x08001746:  2800         CMP        R0, #0
+  0x08001748:  D1D3         BNE        .L2                      ; 0x080016F2
+  0x0800174A:  0228         LSLS       R0, R5, #8
+  0x0800174C:  9904         LDR        R1, [SP, #16]
+  0x0800174E:  1840         ADDS       R0, R0, R1
+  0x08001750:  9902         LDR        R1, [SP, #8]
+  0x08001752:  0409         LSLS       R1, R1, #16
+  0x08001754:  9A01         LDR        R2, [SP, #4]
+  0x08001756:  0612         LSLS       R2, R2, #24
+  0x08001758:  1851         ADDS       R1, R2, R1
+  0x0800175A:  1808         ADDS       R0, R1, R0
+  0x0800175C:  9903         LDR        R1, [SP, #12]
+  0x0800175E:  0209         LSLS       R1, R1, #8
+  0x08001760:  9A07         LDR        R2, [SP, #28]
+  0x08001762:  1889         ADDS       R1, R1, R2
+  0x08001764:  9A06         LDR        R2, [SP, #24]
+  0x08001766:  0412         LSLS       R2, R2, #16
+  0x08001768:  9B05         LDR        R3, [SP, #20]
+  0x0800176A:  061B         LSLS       R3, R3, #24
+  0x0800176C:  189A         ADDS       R2, R3, R2
+  0x0800176E:  1851         ADDS       R1, R2, R1
+  0x08001770:  6832         LDR        R2, [R6]
+  0x08001772:  4322         ORRS       R2, R4
+  0x08001774:  6032         STR        R2, [R6]
+  0x08001776:  9B0A         LDR        R3, [SP, #40]
+  0x08001778:  1F1A         SUBS       R2, R3, #4
+  0x0800177A:  6011         STR        R1, [R2]
+  0x0800177C:  F3BF 8F6F    ISB        SY
+  0x08001780:  6018         STR        R0, [R3]
+  0x08001782:  F7FF FA03    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x08001786:  6831         LDR        R1, [R6]
+  0x08001788:  43A1         BICS       R1, R4
+  0x0800178A:  6031         STR        R1, [R6]
+  0x0800178C:  2100         MOVS       R1, #0
+  0x0800178E:  7039         STRB       R1, [R7]
+  0x08001790:  2800         CMP        R0, #0
+  0x08001792:  9A08         LDR        R2, [SP, #32]
+  0x08001794:  D1AF         BNE        .L3                      ; 0x080016F6
+  0x08001796:  4625         MOV        R5, R4
+  0x08001798:  980A         LDR        R0, [SP, #40]
+  0x0800179A:  3008         ADDS       R0, #8
+  0x0800179C:  3208         ADDS       R2, #8
+  0x0800179E:  E7B9         B          .L6                      ; 0x08001714
+  0x080017A0:  08007800     DC.W       0x08007800
+  0x080017A4:  20000738     DC.W       pFlash.0
+  0x080017A8:  40022014     DC.W       0x40022014
+  0x080017AC:  FFFEFF85     DC.W       0xFFFEFF85
+  0x080017B0:  0001008A     DC.W       0x0001008A
+
+

Section .text.EEPROM_WriteDefaults from PowerPro_lto.o, size=48, align=4

+
+
EEPROM_WriteDefaults:
+  0x080017B4:  B580         PUSH       {R7, LR}
+  0x080017B6:  480A         LDR        R0, =flash_device_parameter_default ; [PC, #40] [0x080017E0] =0x20000674 
+  0x080017B8:  2100         MOVS       R1, #0
+  0x080017BA:  73C1         STRB       R1, [R0, #15]
+  0x080017BC:  2202         MOVS       R2, #2
+  0x080017BE:  7382         STRB       R2, [R0, #14]
+  0x080017C0:  7341         STRB       R1, [R0, #13]
+  0x080017C2:  2201         MOVS       R2, #1
+  0x080017C4:  7302         STRB       R2, [R0, #12]
+  0x080017C6:  72C1         STRB       R1, [R0, #11]
+  0x080017C8:  7282         STRB       R2, [R0, #10]
+  0x080017CA:  7241         STRB       R1, [R0, #9]
+  0x080017CC:  7201         STRB       R1, [R0, #8]
+  0x080017CE:  71C1         STRB       R1, [R0, #7]
+  0x080017D0:  7181         STRB       R1, [R0, #6]
+  0x080017D2:  224B         MOVS       R2, #75
+  0x080017D4:  7142         STRB       R2, [R0, #5]
+  0x080017D6:  7101         STRB       R1, [R0, #4]
+  0x080017D8:  F7FF FF60    BL         EEPROM_Write             ; 0x0800169C
+  0x080017DC:  BD80         POP        {R7, PC}
+  0x080017DE:  46C0         NOP
+  0x080017E0:  20000674     DC.W       flash_device_parameter_default
+
+

Section .text.EEPROM_ReadDeviceParameter from PowerPro_lto.o, size=36, align=4

+
+
EEPROM_ReadDeviceParameter:
+  0x080017E4:  B530         PUSH       {R4-R5, LR}
+  0x080017E6:  4806         LDR        R0, =0x08007800          ; [PC, #24] [0x08001800] 
+  0x080017E8:  8981         LDRH       R1, [R0, #12]
+  0x080017EA:  8942         LDRH       R2, [R0, #10]
+  0x080017EC:  8903         LDRH       R3, [R0, #8]
+  0x080017EE:  6804         LDR        R4, [R0]
+  0x080017F0:  6840         LDR        R0, [R0, #4]
+  0x080017F2:  4D04         LDR        R5, =sys_data            ; [PC, #16] [0x08001804] =0x20000234 
+  0x080017F4:  606C         STR        R4, [R5, #4]
+  0x080017F6:  6128         STR        R0, [R5, #16]
+  0x080017F8:  82AB         STRH       R3, [R5, #20]
+  0x080017FA:  82EA         STRH       R2, [R5, #22]
+  0x080017FC:  8329         STRH       R1, [R5, #24]
+  0x080017FE:  BD30         POP        {R4-R5, PC}
+  0x08001800:  08007800     DC.W       0x08007800
+  0x08001804:  20000234     DC.W       sys_data
+
+

Section .text.EEPROM_StoreConfig from PowerPro_lto.o, size=60, align=4

+
+
EEPROM_StoreConfig:
+  0x08001808:  B5F0         PUSH       {R4-R7, LR}
+  0x0800180A:  B085         SUB        SP, SP, #20
+  0x0800180C:  490B         LDR        R1, =0x08007800          ; [PC, #44] [0x0800183C] 
+  0x0800180E:  AA01         ADD        R2, SP, #4
+  0x08001810:  4613         MOV        R3, R2
+  0x08001812:  C9F0         LDM        R1!, {R4-R7}
+  0x08001814:  C3F0         STM        R3!, {R4-R7}
+  0x08001816:  2800         CMP        R0, #0
+  0x08001818:  4809         LDR        R0, =sys_data            ; [PC, #36] [0x08001840] =0x20000234 
+  0x0800181A:  6901         LDR        R1, [R0, #16]
+  0x0800181C:  8A83         LDRH       R3, [R0, #20]
+  0x0800181E:  8113         STRH       R3, [R2, #8]
+  0x08001820:  8AC3         LDRH       R3, [R0, #22]
+  0x08001822:  8153         STRH       R3, [R2, #10]
+  0x08001824:  8B03         LDRH       R3, [R0, #24]
+  0x08001826:  8193         STRH       R3, [R2, #12]
+  0x08001828:  9102         STR        R1, [SP, #8]
+  0x0800182A:  D001         BEQ        .L1                      ; 0x08001830
+  0x0800182C:  6840         LDR        R0, [R0, #4]
+  0x0800182E:  9001         STR        R0, [SP, #4]
+
.L1:
+  0x08001830:  A801         ADD        R0, SP, #4
+  0x08001832:  F7FF FF33    BL         EEPROM_Write             ; 0x0800169C
+  0x08001836:  B005         ADD        SP, SP, #20
+  0x08001838:  BDF0         POP        {R4-R7, PC}
+  0x0800183A:  46C0         NOP
+  0x0800183C:  08007800     DC.W       0x08007800
+  0x08001840:  20000234     DC.W       sys_data
+
+

Section .text.main from PowerPro_lto.o, size=11532, align=4

+
+
main:
+  0x08001844:  B500         PUSH       {LR}
+  0x08001846:  B0B5         SUB        SP, SP, #212
+  0x08001848:  49F6         LDR        R1, =bootLoaderMark      ; [PC, #0x03D8] [0x08001C24] =0x20000B7C 
+  0x0800184A:  7808         LDRB       R0, [R1]
+  0x0800184C:  2801         CMP        R0, #1
+  0x0800184E:  D101         BNE        .L1                      ; 0x08001854
+  0x08001850:  F002 FE43    BL         .L287                    ; 0x080044DA
+
.L1:
+  0x08001854:  4EF4         LDR        R6, =0x40022000          ; [PC, #0x03D0] [0x08001C28] 
+  0x08001856:  6A30         LDR        R0, [R6, #32]
+  0x08001858:  01C0         LSLS       R0, R0, #7
+  0x0800185A:  D51F         BPL        .L3                      ; 0x0800189C
+  0x0800185C:  48F3         LDR        R0, =0x080061EA          ; [PC, #0x03CC] [0x08001C2C] 
+  0x0800185E:  F003 FCC7    BL         puts                     ; 0x080051F0
+  0x08001862:  F7FF F9BB    BL         HAL_FLASH_Unlock         ; 0x08000BDC
+  0x08001866:  F7FF F991    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x0800186A:  6970         LDR        R0, [R6, #20]
+  0x0800186C:  0040         LSLS       R0, R0, #1
+  0x0800186E:  D504         BPL        .L2                      ; 0x0800187A
+  0x08001870:  48EF         LDR        R0, =0x08192A3B          ; [PC, #0x03BC] [0x08001C30] 
+  0x08001872:  60F0         STR        R0, [R6, #12]
+  0x08001874:  48EF         LDR        R0, =0x4C5D6E7F          ; [PC, #0x03BC] [0x08001C34] 
+  0x08001876:  60F0         STR        R0, [R6, #12]
+  0x08001878:  6970         LDR        R0, [R6, #20]
+
.L2:
+  0x0800187A:  4CEF         LDR        R4, =FLASH_WaitForLastOperation ; [PC, #0x03BC] [0x08001C38] =0x08000B8D 
+  0x0800187C:  47A0         BLX        R4
+  0x0800187E:  2501         MOVS       R5, #1
+  0x08001880:  0628         LSLS       R0, R5, #24
+  0x08001882:  6A31         LDR        R1, [R6, #32]
+  0x08001884:  4381         BICS       R1, R0
+  0x08001886:  6231         STR        R1, [R6, #32]
+  0x08001888:  47A0         BLX        R4
+  0x0800188A:  0468         LSLS       R0, R5, #17
+  0x0800188C:  6971         LDR        R1, [R6, #20]
+  0x0800188E:  4301         ORRS       R1, R0
+  0x08001890:  6171         STR        R1, [R6, #20]
+  0x08001892:  47A0         BLX        R4
+  0x08001894:  06E8         LSLS       R0, R5, #27
+  0x08001896:  6971         LDR        R1, [R6, #20]
+  0x08001898:  4301         ORRS       R1, R0
+  0x0800189A:  6171         STR        R1, [R6, #20]
+
.L3:
+  0x0800189C:  2003         MOVS       R0, #3
+  0x0800189E:  9015         STR        R0, [SP, #84]
+  0x080018A0:  F7FE FED8    BL         HAL_InitTick             ; 0x08000654
+  0x080018A4:  2800         CMP        R0, #0
+  0x080018A6:  4CE5         LDR        R4, =0x40021000          ; [PC, #0x0394] [0x08001C3C] 
+  0x080018A8:  D10F         BNE        .L4                      ; 0x080018CA
+  0x080018AA:  6C20         LDR        R0, [R4, #64]
+  0x080018AC:  2101         MOVS       R1, #1
+  0x080018AE:  4308         ORRS       R0, R1
+  0x080018B0:  6420         STR        R0, [R4, #64]
+  0x080018B2:  6C20         LDR        R0, [R4, #64]
+  0x080018B4:  4008         ANDS       R0, R1
+  0x080018B6:  9029         STR        R0, [SP, #164]
+  0x080018B8:  9829         LDR        R0, [SP, #164]
+  0x080018BA:  0708         LSLS       R0, R1, #28
+  0x080018BC:  6BE1         LDR        R1, [R4, #60]
+  0x080018BE:  4301         ORRS       R1, R0
+  0x080018C0:  63E1         STR        R1, [R4, #60]
+  0x080018C2:  6BE1         LDR        R1, [R4, #60]
+  0x080018C4:  4001         ANDS       R1, R0
+  0x080018C6:  9129         STR        R1, [SP, #164]
+  0x080018C8:  9829         LDR        R0, [SP, #164]
+
.L4:
+  0x080018CA:  6830         LDR        R0, [R6]
+  0x080018CC:  2107         MOVS       R1, #7
+  0x080018CE:  9123         STR        R1, [SP, #140]
+  0x080018D0:  4388         BICS       R0, R1
+  0x080018D2:  6030         STR        R0, [R6]
+  0x080018D4:  2501         MOVS       R5, #1
+  0x080018D6:  032B         LSLS       R3, R5, #12
+  0x080018D8:  68A0         LDR        R0, [R4, #8]
+  0x080018DA:  0680         LSLS       R0, R0, #26
+  0x080018DC:  0F40         LSRS       R0, R0, #29
+  0x080018DE:  4FD8         LDR        R7, =0x000003C7          ; [PC, #0x0360] [0x08001C40] 
+  0x080018E0:  48D8         LDR        R0, =0xFFFFC7FF          ; [PC, #0x0360] [0x08001C44] 
+  0x080018E2:  9314         STR        R3, [SP, #80]
+  0x080018E4:  D013         BEQ        .L6                      ; 0x0800190E
+  0x080018E6:  6821         LDR        R1, [R4]
+  0x080018E8:  4001         ANDS       R1, R0
+  0x080018EA:  4319         ORRS       R1, R3
+  0x080018EC:  6021         STR        R1, [R4]
+  0x080018EE:  0228         LSLS       R0, R5, #8
+  0x080018F0:  6821         LDR        R1, [R4]
+  0x080018F2:  4301         ORRS       R1, R0
+  0x080018F4:  6021         STR        R1, [R4]
+  0x080018F6:  48D4         LDR        R0, =uwTick              ; [PC, #0x0350] [0x08001C48] =0x2000068C 
+  0x080018F8:  6801         LDR        R1, [R0]
+
.L5:
+  0x080018FA:  463A         MOV        R2, R7
+  0x080018FC:  3239         ADDS       R2, #57
+  0x080018FE:  6823         LDR        R3, [R4]
+  0x08001900:  4213         TST        R3, R2
+  0x08001902:  D11E         BNE        .L9                      ; 0x08001942
+  0x08001904:  6802         LDR        R2, [R0]
+  0x08001906:  1A52         SUBS       R2, R2, R1
+  0x08001908:  2A02         CMP        R2, #2
+  0x0800190A:  D9F6         BLS        .L5                      ; 0x080018FA
+  0x0800190C:  E017         B          .L7                      ; 0x0800193E
+
.L6:
+  0x0800190E:  217F         MOVS       R1, #127
+  0x08001910:  0209         LSLS       R1, R1, #8
+  0x08001912:  6862         LDR        R2, [R4, #4]
+  0x08001914:  438A         BICS       R2, R1
+  0x08001916:  03A9         LSLS       R1, R5, #14
+  0x08001918:  1851         ADDS       R1, R2, R1
+  0x0800191A:  6061         STR        R1, [R4, #4]
+  0x0800191C:  6821         LDR        R1, [R4]
+  0x0800191E:  4001         ANDS       R1, R0
+  0x08001920:  4319         ORRS       R1, R3
+  0x08001922:  6021         STR        R1, [R4]
+  0x08001924:  6820         LDR        R0, [R4]
+  0x08001926:  0480         LSLS       R0, R0, #18
+  0x08001928:  0F40         LSRS       R0, R0, #29
+  0x0800192A:  49C8         LDR        R1, =0x02DC6C00          ; [PC, #0x0320] [0x08001C4C] 
+  0x0800192C:  40C1         LSRS       R1, R0
+  0x0800192E:  48C8         LDR        R0, =SystemCoreClock     ; [PC, #0x0320] [0x08001C50] =0x20000BA4 
+  0x08001930:  6001         STR        R1, [R0]
+  0x08001932:  48C8         LDR        R0, =uwTickPrio          ; [PC, #0x0320] [0x08001C54] =0x20000B94 
+  0x08001934:  6800         LDR        R0, [R0]
+  0x08001936:  F7FE FE8D    BL         HAL_InitTick             ; 0x08000654
+  0x0800193A:  2800         CMP        R0, #0
+  0x0800193C:  D008         BEQ        .L10                     ; 0x08001950
+
.L7:
+  0x0800193E:  B672         CPSID      i
+
.L8:
+  0x08001940:  E7FE         B          .L8                      ; 0x08001940
+
.L9:
+  0x08001942:  207F         MOVS       R0, #127
+  0x08001944:  0200         LSLS       R0, R0, #8
+  0x08001946:  6861         LDR        R1, [R4, #4]
+  0x08001948:  4381         BICS       R1, R0
+  0x0800194A:  03A8         LSLS       R0, R5, #14
+  0x0800194C:  1808         ADDS       R0, R1, R0
+  0x0800194E:  6060         STR        R0, [R4, #4]
+
.L10:
+  0x08001950:  6830         LDR        R0, [R6]
+  0x08001952:  207B         MOVS       R0, #123
+  0x08001954:  0200         LSLS       R0, R0, #8
+  0x08001956:  68A1         LDR        R1, [R4, #8]
+  0x08001958:  4381         BICS       R1, R0
+  0x0800195A:  220B         MOVS       R2, #11
+  0x0800195C:  0210         LSLS       R0, R2, #8
+  0x0800195E:  1808         ADDS       R0, R1, R0
+  0x08001960:  60A0         STR        R0, [R4, #8]
+  0x08001962:  48BD         LDR        R0, =0xFFFFF0FE          ; [PC, #0x02F4] [0x08001C58] 
+  0x08001964:  1C40         ADDS       R0, R0, #1
+  0x08001966:  68A1         LDR        R1, [R4, #8]
+  0x08001968:  4001         ANDS       R1, R0
+  0x0800196A:  60A1         STR        R1, [R4, #8]
+  0x0800196C:  4639         MOV        R1, R7
+  0x0800196E:  3139         ADDS       R1, #57
+  0x08001970:  6820         LDR        R0, [R4]
+  0x08001972:  9122         STR        R1, [SP, #136]
+  0x08001974:  4208         TST        R0, R1
+  0x08001976:  D03C         BEQ        .L15                     ; 0x080019F2
+  0x08001978:  68A0         LDR        R0, [R4, #8]
+  0x0800197A:  9923         LDR        R1, [SP, #140]
+  0x0800197C:  4388         BICS       R0, R1
+  0x0800197E:  60A0         STR        R0, [R4, #8]
+  0x08001980:  48B1         LDR        R0, =uwTick              ; [PC, #0x02C4] [0x08001C48] =0x2000068C 
+  0x08001982:  6800         LDR        R0, [R0]
+
.L11:
+  0x08001984:  68A1         LDR        R1, [R4, #8]
+  0x08001986:  0689         LSLS       R1, R1, #26
+  0x08001988:  0F49         LSRS       R1, R1, #29
+  0x0800198A:  D006         BEQ        .L12                     ; 0x0800199A
+  0x0800198C:  49AE         LDR        R1, =uwTick              ; [PC, #0x02B8] [0x08001C48] =0x2000068C 
+  0x0800198E:  6809         LDR        R1, [R1]
+  0x08001990:  1A09         SUBS       R1, R1, R0
+  0x08001992:  4BB2         LDR        R3, =0x00001388          ; [PC, #0x02C8] [0x08001C5C] 
+  0x08001994:  4299         CMP        R1, R3
+  0x08001996:  D9F5         BLS        .L11                     ; 0x08001984
+  0x08001998:  E02B         B          .L15                     ; 0x080019F2
+
.L12:
+  0x0800199A:  6830         LDR        R0, [R6]
+  0x0800199C:  0740         LSLS       R0, R0, #29
+  0x0800199E:  D00F         BEQ        .L14                     ; 0x080019C0
+  0x080019A0:  6830         LDR        R0, [R6]
+  0x080019A2:  9923         LDR        R1, [SP, #140]
+  0x080019A4:  4388         BICS       R0, R1
+  0x080019A6:  6030         STR        R0, [R6]
+  0x080019A8:  48A7         LDR        R0, =uwTick              ; [PC, #0x029C] [0x08001C48] =0x2000068C 
+  0x080019AA:  6800         LDR        R0, [R0]
+
.L13:
+  0x080019AC:  6831         LDR        R1, [R6]
+  0x080019AE:  0749         LSLS       R1, R1, #29
+  0x080019B0:  D006         BEQ        .L14                     ; 0x080019C0
+  0x080019B2:  49A5         LDR        R1, =uwTick              ; [PC, #0x0294] [0x08001C48] =0x2000068C 
+  0x080019B4:  6809         LDR        R1, [R1]
+  0x080019B6:  1A09         SUBS       R1, R1, R0
+  0x080019B8:  4BA8         LDR        R3, =0x00001388          ; [PC, #0x02A0] [0x08001C5C] 
+  0x080019BA:  4299         CMP        R1, R3
+  0x080019BC:  D9F6         BLS        .L13                     ; 0x080019AC
+  0x080019BE:  E018         B          .L15                     ; 0x080019F2
+
.L14:
+  0x080019C0:  9823         LDR        R0, [SP, #140]
+  0x080019C2:  0300         LSLS       R0, R0, #12
+  0x080019C4:  68A1         LDR        R1, [R4, #8]
+  0x080019C6:  4381         BICS       R1, R0
+  0x080019C8:  60A1         STR        R1, [R4, #8]
+  0x080019CA:  9206         STR        R2, [SP, #24]
+  0x080019CC:  F7FF F9D4    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+  0x080019D0:  68A1         LDR        R1, [R4, #8]
+  0x080019D2:  0989         LSRS       R1, R1, #6
+  0x080019D4:  263C         MOVS       R6, #60
+  0x080019D6:  4031         ANDS       R1, R6
+  0x080019D8:  4AA1         LDR        R2, =AHBPrescTable       ; [PC, #0x0284] [0x08001C60] =0x0800515C 
+  0x080019DA:  5851         LDR        R1, [R2, R1]
+  0x080019DC:  221F         MOVS       R2, #31
+  0x080019DE:  400A         ANDS       R2, R1
+  0x080019E0:  40D0         LSRS       R0, R2
+  0x080019E2:  499B         LDR        R1, =SystemCoreClock     ; [PC, #0x026C] [0x08001C50] =0x20000BA4 
+  0x080019E4:  6008         STR        R0, [R1]
+  0x080019E6:  489B         LDR        R0, =uwTickPrio          ; [PC, #0x026C] [0x08001C54] =0x20000B94 
+  0x080019E8:  6800         LDR        R0, [R0]
+  0x080019EA:  F7FE FE33    BL         HAL_InitTick             ; 0x08000654
+  0x080019EE:  2800         CMP        R0, #0
+  0x080019F0:  D001         BEQ        .L17                     ; 0x080019F6
+
.L15:
+  0x080019F2:  B672         CPSID      i
+
.L16:
+  0x080019F4:  E7FE         B          .L16                     ; 0x080019F4
+
.L17:
+  0x080019F6:  223C         MOVS       R2, #60
+  0x080019F8:  2600         MOVS       R6, #0
+  0x080019FA:  962D         STR        R6, [SP, #180]
+  0x080019FC:  962C         STR        R6, [SP, #176]
+  0x080019FE:  6B60         LDR        R0, [R4, #52]
+  0x08001A00:  2102         MOVS       R1, #2
+  0x08001A02:  4308         ORRS       R0, R1
+  0x08001A04:  6360         STR        R0, [R4, #52]
+  0x08001A06:  6B60         LDR        R0, [R4, #52]
+  0x08001A08:  9112         STR        R1, [SP, #72]
+  0x08001A0A:  4008         ANDS       R0, R1
+  0x08001A0C:  9030         STR        R0, [SP, #192]
+  0x08001A0E:  9830         LDR        R0, [SP, #192]
+  0x08001A10:  6B60         LDR        R0, [R4, #52]
+  0x08001A12:  2104         MOVS       R1, #4
+  0x08001A14:  4308         ORRS       R0, R1
+  0x08001A16:  6360         STR        R0, [R4, #52]
+  0x08001A18:  6B60         LDR        R0, [R4, #52]
+  0x08001A1A:  910F         STR        R1, [SP, #60]
+  0x08001A1C:  4008         ANDS       R0, R1
+  0x08001A1E:  9030         STR        R0, [SP, #192]
+  0x08001A20:  9830         LDR        R0, [SP, #192]
+  0x08001A22:  6B60         LDR        R0, [R4, #52]
+  0x08001A24:  4328         ORRS       R0, R5
+  0x08001A26:  6360         STR        R0, [R4, #52]
+  0x08001A28:  6B60         LDR        R0, [R4, #52]
+  0x08001A2A:  4028         ANDS       R0, R5
+  0x08001A2C:  9030         STR        R0, [SP, #192]
+  0x08001A2E:  9830         LDR        R0, [SP, #192]
+  0x08001A30:  9915         LDR        R1, [SP, #84]
+  0x08001A32:  038B         LSLS       R3, R1, #14
+  0x08001A34:  931E         STR        R3, [SP, #120]
+  0x08001A36:  498B         LDR        R1, =0x50000818          ; [PC, #0x022C] [0x08001C64] 
+  0x08001A38:  610B         STR        R3, [R1, #16]
+  0x08001A3A:  0229         LSLS       R1, R5, #8
+  0x08001A3C:  9110         STR        R1, [SP, #64]
+  0x08001A3E:  4B8A         LDR        R3, =0x50000010          ; [PC, #0x0228] [0x08001C68] 
+  0x08001A40:  6199         STR        R1, [R3, #24]
+  0x08001A42:  498A         LDR        R1, =0x50000410          ; [PC, #0x0228] [0x08001C6C] 
+  0x08001A44:  2338         MOVS       R3, #56
+  0x08001A46:  9320         STR        R3, [SP, #128]
+  0x08001A48:  618B         STR        R3, [R1, #24]
+  0x08001A4A:  952B         STR        R5, [SP, #172]
+  0x08001A4C:  962A         STR        R6, [SP, #168]
+  0x08001A4E:  9729         STR        R7, [SP, #164]
+  0x08001A50:  3910         SUBS       R1, #16
+  0x08001A52:  4608         MOV        R0, R1
+  0x08001A54:  911F         STR        R1, [SP, #124]
+  0x08001A56:  921D         STR        R2, [SP, #116]
+  0x08001A58:  A929         ADD        R1, SP, #164
+  0x08001A5A:  9121         STR        R1, [SP, #132]
+  0x08001A5C:  4F84         LDR        R7, =HAL_GPIO_Init       ; [PC, #0x0210] [0x08001C70] =0x08000BFD 
+  0x08001A5E:  47B8         BLX        R7
+  0x08001A60:  962C         STR        R6, [SP, #176]
+  0x08001A62:  962B         STR        R6, [SP, #172]
+  0x08001A64:  952A         STR        R5, [SP, #168]
+  0x08001A66:  981E         LDR        R0, [SP, #120]
+  0x08001A68:  9029         STR        R0, [SP, #164]
+  0x08001A6A:  487E         LDR        R0, =0x50000818          ; [PC, #0x01F8] [0x08001C64] 
+  0x08001A6C:  3818         SUBS       R0, #24
+  0x08001A6E:  901E         STR        R0, [SP, #120]
+  0x08001A70:  9921         LDR        R1, [SP, #132]
+  0x08001A72:  47B8         BLX        R7
+  0x08001A74:  952B         STR        R5, [SP, #172]
+  0x08001A76:  962A         STR        R6, [SP, #168]
+  0x08001A78:  9815         LDR        R0, [SP, #84]
+  0x08001A7A:  9029         STR        R0, [SP, #164]
+  0x08001A7C:  4F7A         LDR        R7, =0x50000010          ; [PC, #0x01E8] [0x08001C68] 
+  0x08001A7E:  3F10         SUBS       R7, #16
+  0x08001A80:  4638         MOV        R0, R7
+  0x08001A82:  9921         LDR        R1, [SP, #132]
+  0x08001A84:  4A7A         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01E8] [0x08001C70] =0x08000BFD 
+  0x08001A86:  4790         BLX        R2
+  0x08001A88:  962C         STR        R6, [SP, #176]
+  0x08001A8A:  962B         STR        R6, [SP, #172]
+  0x08001A8C:  952A         STR        R5, [SP, #168]
+  0x08001A8E:  9810         LDR        R0, [SP, #64]
+  0x08001A90:  9029         STR        R0, [SP, #164]
+  0x08001A92:  4638         MOV        R0, R7
+  0x08001A94:  9921         LDR        R1, [SP, #132]
+  0x08001A96:  4A76         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01D8] [0x08001C70] =0x08000BFD 
+  0x08001A98:  4790         BLX        R2
+  0x08001A9A:  962B         STR        R6, [SP, #172]
+  0x08001A9C:  962A         STR        R6, [SP, #168]
+  0x08001A9E:  2040         MOVS       R0, #64
+  0x08001AA0:  9007         STR        R0, [SP, #28]
+  0x08001AA2:  9029         STR        R0, [SP, #164]
+  0x08001AA4:  981E         LDR        R0, [SP, #120]
+  0x08001AA6:  9921         LDR        R1, [SP, #132]
+  0x08001AA8:  4A71         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01C4] [0x08001C70] =0x08000BFD 
+  0x08001AAA:  4790         BLX        R2
+  0x08001AAC:  962B         STR        R6, [SP, #172]
+  0x08001AAE:  962A         STR        R6, [SP, #168]
+  0x08001AB0:  2009         MOVS       R0, #9
+  0x08001AB2:  0300         LSLS       R0, R0, #12
+  0x08001AB4:  9029         STR        R0, [SP, #164]
+  0x08001AB6:  9709         STR        R7, [SP, #36]
+  0x08001AB8:  4638         MOV        R0, R7
+  0x08001ABA:  9F21         LDR        R7, [SP, #132]
+  0x08001ABC:  4639         MOV        R1, R7
+  0x08001ABE:  4A6C         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01B0] [0x08001C70] =0x08000BFD 
+  0x08001AC0:  4790         BLX        R2
+  0x08001AC2:  962C         STR        R6, [SP, #176]
+  0x08001AC4:  962B         STR        R6, [SP, #172]
+  0x08001AC6:  952A         STR        R5, [SP, #168]
+  0x08001AC8:  9820         LDR        R0, [SP, #128]
+  0x08001ACA:  9029         STR        R0, [SP, #164]
+  0x08001ACC:  981F         LDR        R0, [SP, #124]
+  0x08001ACE:  4639         MOV        R1, R7
+  0x08001AD0:  4A67         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x019C] [0x08001C70] =0x08000BFD 
+  0x08001AD2:  4790         BLX        R2
+  0x08001AD4:  6BA0         LDR        R0, [R4, #56]
+  0x08001AD6:  4328         ORRS       R0, R5
+  0x08001AD8:  63A0         STR        R0, [R4, #56]
+  0x08001ADA:  6BA0         LDR        R0, [R4, #56]
+  0x08001ADC:  4028         ANDS       R0, R5
+  0x08001ADE:  9029         STR        R0, [SP, #164]
+  0x08001AE0:  9829         LDR        R0, [SP, #164]
+  0x08001AE2:  23FF         MOVS       R3, #255
+  0x08001AE4:  0218         LSLS       R0, R3, #8
+  0x08001AE6:  4963         LDR        R1, =0xE000E408          ; [PC, #0x018C] [0x08001C74] 
+  0x08001AE8:  680A         LDR        R2, [R1]
+  0x08001AEA:  4382         BICS       R2, R0
+  0x08001AEC:  600A         STR        R2, [R1]
+  0x08001AEE:  0268         LSLS       R0, R5, #9
+  0x08001AF0:  4A61         LDR        R2, =0xE000E100          ; [PC, #0x0184] [0x08001C78] 
+  0x08001AF2:  6010         STR        R0, [R2]
+  0x08001AF4:  9313         STR        R3, [SP, #76]
+  0x08001AF6:  0418         LSLS       R0, R3, #16
+  0x08001AF8:  680B         LDR        R3, [R1]
+  0x08001AFA:  4383         BICS       R3, R0
+  0x08001AFC:  600B         STR        R3, [R1]
+  0x08001AFE:  9822         LDR        R0, [SP, #136]
+  0x08001B00:  6010         STR        R0, [R2]
+  0x08001B02:  4A5E         LDR        R2, =hadc1               ; [PC, #0x0178] [0x08001C7C] =0x20000450 
+  0x08001B04:  981D         LDR        R0, [SP, #116]
+  0x08001B06:  5415         STRB       R5, [R2, R0]
+  0x08001B08:  202C         MOVS       R0, #44
+  0x08001B0A:  9008         STR        R0, [SP, #32]
+  0x08001B0C:  5415         STRB       R5, [R2, R0]
+  0x08001B0E:  2720         MOVS       R7, #32
+  0x08001B10:  55D6         STRB       R6, [R2, R7]
+  0x08001B12:  2080         MOVS       R0, #128
+  0x08001B14:  211C         MOVS       R1, #28
+  0x08001B16:  9104         STR        R1, [SP, #16]
+  0x08001B18:  6411         STR        R1, [R2, #64]
+  0x08001B1A:  900A         STR        R0, [SP, #40]
+  0x08001B1C:  6450         STR        R0, [R2, #68]
+  0x08001B1E:  6496         STR        R6, [R2, #72]
+  0x08001B20:  64D6         STR        R6, [R2, #76]
+  0x08001B22:  6316         STR        R6, [R2, #48]
+  0x08001B24:  9823         LDR        R0, [SP, #140]
+  0x08001B26:  6350         STR        R0, [R2, #52]
+  0x08001B28:  6256         STR        R6, [R2, #36]
+  0x08001B2A:  6296         STR        R6, [R2, #40]
+  0x08001B2C:  61D5         STR        R5, [R2, #28]
+  0x08001B2E:  7695         STRB       R5, [R2, #26]
+  0x08001B30:  8316         STRH       R6, [R2, #24]
+  0x08001B32:  2108         MOVS       R1, #8
+  0x08001B34:  4852         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0148] [0x08001C80] 
+  0x08001B36:  3018         ADDS       R0, #24
+  0x08001B38:  4B52         LDR        R3, =0x40012400          ; [PC, #0x0148] [0x08001C84] 
+  0x08001B3A:  6013         STR        R3, [R2]
+  0x08001B3C:  6050         STR        R0, [R2, #4]
+  0x08001B3E:  6096         STR        R6, [R2, #8]
+  0x08001B40:  60D6         STR        R6, [R2, #12]
+  0x08001B42:  6110         STR        R0, [R2, #16]
+  0x08001B44:  911B         STR        R1, [SP, #108]
+  0x08001B46:  6151         STR        R1, [R2, #20]
+  0x08001B48:  9626         STR        R6, [SP, #152]
+  0x08001B4A:  9625         STR        R6, [SP, #148]
+  0x08001B4C:  9624         STR        R6, [SP, #144]
+  0x08001B4E:  9621         STR        R6, [SP, #132]
+  0x08001B50:  9627         STR        R6, [SP, #156]
+  0x08001B52:  4616         MOV        R6, R2
+  0x08001B54:  6D90         LDR        R0, [R2, #88]
+  0x08001B56:  2800         CMP        R0, #0
+  0x08001B58:  9720         STR        R7, [SP, #128]
+  0x08001B5A:  D148         BNE        .L20                     ; 0x08001BEE
+  0x08001B5C:  9034         STR        R0, [SP, #208]
+  0x08001B5E:  901F         STR        R0, [SP, #124]
+  0x08001B60:  9033         STR        R0, [SP, #204]
+  0x08001B62:  A829         ADD        R0, SP, #164
+  0x08001B64:  901E         STR        R0, [SP, #120]
+  0x08001B66:  1D00         ADDS       R0, R0, #4
+  0x08001B68:  2118         MOVS       R1, #24
+  0x08001B6A:  F004 FB20    BL         __aeabi_memclr           ; 0x080061AE
+  0x08001B6E:  9729         STR        R7, [SP, #164]
+  0x08001B70:  981E         LDR        R0, [SP, #120]
+  0x08001B72:  F7FF F94B    BL         HAL_RCCEx_PeriphCLKConfig ; 0x08000E0C
+  0x08001B76:  2800         CMP        R0, #0
+  0x08001B78:  D000         BEQ        .L18                     ; 0x08001B7C
+  0x08001B7A:  E2DC         B          .L61                     ; 0x08002136
+
.L18:
+  0x08001B7C:  2201         MOVS       R2, #1
+  0x08001B7E:  0510         LSLS       R0, R2, #20
+  0x08001B80:  6C21         LDR        R1, [R4, #64]
+  0x08001B82:  4301         ORRS       R1, R0
+  0x08001B84:  6421         STR        R1, [R4, #64]
+  0x08001B86:  6C21         LDR        R1, [R4, #64]
+  0x08001B88:  4001         ANDS       R1, R0
+  0x08001B8A:  9128         STR        R1, [SP, #160]
+  0x08001B8C:  9828         LDR        R0, [SP, #160]
+  0x08001B8E:  6B60         LDR        R0, [R4, #52]
+  0x08001B90:  921E         STR        R2, [SP, #120]
+  0x08001B92:  4310         ORRS       R0, R2
+  0x08001B94:  6360         STR        R0, [R4, #52]
+  0x08001B96:  6B60         LDR        R0, [R4, #52]
+  0x08001B98:  4010         ANDS       R0, R2
+  0x08001B9A:  9028         STR        R0, [SP, #160]
+  0x08001B9C:  9F1F         LDR        R7, [SP, #124]
+  0x08001B9E:  9732         STR        R7, [SP, #200]
+  0x08001BA0:  2003         MOVS       R0, #3
+  0x08001BA2:  9031         STR        R0, [SP, #196]
+  0x08001BA4:  981D         LDR        R0, [SP, #116]
+  0x08001BA6:  9030         STR        R0, [SP, #192]
+  0x08001BA8:  9828         LDR        R0, [SP, #160]
+  0x08001BAA:  A930         ADD        R1, SP, #192
+  0x08001BAC:  9809         LDR        R0, [SP, #36]
+  0x08001BAE:  F7FF F825    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x08001BB2:  981E         LDR        R0, [SP, #120]
+  0x08001BB4:  02C2         LSLS       R2, R0, #11
+  0x08001BB6:  4834         LDR        R0, =hdma_adc1           ; [PC, #208] [0x08001C88] =0x2000056C 
+  0x08001BB8:  6207         STR        R7, [R0, #32]
+  0x08001BBA:  4934         LDR        R1, =0x40020008          ; [PC, #208] [0x08001C8C] 
+  0x08001BBC:  6001         STR        R1, [R0]
+  0x08001BBE:  2105         MOVS       R1, #5
+  0x08001BC0:  6041         STR        R1, [R0, #4]
+  0x08001BC2:  6087         STR        R7, [R0, #8]
+  0x08001BC4:  60C7         STR        R7, [R0, #12]
+  0x08001BC6:  990A         LDR        R1, [SP, #40]
+  0x08001BC8:  6101         STR        R1, [R0, #16]
+  0x08001BCA:  9910         LDR        R1, [SP, #64]
+  0x08001BCC:  6141         STR        R1, [R0, #20]
+  0x08001BCE:  6182         STR        R2, [R0, #24]
+  0x08001BD0:  9F20         LDR        R7, [SP, #128]
+  0x08001BD2:  61C7         STR        R7, [R0, #28]
+  0x08001BD4:  F7FE FEB6    BL         HAL_DMA_Init             ; 0x08000944
+  0x08001BD8:  2800         CMP        R0, #0
+  0x08001BDA:  D000         BEQ        .L19                     ; 0x08001BDE
+  0x08001BDC:  E2AB         B          .L61                     ; 0x08002136
+
.L19:
+  0x08001BDE:  2054         MOVS       R0, #84
+  0x08001BE0:  991F         LDR        R1, [SP, #124]
+  0x08001BE2:  5431         STRB       R1, [R6, R0]
+  0x08001BE4:  4828         LDR        R0, =hdma_adc1           ; [PC, #160] [0x08001C88] =0x2000056C 
+  0x08001BE6:  6286         STR        R6, [R0, #40]
+  0x08001BE8:  6530         STR        R0, [R6, #80]
+  0x08001BEA:  65F1         STR        R1, [R6, #92]
+  0x08001BEC:  6833         LDR        R3, [R6]
+
.L20:
+  0x08001BEE:  0728         LSLS       R0, R5, #28
+  0x08001BF0:  901F         STR        R0, [SP, #124]
+  0x08001BF2:  6898         LDR        R0, [R3, #8]
+  0x08001BF4:  00C0         LSLS       R0, R0, #3
+  0x08001BF6:  9F12         LDR        R7, [SP, #72]
+  0x08001BF8:  4A15         LDR        R2, =SystemCoreClock     ; [PC, #84] [0x08001C50] =0x20000BA4 
+  0x08001BFA:  931E         STR        R3, [SP, #120]
+  0x08001BFC:  D44C         BMI        .L22                     ; 0x08001C98
+  0x08001BFE:  6898         LDR        R0, [R3, #8]
+  0x08001C00:  4923         LDR        R1, =0x6FFFFFE8          ; [PC, #140] [0x08001C90] 
+  0x08001C02:  4001         ANDS       R1, R0
+  0x08001C04:  981F         LDR        R0, [SP, #124]
+  0x08001C06:  4301         ORRS       R1, R0
+  0x08001C08:  6099         STR        R1, [R3, #8]
+  0x08001C0A:  6810         LDR        R0, [R2]
+  0x08001C0C:  4921         LDR        R1, =0x00030D40          ; [PC, #132] [0x08001C94] 
+  0x08001C0E:  F004 FA38    BL         __aeabi_uidiv            ; 0x08006082
+  0x08001C12:  9B1E         LDR        R3, [SP, #120]
+  0x08001C14:  0040         LSLS       R0, R0, #1
+
.L21:
+  0x08001C16:  9027         STR        R0, [SP, #156]
+  0x08001C18:  9827         LDR        R0, [SP, #156]
+  0x08001C1A:  2800         CMP        R0, #0
+  0x08001C1C:  D03C         BEQ        .L22                     ; 0x08001C98
+  0x08001C1E:  9827         LDR        R0, [SP, #156]
+  0x08001C20:  1E40         SUBS       R0, R0, #1
+  0x08001C22:  E7F8         B          .L21                     ; 0x08001C16
+  0x08001C24:  20000B7C     DC.W       bootLoaderMark
+  0x08001C28:  40022000     DC.W       0x40022000
+  0x08001C2C:  080061EA     DC.W       080061EA               ; R_ARM_ABS32
+  0x08001C30:  08192A3B     DC.W       0x08192A3B
+  0x08001C34:  4C5D6E7F     DC.W       0x4C5D6E7F
+  0x08001C38:  08000B8D     DC.W       FLASH_WaitForLastOperation
+  0x08001C3C:  40021000     DC.W       0x40021000
+  0x08001C40:  000003C7     DC.W       0x000003C7
+  0x08001C44:  FFFFC7FF     DC.W       0xFFFFC7FF
+  0x08001C48:  2000068C     DC.W       uwTick
+  0x08001C4C:  02DC6C00     DC.W       0x02DC6C00
+  0x08001C50:  20000BA4     DC.W       SystemCoreClock
+  0x08001C54:  20000B94     DC.W       uwTickPrio
+  0x08001C58:  FFFFF0FE     DC.W       0xFFFFF0FE
+  0x08001C5C:  00001388     DC.W       0x00001388
+  0x08001C60:  0800515C     DC.W       AHBPrescTable
+  0x08001C64:  50000818     DC.W       0x50000818
+  0x08001C68:  50000010     DC.W       0x50000010
+  0x08001C6C:  50000410     DC.W       0x50000410
+  0x08001C70:  08000BFD     DC.W       HAL_GPIO_Init
+  0x08001C74:  E000E408     DC.W       0xE000E408
+  0x08001C78:  E000E100     DC.W       0xE000E100
+  0x08001C7C:  20000450     DC.W       hadc1
+  0x08001C80:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08001C84:  40012400     DC.W       0x40012400
+  0x08001C88:  2000056C     DC.W       hdma_adc1
+  0x08001C8C:  40020008     DC.W       0x40020008
+  0x08001C90:  6FFFFFE8     DC.W       0x6FFFFFE8
+  0x08001C94:  00030D40     DC.W       0x00030D40
+
.L22:
+  0x08001C98:  6899         LDR        R1, [R3, #8]
+  0x08001C9A:  981F         LDR        R0, [SP, #124]
+  0x08001C9C:  4001         ANDS       R1, R0
+  0x08001C9E:  911A         STR        R1, [SP, #104]
+  0x08001CA0:  D107         BNE        .L23                     ; 0x08001CB2
+  0x08001CA2:  6DB0         LDR        R0, [R6, #88]
+  0x08001CA4:  2110         MOVS       R1, #16
+  0x08001CA6:  4301         ORRS       R1, R0
+  0x08001CA8:  65B1         STR        R1, [R6, #88]
+  0x08001CAA:  6DF0         LDR        R0, [R6, #92]
+  0x08001CAC:  2101         MOVS       R1, #1
+  0x08001CAE:  4301         ORRS       R1, R0
+  0x08001CB0:  65F1         STR        R1, [R6, #92]
+
.L23:
+  0x08001CB2:  6898         LDR        R0, [R3, #8]
+  0x08001CB4:  990F         LDR        R1, [SP, #60]
+  0x08001CB6:  4008         ANDS       R0, R1
+  0x08001CB8:  6DB2         LDR        R2, [R6, #88]
+  0x08001CBA:  2110         MOVS       R1, #16
+  0x08001CBC:  400A         ANDS       R2, R1
+  0x08001CBE:  1810         ADDS       R0, R2, R0
+  0x08001CC0:  6DB0         LDR        R0, [R6, #88]
+  0x08001CC2:  D001         BEQ        .L24                     ; 0x08001CC8
+  0x08001CC4:  F002 FC11    BL         .L289                    ; 0x080044EA
+
.L24:
+  0x08001CC8:  49CE         LDR        R1, =0xFFFFFEFD          ; [PC, #0x0338] [0x08002004] 
+  0x08001CCA:  4008         ANDS       R0, R1
+  0x08001CCC:  1C80         ADDS       R0, R0, #2
+  0x08001CCE:  65B0         STR        R0, [R6, #88]
+  0x08001CD0:  6930         LDR        R0, [R6, #16]
+  0x08001CD2:  901C         STR        R0, [SP, #112]
+  0x08001CD4:  6898         LDR        R0, [R3, #8]
+  0x08001CD6:  07C0         LSLS       R0, R0, #31
+  0x08001CD8:  D174         BNE        .L33                     ; 0x08001DC4
+  0x08001CDA:  6B30         LDR        R0, [R6, #48]
+  0x08001CDC:  2800         CMP        R0, #0
+  0x08001CDE:  9B14         LDR        R3, [SP, #80]
+  0x08001CE0:  D100         BNE        .L25                     ; 0x08001CE4
+  0x08001CE2:  2300         MOVS       R3, #0
+
.L25:
+  0x08001CE4:  2001         MOVS       R0, #1
+  0x08001CE6:  991C         LDR        R1, [SP, #112]
+  0x08001CE8:  2900         CMP        R1, #0
+  0x08001CEA:  9019         STR        R0, [SP, #100]
+  0x08001CEC:  DA03         BGE        .L26                     ; 0x08001CF6
+  0x08001CEE:  48C6         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0318] [0x08002008] 
+  0x08001CF0:  3017         ADDS       R0, #23
+  0x08001CF2:  4008         ANDS       R0, R1
+  0x08001CF4:  E000         B          .L27                     ; 0x08001CF8
+
.L26:
+  0x08001CF6:  0540         LSLS       R0, R0, #21
+
.L27:
+  0x08001CF8:  68B2         LDR        R2, [R6, #8]
+  0x08001CFA:  4302         ORRS       R2, R0
+  0x08001CFC:  7E30         LDRB       R0, [R6, #24]
+  0x08001CFE:  0380         LSLS       R0, R0, #14
+  0x08001D00:  4310         ORRS       R0, R2
+  0x08001D02:  7E72         LDRB       R2, [R6, #25]
+  0x08001D04:  03D2         LSLS       R2, R2, #15
+  0x08001D06:  4302         ORRS       R2, R0
+  0x08001D08:  7EB0         LDRB       R0, [R6, #26]
+  0x08001D0A:  0347         LSLS       R7, R0, #13
+  0x08001D0C:  4317         ORRS       R7, R2
+  0x08001D0E:  68F2         LDR        R2, [R6, #12]
+  0x08001D10:  433A         ORRS       R2, R7
+  0x08001D12:  431A         ORRS       R2, R3
+  0x08001D14:  9908         LDR        R1, [SP, #32]
+  0x08001D16:  5C73         LDRB       R3, [R6, R1]
+  0x08001D18:  005B         LSLS       R3, R3, #1
+  0x08001D1A:  4313         ORRS       R3, R2
+  0x08001D1C:  9920         LDR        R1, [SP, #128]
+  0x08001D1E:  5C72         LDRB       R2, [R6, R1]
+  0x08001D20:  2A01         CMP        R2, #1
+  0x08001D22:  D10C         BNE        .L29                     ; 0x08001D3E
+  0x08001D24:  2800         CMP        R0, #0
+  0x08001D26:  D007         BEQ        .L28                     ; 0x08001D38
+  0x08001D28:  6DB0         LDR        R0, [R6, #88]
+  0x08001D2A:  4308         ORRS       R0, R1
+  0x08001D2C:  65B0         STR        R0, [R6, #88]
+  0x08001D2E:  6DF0         LDR        R0, [R6, #92]
+  0x08001D30:  9919         LDR        R1, [SP, #100]
+  0x08001D32:  4308         ORRS       R0, R1
+  0x08001D34:  65F0         STR        R0, [R6, #92]
+  0x08001D36:  E002         B          .L29                     ; 0x08001D3E
+
.L28:
+  0x08001D38:  48B4         LDR        R0, =0x0000FFFF          ; [PC, #0x02D0] [0x0800200C] 
+  0x08001D3A:  1C40         ADDS       R0, R0, #1
+  0x08001D3C:  4303         ORRS       R3, R0
+
.L29:
+  0x08001D3E:  6A70         LDR        R0, [R6, #36]
+  0x08001D40:  6AB2         LDR        R2, [R6, #40]
+  0x08001D42:  991E         LDR        R1, [SP, #120]
+  0x08001D44:  68C9         LDR        R1, [R1, #12]
+  0x08001D46:  4FB2         LDR        R7, =0xFFDE0201          ; [PC, #0x02C8] [0x08002010] 
+  0x08001D48:  400F         ANDS       R7, R1
+  0x08001D4A:  2800         CMP        R0, #0
+  0x08001D4C:  D003         BEQ        .L30                     ; 0x08001D56
+  0x08001D4E:  9910         LDR        R1, [SP, #64]
+  0x08001D50:  31C0         ADDS       R1, #192
+  0x08001D52:  4008         ANDS       R0, R1
+  0x08001D54:  4310         ORRS       R0, R2
+
.L30:
+  0x08001D56:  4318         ORRS       R0, R3
+  0x08001D58:  4338         ORRS       R0, R7
+  0x08001D5A:  991E         LDR        R1, [SP, #120]
+  0x08001D5C:  60C8         STR        R0, [R1, #12]
+  0x08001D5E:  2003         MOVS       R0, #3
+  0x08001D60:  0780         LSLS       R0, R0, #30
+  0x08001D62:  6873         LDR        R3, [R6, #4]
+  0x08001D64:  9318         STR        R3, [SP, #96]
+  0x08001D66:  9017         STR        R0, [SP, #92]
+  0x08001D68:  4003         ANDS       R3, R0
+  0x08001D6A:  991D         LDR        R1, [SP, #116]
+  0x08001D6C:  5C71         LDRB       R1, [R6, R1]
+  0x08001D6E:  2901         CMP        R1, #1
+  0x08001D70:  6CF2         LDR        R2, [R6, #76]
+  0x08001D72:  9819         LDR        R0, [SP, #100]
+  0x08001D74:  D109         BNE        .L31                     ; 0x08001D8A
+  0x08001D76:  6C31         LDR        R1, [R6, #64]
+  0x08001D78:  6C77         LDR        R7, [R6, #68]
+  0x08001D7A:  430F         ORRS       R7, R1
+  0x08001D7C:  6CB1         LDR        R1, [R6, #72]
+  0x08001D7E:  4339         ORRS       R1, R7
+  0x08001D80:  4319         ORRS       R1, R3
+  0x08001D82:  4311         ORRS       R1, R2
+  0x08001D84:  4301         ORRS       R1, R0
+  0x08001D86:  460B         MOV        R3, R1
+  0x08001D88:  E000         B          .L32                     ; 0x08001D8C
+
.L31:
+  0x08001D8A:  4313         ORRS       R3, R2
+
.L32:
+  0x08001D8C:  9F1E         LDR        R7, [SP, #120]
+  0x08001D8E:  6939         LDR        R1, [R7, #16]
+  0x08001D90:  4AA0         LDR        R2, =0x1FFFFC02          ; [PC, #0x0280] [0x08002014] 
+  0x08001D92:  400A         ANDS       R2, R1
+  0x08001D94:  431A         ORRS       R2, R3
+  0x08001D96:  463B         MOV        R3, R7
+  0x08001D98:  613A         STR        R2, [R7, #16]
+  0x08001D9A:  07C1         LSLS       R1, R0, #31
+  0x08001D9C:  9A18         LDR        R2, [SP, #96]
+  0x08001D9E:  428A         CMP        R2, R1
+  0x08001DA0:  9F12         LDR        R7, [SP, #72]
+  0x08001DA2:  D00F         BEQ        .L33                     ; 0x08001DC4
+  0x08001DA4:  9917         LDR        R1, [SP, #92]
+  0x08001DA6:  428A         CMP        R2, R1
+  0x08001DA8:  D00C         BEQ        .L33                     ; 0x08001DC4
+  0x08001DAA:  0781         LSLS       R1, R0, #30
+  0x08001DAC:  428A         CMP        R2, R1
+  0x08001DAE:  D009         BEQ        .L33                     ; 0x08001DC4
+  0x08001DB0:  210F         MOVS       R1, #15
+  0x08001DB2:  0489         LSLS       R1, R1, #18
+  0x08001DB4:  400A         ANDS       R2, R1
+  0x08001DB6:  4610         MOV        R0, R2
+  0x08001DB8:  4A97         LDR        R2, =0x40012708          ; [PC, #0x025C] [0x08002018] 
+  0x08001DBA:  6813         LDR        R3, [R2]
+  0x08001DBC:  438B         BICS       R3, R1
+  0x08001DBE:  1818         ADDS       R0, R3, R0
+  0x08001DC0:  9B1E         LDR        R3, [SP, #120]
+  0x08001DC2:  6010         STR        R0, [R2]
+
.L33:
+  0x08001DC4:  6958         LDR        R0, [R3, #20]
+  0x08001DC6:  9923         LDR        R1, [SP, #140]
+  0x08001DC8:  4388         BICS       R0, R1
+  0x08001DCA:  6B72         LDR        R2, [R6, #52]
+  0x08001DCC:  4310         ORRS       R0, R2
+  0x08001DCE:  6158         STR        R0, [R3, #20]
+  0x08001DD0:  6958         LDR        R0, [R3, #20]
+  0x08001DD2:  2170         MOVS       R1, #112
+  0x08001DD4:  4388         BICS       R0, R1
+  0x08001DD6:  6BB1         LDR        R1, [R6, #56]
+  0x08001DD8:  0109         LSLS       R1, R1, #4
+  0x08001DDA:  4301         ORRS       R1, R0
+  0x08001DDC:  6159         STR        R1, [R3, #20]
+  0x08001DDE:  0568         LSLS       R0, R5, #21
+  0x08001DE0:  991C         LDR        R1, [SP, #112]
+  0x08001DE2:  4281         CMP        R1, R0
+  0x08001DE4:  D007         BEQ        .L34                     ; 0x08001DF6
+  0x08001DE6:  2900         CMP        R1, #0
+  0x08001DE8:  D111         BNE        .L35                     ; 0x08001E0E
+  0x08001DEA:  4886         LDR        R0, =0xFFFFFEFD          ; [PC, #0x0218] [0x08002004] 
+  0x08001DEC:  30F3         ADDS       R0, #243
+  0x08001DEE:  6A99         LDR        R1, [R3, #40]
+  0x08001DF0:  4301         ORRS       R1, R0
+  0x08001DF2:  6299         STR        R1, [R3, #40]
+  0x08001DF4:  E00B         B          .L35                     ; 0x08001E0E
+
.L34:
+  0x08001DF6:  6A98         LDR        R0, [R3, #40]
+  0x08001DF8:  69F0         LDR        R0, [R6, #28]
+  0x08001DFA:  0080         LSLS       R0, R0, #2
+  0x08001DFC:  301C         ADDS       R0, #28
+  0x08001DFE:  9904         LDR        R1, [SP, #16]
+  0x08001E00:  4008         ANDS       R0, R1
+  0x08001E02:  4980         LDR        R1, =0xFFFFFEFD          ; [PC, #0x0200] [0x08002004] 
+  0x08001E04:  31F3         ADDS       R1, #243
+  0x08001E06:  4081         LSLS       R1, R0
+  0x08001E08:  6E30         LDR        R0, [R6, #96]
+  0x08001E0A:  4308         ORRS       R0, R1
+  0x08001E0C:  6298         STR        R0, [R3, #40]
+
.L35:
+  0x08001E0E:  6958         LDR        R0, [R3, #20]
+  0x08001E10:  9923         LDR        R1, [SP, #140]
+  0x08001E12:  4008         ANDS       R0, R1
+  0x08001E14:  4290         CMP        R0, R2
+  0x08001E16:  D001         BEQ        .L36                     ; 0x08001E1C
+  0x08001E18:  F002 FB69    BL         .L290                    ; 0x080044EE
+
.L36:
+  0x08001E1C:  9821         LDR        R0, [SP, #132]
+  0x08001E1E:  65F0         STR        R0, [R6, #92]
+  0x08001E20:  6DB0         LDR        R0, [R6, #88]
+  0x08001E22:  2501         MOVS       R5, #1
+  0x08001E24:  4328         ORRS       R0, R5
+  0x08001E26:  43B8         BICS       R0, R7
+  0x08001E28:  65B0         STR        R0, [R6, #88]
+  0x08001E2A:  981A         LDR        R0, [SP, #104]
+  0x08001E2C:  2800         CMP        R0, #0
+  0x08001E2E:  D100         BNE        .L37                     ; 0x08001E32
+  0x08001E30:  E181         B          .L61                     ; 0x08002136
+
.L37:
+  0x08001E32:  9525         STR        R5, [SP, #148]
+  0x08001E34:  06E8         LSLS       R0, R5, #27
+  0x08001E36:  1D00         ADDS       R0, R0, #4
+  0x08001E38:  9024         STR        R0, [SP, #144]
+  0x08001E3A:  A824         ADD        R0, SP, #144
+  0x08001E3C:  F7FE FC44    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E40:  2800         CMP        R0, #0
+  0x08001E42:  D000         BEQ        .L38                     ; 0x08001E46
+  0x08001E44:  E177         B          .L61                     ; 0x08002136
+
.L38:
+  0x08001E46:  4875         LDR        R0, =0x0C000008          ; [PC, #0x01D4] [0x0800201C] 
+  0x08001E48:  9024         STR        R0, [SP, #144]
+  0x08001E4A:  A824         ADD        R0, SP, #144
+  0x08001E4C:  F7FE FC3C    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E50:  2800         CMP        R0, #0
+  0x08001E52:  D000         BEQ        .L39                     ; 0x08001E56
+  0x08001E54:  E16F         B          .L61                     ; 0x08002136
+
.L39:
+  0x08001E56:  981F         LDR        R0, [SP, #124]
+  0x08001E58:  3010         ADDS       R0, #16
+  0x08001E5A:  9024         STR        R0, [SP, #144]
+  0x08001E5C:  A824         ADD        R0, SP, #144
+  0x08001E5E:  F7FE FC33    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E62:  2800         CMP        R0, #0
+  0x08001E64:  D000         BEQ        .L40                     ; 0x08001E68
+  0x08001E66:  E166         B          .L61                     ; 0x08002136
+
.L40:
+  0x08001E68:  486D         LDR        R0, =0x14000020          ; [PC, #0x01B4] [0x08002020] 
+  0x08001E6A:  9024         STR        R0, [SP, #144]
+  0x08001E6C:  A824         ADD        R0, SP, #144
+  0x08001E6E:  F7FE FC2B    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E72:  2800         CMP        R0, #0
+  0x08001E74:  D000         BEQ        .L41                     ; 0x08001E78
+  0x08001E76:  E15E         B          .L61                     ; 0x08002136
+
.L41:
+  0x08001E78:  486A         LDR        R0, =0xA4000200          ; [PC, #0x01A8] [0x08002024] 
+  0x08001E7A:  9024         STR        R0, [SP, #144]
+  0x08001E7C:  A824         ADD        R0, SP, #144
+  0x08001E7E:  F7FE FC23    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E82:  2800         CMP        R0, #0
+  0x08001E84:  D000         BEQ        .L42                     ; 0x08001E88
+  0x08001E86:  E156         B          .L61                     ; 0x08002136
+
.L42:
+  0x08001E88:  4F67         LDR        R7, =htim16              ; [PC, #0x019C] [0x08002028] =0x20000614 
+  0x08001E8A:  2077         MOVS       R0, #119
+  0x08001E8C:  4967         LDR        R1, =0x40014400          ; [PC, #0x019C] [0x0800202C] 
+  0x08001E8E:  6039         STR        R1, [R7]
+  0x08001E90:  6078         STR        R0, [R7, #4]
+  0x08001E92:  9921         LDR        R1, [SP, #132]
+  0x08001E94:  60B9         STR        R1, [R7, #8]
+  0x08001E96:  485D         LDR        R0, =0x0000FFFF          ; [PC, #0x0174] [0x0800200C] 
+  0x08001E98:  60F8         STR        R0, [R7, #12]
+  0x08001E9A:  6139         STR        R1, [R7, #16]
+  0x08001E9C:  6179         STR        R1, [R7, #20]
+  0x08001E9E:  980A         LDR        R0, [SP, #40]
+  0x08001EA0:  61B8         STR        R0, [R7, #24]
+  0x08001EA2:  4638         MOV        R0, R7
+  0x08001EA4:  F7FF F838    BL         HAL_TIM_Base_Init        ; 0x08000F18
+  0x08001EA8:  2800         CMP        R0, #0
+  0x08001EAA:  D000         BEQ        .L43                     ; 0x08001EAE
+  0x08001EAC:  E143         B          .L61                     ; 0x08002136
+
.L43:
+  0x08001EAE:  263D         MOVS       R6, #61
+  0x08001EB0:  5DB8         LDRB       R0, [R7, R6]
+  0x08001EB2:  2800         CMP        R0, #0
+  0x08001EB4:  D101         BNE        .L44                     ; 0x08001EBA
+  0x08001EB6:  991D         LDR        R1, [SP, #116]
+  0x08001EB8:  5478         STRB       R0, [R7, R1]
+
.L44:
+  0x08001EBA:  9812         LDR        R0, [SP, #72]
+  0x08001EBC:  55B8         STRB       R0, [R7, R6]
+  0x08001EBE:  4639         MOV        R1, R7
+  0x08001EC0:  C901         LDM        R1!, {R0}
+  0x08001EC2:  F7FF F88F    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08001EC6:  2048         MOVS       R0, #72
+  0x08001EC8:  901F         STR        R0, [SP, #124]
+  0x08001ECA:  543D         STRB       R5, [R7, R0]
+  0x08001ECC:  203E         MOVS       R0, #62
+  0x08001ECE:  901C         STR        R0, [SP, #112]
+  0x08001ED0:  543D         STRB       R5, [R7, R0]
+  0x08001ED2:  203F         MOVS       R0, #63
+  0x08001ED4:  901E         STR        R0, [SP, #120]
+  0x08001ED6:  543D         STRB       R5, [R7, R0]
+  0x08001ED8:  9807         LDR        R0, [SP, #28]
+  0x08001EDA:  543D         STRB       R5, [R7, R0]
+  0x08001EDC:  2041         MOVS       R0, #65
+  0x08001EDE:  901A         STR        R0, [SP, #104]
+  0x08001EE0:  543D         STRB       R5, [R7, R0]
+  0x08001EE2:  2042         MOVS       R0, #66
+  0x08001EE4:  9017         STR        R0, [SP, #92]
+  0x08001EE6:  543D         STRB       R5, [R7, R0]
+  0x08001EE8:  2043         MOVS       R0, #67
+  0x08001EEA:  9016         STR        R0, [SP, #88]
+  0x08001EEC:  543D         STRB       R5, [R7, R0]
+  0x08001EEE:  2044         MOVS       R0, #68
+  0x08001EF0:  9011         STR        R0, [SP, #68]
+  0x08001EF2:  543D         STRB       R5, [R7, R0]
+  0x08001EF4:  2045         MOVS       R0, #69
+  0x08001EF6:  9019         STR        R0, [SP, #100]
+  0x08001EF8:  543D         STRB       R5, [R7, R0]
+  0x08001EFA:  2046         MOVS       R0, #70
+  0x08001EFC:  900D         STR        R0, [SP, #52]
+  0x08001EFE:  543D         STRB       R5, [R7, R0]
+  0x08001F00:  2047         MOVS       R0, #71
+  0x08001F02:  900B         STR        R0, [SP, #44]
+  0x08001F04:  543D         STRB       R5, [R7, R0]
+  0x08001F06:  55BD         STRB       R5, [R7, R6]
+  0x08001F08:  981D         LDR        R0, [SP, #116]
+  0x08001F0A:  5C38         LDRB       R0, [R7, R0]
+  0x08001F0C:  2801         CMP        R0, #1
+  0x08001F0E:  D100         BNE        .L45                     ; 0x08001F12
+  0x08001F10:  E111         B          .L61                     ; 0x08002136
+
.L45:
+  0x08001F12:  6838         LDR        R0, [R7]
+  0x08001F14:  6A01         LDR        R1, [R0, #32]
+  0x08001F16:  6A02         LDR        R2, [R0, #32]
+  0x08001F18:  43AA         BICS       R2, R5
+  0x08001F1A:  6202         STR        R2, [R0, #32]
+  0x08001F1C:  6982         LDR        R2, [R0, #24]
+  0x08001F1E:  4B44         LDR        R3, =0x40012C00          ; [PC, #0x0110] [0x08002030] 
+  0x08001F20:  4298         CMP        R0, R3
+  0x08001F22:  960C         STR        R6, [SP, #48]
+  0x08001F24:  D002         BEQ        .L46                     ; 0x08001F2C
+  0x08001F26:  4B43         LDR        R3, =0x40000400          ; [PC, #0x010C] [0x08002034] 
+  0x08001F28:  4298         CMP        R0, R3
+  0x08001F2A:  D101         BNE        .L47                     ; 0x08001F30
+
.L46:
+  0x08001F2C:  2303         MOVS       R3, #3
+  0x08001F2E:  439A         BICS       R2, R3
+
.L47:
+  0x08001F30:  9B1D         LDR        R3, [SP, #116]
+  0x08001F32:  9E21         LDR        R6, [SP, #132]
+  0x08001F34:  54FE         STRB       R6, [R7, R3]
+  0x08001F36:  432A         ORRS       R2, R5
+  0x08001F38:  23F0         MOVS       R3, #240
+  0x08001F3A:  439A         BICS       R2, R3
+  0x08001F3C:  6182         STR        R2, [R0, #24]
+  0x08001F3E:  9A12         LDR        R2, [SP, #72]
+  0x08001F40:  4311         ORRS       R1, R2
+  0x08001F42:  9A1B         LDR        R2, [SP, #108]
+  0x08001F44:  4391         BICS       R1, R2
+  0x08001F46:  6201         STR        R1, [R0, #32]
+  0x08001F48:  6981         LDR        R1, [R0, #24]
+  0x08001F4A:  220C         MOVS       R2, #12
+  0x08001F4C:  920E         STR        R2, [SP, #56]
+  0x08001F4E:  4391         BICS       R1, R2
+  0x08001F50:  6181         STR        R1, [R0, #24]
+  0x08001F52:  4F39         LDR        R7, =htim17              ; [PC, #228] [0x08002038] =0x200005C8 
+  0x08001F54:  4A39         LDR        R2, =0x40014800          ; [PC, #228] [0x0800203C] 
+  0x08001F56:  9910         LDR        R1, [SP, #64]
+  0x08001F58:  31DF         ADDS       R1, #223
+  0x08001F5A:  C744         STM        R7!, {R2, R6}
+  0x08001F5C:  603E         STR        R6, [R7]
+  0x08001F5E:  6079         STR        R1, [R7, #4]
+  0x08001F60:  60BE         STR        R6, [R7, #8]
+  0x08001F62:  60FE         STR        R6, [R7, #12]
+  0x08001F64:  990A         LDR        R1, [SP, #40]
+  0x08001F66:  6139         STR        R1, [R7, #16]
+  0x08001F68:  6981         LDR        R1, [R0, #24]
+  0x08001F6A:  6181         STR        R1, [R0, #24]
+  0x08001F6C:  3F08         SUBS       R7, #8
+  0x08001F6E:  4638         MOV        R0, R7
+  0x08001F70:  F7FE FFD2    BL         HAL_TIM_Base_Init        ; 0x08000F18
+  0x08001F74:  2800         CMP        R0, #0
+  0x08001F76:  D000         BEQ        .L48                     ; 0x08001F7A
+  0x08001F78:  E0DD         B          .L61                     ; 0x08002136
+
.L48:
+  0x08001F7A:  9E0C         LDR        R6, [SP, #48]
+  0x08001F7C:  5DB8         LDRB       R0, [R7, R6]
+  0x08001F7E:  2800         CMP        R0, #0
+  0x08001F80:  D101         BNE        .L49                     ; 0x08001F86
+  0x08001F82:  991D         LDR        R1, [SP, #116]
+  0x08001F84:  5478         STRB       R0, [R7, R1]
+
.L49:
+  0x08001F86:  9812         LDR        R0, [SP, #72]
+  0x08001F88:  55B8         STRB       R0, [R7, R6]
+  0x08001F8A:  CF01         LDM        R7!, {R0}
+  0x08001F8C:  4639         MOV        R1, R7
+  0x08001F8E:  F7FF F829    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08001F92:  4929         LDR        R1, =htim17              ; [PC, #164] [0x08002038] =0x200005C8 
+  0x08001F94:  981F         LDR        R0, [SP, #124]
+  0x08001F96:  540D         STRB       R5, [R1, R0]
+  0x08001F98:  981C         LDR        R0, [SP, #112]
+  0x08001F9A:  540D         STRB       R5, [R1, R0]
+  0x08001F9C:  981E         LDR        R0, [SP, #120]
+  0x08001F9E:  540D         STRB       R5, [R1, R0]
+  0x08001FA0:  9807         LDR        R0, [SP, #28]
+  0x08001FA2:  540D         STRB       R5, [R1, R0]
+  0x08001FA4:  981A         LDR        R0, [SP, #104]
+  0x08001FA6:  540D         STRB       R5, [R1, R0]
+  0x08001FA8:  9817         LDR        R0, [SP, #92]
+  0x08001FAA:  540D         STRB       R5, [R1, R0]
+  0x08001FAC:  9816         LDR        R0, [SP, #88]
+  0x08001FAE:  540D         STRB       R5, [R1, R0]
+  0x08001FB0:  9811         LDR        R0, [SP, #68]
+  0x08001FB2:  540D         STRB       R5, [R1, R0]
+  0x08001FB4:  9819         LDR        R0, [SP, #100]
+  0x08001FB6:  540D         STRB       R5, [R1, R0]
+  0x08001FB8:  980D         LDR        R0, [SP, #52]
+  0x08001FBA:  540D         STRB       R5, [R1, R0]
+  0x08001FBC:  980B         LDR        R0, [SP, #44]
+  0x08001FBE:  540D         STRB       R5, [R1, R0]
+  0x08001FC0:  558D         STRB       R5, [R1, R6]
+  0x08001FC2:  981D         LDR        R0, [SP, #116]
+  0x08001FC4:  5C08         LDRB       R0, [R1, R0]
+  0x08001FC6:  2801         CMP        R0, #1
+  0x08001FC8:  D100         BNE        .L50                     ; 0x08001FCC
+  0x08001FCA:  E0B4         B          .L61                     ; 0x08002136
+
.L50:
+  0x08001FCC:  6808         LDR        R0, [R1]
+  0x08001FCE:  6A01         LDR        R1, [R0, #32]
+  0x08001FD0:  6A02         LDR        R2, [R0, #32]
+  0x08001FD2:  43AA         BICS       R2, R5
+  0x08001FD4:  6202         STR        R2, [R0, #32]
+  0x08001FD6:  9A12         LDR        R2, [SP, #72]
+  0x08001FD8:  4311         ORRS       R1, R2
+  0x08001FDA:  6846         LDR        R6, [R0, #4]
+  0x08001FDC:  6982         LDR        R2, [R0, #24]
+  0x08001FDE:  921F         STR        R2, [SP, #124]
+  0x08001FE0:  4B13         LDR        R3, =0x40012C00          ; [PC, #76] [0x08002030] 
+  0x08001FE2:  4298         CMP        R0, R3
+  0x08001FE4:  D02C         BEQ        .L53                     ; 0x08002040
+  0x08001FE6:  4B15         LDR        R3, =0x40014800          ; [PC, #84] [0x0800203C] 
+  0x08001FE8:  4298         CMP        R0, R3
+  0x08001FEA:  D002         BEQ        .L51                     ; 0x08001FF2
+  0x08001FEC:  4B0F         LDR        R3, =0x40014400          ; [PC, #60] [0x0800202C] 
+  0x08001FEE:  4298         CMP        R0, R3
+  0x08001FF0:  D101         BNE        .L52                     ; 0x08001FF6
+
.L51:
+  0x08001FF2:  9F0E         LDR        R7, [SP, #56]
+  0x08001FF4:  43B9         BICS       R1, R7
+
.L52:
+  0x08001FF6:  4B11         LDR        R3, =0x40014800          ; [PC, #68] [0x0800203C] 
+  0x08001FF8:  4298         CMP        R0, R3
+  0x08001FFA:  D023         BEQ        .L54                     ; 0x08002044
+  0x08001FFC:  4B0B         LDR        R3, =0x40014400          ; [PC, #44] [0x0800202C] 
+  0x08001FFE:  4298         CMP        R0, R3
+  0x08002000:  D020         BEQ        .L54                     ; 0x08002044
+  0x08002002:  E021         B          .L55                     ; 0x08002048
+  0x08002004:  FFFFFEFD     DC.W       0xFFFFFEFD
+  0x08002008:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x0800200C:  0000FFFF     DC.W       0x0000FFFF
+  0x08002010:  FFDE0201     DC.W       0xFFDE0201
+  0x08002014:  1FFFFC02     DC.W       0x1FFFFC02
+  0x08002018:  40012708     DC.W       0x40012708
+  0x0800201C:  0C000008     DC.W       0x0C000008
+  0x08002020:  14000020     DC.W       0x14000020
+  0x08002024:  A4000200     DC.W       0xA4000200
+  0x08002028:  20000614     DC.W       htim16
+  0x0800202C:  40014400     DC.W       0x40014400
+  0x08002030:  40012C00     DC.W       0x40012C00
+  0x08002034:  40000400     DC.W       0x40000400
+  0x08002038:  200005C8     DC.W       htim17
+  0x0800203C:  40014800     DC.W       0x40014800
+
.L53:
+  0x08002040:  9F0E         LDR        R7, [SP, #56]
+  0x08002042:  43B9         BICS       R1, R7
+
.L54:
+  0x08002044:  4BBB         LDR        R3, =0xFFFFFCFF          ; [PC, #0x02EC] [0x08002334] 
+  0x08002046:  401E         ANDS       R6, R3
+
.L55:
+  0x08002048:  4632         MOV        R2, R6
+  0x0800204A:  9F1D         LDR        R7, [SP, #116]
+  0x0800204C:  4BBA         LDR        R3, =htim17              ; [PC, #0x02E8] [0x08002338] =0x200005C8 
+  0x0800204E:  9E21         LDR        R6, [SP, #132]
+  0x08002050:  55DE         STRB       R6, [R3, R7]
+  0x08002052:  6042         STR        R2, [R0, #4]
+  0x08002054:  4BB9         LDR        R3, =0xFFFEFF8C          ; [PC, #0x02E4] [0x0800233C] 
+  0x08002056:  9A1F         LDR        R2, [SP, #124]
+  0x08002058:  401A         ANDS       R2, R3
+  0x0800205A:  3260         ADDS       R2, #96
+  0x0800205C:  6182         STR        R2, [R0, #24]
+  0x0800205E:  6346         STR        R6, [R0, #52]
+  0x08002060:  6201         STR        R1, [R0, #32]
+  0x08002062:  6981         LDR        R1, [R0, #24]
+  0x08002064:  9A1B         LDR        R2, [SP, #108]
+  0x08002066:  4311         ORRS       R1, R2
+  0x08002068:  6181         STR        R1, [R0, #24]
+  0x0800206A:  6981         LDR        R1, [R0, #24]
+  0x0800206C:  9A0F         LDR        R2, [SP, #60]
+  0x0800206E:  4391         BICS       R1, R2
+  0x08002070:  6181         STR        R1, [R0, #24]
+  0x08002072:  6981         LDR        R1, [R0, #24]
+  0x08002074:  6181         STR        R1, [R0, #24]
+  0x08002076:  0369         LSLS       R1, R5, #13
+  0x08002078:  9116         STR        R1, [SP, #88]
+  0x0800207A:  6441         STR        R1, [R0, #68]
+  0x0800207C:  49B0         LDR        R1, =0x40014800          ; [PC, #0x02C0] [0x08002340] 
+  0x0800207E:  4288         CMP        R0, R1
+  0x08002080:  4FB0         LDR        R7, =0x000003C7          ; [PC, #0x02C0] [0x08002344] 
+  0x08002082:  D140         BNE        .L59                     ; 0x08002106
+  0x08002084:  6B60         LDR        R0, [R4, #52]
+  0x08002086:  2601         MOVS       R6, #1
+  0x08002088:  4330         ORRS       R0, R6
+  0x0800208A:  6360         STR        R0, [R4, #52]
+  0x0800208C:  6B60         LDR        R0, [R4, #52]
+  0x0800208E:  4030         ANDS       R0, R6
+  0x08002090:  9030         STR        R0, [SP, #192]
+  0x08002092:  2005         MOVS       R0, #5
+  0x08002094:  902D         STR        R0, [SP, #180]
+  0x08002096:  2000         MOVS       R0, #0
+  0x08002098:  902C         STR        R0, [SP, #176]
+  0x0800209A:  902B         STR        R0, [SP, #172]
+  0x0800209C:  2402         MOVS       R4, #2
+  0x0800209E:  942A         STR        R4, [SP, #168]
+  0x080020A0:  980A         LDR        R0, [SP, #40]
+  0x080020A2:  9029         STR        R0, [SP, #164]
+  0x080020A4:  9830         LDR        R0, [SP, #192]
+  0x080020A6:  A929         ADD        R1, SP, #164
+  0x080020A8:  9809         LDR        R0, [SP, #36]
+  0x080020AA:  F7FE FDA7    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x080020AE:  49A2         LDR        R1, =htim17              ; [PC, #0x0288] [0x08002338] =0x200005C8 
+  0x080020B0:  9A1C         LDR        R2, [SP, #112]
+  0x080020B2:  5C88         LDRB       R0, [R1, R2]
+  0x080020B4:  2801         CMP        R0, #1
+  0x080020B6:  D13E         BNE        .L61                     ; 0x08002136
+  0x080020B8:  548C         STRB       R4, [R1, R2]
+  0x080020BA:  6808         LDR        R0, [R1]
+  0x080020BC:  6A01         LDR        R1, [R0, #32]
+  0x080020BE:  43B1         BICS       R1, R6
+  0x080020C0:  6201         STR        R1, [R0, #32]
+  0x080020C2:  6A01         LDR        R1, [R0, #32]
+  0x080020C4:  4331         ORRS       R1, R6
+  0x080020C6:  6201         STR        R1, [R0, #32]
+  0x080020C8:  499F         LDR        R1, =0x40000400          ; [PC, #0x027C] [0x08002348] 
+  0x080020CA:  4288         CMP        R0, R1
+  0x080020CC:  D00F         BEQ        .L57                     ; 0x080020EE
+  0x080020CE:  499F         LDR        R1, =0x40012C00          ; [PC, #0x027C] [0x0800234C] 
+  0x080020D0:  4288         CMP        R0, R1
+  0x080020D2:  D005         BEQ        .L56                     ; 0x080020E0
+  0x080020D4:  499A         LDR        R1, =0x40014800          ; [PC, #0x0268] [0x08002340] 
+  0x080020D6:  4288         CMP        R0, R1
+  0x080020D8:  D002         BEQ        .L56                     ; 0x080020E0
+  0x080020DA:  499D         LDR        R1, =0x40014400          ; [PC, #0x0274] [0x08002350] 
+  0x080020DC:  4288         CMP        R0, R1
+  0x080020DE:  D10F         BNE        .L58                     ; 0x08002100
+
.L56:
+  0x080020E0:  03F1         LSLS       R1, R6, #15
+  0x080020E2:  6C42         LDR        R2, [R0, #68]
+  0x080020E4:  430A         ORRS       R2, R1
+  0x080020E6:  6442         STR        R2, [R0, #68]
+  0x080020E8:  4998         LDR        R1, =0x40012C00          ; [PC, #0x0260] [0x0800234C] 
+  0x080020EA:  4288         CMP        R0, R1
+  0x080020EC:  D108         BNE        .L58                     ; 0x08002100
+
.L57:
+  0x080020EE:  4A99         LDR        R2, =0x0000FFFF          ; [PC, #0x0264] [0x08002354] 
+  0x080020F0:  3208         ADDS       R2, #8
+  0x080020F2:  6881         LDR        R1, [R0, #8]
+  0x080020F4:  4011         ANDS       R1, R2
+  0x080020F6:  2906         CMP        R1, #6
+  0x080020F8:  D005         BEQ        .L59                     ; 0x08002106
+  0x080020FA:  0432         LSLS       R2, R6, #16
+  0x080020FC:  4291         CMP        R1, R2
+  0x080020FE:  D002         BEQ        .L59                     ; 0x08002106
+
.L58:
+  0x08002100:  6801         LDR        R1, [R0]
+  0x08002102:  4331         ORRS       R1, R6
+  0x08002104:  6001         STR        R1, [R0]
+
.L59:
+  0x08002106:  4B94         LDR        R3, =0x40003000          ; [PC, #0x0250] [0x08002358] 
+  0x08002108:  4894         LDR        R0, =0x0000CCCC          ; [PC, #0x0250] [0x0800235C] 
+  0x0800210A:  6018         STR        R0, [R3]
+  0x0800210C:  4894         LDR        R0, =0x00005555          ; [PC, #0x0250] [0x08002360] 
+  0x0800210E:  6018         STR        R0, [R3]
+  0x08002110:  9815         LDR        R0, [SP, #84]
+  0x08002112:  6058         STR        R0, [R3, #4]
+  0x08002114:  463C         MOV        R4, R7
+  0x08002116:  3421         ADDS       R4, #33
+  0x08002118:  609C         STR        R4, [R3, #8]
+  0x0800211A:  4892         LDR        R0, =uwTick              ; [PC, #0x0248] [0x08002364] =0x2000068C 
+  0x0800211C:  6800         LDR        R0, [R0]
+  0x0800211E:  9A14         LDR        R2, [SP, #80]
+
.L60:
+  0x08002120:  68D9         LDR        R1, [R3, #12]
+  0x08002122:  0749         LSLS       R1, R1, #29
+  0x08002124:  D009         BEQ        .L62                     ; 0x0800213A
+  0x08002126:  498F         LDR        R1, =uwTick              ; [PC, #0x023C] [0x08002364] =0x2000068C 
+  0x08002128:  6809         LDR        R1, [R1]
+  0x0800212A:  1A09         SUBS       R1, R1, R0
+  0x0800212C:  2932         CMP        R1, #50
+  0x0800212E:  D3F7         BCC        .L60                     ; 0x08002120
+  0x08002130:  68D9         LDR        R1, [R3, #12]
+  0x08002132:  0749         LSLS       R1, R1, #29
+  0x08002134:  D0F4         BEQ        .L60                     ; 0x08002120
+
.L61:
+  0x08002136:  F003 FED6    BL         Error_Handler            ; 0x08005EE6
+
.L62:
+  0x0800213A:  6918         LDR        R0, [R3, #16]
+  0x0800213C:  42A0         CMP        R0, R4
+  0x0800213E:  D102         BNE        .L63                     ; 0x08002146
+  0x08002140:  4889         LDR        R0, =0x0000AAAA          ; [PC, #0x0224] [0x08002368] 
+  0x08002142:  6018         STR        R0, [R3]
+  0x08002144:  E000         B          .L64                     ; 0x08002148
+
.L63:
+  0x08002146:  611C         STR        R4, [R3, #16]
+
.L64:
+  0x08002148:  4F88         LDR        R7, =huart1              ; [PC, #0x0220] [0x0800236C] =0x200003BC 
+  0x0800214A:  4889         LDR        R0, =0x40013800          ; [PC, #0x0224] [0x08002370] 
+  0x0800214C:  6038         STR        R0, [R7]
+  0x0800214E:  204B         MOVS       R0, #75
+  0x08002150:  9005         STR        R0, [SP, #20]
+  0x08002152:  0200         LSLS       R0, R0, #8
+  0x08002154:  901A         STR        R0, [SP, #104]
+  0x08002156:  6078         STR        R0, [R7, #4]
+  0x08002158:  60BA         STR        R2, [R7, #8]
+  0x0800215A:  9821         LDR        R0, [SP, #132]
+  0x0800215C:  60F8         STR        R0, [R7, #12]
+  0x0800215E:  9822         LDR        R0, [SP, #136]
+  0x08002160:  6138         STR        R0, [R7, #16]
+  0x08002162:  980E         LDR        R0, [SP, #56]
+  0x08002164:  6178         STR        R0, [R7, #20]
+  0x08002166:  4638         MOV        R0, R7
+  0x08002168:  3018         ADDS       R0, #24
+  0x0800216A:  2114         MOVS       R1, #20
+  0x0800216C:  F004 F81F    BL         __aeabi_memclr           ; 0x080061AE
+  0x08002170:  F7FE FF80    BL         HAL_UART_Init            ; 0x08001074
+  0x08002174:  2800         CMP        R0, #0
+  0x08002176:  D1DE         BNE        .L61                     ; 0x08002136
+  0x08002178:  940B         STR        R4, [SP, #44]
+  0x0800217A:  2684         MOVS       R6, #132
+  0x0800217C:  5DB8         LDRB       R0, [R7, R6]
+  0x0800217E:  2801         CMP        R0, #1
+  0x08002180:  D0D9         BEQ        .L61                     ; 0x08002136
+  0x08002182:  2488         MOVS       R4, #136
+  0x08002184:  2024         MOVS       R0, #36
+  0x08002186:  901F         STR        R0, [SP, #124]
+  0x08002188:  5138         STR        R0, [R7, R4]
+  0x0800218A:  55BD         STRB       R5, [R7, R6]
+  0x0800218C:  6838         LDR        R0, [R7]
+  0x0800218E:  6807         LDR        R7, [R0]
+  0x08002190:  43EA         MVNS       R2, R5
+  0x08002192:  921E         STR        R2, [SP, #120]
+  0x08002194:  6801         LDR        R1, [R0]
+  0x08002196:  4011         ANDS       R1, R2
+  0x08002198:  6001         STR        R1, [R0]
+  0x0800219A:  9923         LDR        R1, [SP, #140]
+  0x0800219C:  0749         LSLS       R1, R1, #29
+  0x0800219E:  6882         LDR        R2, [R0, #8]
+  0x080021A0:  438A         BICS       R2, R1
+  0x080021A2:  6082         STR        R2, [R0, #8]
+  0x080021A4:  F7FF FA50    BL         UARTEx_SetNbDataToProcess ; 0x08001648
+  0x080021A8:  4870         LDR        R0, =huart1              ; [PC, #0x01C0] [0x0800236C] =0x200003BC 
+  0x080021AA:  6800         LDR        R0, [R0]
+  0x080021AC:  6007         STR        R7, [R0]
+  0x080021AE:  9F20         LDR        R7, [SP, #128]
+  0x080021B0:  496E         LDR        R1, =huart1              ; [PC, #0x01B8] [0x0800236C] =0x200003BC 
+  0x080021B2:  510F         STR        R7, [R1, R4]
+  0x080021B4:  9A1F         LDR        R2, [SP, #124]
+  0x080021B6:  510A         STR        R2, [R1, R4]
+  0x080021B8:  558D         STRB       R5, [R1, R6]
+  0x080021BA:  6801         LDR        R1, [R0]
+  0x080021BC:  9117         STR        R1, [SP, #92]
+  0x080021BE:  6801         LDR        R1, [R0]
+  0x080021C0:  9A1E         LDR        R2, [SP, #120]
+  0x080021C2:  4011         ANDS       R1, R2
+  0x080021C4:  6001         STR        R1, [R0]
+  0x080021C6:  9923         LDR        R1, [SP, #140]
+  0x080021C8:  0649         LSLS       R1, R1, #25
+  0x080021CA:  6882         LDR        R2, [R0, #8]
+  0x080021CC:  438A         BICS       R2, R1
+  0x080021CE:  6082         STR        R2, [R0, #8]
+  0x080021D0:  F7FF FA3A    BL         UARTEx_SetNbDataToProcess ; 0x08001648
+  0x080021D4:  4865         LDR        R0, =huart1              ; [PC, #0x0194] [0x0800236C] =0x200003BC 
+  0x080021D6:  6800         LDR        R0, [R0]
+  0x080021D8:  9917         LDR        R1, [SP, #92]
+  0x080021DA:  6001         STR        R1, [R0]
+  0x080021DC:  4963         LDR        R1, =huart1              ; [PC, #0x018C] [0x0800236C] =0x200003BC 
+  0x080021DE:  510F         STR        R7, [R1, R4]
+  0x080021E0:  9A1F         LDR        R2, [SP, #124]
+  0x080021E2:  510A         STR        R2, [R1, R4]
+  0x080021E4:  9B21         LDR        R3, [SP, #132]
+  0x080021E6:  9617         STR        R6, [SP, #92]
+  0x080021E8:  558B         STRB       R3, [R1, R6]
+  0x080021EA:  6801         LDR        R1, [R0]
+  0x080021EC:  6802         LDR        R2, [R0]
+  0x080021EE:  9E1E         LDR        R6, [SP, #120]
+  0x080021F0:  4032         ANDS       R2, R6
+  0x080021F2:  6002         STR        R2, [R0]
+  0x080021F4:  076A         LSLS       R2, R5, #29
+  0x080021F6:  4391         BICS       R1, R2
+  0x080021F8:  6001         STR        R1, [R0]
+  0x080021FA:  485C         LDR        R0, =huart1              ; [PC, #0x0170] [0x0800236C] =0x200003BC 
+  0x080021FC:  940D         STR        R4, [SP, #52]
+  0x080021FE:  5107         STR        R7, [R0, R4]
+  0x08002200:  6643         STR        R3, [R0, #100]
+  0x08002202:  485C         LDR        R0, =0x0800780E          ; [PC, #0x0170] [0x08002374] 
+  0x08002204:  8800         LDRH       R0, [R0]
+  0x08002206:  2802         CMP        R0, #2
+  0x08002208:  D003         BEQ        .L65                     ; 0x08002212
+  0x0800220A:  28FF         CMP        R0, #255
+  0x0800220C:  D105         BNE        .L66                     ; 0x0800221A
+  0x0800220E:  485A         LDR        R0, =0x0800640B          ; [PC, #0x0168] [0x08002378] 
+  0x08002210:  E004         B          .L67                     ; 0x0800221C
+
.L65:
+  0x08002212:  485A         LDR        R0, =0x080063F9          ; [PC, #0x0168] [0x0800237C] 
+  0x08002214:  F002 FFEC    BL         puts                     ; 0x080051F0
+  0x08002218:  E004         B          .L68                     ; 0x08002224
+
.L66:
+  0x0800221A:  4859         LDR        R0, =0x080061FD          ; [PC, #0x0164] [0x08002380] 
+
.L67:
+  0x0800221C:  F002 FFE8    BL         puts                     ; 0x080051F0
+  0x08002220:  F7FF FAC8    BL         EEPROM_WriteDefaults     ; 0x080017B4
+
.L68:
+  0x08002224:  9E14         LDR        R6, [SP, #80]
+  0x08002226:  F7FF FADD    BL         EEPROM_ReadDeviceParameter ; 0x080017E4
+  0x0800222A:  9805         LDR        R0, [SP, #20]
+  0x0800222C:  00C0         LSLS       R0, R0, #3
+  0x0800222E:  4C55         LDR        R4, =sys_data            ; [PC, #0x0154] [0x08002384] =0x20000234 
+  0x08002230:  8020         STRH       R0, [R4]
+  0x08002232:  8125         STRH       R5, [R4, #8]
+  0x08002234:  9821         LDR        R0, [SP, #132]
+  0x08002236:  8160         STRH       R0, [R4, #10]
+  0x08002238:  81A0         STRH       R0, [R4, #12]
+  0x0800223A:  4853         LDR        R0, =0x08006890          ; [PC, #0x014C] [0x08002388] 
+  0x0800223C:  F002 FFD8    BL         puts                     ; 0x080051F0
+  0x08002240:  6923         LDR        R3, [R4, #16]
+  0x08002242:  8AA1         LDRH       R1, [R4, #20]
+  0x08002244:  8AE0         LDRH       R0, [R4, #22]
+  0x08002246:  2800         CMP        R0, #0
+  0x08002248:  D001         BEQ        .L69                     ; 0x0800224E
+  0x0800224A:  2803         CMP        R0, #3
+  0x0800224C:  D300         BCC        .L70                     ; 0x08002250
+
.L69:
+  0x0800224E:  2001         MOVS       R0, #1
+
.L70:
+  0x08002250:  2900         CMP        R1, #0
+  0x08002252:  D001         BEQ        .L71                     ; 0x08002258
+  0x08002254:  2901         CMP        R1, #1
+  0x08002256:  D102         BNE        .L72                     ; 0x0800225E
+
.L71:
+  0x08002258:  4607         MOV        R7, R0
+  0x0800225A:  370A         ADDS       R7, #10
+  0x0800225C:  E001         B          .L73                     ; 0x08002262
+
.L72:
+  0x0800225E:  4607         MOV        R7, R0
+  0x08002260:  3709         ADDS       R7, #9
+
.L73:
+  0x08002262:  4A42         LDR        R2, =huart1              ; [PC, #0x0108] [0x0800236C] =0x200003BC 
+  0x08002264:  9323         STR        R3, [SP, #140]
+  0x08002266:  6053         STR        R3, [R2, #4]
+  0x08002268:  4B48         LDR        R3, =modbusData          ; [PC, #0x0120] [0x0800238C] =0x20000000 
+  0x0800226A:  601A         STR        R2, [R3]
+  0x0800226C:  2900         CMP        R1, #0
+  0x0800226E:  4632         MOV        R2, R6
+  0x08002270:  D007         BEQ        .L75                     ; 0x08002282
+  0x08002272:  2901         CMP        R1, #1
+  0x08002274:  D103         BNE        .L74                     ; 0x0800227E
+  0x08002276:  9915         LDR        R1, [SP, #84]
+  0x08002278:  0249         LSLS       R1, R1, #9
+  0x0800227A:  9122         STR        R1, [SP, #136]
+  0x0800227C:  E001         B          .L75                     ; 0x08002282
+
.L74:
+  0x0800227E:  9A21         LDR        R2, [SP, #132]
+  0x08002280:  9222         STR        R2, [SP, #136]
+
.L75:
+  0x08002282:  493A         LDR        R1, =huart1              ; [PC, #232] [0x0800236C] =0x200003BC 
+  0x08002284:  608A         STR        R2, [R1, #8]
+  0x08002286:  9A22         LDR        R2, [SP, #136]
+  0x08002288:  610A         STR        R2, [R1, #16]
+  0x0800228A:  2801         CMP        R0, #1
+  0x0800228C:  D001         BEQ        .L76                     ; 0x08002292
+  0x0800228E:  9816         LDR        R0, [SP, #88]
+  0x08002290:  9021         STR        R0, [SP, #132]
+
.L76:
+  0x08002292:  9821         LDR        R0, [SP, #132]
+  0x08002294:  60C8         STR        R0, [R1, #12]
+  0x08002296:  460C         MOV        R4, R1
+  0x08002298:  F7FE FEEC    BL         HAL_UART_Init            ; 0x08001074
+  0x0800229C:  2800         CMP        R0, #0
+  0x0800229E:  D001         BEQ        .L77                     ; 0x080022A4
+  0x080022A0:  F002 F931    BL         .L292                    ; 0x08004506
+
.L77:
+  0x080022A4:  980D         LDR        R0, [SP, #52]
+  0x080022A6:  5820         LDR        R0, [R4, R0]
+  0x080022A8:  2820         CMP        R0, #32
+  0x080022AA:  9A17         LDR        R2, [SP, #92]
+  0x080022AC:  9B23         LDR        R3, [SP, #140]
+  0x080022AE:  D111         BNE        .L78                     ; 0x080022D4
+  0x080022B0:  4621         MOV        R1, R4
+  0x080022B2:  5CA0         LDRB       R0, [R4, R2]
+  0x080022B4:  2801         CMP        R0, #1
+  0x080022B6:  D00D         BEQ        .L78                     ; 0x080022D4
+  0x080022B8:  9B0D         LDR        R3, [SP, #52]
+  0x080022BA:  981F         LDR        R0, [SP, #124]
+  0x080022BC:  50C8         STR        R0, [R1, R3]
+  0x080022BE:  2000         MOVS       R0, #0
+  0x080022C0:  5488         STRB       R0, [R1, R2]
+  0x080022C2:  2001         MOVS       R0, #1
+  0x080022C4:  05C0         LSLS       R0, R0, #23
+  0x080022C6:  6809         LDR        R1, [R1]
+  0x080022C8:  684A         LDR        R2, [R1, #4]
+  0x080022CA:  4302         ORRS       R2, R0
+  0x080022CC:  604A         STR        R2, [R1, #4]
+  0x080022CE:  9820         LDR        R0, [SP, #128]
+  0x080022D0:  50E0         STR        R0, [R4, R3]
+  0x080022D2:  9B23         LDR        R3, [SP, #140]
+
.L78:
+  0x080022D4:  981A         LDR        R0, [SP, #104]
+  0x080022D6:  1C40         ADDS       R0, R0, #1
+  0x080022D8:  4283         CMP        R3, R0
+  0x080022DA:  4C2C         LDR        R4, =modbusData          ; [PC, #176] [0x0800238C] =0x20000000 
+  0x080022DC:  D209         BCS        .L79                     ; 0x080022F2
+  0x080022DE:  4638         MOV        R0, R7
+  0x080022E0:  F003 FEA1    BL         __aeabi_ui2d             ; 0x08006026
+  0x080022E4:  2200         MOVS       R2, #0
+  0x080022E6:  4B2A         LDR        R3, =0x400C0000          ; [PC, #168] [0x08002390] 
+  0x080022E8:  F003 FB89    BL         __aeabi_dmul             ; 0x080059FE
+  0x080022EC:  F003 FC30    BL         __aeabi_d2uiz            ; 0x08005B50
+  0x080022F0:  E007         B          .L80                     ; 0x08002302
+
.L79:
+  0x080022F2:  9815         LDR        R0, [SP, #84]
+  0x080022F4:  0240         LSLS       R0, R0, #9
+  0x080022F6:  30D6         ADDS       R0, #214
+  0x080022F8:  4358         MULS       R0, R3, R0
+  0x080022FA:  4926         LDR        R1, =0x000F4240          ; [PC, #152] [0x08002394] 
+  0x080022FC:  F003 FEC1    BL         __aeabi_uidiv            ; 0x08006082
+  0x08002300:  1C40         ADDS       R0, R0, #1
+
.L80:
+  0x08002302:  4925         LDR        R1, =0xFEFFFFFF          ; [PC, #148] [0x08002398] 
+  0x08002304:  1C49         ADDS       R1, R1, #1
+  0x08002306:  4A19         LDR        R2, =huart1              ; [PC, #100] [0x0800236C] =0x200003BC 
+  0x08002308:  6812         LDR        R2, [R2]
+  0x0800230A:  6953         LDR        R3, [R2, #20]
+  0x0800230C:  400B         ANDS       R3, R1
+  0x0800230E:  4303         ORRS       R3, R0
+  0x08002310:  6153         STR        R3, [R2, #20]
+  0x08002312:  06A8         LSLS       R0, R5, #26
+  0x08002314:  6811         LDR        R1, [R2]
+  0x08002316:  4301         ORRS       R1, R0
+  0x08002318:  6011         STR        R1, [R2]
+  0x0800231A:  6820         LDR        R0, [R4]
+  0x0800231C:  4626         MOV        R6, R4
+  0x0800231E:  3627         ADDS       R6, #39
+  0x08002320:  4631         MOV        R1, R6
+  0x08002322:  F7FF F915    BL         HAL_UART_Receive_DMA     ; 0x08001550
+  0x08002326:  2800         CMP        R0, #0
+  0x08002328:  D03A         BEQ        .L82                     ; 0x080023A0
+  0x0800232A:  481C         LDR        R0, =0x08006439          ; [PC, #112] [0x0800239C] 
+  0x0800232C:  F002 FFBA    BL         printf                   ; 0x080052A4
+
.L81:
+  0x08002330:  E7FE         B          .L81                     ; 0x08002330
+  0x08002332:  46C0         NOP
+  0x08002334:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08002338:  200005C8     DC.W       htim17
+  0x0800233C:  FFFEFF8C     DC.W       0xFFFEFF8C
+  0x08002340:  40014800     DC.W       0x40014800
+  0x08002344:  000003C7     DC.W       0x000003C7
+  0x08002348:  40000400     DC.W       0x40000400
+  0x0800234C:  40012C00     DC.W       0x40012C00
+  0x08002350:  40014400     DC.W       0x40014400
+  0x08002354:  0000FFFF     DC.W       0x0000FFFF
+  0x08002358:  40003000     DC.W       0x40003000
+  0x0800235C:  0000CCCC     DC.W       0x0000CCCC
+  0x08002360:  00005555     DC.W       0x00005555
+  0x08002364:  2000068C     DC.W       uwTick
+  0x08002368:  0000AAAA     DC.W       0x0000AAAA
+  0x0800236C:  200003BC     DC.W       huart1
+  0x08002370:  40013800     DC.W       0x40013800
+  0x08002374:  0800780E     DC.W       0x0800780E
+  0x08002378:  0800640B     DC.W       0800640B               ; R_ARM_ABS32
+  0x0800237C:  080063F9     DC.W       080063F9               ; R_ARM_ABS32
+  0x08002380:  080061FD     DC.W       080061FD               ; R_ARM_ABS32
+  0x08002384:  20000234     DC.W       sys_data
+  0x08002388:  08006890     DC.W       08006890               ; R_ARM_ABS32
+  0x0800238C:  20000000     DC.W       modbusData
+  0x08002390:  400C0000     DC.W       0x400C0000
+  0x08002394:  000F4240     DC.W       0x000F4240
+  0x08002398:  FEFFFFFF     DC.W       0xFEFFFFFF
+  0x0800239C:  08006439     DC.W       08006439               ; R_ARM_ABS32
+
.L82:
+  0x080023A0:  2026         MOVS       R0, #38
+  0x080023A2:  9617         STR        R6, [SP, #92]
+  0x080023A4:  2100         MOVS       R1, #0
+  0x080023A6:  9022         STR        R0, [SP, #136]
+  0x080023A8:  5421         STRB       R1, [R4, R0]
+  0x080023AA:  61E1         STR        R1, [R4, #28]
+  0x080023AC:  84A1         STRH       R1, [R4, #36]
+  0x080023AE:  8421         STRH       R1, [R4, #32]
+  0x080023B0:  9123         STR        R1, [SP, #140]
+  0x080023B2:  4620         MOV        R0, R4
+  0x080023B4:  301C         ADDS       R0, #28
+  0x080023B6:  7181         STRB       R1, [R0, #6]
+  0x080023B8:  4EFD         LDR        R6, =0x50000410          ; [PC, #0x03F4] [0x080027B0] 
+  0x080023BA:  9820         LDR        R0, [SP, #128]
+  0x080023BC:  60B0         STR        R0, [R6, #8]
+  0x080023BE:  03EF         LSLS       R7, R5, #15
+  0x080023C0:  48FC         LDR        R0, =0x50000818          ; [PC, #0x03F0] [0x080027B4] 
+  0x080023C2:  6007         STR        R7, [R0]
+  0x080023C4:  03AC         LSLS       R4, R5, #14
+  0x080023C6:  6004         STR        R4, [R0]
+  0x080023C8:  9810         LDR        R0, [SP, #64]
+  0x080023CA:  30F4         ADDS       R0, #244
+  0x080023CC:  9009         STR        R0, [SP, #36]
+  0x080023CE:  F7FE F971    BL         HAL_Delay                ; 0x080006B4
+  0x080023D2:  9820         LDR        R0, [SP, #128]
+  0x080023D4:  61B0         STR        R0, [R6, #24]
+  0x080023D6:  971E         STR        R7, [SP, #120]
+  0x080023D8:  48F6         LDR        R0, =0x50000818          ; [PC, #0x03D8] [0x080027B4] 
+  0x080023DA:  6107         STR        R7, [R0, #16]
+  0x080023DC:  4FF6         LDR        R7, =0x000003C7          ; [PC, #0x03D8] [0x080027B8] 
+  0x080023DE:  941F         STR        R4, [SP, #124]
+  0x080023E0:  6104         STR        R4, [R0, #16]
+  0x080023E2:  48F6         LDR        R0, =0x50000010          ; [PC, #0x03D8] [0x080027BC] 
+  0x080023E4:  9910         LDR        R1, [SP, #64]
+  0x080023E6:  6081         STR        R1, [R0, #8]
+  0x080023E8:  981B         LDR        R0, [SP, #108]
+  0x080023EA:  61B0         STR        R0, [R6, #24]
+  0x080023EC:  2410         MOVS       R4, #16
+  0x080023EE:  60B4         STR        R4, [R6, #8]
+  0x080023F0:  2032         MOVS       R0, #50
+  0x080023F2:  9016         STR        R0, [SP, #88]
+  0x080023F4:  F7FE F95E    BL         HAL_Delay                ; 0x080006B4
+  0x080023F8:  941A         STR        R4, [SP, #104]
+  0x080023FA:  61B4         STR        R4, [R6, #24]
+  0x080023FC:  6830         LDR        R0, [R6]
+  0x080023FE:  6831         LDR        R1, [R6]
+  0x08002400:  6832         LDR        R2, [R6]
+  0x08002402:  0992         LSRS       R2, R2, #6
+  0x08002404:  9B0F         LDR        R3, [SP, #60]
+  0x08002406:  401A         ANDS       R2, R3
+  0x08002408:  0989         LSRS       R1, R1, #6
+  0x0800240A:  9B12         LDR        R3, [SP, #72]
+  0x0800240C:  4019         ANDS       R1, R3
+  0x0800240E:  0640         LSLS       R0, R0, #25
+  0x08002410:  0FC0         LSRS       R0, R0, #31
+  0x08002412:  1808         ADDS       R0, R1, R0
+  0x08002414:  1880         ADDS       R0, R0, R2
+  0x08002416:  6831         LDR        R1, [R6]
+  0x08002418:  0989         LSRS       R1, R1, #6
+  0x0800241A:  9A1B         LDR        R2, [SP, #108]
+  0x0800241C:  4011         ANDS       R1, R2
+  0x0800241E:  1841         ADDS       R1, R0, R1
+  0x08002420:  200F         MOVS       R0, #15
+  0x08002422:  9003         STR        R0, [SP, #12]
+  0x08002424:  4041         EORS       R1, R0
+  0x08002426:  4CE6         LDR        R4, =mode                ; [PC, #0x0398] [0x080027C0] =0x20000739 
+  0x08002428:  7021         STRB       R1, [R4]
+  0x0800242A:  48E6         LDR        R0, =0x080067CE          ; [PC, #0x0398] [0x080027C4] 
+  0x0800242C:  F002 FF3A    BL         printf                   ; 0x080052A4
+  0x08002430:  7820         LDRB       R0, [R4]
+  0x08002432:  49E5         LDR        R1, =sys_data            ; [PC, #0x0394] [0x080027C8] =0x20000234 
+  0x08002434:  8508         STRH       R0, [R1, #40]
+  0x08002436:  48E5         LDR        R0, =0x1FFF7568          ; [PC, #0x0394] [0x080027CC] 
+  0x08002438:  8800         LDRH       R0, [R0]
+  0x0800243A:  F003 FBA0    BL         __aeabi_ui2f             ; 0x08005B7E
+  0x0800243E:  2173         MOVS       R1, #115
+  0x08002440:  05C9         LSLS       R1, R1, #23
+  0x08002442:  F003 FA65    BL         __aeabi_fmul             ; 0x08005910
+  0x08002446:  49E2         LDR        R1, =0x453B8000          ; [PC, #0x0388] [0x080027D0] 
+  0x08002448:  F003 FA62    BL         __aeabi_fmul             ; 0x08005910
+  0x0800244C:  F003 FDD9    BL         __aeabi_f2uiz            ; 0x08006002
+  0x08002450:  49E0         LDR        R1, =calTemperatureSensor30Value ; [PC, #0x0380] [0x080027D4] =0x200006E8 
+  0x08002452:  6008         STR        R0, [R1]
+  0x08002454:  9823         LDR        R0, [SP, #140]
+  0x08002456:  9029         STR        R0, [SP, #164]
+  0x08002458:  4EDF         LDR        R6, =hadc1               ; [PC, #0x037C] [0x080027D8] =0x20000450 
+  0x0800245A:  2354         MOVS       R3, #84
+  0x0800245C:  5CF0         LDRB       R0, [R6, R3]
+  0x0800245E:  2801         CMP        R0, #1
+  0x08002460:  6834         LDR        R4, [R6]
+  0x08002462:  4628         MOV        R0, R5
+  0x08002464:  9321         STR        R3, [SP, #132]
+  0x08002466:  D069         BEQ        .L93                     ; 0x0800253C
+  0x08002468:  2001         MOVS       R0, #1
+  0x0800246A:  9002         STR        R0, [SP, #8]
+  0x0800246C:  54F0         STRB       R0, [R6, R3]
+  0x0800246E:  68A1         LDR        R1, [R4, #8]
+  0x08002470:  68A2         LDR        R2, [R4, #8]
+  0x08002472:  07D2         LSLS       R2, R2, #31
+  0x08002474:  D020         BEQ        .L85                     ; 0x080024B8
+  0x08002476:  9812         LDR        R0, [SP, #72]
+  0x08002478:  4001         ANDS       R1, R0
+  0x0800247A:  D11D         BNE        .L85                     ; 0x080024B8
+  0x0800247C:  68A1         LDR        R1, [R4, #8]
+  0x0800247E:  2205         MOVS       R2, #5
+  0x08002480:  400A         ANDS       R2, R1
+  0x08002482:  2A01         CMP        R2, #1
+  0x08002484:  D110         BNE        .L84                     ; 0x080024A8
+  0x08002486:  68A1         LDR        R1, [R4, #8]
+  0x08002488:  48D4         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0350] [0x080027DC] 
+  0x0800248A:  4001         ANDS       R1, R0
+  0x0800248C:  9812         LDR        R0, [SP, #72]
+  0x0800248E:  4301         ORRS       R1, R0
+  0x08002490:  60A1         STR        R1, [R4, #8]
+  0x08002492:  9815         LDR        R0, [SP, #84]
+  0x08002494:  6020         STR        R0, [R4]
+  0x08002496:  48D2         LDR        R0, =uwTick              ; [PC, #0x0348] [0x080027E0] =0x2000068C 
+  0x08002498:  6801         LDR        R1, [R0]
+
.L83:
+  0x0800249A:  68A2         LDR        R2, [R4, #8]
+  0x0800249C:  07D2         LSLS       R2, R2, #31
+  0x0800249E:  D00B         BEQ        .L85                     ; 0x080024B8
+  0x080024A0:  6802         LDR        R2, [R0]
+  0x080024A2:  1A52         SUBS       R2, R2, R1
+  0x080024A4:  2A03         CMP        R2, #3
+  0x080024A6:  D3F8         BCC        .L83                     ; 0x0800249A
+
.L84:
+  0x080024A8:  6DB1         LDR        R1, [R6, #88]
+  0x080024AA:  981A         LDR        R0, [SP, #104]
+  0x080024AC:  4301         ORRS       R1, R0
+  0x080024AE:  65B1         STR        R1, [R6, #88]
+  0x080024B0:  6DF1         LDR        R1, [R6, #92]
+  0x080024B2:  9802         LDR        R0, [SP, #8]
+  0x080024B4:  4301         ORRS       R1, R0
+  0x080024B6:  65F1         STR        R1, [R6, #92]
+
.L85:
+  0x080024B8:  68A1         LDR        R1, [R4, #8]
+  0x080024BA:  07C9         LSLS       R1, R1, #31
+  0x080024BC:  6DB1         LDR        R1, [R6, #88]
+  0x080024BE:  D12D         BNE        .L90                     ; 0x0800251C
+  0x080024C0:  48C8         LDR        R0, =0xFFFFFEFD          ; [PC, #0x0320] [0x080027E4] 
+  0x080024C2:  4001         ANDS       R1, R0
+  0x080024C4:  9812         LDR        R0, [SP, #72]
+  0x080024C6:  4301         ORRS       R1, R0
+  0x080024C8:  65B1         STR        R1, [R6, #88]
+  0x080024CA:  68E1         LDR        R1, [R4, #12]
+  0x080024CC:  68E2         LDR        R2, [R4, #12]
+  0x080024CE:  4BC6         LDR        R3, =0xFFFF7FFC          ; [PC, #0x0318] [0x080027E8] 
+  0x080024D0:  4013         ANDS       R3, R2
+  0x080024D2:  60E3         STR        R3, [R4, #12]
+  0x080024D4:  981E         LDR        R0, [SP, #120]
+  0x080024D6:  1CC0         ADDS       R0, R0, #3
+  0x080024D8:  4008         ANDS       R0, R1
+  0x080024DA:  9001         STR        R0, [SP, #4]
+  0x080024DC:  4622         MOV        R2, R4
+  0x080024DE:  32B4         ADDS       R2, #180
+  0x080024E0:  2300         MOVS       R3, #0
+  0x080024E2:  461F         MOV        R7, R3
+
.L86:
+  0x080024E4:  2F08         CMP        R7, #8
+  0x080024E6:  68A1         LDR        R1, [R4, #8]
+  0x080024E8:  48BC         LDR        R0, =0x7FFFFFE8          ; [PC, #0x02F0] [0x080027DC] 
+  0x080024EA:  D101         BNE        .L87                     ; 0x080024F0
+  0x080024EC:  F001 FFA7    BL         .L282                    ; 0x0800443E
+
.L87:
+  0x080024F0:  4001         ANDS       R1, R0
+  0x080024F2:  1841         ADDS       R1, R0, R1
+  0x080024F4:  3118         ADDS       R1, #24
+  0x080024F6:  60A1         STR        R1, [R4, #8]
+
.L88:
+  0x080024F8:  68A1         LDR        R1, [R4, #8]
+  0x080024FA:  2900         CMP        R1, #0
+  0x080024FC:  D507         BPL        .L89                     ; 0x0800250E
+  0x080024FE:  9929         LDR        R1, [SP, #164]
+  0x08002500:  1C49         ADDS       R1, R1, #1
+  0x08002502:  9129         STR        R1, [SP, #164]
+  0x08002504:  9929         LDR        R1, [SP, #164]
+  0x08002506:  0AC9         LSRS       R1, R1, #11
+  0x08002508:  2957         CMP        R1, #87
+  0x0800250A:  D3F5         BCC        .L88                     ; 0x080024F8
+  0x0800250C:  E00C         B          .L92                     ; 0x08002528
+
.L89:
+  0x0800250E:  6811         LDR        R1, [R2]
+  0x08002510:  207F         MOVS       R0, #127
+  0x08002512:  4008         ANDS       R0, R1
+  0x08002514:  1818         ADDS       R0, R3, R0
+  0x08002516:  1C43         ADDS       R3, R0, #1
+  0x08002518:  1C7F         ADDS       R7, R7, #1
+  0x0800251A:  E7E3         B          .L86                     ; 0x080024E4
+
.L90:
+  0x0800251C:  981A         LDR        R0, [SP, #104]
+  0x0800251E:  4301         ORRS       R1, R0
+
.L91:
+  0x08002520:  9823         LDR        R0, [SP, #140]
+  0x08002522:  54F0         STRB       R0, [R6, R3]
+  0x08002524:  65B1         STR        R1, [R6, #88]
+  0x08002526:  E009         B          .L93                     ; 0x0800253C
+
.L92:
+  0x08002528:  2000         MOVS       R0, #0
+  0x0800252A:  9B21         LDR        R3, [SP, #132]
+  0x0800252C:  54F0         STRB       R0, [R6, R3]
+  0x0800252E:  6DB1         LDR        R1, [R6, #88]
+  0x08002530:  9A1A         LDR        R2, [SP, #104]
+  0x08002532:  4311         ORRS       R1, R2
+  0x08002534:  9A12         LDR        R2, [SP, #72]
+  0x08002536:  4391         BICS       R1, R2
+  0x08002538:  65B1         STR        R1, [R6, #88]
+  0x0800253A:  4F9F         LDR        R7, =0x000003C7          ; [PC, #0x027C] [0x080027B8] 
+
.L93:
+  0x0800253C:  68A1         LDR        R1, [R4, #8]
+  0x0800253E:  0749         LSLS       R1, R1, #29
+  0x08002540:  D459         BMI        .L100                    ; 0x080025F6
+  0x08002542:  2800         CMP        R0, #0
+  0x08002544:  D157         BNE        .L100                    ; 0x080025F6
+  0x08002546:  2201         MOVS       R2, #1
+  0x08002548:  54F2         STRB       R2, [R6, R3]
+  0x0800254A:  68E0         LDR        R0, [R4, #12]
+  0x0800254C:  07C0         LSLS       R0, R0, #31
+  0x0800254E:  D10B         BNE        .L95                     ; 0x08002568
+  0x08002550:  68A0         LDR        R0, [R4, #8]
+  0x08002552:  07C0         LSLS       R0, R0, #31
+  0x08002554:  D005         BEQ        .L94                     ; 0x08002562
+  0x08002556:  68A0         LDR        R0, [R4, #8]
+  0x08002558:  49A0         LDR        R1, =0x7FFFFFE8          ; [PC, #0x0280] [0x080027DC] 
+  0x0800255A:  4008         ANDS       R0, R1
+  0x0800255C:  9912         LDR        R1, [SP, #72]
+  0x0800255E:  4308         ORRS       R0, R1
+  0x08002560:  60A0         STR        R0, [R4, #8]
+
.L94:
+  0x08002562:  68E0         LDR        R0, [R4, #12]
+  0x08002564:  4310         ORRS       R0, R2
+  0x08002566:  60E0         STR        R0, [R4, #12]
+
.L95:
+  0x08002568:  2000         MOVS       R0, #0
+  0x0800256A:  9023         STR        R0, [SP, #140]
+  0x0800256C:  9029         STR        R0, [SP, #164]
+  0x0800256E:  68A0         LDR        R0, [R4, #8]
+  0x08002570:  07C0         LSLS       R0, R0, #31
+  0x08002572:  D11D         BNE        .L99                     ; 0x080025B0
+  0x08002574:  4899         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0264] [0x080027DC] 
+  0x08002576:  302F         ADDS       R0, #47
+  0x08002578:  68A1         LDR        R1, [R4, #8]
+  0x0800257A:  4201         TST        R1, R0
+  0x0800257C:  D007         BEQ        .L97                     ; 0x0800258E
+
.L96:
+  0x0800257E:  6DB0         LDR        R0, [R6, #88]
+  0x08002580:  991A         LDR        R1, [SP, #104]
+  0x08002582:  4308         ORRS       R0, R1
+  0x08002584:  65B0         STR        R0, [R6, #88]
+  0x08002586:  6DF0         LDR        R0, [R6, #92]
+  0x08002588:  4310         ORRS       R0, R2
+  0x0800258A:  65F0         STR        R0, [R6, #92]
+  0x0800258C:  E033         B          .L100                    ; 0x080025F6
+
.L97:
+  0x0800258E:  68A0         LDR        R0, [R4, #8]
+  0x08002590:  4992         LDR        R1, =0x7FFFFFE8          ; [PC, #0x0248] [0x080027DC] 
+  0x08002592:  4008         ANDS       R0, R1
+  0x08002594:  4310         ORRS       R0, R2
+  0x08002596:  60A0         STR        R0, [R4, #8]
+  0x08002598:  4894         LDR        R0, =0x40012708          ; [PC, #0x0250] [0x080027EC] 
+  0x0800259A:  6800         LDR        R0, [R0]
+  0x0800259C:  0200         LSLS       R0, R0, #8
+  0x0800259E:  9203         STR        R2, [SP, #12]
+  0x080025A0:  D501         BPL        .L98                     ; 0x080025A6
+  0x080025A2:  F001 FF24    BL         .L275                    ; 0x080043EE
+
.L98:
+  0x080025A6:  7E70         LDRB       R0, [R6, #25]
+  0x080025A8:  2801         CMP        R0, #1
+  0x080025AA:  D001         BEQ        .L99                     ; 0x080025B0
+  0x080025AC:  F001 FF30    BL         .L278                    ; 0x08004410
+
.L99:
+  0x080025B0:  9A23         LDR        R2, [SP, #140]
+  0x080025B2:  54F2         STRB       R2, [R6, R3]
+  0x080025B4:  6DB0         LDR        R0, [R6, #88]
+  0x080025B6:  498E         LDR        R1, =0xFFFFF0FE          ; [PC, #0x0238] [0x080027F0] 
+  0x080025B8:  4008         ANDS       R0, R1
+  0x080025BA:  9910         LDR        R1, [SP, #64]
+  0x080025BC:  4308         ORRS       R0, R1
+  0x080025BE:  65B0         STR        R0, [R6, #88]
+  0x080025C0:  65F2         STR        R2, [R6, #92]
+  0x080025C2:  9804         LDR        R0, [SP, #16]
+  0x080025C4:  6020         STR        R0, [R4]
+  0x080025C6:  6D30         LDR        R0, [R6, #80]
+  0x080025C8:  498A         LDR        R1, =ADC_DMAError        ; [PC, #0x0228] [0x080027F4] =0x08005DF3 
+  0x080025CA:  4A8B         LDR        R2, =ADC_DMAHalfConvCplt ; [PC, #0x022C] [0x080027F8] =0x0800580D 
+  0x080025CC:  4B8B         LDR        R3, =ADC_DMAConvCplt     ; [PC, #0x022C] [0x080027FC] =0x08005D8F 
+  0x080025CE:  62C3         STR        R3, [R0, #44]
+  0x080025D0:  6302         STR        R2, [R0, #48]
+  0x080025D2:  6341         STR        R1, [R0, #52]
+  0x080025D4:  6861         LDR        R1, [R4, #4]
+  0x080025D6:  9A1A         LDR        R2, [SP, #104]
+  0x080025D8:  4311         ORRS       R1, R2
+  0x080025DA:  6061         STR        R1, [R4, #4]
+  0x080025DC:  3440         ADDS       R4, #64
+  0x080025DE:  4A88         LDR        R2, =adcData             ; [PC, #0x0220] [0x08002800] =0x20000660 
+  0x080025E0:  2305         MOVS       R3, #5
+  0x080025E2:  4621         MOV        R1, R4
+  0x080025E4:  F7FE FA1E    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080025E8:  6830         LDR        R0, [R6]
+  0x080025EA:  6881         LDR        R1, [R0, #8]
+  0x080025EC:  4A7B         LDR        R2, =0x7FFFFFE8          ; [PC, #0x01EC] [0x080027DC] 
+  0x080025EE:  4011         ANDS       R1, R2
+  0x080025F0:  9A0F         LDR        R2, [SP, #60]
+  0x080025F2:  4311         ORRS       R1, R2
+  0x080025F4:  6081         STR        R1, [R0, #8]
+
.L100:
+  0x080025F6:  4B83         LDR        R3, =htim16              ; [PC, #0x020C] [0x08002804] =0x20000614 
+  0x080025F8:  6818         LDR        R0, [R3]
+  0x080025FA:  2200         MOVS       R2, #0
+  0x080025FC:  6242         STR        R2, [R0, #36]
+  0x080025FE:  4982         LDR        R1, =ic_overflows        ; [PC, #0x0208] [0x08002808] =0x200006DC 
+  0x08002600:  9223         STR        R2, [SP, #140]
+  0x08002602:  600A         STR        R2, [R1]
+  0x08002604:  9C0C         LDR        R4, [SP, #48]
+  0x08002606:  5D19         LDRB       R1, [R3, R4]
+  0x08002608:  2901         CMP        R1, #1
+  0x0800260A:  D117         BNE        .L103                    ; 0x0800263C
+  0x0800260C:  2102         MOVS       R1, #2
+  0x0800260E:  5519         STRB       R1, [R3, R4]
+  0x08002610:  68C2         LDR        R2, [R0, #12]
+  0x08002612:  2101         MOVS       R1, #1
+  0x08002614:  430A         ORRS       R2, R1
+  0x08002616:  60C2         STR        R2, [R0, #12]
+  0x08002618:  4A7C         LDR        R2, =0x40012C00          ; [PC, #0x01F0] [0x0800280C] 
+  0x0800261A:  4290         CMP        R0, R2
+  0x0800261C:  D002         BEQ        .L101                    ; 0x08002624
+  0x0800261E:  4A7C         LDR        R2, =0x40000400          ; [PC, #0x01F0] [0x08002810] 
+  0x08002620:  4290         CMP        R0, R2
+  0x08002622:  D108         BNE        .L102                    ; 0x08002636
+
.L101:
+  0x08002624:  4B7B         LDR        R3, =0x0000FFFF          ; [PC, #0x01EC] [0x08002814] 
+  0x08002626:  3308         ADDS       R3, #8
+  0x08002628:  6882         LDR        R2, [R0, #8]
+  0x0800262A:  401A         ANDS       R2, R3
+  0x0800262C:  2A06         CMP        R2, #6
+  0x0800262E:  D005         BEQ        .L103                    ; 0x0800263C
+  0x08002630:  040B         LSLS       R3, R1, #16
+  0x08002632:  429A         CMP        R2, R3
+  0x08002634:  D002         BEQ        .L103                    ; 0x0800263C
+
.L102:
+  0x08002636:  6802         LDR        R2, [R0]
+  0x08002638:  430A         ORRS       R2, R1
+  0x0800263A:  6002         STR        R2, [R0]
+
.L103:
+  0x0800263C:  4A71         LDR        R2, =htim16              ; [PC, #0x01C4] [0x08002804] =0x20000614 
+  0x0800263E:  9B1C         LDR        R3, [SP, #112]
+  0x08002640:  5CD1         LDRB       R1, [R2, R3]
+  0x08002642:  2901         CMP        R1, #1
+  0x08002644:  9911         LDR        R1, [SP, #68]
+  0x08002646:  5C51         LDRB       R1, [R2, R1]
+  0x08002648:  4C73         LDR        R4, =modbusData          ; [PC, #0x01CC] [0x08002818] =0x20000000 
+  0x0800264A:  D121         BNE        .L106                    ; 0x08002690
+  0x0800264C:  2901         CMP        R1, #1
+  0x0800264E:  D11F         BNE        .L106                    ; 0x08002690
+  0x08002650:  2102         MOVS       R1, #2
+  0x08002652:  54D1         STRB       R1, [R2, R3]
+  0x08002654:  9B11         LDR        R3, [SP, #68]
+  0x08002656:  54D1         STRB       R1, [R2, R3]
+  0x08002658:  68C2         LDR        R2, [R0, #12]
+  0x0800265A:  430A         ORRS       R2, R1
+  0x0800265C:  60C2         STR        R2, [R0, #12]
+  0x0800265E:  6A02         LDR        R2, [R0, #32]
+  0x08002660:  2101         MOVS       R1, #1
+  0x08002662:  438A         BICS       R2, R1
+  0x08002664:  6202         STR        R2, [R0, #32]
+  0x08002666:  6A02         LDR        R2, [R0, #32]
+  0x08002668:  430A         ORRS       R2, R1
+  0x0800266A:  6202         STR        R2, [R0, #32]
+  0x0800266C:  4A67         LDR        R2, =0x40012C00          ; [PC, #0x019C] [0x0800280C] 
+  0x0800266E:  4290         CMP        R0, R2
+  0x08002670:  D002         BEQ        .L104                    ; 0x08002678
+  0x08002672:  4A67         LDR        R2, =0x40000400          ; [PC, #0x019C] [0x08002810] 
+  0x08002674:  4290         CMP        R0, R2
+  0x08002676:  D108         BNE        .L105                    ; 0x0800268A
+
.L104:
+  0x08002678:  4B66         LDR        R3, =0x0000FFFF          ; [PC, #0x0198] [0x08002814] 
+  0x0800267A:  3308         ADDS       R3, #8
+  0x0800267C:  6882         LDR        R2, [R0, #8]
+  0x0800267E:  401A         ANDS       R2, R3
+  0x08002680:  2A06         CMP        R2, #6
+  0x08002682:  D005         BEQ        .L106                    ; 0x08002690
+  0x08002684:  040B         LSLS       R3, R1, #16
+  0x08002686:  429A         CMP        R2, R3
+  0x08002688:  D002         BEQ        .L106                    ; 0x08002690
+
.L105:
+  0x0800268A:  6802         LDR        R2, [R0]
+  0x0800268C:  430A         ORRS       R2, R1
+  0x0800268E:  6002         STR        R2, [R0]
+
.L106:
+  0x08002690:  9518         STR        R5, [SP, #96]
+
.L107:
+  0x08002692:  4862         LDR        R0, =0x40003000          ; [PC, #0x0188] [0x0800281C] 
+  0x08002694:  4962         LDR        R1, =0x0000AAAA          ; [PC, #0x0188] [0x08002820] 
+  0x08002696:  6001         STR        R1, [R0]
+  0x08002698:  7D20         LDRB       R0, [R4, #20]
+  0x0800269A:  2801         CMP        R0, #1
+  0x0800269C:  D10E         BNE        .L110                    ; 0x080026BC
+  0x0800269E:  9819         LDR        R0, [SP, #100]
+  0x080026A0:  00C0         LSLS       R0, R0, #3
+  0x080026A2:  9021         STR        R0, [SP, #132]
+  0x080026A4:  5827         LDR        R7, [R4, R0]
+  0x080026A6:  2F05         CMP        R7, #5
+  0x080026A8:  D223         BCS        .L113                    ; 0x080026F2
+
.L108:
+  0x080026AA:  2000         MOVS       R0, #0
+  0x080026AC:  9921         LDR        R1, [SP, #132]
+  0x080026AE:  5060         STR        R0, [R4, R1]
+  0x080026B0:  7520         STRB       R0, [R4, #20]
+  0x080026B2:  208C         MOVS       R0, #140
+  0x080026B4:  2122         MOVS       R1, #34
+  0x080026B6:  4A5B         LDR        R2, =huart1              ; [PC, #0x016C] [0x08002824] =0x200003BC 
+  0x080026B8:  5011         STR        R1, [R2, R0]
+
.L109:
+  0x080026BA:  4F3F         LDR        R7, =0x000003C7          ; [PC, #252] [0x080027B8] 
+
.L110:
+  0x080026BC:  4848         LDR        R0, =uwTick              ; [PC, #0x0120] [0x080027E0] =0x2000068C 
+  0x080026BE:  6800         LDR        R0, [R0]
+  0x080026C0:  4959         LDR        R1, =oldTimeMSTick       ; [PC, #0x0164] [0x08002828] =0x200006AC 
+  0x080026C2:  6809         LDR        R1, [R1]
+  0x080026C4:  4281         CMP        R1, R0
+  0x080026C6:  D102         BNE        .L111                    ; 0x080026CE
+  0x080026C8:  4858         LDR        R0, =msCounter           ; [PC, #0x0160] [0x0800282C] =0x200006C0 
+  0x080026CA:  6800         LDR        R0, [R0]
+  0x080026CC:  E1B5         B          .L151                    ; 0x08002A3A
+
.L111:
+  0x080026CE:  4838         LDR        R0, =0x50000410          ; [PC, #224] [0x080027B0] 
+  0x080026D0:  6800         LDR        R0, [R0]
+  0x080026D2:  07C0         LSLS       R0, R0, #31
+  0x080026D4:  4C56         LDR        R4, =longPressCounterButtonOn ; [PC, #0x0158] [0x08002830] =0x200006C4 
+  0x080026D6:  6820         LDR        R0, [R4]
+  0x080026D8:  D001         BEQ        .L112                    ; 0x080026DE
+  0x080026DA:  1C40         ADDS       R0, R0, #1
+  0x080026DC:  6020         STR        R0, [R4]
+
.L112:
+  0x080026DE:  4955         LDR        R1, =0x00001388          ; [PC, #0x0154] [0x08002834] 
+  0x080026E0:  4288         CMP        R0, R1
+  0x080026E2:  D947         BLS        .L120                    ; 0x08002774
+  0x080026E4:  4854         LDR        R0, =buttonState         ; [PC, #0x0150] [0x08002838] =0x2000073A 
+  0x080026E6:  7800         LDRB       R0, [R0]
+  0x080026E8:  2802         CMP        R0, #2
+  0x080026EA:  D053         BEQ        .L122                    ; 0x08002794
+  0x080026EC:  4853         LDR        R0, =0x08006874          ; [PC, #0x014C] [0x0800283C] 
+  0x080026EE:  9E12         LDR        R6, [SP, #72]
+  0x080026F0:  E04C         B          .L121                    ; 0x0800278C
+
.L113:
+  0x080026F2:  2027         MOVS       R0, #39
+  0x080026F4:  5C20         LDRB       R0, [R4, R0]
+  0x080026F6:  901C         STR        R0, [SP, #112]
+  0x080026F8:  1EBE         SUBS       R6, R7, #2
+  0x080026FA:  9817         LDR        R0, [SP, #92]
+  0x080026FC:  4631         MOV        R1, R6
+  0x080026FE:  F001 FFA9    BL         mbCrc16                  ; 0x08004654
+  0x08002702:  1C79         ADDS       R1, R7, #1
+  0x08002704:  D0D1         BEQ        .L108                    ; 0x080026AA
+  0x08002706:  9917         LDR        R1, [SP, #92]
+  0x08002708:  5D89         LDRB       R1, [R1, R6]
+  0x0800270A:  19E2         ADDS       R2, R4, R7
+  0x0800270C:  9B22         LDR        R3, [SP, #136]
+  0x0800270E:  5CD2         LDRB       R2, [R2, R3]
+  0x08002710:  0212         LSLS       R2, R2, #8
+  0x08002712:  1851         ADDS       R1, R2, R1
+  0x08002714:  4281         CMP        R1, R0
+  0x08002716:  D1C8         BNE        .L108                    ; 0x080026AA
+  0x08002718:  981C         LDR        R0, [SP, #112]
+  0x0800271A:  2800         CMP        R0, #0
+  0x0800271C:  D004         BEQ        .L114                    ; 0x08002728
+  0x0800271E:  482A         LDR        R0, =sys_data            ; [PC, #168] [0x080027C8] =0x20000234 
+  0x08002720:  8B00         LDRH       R0, [R0, #24]
+  0x08002722:  991C         LDR        R1, [SP, #112]
+  0x08002724:  4288         CMP        R0, R1
+  0x08002726:  D1C0         BNE        .L108                    ; 0x080026AA
+
.L114:
+  0x08002728:  9F13         LDR        R7, [SP, #76]
+  0x0800272A:  3728         ADDS       R7, #40
+  0x0800272C:  9B1C         LDR        R3, [SP, #112]
+  0x0800272E:  55E3         STRB       R3, [R4, R7]
+  0x08002730:  218B         MOVS       R1, #139
+  0x08002732:  0088         LSLS       R0, R1, #2
+  0x08002734:  9011         STR        R0, [SP, #68]
+  0x08002736:  2100         MOVS       R1, #0
+  0x08002738:  5021         STR        R1, [R4, R0]
+  0x0800273A:  2228         MOVS       R2, #40
+  0x0800273C:  5CA2         LDRB       R2, [R4, R2]
+  0x0800273E:  2A10         CMP        R2, #16
+  0x08002740:  970C         STR        R7, [SP, #48]
+  0x08002742:  D101         BNE        .L115                    ; 0x08002748
+  0x08002744:  F001 FA29    BL         .L217                    ; 0x08003B9A
+
.L115:
+  0x08002748:  2A06         CMP        R2, #6
+  0x0800274A:  D101         BNE        .L116                    ; 0x08002750
+  0x0800274C:  F001 FA12    BL         .L214                    ; 0x08003B74
+
.L116:
+  0x08002750:  2A03         CMP        R2, #3
+  0x08002752:  D001         BEQ        .L117                    ; 0x08002758
+  0x08002754:  F001 FA2B    BL         .L219                    ; 0x08003BAE
+
.L117:
+  0x08002758:  4A1B         LDR        R2, =sys_data            ; [PC, #108] [0x080027C8] =0x20000234 
+  0x0800275A:  8B12         LDRH       R2, [R2, #24]
+  0x0800275C:  2B00         CMP        R3, #0
+  0x0800275E:  D101         BNE        .L118                    ; 0x08002764
+  0x08002760:  F001 FA41    BL         .L223                    ; 0x08003BE6
+
.L118:
+  0x08002764:  429A         CMP        R2, R3
+  0x08002766:  D101         BNE        .L119                    ; 0x0800276C
+  0x08002768:  F001 FA3D    BL         .L223                    ; 0x08003BE6
+
.L119:
+  0x0800276C:  2386         MOVS       R3, #134
+  0x0800276E:  9A06         LDR        R2, [SP, #24]
+  0x08002770:  F001 FA46    BL         .L225                    ; 0x08003C00
+
.L120:
+  0x08002774:  280B         CMP        R0, #11
+  0x08002776:  D30D         BCC        .L122                    ; 0x08002794
+  0x08002778:  482F         LDR        R0, =buttonState         ; [PC, #188] [0x08002838] =0x2000073A 
+  0x0800277A:  7800         LDRB       R0, [R0]
+  0x0800277C:  490C         LDR        R1, =0x50000410          ; [PC, #48] [0x080027B0] 
+  0x0800277E:  6809         LDR        R1, [R1]
+  0x08002780:  07C9         LSLS       R1, R1, #31
+  0x08002782:  D107         BNE        .L122                    ; 0x08002794
+  0x08002784:  2801         CMP        R0, #1
+  0x08002786:  D005         BEQ        .L122                    ; 0x08002794
+  0x08002788:  2601         MOVS       R6, #1
+  0x0800278A:  48F3         LDR        R0, =0x080063E7          ; [PC, #0x03CC] [0x08002B58] 
+
.L121:
+  0x0800278C:  F002 FD30    BL         puts                     ; 0x080051F0
+  0x08002790:  4829         LDR        R0, =buttonState         ; [PC, #164] [0x08002838] =0x2000073A 
+  0x08002792:  7006         STRB       R6, [R0]
+
.L122:
+  0x08002794:  4806         LDR        R0, =0x50000410          ; [PC, #24] [0x080027B0] 
+  0x08002796:  6800         LDR        R0, [R0]
+  0x08002798:  07C0         LSLS       R0, R0, #31
+  0x0800279A:  D100         BNE        .L123                    ; 0x0800279E
+  0x0800279C:  6020         STR        R0, [R4]
+
.L123:
+  0x0800279E:  4804         LDR        R0, =0x50000410          ; [PC, #16] [0x080027B0] 
+  0x080027A0:  6800         LDR        R0, [R0]
+  0x080027A2:  0780         LSLS       R0, R0, #30
+  0x080027A4:  48ED         LDR        R0, =longPressCounterButtonOff ; [PC, #0x03B4] [0x08002B5C] =0x200006C8 
+  0x080027A6:  D44B         BMI        .L124                    ; 0x08002840
+  0x080027A8:  2100         MOVS       R1, #0
+  0x080027AA:  6001         STR        R1, [R0]
+  0x080027AC:  E056         B          .L125                    ; 0x0800285C
+  0x080027AE:  46C0         NOP
+  0x080027B0:  50000410     DC.W       0x50000410
+  0x080027B4:  50000818     DC.W       0x50000818
+  0x080027B8:  000003C7     DC.W       0x000003C7
+  0x080027BC:  50000010     DC.W       0x50000010
+  0x080027C0:  20000739     DC.W       mode
+  0x080027C4:  080067CE     DC.W       080067CE               ; R_ARM_ABS32
+  0x080027C8:  20000234     DC.W       sys_data
+  0x080027CC:  1FFF7568     DC.W       0x1FFF7568
+  0x080027D0:  453B8000     DC.W       0x453B8000
+  0x080027D4:  200006E8     DC.W       calTemperatureSensor30Value
+  0x080027D8:  20000450     DC.W       hadc1
+  0x080027DC:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x080027E0:  2000068C     DC.W       uwTick
+  0x080027E4:  FFFFFEFD     DC.W       0xFFFFFEFD
+  0x080027E8:  FFFF7FFC     DC.W       0xFFFF7FFC
+  0x080027EC:  40012708     DC.W       0x40012708
+  0x080027F0:  FFFFF0FE     DC.W       0xFFFFF0FE
+  0x080027F4:  08005DF3     DC.W       ADC_DMAError
+  0x080027F8:  0800580D     DC.W       ADC_DMAHalfConvCplt
+  0x080027FC:  08005D8F     DC.W       ADC_DMAConvCplt
+  0x08002800:  20000660     DC.W       adcData
+  0x08002804:  20000614     DC.W       htim16
+  0x08002808:  200006DC     DC.W       ic_overflows
+  0x0800280C:  40012C00     DC.W       0x40012C00
+  0x08002810:  40000400     DC.W       0x40000400
+  0x08002814:  0000FFFF     DC.W       0x0000FFFF
+  0x08002818:  20000000     DC.W       modbusData
+  0x0800281C:  40003000     DC.W       0x40003000
+  0x08002820:  0000AAAA     DC.W       0x0000AAAA
+  0x08002824:  200003BC     DC.W       huart1
+  0x08002828:  200006AC     DC.W       oldTimeMSTick
+  0x0800282C:  200006C0     DC.W       msCounter
+  0x08002830:  200006C4     DC.W       longPressCounterButtonOn
+  0x08002834:  00001388     DC.W       0x00001388
+  0x08002838:  2000073A     DC.W       buttonState
+  0x0800283C:  08006874     DC.W       08006874               ; R_ARM_ABS32
+
.L124:
+  0x08002840:  6801         LDR        R1, [R0]
+  0x08002842:  1C49         ADDS       R1, R1, #1
+  0x08002844:  6001         STR        R1, [R0]
+  0x08002846:  290B         CMP        R1, #11
+  0x08002848:  D308         BCC        .L125                    ; 0x0800285C
+  0x0800284A:  4CE4         LDR        R4, =buttonState         ; [PC, #0x0390] [0x08002BDC] =0x2000073A 
+  0x0800284C:  7820         LDRB       R0, [R4]
+  0x0800284E:  2800         CMP        R0, #0
+  0x08002850:  D004         BEQ        .L125                    ; 0x0800285C
+  0x08002852:  48E3         LDR        R0, =0x080065A9          ; [PC, #0x038C] [0x08002BE0] 
+  0x08002854:  F002 FCCC    BL         puts                     ; 0x080051F0
+  0x08002858:  2000         MOVS       R0, #0
+  0x0800285A:  7020         STRB       R0, [R4]
+
.L125:
+  0x0800285C:  48E1         LDR        R0, =onTimeCounter       ; [PC, #0x0384] [0x08002BE4] =0x200006A8 
+  0x0800285E:  6801         LDR        R1, [R0]
+  0x08002860:  2900         CMP        R1, #0
+  0x08002862:  D012         BEQ        .L127                    ; 0x0800288A
+  0x08002864:  1E49         SUBS       R1, R1, #1
+  0x08002866:  6001         STR        R1, [R0]
+  0x08002868:  D10F         BNE        .L127                    ; 0x0800288A
+  0x0800286A:  49DF         LDR        R1, =0x50000410          ; [PC, #0x037C] [0x08002BE8] 
+  0x0800286C:  9A20         LDR        R2, [SP, #128]
+  0x0800286E:  618A         STR        R2, [R1, #24]
+  0x08002870:  49DE         LDR        R1, =alarmMode           ; [PC, #0x0378] [0x08002BEC] =0x2000075C 
+  0x08002872:  7809         LDRB       R1, [R1]
+  0x08002874:  2901         CMP        R1, #1
+  0x08002876:  D108         BNE        .L127                    ; 0x0800288A
+  0x08002878:  49DD         LDR        R1, =offTime             ; [PC, #0x0374] [0x08002BF0] =0x20000750 
+  0x0800287A:  780A         LDRB       R2, [R1]
+  0x0800287C:  2A00         CMP        R2, #0
+  0x0800287E:  49DD         LDR        R1, =0x00001388          ; [PC, #0x0374] [0x08002BF4] 
+  0x08002880:  D100         BNE        .L126                    ; 0x08002884
+  0x08002882:  2100         MOVS       R1, #0
+
.L126:
+  0x08002884:  4AF5         LDR        R2, =offTimeCounter      ; [PC, #0x03D4] [0x08002C5C] =0x200006B8 
+  0x08002886:  6011         STR        R1, [R2]
+  0x08002888:  E001         B          .L128                    ; 0x0800288E
+
.L127:
+  0x0800288A:  49F4         LDR        R1, =offTimeCounter      ; [PC, #0x03D0] [0x08002C5C] =0x200006B8 
+  0x0800288C:  6809         LDR        R1, [R1]
+
.L128:
+  0x0800288E:  2900         CMP        R1, #0
+  0x08002890:  D00C         BEQ        .L130                    ; 0x080028AC
+  0x08002892:  1E49         SUBS       R1, R1, #1
+  0x08002894:  4AF1         LDR        R2, =offTimeCounter      ; [PC, #0x03C4] [0x08002C5C] =0x200006B8 
+  0x08002896:  6011         STR        R1, [R2]
+  0x08002898:  D108         BNE        .L130                    ; 0x080028AC
+  0x0800289A:  49F3         LDR        R1, =0x50000410          ; [PC, #0x03CC] [0x08002C68] 
+  0x0800289C:  9A20         LDR        R2, [SP, #128]
+  0x0800289E:  608A         STR        R2, [R1, #8]
+  0x080028A0:  49F3         LDR        R1, =onTime              ; [PC, #0x03CC] [0x08002C70] =0x20000744 
+  0x080028A2:  7809         LDRB       R1, [R1]
+  0x080028A4:  2900         CMP        R1, #0
+  0x080028A6:  D000         BEQ        .L129                    ; 0x080028AA
+  0x080028A8:  21C8         MOVS       R1, #200
+
.L129:
+  0x080028AA:  6001         STR        R1, [R0]
+
.L130:
+  0x080028AC:  4CF1         LDR        R4, =adcData             ; [PC, #0x03C4] [0x08002C74] =0x20000660 
+  0x080028AE:  6820         LDR        R0, [R4]
+  0x080028B0:  49F1         LDR        R1, =0x00000CE4          ; [PC, #0x03C4] [0x08002C78] 
+  0x080028B2:  4348         MULS       R0, R1, R0
+  0x080028B4:  49F1         LDR        R1, =0x00010063          ; [PC, #0x03C4] [0x08002C7C] 
+  0x080028B6:  F003 FBC4    BL         __aeabi_idiv             ; 0x08006042
+  0x080028BA:  49F1         LDR        R1, =0xFFFFFCFF          ; [PC, #0x03C4] [0x08002C80] 
+  0x080028BC:  1808         ADDS       R0, R1, R0
+  0x080028BE:  30A9         ADDS       R0, #169
+  0x080028C0:  210A         MOVS       R1, #10
+  0x080028C2:  F003 FBBE    BL         __aeabi_idiv             ; 0x08006042
+  0x080028C6:  49EF         LDR        R1, =relais_temperature  ; [PC, #0x03BC] [0x08002C84] =0x20000694 
+  0x080028C8:  6008         STR        R0, [R1]
+  0x080028CA:  48EF         LDR        R0, =onTimeCounterSET    ; [PC, #0x03BC] [0x08002C88] =0x20000698 
+  0x080028CC:  6801         LDR        R1, [R0]
+  0x080028CE:  2900         CMP        R1, #0
+  0x080028D0:  D005         BEQ        .L131                    ; 0x080028DE
+  0x080028D2:  1E49         SUBS       R1, R1, #1
+  0x080028D4:  6001         STR        R1, [R0]
+  0x080028D6:  D102         BNE        .L131                    ; 0x080028DE
+  0x080028D8:  48E3         LDR        R0, =0x50000410          ; [PC, #0x038C] [0x08002C68] 
+  0x080028DA:  991B         LDR        R1, [SP, #108]
+  0x080028DC:  6181         STR        R1, [R0, #24]
+
.L131:
+  0x080028DE:  48EB         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03AC] [0x08002C8C] =0x200006A0 
+  0x080028E0:  6801         LDR        R1, [R0]
+  0x080028E2:  2900         CMP        R1, #0
+  0x080028E4:  D005         BEQ        .L132                    ; 0x080028F2
+  0x080028E6:  1E49         SUBS       R1, R1, #1
+  0x080028E8:  6001         STR        R1, [R0]
+  0x080028EA:  D102         BNE        .L132                    ; 0x080028F2
+  0x080028EC:  48DE         LDR        R0, =0x50000410          ; [PC, #0x0378] [0x08002C68] 
+  0x080028EE:  991A         LDR        R1, [SP, #104]
+  0x080028F0:  6181         STR        R1, [R0, #24]
+
.L132:
+  0x080028F2:  48E7         LDR        R0, =onTimeCounterGN     ; [PC, #0x039C] [0x08002C90] =0x200006A4 
+  0x080028F4:  6801         LDR        R1, [R0]
+  0x080028F6:  2900         CMP        R1, #0
+  0x080028F8:  D012         BEQ        .L134                    ; 0x08002920
+  0x080028FA:  1E49         SUBS       R1, R1, #1
+  0x080028FC:  6001         STR        R1, [R0]
+  0x080028FE:  D10F         BNE        .L134                    ; 0x08002920
+  0x08002900:  49E4         LDR        R1, =0x50000818          ; [PC, #0x0390] [0x08002C94] 
+  0x08002902:  9A1F         LDR        R2, [SP, #124]
+  0x08002904:  610A         STR        R2, [R1, #16]
+  0x08002906:  49E4         LDR        R1, =blinkModeGN         ; [PC, #0x0390] [0x08002C98] =0x20000758 
+  0x08002908:  7809         LDRB       R1, [R1]
+  0x0800290A:  2901         CMP        R1, #1
+  0x0800290C:  D108         BNE        .L134                    ; 0x08002920
+  0x0800290E:  49E3         LDR        R1, =offTimeGN           ; [PC, #0x038C] [0x08002C9C] =0x2000074C 
+  0x08002910:  780A         LDRB       R2, [R1]
+  0x08002912:  2A00         CMP        R2, #0
+  0x08002914:  990B         LDR        R1, [SP, #44]
+  0x08002916:  D100         BNE        .L133                    ; 0x0800291A
+  0x08002918:  2100         MOVS       R1, #0
+
.L133:
+  0x0800291A:  4AE1         LDR        R2, =offTimeCounterGN    ; [PC, #0x0384] [0x08002CA0] =0x200006B4 
+  0x0800291C:  6011         STR        R1, [R2]
+  0x0800291E:  E001         B          .L135                    ; 0x08002924
+
.L134:
+  0x08002920:  49DF         LDR        R1, =offTimeCounterGN    ; [PC, #0x037C] [0x08002CA0] =0x200006B4 
+  0x08002922:  6809         LDR        R1, [R1]
+
.L135:
+  0x08002924:  2900         CMP        R1, #0
+  0x08002926:  D00C         BEQ        .L137                    ; 0x08002942
+  0x08002928:  1E49         SUBS       R1, R1, #1
+  0x0800292A:  4AF4         LDR        R2, =offTimeCounterGN    ; [PC, #0x03D0] [0x08002CFC] =0x200006B4 
+  0x0800292C:  6011         STR        R1, [R2]
+  0x0800292E:  D108         BNE        .L137                    ; 0x08002942
+  0x08002930:  49D8         LDR        R1, =0x50000818          ; [PC, #0x0360] [0x08002C94] 
+  0x08002932:  9A1F         LDR        R2, [SP, #124]
+  0x08002934:  600A         STR        R2, [R1]
+  0x08002936:  49F2         LDR        R1, =onTimeGN            ; [PC, #0x03C8] [0x08002D00] =0x20000740 
+  0x08002938:  7809         LDRB       R1, [R1]
+  0x0800293A:  2900         CMP        R1, #0
+  0x0800293C:  D000         BEQ        .L136                    ; 0x08002940
+  0x0800293E:  21C8         MOVS       R1, #200
+
.L136:
+  0x08002940:  6001         STR        R1, [R0]
+
.L137:
+  0x08002942:  48F0         LDR        R0, =onTimeCounterRT     ; [PC, #0x03C0] [0x08002D04] =0x2000069C 
+  0x08002944:  6801         LDR        R1, [R0]
+  0x08002946:  2900         CMP        R1, #0
+  0x08002948:  D002         BEQ        .L138                    ; 0x08002950
+  0x0800294A:  1E49         SUBS       R1, R1, #1
+  0x0800294C:  6001         STR        R1, [R0]
+  0x0800294E:  D006         BEQ        .L140                    ; 0x0800295E
+
.L138:
+  0x08002950:  49F1         LDR        R1, =blinkCounter        ; [PC, #0x03C4] [0x08002D18] =0x200006EC 
+  0x08002952:  6809         LDR        R1, [R1]
+
.L139:
+  0x08002954:  2900         CMP        R1, #0
+  0x08002956:  D018         BEQ        .L143                    ; 0x0800298A
+  0x08002958:  49F0         LDR        R1, =offTimeCounterRT    ; [PC, #0x03C0] [0x08002D1C] =0x200006B0 
+  0x0800295A:  6809         LDR        R1, [R1]
+  0x0800295C:  E021         B          .L145                    ; 0x080029A2
+
.L140:
+  0x0800295E:  49EC         LDR        R1, =0x50000818          ; [PC, #0x03B0] [0x08002D10] 
+  0x08002960:  9A1E         LDR        R2, [SP, #120]
+  0x08002962:  610A         STR        R2, [R1, #16]
+  0x08002964:  49EE         LDR        R1, =blinkModeRT         ; [PC, #0x03B8] [0x08002D20] =0x20000754 
+  0x08002966:  7809         LDRB       R1, [R1]
+  0x08002968:  2901         CMP        R1, #1
+  0x0800296A:  D107         BNE        .L142                    ; 0x0800297C
+  0x0800296C:  49ED         LDR        R1, =offTimeRT           ; [PC, #0x03B4] [0x08002D24] =0x20000748 
+  0x0800296E:  7809         LDRB       R1, [R1]
+  0x08002970:  2900         CMP        R1, #0
+  0x08002972:  D001         BEQ        .L141                    ; 0x08002978
+  0x08002974:  4639         MOV        R1, R7
+  0x08002976:  3121         ADDS       R1, #33
+
.L141:
+  0x08002978:  4AE8         LDR        R2, =offTimeCounterRT    ; [PC, #0x03A0] [0x08002D1C] =0x200006B0 
+  0x0800297A:  6011         STR        R1, [R2]
+
.L142:
+  0x0800297C:  4AE6         LDR        R2, =blinkCounter        ; [PC, #0x0398] [0x08002D18] =0x200006EC 
+  0x0800297E:  6811         LDR        R1, [R2]
+  0x08002980:  2900         CMP        R1, #0
+  0x08002982:  D002         BEQ        .L143                    ; 0x0800298A
+  0x08002984:  1E49         SUBS       R1, R1, #1
+  0x08002986:  6011         STR        R1, [R2]
+  0x08002988:  E7E4         B          .L139                    ; 0x08002954
+
.L143:
+  0x0800298A:  49E7         LDR        R1, =numberOfBlinks      ; [PC, #0x039C] [0x08002D28] =0x200006BC 
+  0x0800298C:  6809         LDR        R1, [R1]
+  0x0800298E:  4AE2         LDR        R2, =blinkCounter        ; [PC, #0x0388] [0x08002D18] =0x200006EC 
+  0x08002990:  6011         STR        R1, [R2]
+  0x08002992:  49E6         LDR        R1, =pauseTime           ; [PC, #0x0398] [0x08002D2C] =0x20000734 
+  0x08002994:  780A         LDRB       R2, [R1]
+  0x08002996:  2A00         CMP        R2, #0
+  0x08002998:  49B4         LDR        R1, =0x00001388          ; [PC, #0x02D0] [0x08002C6C] 
+  0x0800299A:  D100         BNE        .L144                    ; 0x0800299E
+  0x0800299C:  2100         MOVS       R1, #0
+
.L144:
+  0x0800299E:  4ADF         LDR        R2, =offTimeCounterRT    ; [PC, #0x037C] [0x08002D1C] =0x200006B0 
+  0x080029A0:  6011         STR        R1, [R2]
+
.L145:
+  0x080029A2:  2900         CMP        R1, #0
+  0x080029A4:  D00C         BEQ        .L147                    ; 0x080029C0
+  0x080029A6:  1E49         SUBS       R1, R1, #1
+  0x080029A8:  4ADC         LDR        R2, =offTimeCounterRT    ; [PC, #0x0370] [0x08002D1C] =0x200006B0 
+  0x080029AA:  6011         STR        R1, [R2]
+  0x080029AC:  D108         BNE        .L147                    ; 0x080029C0
+  0x080029AE:  49D8         LDR        R1, =0x50000818          ; [PC, #0x0360] [0x08002D10] 
+  0x080029B0:  9A1E         LDR        R2, [SP, #120]
+  0x080029B2:  600A         STR        R2, [R1]
+  0x080029B4:  49DE         LDR        R1, =onTimeRT            ; [PC, #0x0378] [0x08002D30] =0x2000073C 
+  0x080029B6:  7809         LDRB       R1, [R1]
+  0x080029B8:  2900         CMP        R1, #0
+  0x080029BA:  D000         BEQ        .L146                    ; 0x080029BE
+  0x080029BC:  21C8         MOVS       R1, #200
+
.L146:
+  0x080029BE:  6001         STR        R1, [R0]
+
.L147:
+  0x080029C0:  6860         LDR        R0, [R4, #4]
+  0x080029C2:  4DAD         LDR        R5, =0x00000CE4          ; [PC, #0x02B4] [0x08002C78] 
+  0x080029C4:  4368         MULS       R0, R5, R0
+  0x080029C6:  4EAD         LDR        R6, =0x00010063          ; [PC, #0x02B4] [0x08002C7C] 
+  0x080029C8:  4631         MOV        R1, R6
+  0x080029CA:  F003 FB3A    BL         __aeabi_idiv             ; 0x08006042
+  0x080029CE:  4621         MOV        R1, R4
+  0x080029D0:  4604         MOV        R4, R0
+  0x080029D2:  2706         MOVS       R7, #6
+  0x080029D4:  437C         MULS       R4, R7, R4
+  0x080029D6:  48D7         LDR        R0, =voltageUin          ; [PC, #0x035C] [0x08002D34] =0x20000688 
+  0x080029D8:  6004         STR        R4, [R0]
+  0x080029DA:  6888         LDR        R0, [R1, #8]
+  0x080029DC:  4368         MULS       R0, R5, R0
+  0x080029DE:  4631         MOV        R1, R6
+  0x080029E0:  F003 FB2F    BL         __aeabi_idiv             ; 0x08006042
+  0x080029E4:  4602         MOV        R2, R0
+  0x080029E6:  437A         MULS       R2, R7, R2
+  0x080029E8:  48D3         LDR        R0, =voltageUout         ; [PC, #0x034C] [0x08002D38] =0x20000684 
+  0x080029EA:  6002         STR        R2, [R0]
+  0x080029EC:  49D3         LDR        R1, =relaisState         ; [PC, #0x034C] [0x08002D3C] =0x20000730 
+  0x080029EE:  48D4         LDR        R0, =dropLimitCounter    ; [PC, #0x0350] [0x08002D40] =0x200006E4 
+  0x080029F0:  7809         LDRB       R1, [R1]
+  0x080029F2:  2901         CMP        R1, #1
+  0x080029F4:  6801         LDR        R1, [R0]
+  0x080029F6:  D112         BNE        .L149                    ; 0x08002A1E
+  0x080029F8:  1AA3         SUBS       R3, R4, R2
+  0x080029FA:  17DE         ASRS       R6, R3, #31
+  0x080029FC:  4073         EORS       R3, R6
+  0x080029FE:  1B9B         SUBS       R3, R3, R6
+  0x08002A00:  2B5B         CMP        R3, #91
+  0x08002A02:  D30C         BCC        .L149                    ; 0x08002A1E
+  0x08002A04:  4FCF         LDR        R7, =0x000003C7          ; [PC, #0x033C] [0x08002D44] 
+  0x08002A06:  463E         MOV        R6, R7
+  0x08002A08:  3621         ADDS       R6, #33
+  0x08002A0A:  42B1         CMP        R1, R6
+  0x08002A0C:  9D18         LDR        R5, [SP, #96]
+  0x08002A0E:  D201         BCS        .L148                    ; 0x08002A14
+  0x08002A10:  1C49         ADDS       R1, R1, #1
+  0x08002A12:  6001         STR        R1, [R0]
+
.L148:
+  0x08002A14:  48CC         LDR        R0, =0x08006357          ; [PC, #0x0330] [0x08002D48] 
+  0x08002A16:  4621         MOV        R1, R4
+  0x08002A18:  F002 FC44    BL         printf                   ; 0x080052A4
+  0x08002A1C:  E005         B          .L150                    ; 0x08002A2A
+
.L149:
+  0x08002A1E:  2900         CMP        R1, #0
+  0x08002A20:  4FC8         LDR        R7, =0x000003C7          ; [PC, #0x0320] [0x08002D44] 
+  0x08002A22:  9D18         LDR        R5, [SP, #96]
+  0x08002A24:  D001         BEQ        .L150                    ; 0x08002A2A
+  0x08002A26:  1E49         SUBS       R1, R1, #1
+  0x08002A28:  6001         STR        R1, [R0]
+
.L150:
+  0x08002A2A:  48C8         LDR        R0, =uwTick              ; [PC, #0x0320] [0x08002D4C] =0x2000068C 
+  0x08002A2C:  6800         LDR        R0, [R0]
+  0x08002A2E:  49C8         LDR        R1, =oldTimeMSTick       ; [PC, #0x0320] [0x08002D50] =0x200006AC 
+  0x08002A30:  6008         STR        R0, [R1]
+  0x08002A32:  49C8         LDR        R1, =msCounter           ; [PC, #0x0320] [0x08002D54] =0x200006C0 
+  0x08002A34:  6808         LDR        R0, [R1]
+  0x08002A36:  1C40         ADDS       R0, R0, #1
+  0x08002A38:  6008         STR        R0, [R1]
+
.L151:
+  0x08002A3A:  4639         MOV        R1, R7
+  0x08002A3C:  311F         ADDS       R1, #31
+  0x08002A3E:  4288         CMP        R0, R1
+  0x08002A40:  DD6F         BLE        .L156                    ; 0x08002B22
+  0x08002A42:  488C         LDR        R0, =adcData             ; [PC, #0x0230] [0x08002C74] =0x20000660 
+  0x08002A44:  6900         LDR        R0, [R0, #16]
+  0x08002A46:  498C         LDR        R1, =0x00000CE4          ; [PC, #0x0230] [0x08002C78] 
+  0x08002A48:  4348         MULS       R0, R1, R0
+  0x08002A4A:  0C00         LSRS       R0, R0, #16
+  0x08002A4C:  49C2         LDR        R1, =calTemperatureSensor30Value ; [PC, #0x0308] [0x08002D58] =0x200006E8 
+  0x08002A4E:  6809         LDR        R1, [R1]
+  0x08002A50:  1A40         SUBS       R0, R0, R1
+  0x08002A52:  F002 FBE3    BL         __aeabi_i2d              ; 0x0800521C
+  0x08002A56:  4AC1         LDR        R2, =0xA3D70A3D          ; [PC, #0x0304] [0x08002D5C] 
+  0x08002A58:  4BC1         LDR        R3, =0x40043D70          ; [PC, #0x0304] [0x08002D60] 
+  0x08002A5A:  F003 FA56    BL         __aeabi_ddiv             ; 0x08005F0A
+  0x08002A5E:  F003 FAB6    BL         __aeabi_d2iz             ; 0x08005FCE
+  0x08002A62:  4604         MOV        R4, R0
+  0x08002A64:  3419         ADDS       R4, #25
+  0x08002A66:  22C8         MOVS       R2, #200
+  0x08002A68:  48BE         LDR        R0, =sys_data            ; [PC, #0x02F8] [0x08002D64] =0x20000234 
+  0x08002A6A:  5284         STRH       R4, [R0, R2]
+  0x08002A6C:  9823         LDR        R0, [SP, #140]
+  0x08002A6E:  1C40         ADDS       R0, R0, #1
+  0x08002A70:  2164         MOVS       R1, #100
+  0x08002A72:  2864         CMP        R0, #100
+  0x08002A74:  D300         BCC        .L152                    ; 0x08002A78
+  0x08002A76:  4608         MOV        R0, R1
+
.L152:
+  0x08002A78:  4BBA         LDR        R3, =sys_data            ; [PC, #0x02E8] [0x08002D64] =0x20000234 
+  0x08002A7A:  5E9B         LDRSH      R3, [R3, R2]
+  0x08002A7C:  2B32         CMP        R3, #50
+  0x08002A7E:  DC00         BGT        .L153                    ; 0x08002A82
+  0x08002A80:  9823         LDR        R0, [SP, #140]
+
.L153:
+  0x08002A82:  1E46         SUBS       R6, R0, #1
+  0x08002A84:  4603         MOV        R3, R0
+  0x08002A86:  41B3         SBCS       R3, R6
+  0x08002A88:  4EB6         LDR        R6, =sys_data            ; [PC, #0x02D8] [0x08002D64] =0x20000234 
+  0x08002A8A:  5EB2         LDRSH      R2, [R6, R2]
+  0x08002A8C:  2601         MOVS       R6, #1
+  0x08002A8E:  2700         MOVS       R7, #0
+  0x08002A90:  2A32         CMP        R2, #50
+  0x08002A92:  4632         MOV        R2, R6
+  0x08002A94:  DB00         BLT        .L154                    ; 0x08002A98
+  0x08002A96:  463A         MOV        R2, R7
+
.L154:
+  0x08002A98:  9721         STR        R7, [SP, #132]
+  0x08002A9A:  401A         ANDS       R2, R3
+  0x08002A9C:  1A82         SUBS       R2, R0, R2
+  0x08002A9E:  2A64         CMP        R2, #100
+  0x08002AA0:  9223         STR        R2, [SP, #140]
+  0x08002AA2:  D300         BCC        .L155                    ; 0x08002AA6
+  0x08002AA4:  460A         MOV        R2, R1
+
.L155:
+  0x08002AA6:  48B0         LDR        R0, =htim17              ; [PC, #0x02C0] [0x08002D68] =0x200005C8 
+  0x08002AA8:  6807         LDR        R7, [R0]
+  0x08002AAA:  6AF8         LDR        R0, [R7, #44]
+  0x08002AAC:  1C40         ADDS       R0, R0, #1
+  0x08002AAE:  4350         MULS       R0, R2, R0
+  0x08002AB0:  F003 FAE7    BL         __aeabi_uidiv            ; 0x08006082
+  0x08002AB4:  6378         STR        R0, [R7, #52]
+  0x08002AB6:  489F         LDR        R0, =voltageUin          ; [PC, #0x027C] [0x08002D34] =0x20000688 
+  0x08002AB8:  6800         LDR        R0, [R0]
+  0x08002ABA:  21CC         MOVS       R1, #204
+  0x08002ABC:  4BA9         LDR        R3, =sys_data            ; [PC, #0x02A4] [0x08002D64] =0x20000234 
+  0x08002ABE:  5258         STRH       R0, [R3, R1]
+  0x08002AC0:  489D         LDR        R0, =voltageUout         ; [PC, #0x0274] [0x08002D38] =0x20000684 
+  0x08002AC2:  6800         LDR        R0, [R0]
+  0x08002AC4:  22CE         MOVS       R2, #206
+  0x08002AC6:  5298         STRH       R0, [R3, R2]
+  0x08002AC8:  5A58         LDRH       R0, [R3, R1]
+  0x08002ACA:  5A99         LDRH       R1, [R3, R2]
+  0x08002ACC:  1A40         SUBS       R0, R0, R1
+  0x08002ACE:  21D0         MOVS       R1, #208
+  0x08002AD0:  5258         STRH       R0, [R3, R1]
+  0x08002AD2:  48A6         LDR        R0, =frequency           ; [PC, #0x0298] [0x08002D6C] =0x200006E0 
+  0x08002AD4:  8800         LDRH       R0, [R0]
+  0x08002AD6:  0840         LSRS       R0, R0, #1
+  0x08002AD8:  991D         LDR        R1, [SP, #116]
+  0x08002ADA:  4348         MULS       R0, R1, R0
+  0x08002ADC:  21D4         MOVS       R1, #212
+  0x08002ADE:  5258         STRH       R0, [R3, R1]
+  0x08002AE0:  20D2         MOVS       R0, #210
+  0x08002AE2:  9923         LDR        R1, [SP, #140]
+  0x08002AE4:  5219         STRH       R1, [R3, R0]
+  0x08002AE6:  489B         LDR        R0, =msCounter           ; [PC, #0x026C] [0x08002D54] =0x200006C0 
+  0x08002AE8:  9921         LDR        R1, [SP, #132]
+  0x08002AEA:  6001         STR        R1, [R0]
+  0x08002AEC:  48A0         LDR        R0, =temp                ; [PC, #0x0280] [0x08002D70] =0x20000690 
+  0x08002AEE:  6004         STR        R4, [R0]
+  0x08002AF0:  4AA0         LDR        R2, =0x50000010          ; [PC, #0x0280] [0x08002D74] 
+  0x08002AF2:  6810         LDR        R0, [R2]
+  0x08002AF4:  4030         ANDS       R0, R6
+  0x08002AF6:  21D8         MOVS       R1, #216
+  0x08002AF8:  5258         STRH       R0, [R3, R1]
+  0x08002AFA:  6810         LDR        R0, [R2]
+  0x08002AFC:  0780         LSLS       R0, R0, #30
+  0x08002AFE:  0FC0         LSRS       R0, R0, #31
+  0x08002B00:  21D6         MOVS       R1, #214
+  0x08002B02:  5258         STRH       R0, [R3, R1]
+  0x08002B04:  4858         LDR        R0, =0x50000410          ; [PC, #0x0160] [0x08002C68] 
+  0x08002B06:  6800         LDR        R0, [R0]
+  0x08002B08:  0880         LSRS       R0, R0, #2
+  0x08002B0A:  4386         BICS       R6, R0
+  0x08002B0C:  20DA         MOVS       R0, #218
+  0x08002B0E:  521E         STRH       R6, [R3, R0]
+  0x08002B10:  488A         LDR        R0, =relaisState         ; [PC, #0x0228] [0x08002D3C] =0x20000730 
+  0x08002B12:  7800         LDRB       R0, [R0]
+  0x08002B14:  21DC         MOVS       R1, #220
+  0x08002B16:  5258         STRH       R0, [R3, R1]
+  0x08002B18:  485A         LDR        R0, =relais_temperature  ; [PC, #0x0168] [0x08002C84] =0x20000694 
+  0x08002B1A:  6800         LDR        R0, [R0]
+  0x08002B1C:  21CA         MOVS       R1, #202
+  0x08002B1E:  5258         STRH       R0, [R3, R1]
+  0x08002B20:  4F88         LDR        R7, =0x000003C7          ; [PC, #0x0220] [0x08002D44] 
+
.L156:
+  0x08002B22:  4895         LDR        R0, =mode                ; [PC, #0x0254] [0x08002D78] =0x20000739 
+  0x08002B24:  7800         LDRB       R0, [R0]
+  0x08002B26:  2807         CMP        R0, #7
+  0x08002B28:  D900         BLS        .L157                    ; 0x08002B2C
+  0x08002B2A:  E15D         B          .L166                    ; 0x08002DE8
+
.L157:
+  0x08002B2C:  463C         MOV        R4, R7
+  0x08002B2E:  46C0         NOP
+  0x08002B30:  4478         ADD        R0, PC
+  0x08002B32:  7900         LDRB       R0, [R0, #4]
+  0x08002B34:  0040         LSLS       R0, R0, #1
+  0x08002B36:  4487         ADD        PC, R0
+  0x08002B38:  03           DC.B       0x03                     ; '\x03'
+  0x08002B39:  82           DC.B       0x82                     ; '\x82'
+  0x08002B3A:  3C           DC.B       0x3C                     ; '<'
+  0x08002B3B:  41           DC.B       0x41                     ; 'A'
+  0x08002B3C:  37           DC.B       0x37                     ; '7'
+  0x08002B3D:  87           DC.B       0x87                     ; '\x87'
+  0x08002B3E:  D9           DC.B       0xD9                     ; '\xD9'
+  0x08002B3F:  46           DC.B       0x46                     ; 'F'
+  0x08002B40:  4C8E         LDR        R4, =smState.137         ; [PC, #0x0238] [0x08002D7C] =0x20000735 
+  0x08002B42:  7820         LDRB       R0, [R4]
+  0x08002B44:  0040         LSLS       R0, R0, #1
+  0x08002B46:  46C0         NOP
+  0x08002B48:  4478         ADD        R0, PC
+  0x08002B4A:  8880         LDRH       R0, [R0, #4]
+  0x08002B4C:  0040         LSLS       R0, R0, #1
+  0x08002B4E:  4487         ADD        PC, R0
+  0x08002B50:  07           DC.B       0x07                     ; '\x07'
+  0x08002B51:  00           DC.B       0x00                     ; '\0'
+  0x08002B52:  B7           DC.B       0xB7                     ; '\xB7'
+  0x08002B53:  03           DC.B       0x03                     ; '\x03'
+  0x08002B54:  81           DC.B       0x81                     ; '\x81'
+  0x08002B55:  01           DC.B       0x01                     ; '\x01'
+  0x08002B56:  C7           DC.B       0xC7                     ; '\xC7'
+  0x08002B57:  01           DC.B       0x01                     ; '\x01'
+  0x08002B58:  080063E7     DC.W       080063E7               ; R_ARM_ABS32
+  0x08002B5C:  200006C8     DC.W       longPressCounterButtonOff
+  0x08002B60:  4841         LDR        R0, =0x50000410          ; [PC, #0x0104] [0x08002C68] 
+  0x08002B62:  6801         LDR        R1, [R0]
+  0x08002B64:  4A3C         LDR        R2, =buttonState         ; [PC, #240] [0x08002C58] =0x2000073A 
+  0x08002B66:  7810         LDRB       R0, [R2]
+  0x08002B68:  2801         CMP        R0, #1
+  0x08002B6A:  D001         BEQ        .L158                    ; 0x08002B70
+  0x08002B6C:  F001 F988    BL         .L236                    ; 0x08003E80
+
.L158:
+  0x08002B70:  0748         LSLS       R0, R1, #29
+  0x08002B72:  D501         BPL        .L159                    ; 0x08002B78
+  0x08002B74:  F001 F961    BL         .L234                    ; 0x08003E3A
+
.L159:
+  0x08002B78:  483B         LDR        R0, =0x50000410          ; [PC, #236] [0x08002C68] 
+  0x08002B7A:  9920         LDR        R1, [SP, #128]
+  0x08002B7C:  6081         STR        R1, [R0, #8]
+  0x08002B7E:  2000         MOVS       R0, #0
+  0x08002B80:  7010         STRB       R0, [R2]
+  0x08002B82:  486B         LDR        R0, =onTimeRT            ; [PC, #0x01AC] [0x08002D30] =0x2000073C 
+  0x08002B84:  7005         STRB       R5, [R0]
+  0x08002B86:  4867         LDR        R0, =offTimeRT           ; [PC, #0x019C] [0x08002D24] =0x20000748 
+  0x08002B88:  7005         STRB       R5, [R0]
+  0x08002B8A:  4865         LDR        R0, =blinkModeRT         ; [PC, #0x0194] [0x08002D20] =0x20000754 
+  0x08002B8C:  7005         STRB       R5, [R0]
+  0x08002B8E:  4866         LDR        R0, =numberOfBlinks      ; [PC, #0x0198] [0x08002D28] =0x200006BC 
+  0x08002B90:  2703         MOVS       R7, #3
+  0x08002B92:  6007         STR        R7, [R0]
+  0x08002B94:  4860         LDR        R0, =blinkCounter        ; [PC, #0x0180] [0x08002D18] =0x200006EC 
+  0x08002B96:  6007         STR        R7, [R0]
+  0x08002B98:  9A10         LDR        R2, [SP, #64]
+  0x08002B9A:  32F4         ADDS       R2, #244
+  0x08002B9C:  4878         LDR        R0, =0x0800690C          ; [PC, #0x01E0] [0x08002D80] 
+  0x08002B9E:  495D         LDR        R1, =onTimeCounterRT     ; [PC, #0x0174] [0x08002D14] =0x2000069C 
+  0x08002BA0:  4B62         LDR        R3, =pauseTime           ; [PC, #0x0188] [0x08002D2C] =0x20000734 
+  0x08002BA2:  9E1E         LDR        R6, [SP, #120]
+  0x08002BA4:  F001 F95F    BL         .L235                    ; 0x08003E66
+  0x08002BA8:  2001         MOVS       R0, #1
+  0x08002BAA:  F002 F8AD    BL         MODE_SECONDARYPROTECTION_PLUS_Exec ; 0x08004D08
+  0x08002BAE:  F001 FAB1    BL         .L252                    ; 0x08004114
+  0x08002BB2:  2000         MOVS       R0, #0
+  0x08002BB4:  F002 F8A8    BL         MODE_SECONDARYPROTECTION_PLUS_Exec ; 0x08004D08
+  0x08002BB8:  F001 FAAC    BL         .L252                    ; 0x08004114
+  0x08002BBC:  2001         MOVS       R0, #1
+  0x08002BBE:  F001 FD65    BL         MODE_SECONDARYPROTECTION_Exec ; 0x0800468C
+  0x08002BC2:  F001 FAA7    BL         .L252                    ; 0x08004114
+  0x08002BC6:  486F         LDR        R0, =smState.145         ; [PC, #0x01BC] [0x08002D84] =0x20000733 
+  0x08002BC8:  7800         LDRB       R0, [R0]
+  0x08002BCA:  0040         LSLS       R0, R0, #1
+  0x08002BCC:  4478         ADD        R0, PC
+  0x08002BCE:  8880         LDRH       R0, [R0, #4]
+  0x08002BD0:  0040         LSLS       R0, R0, #1
+  0x08002BD2:  4487         ADD        PC, R0
+  0x08002BD4:  11           DC.B       0x11                     ; '\x11'
+  0x08002BD5:  00           DC.B       0x00                     ; '\0'
+  0x08002BD6:  29           DC.B       0x29                     ; ')'
+  0x08002BD7:  02           DC.B       0x02                     ; '\x02'
+  0x08002BD8:  0E           DC.B       0x0E                     ; '\x0E'
+  0x08002BD9:  01           DC.B       0x01                     ; '\x01'
+  0x08002BDA:  6F           DC.B       0x6F                     ; 'o'
+  0x08002BDB:  01           DC.B       0x01                     ; '\x01'
+  0x08002BDC:  2000073A     DC.W       buttonState
+  0x08002BE0:  080065A9     DC.W       080065A9               ; R_ARM_ABS32
+  0x08002BE4:  200006A8     DC.W       onTimeCounter
+  0x08002BE8:  50000410     DC.W       0x50000410
+  0x08002BEC:  2000075C     DC.W       alarmMode
+  0x08002BF0:  20000750     DC.W       offTime
+  0x08002BF4:  00001388     DC.W       0x00001388
+  0x08002BF8:  481B         LDR        R0, =0x50000410          ; [PC, #108] [0x08002C68] 
+  0x08002BFA:  6801         LDR        R1, [R0]
+  0x08002BFC:  4C16         LDR        R4, =buttonState         ; [PC, #88] [0x08002C58] =0x2000073A 
+  0x08002BFE:  7820         LDRB       R0, [R4]
+  0x08002C00:  2801         CMP        R0, #1
+  0x08002C02:  D001         BEQ        .L160                    ; 0x08002C08
+  0x08002C04:  F001 F8E1    BL         .L231                    ; 0x08003DCA
+
.L160:
+  0x08002C08:  0748         LSLS       R0, R1, #29
+  0x08002C0A:  D501         BPL        .L161                    ; 0x08002C10
+  0x08002C0C:  F001 F8BA    BL         .L229                    ; 0x08003D84
+
.L161:
+  0x08002C10:  4815         LDR        R0, =0x50000410          ; [PC, #84] [0x08002C68] 
+  0x08002C12:  9920         LDR        R1, [SP, #128]
+  0x08002C14:  6081         STR        R1, [R0, #8]
+  0x08002C16:  2000         MOVS       R0, #0
+  0x08002C18:  7020         STRB       R0, [R4]
+  0x08002C1A:  4845         LDR        R0, =onTimeRT            ; [PC, #0x0114] [0x08002D30] =0x2000073C 
+  0x08002C1C:  7005         STRB       R5, [R0]
+  0x08002C1E:  4841         LDR        R0, =offTimeRT           ; [PC, #0x0104] [0x08002D24] =0x20000748 
+  0x08002C20:  7005         STRB       R5, [R0]
+  0x08002C22:  483F         LDR        R0, =blinkModeRT         ; [PC, #252] [0x08002D20] =0x20000754 
+  0x08002C24:  7005         STRB       R5, [R0]
+  0x08002C26:  4840         LDR        R0, =numberOfBlinks      ; [PC, #0x0100] [0x08002D28] =0x200006BC 
+  0x08002C28:  9F15         LDR        R7, [SP, #84]
+  0x08002C2A:  6007         STR        R7, [R0]
+  0x08002C2C:  483A         LDR        R0, =blinkCounter        ; [PC, #232] [0x08002D18] =0x200006EC 
+  0x08002C2E:  6007         STR        R7, [R0]
+  0x08002C30:  4855         LDR        R0, =0x080066FF          ; [PC, #0x0154] [0x08002D88] 
+  0x08002C32:  4938         LDR        R1, =onTimeCounterRT     ; [PC, #224] [0x08002D14] =0x2000069C 
+  0x08002C34:  4B3D         LDR        R3, =pauseTime           ; [PC, #244] [0x08002D2C] =0x20000734 
+  0x08002C36:  9A09         LDR        R2, [SP, #36]
+  0x08002C38:  9E1E         LDR        R6, [SP, #120]
+  0x08002C3A:  F001 F8B9    BL         .L230                    ; 0x08003DB0
+  0x08002C3E:  2000         MOVS       R0, #0
+  0x08002C40:  F001 FD24    BL         MODE_SECONDARYPROTECTION_Exec ; 0x0800468C
+  0x08002C44:  F001 FA66    BL         .L252                    ; 0x08004114
+  0x08002C48:  4850         LDR        R0, =smState.122         ; [PC, #0x0140] [0x08002D8C] =0x20000736 
+  0x08002C4A:  7800         LDRB       R0, [R0]
+  0x08002C4C:  A104         ADR        R1, 0x08002C60
+  0x08002C4E:  0040         LSLS       R0, R0, #1
+  0x08002C50:  5A08         LDRH       R0, [R1, R0]
+  0x08002C52:  0040         LSLS       R0, R0, #1
+  0x08002C54:  4487         ADD        PC, R0
+  0x08002C56:  46C0         NOP
+  0x08002C58:  2000073A     DC.W       buttonState
+  0x08002C5C:  200006B8     DC.W       offTimeCounter
+  0x08002C60:  26           DC.B       0x26                     ; '&'
+  0x08002C61:  00           DC.B       0x00                     ; '\0'
+  0x08002C62:  D5           DC.B       0xD5                     ; '\xD5'
+  0x08002C63:  04           DC.B       0x04                     ; '\x04'
+  0x08002C64:  03           DC.B       0x03                     ; '\x03'
+  0x08002C65:  03           DC.B       0x03                     ; '\x03'
+  0x08002C66:  57           DC.B       0x57                     ; 'W'
+  0x08002C67:  04           DC.B       0x04                     ; '\x04'
+  0x08002C68:  50000410     DC.W       0x50000410
+  0x08002C6C:  00001388     DC.W       0x00001388
+  0x08002C70:  20000744     DC.W       onTime
+  0x08002C74:  20000660     DC.W       adcData
+  0x08002C78:  00000CE4     DC.W       0x00000CE4
+  0x08002C7C:  00010063     DC.W       0x00010063
+  0x08002C80:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08002C84:  20000694     DC.W       relais_temperature
+  0x08002C88:  20000698     DC.W       onTimeCounterSET
+  0x08002C8C:  200006A0     DC.W       onTimeCounterRESET
+  0x08002C90:  200006A4     DC.W       onTimeCounterGN
+  0x08002C94:  50000818     DC.W       0x50000818
+  0x08002C98:  20000758     DC.W       blinkModeGN
+  0x08002C9C:  2000074C     DC.W       offTimeGN
+  0x08002CA0:  200006B4     DC.W       offTimeCounterGN
+  0x08002CA4:  483A         LDR        R0, =0x50000410          ; [PC, #232] [0x08002D90] 
+  0x08002CA6:  6801         LDR        R1, [R0]
+  0x08002CA8:  4C3A         LDR        R4, =buttonState         ; [PC, #232] [0x08002D94] =0x2000073A 
+  0x08002CAA:  7820         LDRB       R0, [R4]
+  0x08002CAC:  2801         CMP        R0, #1
+  0x08002CAE:  D001         BEQ        .L162                    ; 0x08002CB4
+  0x08002CB0:  F001 F99E    BL         .L244                    ; 0x08003FF0
+
.L162:
+  0x08002CB4:  0748         LSLS       R0, R1, #29
+  0x08002CB6:  D501         BPL        .L163                    ; 0x08002CBC
+  0x08002CB8:  F001 F977    BL         .L242                    ; 0x08003FAA
+
.L163:
+  0x08002CBC:  4834         LDR        R0, =0x50000410          ; [PC, #208] [0x08002D90] 
+  0x08002CBE:  9920         LDR        R1, [SP, #128]
+  0x08002CC0:  6081         STR        R1, [R0, #8]
+  0x08002CC2:  2000         MOVS       R0, #0
+  0x08002CC4:  7020         STRB       R0, [R4]
+  0x08002CC6:  481A         LDR        R0, =onTimeRT            ; [PC, #104] [0x08002D30] =0x2000073C 
+  0x08002CC8:  7005         STRB       R5, [R0]
+  0x08002CCA:  4816         LDR        R0, =offTimeRT           ; [PC, #88] [0x08002D24] =0x20000748 
+  0x08002CCC:  7005         STRB       R5, [R0]
+  0x08002CCE:  4814         LDR        R0, =blinkModeRT         ; [PC, #80] [0x08002D20] =0x20000754 
+  0x08002CD0:  7005         STRB       R5, [R0]
+  0x08002CD2:  4815         LDR        R0, =numberOfBlinks      ; [PC, #84] [0x08002D28] =0x200006BC 
+  0x08002CD4:  2703         MOVS       R7, #3
+  0x08002CD6:  6007         STR        R7, [R0]
+  0x08002CD8:  480F         LDR        R0, =blinkCounter        ; [PC, #60] [0x08002D18] =0x200006EC 
+  0x08002CDA:  6007         STR        R7, [R0]
+  0x08002CDC:  9A10         LDR        R2, [SP, #64]
+  0x08002CDE:  32F4         ADDS       R2, #244
+  0x08002CE0:  482D         LDR        R0, =0x0800667B          ; [PC, #180] [0x08002D98] 
+  0x08002CE2:  490C         LDR        R1, =onTimeCounterRT     ; [PC, #48] [0x08002D14] =0x2000069C 
+  0x08002CE4:  4B11         LDR        R3, =pauseTime           ; [PC, #68] [0x08002D2C] =0x20000734 
+  0x08002CE6:  9E1E         LDR        R6, [SP, #120]
+  0x08002CE8:  F001 F975    BL         .L243                    ; 0x08003FD6
+  0x08002CEC:  482B         LDR        R0, =smState             ; [PC, #172] [0x08002D9C] =0x20000737 
+  0x08002CEE:  7800         LDRB       R0, [R0]
+  0x08002CF0:  A105         ADR        R1, 0x08002D08
+  0x08002CF2:  0040         LSLS       R0, R0, #1
+  0x08002CF4:  5A08         LDRH       R0, [R1, R0]
+  0x08002CF6:  0040         LSLS       R0, R0, #1
+  0x08002CF8:  4487         ADD        PC, R0
+  0x08002CFA:  46C0         NOP
+  0x08002CFC:  200006B4     DC.W       offTimeCounterGN
+  0x08002D00:  20000740     DC.W       onTimeGN
+  0x08002D04:  2000069C     DC.W       onTimeCounterRT
+  0x08002D08:  52           DC.B       0x52                     ; 'R'
+  0x08002D09:  00           DC.B       0x00                     ; '\0'
+  0x08002D0A:  0C           DC.B       0x0C                     ; '\x0C'
+  0x08002D0B:  06           DC.B       0x06                     ; '\x06'
+  0x08002D0C:  D4           DC.B       0xD4                     ; '\xD4'
+  0x08002D0D:  03           DC.B       0x03                     ; '\x03'
+  0x08002D0E:  6C           DC.B       0x6C                     ; 'l'
+  0x08002D0F:  04           DC.B       0x04                     ; '\x04'
+  0x08002D10:  50000818     DC.W       0x50000818
+  0x08002D14:  2000069C     DC.W       onTimeCounterRT
+  0x08002D18:  200006EC     DC.W       blinkCounter
+  0x08002D1C:  200006B0     DC.W       offTimeCounterRT
+  0x08002D20:  20000754     DC.W       blinkModeRT
+  0x08002D24:  20000748     DC.W       offTimeRT
+  0x08002D28:  200006BC     DC.W       numberOfBlinks
+  0x08002D2C:  20000734     DC.W       pauseTime
+  0x08002D30:  2000073C     DC.W       onTimeRT
+  0x08002D34:  20000688     DC.W       voltageUin
+  0x08002D38:  20000684     DC.W       voltageUout
+  0x08002D3C:  20000730     DC.W       relaisState
+  0x08002D40:  200006E4     DC.W       dropLimitCounter
+  0x08002D44:  000003C7     DC.W       0x000003C7
+  0x08002D48:  08006357     DC.W       08006357               ; R_ARM_ABS32
+  0x08002D4C:  2000068C     DC.W       uwTick
+  0x08002D50:  200006AC     DC.W       oldTimeMSTick
+  0x08002D54:  200006C0     DC.W       msCounter
+  0x08002D58:  200006E8     DC.W       calTemperatureSensor30Value
+  0x08002D5C:  A3D70A3D     DC.W       0xA3D70A3D
+  0x08002D60:  40043D70     DC.W       0x40043D70
+  0x08002D64:  20000234     DC.W       sys_data
+  0x08002D68:  200005C8     DC.W       htim17
+  0x08002D6C:  200006E0     DC.W       frequency
+  0x08002D70:  20000690     DC.W       temp
+  0x08002D74:  50000010     DC.W       0x50000010
+  0x08002D78:  20000739     DC.W       mode
+  0x08002D7C:  20000735     DC.W       smState.137
+  0x08002D80:  0800690C     DC.W       0800690C               ; R_ARM_ABS32
+  0x08002D84:  20000733     DC.W       smState.145
+  0x08002D88:  080066FF     DC.W       080066FF               ; R_ARM_ABS32
+  0x08002D8C:  20000736     DC.W       smState.122
+  0x08002D90:  50000410     DC.W       0x50000410
+  0x08002D94:  2000073A     DC.W       buttonState
+  0x08002D98:  0800667B     DC.W       0800667B               ; R_ARM_ABS32
+  0x08002D9C:  20000737     DC.W       smState
+  0x08002DA0:  4883         LDR        R0, =0x50000410          ; [PC, #0x020C] [0x08002FB0] 
+  0x08002DA2:  6801         LDR        R1, [R0]
+  0x08002DA4:  4C83         LDR        R4, =buttonState         ; [PC, #0x020C] [0x08002FB4] =0x2000073A 
+  0x08002DA6:  7820         LDRB       R0, [R4]
+  0x08002DA8:  2801         CMP        R0, #1
+  0x08002DAA:  D001         BEQ        .L164                    ; 0x08002DB0
+  0x08002DAC:  F001 F97B    BL         .L249                    ; 0x080040A6
+
.L164:
+  0x08002DB0:  0748         LSLS       R0, R1, #29
+  0x08002DB2:  D501         BPL        .L165                    ; 0x08002DB8
+  0x08002DB4:  F001 F954    BL         .L247                    ; 0x08004060
+
.L165:
+  0x08002DB8:  487D         LDR        R0, =0x50000410          ; [PC, #0x01F4] [0x08002FB0] 
+  0x08002DBA:  9920         LDR        R1, [SP, #128]
+  0x08002DBC:  6081         STR        R1, [R0, #8]
+  0x08002DBE:  2000         MOVS       R0, #0
+  0x08002DC0:  7020         STRB       R0, [R4]
+  0x08002DC2:  487D         LDR        R0, =onTimeRT            ; [PC, #0x01F4] [0x08002FB8] =0x2000073C 
+  0x08002DC4:  7005         STRB       R5, [R0]
+  0x08002DC6:  487D         LDR        R0, =offTimeRT           ; [PC, #0x01F4] [0x08002FBC] =0x20000748 
+  0x08002DC8:  7005         STRB       R5, [R0]
+  0x08002DCA:  487D         LDR        R0, =blinkModeRT         ; [PC, #0x01F4] [0x08002FC0] =0x20000754 
+  0x08002DCC:  7005         STRB       R5, [R0]
+  0x08002DCE:  487D         LDR        R0, =numberOfBlinks      ; [PC, #0x01F4] [0x08002FC4] =0x200006BC 
+  0x08002DD0:  2703         MOVS       R7, #3
+  0x08002DD2:  6007         STR        R7, [R0]
+  0x08002DD4:  487C         LDR        R0, =blinkCounter        ; [PC, #0x01F0] [0x08002FC8] =0x200006EC 
+  0x08002DD6:  6007         STR        R7, [R0]
+  0x08002DD8:  9A10         LDR        R2, [SP, #64]
+  0x08002DDA:  32F4         ADDS       R2, #244
+  0x08002DDC:  487B         LDR        R0, =0x08006617          ; [PC, #0x01EC] [0x08002FCC] 
+  0x08002DDE:  497C         LDR        R1, =onTimeCounterRT     ; [PC, #0x01F0] [0x08002FD0] =0x2000069C 
+  0x08002DE0:  4B7C         LDR        R3, =pauseTime           ; [PC, #0x01F0] [0x08002FD4] =0x20000734 
+  0x08002DE2:  9E1E         LDR        R6, [SP, #120]
+  0x08002DE4:  F001 F952    BL         .L248                    ; 0x0800408C
+
.L166:
+  0x08002DE8:  487B         LDR        R0, =0x080065BA          ; [PC, #0x01EC] [0x08002FD8] 
+  0x08002DEA:  F002 FA01    BL         puts                     ; 0x080051F0
+  0x08002DEE:  F001 F991    BL         .L252                    ; 0x08004114
+  0x08002DF2:  4870         LDR        R0, =buttonState         ; [PC, #0x01C0] [0x08002FB4] =0x2000073A 
+  0x08002DF4:  7800         LDRB       R0, [R0]
+  0x08002DF6:  2800         CMP        R0, #0
+  0x08002DF8:  D001         BEQ        .L167                    ; 0x08002DFE
+  0x08002DFA:  F001 F98B    BL         .L252                    ; 0x08004114
+
.L167:
+  0x08002DFE:  496C         LDR        R1, =0x50000410          ; [PC, #0x01B0] [0x08002FB0] 
+  0x08002E00:  981B         LDR        R0, [SP, #108]
+  0x08002E02:  6188         STR        R0, [R1, #24]
+  0x08002E04:  981A         LDR        R0, [SP, #104]
+  0x08002E06:  6088         STR        R0, [R1, #8]
+  0x08002E08:  4874         LDR        R0, =relaisState         ; [PC, #0x01D0] [0x08002FDC] =0x20000730 
+  0x08002E0A:  2600         MOVS       R6, #0
+  0x08002E0C:  7006         STRB       R6, [R0]
+  0x08002E0E:  4874         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01D0] [0x08002FE0] =0x200006A0 
+  0x08002E10:  9A16         LDR        R2, [SP, #88]
+  0x08002E12:  6002         STR        R2, [R0]
+  0x08002E14:  9820         LDR        R0, [SP, #128]
+  0x08002E16:  6188         STR        R0, [R1, #24]
+  0x08002E18:  4872         LDR        R0, =offTimeCounter      ; [PC, #0x01C8] [0x08002FE4] =0x200006B8 
+  0x08002E1A:  6006         STR        R6, [R0]
+  0x08002E1C:  4872         LDR        R0, =alarmMode           ; [PC, #0x01C8] [0x08002FE8] =0x2000075C 
+  0x08002E1E:  7006         STRB       R6, [R0]
+  0x08002E20:  4872         LDR        R0, =onTimeCounter       ; [PC, #0x01C8] [0x08002FEC] =0x200006A8 
+  0x08002E22:  6006         STR        R6, [R0]
+  0x08002E24:  4972         LDR        R1, =0x50000818          ; [PC, #0x01C8] [0x08002FF0] 
+  0x08002E26:  981F         LDR        R0, [SP, #124]
+  0x08002E28:  6108         STR        R0, [R1, #16]
+  0x08002E2A:  4872         LDR        R0, =offTimeCounterGN    ; [PC, #0x01C8] [0x08002FF4] =0x200006B4 
+  0x08002E2C:  6006         STR        R6, [R0]
+  0x08002E2E:  4872         LDR        R0, =blinkModeGN         ; [PC, #0x01C8] [0x08002FF8] =0x20000758 
+  0x08002E30:  7006         STRB       R6, [R0]
+  0x08002E32:  4872         LDR        R0, =onTimeCounterGN     ; [PC, #0x01C8] [0x08002FFC] =0x200006A4 
+  0x08002E34:  6006         STR        R6, [R0]
+  0x08002E36:  981E         LDR        R0, [SP, #120]
+  0x08002E38:  6108         STR        R0, [R1, #16]
+  0x08002E3A:  4871         LDR        R0, =offTimeCounterRT    ; [PC, #0x01C4] [0x08003000] =0x200006B0 
+  0x08002E3C:  6006         STR        R6, [R0]
+  0x08002E3E:  4860         LDR        R0, =blinkModeRT         ; [PC, #0x0180] [0x08002FC0] =0x20000754 
+  0x08002E40:  7006         STRB       R6, [R0]
+  0x08002E42:  4863         LDR        R0, =onTimeCounterRT     ; [PC, #0x018C] [0x08002FD0] =0x2000069C 
+  0x08002E44:  6006         STR        R6, [R0]
+  0x08002E46:  486F         LDR        R0, =0x080062F6          ; [PC, #0x01BC] [0x08003004] 
+  0x08002E48:  F002 F9D2    BL         puts                     ; 0x080051F0
+  0x08002E4C:  486E         LDR        R0, =smState.145         ; [PC, #0x01B8] [0x08003008] =0x20000733 
+  0x08002E4E:  7006         STRB       R6, [R0]
+  0x08002E50:  F001 F960    BL         .L252                    ; 0x08004114
+  0x08002E54:  4857         LDR        R0, =buttonState         ; [PC, #0x015C] [0x08002FB4] =0x2000073A 
+  0x08002E56:  7800         LDRB       R0, [R0]
+  0x08002E58:  2800         CMP        R0, #0
+  0x08002E5A:  D001         BEQ        .L168                    ; 0x08002E60
+  0x08002E5C:  F001 F95A    BL         .L252                    ; 0x08004114
+
.L168:
+  0x08002E60:  4953         LDR        R1, =0x50000410          ; [PC, #0x014C] [0x08002FB0] 
+  0x08002E62:  981B         LDR        R0, [SP, #108]
+  0x08002E64:  6188         STR        R0, [R1, #24]
+  0x08002E66:  981A         LDR        R0, [SP, #104]
+  0x08002E68:  6088         STR        R0, [R1, #8]
+  0x08002E6A:  485C         LDR        R0, =relaisState         ; [PC, #0x0170] [0x08002FDC] =0x20000730 
+  0x08002E6C:  2600         MOVS       R6, #0
+  0x08002E6E:  7006         STRB       R6, [R0]
+  0x08002E70:  485B         LDR        R0, =onTimeCounterRESET  ; [PC, #0x016C] [0x08002FE0] =0x200006A0 
+  0x08002E72:  9A16         LDR        R2, [SP, #88]
+  0x08002E74:  6002         STR        R2, [R0]
+  0x08002E76:  9820         LDR        R0, [SP, #128]
+  0x08002E78:  6188         STR        R0, [R1, #24]
+  0x08002E7A:  485A         LDR        R0, =offTimeCounter      ; [PC, #0x0168] [0x08002FE4] =0x200006B8 
+  0x08002E7C:  6006         STR        R6, [R0]
+  0x08002E7E:  485A         LDR        R0, =alarmMode           ; [PC, #0x0168] [0x08002FE8] =0x2000075C 
+  0x08002E80:  7006         STRB       R6, [R0]
+  0x08002E82:  485A         LDR        R0, =onTimeCounter       ; [PC, #0x0168] [0x08002FEC] =0x200006A8 
+  0x08002E84:  6006         STR        R6, [R0]
+  0x08002E86:  495A         LDR        R1, =0x50000818          ; [PC, #0x0168] [0x08002FF0] 
+  0x08002E88:  981F         LDR        R0, [SP, #124]
+  0x08002E8A:  6108         STR        R0, [R1, #16]
+  0x08002E8C:  4859         LDR        R0, =offTimeCounterGN    ; [PC, #0x0164] [0x08002FF4] =0x200006B4 
+  0x08002E8E:  6006         STR        R6, [R0]
+  0x08002E90:  4859         LDR        R0, =blinkModeGN         ; [PC, #0x0164] [0x08002FF8] =0x20000758 
+  0x08002E92:  7006         STRB       R6, [R0]
+  0x08002E94:  4859         LDR        R0, =onTimeCounterGN     ; [PC, #0x0164] [0x08002FFC] =0x200006A4 
+  0x08002E96:  6006         STR        R6, [R0]
+  0x08002E98:  981E         LDR        R0, [SP, #120]
+  0x08002E9A:  6108         STR        R0, [R1, #16]
+  0x08002E9C:  4858         LDR        R0, =offTimeCounterRT    ; [PC, #0x0160] [0x08003000] =0x200006B0 
+  0x08002E9E:  6006         STR        R6, [R0]
+  0x08002EA0:  4847         LDR        R0, =blinkModeRT         ; [PC, #0x011C] [0x08002FC0] =0x20000754 
+  0x08002EA2:  7006         STRB       R6, [R0]
+  0x08002EA4:  484A         LDR        R0, =onTimeCounterRT     ; [PC, #0x0128] [0x08002FD0] =0x2000069C 
+  0x08002EA6:  6006         STR        R6, [R0]
+  0x08002EA8:  4858         LDR        R0, =0x080064D9          ; [PC, #0x0160] [0x0800300C] 
+  0x08002EAA:  F002 F9A1    BL         puts                     ; 0x080051F0
+  0x08002EAE:  7026         STRB       R6, [R4]
+  0x08002EB0:  F001 F930    BL         .L252                    ; 0x08004114
+  0x08002EB4:  483E         LDR        R0, =0x50000410          ; [PC, #248] [0x08002FB0] 
+  0x08002EB6:  6801         LDR        R1, [R0]
+  0x08002EB8:  4E3E         LDR        R6, =buttonState         ; [PC, #248] [0x08002FB4] =0x2000073A 
+  0x08002EBA:  7830         LDRB       R0, [R6]
+  0x08002EBC:  2801         CMP        R0, #1
+  0x08002EBE:  D001         BEQ        .L169                    ; 0x08002EC4
+  0x08002EC0:  F000 FECF    BL         .L227                    ; 0x08003C62
+
.L169:
+  0x08002EC4:  0748         LSLS       R0, R1, #29
+  0x08002EC6:  D501         BPL        .L170                    ; 0x08002ECC
+  0x08002EC8:  F000 FEA2    BL         .L226                    ; 0x08003C10
+
.L170:
+  0x08002ECC:  4838         LDR        R0, =0x50000410          ; [PC, #224] [0x08002FB0] 
+  0x08002ECE:  9920         LDR        R1, [SP, #128]
+  0x08002ED0:  6081         STR        R1, [R0, #8]
+  0x08002ED2:  2000         MOVS       R0, #0
+  0x08002ED4:  7030         STRB       R0, [R6]
+  0x08002ED6:  4845         LDR        R0, =onTimeCounter       ; [PC, #0x0114] [0x08002FEC] =0x200006A8 
+  0x08002ED8:  9909         LDR        R1, [SP, #36]
+  0x08002EDA:  6001         STR        R1, [R0]
+  0x08002EDC:  F001 F91A    BL         .L252                    ; 0x08004114
+  0x08002EE0:  4833         LDR        R0, =0x50000410          ; [PC, #204] [0x08002FB0] 
+  0x08002EE2:  6801         LDR        R1, [R0]
+  0x08002EE4:  4E33         LDR        R6, =buttonState         ; [PC, #204] [0x08002FB4] =0x2000073A 
+  0x08002EE6:  7830         LDRB       R0, [R6]
+  0x08002EE8:  2801         CMP        R0, #1
+  0x08002EEA:  D12A         BNE        .L172                    ; 0x08002F42
+  0x08002EEC:  0748         LSLS       R0, R1, #29
+  0x08002EEE:  D400         BMI        .L171                    ; 0x08002EF2
+  0x08002EF0:  E37C         B          .L192                    ; 0x080035EC
+
.L171:
+  0x08002EF2:  492F         LDR        R1, =0x50000410          ; [PC, #188] [0x08002FB0] 
+  0x08002EF4:  981A         LDR        R0, [SP, #104]
+  0x08002EF6:  6188         STR        R0, [R1, #24]
+  0x08002EF8:  981B         LDR        R0, [SP, #108]
+  0x08002EFA:  6088         STR        R0, [R1, #8]
+  0x08002EFC:  4837         LDR        R0, =relaisState         ; [PC, #220] [0x08002FDC] =0x20000730 
+  0x08002EFE:  7005         STRB       R5, [R0]
+  0x08002F00:  4843         LDR        R0, =onTimeCounterSET    ; [PC, #0x010C] [0x08003010] =0x20000698 
+  0x08002F02:  9A16         LDR        R2, [SP, #88]
+  0x08002F04:  6002         STR        R2, [R0]
+  0x08002F06:  9820         LDR        R0, [SP, #128]
+  0x08002F08:  6088         STR        R0, [R1, #8]
+  0x08002F0A:  4842         LDR        R0, =onTimeGN            ; [PC, #0x0108] [0x08003014] =0x20000740 
+  0x08002F0C:  7005         STRB       R5, [R0]
+  0x08002F0E:  4837         LDR        R0, =onTimeCounter       ; [PC, #220] [0x08002FEC] =0x200006A8 
+  0x08002F10:  21C8         MOVS       R1, #200
+  0x08002F12:  6001         STR        R1, [R0]
+  0x08002F14:  4840         LDR        R0, =offTimeGN           ; [PC, #0x0100] [0x08003018] =0x2000074C 
+  0x08002F16:  7005         STRB       R5, [R0]
+  0x08002F18:  4837         LDR        R0, =blinkModeGN         ; [PC, #220] [0x08002FF8] =0x20000758 
+  0x08002F1A:  7005         STRB       R5, [R0]
+  0x08002F1C:  4A34         LDR        R2, =0x50000818          ; [PC, #208] [0x08002FF0] 
+  0x08002F1E:  981F         LDR        R0, [SP, #124]
+  0x08002F20:  6010         STR        R0, [R2]
+  0x08002F22:  4836         LDR        R0, =onTimeCounterGN     ; [PC, #216] [0x08002FFC] =0x200006A4 
+  0x08002F24:  6001         STR        R1, [R0]
+  0x08002F26:  981E         LDR        R0, [SP, #120]
+  0x08002F28:  6110         STR        R0, [R2, #16]
+  0x08002F2A:  4835         LDR        R0, =offTimeCounterRT    ; [PC, #212] [0x08003000] =0x200006B0 
+  0x08002F2C:  2100         MOVS       R1, #0
+  0x08002F2E:  6001         STR        R1, [R0]
+  0x08002F30:  4823         LDR        R0, =blinkModeRT         ; [PC, #140] [0x08002FC0] =0x20000754 
+  0x08002F32:  7001         STRB       R1, [R0]
+  0x08002F34:  4826         LDR        R0, =onTimeCounterRT     ; [PC, #152] [0x08002FD0] =0x2000069C 
+  0x08002F36:  6001         STR        R1, [R0]
+  0x08002F38:  4838         LDR        R0, =0x080066E6          ; [PC, #224] [0x0800301C] 
+  0x08002F3A:  F002 F959    BL         puts                     ; 0x080051F0
+  0x08002F3E:  7025         STRB       R5, [R4]
+  0x08002F40:  7830         LDRB       R0, [R6]
+
.L172:
+  0x08002F42:  2802         CMP        R0, #2
+  0x08002F44:  D001         BEQ        .L173                    ; 0x08002F4A
+  0x08002F46:  F001 F8E5    BL         .L252                    ; 0x08004114
+
.L173:
+  0x08002F4A:  4919         LDR        R1, =0x50000410          ; [PC, #100] [0x08002FB0] 
+  0x08002F4C:  981A         LDR        R0, [SP, #104]
+  0x08002F4E:  6188         STR        R0, [R1, #24]
+  0x08002F50:  981B         LDR        R0, [SP, #108]
+  0x08002F52:  6088         STR        R0, [R1, #8]
+  0x08002F54:  4821         LDR        R0, =relaisState         ; [PC, #132] [0x08002FDC] =0x20000730 
+  0x08002F56:  7005         STRB       R5, [R0]
+  0x08002F58:  482D         LDR        R0, =onTimeCounterSET    ; [PC, #180] [0x08003010] =0x20000698 
+  0x08002F5A:  9A16         LDR        R2, [SP, #88]
+  0x08002F5C:  6002         STR        R2, [R0]
+  0x08002F5E:  4830         LDR        R0, =onTime              ; [PC, #192] [0x08003020] =0x20000744 
+  0x08002F60:  7005         STRB       R5, [R0]
+  0x08002F62:  4830         LDR        R0, =offTime             ; [PC, #192] [0x08003024] =0x20000750 
+  0x08002F64:  7005         STRB       R5, [R0]
+  0x08002F66:  4820         LDR        R0, =alarmMode           ; [PC, #128] [0x08002FE8] =0x2000075C 
+  0x08002F68:  7005         STRB       R5, [R0]
+  0x08002F6A:  9820         LDR        R0, [SP, #128]
+  0x08002F6C:  6088         STR        R0, [R1, #8]
+  0x08002F6E:  491F         LDR        R1, =onTimeCounter       ; [PC, #124] [0x08002FEC] =0x200006A8 
+  0x08002F70:  20C8         MOVS       R0, #200
+  0x08002F72:  6008         STR        R0, [R1]
+  0x08002F74:  4B1E         LDR        R3, =0x50000818          ; [PC, #120] [0x08002FF0] 
+  0x08002F76:  991F         LDR        R1, [SP, #124]
+  0x08002F78:  6019         STR        R1, [R3]
+  0x08002F7A:  4920         LDR        R1, =onTimeCounterGN     ; [PC, #128] [0x08002FFC] =0x200006A4 
+  0x08002F7C:  2200         MOVS       R2, #0
+  0x08002F7E:  600A         STR        R2, [R1]
+  0x08002F80:  491D         LDR        R1, =blinkModeGN         ; [PC, #116] [0x08002FF8] =0x20000758 
+  0x08002F82:  700A         STRB       R2, [R1]
+  0x08002F84:  491B         LDR        R1, =offTimeCounterGN    ; [PC, #108] [0x08002FF4] =0x200006B4 
+  0x08002F86:  600A         STR        R2, [R1]
+  0x08002F88:  9E1E         LDR        R6, [SP, #120]
+  0x08002F8A:  611E         STR        R6, [R3, #16]
+  0x08002F8C:  490A         LDR        R1, =onTimeRT            ; [PC, #40] [0x08002FB8] =0x2000073C 
+  0x08002F8E:  700D         STRB       R5, [R1]
+  0x08002F90:  491B         LDR        R1, =offTimeCounterRT    ; [PC, #108] [0x08003000] =0x200006B0 
+  0x08002F92:  600A         STR        R2, [R1]
+  0x08002F94:  4909         LDR        R1, =offTimeRT           ; [PC, #36] [0x08002FBC] =0x20000748 
+  0x08002F96:  700D         STRB       R5, [R1]
+  0x08002F98:  4909         LDR        R1, =blinkModeRT         ; [PC, #36] [0x08002FC0] =0x20000754 
+  0x08002F9A:  700D         STRB       R5, [R1]
+  0x08002F9C:  4909         LDR        R1, =numberOfBlinks      ; [PC, #36] [0x08002FC4] =0x200006BC 
+  0x08002F9E:  600D         STR        R5, [R1]
+  0x08002FA0:  4909         LDR        R1, =blinkCounter        ; [PC, #36] [0x08002FC8] =0x200006EC 
+  0x08002FA2:  600D         STR        R5, [R1]
+  0x08002FA4:  490B         LDR        R1, =pauseTime           ; [PC, #44] [0x08002FD4] =0x20000734 
+  0x08002FA6:  700D         STRB       R5, [R1]
+  0x08002FA8:  601E         STR        R6, [R3]
+  0x08002FAA:  F000 FF99    BL         .L238                    ; 0x08003EE0
+  0x08002FAE:  46C0         NOP
+  0x08002FB0:  50000410     DC.W       0x50000410
+  0x08002FB4:  2000073A     DC.W       buttonState
+  0x08002FB8:  2000073C     DC.W       onTimeRT
+  0x08002FBC:  20000748     DC.W       offTimeRT
+  0x08002FC0:  20000754     DC.W       blinkModeRT
+  0x08002FC4:  200006BC     DC.W       numberOfBlinks
+  0x08002FC8:  200006EC     DC.W       blinkCounter
+  0x08002FCC:  08006617     DC.W       08006617               ; R_ARM_ABS32
+  0x08002FD0:  2000069C     DC.W       onTimeCounterRT
+  0x08002FD4:  20000734     DC.W       pauseTime
+  0x08002FD8:  080065BA     DC.W       080065BA               ; R_ARM_ABS32
+  0x08002FDC:  20000730     DC.W       relaisState
+  0x08002FE0:  200006A0     DC.W       onTimeCounterRESET
+  0x08002FE4:  200006B8     DC.W       offTimeCounter
+  0x08002FE8:  2000075C     DC.W       alarmMode
+  0x08002FEC:  200006A8     DC.W       onTimeCounter
+  0x08002FF0:  50000818     DC.W       0x50000818
+  0x08002FF4:  200006B4     DC.W       offTimeCounterGN
+  0x08002FF8:  20000758     DC.W       blinkModeGN
+  0x08002FFC:  200006A4     DC.W       onTimeCounterGN
+  0x08003000:  200006B0     DC.W       offTimeCounterRT
+  0x08003004:  080062F6     DC.W       080062F6               ; R_ARM_ABS32
+  0x08003008:  20000733     DC.W       smState.145
+  0x0800300C:  080064D9     DC.W       080064D9               ; R_ARM_ABS32
+  0x08003010:  20000698     DC.W       onTimeCounterSET
+  0x08003014:  20000740     DC.W       onTimeGN
+  0x08003018:  2000074C     DC.W       offTimeGN
+  0x0800301C:  080066E6     DC.W       080066E6               ; R_ARM_ABS32
+  0x08003020:  20000744     DC.W       onTime
+  0x08003024:  20000750     DC.W       offTime
+  0x08003028:  48F3         LDR        R0, =0x50000410          ; [PC, #0x03CC] [0x080033F8] 
+  0x0800302A:  6800         LDR        R0, [R0]
+  0x0800302C:  49F3         LDR        R1, =0x50000010          ; [PC, #0x03CC] [0x080033FC] 
+  0x0800302E:  6809         LDR        R1, [R1]
+  0x08003030:  0789         LSLS       R1, R1, #30
+  0x08003032:  D403         BMI        .L174                    ; 0x0800303C
+  0x08003034:  49F1         LDR        R1, =0x50000010          ; [PC, #0x03C4] [0x080033FC] 
+  0x08003036:  6809         LDR        R1, [R1]
+  0x08003038:  0789         LSLS       R1, R1, #30
+  0x0800303A:  D517         BPL        .L177                    ; 0x0800306C
+
.L174:
+  0x0800303C:  49F0         LDR        R1, =OVP_SM_On.oldtime   ; [PC, #0x03C0] [0x08003400] =0x2000071C 
+  0x0800303E:  680A         LDR        R2, [R1]
+  0x08003040:  4BF0         LDR        R3, =uwTick              ; [PC, #0x03C0] [0x08003404] =0x2000068C 
+  0x08003042:  681B         LDR        R3, [R3]
+  0x08003044:  4293         CMP        R3, R2
+  0x08003046:  D011         BEQ        .L177                    ; 0x0800306C
+  0x08003048:  4AEF         LDR        R2, =OVP_SM_On.ovpTimeCounter ; [PC, #0x03BC] [0x08003408] =0x20000718 
+  0x0800304A:  6813         LDR        R3, [R2]
+  0x0800304C:  4EEF         LDR        R6, =0x00001388          ; [PC, #0x03BC] [0x0800340C] 
+  0x0800304E:  42B3         CMP        R3, R6
+  0x08003050:  DA05         BGE        .L175                    ; 0x0800305E
+  0x08003052:  1C5E         ADDS       R6, R3, #1
+  0x08003054:  6016         STR        R6, [R2]
+  0x08003056:  4EED         LDR        R6, =0x00001388          ; [PC, #0x03B4] [0x0800340C] 
+  0x08003058:  1E76         SUBS       R6, R6, #1
+  0x0800305A:  42B3         CMP        R3, R6
+  0x0800305C:  D103         BNE        .L176                    ; 0x08003066
+
.L175:
+  0x0800305E:  2300         MOVS       R3, #0
+  0x08003060:  6013         STR        R3, [R2]
+  0x08003062:  4AEB         LDR        R2, =OVP_SM_On.ovpInput  ; [PC, #0x03AC] [0x08003410] =0x20000760 
+  0x08003064:  7015         STRB       R5, [R2]
+
.L176:
+  0x08003066:  4AE7         LDR        R2, =uwTick              ; [PC, #0x039C] [0x08003404] =0x2000068C 
+  0x08003068:  6812         LDR        R2, [R2]
+  0x0800306A:  600A         STR        R2, [R1]
+
.L177:
+  0x0800306C:  49E3         LDR        R1, =0x50000010          ; [PC, #0x038C] [0x080033FC] 
+  0x0800306E:  6809         LDR        R1, [R1]
+  0x08003070:  0789         LSLS       R1, R1, #30
+  0x08003072:  D404         BMI        .L178                    ; 0x0800307E
+  0x08003074:  49E4         LDR        R1, =OVP_SM_On.ovpTimeCounter ; [PC, #0x0390] [0x08003408] =0x20000718 
+  0x08003076:  2200         MOVS       R2, #0
+  0x08003078:  600A         STR        R2, [R1]
+  0x0800307A:  49E5         LDR        R1, =OVP_SM_On.ovpInput  ; [PC, #0x0394] [0x08003410] =0x20000760 
+  0x0800307C:  700A         STRB       R2, [R1]
+
.L178:
+  0x0800307E:  990F         LDR        R1, [SP, #60]
+  0x08003080:  4008         ANDS       R0, R1
+  0x08003082:  D134         BNE        .L179                    ; 0x080030EE
+  0x08003084:  4ADC         LDR        R2, =0x50000410          ; [PC, #0x0370] [0x080033F8] 
+  0x08003086:  981B         LDR        R0, [SP, #108]
+  0x08003088:  6190         STR        R0, [R2, #24]
+  0x0800308A:  981A         LDR        R0, [SP, #104]
+  0x0800308C:  6090         STR        R0, [R2, #8]
+  0x0800308E:  49E1         LDR        R1, =relaisState         ; [PC, #0x0384] [0x08003414] =0x20000730 
+  0x08003090:  2000         MOVS       R0, #0
+  0x08003092:  7008         STRB       R0, [R1]
+  0x08003094:  49E0         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0380] [0x08003418] =0x200006A0 
+  0x08003096:  9B16         LDR        R3, [SP, #88]
+  0x08003098:  600B         STR        R3, [R1]
+  0x0800309A:  9920         LDR        R1, [SP, #128]
+  0x0800309C:  6091         STR        R1, [R2, #8]
+  0x0800309E:  49DF         LDR        R1, =onTimeCounter       ; [PC, #0x037C] [0x0800341C] =0x200006A8 
+  0x080030A0:  9A09         LDR        R2, [SP, #36]
+  0x080030A2:  600A         STR        R2, [R1]
+  0x080030A4:  4ADE         LDR        R2, =0x50000818          ; [PC, #0x0378] [0x08003420] 
+  0x080030A6:  991F         LDR        R1, [SP, #124]
+  0x080030A8:  6111         STR        R1, [R2, #16]
+  0x080030AA:  49DE         LDR        R1, =offTimeCounterGN    ; [PC, #0x0378] [0x08003424] =0x200006B4 
+  0x080030AC:  6008         STR        R0, [R1]
+  0x080030AE:  49DE         LDR        R1, =blinkModeGN         ; [PC, #0x0378] [0x08003428] =0x20000758 
+  0x080030B0:  7008         STRB       R0, [R1]
+  0x080030B2:  49DE         LDR        R1, =onTimeCounterGN     ; [PC, #0x0378] [0x0800342C] =0x200006A4 
+  0x080030B4:  6008         STR        R0, [R1]
+  0x080030B6:  49DE         LDR        R1, =onTimeRT            ; [PC, #0x0378] [0x08003430] =0x2000073C 
+  0x080030B8:  700D         STRB       R5, [R1]
+  0x080030BA:  49DE         LDR        R1, =offTimeRT           ; [PC, #0x0378] [0x08003434] =0x20000748 
+  0x080030BC:  700D         STRB       R5, [R1]
+  0x080030BE:  49DE         LDR        R1, =blinkModeRT         ; [PC, #0x0378] [0x08003438] =0x20000754 
+  0x080030C0:  700D         STRB       R5, [R1]
+  0x080030C2:  49DE         LDR        R1, =numberOfBlinks      ; [PC, #0x0378] [0x0800343C] =0x200006BC 
+  0x080030C4:  9E15         LDR        R6, [SP, #84]
+  0x080030C6:  600E         STR        R6, [R1]
+  0x080030C8:  49DD         LDR        R1, =blinkCounter        ; [PC, #0x0374] [0x08003440] =0x200006EC 
+  0x080030CA:  600E         STR        R6, [R1]
+  0x080030CC:  49DD         LDR        R1, =pauseTime           ; [PC, #0x0374] [0x08003444] =0x20000734 
+  0x080030CE:  700D         STRB       R5, [R1]
+  0x080030D0:  991E         LDR        R1, [SP, #120]
+  0x080030D2:  6011         STR        R1, [R2]
+  0x080030D4:  49DC         LDR        R1, =buttonState         ; [PC, #0x0370] [0x08003448] =0x2000073A 
+  0x080030D6:  7008         STRB       R0, [R1]
+  0x080030D8:  48DC         LDR        R0, =onTimeCounterRT     ; [PC, #0x0370] [0x0800344C] =0x2000069C 
+  0x080030DA:  21C8         MOVS       R1, #200
+  0x080030DC:  6001         STR        R1, [R0]
+  0x080030DE:  48DC         LDR        R0, =0x0800698C          ; [PC, #0x0370] [0x08003450] 
+  0x080030E0:  F002 F886    BL         puts                     ; 0x080051F0
+  0x080030E4:  48DB         LDR        R0, =0x0800672C          ; [PC, #0x036C] [0x08003454] 
+  0x080030E6:  F002 F883    BL         puts                     ; 0x080051F0
+  0x080030EA:  48DB         LDR        R0, =smState.145         ; [PC, #0x036C] [0x08003458] =0x20000733 
+  0x080030EC:  7006         STRB       R6, [R0]
+
.L179:
+  0x080030EE:  48DB         LDR        R0, =temp                ; [PC, #0x036C] [0x0800345C] =0x20000690 
+  0x080030F0:  6800         LDR        R0, [R0]
+  0x080030F2:  2851         CMP        R0, #81
+  0x080030F4:  DB32         BLT        .L180                    ; 0x0800315C
+  0x080030F6:  4AC0         LDR        R2, =0x50000410          ; [PC, #0x0300] [0x080033F8] 
+  0x080030F8:  981B         LDR        R0, [SP, #108]
+  0x080030FA:  6190         STR        R0, [R2, #24]
+  0x080030FC:  981A         LDR        R0, [SP, #104]
+  0x080030FE:  6090         STR        R0, [R2, #8]
+  0x08003100:  49C4         LDR        R1, =relaisState         ; [PC, #0x0310] [0x08003414] =0x20000730 
+  0x08003102:  2000         MOVS       R0, #0
+  0x08003104:  7008         STRB       R0, [R1]
+  0x08003106:  49C4         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0310] [0x08003418] =0x200006A0 
+  0x08003108:  9B16         LDR        R3, [SP, #88]
+  0x0800310A:  600B         STR        R3, [R1]
+  0x0800310C:  9920         LDR        R1, [SP, #128]
+  0x0800310E:  6091         STR        R1, [R2, #8]
+  0x08003110:  49C2         LDR        R1, =onTimeCounter       ; [PC, #0x0308] [0x0800341C] =0x200006A8 
+  0x08003112:  9A09         LDR        R2, [SP, #36]
+  0x08003114:  600A         STR        R2, [R1]
+  0x08003116:  4BC2         LDR        R3, =0x50000818          ; [PC, #0x0308] [0x08003420] 
+  0x08003118:  991F         LDR        R1, [SP, #124]
+  0x0800311A:  6119         STR        R1, [R3, #16]
+  0x0800311C:  49C1         LDR        R1, =offTimeCounterGN    ; [PC, #0x0304] [0x08003424] =0x200006B4 
+  0x0800311E:  6008         STR        R0, [R1]
+  0x08003120:  49C1         LDR        R1, =blinkModeGN         ; [PC, #0x0304] [0x08003428] =0x20000758 
+  0x08003122:  7008         STRB       R0, [R1]
+  0x08003124:  49C1         LDR        R1, =onTimeCounterGN     ; [PC, #0x0304] [0x0800342C] =0x200006A4 
+  0x08003126:  6008         STR        R0, [R1]
+  0x08003128:  49C1         LDR        R1, =onTimeRT            ; [PC, #0x0304] [0x08003430] =0x2000073C 
+  0x0800312A:  700D         STRB       R5, [R1]
+  0x0800312C:  49C1         LDR        R1, =offTimeRT           ; [PC, #0x0304] [0x08003434] =0x20000748 
+  0x0800312E:  700D         STRB       R5, [R1]
+  0x08003130:  49C1         LDR        R1, =blinkModeRT         ; [PC, #0x0304] [0x08003438] =0x20000754 
+  0x08003132:  700D         STRB       R5, [R1]
+  0x08003134:  49C1         LDR        R1, =numberOfBlinks      ; [PC, #0x0304] [0x0800343C] =0x200006BC 
+  0x08003136:  2205         MOVS       R2, #5
+  0x08003138:  600A         STR        R2, [R1]
+  0x0800313A:  49C1         LDR        R1, =blinkCounter        ; [PC, #0x0304] [0x08003440] =0x200006EC 
+  0x0800313C:  600A         STR        R2, [R1]
+  0x0800313E:  49C1         LDR        R1, =pauseTime           ; [PC, #0x0304] [0x08003444] =0x20000734 
+  0x08003140:  700D         STRB       R5, [R1]
+  0x08003142:  991E         LDR        R1, [SP, #120]
+  0x08003144:  6019         STR        R1, [R3]
+  0x08003146:  49C0         LDR        R1, =buttonState         ; [PC, #0x0300] [0x08003448] =0x2000073A 
+  0x08003148:  7008         STRB       R0, [R1]
+  0x0800314A:  48C0         LDR        R0, =onTimeCounterRT     ; [PC, #0x0300] [0x0800344C] =0x2000069C 
+  0x0800314C:  21C8         MOVS       R1, #200
+  0x0800314E:  6001         STR        R1, [R0]
+  0x08003150:  48C3         LDR        R0, =0x0800632C          ; [PC, #0x030C] [0x08003460] 
+  0x08003152:  F002 F84D    BL         puts                     ; 0x080051F0
+  0x08003156:  9815         LDR        R0, [SP, #84]
+  0x08003158:  49BF         LDR        R1, =smState.145         ; [PC, #0x02FC] [0x08003458] =0x20000733 
+  0x0800315A:  7008         STRB       R0, [R1]
+
.L180:
+  0x0800315C:  48AC         LDR        R0, =OVP_SM_On.ovpInput  ; [PC, #0x02B0] [0x08003410] =0x20000760 
+  0x0800315E:  4EAD         LDR        R6, =relaisState         ; [PC, #0x02B4] [0x08003414] =0x20000730 
+  0x08003160:  7800         LDRB       R0, [R0]
+  0x08003162:  2801         CMP        R0, #1
+  0x08003164:  7830         LDRB       R0, [R6]
+  0x08003166:  D124         BNE        .L181                    ; 0x080031B2
+  0x08003168:  2800         CMP        R0, #0
+  0x0800316A:  D048         BEQ        .L182                    ; 0x080031FE
+  0x0800316C:  4AA2         LDR        R2, =0x50000410          ; [PC, #0x0288] [0x080033F8] 
+  0x0800316E:  981B         LDR        R0, [SP, #108]
+  0x08003170:  6190         STR        R0, [R2, #24]
+  0x08003172:  981A         LDR        R0, [SP, #104]
+  0x08003174:  6090         STR        R0, [R2, #8]
+  0x08003176:  2000         MOVS       R0, #0
+  0x08003178:  7030         STRB       R0, [R6]
+  0x0800317A:  49A7         LDR        R1, =onTimeCounterRESET  ; [PC, #0x029C] [0x08003418] =0x200006A0 
+  0x0800317C:  9B16         LDR        R3, [SP, #88]
+  0x0800317E:  600B         STR        R3, [R1]
+  0x08003180:  9920         LDR        R1, [SP, #128]
+  0x08003182:  6091         STR        R1, [R2, #8]
+  0x08003184:  49A5         LDR        R1, =onTimeCounter       ; [PC, #0x0294] [0x0800341C] =0x200006A8 
+  0x08003186:  9A09         LDR        R2, [SP, #36]
+  0x08003188:  600A         STR        R2, [R1]
+  0x0800318A:  49A5         LDR        R1, =0x50000818          ; [PC, #0x0294] [0x08003420] 
+  0x0800318C:  9A1F         LDR        R2, [SP, #124]
+  0x0800318E:  610A         STR        R2, [R1, #16]
+  0x08003190:  49A4         LDR        R1, =offTimeCounterGN    ; [PC, #0x0290] [0x08003424] =0x200006B4 
+  0x08003192:  6008         STR        R0, [R1]
+  0x08003194:  49A4         LDR        R1, =blinkModeGN         ; [PC, #0x0290] [0x08003428] =0x20000758 
+  0x08003196:  7008         STRB       R0, [R1]
+  0x08003198:  49A4         LDR        R1, =onTimeCounterGN     ; [PC, #0x0290] [0x0800342C] =0x200006A4 
+  0x0800319A:  6008         STR        R0, [R1]
+  0x0800319C:  48B1         LDR        R0, =0x08006741          ; [PC, #0x02C4] [0x08003464] 
+  0x0800319E:  F002 F827    BL         puts                     ; 0x080051F0
+  0x080031A2:  48B1         LDR        R0, =0x080062D3          ; [PC, #0x02C4] [0x08003468] 
+  0x080031A4:  F002 F824    BL         puts                     ; 0x080051F0
+  0x080031A8:  4899         LDR        R0, =OVP_SM_On.ovpInput  ; [PC, #0x0264] [0x08003410] =0x20000760 
+  0x080031AA:  7800         LDRB       R0, [R0]
+  0x080031AC:  2800         CMP        R0, #0
+  0x080031AE:  D126         BNE        .L182                    ; 0x080031FE
+  0x080031B0:  7830         LDRB       R0, [R6]
+
.L181:
+  0x080031B2:  2800         CMP        R0, #0
+  0x080031B4:  D123         BNE        .L182                    ; 0x080031FE
+  0x080031B6:  4990         LDR        R1, =0x50000410          ; [PC, #0x0240] [0x080033F8] 
+  0x080031B8:  981A         LDR        R0, [SP, #104]
+  0x080031BA:  6188         STR        R0, [R1, #24]
+  0x080031BC:  981B         LDR        R0, [SP, #108]
+  0x080031BE:  6088         STR        R0, [R1, #8]
+  0x080031C0:  7035         STRB       R5, [R6]
+  0x080031C2:  48AA         LDR        R0, =onTimeCounterSET    ; [PC, #0x02A8] [0x0800346C] =0x20000698 
+  0x080031C4:  9A16         LDR        R2, [SP, #88]
+  0x080031C6:  6002         STR        R2, [R0]
+  0x080031C8:  9820         LDR        R0, [SP, #128]
+  0x080031CA:  6088         STR        R0, [R1, #8]
+  0x080031CC:  4893         LDR        R0, =onTimeCounter       ; [PC, #0x024C] [0x0800341C] =0x200006A8 
+  0x080031CE:  21C8         MOVS       R1, #200
+  0x080031D0:  6001         STR        R1, [R0]
+  0x080031D2:  4B93         LDR        R3, =0x50000818          ; [PC, #0x024C] [0x08003420] 
+  0x080031D4:  9F1F         LDR        R7, [SP, #124]
+  0x080031D6:  611F         STR        R7, [R3, #16]
+  0x080031D8:  48A5         LDR        R0, =onTimeGN            ; [PC, #0x0294] [0x08003470] =0x20000740 
+  0x080031DA:  7005         STRB       R5, [R0]
+  0x080031DC:  4891         LDR        R0, =offTimeCounterGN    ; [PC, #0x0244] [0x08003424] =0x200006B4 
+  0x080031DE:  2200         MOVS       R2, #0
+  0x080031E0:  6002         STR        R2, [R0]
+  0x080031E2:  48A4         LDR        R0, =offTimeGN           ; [PC, #0x0290] [0x08003474] =0x2000074C 
+  0x080031E4:  7005         STRB       R5, [R0]
+  0x080031E6:  4890         LDR        R0, =blinkModeGN         ; [PC, #0x0240] [0x08003428] =0x20000758 
+  0x080031E8:  7005         STRB       R5, [R0]
+  0x080031EA:  601F         STR        R7, [R3]
+  0x080031EC:  4627         MOV        R7, R4
+  0x080031EE:  488F         LDR        R0, =onTimeCounterGN     ; [PC, #0x023C] [0x0800342C] =0x200006A4 
+  0x080031F0:  6001         STR        R1, [R0]
+  0x080031F2:  48A1         LDR        R0, =0x08006948          ; [PC, #0x0284] [0x08003478] 
+  0x080031F4:  F001 FFFC    BL         puts                     ; 0x080051F0
+  0x080031F8:  48A0         LDR        R0, =0x08006511          ; [PC, #0x0280] [0x0800347C] 
+  0x080031FA:  F001 FFF9    BL         puts                     ; 0x080051F0
+
.L182:
+  0x080031FE:  4892         LDR        R0, =buttonState         ; [PC, #0x0248] [0x08003448] =0x2000073A 
+  0x08003200:  7800         LDRB       R0, [R0]
+  0x08003202:  2800         CMP        R0, #0
+  0x08003204:  D001         BEQ        .L183                    ; 0x0800320A
+  0x08003206:  F000 FF85    BL         .L252                    ; 0x08004114
+
.L183:
+  0x0800320A:  497B         LDR        R1, =0x50000410          ; [PC, #0x01EC] [0x080033F8] 
+  0x0800320C:  981B         LDR        R0, [SP, #108]
+  0x0800320E:  6188         STR        R0, [R1, #24]
+  0x08003210:  981A         LDR        R0, [SP, #104]
+  0x08003212:  6088         STR        R0, [R1, #8]
+  0x08003214:  2700         MOVS       R7, #0
+  0x08003216:  7037         STRB       R7, [R6]
+  0x08003218:  487F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01FC] [0x08003418] =0x200006A0 
+  0x0800321A:  9A16         LDR        R2, [SP, #88]
+  0x0800321C:  6002         STR        R2, [R0]
+  0x0800321E:  9820         LDR        R0, [SP, #128]
+  0x08003220:  6088         STR        R0, [R1, #8]
+  0x08003222:  487E         LDR        R0, =onTimeCounter       ; [PC, #0x01F8] [0x0800341C] =0x200006A8 
+  0x08003224:  21C8         MOVS       R1, #200
+  0x08003226:  6001         STR        R1, [R0]
+  0x08003228:  497D         LDR        R1, =0x50000818          ; [PC, #0x01F4] [0x08003420] 
+  0x0800322A:  981F         LDR        R0, [SP, #124]
+  0x0800322C:  6108         STR        R0, [R1, #16]
+  0x0800322E:  487D         LDR        R0, =offTimeCounterGN    ; [PC, #0x01F4] [0x08003424] =0x200006B4 
+  0x08003230:  6007         STR        R7, [R0]
+  0x08003232:  487D         LDR        R0, =blinkModeGN         ; [PC, #0x01F4] [0x08003428] =0x20000758 
+  0x08003234:  7007         STRB       R7, [R0]
+  0x08003236:  487D         LDR        R0, =onTimeCounterGN     ; [PC, #0x01F4] [0x0800342C] =0x200006A4 
+  0x08003238:  6007         STR        R7, [R0]
+  0x0800323A:  981E         LDR        R0, [SP, #120]
+  0x0800323C:  6108         STR        R0, [R1, #16]
+  0x0800323E:  4890         LDR        R0, =offTimeCounterRT    ; [PC, #0x0240] [0x08003480] =0x200006B0 
+  0x08003240:  6007         STR        R7, [R0]
+  0x08003242:  487D         LDR        R0, =blinkModeRT         ; [PC, #0x01F4] [0x08003438] =0x20000754 
+  0x08003244:  7007         STRB       R7, [R0]
+  0x08003246:  4881         LDR        R0, =onTimeCounterRT     ; [PC, #0x0204] [0x0800344C] =0x2000069C 
+  0x08003248:  6007         STR        R7, [R0]
+  0x0800324A:  488E         LDR        R0, =0x080062F6          ; [PC, #0x0238] [0x08003484] 
+  0x0800324C:  F001 FFD0    BL         puts                     ; 0x080051F0
+  0x08003250:  4881         LDR        R0, =smState.145         ; [PC, #0x0204] [0x08003458] =0x20000733 
+  0x08003252:  7007         STRB       R7, [R0]
+  0x08003254:  486C         LDR        R0, =OVP_SM_On.ovpTimeCounter ; [PC, #0x01B0] [0x08003408] =0x20000718 
+  0x08003256:  6007         STR        R7, [R0]
+  0x08003258:  486D         LDR        R0, =OVP_SM_On.ovpInput  ; [PC, #0x01B4] [0x08003410] =0x20000760 
+  0x0800325A:  F000 FC88    BL         .L213                    ; 0x08003B6E
+  0x0800325E:  487A         LDR        R0, =buttonState         ; [PC, #0x01E8] [0x08003448] =0x2000073A 
+  0x08003260:  7800         LDRB       R0, [R0]
+  0x08003262:  2800         CMP        R0, #0
+  0x08003264:  D001         BEQ        .L184                    ; 0x0800326A
+  0x08003266:  F000 FF55    BL         .L252                    ; 0x08004114
+
.L184:
+  0x0800326A:  4963         LDR        R1, =0x50000410          ; [PC, #0x018C] [0x080033F8] 
+  0x0800326C:  981B         LDR        R0, [SP, #108]
+  0x0800326E:  6188         STR        R0, [R1, #24]
+  0x08003270:  981A         LDR        R0, [SP, #104]
+  0x08003272:  6088         STR        R0, [R1, #8]
+  0x08003274:  4867         LDR        R0, =relaisState         ; [PC, #0x019C] [0x08003414] =0x20000730 
+  0x08003276:  2600         MOVS       R6, #0
+  0x08003278:  7006         STRB       R6, [R0]
+  0x0800327A:  4867         LDR        R0, =onTimeCounterRESET  ; [PC, #0x019C] [0x08003418] =0x200006A0 
+  0x0800327C:  9A16         LDR        R2, [SP, #88]
+  0x0800327E:  6002         STR        R2, [R0]
+  0x08003280:  9820         LDR        R0, [SP, #128]
+  0x08003282:  6188         STR        R0, [R1, #24]
+  0x08003284:  4880         LDR        R0, =offTimeCounter      ; [PC, #0x0200] [0x08003488] =0x200006B8 
+  0x08003286:  6006         STR        R6, [R0]
+  0x08003288:  4880         LDR        R0, =alarmMode           ; [PC, #0x0200] [0x0800348C] =0x2000075C 
+  0x0800328A:  7006         STRB       R6, [R0]
+  0x0800328C:  4863         LDR        R0, =onTimeCounter       ; [PC, #0x018C] [0x0800341C] =0x200006A8 
+  0x0800328E:  6006         STR        R6, [R0]
+  0x08003290:  4963         LDR        R1, =0x50000818          ; [PC, #0x018C] [0x08003420] 
+  0x08003292:  981F         LDR        R0, [SP, #124]
+  0x08003294:  6108         STR        R0, [R1, #16]
+  0x08003296:  4863         LDR        R0, =offTimeCounterGN    ; [PC, #0x018C] [0x08003424] =0x200006B4 
+  0x08003298:  6006         STR        R6, [R0]
+  0x0800329A:  4863         LDR        R0, =blinkModeGN         ; [PC, #0x018C] [0x08003428] =0x20000758 
+  0x0800329C:  7006         STRB       R6, [R0]
+  0x0800329E:  4863         LDR        R0, =onTimeCounterGN     ; [PC, #0x018C] [0x0800342C] =0x200006A4 
+  0x080032A0:  6006         STR        R6, [R0]
+  0x080032A2:  981E         LDR        R0, [SP, #120]
+  0x080032A4:  6108         STR        R0, [R1, #16]
+  0x080032A6:  4876         LDR        R0, =offTimeCounterRT    ; [PC, #0x01D8] [0x08003480] =0x200006B0 
+  0x080032A8:  6006         STR        R6, [R0]
+  0x080032AA:  4863         LDR        R0, =blinkModeRT         ; [PC, #0x018C] [0x08003438] =0x20000754 
+  0x080032AC:  7006         STRB       R6, [R0]
+  0x080032AE:  4867         LDR        R0, =onTimeCounterRT     ; [PC, #0x019C] [0x0800344C] =0x2000069C 
+  0x080032B0:  6006         STR        R6, [R0]
+  0x080032B2:  4877         LDR        R0, =0x080062BC          ; [PC, #0x01DC] [0x08003490] 
+  0x080032B4:  F001 FF9C    BL         puts                     ; 0x080051F0
+  0x080032B8:  4876         LDR        R0, =smState.122         ; [PC, #0x01D8] [0x08003494] =0x20000736 
+  0x080032BA:  7006         STRB       R6, [R0]
+  0x080032BC:  F000 FF2A    BL         .L252                    ; 0x08004114
+  0x080032C0:  484D         LDR        R0, =0x50000410          ; [PC, #0x0134] [0x080033F8] 
+  0x080032C2:  6807         LDR        R7, [R0]
+  0x080032C4:  4860         LDR        R0, =buttonState         ; [PC, #0x0180] [0x08003448] =0x2000073A 
+  0x080032C6:  7800         LDRB       R0, [R0]
+  0x080032C8:  2800         CMP        R0, #0
+  0x080032CA:  D124         BNE        .L185                    ; 0x08003316
+  0x080032CC:  494A         LDR        R1, =0x50000410          ; [PC, #0x0128] [0x080033F8] 
+  0x080032CE:  981B         LDR        R0, [SP, #108]
+  0x080032D0:  6188         STR        R0, [R1, #24]
+  0x080032D2:  981A         LDR        R0, [SP, #104]
+  0x080032D4:  6088         STR        R0, [R1, #8]
+  0x080032D6:  484F         LDR        R0, =relaisState         ; [PC, #0x013C] [0x08003414] =0x20000730 
+  0x080032D8:  2600         MOVS       R6, #0
+  0x080032DA:  7006         STRB       R6, [R0]
+  0x080032DC:  484E         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0138] [0x08003418] =0x200006A0 
+  0x080032DE:  9A16         LDR        R2, [SP, #88]
+  0x080032E0:  6002         STR        R2, [R0]
+  0x080032E2:  9820         LDR        R0, [SP, #128]
+  0x080032E4:  6088         STR        R0, [R1, #8]
+  0x080032E6:  484D         LDR        R0, =onTimeCounter       ; [PC, #0x0134] [0x0800341C] =0x200006A8 
+  0x080032E8:  21C8         MOVS       R1, #200
+  0x080032EA:  6001         STR        R1, [R0]
+  0x080032EC:  494C         LDR        R1, =0x50000818          ; [PC, #0x0130] [0x08003420] 
+  0x080032EE:  981F         LDR        R0, [SP, #124]
+  0x080032F0:  6108         STR        R0, [R1, #16]
+  0x080032F2:  484C         LDR        R0, =offTimeCounterGN    ; [PC, #0x0130] [0x08003424] =0x200006B4 
+  0x080032F4:  6006         STR        R6, [R0]
+  0x080032F6:  484C         LDR        R0, =blinkModeGN         ; [PC, #0x0130] [0x08003428] =0x20000758 
+  0x080032F8:  7006         STRB       R6, [R0]
+  0x080032FA:  484C         LDR        R0, =onTimeCounterGN     ; [PC, #0x0130] [0x0800342C] =0x200006A4 
+  0x080032FC:  6006         STR        R6, [R0]
+  0x080032FE:  981E         LDR        R0, [SP, #120]
+  0x08003300:  6108         STR        R0, [R1, #16]
+  0x08003302:  485F         LDR        R0, =offTimeCounterRT    ; [PC, #0x017C] [0x08003480] =0x200006B0 
+  0x08003304:  6006         STR        R6, [R0]
+  0x08003306:  484C         LDR        R0, =blinkModeRT         ; [PC, #0x0130] [0x08003438] =0x20000754 
+  0x08003308:  7006         STRB       R6, [R0]
+  0x0800330A:  4850         LDR        R0, =onTimeCounterRT     ; [PC, #0x0140] [0x0800344C] =0x2000069C 
+  0x0800330C:  6006         STR        R6, [R0]
+  0x0800330E:  4862         LDR        R0, =0x080064D9          ; [PC, #0x0188] [0x08003498] 
+  0x08003310:  F001 FF6E    BL         puts                     ; 0x080051F0
+  0x08003314:  7026         STRB       R6, [R4]
+
.L185:
+  0x08003316:  980F         LDR        R0, [SP, #60]
+  0x08003318:  4007         ANDS       R7, R0
+  0x0800331A:  D130         BNE        .L186                    ; 0x0800337E
+  0x0800331C:  4A36         LDR        R2, =0x50000410          ; [PC, #216] [0x080033F8] 
+  0x0800331E:  981B         LDR        R0, [SP, #108]
+  0x08003320:  6190         STR        R0, [R2, #24]
+  0x08003322:  981A         LDR        R0, [SP, #104]
+  0x08003324:  6090         STR        R0, [R2, #8]
+  0x08003326:  493B         LDR        R1, =relaisState         ; [PC, #236] [0x08003414] =0x20000730 
+  0x08003328:  700F         STRB       R7, [R1]
+  0x0800332A:  493B         LDR        R1, =onTimeCounterRESET  ; [PC, #236] [0x08003418] =0x200006A0 
+  0x0800332C:  9B16         LDR        R3, [SP, #88]
+  0x0800332E:  600B         STR        R3, [R1]
+  0x08003330:  9920         LDR        R1, [SP, #128]
+  0x08003332:  6091         STR        R1, [R2, #8]
+  0x08003334:  9910         LDR        R1, [SP, #64]
+  0x08003336:  31F4         ADDS       R1, #244
+  0x08003338:  4A38         LDR        R2, =onTimeCounter       ; [PC, #224] [0x0800341C] =0x200006A8 
+  0x0800333A:  6011         STR        R1, [R2]
+  0x0800333C:  4A38         LDR        R2, =0x50000818          ; [PC, #224] [0x08003420] 
+  0x0800333E:  991F         LDR        R1, [SP, #124]
+  0x08003340:  6111         STR        R1, [R2, #16]
+  0x08003342:  4938         LDR        R1, =offTimeCounterGN    ; [PC, #224] [0x08003424] =0x200006B4 
+  0x08003344:  600F         STR        R7, [R1]
+  0x08003346:  4938         LDR        R1, =blinkModeGN         ; [PC, #224] [0x08003428] =0x20000758 
+  0x08003348:  700F         STRB       R7, [R1]
+  0x0800334A:  4938         LDR        R1, =onTimeCounterGN     ; [PC, #224] [0x0800342C] =0x200006A4 
+  0x0800334C:  600F         STR        R7, [R1]
+  0x0800334E:  4938         LDR        R1, =onTimeRT            ; [PC, #224] [0x08003430] =0x2000073C 
+  0x08003350:  700D         STRB       R5, [R1]
+  0x08003352:  4938         LDR        R1, =offTimeRT           ; [PC, #224] [0x08003434] =0x20000748 
+  0x08003354:  700D         STRB       R5, [R1]
+  0x08003356:  4938         LDR        R1, =blinkModeRT         ; [PC, #224] [0x08003438] =0x20000754 
+  0x08003358:  700D         STRB       R5, [R1]
+  0x0800335A:  4938         LDR        R1, =numberOfBlinks      ; [PC, #224] [0x0800343C] =0x200006BC 
+  0x0800335C:  2603         MOVS       R6, #3
+  0x0800335E:  600E         STR        R6, [R1]
+  0x08003360:  4937         LDR        R1, =blinkCounter        ; [PC, #220] [0x08003440] =0x200006EC 
+  0x08003362:  600E         STR        R6, [R1]
+  0x08003364:  4937         LDR        R1, =pauseTime           ; [PC, #220] [0x08003444] =0x20000734 
+  0x08003366:  700D         STRB       R5, [R1]
+  0x08003368:  991E         LDR        R1, [SP, #120]
+  0x0800336A:  6011         STR        R1, [R2]
+  0x0800336C:  4936         LDR        R1, =buttonState         ; [PC, #216] [0x08003448] =0x2000073A 
+  0x0800336E:  700F         STRB       R7, [R1]
+  0x08003370:  4836         LDR        R0, =onTimeCounterRT     ; [PC, #216] [0x0800344C] =0x2000069C 
+  0x08003372:  21C8         MOVS       R1, #200
+  0x08003374:  6001         STR        R1, [R0]
+  0x08003376:  4849         LDR        R0, =0x0800690C          ; [PC, #0x0124] [0x0800349C] 
+  0x08003378:  F001 FF3A    BL         puts                     ; 0x080051F0
+  0x0800337C:  7026         STRB       R6, [R4]
+
.L186:
+  0x0800337E:  4837         LDR        R0, =temp                ; [PC, #220] [0x0800345C] =0x20000690 
+  0x08003380:  6800         LDR        R0, [R0]
+  0x08003382:  2851         CMP        R0, #81
+  0x08003384:  4F46         LDR        R7, =0x000003C7          ; [PC, #0x0118] [0x080034A0] 
+  0x08003386:  DA01         BGE        .L187                    ; 0x0800338C
+  0x08003388:  F000 FEC4    BL         .L252                    ; 0x08004114
+
.L187:
+  0x0800338C:  4A1A         LDR        R2, =0x50000410          ; [PC, #104] [0x080033F8] 
+  0x0800338E:  981B         LDR        R0, [SP, #108]
+  0x08003390:  6190         STR        R0, [R2, #24]
+  0x08003392:  981A         LDR        R0, [SP, #104]
+  0x08003394:  6090         STR        R0, [R2, #8]
+  0x08003396:  491F         LDR        R1, =relaisState         ; [PC, #124] [0x08003414] =0x20000730 
+  0x08003398:  2000         MOVS       R0, #0
+  0x0800339A:  7008         STRB       R0, [R1]
+  0x0800339C:  491E         LDR        R1, =onTimeCounterRESET  ; [PC, #120] [0x08003418] =0x200006A0 
+  0x0800339E:  9B16         LDR        R3, [SP, #88]
+  0x080033A0:  600B         STR        R3, [R1]
+  0x080033A2:  9920         LDR        R1, [SP, #128]
+  0x080033A4:  6091         STR        R1, [R2, #8]
+  0x080033A6:  9910         LDR        R1, [SP, #64]
+  0x080033A8:  31F4         ADDS       R1, #244
+  0x080033AA:  4A1C         LDR        R2, =onTimeCounter       ; [PC, #112] [0x0800341C] =0x200006A8 
+  0x080033AC:  6011         STR        R1, [R2]
+  0x080033AE:  4B1C         LDR        R3, =0x50000818          ; [PC, #112] [0x08003420] 
+  0x080033B0:  991F         LDR        R1, [SP, #124]
+  0x080033B2:  6119         STR        R1, [R3, #16]
+  0x080033B4:  491B         LDR        R1, =offTimeCounterGN    ; [PC, #108] [0x08003424] =0x200006B4 
+  0x080033B6:  6008         STR        R0, [R1]
+  0x080033B8:  491B         LDR        R1, =blinkModeGN         ; [PC, #108] [0x08003428] =0x20000758 
+  0x080033BA:  7008         STRB       R0, [R1]
+  0x080033BC:  491B         LDR        R1, =onTimeCounterGN     ; [PC, #108] [0x0800342C] =0x200006A4 
+  0x080033BE:  6008         STR        R0, [R1]
+  0x080033C0:  491B         LDR        R1, =onTimeRT            ; [PC, #108] [0x08003430] =0x2000073C 
+  0x080033C2:  700D         STRB       R5, [R1]
+  0x080033C4:  491B         LDR        R1, =offTimeRT           ; [PC, #108] [0x08003434] =0x20000748 
+  0x080033C6:  700D         STRB       R5, [R1]
+  0x080033C8:  491B         LDR        R1, =blinkModeRT         ; [PC, #108] [0x08003438] =0x20000754 
+  0x080033CA:  700D         STRB       R5, [R1]
+  0x080033CC:  491B         LDR        R1, =numberOfBlinks      ; [PC, #108] [0x0800343C] =0x200006BC 
+  0x080033CE:  2205         MOVS       R2, #5
+  0x080033D0:  600A         STR        R2, [R1]
+  0x080033D2:  491B         LDR        R1, =blinkCounter        ; [PC, #108] [0x08003440] =0x200006EC 
+  0x080033D4:  600A         STR        R2, [R1]
+  0x080033D6:  491B         LDR        R1, =pauseTime           ; [PC, #108] [0x08003444] =0x20000734 
+  0x080033D8:  700D         STRB       R5, [R1]
+  0x080033DA:  991E         LDR        R1, [SP, #120]
+  0x080033DC:  6019         STR        R1, [R3]
+  0x080033DE:  491A         LDR        R1, =buttonState         ; [PC, #104] [0x08003448] =0x2000073A 
+  0x080033E0:  7008         STRB       R0, [R1]
+  0x080033E2:  481A         LDR        R0, =onTimeCounterRT     ; [PC, #104] [0x0800344C] =0x2000069C 
+  0x080033E4:  21C8         MOVS       R1, #200
+  0x080033E6:  6001         STR        R1, [R0]
+  0x080033E8:  481D         LDR        R0, =0x0800632C          ; [PC, #116] [0x08003460] 
+  0x080033EA:  F001 FF01    BL         puts                     ; 0x080051F0
+  0x080033EE:  2003         MOVS       R0, #3
+  0x080033F0:  7020         STRB       R0, [R4]
+  0x080033F2:  F000 FE8F    BL         .L252                    ; 0x08004114
+  0x080033F6:  46C0         NOP
+  0x080033F8:  50000410     DC.W       0x50000410
+  0x080033FC:  50000010     DC.W       0x50000010
+  0x08003400:  2000071C     DC.W       OVP_SM_On.oldtime
+  0x08003404:  2000068C     DC.W       uwTick
+  0x08003408:  20000718     DC.W       OVP_SM_On.ovpTimeCounter
+  0x0800340C:  00001388     DC.W       0x00001388
+  0x08003410:  20000760     DC.W       OVP_SM_On.ovpInput
+  0x08003414:  20000730     DC.W       relaisState
+  0x08003418:  200006A0     DC.W       onTimeCounterRESET
+  0x0800341C:  200006A8     DC.W       onTimeCounter
+  0x08003420:  50000818     DC.W       0x50000818
+  0x08003424:  200006B4     DC.W       offTimeCounterGN
+  0x08003428:  20000758     DC.W       blinkModeGN
+  0x0800342C:  200006A4     DC.W       onTimeCounterGN
+  0x08003430:  2000073C     DC.W       onTimeRT
+  0x08003434:  20000748     DC.W       offTimeRT
+  0x08003438:  20000754     DC.W       blinkModeRT
+  0x0800343C:  200006BC     DC.W       numberOfBlinks
+  0x08003440:  200006EC     DC.W       blinkCounter
+  0x08003444:  20000734     DC.W       pauseTime
+  0x08003448:  2000073A     DC.W       buttonState
+  0x0800344C:  2000069C     DC.W       onTimeCounterRT
+  0x08003450:  0800698C     DC.W       0800698C               ; R_ARM_ABS32
+  0x08003454:  0800672C     DC.W       0800672C               ; R_ARM_ABS32
+  0x08003458:  20000733     DC.W       smState.145
+  0x0800345C:  20000690     DC.W       temp
+  0x08003460:  0800632C     DC.W       0800632C               ; R_ARM_ABS32
+  0x08003464:  08006741     DC.W       08006741               ; R_ARM_ABS32
+  0x08003468:  080062D3     DC.W       080062D3               ; R_ARM_ABS32
+  0x0800346C:  20000698     DC.W       onTimeCounterSET
+  0x08003470:  20000740     DC.W       onTimeGN
+  0x08003474:  2000074C     DC.W       offTimeGN
+  0x08003478:  08006948     DC.W       08006948               ; R_ARM_ABS32
+  0x0800347C:  08006511     DC.W       08006511               ; R_ARM_ABS32
+  0x08003480:  200006B0     DC.W       offTimeCounterRT
+  0x08003484:  080062F6     DC.W       080062F6               ; R_ARM_ABS32
+  0x08003488:  200006B8     DC.W       offTimeCounter
+  0x0800348C:  2000075C     DC.W       alarmMode
+  0x08003490:  080062BC     DC.W       080062BC               ; R_ARM_ABS32
+  0x08003494:  20000736     DC.W       smState.122
+  0x08003498:  080064D9     DC.W       080064D9               ; R_ARM_ABS32
+  0x0800349C:  0800690C     DC.W       0800690C               ; R_ARM_ABS32
+  0x080034A0:  000003C7     DC.W       0x000003C7
+  0x080034A4:  48F0         LDR        R0, =buttonState         ; [PC, #0x03C0] [0x08003868] =0x2000073A 
+  0x080034A6:  7800         LDRB       R0, [R0]
+  0x080034A8:  2800         CMP        R0, #0
+  0x080034AA:  D001         BEQ        .L188                    ; 0x080034B0
+  0x080034AC:  F000 FE32    BL         .L252                    ; 0x08004114
+
.L188:
+  0x080034B0:  49EE         LDR        R1, =0x50000410          ; [PC, #0x03B8] [0x0800386C] 
+  0x080034B2:  981B         LDR        R0, [SP, #108]
+  0x080034B4:  6188         STR        R0, [R1, #24]
+  0x080034B6:  981A         LDR        R0, [SP, #104]
+  0x080034B8:  6088         STR        R0, [R1, #8]
+  0x080034BA:  48ED         LDR        R0, =relaisState         ; [PC, #0x03B4] [0x08003870] =0x20000730 
+  0x080034BC:  2600         MOVS       R6, #0
+  0x080034BE:  7006         STRB       R6, [R0]
+  0x080034C0:  48EC         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03B0] [0x08003874] =0x200006A0 
+  0x080034C2:  9A16         LDR        R2, [SP, #88]
+  0x080034C4:  6002         STR        R2, [R0]
+  0x080034C6:  9820         LDR        R0, [SP, #128]
+  0x080034C8:  6188         STR        R0, [R1, #24]
+  0x080034CA:  48EB         LDR        R0, =offTimeCounter      ; [PC, #0x03AC] [0x08003878] =0x200006B8 
+  0x080034CC:  6006         STR        R6, [R0]
+  0x080034CE:  48EB         LDR        R0, =alarmMode           ; [PC, #0x03AC] [0x0800387C] =0x2000075C 
+  0x080034D0:  7006         STRB       R6, [R0]
+  0x080034D2:  48EB         LDR        R0, =onTimeCounter       ; [PC, #0x03AC] [0x08003880] =0x200006A8 
+  0x080034D4:  6006         STR        R6, [R0]
+  0x080034D6:  49EB         LDR        R1, =0x50000818          ; [PC, #0x03AC] [0x08003884] 
+  0x080034D8:  981F         LDR        R0, [SP, #124]
+  0x080034DA:  6108         STR        R0, [R1, #16]
+  0x080034DC:  48EA         LDR        R0, =offTimeCounterGN    ; [PC, #0x03A8] [0x08003888] =0x200006B4 
+  0x080034DE:  6006         STR        R6, [R0]
+  0x080034E0:  48EA         LDR        R0, =blinkModeGN         ; [PC, #0x03A8] [0x0800388C] =0x20000758 
+  0x080034E2:  7006         STRB       R6, [R0]
+  0x080034E4:  48EA         LDR        R0, =onTimeCounterGN     ; [PC, #0x03A8] [0x08003890] =0x200006A4 
+  0x080034E6:  6006         STR        R6, [R0]
+  0x080034E8:  981E         LDR        R0, [SP, #120]
+  0x080034EA:  6108         STR        R0, [R1, #16]
+  0x080034EC:  48E9         LDR        R0, =offTimeCounterRT    ; [PC, #0x03A4] [0x08003894] =0x200006B0 
+  0x080034EE:  6006         STR        R6, [R0]
+  0x080034F0:  48E9         LDR        R0, =blinkModeRT         ; [PC, #0x03A4] [0x08003898] =0x20000754 
+  0x080034F2:  7006         STRB       R6, [R0]
+  0x080034F4:  48E9         LDR        R0, =onTimeCounterRT     ; [PC, #0x03A4] [0x0800389C] =0x2000069C 
+  0x080034F6:  6006         STR        R6, [R0]
+  0x080034F8:  48E9         LDR        R0, =0x08006282          ; [PC, #0x03A4] [0x080038A0] 
+  0x080034FA:  F001 FE79    BL         puts                     ; 0x080051F0
+  0x080034FE:  48E9         LDR        R0, =smState             ; [PC, #0x03A4] [0x080038A4] =0x20000737 
+  0x08003500:  7006         STRB       R6, [R0]
+  0x08003502:  F000 FE07    BL         .L252                    ; 0x08004114
+  0x08003506:  48D9         LDR        R0, =0x50000410          ; [PC, #0x0364] [0x0800386C] 
+  0x08003508:  6801         LDR        R1, [R0]
+  0x0800350A:  4ED7         LDR        R6, =buttonState         ; [PC, #0x035C] [0x08003868] =0x2000073A 
+  0x0800350C:  7830         LDRB       R0, [R6]
+  0x0800350E:  2801         CMP        R0, #1
+  0x08003510:  D12A         BNE        .L189                    ; 0x08003568
+  0x08003512:  0748         LSLS       R0, R1, #29
+  0x08003514:  D56A         BPL        .L192                    ; 0x080035EC
+  0x08003516:  49D5         LDR        R1, =0x50000410          ; [PC, #0x0354] [0x0800386C] 
+  0x08003518:  981A         LDR        R0, [SP, #104]
+  0x0800351A:  6188         STR        R0, [R1, #24]
+  0x0800351C:  981B         LDR        R0, [SP, #108]
+  0x0800351E:  6088         STR        R0, [R1, #8]
+  0x08003520:  48D3         LDR        R0, =relaisState         ; [PC, #0x034C] [0x08003870] =0x20000730 
+  0x08003522:  7005         STRB       R5, [R0]
+  0x08003524:  48E0         LDR        R0, =onTimeCounterSET    ; [PC, #0x0380] [0x080038A8] =0x20000698 
+  0x08003526:  9A16         LDR        R2, [SP, #88]
+  0x08003528:  6002         STR        R2, [R0]
+  0x0800352A:  9820         LDR        R0, [SP, #128]
+  0x0800352C:  6088         STR        R0, [R1, #8]
+  0x0800352E:  48DF         LDR        R0, =onTimeGN            ; [PC, #0x037C] [0x080038AC] =0x20000740 
+  0x08003530:  7005         STRB       R5, [R0]
+  0x08003532:  48D3         LDR        R0, =onTimeCounter       ; [PC, #0x034C] [0x08003880] =0x200006A8 
+  0x08003534:  21C8         MOVS       R1, #200
+  0x08003536:  6001         STR        R1, [R0]
+  0x08003538:  48DD         LDR        R0, =offTimeGN           ; [PC, #0x0374] [0x080038B0] =0x2000074C 
+  0x0800353A:  7005         STRB       R5, [R0]
+  0x0800353C:  48D3         LDR        R0, =blinkModeGN         ; [PC, #0x034C] [0x0800388C] =0x20000758 
+  0x0800353E:  7005         STRB       R5, [R0]
+  0x08003540:  4AD0         LDR        R2, =0x50000818          ; [PC, #0x0340] [0x08003884] 
+  0x08003542:  981F         LDR        R0, [SP, #124]
+  0x08003544:  6010         STR        R0, [R2]
+  0x08003546:  48D2         LDR        R0, =onTimeCounterGN     ; [PC, #0x0348] [0x08003890] =0x200006A4 
+  0x08003548:  6001         STR        R1, [R0]
+  0x0800354A:  981E         LDR        R0, [SP, #120]
+  0x0800354C:  6110         STR        R0, [R2, #16]
+  0x0800354E:  48D1         LDR        R0, =offTimeCounterRT    ; [PC, #0x0344] [0x08003894] =0x200006B0 
+  0x08003550:  2100         MOVS       R1, #0
+  0x08003552:  6001         STR        R1, [R0]
+  0x08003554:  48D0         LDR        R0, =blinkModeRT         ; [PC, #0x0340] [0x08003898] =0x20000754 
+  0x08003556:  7001         STRB       R1, [R0]
+  0x08003558:  48D0         LDR        R0, =onTimeCounterRT     ; [PC, #0x0340] [0x0800389C] =0x2000069C 
+  0x0800355A:  6001         STR        R1, [R0]
+  0x0800355C:  48D5         LDR        R0, =0x080064C3          ; [PC, #0x0354] [0x080038B4] 
+  0x0800355E:  F001 FE47    BL         puts                     ; 0x080051F0
+  0x08003562:  48D5         LDR        R0, =smState.122         ; [PC, #0x0354] [0x080038B8] =0x20000736 
+  0x08003564:  7005         STRB       R5, [R0]
+  0x08003566:  7830         LDRB       R0, [R6]
+
.L189:
+  0x08003568:  2802         CMP        R0, #2
+  0x0800356A:  D001         BEQ        .L190                    ; 0x08003570
+  0x0800356C:  F000 FDD2    BL         .L252                    ; 0x08004114
+
.L190:
+  0x08003570:  49BE         LDR        R1, =0x50000410          ; [PC, #0x02F8] [0x0800386C] 
+  0x08003572:  981A         LDR        R0, [SP, #104]
+  0x08003574:  6188         STR        R0, [R1, #24]
+  0x08003576:  981B         LDR        R0, [SP, #108]
+  0x08003578:  6088         STR        R0, [R1, #8]
+  0x0800357A:  48BD         LDR        R0, =relaisState         ; [PC, #0x02F4] [0x08003870] =0x20000730 
+  0x0800357C:  7005         STRB       R5, [R0]
+  0x0800357E:  48CA         LDR        R0, =onTimeCounterSET    ; [PC, #0x0328] [0x080038A8] =0x20000698 
+  0x08003580:  9A16         LDR        R2, [SP, #88]
+  0x08003582:  6002         STR        R2, [R0]
+  0x08003584:  48CD         LDR        R0, =onTime              ; [PC, #0x0334] [0x080038BC] =0x20000744 
+  0x08003586:  7005         STRB       R5, [R0]
+  0x08003588:  48CD         LDR        R0, =offTime             ; [PC, #0x0334] [0x080038C0] =0x20000750 
+  0x0800358A:  7005         STRB       R5, [R0]
+  0x0800358C:  48BB         LDR        R0, =alarmMode           ; [PC, #0x02EC] [0x0800387C] =0x2000075C 
+  0x0800358E:  7005         STRB       R5, [R0]
+  0x08003590:  9820         LDR        R0, [SP, #128]
+  0x08003592:  6088         STR        R0, [R1, #8]
+  0x08003594:  49BA         LDR        R1, =onTimeCounter       ; [PC, #0x02E8] [0x08003880] =0x200006A8 
+  0x08003596:  20C8         MOVS       R0, #200
+  0x08003598:  6008         STR        R0, [R1]
+  0x0800359A:  4BBA         LDR        R3, =0x50000818          ; [PC, #0x02E8] [0x08003884] 
+  0x0800359C:  991F         LDR        R1, [SP, #124]
+  0x0800359E:  6019         STR        R1, [R3]
+  0x080035A0:  49BB         LDR        R1, =onTimeCounterGN     ; [PC, #0x02EC] [0x08003890] =0x200006A4 
+  0x080035A2:  2200         MOVS       R2, #0
+  0x080035A4:  600A         STR        R2, [R1]
+  0x080035A6:  49B9         LDR        R1, =blinkModeGN         ; [PC, #0x02E4] [0x0800388C] =0x20000758 
+  0x080035A8:  700A         STRB       R2, [R1]
+  0x080035AA:  49B7         LDR        R1, =offTimeCounterGN    ; [PC, #0x02DC] [0x08003888] =0x200006B4 
+  0x080035AC:  600A         STR        R2, [R1]
+  0x080035AE:  9E1E         LDR        R6, [SP, #120]
+  0x080035B0:  611E         STR        R6, [R3, #16]
+  0x080035B2:  49C4         LDR        R1, =onTimeRT            ; [PC, #0x0310] [0x080038C4] =0x2000073C 
+  0x080035B4:  700D         STRB       R5, [R1]
+  0x080035B6:  49B7         LDR        R1, =offTimeCounterRT    ; [PC, #0x02DC] [0x08003894] =0x200006B0 
+  0x080035B8:  600A         STR        R2, [R1]
+  0x080035BA:  49C3         LDR        R1, =offTimeRT           ; [PC, #0x030C] [0x080038C8] =0x20000748 
+  0x080035BC:  700D         STRB       R5, [R1]
+  0x080035BE:  49B6         LDR        R1, =blinkModeRT         ; [PC, #0x02D8] [0x08003898] =0x20000754 
+  0x080035C0:  700D         STRB       R5, [R1]
+  0x080035C2:  49C2         LDR        R1, =numberOfBlinks      ; [PC, #0x0308] [0x080038CC] =0x200006BC 
+  0x080035C4:  600D         STR        R5, [R1]
+  0x080035C6:  49C2         LDR        R1, =blinkCounter        ; [PC, #0x0308] [0x080038D0] =0x200006EC 
+  0x080035C8:  600D         STR        R5, [R1]
+  0x080035CA:  49C2         LDR        R1, =pauseTime           ; [PC, #0x0308] [0x080038D4] =0x20000734 
+  0x080035CC:  700D         STRB       R5, [R1]
+  0x080035CE:  601E         STR        R6, [R3]
+  0x080035D0:  F000 FD3E    BL         .L246                    ; 0x08004050
+  0x080035D4:  48A5         LDR        R0, =0x50000410          ; [PC, #0x0294] [0x0800386C] 
+  0x080035D6:  6801         LDR        R1, [R0]
+  0x080035D8:  4EA3         LDR        R6, =buttonState         ; [PC, #0x028C] [0x08003868] =0x2000073A 
+  0x080035DA:  7830         LDRB       R0, [R6]
+  0x080035DC:  2801         CMP        R0, #1
+  0x080035DE:  D001         BEQ        .L191                    ; 0x080035E4
+  0x080035E0:  F000 FCAF    BL         .L240                    ; 0x08003F42
+
.L191:
+  0x080035E4:  0748         LSLS       R0, R1, #29
+  0x080035E6:  D501         BPL        .L192                    ; 0x080035EC
+  0x080035E8:  F000 FC82    BL         .L239                    ; 0x08003EF0
+
.L192:
+  0x080035EC:  489F         LDR        R0, =0x50000410          ; [PC, #0x027C] [0x0800386C] 
+  0x080035EE:  9920         LDR        R1, [SP, #128]
+  0x080035F0:  6081         STR        R1, [R0, #8]
+  0x080035F2:  2000         MOVS       R0, #0
+  0x080035F4:  7030         STRB       R0, [R6]
+  0x080035F6:  9810         LDR        R0, [SP, #64]
+  0x080035F8:  30F4         ADDS       R0, #244
+  0x080035FA:  49A1         LDR        R1, =onTimeCounter       ; [PC, #0x0284] [0x08003880] =0x200006A8 
+  0x080035FC:  6008         STR        R0, [R1]
+  0x080035FE:  F000 FD89    BL         .L252                    ; 0x08004114
+  0x08003602:  489A         LDR        R0, =0x50000410          ; [PC, #0x0268] [0x0800386C] 
+  0x08003604:  6800         LDR        R0, [R0]
+  0x08003606:  49B4         LDR        R1, =0x50000010          ; [PC, #0x02D0] [0x080038D8] 
+  0x08003608:  6809         LDR        R1, [R1]
+  0x0800360A:  07C9         LSLS       R1, R1, #31
+  0x0800360C:  D103         BNE        .L193                    ; 0x08003616
+  0x0800360E:  49B2         LDR        R1, =0x50000010          ; [PC, #0x02C8] [0x080038D8] 
+  0x08003610:  6809         LDR        R1, [R1]
+  0x08003612:  0789         LSLS       R1, R1, #30
+  0x08003614:  D517         BPL        .L196                    ; 0x08003646
+
.L193:
+  0x08003616:  49B1         LDR        R1, =LVP_OVP_SM_On.oldtime ; [PC, #0x02C4] [0x080038DC] =0x20000728 
+  0x08003618:  680A         LDR        R2, [R1]
+  0x0800361A:  4BB1         LDR        R3, =uwTick              ; [PC, #0x02C4] [0x080038E0] =0x2000068C 
+  0x0800361C:  681B         LDR        R3, [R3]
+  0x0800361E:  4293         CMP        R3, R2
+  0x08003620:  D011         BEQ        .L196                    ; 0x08003646
+  0x08003622:  4AB0         LDR        R2, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x02C0] [0x080038E4] =0x2000072C 
+  0x08003624:  6813         LDR        R3, [R2]
+  0x08003626:  4EB0         LDR        R6, =0x00001388          ; [PC, #0x02C0] [0x080038E8] 
+  0x08003628:  42B3         CMP        R3, R6
+  0x0800362A:  DA05         BGE        .L194                    ; 0x08003638
+  0x0800362C:  1C5E         ADDS       R6, R3, #1
+  0x0800362E:  6016         STR        R6, [R2]
+  0x08003630:  4EAD         LDR        R6, =0x00001388          ; [PC, #0x02B4] [0x080038E8] 
+  0x08003632:  1E76         SUBS       R6, R6, #1
+  0x08003634:  42B3         CMP        R3, R6
+  0x08003636:  D103         BNE        .L195                    ; 0x08003640
+
.L194:
+  0x08003638:  2300         MOVS       R3, #0
+  0x0800363A:  6013         STR        R3, [R2]
+  0x0800363C:  4AAB         LDR        R2, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x02AC] [0x080038EC] =0x20000768 
+  0x0800363E:  7015         STRB       R5, [R2]
+
.L195:
+  0x08003640:  4AA7         LDR        R2, =uwTick              ; [PC, #0x029C] [0x080038E0] =0x2000068C 
+  0x08003642:  6812         LDR        R2, [R2]
+  0x08003644:  600A         STR        R2, [R1]
+
.L196:
+  0x08003646:  49A4         LDR        R1, =0x50000010          ; [PC, #0x0290] [0x080038D8] 
+  0x08003648:  6809         LDR        R1, [R1]
+  0x0800364A:  07C9         LSLS       R1, R1, #31
+  0x0800364C:  D108         BNE        .L197                    ; 0x08003660
+  0x0800364E:  49A2         LDR        R1, =0x50000010          ; [PC, #0x0288] [0x080038D8] 
+  0x08003650:  6809         LDR        R1, [R1]
+  0x08003652:  0789         LSLS       R1, R1, #30
+  0x08003654:  D404         BMI        .L197                    ; 0x08003660
+  0x08003656:  49A3         LDR        R1, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x028C] [0x080038E4] =0x2000072C 
+  0x08003658:  2200         MOVS       R2, #0
+  0x0800365A:  600A         STR        R2, [R1]
+  0x0800365C:  49A3         LDR        R1, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x028C] [0x080038EC] =0x20000768 
+  0x0800365E:  700A         STRB       R2, [R1]
+
.L197:
+  0x08003660:  990F         LDR        R1, [SP, #60]
+  0x08003662:  4008         ANDS       R0, R1
+  0x08003664:  D135         BNE        .L198                    ; 0x080036D2
+  0x08003666:  4A81         LDR        R2, =0x50000410          ; [PC, #0x0204] [0x0800386C] 
+  0x08003668:  981B         LDR        R0, [SP, #108]
+  0x0800366A:  6190         STR        R0, [R2, #24]
+  0x0800366C:  981A         LDR        R0, [SP, #104]
+  0x0800366E:  6090         STR        R0, [R2, #8]
+  0x08003670:  497F         LDR        R1, =relaisState         ; [PC, #0x01FC] [0x08003870] =0x20000730 
+  0x08003672:  2000         MOVS       R0, #0
+  0x08003674:  7008         STRB       R0, [R1]
+  0x08003676:  497F         LDR        R1, =onTimeCounterRESET  ; [PC, #0x01FC] [0x08003874] =0x200006A0 
+  0x08003678:  9B16         LDR        R3, [SP, #88]
+  0x0800367A:  600B         STR        R3, [R1]
+  0x0800367C:  9920         LDR        R1, [SP, #128]
+  0x0800367E:  6091         STR        R1, [R2, #8]
+  0x08003680:  9910         LDR        R1, [SP, #64]
+  0x08003682:  31F4         ADDS       R1, #244
+  0x08003684:  4A7E         LDR        R2, =onTimeCounter       ; [PC, #0x01F8] [0x08003880] =0x200006A8 
+  0x08003686:  6011         STR        R1, [R2]
+  0x08003688:  4A7E         LDR        R2, =0x50000818          ; [PC, #0x01F8] [0x08003884] 
+  0x0800368A:  991F         LDR        R1, [SP, #124]
+  0x0800368C:  6111         STR        R1, [R2, #16]
+  0x0800368E:  497E         LDR        R1, =offTimeCounterGN    ; [PC, #0x01F8] [0x08003888] =0x200006B4 
+  0x08003690:  6008         STR        R0, [R1]
+  0x08003692:  497E         LDR        R1, =blinkModeGN         ; [PC, #0x01F8] [0x0800388C] =0x20000758 
+  0x08003694:  7008         STRB       R0, [R1]
+  0x08003696:  497E         LDR        R1, =onTimeCounterGN     ; [PC, #0x01F8] [0x08003890] =0x200006A4 
+  0x08003698:  6008         STR        R0, [R1]
+  0x0800369A:  498A         LDR        R1, =onTimeRT            ; [PC, #0x0228] [0x080038C4] =0x2000073C 
+  0x0800369C:  700D         STRB       R5, [R1]
+  0x0800369E:  498A         LDR        R1, =offTimeRT           ; [PC, #0x0228] [0x080038C8] =0x20000748 
+  0x080036A0:  700D         STRB       R5, [R1]
+  0x080036A2:  497D         LDR        R1, =blinkModeRT         ; [PC, #0x01F4] [0x08003898] =0x20000754 
+  0x080036A4:  700D         STRB       R5, [R1]
+  0x080036A6:  4989         LDR        R1, =numberOfBlinks      ; [PC, #0x0224] [0x080038CC] =0x200006BC 
+  0x080036A8:  2603         MOVS       R6, #3
+  0x080036AA:  600E         STR        R6, [R1]
+  0x080036AC:  4988         LDR        R1, =blinkCounter        ; [PC, #0x0220] [0x080038D0] =0x200006EC 
+  0x080036AE:  600E         STR        R6, [R1]
+  0x080036B0:  4988         LDR        R1, =pauseTime           ; [PC, #0x0220] [0x080038D4] =0x20000734 
+  0x080036B2:  700D         STRB       R5, [R1]
+  0x080036B4:  991E         LDR        R1, [SP, #120]
+  0x080036B6:  6011         STR        R1, [R2]
+  0x080036B8:  496B         LDR        R1, =buttonState         ; [PC, #0x01AC] [0x08003868] =0x2000073A 
+  0x080036BA:  7008         STRB       R0, [R1]
+  0x080036BC:  4877         LDR        R0, =onTimeCounterRT     ; [PC, #0x01DC] [0x0800389C] =0x2000069C 
+  0x080036BE:  21C8         MOVS       R1, #200
+  0x080036C0:  6001         STR        R1, [R0]
+  0x080036C2:  488B         LDR        R0, =0x0800698C          ; [PC, #0x022C] [0x080038F0] 
+  0x080036C4:  F001 FD94    BL         puts                     ; 0x080051F0
+  0x080036C8:  488A         LDR        R0, =0x080066B0          ; [PC, #0x0228] [0x080038F4] 
+  0x080036CA:  F001 FD91    BL         puts                     ; 0x080051F0
+  0x080036CE:  487A         LDR        R0, =smState.122         ; [PC, #0x01E8] [0x080038B8] =0x20000736 
+  0x080036D0:  7006         STRB       R6, [R0]
+
.L198:
+  0x080036D2:  4889         LDR        R0, =temp                ; [PC, #0x0224] [0x080038F8] =0x20000690 
+  0x080036D4:  6800         LDR        R0, [R0]
+  0x080036D6:  2851         CMP        R0, #81
+  0x080036D8:  DB33         BLT        .L199                    ; 0x08003742
+  0x080036DA:  4A64         LDR        R2, =0x50000410          ; [PC, #0x0190] [0x0800386C] 
+  0x080036DC:  981B         LDR        R0, [SP, #108]
+  0x080036DE:  6190         STR        R0, [R2, #24]
+  0x080036E0:  981A         LDR        R0, [SP, #104]
+  0x080036E2:  6090         STR        R0, [R2, #8]
+  0x080036E4:  4962         LDR        R1, =relaisState         ; [PC, #0x0188] [0x08003870] =0x20000730 
+  0x080036E6:  2000         MOVS       R0, #0
+  0x080036E8:  7008         STRB       R0, [R1]
+  0x080036EA:  4962         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0188] [0x08003874] =0x200006A0 
+  0x080036EC:  9B16         LDR        R3, [SP, #88]
+  0x080036EE:  600B         STR        R3, [R1]
+  0x080036F0:  9920         LDR        R1, [SP, #128]
+  0x080036F2:  6091         STR        R1, [R2, #8]
+  0x080036F4:  9910         LDR        R1, [SP, #64]
+  0x080036F6:  31F4         ADDS       R1, #244
+  0x080036F8:  4A61         LDR        R2, =onTimeCounter       ; [PC, #0x0184] [0x08003880] =0x200006A8 
+  0x080036FA:  6011         STR        R1, [R2]
+  0x080036FC:  4B61         LDR        R3, =0x50000818          ; [PC, #0x0184] [0x08003884] 
+  0x080036FE:  991F         LDR        R1, [SP, #124]
+  0x08003700:  6119         STR        R1, [R3, #16]
+  0x08003702:  4961         LDR        R1, =offTimeCounterGN    ; [PC, #0x0184] [0x08003888] =0x200006B4 
+  0x08003704:  6008         STR        R0, [R1]
+  0x08003706:  4961         LDR        R1, =blinkModeGN         ; [PC, #0x0184] [0x0800388C] =0x20000758 
+  0x08003708:  7008         STRB       R0, [R1]
+  0x0800370A:  4961         LDR        R1, =onTimeCounterGN     ; [PC, #0x0184] [0x08003890] =0x200006A4 
+  0x0800370C:  6008         STR        R0, [R1]
+  0x0800370E:  496D         LDR        R1, =onTimeRT            ; [PC, #0x01B4] [0x080038C4] =0x2000073C 
+  0x08003710:  700D         STRB       R5, [R1]
+  0x08003712:  496D         LDR        R1, =offTimeRT           ; [PC, #0x01B4] [0x080038C8] =0x20000748 
+  0x08003714:  700D         STRB       R5, [R1]
+  0x08003716:  4960         LDR        R1, =blinkModeRT         ; [PC, #0x0180] [0x08003898] =0x20000754 
+  0x08003718:  700D         STRB       R5, [R1]
+  0x0800371A:  496C         LDR        R1, =numberOfBlinks      ; [PC, #0x01B0] [0x080038CC] =0x200006BC 
+  0x0800371C:  2205         MOVS       R2, #5
+  0x0800371E:  600A         STR        R2, [R1]
+  0x08003720:  496B         LDR        R1, =blinkCounter        ; [PC, #0x01AC] [0x080038D0] =0x200006EC 
+  0x08003722:  600A         STR        R2, [R1]
+  0x08003724:  496B         LDR        R1, =pauseTime           ; [PC, #0x01AC] [0x080038D4] =0x20000734 
+  0x08003726:  700D         STRB       R5, [R1]
+  0x08003728:  991E         LDR        R1, [SP, #120]
+  0x0800372A:  6019         STR        R1, [R3]
+  0x0800372C:  494E         LDR        R1, =buttonState         ; [PC, #0x0138] [0x08003868] =0x2000073A 
+  0x0800372E:  7008         STRB       R0, [R1]
+  0x08003730:  485A         LDR        R0, =onTimeCounterRT     ; [PC, #0x0168] [0x0800389C] =0x2000069C 
+  0x08003732:  21C8         MOVS       R1, #200
+  0x08003734:  6001         STR        R1, [R0]
+  0x08003736:  4871         LDR        R0, =0x0800632C          ; [PC, #0x01C4] [0x080038FC] 
+  0x08003738:  F001 FD5A    BL         puts                     ; 0x080051F0
+  0x0800373C:  2003         MOVS       R0, #3
+  0x0800373E:  495E         LDR        R1, =smState.122         ; [PC, #0x0178] [0x080038B8] =0x20000736 
+  0x08003740:  7008         STRB       R0, [R1]
+
.L199:
+  0x08003742:  486A         LDR        R0, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x01A8] [0x080038EC] =0x20000768 
+  0x08003744:  4E4A         LDR        R6, =relaisState         ; [PC, #0x0128] [0x08003870] =0x20000730 
+  0x08003746:  7800         LDRB       R0, [R0]
+  0x08003748:  2801         CMP        R0, #1
+  0x0800374A:  7830         LDRB       R0, [R6]
+  0x0800374C:  D137         BNE        .L200                    ; 0x080037BE
+  0x0800374E:  2800         CMP        R0, #0
+  0x08003750:  D05B         BEQ        .L201                    ; 0x0800380A
+  0x08003752:  4A46         LDR        R2, =0x50000410          ; [PC, #0x0118] [0x0800386C] 
+  0x08003754:  981B         LDR        R0, [SP, #108]
+  0x08003756:  6190         STR        R0, [R2, #24]
+  0x08003758:  981A         LDR        R0, [SP, #104]
+  0x0800375A:  6090         STR        R0, [R2, #8]
+  0x0800375C:  2000         MOVS       R0, #0
+  0x0800375E:  7030         STRB       R0, [R6]
+  0x08003760:  4944         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0110] [0x08003874] =0x200006A0 
+  0x08003762:  9B16         LDR        R3, [SP, #88]
+  0x08003764:  600B         STR        R3, [R1]
+  0x08003766:  9920         LDR        R1, [SP, #128]
+  0x08003768:  6091         STR        R1, [R2, #8]
+  0x0800376A:  9910         LDR        R1, [SP, #64]
+  0x0800376C:  31F4         ADDS       R1, #244
+  0x0800376E:  4A44         LDR        R2, =onTimeCounter       ; [PC, #0x0110] [0x08003880] =0x200006A8 
+  0x08003770:  6011         STR        R1, [R2]
+  0x08003772:  4A44         LDR        R2, =0x50000818          ; [PC, #0x0110] [0x08003884] 
+  0x08003774:  991F         LDR        R1, [SP, #124]
+  0x08003776:  6111         STR        R1, [R2, #16]
+  0x08003778:  4943         LDR        R1, =offTimeCounterGN    ; [PC, #0x010C] [0x08003888] =0x200006B4 
+  0x0800377A:  6008         STR        R0, [R1]
+  0x0800377C:  4943         LDR        R1, =blinkModeGN         ; [PC, #0x010C] [0x0800388C] =0x20000758 
+  0x0800377E:  7008         STRB       R0, [R1]
+  0x08003780:  4943         LDR        R1, =onTimeCounterGN     ; [PC, #0x010C] [0x08003890] =0x200006A4 
+  0x08003782:  6008         STR        R0, [R1]
+  0x08003784:  484F         LDR        R0, =onTimeRT            ; [PC, #0x013C] [0x080038C4] =0x2000073C 
+  0x08003786:  7005         STRB       R5, [R0]
+  0x08003788:  484F         LDR        R0, =offTimeRT           ; [PC, #0x013C] [0x080038C8] =0x20000748 
+  0x0800378A:  7005         STRB       R5, [R0]
+  0x0800378C:  4842         LDR        R0, =blinkModeRT         ; [PC, #0x0108] [0x08003898] =0x20000754 
+  0x0800378E:  7005         STRB       R5, [R0]
+  0x08003790:  484E         LDR        R0, =numberOfBlinks      ; [PC, #0x0138] [0x080038CC] =0x200006BC 
+  0x08003792:  2102         MOVS       R1, #2
+  0x08003794:  6001         STR        R1, [R0]
+  0x08003796:  484E         LDR        R0, =blinkCounter        ; [PC, #0x0138] [0x080038D0] =0x200006EC 
+  0x08003798:  6001         STR        R1, [R0]
+  0x0800379A:  484E         LDR        R0, =pauseTime           ; [PC, #0x0138] [0x080038D4] =0x20000734 
+  0x0800379C:  7005         STRB       R5, [R0]
+  0x0800379E:  981E         LDR        R0, [SP, #120]
+  0x080037A0:  6010         STR        R0, [R2]
+  0x080037A2:  483E         LDR        R0, =onTimeCounterRT     ; [PC, #248] [0x0800389C] =0x2000069C 
+  0x080037A4:  21C8         MOVS       R1, #200
+  0x080037A6:  6001         STR        R1, [R0]
+  0x080037A8:  4855         LDR        R0, =0x080068EC          ; [PC, #0x0154] [0x08003900] 
+  0x080037AA:  F001 FD21    BL         puts                     ; 0x080051F0
+  0x080037AE:  4855         LDR        R0, =0x08006295          ; [PC, #0x0154] [0x08003904] 
+  0x080037B0:  F001 FD1E    BL         puts                     ; 0x080051F0
+  0x080037B4:  484D         LDR        R0, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x0134] [0x080038EC] =0x20000768 
+  0x080037B6:  7800         LDRB       R0, [R0]
+  0x080037B8:  2800         CMP        R0, #0
+  0x080037BA:  D126         BNE        .L201                    ; 0x0800380A
+  0x080037BC:  7830         LDRB       R0, [R6]
+
.L200:
+  0x080037BE:  2800         CMP        R0, #0
+  0x080037C0:  D123         BNE        .L201                    ; 0x0800380A
+  0x080037C2:  492A         LDR        R1, =0x50000410          ; [PC, #168] [0x0800386C] 
+  0x080037C4:  981A         LDR        R0, [SP, #104]
+  0x080037C6:  6188         STR        R0, [R1, #24]
+  0x080037C8:  981B         LDR        R0, [SP, #108]
+  0x080037CA:  6088         STR        R0, [R1, #8]
+  0x080037CC:  7035         STRB       R5, [R6]
+  0x080037CE:  4836         LDR        R0, =onTimeCounterSET    ; [PC, #216] [0x080038A8] =0x20000698 
+  0x080037D0:  9A16         LDR        R2, [SP, #88]
+  0x080037D2:  6002         STR        R2, [R0]
+  0x080037D4:  9820         LDR        R0, [SP, #128]
+  0x080037D6:  6088         STR        R0, [R1, #8]
+  0x080037D8:  4829         LDR        R0, =onTimeCounter       ; [PC, #164] [0x08003880] =0x200006A8 
+  0x080037DA:  21C8         MOVS       R1, #200
+  0x080037DC:  6001         STR        R1, [R0]
+  0x080037DE:  4B29         LDR        R3, =0x50000818          ; [PC, #164] [0x08003884] 
+  0x080037E0:  9F1F         LDR        R7, [SP, #124]
+  0x080037E2:  611F         STR        R7, [R3, #16]
+  0x080037E4:  4831         LDR        R0, =onTimeGN            ; [PC, #196] [0x080038AC] =0x20000740 
+  0x080037E6:  7005         STRB       R5, [R0]
+  0x080037E8:  4827         LDR        R0, =offTimeCounterGN    ; [PC, #156] [0x08003888] =0x200006B4 
+  0x080037EA:  2200         MOVS       R2, #0
+  0x080037EC:  6002         STR        R2, [R0]
+  0x080037EE:  4830         LDR        R0, =offTimeGN           ; [PC, #192] [0x080038B0] =0x2000074C 
+  0x080037F0:  7005         STRB       R5, [R0]
+  0x080037F2:  4826         LDR        R0, =blinkModeGN         ; [PC, #152] [0x0800388C] =0x20000758 
+  0x080037F4:  7005         STRB       R5, [R0]
+  0x080037F6:  601F         STR        R7, [R3]
+  0x080037F8:  4627         MOV        R7, R4
+  0x080037FA:  4825         LDR        R0, =onTimeCounterGN     ; [PC, #148] [0x08003890] =0x200006A4 
+  0x080037FC:  6001         STR        R1, [R0]
+  0x080037FE:  4842         LDR        R0, =0x080068FC          ; [PC, #0x0108] [0x08003908] 
+  0x08003800:  F001 FCF6    BL         puts                     ; 0x080051F0
+  0x08003804:  4841         LDR        R0, =0x0800649D          ; [PC, #0x0104] [0x0800390C] 
+  0x08003806:  F001 FCF3    BL         puts                     ; 0x080051F0
+
.L201:
+  0x0800380A:  4817         LDR        R0, =buttonState         ; [PC, #92] [0x08003868] =0x2000073A 
+  0x0800380C:  7800         LDRB       R0, [R0]
+  0x0800380E:  2800         CMP        R0, #0
+  0x08003810:  D001         BEQ        .L202                    ; 0x08003816
+  0x08003812:  F000 FC7F    BL         .L252                    ; 0x08004114
+
.L202:
+  0x08003816:  4915         LDR        R1, =0x50000410          ; [PC, #84] [0x0800386C] 
+  0x08003818:  981B         LDR        R0, [SP, #108]
+  0x0800381A:  6188         STR        R0, [R1, #24]
+  0x0800381C:  981A         LDR        R0, [SP, #104]
+  0x0800381E:  6088         STR        R0, [R1, #8]
+  0x08003820:  2700         MOVS       R7, #0
+  0x08003822:  7037         STRB       R7, [R6]
+  0x08003824:  4813         LDR        R0, =onTimeCounterRESET  ; [PC, #76] [0x08003874] =0x200006A0 
+  0x08003826:  9A16         LDR        R2, [SP, #88]
+  0x08003828:  6002         STR        R2, [R0]
+  0x0800382A:  9820         LDR        R0, [SP, #128]
+  0x0800382C:  6088         STR        R0, [R1, #8]
+  0x0800382E:  4814         LDR        R0, =onTimeCounter       ; [PC, #80] [0x08003880] =0x200006A8 
+  0x08003830:  21C8         MOVS       R1, #200
+  0x08003832:  6001         STR        R1, [R0]
+  0x08003834:  4913         LDR        R1, =0x50000818          ; [PC, #76] [0x08003884] 
+  0x08003836:  981F         LDR        R0, [SP, #124]
+  0x08003838:  6108         STR        R0, [R1, #16]
+  0x0800383A:  4813         LDR        R0, =offTimeCounterGN    ; [PC, #76] [0x08003888] =0x200006B4 
+  0x0800383C:  6007         STR        R7, [R0]
+  0x0800383E:  4813         LDR        R0, =blinkModeGN         ; [PC, #76] [0x0800388C] =0x20000758 
+  0x08003840:  7007         STRB       R7, [R0]
+  0x08003842:  4813         LDR        R0, =onTimeCounterGN     ; [PC, #76] [0x08003890] =0x200006A4 
+  0x08003844:  6007         STR        R7, [R0]
+  0x08003846:  981E         LDR        R0, [SP, #120]
+  0x08003848:  6108         STR        R0, [R1, #16]
+  0x0800384A:  4812         LDR        R0, =offTimeCounterRT    ; [PC, #72] [0x08003894] =0x200006B0 
+  0x0800384C:  6007         STR        R7, [R0]
+  0x0800384E:  4812         LDR        R0, =blinkModeRT         ; [PC, #72] [0x08003898] =0x20000754 
+  0x08003850:  7007         STRB       R7, [R0]
+  0x08003852:  4812         LDR        R0, =onTimeCounterRT     ; [PC, #72] [0x0800389C] =0x2000069C 
+  0x08003854:  6007         STR        R7, [R0]
+  0x08003856:  482E         LDR        R0, =0x080062BC          ; [PC, #184] [0x08003910] 
+  0x08003858:  F001 FCCA    BL         puts                     ; 0x080051F0
+  0x0800385C:  4816         LDR        R0, =smState.122         ; [PC, #88] [0x080038B8] =0x20000736 
+  0x0800385E:  7007         STRB       R7, [R0]
+  0x08003860:  4820         LDR        R0, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #128] [0x080038E4] =0x2000072C 
+  0x08003862:  6007         STR        R7, [R0]
+  0x08003864:  4821         LDR        R0, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #132] [0x080038EC] =0x20000768 
+  0x08003866:  E182         B          .L213                    ; 0x08003B6E
+  0x08003868:  2000073A     DC.W       buttonState
+  0x0800386C:  50000410     DC.W       0x50000410
+  0x08003870:  20000730     DC.W       relaisState
+  0x08003874:  200006A0     DC.W       onTimeCounterRESET
+  0x08003878:  200006B8     DC.W       offTimeCounter
+  0x0800387C:  2000075C     DC.W       alarmMode
+  0x08003880:  200006A8     DC.W       onTimeCounter
+  0x08003884:  50000818     DC.W       0x50000818
+  0x08003888:  200006B4     DC.W       offTimeCounterGN
+  0x0800388C:  20000758     DC.W       blinkModeGN
+  0x08003890:  200006A4     DC.W       onTimeCounterGN
+  0x08003894:  200006B0     DC.W       offTimeCounterRT
+  0x08003898:  20000754     DC.W       blinkModeRT
+  0x0800389C:  2000069C     DC.W       onTimeCounterRT
+  0x080038A0:  08006282     DC.W       08006282               ; R_ARM_ABS32
+  0x080038A4:  20000737     DC.W       smState
+  0x080038A8:  20000698     DC.W       onTimeCounterSET
+  0x080038AC:  20000740     DC.W       onTimeGN
+  0x080038B0:  2000074C     DC.W       offTimeGN
+  0x080038B4:  080064C3     DC.W       080064C3               ; R_ARM_ABS32
+  0x080038B8:  20000736     DC.W       smState.122
+  0x080038BC:  20000744     DC.W       onTime
+  0x080038C0:  20000750     DC.W       offTime
+  0x080038C4:  2000073C     DC.W       onTimeRT
+  0x080038C8:  20000748     DC.W       offTimeRT
+  0x080038CC:  200006BC     DC.W       numberOfBlinks
+  0x080038D0:  200006EC     DC.W       blinkCounter
+  0x080038D4:  20000734     DC.W       pauseTime
+  0x080038D8:  50000010     DC.W       0x50000010
+  0x080038DC:  20000728     DC.W       LVP_OVP_SM_On.oldtime
+  0x080038E0:  2000068C     DC.W       uwTick
+  0x080038E4:  2000072C     DC.W       LVP_OVP_SM_On.lvpAndOvpInputTimeCounter
+  0x080038E8:  00001388     DC.W       0x00001388
+  0x080038EC:  20000768     DC.W       LVP_OVP_SM_On.lvpOROvpInput
+  0x080038F0:  0800698C     DC.W       0800698C               ; R_ARM_ABS32
+  0x080038F4:  080066B0     DC.W       080066B0               ; R_ARM_ABS32
+  0x080038F8:  20000690     DC.W       temp
+  0x080038FC:  0800632C     DC.W       0800632C               ; R_ARM_ABS32
+  0x08003900:  080068EC     DC.W       080068EC               ; R_ARM_ABS32
+  0x08003904:  08006295     DC.W       08006295               ; R_ARM_ABS32
+  0x08003908:  080068FC     DC.W       080068FC               ; R_ARM_ABS32
+  0x0800390C:  0800649D     DC.W       0800649D               ; R_ARM_ABS32
+  0x08003910:  080062BC     DC.W       080062BC               ; R_ARM_ABS32
+  0x08003914:  48ED         LDR        R0, =0x50000410          ; [PC, #0x03B4] [0x08003CCC] 
+  0x08003916:  6800         LDR        R0, [R0]
+  0x08003918:  49ED         LDR        R1, =0x50000010          ; [PC, #0x03B4] [0x08003CD0] 
+  0x0800391A:  6809         LDR        R1, [R1]
+  0x0800391C:  07C9         LSLS       R1, R1, #31
+  0x0800391E:  D103         BNE        .L203                    ; 0x08003928
+  0x08003920:  49EB         LDR        R1, =0x50000010          ; [PC, #0x03AC] [0x08003CD0] 
+  0x08003922:  6809         LDR        R1, [R1]
+  0x08003924:  0789         LSLS       R1, R1, #30
+  0x08003926:  D517         BPL        .L206                    ; 0x08003958
+
.L203:
+  0x08003928:  49EA         LDR        R1, =LVP_SM_On.oldtime   ; [PC, #0x03A8] [0x08003CD4] =0x20000720 
+  0x0800392A:  680A         LDR        R2, [R1]
+  0x0800392C:  4BEA         LDR        R3, =uwTick              ; [PC, #0x03A8] [0x08003CD8] =0x2000068C 
+  0x0800392E:  681B         LDR        R3, [R3]
+  0x08003930:  4293         CMP        R3, R2
+  0x08003932:  D011         BEQ        .L206                    ; 0x08003958
+  0x08003934:  4AE9         LDR        R2, =LVP_SM_On.lvpTimeCounter ; [PC, #0x03A4] [0x08003CDC] =0x20000724 
+  0x08003936:  6813         LDR        R3, [R2]
+  0x08003938:  4EE9         LDR        R6, =0x00001388          ; [PC, #0x03A4] [0x08003CE0] 
+  0x0800393A:  42B3         CMP        R3, R6
+  0x0800393C:  DA05         BGE        .L204                    ; 0x0800394A
+  0x0800393E:  1C5E         ADDS       R6, R3, #1
+  0x08003940:  6016         STR        R6, [R2]
+  0x08003942:  4EE7         LDR        R6, =0x00001388          ; [PC, #0x039C] [0x08003CE0] 
+  0x08003944:  1E76         SUBS       R6, R6, #1
+  0x08003946:  42B3         CMP        R3, R6
+  0x08003948:  D103         BNE        .L205                    ; 0x08003952
+
.L204:
+  0x0800394A:  2300         MOVS       R3, #0
+  0x0800394C:  6013         STR        R3, [R2]
+  0x0800394E:  4AE5         LDR        R2, =LVP_SM_On.lvpInput  ; [PC, #0x0394] [0x08003CE4] =0x20000764 
+  0x08003950:  7015         STRB       R5, [R2]
+
.L205:
+  0x08003952:  4AE1         LDR        R2, =uwTick              ; [PC, #0x0384] [0x08003CD8] =0x2000068C 
+  0x08003954:  6812         LDR        R2, [R2]
+  0x08003956:  600A         STR        R2, [R1]
+
.L206:
+  0x08003958:  49DD         LDR        R1, =0x50000010          ; [PC, #0x0374] [0x08003CD0] 
+  0x0800395A:  6809         LDR        R1, [R1]
+  0x0800395C:  07C9         LSLS       R1, R1, #31
+  0x0800395E:  D104         BNE        .L207                    ; 0x0800396A
+  0x08003960:  49DE         LDR        R1, =LVP_SM_On.lvpTimeCounter ; [PC, #0x0378] [0x08003CDC] =0x20000724 
+  0x08003962:  2200         MOVS       R2, #0
+  0x08003964:  600A         STR        R2, [R1]
+  0x08003966:  49DF         LDR        R1, =LVP_SM_On.lvpInput  ; [PC, #0x037C] [0x08003CE4] =0x20000764 
+  0x08003968:  700A         STRB       R2, [R1]
+
.L207:
+  0x0800396A:  990F         LDR        R1, [SP, #60]
+  0x0800396C:  4008         ANDS       R0, R1
+  0x0800396E:  D135         BNE        .L208                    ; 0x080039DC
+  0x08003970:  4AD6         LDR        R2, =0x50000410          ; [PC, #0x0358] [0x08003CCC] 
+  0x08003972:  981B         LDR        R0, [SP, #108]
+  0x08003974:  6190         STR        R0, [R2, #24]
+  0x08003976:  981A         LDR        R0, [SP, #104]
+  0x08003978:  6090         STR        R0, [R2, #8]
+  0x0800397A:  49DB         LDR        R1, =relaisState         ; [PC, #0x036C] [0x08003CE8] =0x20000730 
+  0x0800397C:  2000         MOVS       R0, #0
+  0x0800397E:  7008         STRB       R0, [R1]
+  0x08003980:  49DA         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0368] [0x08003CEC] =0x200006A0 
+  0x08003982:  9B16         LDR        R3, [SP, #88]
+  0x08003984:  600B         STR        R3, [R1]
+  0x08003986:  9920         LDR        R1, [SP, #128]
+  0x08003988:  6091         STR        R1, [R2, #8]
+  0x0800398A:  9910         LDR        R1, [SP, #64]
+  0x0800398C:  31F4         ADDS       R1, #244
+  0x0800398E:  4AD8         LDR        R2, =onTimeCounter       ; [PC, #0x0360] [0x08003CF0] =0x200006A8 
+  0x08003990:  6011         STR        R1, [R2]
+  0x08003992:  4AD8         LDR        R2, =0x50000818          ; [PC, #0x0360] [0x08003CF4] 
+  0x08003994:  991F         LDR        R1, [SP, #124]
+  0x08003996:  6111         STR        R1, [R2, #16]
+  0x08003998:  49D7         LDR        R1, =offTimeCounterGN    ; [PC, #0x035C] [0x08003CF8] =0x200006B4 
+  0x0800399A:  6008         STR        R0, [R1]
+  0x0800399C:  49D7         LDR        R1, =blinkModeGN         ; [PC, #0x035C] [0x08003CFC] =0x20000758 
+  0x0800399E:  7008         STRB       R0, [R1]
+  0x080039A0:  49D7         LDR        R1, =onTimeCounterGN     ; [PC, #0x035C] [0x08003D00] =0x200006A4 
+  0x080039A2:  6008         STR        R0, [R1]
+  0x080039A4:  49D7         LDR        R1, =onTimeRT            ; [PC, #0x035C] [0x08003D04] =0x2000073C 
+  0x080039A6:  700D         STRB       R5, [R1]
+  0x080039A8:  49D7         LDR        R1, =offTimeRT           ; [PC, #0x035C] [0x08003D08] =0x20000748 
+  0x080039AA:  700D         STRB       R5, [R1]
+  0x080039AC:  49D7         LDR        R1, =blinkModeRT         ; [PC, #0x035C] [0x08003D0C] =0x20000754 
+  0x080039AE:  700D         STRB       R5, [R1]
+  0x080039B0:  49D7         LDR        R1, =numberOfBlinks      ; [PC, #0x035C] [0x08003D10] =0x200006BC 
+  0x080039B2:  2603         MOVS       R6, #3
+  0x080039B4:  600E         STR        R6, [R1]
+  0x080039B6:  49D7         LDR        R1, =blinkCounter        ; [PC, #0x035C] [0x08003D14] =0x200006EC 
+  0x080039B8:  600E         STR        R6, [R1]
+  0x080039BA:  49D7         LDR        R1, =pauseTime           ; [PC, #0x035C] [0x08003D18] =0x20000734 
+  0x080039BC:  700D         STRB       R5, [R1]
+  0x080039BE:  991E         LDR        R1, [SP, #120]
+  0x080039C0:  6011         STR        R1, [R2]
+  0x080039C2:  49D6         LDR        R1, =buttonState         ; [PC, #0x0358] [0x08003D1C] =0x2000073A 
+  0x080039C4:  7008         STRB       R0, [R1]
+  0x080039C6:  48D6         LDR        R0, =onTimeCounterRT     ; [PC, #0x0358] [0x08003D20] =0x2000069C 
+  0x080039C8:  21C8         MOVS       R1, #200
+  0x080039CA:  6001         STR        R1, [R0]
+  0x080039CC:  48D5         LDR        R0, =0x0800698C          ; [PC, #0x0354] [0x08003D24] 
+  0x080039CE:  F001 FC0F    BL         puts                     ; 0x080051F0
+  0x080039D2:  48D5         LDR        R0, =0x08006644          ; [PC, #0x0354] [0x08003D28] 
+  0x080039D4:  F001 FC0C    BL         puts                     ; 0x080051F0
+  0x080039D8:  48D4         LDR        R0, =smState             ; [PC, #0x0350] [0x08003D2C] =0x20000737 
+  0x080039DA:  7006         STRB       R6, [R0]
+
.L208:
+  0x080039DC:  48D4         LDR        R0, =temp                ; [PC, #0x0350] [0x08003D30] =0x20000690 
+  0x080039DE:  6800         LDR        R0, [R0]
+  0x080039E0:  2851         CMP        R0, #81
+  0x080039E2:  DB33         BLT        .L209                    ; 0x08003A4C
+  0x080039E4:  4AB9         LDR        R2, =0x50000410          ; [PC, #0x02E4] [0x08003CCC] 
+  0x080039E6:  981B         LDR        R0, [SP, #108]
+  0x080039E8:  6190         STR        R0, [R2, #24]
+  0x080039EA:  981A         LDR        R0, [SP, #104]
+  0x080039EC:  6090         STR        R0, [R2, #8]
+  0x080039EE:  49BE         LDR        R1, =relaisState         ; [PC, #0x02F8] [0x08003CE8] =0x20000730 
+  0x080039F0:  2000         MOVS       R0, #0
+  0x080039F2:  7008         STRB       R0, [R1]
+  0x080039F4:  49BD         LDR        R1, =onTimeCounterRESET  ; [PC, #0x02F4] [0x08003CEC] =0x200006A0 
+  0x080039F6:  9B16         LDR        R3, [SP, #88]
+  0x080039F8:  600B         STR        R3, [R1]
+  0x080039FA:  9920         LDR        R1, [SP, #128]
+  0x080039FC:  6091         STR        R1, [R2, #8]
+  0x080039FE:  9910         LDR        R1, [SP, #64]
+  0x08003A00:  31F4         ADDS       R1, #244
+  0x08003A02:  4ABB         LDR        R2, =onTimeCounter       ; [PC, #0x02EC] [0x08003CF0] =0x200006A8 
+  0x08003A04:  6011         STR        R1, [R2]
+  0x08003A06:  4BBB         LDR        R3, =0x50000818          ; [PC, #0x02EC] [0x08003CF4] 
+  0x08003A08:  991F         LDR        R1, [SP, #124]
+  0x08003A0A:  6119         STR        R1, [R3, #16]
+  0x08003A0C:  49BA         LDR        R1, =offTimeCounterGN    ; [PC, #0x02E8] [0x08003CF8] =0x200006B4 
+  0x08003A0E:  6008         STR        R0, [R1]
+  0x08003A10:  49BA         LDR        R1, =blinkModeGN         ; [PC, #0x02E8] [0x08003CFC] =0x20000758 
+  0x08003A12:  7008         STRB       R0, [R1]
+  0x08003A14:  49BA         LDR        R1, =onTimeCounterGN     ; [PC, #0x02E8] [0x08003D00] =0x200006A4 
+  0x08003A16:  6008         STR        R0, [R1]
+  0x08003A18:  49BA         LDR        R1, =onTimeRT            ; [PC, #0x02E8] [0x08003D04] =0x2000073C 
+  0x08003A1A:  700D         STRB       R5, [R1]
+  0x08003A1C:  49BA         LDR        R1, =offTimeRT           ; [PC, #0x02E8] [0x08003D08] =0x20000748 
+  0x08003A1E:  700D         STRB       R5, [R1]
+  0x08003A20:  49BA         LDR        R1, =blinkModeRT         ; [PC, #0x02E8] [0x08003D0C] =0x20000754 
+  0x08003A22:  700D         STRB       R5, [R1]
+  0x08003A24:  49BA         LDR        R1, =numberOfBlinks      ; [PC, #0x02E8] [0x08003D10] =0x200006BC 
+  0x08003A26:  2205         MOVS       R2, #5
+  0x08003A28:  600A         STR        R2, [R1]
+  0x08003A2A:  49BA         LDR        R1, =blinkCounter        ; [PC, #0x02E8] [0x08003D14] =0x200006EC 
+  0x08003A2C:  600A         STR        R2, [R1]
+  0x08003A2E:  49BA         LDR        R1, =pauseTime           ; [PC, #0x02E8] [0x08003D18] =0x20000734 
+  0x08003A30:  700D         STRB       R5, [R1]
+  0x08003A32:  991E         LDR        R1, [SP, #120]
+  0x08003A34:  6019         STR        R1, [R3]
+  0x08003A36:  49B9         LDR        R1, =buttonState         ; [PC, #0x02E4] [0x08003D1C] =0x2000073A 
+  0x08003A38:  7008         STRB       R0, [R1]
+  0x08003A3A:  48B9         LDR        R0, =onTimeCounterRT     ; [PC, #0x02E4] [0x08003D20] =0x2000069C 
+  0x08003A3C:  21C8         MOVS       R1, #200
+  0x08003A3E:  6001         STR        R1, [R0]
+  0x08003A40:  48BC         LDR        R0, =0x0800632C          ; [PC, #0x02F0] [0x08003D34] 
+  0x08003A42:  F001 FBD5    BL         puts                     ; 0x080051F0
+  0x08003A46:  2003         MOVS       R0, #3
+  0x08003A48:  49B8         LDR        R1, =smState             ; [PC, #0x02E0] [0x08003D2C] =0x20000737 
+  0x08003A4A:  7008         STRB       R0, [R1]
+
.L209:
+  0x08003A4C:  48A5         LDR        R0, =LVP_SM_On.lvpInput  ; [PC, #0x0294] [0x08003CE4] =0x20000764 
+  0x08003A4E:  4EA6         LDR        R6, =relaisState         ; [PC, #0x0298] [0x08003CE8] =0x20000730 
+  0x08003A50:  7800         LDRB       R0, [R0]
+  0x08003A52:  2801         CMP        R0, #1
+  0x08003A54:  7830         LDRB       R0, [R6]
+  0x08003A56:  D137         BNE        .L210                    ; 0x08003AC8
+  0x08003A58:  2800         CMP        R0, #0
+  0x08003A5A:  D05B         BEQ        .L211                    ; 0x08003B14
+  0x08003A5C:  4A9B         LDR        R2, =0x50000410          ; [PC, #0x026C] [0x08003CCC] 
+  0x08003A5E:  981B         LDR        R0, [SP, #108]
+  0x08003A60:  6190         STR        R0, [R2, #24]
+  0x08003A62:  981A         LDR        R0, [SP, #104]
+  0x08003A64:  6090         STR        R0, [R2, #8]
+  0x08003A66:  2000         MOVS       R0, #0
+  0x08003A68:  7030         STRB       R0, [R6]
+  0x08003A6A:  49A0         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0280] [0x08003CEC] =0x200006A0 
+  0x08003A6C:  9B16         LDR        R3, [SP, #88]
+  0x08003A6E:  600B         STR        R3, [R1]
+  0x08003A70:  9920         LDR        R1, [SP, #128]
+  0x08003A72:  6091         STR        R1, [R2, #8]
+  0x08003A74:  9910         LDR        R1, [SP, #64]
+  0x08003A76:  31F4         ADDS       R1, #244
+  0x08003A78:  4A9D         LDR        R2, =onTimeCounter       ; [PC, #0x0274] [0x08003CF0] =0x200006A8 
+  0x08003A7A:  6011         STR        R1, [R2]
+  0x08003A7C:  4A9D         LDR        R2, =0x50000818          ; [PC, #0x0274] [0x08003CF4] 
+  0x08003A7E:  991F         LDR        R1, [SP, #124]
+  0x08003A80:  6111         STR        R1, [R2, #16]
+  0x08003A82:  499D         LDR        R1, =offTimeCounterGN    ; [PC, #0x0274] [0x08003CF8] =0x200006B4 
+  0x08003A84:  6008         STR        R0, [R1]
+  0x08003A86:  499D         LDR        R1, =blinkModeGN         ; [PC, #0x0274] [0x08003CFC] =0x20000758 
+  0x08003A88:  7008         STRB       R0, [R1]
+  0x08003A8A:  499D         LDR        R1, =onTimeCounterGN     ; [PC, #0x0274] [0x08003D00] =0x200006A4 
+  0x08003A8C:  6008         STR        R0, [R1]
+  0x08003A8E:  489D         LDR        R0, =onTimeRT            ; [PC, #0x0274] [0x08003D04] =0x2000073C 
+  0x08003A90:  7005         STRB       R5, [R0]
+  0x08003A92:  489D         LDR        R0, =offTimeRT           ; [PC, #0x0274] [0x08003D08] =0x20000748 
+  0x08003A94:  7005         STRB       R5, [R0]
+  0x08003A96:  489D         LDR        R0, =blinkModeRT         ; [PC, #0x0274] [0x08003D0C] =0x20000754 
+  0x08003A98:  7005         STRB       R5, [R0]
+  0x08003A9A:  489D         LDR        R0, =numberOfBlinks      ; [PC, #0x0274] [0x08003D10] =0x200006BC 
+  0x08003A9C:  2102         MOVS       R1, #2
+  0x08003A9E:  6001         STR        R1, [R0]
+  0x08003AA0:  489C         LDR        R0, =blinkCounter        ; [PC, #0x0270] [0x08003D14] =0x200006EC 
+  0x08003AA2:  6001         STR        R1, [R0]
+  0x08003AA4:  489C         LDR        R0, =pauseTime           ; [PC, #0x0270] [0x08003D18] =0x20000734 
+  0x08003AA6:  7005         STRB       R5, [R0]
+  0x08003AA8:  981E         LDR        R0, [SP, #120]
+  0x08003AAA:  6010         STR        R0, [R2]
+  0x08003AAC:  489C         LDR        R0, =onTimeCounterRT     ; [PC, #0x0270] [0x08003D20] =0x2000069C 
+  0x08003AAE:  21C8         MOVS       R1, #200
+  0x08003AB0:  6001         STR        R1, [R0]
+  0x08003AB2:  48A1         LDR        R0, =0x08006659          ; [PC, #0x0284] [0x08003D38] 
+  0x08003AB4:  F001 FB9C    BL         puts                     ; 0x080051F0
+  0x08003AB8:  48A0         LDR        R0, =0x0800625F          ; [PC, #0x0280] [0x08003D3C] 
+  0x08003ABA:  F001 FB99    BL         puts                     ; 0x080051F0
+  0x08003ABE:  4889         LDR        R0, =LVP_SM_On.lvpInput  ; [PC, #0x0224] [0x08003CE4] =0x20000764 
+  0x08003AC0:  7800         LDRB       R0, [R0]
+  0x08003AC2:  2800         CMP        R0, #0
+  0x08003AC4:  D126         BNE        .L211                    ; 0x08003B14
+  0x08003AC6:  7830         LDRB       R0, [R6]
+
.L210:
+  0x08003AC8:  2800         CMP        R0, #0
+  0x08003ACA:  D123         BNE        .L211                    ; 0x08003B14
+  0x08003ACC:  497F         LDR        R1, =0x50000410          ; [PC, #0x01FC] [0x08003CCC] 
+  0x08003ACE:  981A         LDR        R0, [SP, #104]
+  0x08003AD0:  6188         STR        R0, [R1, #24]
+  0x08003AD2:  981B         LDR        R0, [SP, #108]
+  0x08003AD4:  6088         STR        R0, [R1, #8]
+  0x08003AD6:  7035         STRB       R5, [R6]
+  0x08003AD8:  4899         LDR        R0, =onTimeCounterSET    ; [PC, #0x0264] [0x08003D40] =0x20000698 
+  0x08003ADA:  9A16         LDR        R2, [SP, #88]
+  0x08003ADC:  6002         STR        R2, [R0]
+  0x08003ADE:  9820         LDR        R0, [SP, #128]
+  0x08003AE0:  6088         STR        R0, [R1, #8]
+  0x08003AE2:  4883         LDR        R0, =onTimeCounter       ; [PC, #0x020C] [0x08003CF0] =0x200006A8 
+  0x08003AE4:  21C8         MOVS       R1, #200
+  0x08003AE6:  6001         STR        R1, [R0]
+  0x08003AE8:  4B82         LDR        R3, =0x50000818          ; [PC, #0x0208] [0x08003CF4] 
+  0x08003AEA:  9F1F         LDR        R7, [SP, #124]
+  0x08003AEC:  611F         STR        R7, [R3, #16]
+  0x08003AEE:  4895         LDR        R0, =onTimeGN            ; [PC, #0x0254] [0x08003D44] =0x20000740 
+  0x08003AF0:  7005         STRB       R5, [R0]
+  0x08003AF2:  4881         LDR        R0, =offTimeCounterGN    ; [PC, #0x0204] [0x08003CF8] =0x200006B4 
+  0x08003AF4:  2200         MOVS       R2, #0
+  0x08003AF6:  6002         STR        R2, [R0]
+  0x08003AF8:  4893         LDR        R0, =offTimeGN           ; [PC, #0x024C] [0x08003D48] =0x2000074C 
+  0x08003AFA:  7005         STRB       R5, [R0]
+  0x08003AFC:  487F         LDR        R0, =blinkModeGN         ; [PC, #0x01FC] [0x08003CFC] =0x20000758 
+  0x08003AFE:  7005         STRB       R5, [R0]
+  0x08003B00:  601F         STR        R7, [R3]
+  0x08003B02:  4627         MOV        R7, R4
+  0x08003B04:  487E         LDR        R0, =onTimeCounterGN     ; [PC, #0x01F8] [0x08003D00] =0x200006A4 
+  0x08003B06:  6001         STR        R1, [R0]
+  0x08003B08:  4890         LDR        R0, =0x080068E4          ; [PC, #0x0240] [0x08003D4C] 
+  0x08003B0A:  F001 FB71    BL         puts                     ; 0x080051F0
+  0x08003B0E:  4890         LDR        R0, =0x0800649D          ; [PC, #0x0240] [0x08003D50] 
+  0x08003B10:  F001 FB6E    BL         puts                     ; 0x080051F0
+
.L211:
+  0x08003B14:  4881         LDR        R0, =buttonState         ; [PC, #0x0204] [0x08003D1C] =0x2000073A 
+  0x08003B16:  7800         LDRB       R0, [R0]
+  0x08003B18:  2800         CMP        R0, #0
+  0x08003B1A:  D000         BEQ        .L212                    ; 0x08003B1E
+  0x08003B1C:  E2FA         B          .L252                    ; 0x08004114
+
.L212:
+  0x08003B1E:  496B         LDR        R1, =0x50000410          ; [PC, #0x01AC] [0x08003CCC] 
+  0x08003B20:  981B         LDR        R0, [SP, #108]
+  0x08003B22:  6188         STR        R0, [R1, #24]
+  0x08003B24:  981A         LDR        R0, [SP, #104]
+  0x08003B26:  6088         STR        R0, [R1, #8]
+  0x08003B28:  2700         MOVS       R7, #0
+  0x08003B2A:  7037         STRB       R7, [R6]
+  0x08003B2C:  486F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01BC] [0x08003CEC] =0x200006A0 
+  0x08003B2E:  9A16         LDR        R2, [SP, #88]
+  0x08003B30:  6002         STR        R2, [R0]
+  0x08003B32:  9820         LDR        R0, [SP, #128]
+  0x08003B34:  6088         STR        R0, [R1, #8]
+  0x08003B36:  486E         LDR        R0, =onTimeCounter       ; [PC, #0x01B8] [0x08003CF0] =0x200006A8 
+  0x08003B38:  21C8         MOVS       R1, #200
+  0x08003B3A:  6001         STR        R1, [R0]
+  0x08003B3C:  496D         LDR        R1, =0x50000818          ; [PC, #0x01B4] [0x08003CF4] 
+  0x08003B3E:  981F         LDR        R0, [SP, #124]
+  0x08003B40:  6108         STR        R0, [R1, #16]
+  0x08003B42:  486D         LDR        R0, =offTimeCounterGN    ; [PC, #0x01B4] [0x08003CF8] =0x200006B4 
+  0x08003B44:  6007         STR        R7, [R0]
+  0x08003B46:  486D         LDR        R0, =blinkModeGN         ; [PC, #0x01B4] [0x08003CFC] =0x20000758 
+  0x08003B48:  7007         STRB       R7, [R0]
+  0x08003B4A:  486D         LDR        R0, =onTimeCounterGN     ; [PC, #0x01B4] [0x08003D00] =0x200006A4 
+  0x08003B4C:  6007         STR        R7, [R0]
+  0x08003B4E:  981E         LDR        R0, [SP, #120]
+  0x08003B50:  6108         STR        R0, [R1, #16]
+  0x08003B52:  4880         LDR        R0, =offTimeCounterRT    ; [PC, #0x0200] [0x08003D54] =0x200006B0 
+  0x08003B54:  6007         STR        R7, [R0]
+  0x08003B56:  486D         LDR        R0, =blinkModeRT         ; [PC, #0x01B4] [0x08003D0C] =0x20000754 
+  0x08003B58:  7007         STRB       R7, [R0]
+  0x08003B5A:  4871         LDR        R0, =onTimeCounterRT     ; [PC, #0x01C4] [0x08003D20] =0x2000069C 
+  0x08003B5C:  6007         STR        R7, [R0]
+  0x08003B5E:  487E         LDR        R0, =0x08006282          ; [PC, #0x01F8] [0x08003D58] 
+  0x08003B60:  F001 FB46    BL         puts                     ; 0x080051F0
+  0x08003B64:  4871         LDR        R0, =smState             ; [PC, #0x01C4] [0x08003D2C] =0x20000737 
+  0x08003B66:  7007         STRB       R7, [R0]
+  0x08003B68:  485C         LDR        R0, =LVP_SM_On.lvpTimeCounter ; [PC, #0x0170] [0x08003CDC] =0x20000724 
+  0x08003B6A:  6007         STR        R7, [R0]
+  0x08003B6C:  485D         LDR        R0, =LVP_SM_On.lvpInput  ; [PC, #0x0174] [0x08003CE4] =0x20000764 
+
.L213:
+  0x08003B6E:  7007         STRB       R7, [R0]
+  0x08003B70:  4F7A         LDR        R7, =0x000003C7          ; [PC, #0x01E8] [0x08003D5C] 
+  0x08003B72:  E2CF         B          .L252                    ; 0x08004114
+
.L214:
+  0x08003B74:  497A         LDR        R1, =sys_data            ; [PC, #0x01E8] [0x08003D60] =0x20000234 
+  0x08003B76:  8B09         LDRH       R1, [R1, #24]
+  0x08003B78:  2B00         CMP        R3, #0
+  0x08003B7A:  D001         BEQ        .L215                    ; 0x08003B80
+  0x08003B7C:  4299         CMP        R1, R3
+  0x08003B7E:  D112         BNE        .L218                    ; 0x08003BA6
+
.L215:
+  0x08003B80:  212A         MOVS       R1, #42
+  0x08003B82:  5C62         LDRB       R2, [R4, R1]
+  0x08003B84:  2129         MOVS       R1, #41
+  0x08003B86:  5C61         LDRB       R1, [R4, R1]
+  0x08003B88:  0209         LSLS       R1, R1, #8
+  0x08003B8A:  1889         ADDS       R1, R1, R2
+  0x08003B8C:  2970         CMP        R1, #112
+  0x08003B8E:  D200         BCS        .L216                    ; 0x08003B92
+  0x08003B90:  E343         B          .L260                    ; 0x0800421A
+
.L216:
+  0x08003B92:  2125         MOVS       R1, #37
+  0x08003B94:  00C9         LSLS       R1, R1, #3
+  0x08003B96:  4A73         LDR        R2, =0x00000286          ; [PC, #0x01CC] [0x08003D64] 
+  0x08003B98:  E022         B          .L222                    ; 0x08003BE0
+
.L217:
+  0x08003B9A:  4971         LDR        R1, =sys_data            ; [PC, #0x01C4] [0x08003D60] =0x20000234 
+  0x08003B9C:  8B09         LDRH       R1, [R1, #24]
+  0x08003B9E:  2B00         CMP        R3, #0
+  0x08003BA0:  D010         BEQ        .L220                    ; 0x08003BC4
+  0x08003BA2:  4299         CMP        R1, R3
+  0x08003BA4:  D00E         BEQ        .L220                    ; 0x08003BC4
+
.L218:
+  0x08003BA6:  2125         MOVS       R1, #37
+  0x08003BA8:  00C9         LSLS       R1, R1, #3
+  0x08003BAA:  4A6F         LDR        R2, =0x00000B86          ; [PC, #0x01BC] [0x08003D68] 
+  0x08003BAC:  E018         B          .L222                    ; 0x08003BE0
+
.L219:
+  0x08003BAE:  9913         LDR        R1, [SP, #76]
+  0x08003BB0:  312A         ADDS       R1, #42
+  0x08003BB2:  2301         MOVS       R3, #1
+  0x08003BB4:  5463         STRB       R3, [R4, R1]
+  0x08003BB6:  990A         LDR        R1, [SP, #40]
+  0x08003BB8:  404A         EORS       R2, R1
+  0x08003BBA:  2125         MOVS       R1, #37
+  0x08003BBC:  00C9         LSLS       R1, R1, #3
+  0x08003BBE:  5462         STRB       R2, [R4, R1]
+  0x08003BC0:  2603         MOVS       R6, #3
+  0x08003BC2:  E3BC         B          .L270                    ; 0x0800433E
+
.L220:
+  0x08003BC4:  9908         LDR        R1, [SP, #32]
+  0x08003BC6:  5C60         LDRB       R0, [R4, R1]
+  0x08003BC8:  222B         MOVS       R2, #43
+  0x08003BCA:  5CA2         LDRB       R2, [R4, R2]
+  0x08003BCC:  0212         LSLS       R2, R2, #8
+  0x08003BCE:  1816         ADDS       R6, R2, R0
+  0x08003BD0:  D002         BEQ        .L221                    ; 0x08003BD8
+  0x08003BD2:  2E7C         CMP        R6, #124
+  0x08003BD4:  D200         BCS        .L221                    ; 0x08003BD8
+  0x08003BD6:  E339         B          .L261                    ; 0x0800424C
+
.L221:
+  0x08003BD8:  2125         MOVS       R1, #37
+  0x08003BDA:  00C9         LSLS       R1, R1, #3
+  0x08003BDC:  2239         MOVS       R2, #57
+  0x08003BDE:  0112         LSLS       R2, R2, #4
+
.L222:
+  0x08003BE0:  5262         STRH       R2, [R4, R1]
+  0x08003BE2:  2603         MOVS       R6, #3
+  0x08003BE4:  E3AB         B          .L270                    ; 0x0800433E
+
.L223:
+  0x08003BE6:  9A08         LDR        R2, [SP, #32]
+  0x08003BE8:  5CA0         LDRB       R0, [R4, R2]
+  0x08003BEA:  222B         MOVS       R2, #43
+  0x08003BEC:  5CA2         LDRB       R2, [R4, R2]
+  0x08003BEE:  0214         LSLS       R4, R2, #8
+  0x08003BF0:  2203         MOVS       R2, #3
+  0x08003BF2:  2383         MOVS       R3, #131
+  0x08003BF4:  1824         ADDS       R4, R4, R0
+  0x08003BF6:  D002         BEQ        .L224                    ; 0x08003BFE
+  0x08003BF8:  2C7D         CMP        R4, #125
+  0x08003BFA:  D800         BHI        .L224                    ; 0x08003BFE
+  0x08003BFC:  E33B         B          .L262                    ; 0x08004276
+
.L224:
+  0x08003BFE:  4C5B         LDR        R4, =modbusData          ; [PC, #0x016C] [0x08003D6C] =0x20000000 
+
.L225:
+  0x08003C00:  9913         LDR        R1, [SP, #76]
+  0x08003C02:  312A         ADDS       R1, #42
+  0x08003C04:  5462         STRB       R2, [R4, R1]
+  0x08003C06:  2125         MOVS       R1, #37
+  0x08003C08:  00C9         LSLS       R1, R1, #3
+  0x08003C0A:  5463         STRB       R3, [R4, R1]
+  0x08003C0C:  2603         MOVS       R6, #3
+  0x08003C0E:  E396         B          .L270                    ; 0x0800433E
+
.L226:
+  0x08003C10:  492E         LDR        R1, =0x50000410          ; [PC, #184] [0x08003CCC] 
+  0x08003C12:  981A         LDR        R0, [SP, #104]
+  0x08003C14:  6188         STR        R0, [R1, #24]
+  0x08003C16:  981B         LDR        R0, [SP, #108]
+  0x08003C18:  6088         STR        R0, [R1, #8]
+  0x08003C1A:  4833         LDR        R0, =relaisState         ; [PC, #204] [0x08003CE8] =0x20000730 
+  0x08003C1C:  7005         STRB       R5, [R0]
+  0x08003C1E:  4848         LDR        R0, =onTimeCounterSET    ; [PC, #0x0120] [0x08003D40] =0x20000698 
+  0x08003C20:  9A16         LDR        R2, [SP, #88]
+  0x08003C22:  6002         STR        R2, [R0]
+  0x08003C24:  9820         LDR        R0, [SP, #128]
+  0x08003C26:  6088         STR        R0, [R1, #8]
+  0x08003C28:  4846         LDR        R0, =onTimeGN            ; [PC, #0x0118] [0x08003D44] =0x20000740 
+  0x08003C2A:  7005         STRB       R5, [R0]
+  0x08003C2C:  4830         LDR        R0, =onTimeCounter       ; [PC, #192] [0x08003CF0] =0x200006A8 
+  0x08003C2E:  21C8         MOVS       R1, #200
+  0x08003C30:  6001         STR        R1, [R0]
+  0x08003C32:  4845         LDR        R0, =offTimeGN           ; [PC, #0x0114] [0x08003D48] =0x2000074C 
+  0x08003C34:  7005         STRB       R5, [R0]
+  0x08003C36:  4831         LDR        R0, =blinkModeGN         ; [PC, #196] [0x08003CFC] =0x20000758 
+  0x08003C38:  7005         STRB       R5, [R0]
+  0x08003C3A:  4A2E         LDR        R2, =0x50000818          ; [PC, #184] [0x08003CF4] 
+  0x08003C3C:  981F         LDR        R0, [SP, #124]
+  0x08003C3E:  6010         STR        R0, [R2]
+  0x08003C40:  482F         LDR        R0, =onTimeCounterGN     ; [PC, #188] [0x08003D00] =0x200006A4 
+  0x08003C42:  6001         STR        R1, [R0]
+  0x08003C44:  981E         LDR        R0, [SP, #120]
+  0x08003C46:  6110         STR        R0, [R2, #16]
+  0x08003C48:  4842         LDR        R0, =offTimeCounterRT    ; [PC, #0x0108] [0x08003D54] =0x200006B0 
+  0x08003C4A:  2100         MOVS       R1, #0
+  0x08003C4C:  6001         STR        R1, [R0]
+  0x08003C4E:  482F         LDR        R0, =blinkModeRT         ; [PC, #188] [0x08003D0C] =0x20000754 
+  0x08003C50:  7001         STRB       R1, [R0]
+  0x08003C52:  4833         LDR        R0, =onTimeCounterRT     ; [PC, #204] [0x08003D20] =0x2000069C 
+  0x08003C54:  6001         STR        R1, [R0]
+  0x08003C56:  4846         LDR        R0, =0x08006537          ; [PC, #0x0118] [0x08003D70] 
+  0x08003C58:  F001 FACA    BL         puts                     ; 0x080051F0
+  0x08003C5C:  4845         LDR        R0, =smState.145         ; [PC, #0x0114] [0x08003D74] =0x20000733 
+  0x08003C5E:  7005         STRB       R5, [R0]
+  0x08003C60:  7830         LDRB       R0, [R6]
+
.L227:
+  0x08003C62:  2802         CMP        R0, #2
+  0x08003C64:  D000         BEQ        .L228                    ; 0x08003C68
+  0x08003C66:  E255         B          .L252                    ; 0x08004114
+
.L228:
+  0x08003C68:  4918         LDR        R1, =0x50000410          ; [PC, #96] [0x08003CCC] 
+  0x08003C6A:  981A         LDR        R0, [SP, #104]
+  0x08003C6C:  6188         STR        R0, [R1, #24]
+  0x08003C6E:  981B         LDR        R0, [SP, #108]
+  0x08003C70:  6088         STR        R0, [R1, #8]
+  0x08003C72:  481D         LDR        R0, =relaisState         ; [PC, #116] [0x08003CE8] =0x20000730 
+  0x08003C74:  7005         STRB       R5, [R0]
+  0x08003C76:  4832         LDR        R0, =onTimeCounterSET    ; [PC, #200] [0x08003D40] =0x20000698 
+  0x08003C78:  9A16         LDR        R2, [SP, #88]
+  0x08003C7A:  6002         STR        R2, [R0]
+  0x08003C7C:  483E         LDR        R0, =onTime              ; [PC, #248] [0x08003D78] =0x20000744 
+  0x08003C7E:  7005         STRB       R5, [R0]
+  0x08003C80:  483E         LDR        R0, =offTime             ; [PC, #248] [0x08003D7C] =0x20000750 
+  0x08003C82:  7005         STRB       R5, [R0]
+  0x08003C84:  483E         LDR        R0, =alarmMode           ; [PC, #248] [0x08003D80] =0x2000075C 
+  0x08003C86:  7005         STRB       R5, [R0]
+  0x08003C88:  9820         LDR        R0, [SP, #128]
+  0x08003C8A:  6088         STR        R0, [R1, #8]
+  0x08003C8C:  4918         LDR        R1, =onTimeCounter       ; [PC, #96] [0x08003CF0] =0x200006A8 
+  0x08003C8E:  20C8         MOVS       R0, #200
+  0x08003C90:  6008         STR        R0, [R1]
+  0x08003C92:  4B18         LDR        R3, =0x50000818          ; [PC, #96] [0x08003CF4] 
+  0x08003C94:  991F         LDR        R1, [SP, #124]
+  0x08003C96:  6019         STR        R1, [R3]
+  0x08003C98:  4919         LDR        R1, =onTimeCounterGN     ; [PC, #100] [0x08003D00] =0x200006A4 
+  0x08003C9A:  2200         MOVS       R2, #0
+  0x08003C9C:  600A         STR        R2, [R1]
+  0x08003C9E:  4917         LDR        R1, =blinkModeGN         ; [PC, #92] [0x08003CFC] =0x20000758 
+  0x08003CA0:  700A         STRB       R2, [R1]
+  0x08003CA2:  4915         LDR        R1, =offTimeCounterGN    ; [PC, #84] [0x08003CF8] =0x200006B4 
+  0x08003CA4:  600A         STR        R2, [R1]
+  0x08003CA6:  9E1E         LDR        R6, [SP, #120]
+  0x08003CA8:  611E         STR        R6, [R3, #16]
+  0x08003CAA:  4916         LDR        R1, =onTimeRT            ; [PC, #88] [0x08003D04] =0x2000073C 
+  0x08003CAC:  700D         STRB       R5, [R1]
+  0x08003CAE:  4929         LDR        R1, =offTimeCounterRT    ; [PC, #164] [0x08003D54] =0x200006B0 
+  0x08003CB0:  600A         STR        R2, [R1]
+  0x08003CB2:  4915         LDR        R1, =offTimeRT           ; [PC, #84] [0x08003D08] =0x20000748 
+  0x08003CB4:  700D         STRB       R5, [R1]
+  0x08003CB6:  4915         LDR        R1, =blinkModeRT         ; [PC, #84] [0x08003D0C] =0x20000754 
+  0x08003CB8:  700D         STRB       R5, [R1]
+  0x08003CBA:  4915         LDR        R1, =numberOfBlinks      ; [PC, #84] [0x08003D10] =0x200006BC 
+  0x08003CBC:  600D         STR        R5, [R1]
+  0x08003CBE:  4915         LDR        R1, =blinkCounter        ; [PC, #84] [0x08003D14] =0x200006EC 
+  0x08003CC0:  600D         STR        R5, [R1]
+  0x08003CC2:  4915         LDR        R1, =pauseTime           ; [PC, #84] [0x08003D18] =0x20000734 
+  0x08003CC4:  700D         STRB       R5, [R1]
+  0x08003CC6:  601E         STR        R6, [R3]
+  0x08003CC8:  E0AF         B          .L233                    ; 0x08003E2A
+  0x08003CCA:  46C0         NOP
+  0x08003CCC:  50000410     DC.W       0x50000410
+  0x08003CD0:  50000010     DC.W       0x50000010
+  0x08003CD4:  20000720     DC.W       LVP_SM_On.oldtime
+  0x08003CD8:  2000068C     DC.W       uwTick
+  0x08003CDC:  20000724     DC.W       LVP_SM_On.lvpTimeCounter
+  0x08003CE0:  00001388     DC.W       0x00001388
+  0x08003CE4:  20000764     DC.W       LVP_SM_On.lvpInput
+  0x08003CE8:  20000730     DC.W       relaisState
+  0x08003CEC:  200006A0     DC.W       onTimeCounterRESET
+  0x08003CF0:  200006A8     DC.W       onTimeCounter
+  0x08003CF4:  50000818     DC.W       0x50000818
+  0x08003CF8:  200006B4     DC.W       offTimeCounterGN
+  0x08003CFC:  20000758     DC.W       blinkModeGN
+  0x08003D00:  200006A4     DC.W       onTimeCounterGN
+  0x08003D04:  2000073C     DC.W       onTimeRT
+  0x08003D08:  20000748     DC.W       offTimeRT
+  0x08003D0C:  20000754     DC.W       blinkModeRT
+  0x08003D10:  200006BC     DC.W       numberOfBlinks
+  0x08003D14:  200006EC     DC.W       blinkCounter
+  0x08003D18:  20000734     DC.W       pauseTime
+  0x08003D1C:  2000073A     DC.W       buttonState
+  0x08003D20:  2000069C     DC.W       onTimeCounterRT
+  0x08003D24:  0800698C     DC.W       0800698C               ; R_ARM_ABS32
+  0x08003D28:  08006644     DC.W       08006644               ; R_ARM_ABS32
+  0x08003D2C:  20000737     DC.W       smState
+  0x08003D30:  20000690     DC.W       temp
+  0x08003D34:  0800632C     DC.W       0800632C               ; R_ARM_ABS32
+  0x08003D38:  08006659     DC.W       08006659               ; R_ARM_ABS32
+  0x08003D3C:  0800625F     DC.W       0800625F               ; R_ARM_ABS32
+  0x08003D40:  20000698     DC.W       onTimeCounterSET
+  0x08003D44:  20000740     DC.W       onTimeGN
+  0x08003D48:  2000074C     DC.W       offTimeGN
+  0x08003D4C:  080068E4     DC.W       080068E4               ; R_ARM_ABS32
+  0x08003D50:  0800649D     DC.W       0800649D               ; R_ARM_ABS32
+  0x08003D54:  200006B0     DC.W       offTimeCounterRT
+  0x08003D58:  08006282     DC.W       08006282               ; R_ARM_ABS32
+  0x08003D5C:  000003C7     DC.W       0x000003C7
+  0x08003D60:  20000234     DC.W       sys_data
+  0x08003D64:  00000286     DC.W       0x00000286
+  0x08003D68:  00000B86     DC.W       0x00000B86
+  0x08003D6C:  20000000     DC.W       modbusData
+  0x08003D70:  08006537     DC.W       08006537               ; R_ARM_ABS32
+  0x08003D74:  20000733     DC.W       smState.145
+  0x08003D78:  20000744     DC.W       onTime
+  0x08003D7C:  20000750     DC.W       offTime
+  0x08003D80:  2000075C     DC.W       alarmMode
+
.L229:
+  0x08003D84:  49F2         LDR        R1, =0x50000410          ; [PC, #0x03C8] [0x08004150] 
+  0x08003D86:  981A         LDR        R0, [SP, #104]
+  0x08003D88:  6188         STR        R0, [R1, #24]
+  0x08003D8A:  981B         LDR        R0, [SP, #108]
+  0x08003D8C:  6088         STR        R0, [R1, #8]
+  0x08003D8E:  48F1         LDR        R0, =relaisState         ; [PC, #0x03C4] [0x08004154] =0x20000730 
+  0x08003D90:  7005         STRB       R5, [R0]
+  0x08003D92:  48F1         LDR        R0, =onTimeCounterSET    ; [PC, #0x03C4] [0x08004158] =0x20000698 
+  0x08003D94:  9A16         LDR        R2, [SP, #88]
+  0x08003D96:  6002         STR        R2, [R0]
+  0x08003D98:  9820         LDR        R0, [SP, #128]
+  0x08003D9A:  6088         STR        R0, [R1, #8]
+  0x08003D9C:  48EF         LDR        R0, =offTimeGN           ; [PC, #0x03BC] [0x0800415C] =0x2000074C 
+  0x08003D9E:  7005         STRB       R5, [R0]
+  0x08003DA0:  48EF         LDR        R0, =onTimeGN            ; [PC, #0x03BC] [0x08004160] =0x20000740 
+  0x08003DA2:  7005         STRB       R5, [R0]
+  0x08003DA4:  48EF         LDR        R0, =0x080064F3          ; [PC, #0x03BC] [0x08004164] 
+  0x08003DA6:  49F0         LDR        R1, =onTimeCounterGN     ; [PC, #0x03C0] [0x08004168] =0x200006A4 
+  0x08003DA8:  4BF0         LDR        R3, =blinkModeGN         ; [PC, #0x03C0] [0x0800416C] =0x20000758 
+  0x08003DAA:  22C8         MOVS       R2, #200
+  0x08003DAC:  9E1F         LDR        R6, [SP, #124]
+  0x08003DAE:  462F         MOV        R7, R5
+
.L230:
+  0x08003DB0:  701D         STRB       R5, [R3]
+  0x08003DB2:  4BEF         LDR        R3, =onTimeCounter       ; [PC, #0x03BC] [0x08004170] =0x200006A8 
+  0x08003DB4:  601A         STR        R2, [R3]
+  0x08003DB6:  4AEF         LDR        R2, =0x50000818          ; [PC, #0x03BC] [0x08004174] 
+  0x08003DB8:  6016         STR        R6, [R2]
+  0x08003DBA:  22C8         MOVS       R2, #200
+  0x08003DBC:  600A         STR        R2, [R1]
+  0x08003DBE:  F001 FA17    BL         puts                     ; 0x080051F0
+  0x08003DC2:  48ED         LDR        R0, =smState.145         ; [PC, #0x03B4] [0x08004178] =0x20000733 
+  0x08003DC4:  7007         STRB       R7, [R0]
+  0x08003DC6:  7820         LDRB       R0, [R4]
+  0x08003DC8:  4FEC         LDR        R7, =0x000003C7          ; [PC, #0x03B0] [0x0800417C] 
+
.L231:
+  0x08003DCA:  2802         CMP        R0, #2
+  0x08003DCC:  D000         BEQ        .L232                    ; 0x08003DD0
+  0x08003DCE:  E1A1         B          .L252                    ; 0x08004114
+
.L232:
+  0x08003DD0:  49DF         LDR        R1, =0x50000410          ; [PC, #0x037C] [0x08004150] 
+  0x08003DD2:  981A         LDR        R0, [SP, #104]
+  0x08003DD4:  6188         STR        R0, [R1, #24]
+  0x08003DD6:  981B         LDR        R0, [SP, #108]
+  0x08003DD8:  6088         STR        R0, [R1, #8]
+  0x08003DDA:  48DE         LDR        R0, =relaisState         ; [PC, #0x0378] [0x08004154] =0x20000730 
+  0x08003DDC:  7005         STRB       R5, [R0]
+  0x08003DDE:  48DE         LDR        R0, =onTimeCounterSET    ; [PC, #0x0378] [0x08004158] =0x20000698 
+  0x08003DE0:  9A16         LDR        R2, [SP, #88]
+  0x08003DE2:  6002         STR        R2, [R0]
+  0x08003DE4:  48E6         LDR        R0, =onTime              ; [PC, #0x0398] [0x08004180] =0x20000744 
+  0x08003DE6:  7005         STRB       R5, [R0]
+  0x08003DE8:  48E6         LDR        R0, =offTime             ; [PC, #0x0398] [0x08004184] =0x20000750 
+  0x08003DEA:  7005         STRB       R5, [R0]
+  0x08003DEC:  48E6         LDR        R0, =alarmMode           ; [PC, #0x0398] [0x08004188] =0x2000075C 
+  0x08003DEE:  7005         STRB       R5, [R0]
+  0x08003DF0:  9820         LDR        R0, [SP, #128]
+  0x08003DF2:  6088         STR        R0, [R1, #8]
+  0x08003DF4:  49DE         LDR        R1, =onTimeCounter       ; [PC, #0x0378] [0x08004170] =0x200006A8 
+  0x08003DF6:  20C8         MOVS       R0, #200
+  0x08003DF8:  6008         STR        R0, [R1]
+  0x08003DFA:  4BDE         LDR        R3, =0x50000818          ; [PC, #0x0378] [0x08004174] 
+  0x08003DFC:  991F         LDR        R1, [SP, #124]
+  0x08003DFE:  6019         STR        R1, [R3]
+  0x08003E00:  49D9         LDR        R1, =onTimeCounterGN     ; [PC, #0x0364] [0x08004168] =0x200006A4 
+  0x08003E02:  2200         MOVS       R2, #0
+  0x08003E04:  600A         STR        R2, [R1]
+  0x08003E06:  49D9         LDR        R1, =blinkModeGN         ; [PC, #0x0364] [0x0800416C] =0x20000758 
+  0x08003E08:  700A         STRB       R2, [R1]
+  0x08003E0A:  49E0         LDR        R1, =offTimeCounterGN    ; [PC, #0x0380] [0x0800418C] =0x200006B4 
+  0x08003E0C:  600A         STR        R2, [R1]
+  0x08003E0E:  49E0         LDR        R1, =onTimeRT            ; [PC, #0x0380] [0x08004190] =0x2000073C 
+  0x08003E10:  700D         STRB       R5, [R1]
+  0x08003E12:  49E0         LDR        R1, =offTimeRT           ; [PC, #0x0380] [0x08004194] =0x20000748 
+  0x08003E14:  700D         STRB       R5, [R1]
+  0x08003E16:  49E0         LDR        R1, =blinkModeRT         ; [PC, #0x0380] [0x08004198] =0x20000754 
+  0x08003E18:  700D         STRB       R5, [R1]
+  0x08003E1A:  49E0         LDR        R1, =numberOfBlinks      ; [PC, #0x0380] [0x0800419C] =0x200006BC 
+  0x08003E1C:  600D         STR        R5, [R1]
+  0x08003E1E:  49E0         LDR        R1, =blinkCounter        ; [PC, #0x0380] [0x080041A0] =0x200006EC 
+  0x08003E20:  600D         STR        R5, [R1]
+  0x08003E22:  49E0         LDR        R1, =pauseTime           ; [PC, #0x0380] [0x080041A4] =0x20000734 
+  0x08003E24:  700D         STRB       R5, [R1]
+  0x08003E26:  991E         LDR        R1, [SP, #120]
+  0x08003E28:  6019         STR        R1, [R3]
+
.L233:
+  0x08003E2A:  49DF         LDR        R1, =onTimeCounterRT     ; [PC, #0x037C] [0x080041A8] =0x2000069C 
+  0x08003E2C:  6008         STR        R0, [R1]
+  0x08003E2E:  48DF         LDR        R0, =0x0800674A          ; [PC, #0x037C] [0x080041AC] 
+  0x08003E30:  F001 F9DE    BL         puts                     ; 0x080051F0
+  0x08003E34:  2002         MOVS       R0, #2
+  0x08003E36:  49D0         LDR        R1, =smState.145         ; [PC, #0x0340] [0x08004178] =0x20000733 
+  0x08003E38:  E16B         B          .L251                    ; 0x08004112
+
.L234:
+  0x08003E3A:  49C5         LDR        R1, =0x50000410          ; [PC, #0x0314] [0x08004150] 
+  0x08003E3C:  981A         LDR        R0, [SP, #104]
+  0x08003E3E:  6188         STR        R0, [R1, #24]
+  0x08003E40:  981B         LDR        R0, [SP, #108]
+  0x08003E42:  6088         STR        R0, [R1, #8]
+  0x08003E44:  48C3         LDR        R0, =relaisState         ; [PC, #0x030C] [0x08004154] =0x20000730 
+  0x08003E46:  7005         STRB       R5, [R0]
+  0x08003E48:  48C3         LDR        R0, =onTimeCounterSET    ; [PC, #0x030C] [0x08004158] =0x20000698 
+  0x08003E4A:  9A16         LDR        R2, [SP, #88]
+  0x08003E4C:  6002         STR        R2, [R0]
+  0x08003E4E:  9820         LDR        R0, [SP, #128]
+  0x08003E50:  6088         STR        R0, [R1, #8]
+  0x08003E52:  48C2         LDR        R0, =offTimeGN           ; [PC, #0x0308] [0x0800415C] =0x2000074C 
+  0x08003E54:  7005         STRB       R5, [R0]
+  0x08003E56:  48C2         LDR        R0, =onTimeGN            ; [PC, #0x0308] [0x08004160] =0x20000740 
+  0x08003E58:  7005         STRB       R5, [R0]
+  0x08003E5A:  48D5         LDR        R0, =0x080066E6          ; [PC, #0x0354] [0x080041B0] 
+  0x08003E5C:  49C2         LDR        R1, =onTimeCounterGN     ; [PC, #0x0308] [0x08004168] =0x200006A4 
+  0x08003E5E:  4BC3         LDR        R3, =blinkModeGN         ; [PC, #0x030C] [0x0800416C] =0x20000758 
+  0x08003E60:  22C8         MOVS       R2, #200
+  0x08003E62:  9E1F         LDR        R6, [SP, #124]
+  0x08003E64:  462F         MOV        R7, R5
+
.L235:
+  0x08003E66:  701D         STRB       R5, [R3]
+  0x08003E68:  4BC1         LDR        R3, =onTimeCounter       ; [PC, #0x0304] [0x08004170] =0x200006A8 
+  0x08003E6A:  601A         STR        R2, [R3]
+  0x08003E6C:  4AC1         LDR        R2, =0x50000818          ; [PC, #0x0304] [0x08004174] 
+  0x08003E6E:  6016         STR        R6, [R2]
+  0x08003E70:  22C8         MOVS       R2, #200
+  0x08003E72:  600A         STR        R2, [R1]
+  0x08003E74:  F001 F9BC    BL         puts                     ; 0x080051F0
+  0x08003E78:  7027         STRB       R7, [R4]
+  0x08003E7A:  48CE         LDR        R0, =buttonState         ; [PC, #0x0338] [0x080041B4] =0x2000073A 
+  0x08003E7C:  7800         LDRB       R0, [R0]
+  0x08003E7E:  4FBF         LDR        R7, =0x000003C7          ; [PC, #0x02FC] [0x0800417C] 
+
.L236:
+  0x08003E80:  2802         CMP        R0, #2
+  0x08003E82:  D000         BEQ        .L237                    ; 0x08003E86
+  0x08003E84:  E146         B          .L252                    ; 0x08004114
+
.L237:
+  0x08003E86:  49B2         LDR        R1, =0x50000410          ; [PC, #0x02C8] [0x08004150] 
+  0x08003E88:  981A         LDR        R0, [SP, #104]
+  0x08003E8A:  6188         STR        R0, [R1, #24]
+  0x08003E8C:  981B         LDR        R0, [SP, #108]
+  0x08003E8E:  6088         STR        R0, [R1, #8]
+  0x08003E90:  48B0         LDR        R0, =relaisState         ; [PC, #0x02C0] [0x08004154] =0x20000730 
+  0x08003E92:  7005         STRB       R5, [R0]
+  0x08003E94:  48B0         LDR        R0, =onTimeCounterSET    ; [PC, #0x02C0] [0x08004158] =0x20000698 
+  0x08003E96:  9A16         LDR        R2, [SP, #88]
+  0x08003E98:  6002         STR        R2, [R0]
+  0x08003E9A:  48B9         LDR        R0, =onTime              ; [PC, #0x02E4] [0x08004180] =0x20000744 
+  0x08003E9C:  7005         STRB       R5, [R0]
+  0x08003E9E:  48B9         LDR        R0, =offTime             ; [PC, #0x02E4] [0x08004184] =0x20000750 
+  0x08003EA0:  7005         STRB       R5, [R0]
+  0x08003EA2:  48B9         LDR        R0, =alarmMode           ; [PC, #0x02E4] [0x08004188] =0x2000075C 
+  0x08003EA4:  7005         STRB       R5, [R0]
+  0x08003EA6:  9820         LDR        R0, [SP, #128]
+  0x08003EA8:  6088         STR        R0, [R1, #8]
+  0x08003EAA:  49B1         LDR        R1, =onTimeCounter       ; [PC, #0x02C4] [0x08004170] =0x200006A8 
+  0x08003EAC:  20C8         MOVS       R0, #200
+  0x08003EAE:  6008         STR        R0, [R1]
+  0x08003EB0:  4BB0         LDR        R3, =0x50000818          ; [PC, #0x02C0] [0x08004174] 
+  0x08003EB2:  991F         LDR        R1, [SP, #124]
+  0x08003EB4:  6019         STR        R1, [R3]
+  0x08003EB6:  49AC         LDR        R1, =onTimeCounterGN     ; [PC, #0x02B0] [0x08004168] =0x200006A4 
+  0x08003EB8:  2200         MOVS       R2, #0
+  0x08003EBA:  600A         STR        R2, [R1]
+  0x08003EBC:  49AB         LDR        R1, =blinkModeGN         ; [PC, #0x02AC] [0x0800416C] =0x20000758 
+  0x08003EBE:  700A         STRB       R2, [R1]
+  0x08003EC0:  49B2         LDR        R1, =offTimeCounterGN    ; [PC, #0x02C8] [0x0800418C] =0x200006B4 
+  0x08003EC2:  600A         STR        R2, [R1]
+  0x08003EC4:  49B2         LDR        R1, =onTimeRT            ; [PC, #0x02C8] [0x08004190] =0x2000073C 
+  0x08003EC6:  700D         STRB       R5, [R1]
+  0x08003EC8:  49B2         LDR        R1, =offTimeRT           ; [PC, #0x02C8] [0x08004194] =0x20000748 
+  0x08003ECA:  700D         STRB       R5, [R1]
+  0x08003ECC:  49B2         LDR        R1, =blinkModeRT         ; [PC, #0x02C8] [0x08004198] =0x20000754 
+  0x08003ECE:  700D         STRB       R5, [R1]
+  0x08003ED0:  49B2         LDR        R1, =numberOfBlinks      ; [PC, #0x02C8] [0x0800419C] =0x200006BC 
+  0x08003ED2:  600D         STR        R5, [R1]
+  0x08003ED4:  49B2         LDR        R1, =blinkCounter        ; [PC, #0x02C8] [0x080041A0] =0x200006EC 
+  0x08003ED6:  600D         STR        R5, [R1]
+  0x08003ED8:  49B2         LDR        R1, =pauseTime           ; [PC, #0x02C8] [0x080041A4] =0x20000734 
+  0x08003EDA:  700D         STRB       R5, [R1]
+  0x08003EDC:  991E         LDR        R1, [SP, #120]
+  0x08003EDE:  6019         STR        R1, [R3]
+
.L238:
+  0x08003EE0:  49B1         LDR        R1, =onTimeCounterRT     ; [PC, #0x02C4] [0x080041A8] =0x2000069C 
+  0x08003EE2:  6008         STR        R0, [R1]
+  0x08003EE4:  48B4         LDR        R0, =0x08006928          ; [PC, #0x02D0] [0x080041B8] 
+  0x08003EE6:  F001 F983    BL         puts                     ; 0x080051F0
+  0x08003EEA:  2002         MOVS       R0, #2
+  0x08003EEC:  7020         STRB       R0, [R4]
+  0x08003EEE:  E111         B          .L252                    ; 0x08004114
+
.L239:
+  0x08003EF0:  4997         LDR        R1, =0x50000410          ; [PC, #0x025C] [0x08004150] 
+  0x08003EF2:  981A         LDR        R0, [SP, #104]
+  0x08003EF4:  6188         STR        R0, [R1, #24]
+  0x08003EF6:  981B         LDR        R0, [SP, #108]
+  0x08003EF8:  6088         STR        R0, [R1, #8]
+  0x08003EFA:  4896         LDR        R0, =relaisState         ; [PC, #0x0258] [0x08004154] =0x20000730 
+  0x08003EFC:  7005         STRB       R5, [R0]
+  0x08003EFE:  4896         LDR        R0, =onTimeCounterSET    ; [PC, #0x0258] [0x08004158] =0x20000698 
+  0x08003F00:  9A16         LDR        R2, [SP, #88]
+  0x08003F02:  6002         STR        R2, [R0]
+  0x08003F04:  9820         LDR        R0, [SP, #128]
+  0x08003F06:  6088         STR        R0, [R1, #8]
+  0x08003F08:  4895         LDR        R0, =onTimeGN            ; [PC, #0x0254] [0x08004160] =0x20000740 
+  0x08003F0A:  7005         STRB       R5, [R0]
+  0x08003F0C:  4898         LDR        R0, =onTimeCounter       ; [PC, #0x0260] [0x08004170] =0x200006A8 
+  0x08003F0E:  21C8         MOVS       R1, #200
+  0x08003F10:  6001         STR        R1, [R0]
+  0x08003F12:  4892         LDR        R0, =offTimeGN           ; [PC, #0x0248] [0x0800415C] =0x2000074C 
+  0x08003F14:  7005         STRB       R5, [R0]
+  0x08003F16:  4895         LDR        R0, =blinkModeGN         ; [PC, #0x0254] [0x0800416C] =0x20000758 
+  0x08003F18:  7005         STRB       R5, [R0]
+  0x08003F1A:  4A96         LDR        R2, =0x50000818          ; [PC, #0x0258] [0x08004174] 
+  0x08003F1C:  981F         LDR        R0, [SP, #124]
+  0x08003F1E:  6010         STR        R0, [R2]
+  0x08003F20:  4891         LDR        R0, =onTimeCounterGN     ; [PC, #0x0244] [0x08004168] =0x200006A4 
+  0x08003F22:  6001         STR        R1, [R0]
+  0x08003F24:  981E         LDR        R0, [SP, #120]
+  0x08003F26:  6110         STR        R0, [R2, #16]
+  0x08003F28:  48A4         LDR        R0, =offTimeCounterRT    ; [PC, #0x0290] [0x080041BC] =0x200006B0 
+  0x08003F2A:  2100         MOVS       R1, #0
+  0x08003F2C:  6001         STR        R1, [R0]
+  0x08003F2E:  489A         LDR        R0, =blinkModeRT         ; [PC, #0x0268] [0x08004198] =0x20000754 
+  0x08003F30:  7001         STRB       R1, [R0]
+  0x08003F32:  489D         LDR        R0, =onTimeCounterRT     ; [PC, #0x0274] [0x080041A8] =0x2000069C 
+  0x08003F34:  6001         STR        R1, [R0]
+  0x08003F36:  48A2         LDR        R0, =0x08006465          ; [PC, #0x0288] [0x080041C0] 
+  0x08003F38:  F001 F95A    BL         puts                     ; 0x080051F0
+  0x08003F3C:  48A1         LDR        R0, =smState             ; [PC, #0x0284] [0x080041C4] =0x20000737 
+  0x08003F3E:  7005         STRB       R5, [R0]
+  0x08003F40:  7830         LDRB       R0, [R6]
+
.L240:
+  0x08003F42:  2802         CMP        R0, #2
+  0x08003F44:  D000         BEQ        .L241                    ; 0x08003F48
+  0x08003F46:  E0E5         B          .L252                    ; 0x08004114
+
.L241:
+  0x08003F48:  4981         LDR        R1, =0x50000410          ; [PC, #0x0204] [0x08004150] 
+  0x08003F4A:  981A         LDR        R0, [SP, #104]
+  0x08003F4C:  6188         STR        R0, [R1, #24]
+  0x08003F4E:  981B         LDR        R0, [SP, #108]
+  0x08003F50:  6088         STR        R0, [R1, #8]
+  0x08003F52:  4880         LDR        R0, =relaisState         ; [PC, #0x0200] [0x08004154] =0x20000730 
+  0x08003F54:  7005         STRB       R5, [R0]
+  0x08003F56:  4880         LDR        R0, =onTimeCounterSET    ; [PC, #0x0200] [0x08004158] =0x20000698 
+  0x08003F58:  9A16         LDR        R2, [SP, #88]
+  0x08003F5A:  6002         STR        R2, [R0]
+  0x08003F5C:  4888         LDR        R0, =onTime              ; [PC, #0x0220] [0x08004180] =0x20000744 
+  0x08003F5E:  7005         STRB       R5, [R0]
+  0x08003F60:  4888         LDR        R0, =offTime             ; [PC, #0x0220] [0x08004184] =0x20000750 
+  0x08003F62:  7005         STRB       R5, [R0]
+  0x08003F64:  4888         LDR        R0, =alarmMode           ; [PC, #0x0220] [0x08004188] =0x2000075C 
+  0x08003F66:  7005         STRB       R5, [R0]
+  0x08003F68:  9820         LDR        R0, [SP, #128]
+  0x08003F6A:  6088         STR        R0, [R1, #8]
+  0x08003F6C:  4980         LDR        R1, =onTimeCounter       ; [PC, #0x0200] [0x08004170] =0x200006A8 
+  0x08003F6E:  20C8         MOVS       R0, #200
+  0x08003F70:  6008         STR        R0, [R1]
+  0x08003F72:  4B80         LDR        R3, =0x50000818          ; [PC, #0x0200] [0x08004174] 
+  0x08003F74:  991F         LDR        R1, [SP, #124]
+  0x08003F76:  6019         STR        R1, [R3]
+  0x08003F78:  497B         LDR        R1, =onTimeCounterGN     ; [PC, #0x01EC] [0x08004168] =0x200006A4 
+  0x08003F7A:  2200         MOVS       R2, #0
+  0x08003F7C:  600A         STR        R2, [R1]
+  0x08003F7E:  497B         LDR        R1, =blinkModeGN         ; [PC, #0x01EC] [0x0800416C] =0x20000758 
+  0x08003F80:  700A         STRB       R2, [R1]
+  0x08003F82:  4982         LDR        R1, =offTimeCounterGN    ; [PC, #0x0208] [0x0800418C] =0x200006B4 
+  0x08003F84:  600A         STR        R2, [R1]
+  0x08003F86:  9E1E         LDR        R6, [SP, #120]
+  0x08003F88:  611E         STR        R6, [R3, #16]
+  0x08003F8A:  4981         LDR        R1, =onTimeRT            ; [PC, #0x0204] [0x08004190] =0x2000073C 
+  0x08003F8C:  700D         STRB       R5, [R1]
+  0x08003F8E:  498B         LDR        R1, =offTimeCounterRT    ; [PC, #0x022C] [0x080041BC] =0x200006B0 
+  0x08003F90:  600A         STR        R2, [R1]
+  0x08003F92:  4980         LDR        R1, =offTimeRT           ; [PC, #0x0200] [0x08004194] =0x20000748 
+  0x08003F94:  700D         STRB       R5, [R1]
+  0x08003F96:  4980         LDR        R1, =blinkModeRT         ; [PC, #0x0200] [0x08004198] =0x20000754 
+  0x08003F98:  700D         STRB       R5, [R1]
+  0x08003F9A:  4980         LDR        R1, =numberOfBlinks      ; [PC, #0x0200] [0x0800419C] =0x200006BC 
+  0x08003F9C:  600D         STR        R5, [R1]
+  0x08003F9E:  4980         LDR        R1, =blinkCounter        ; [PC, #0x0200] [0x080041A0] =0x200006EC 
+  0x08003FA0:  600D         STR        R5, [R1]
+  0x08003FA2:  4980         LDR        R1, =pauseTime           ; [PC, #0x0200] [0x080041A4] =0x20000734 
+  0x08003FA4:  700D         STRB       R5, [R1]
+  0x08003FA6:  601E         STR        R6, [R3]
+  0x08003FA8:  E0AC         B          .L250                    ; 0x08004104
+
.L242:
+  0x08003FAA:  4969         LDR        R1, =0x50000410          ; [PC, #0x01A4] [0x08004150] 
+  0x08003FAC:  981A         LDR        R0, [SP, #104]
+  0x08003FAE:  6188         STR        R0, [R1, #24]
+  0x08003FB0:  981B         LDR        R0, [SP, #108]
+  0x08003FB2:  6088         STR        R0, [R1, #8]
+  0x08003FB4:  4867         LDR        R0, =relaisState         ; [PC, #0x019C] [0x08004154] =0x20000730 
+  0x08003FB6:  7005         STRB       R5, [R0]
+  0x08003FB8:  4867         LDR        R0, =onTimeCounterSET    ; [PC, #0x019C] [0x08004158] =0x20000698 
+  0x08003FBA:  9A16         LDR        R2, [SP, #88]
+  0x08003FBC:  6002         STR        R2, [R0]
+  0x08003FBE:  9820         LDR        R0, [SP, #128]
+  0x08003FC0:  6088         STR        R0, [R1, #8]
+  0x08003FC2:  4866         LDR        R0, =offTimeGN           ; [PC, #0x0198] [0x0800415C] =0x2000074C 
+  0x08003FC4:  7005         STRB       R5, [R0]
+  0x08003FC6:  4866         LDR        R0, =onTimeGN            ; [PC, #0x0198] [0x08004160] =0x20000740 
+  0x08003FC8:  7005         STRB       R5, [R0]
+  0x08003FCA:  487F         LDR        R0, =0x08006477          ; [PC, #0x01FC] [0x080041C8] 
+  0x08003FCC:  4966         LDR        R1, =onTimeCounterGN     ; [PC, #0x0198] [0x08004168] =0x200006A4 
+  0x08003FCE:  4B67         LDR        R3, =blinkModeGN         ; [PC, #0x019C] [0x0800416C] =0x20000758 
+  0x08003FD0:  22C8         MOVS       R2, #200
+  0x08003FD2:  9E1F         LDR        R6, [SP, #124]
+  0x08003FD4:  462F         MOV        R7, R5
+
.L243:
+  0x08003FD6:  701D         STRB       R5, [R3]
+  0x08003FD8:  4B65         LDR        R3, =onTimeCounter       ; [PC, #0x0194] [0x08004170] =0x200006A8 
+  0x08003FDA:  601A         STR        R2, [R3]
+  0x08003FDC:  4A65         LDR        R2, =0x50000818          ; [PC, #0x0194] [0x08004174] 
+  0x08003FDE:  6016         STR        R6, [R2]
+  0x08003FE0:  22C8         MOVS       R2, #200
+  0x08003FE2:  600A         STR        R2, [R1]
+  0x08003FE4:  F001 F904    BL         puts                     ; 0x080051F0
+  0x08003FE8:  4878         LDR        R0, =smState.122         ; [PC, #0x01E0] [0x080041CC] =0x20000736 
+  0x08003FEA:  7007         STRB       R7, [R0]
+  0x08003FEC:  7820         LDRB       R0, [R4]
+  0x08003FEE:  4F63         LDR        R7, =0x000003C7          ; [PC, #0x018C] [0x0800417C] 
+
.L244:
+  0x08003FF0:  2802         CMP        R0, #2
+  0x08003FF2:  D000         BEQ        .L245                    ; 0x08003FF6
+  0x08003FF4:  E08E         B          .L252                    ; 0x08004114
+
.L245:
+  0x08003FF6:  4956         LDR        R1, =0x50000410          ; [PC, #0x0158] [0x08004150] 
+  0x08003FF8:  981A         LDR        R0, [SP, #104]
+  0x08003FFA:  6188         STR        R0, [R1, #24]
+  0x08003FFC:  981B         LDR        R0, [SP, #108]
+  0x08003FFE:  6088         STR        R0, [R1, #8]
+  0x08004000:  4854         LDR        R0, =relaisState         ; [PC, #0x0150] [0x08004154] =0x20000730 
+  0x08004002:  7005         STRB       R5, [R0]
+  0x08004004:  4854         LDR        R0, =onTimeCounterSET    ; [PC, #0x0150] [0x08004158] =0x20000698 
+  0x08004006:  9A16         LDR        R2, [SP, #88]
+  0x08004008:  6002         STR        R2, [R0]
+  0x0800400A:  485D         LDR        R0, =onTime              ; [PC, #0x0174] [0x08004180] =0x20000744 
+  0x0800400C:  7005         STRB       R5, [R0]
+  0x0800400E:  485D         LDR        R0, =offTime             ; [PC, #0x0174] [0x08004184] =0x20000750 
+  0x08004010:  7005         STRB       R5, [R0]
+  0x08004012:  485D         LDR        R0, =alarmMode           ; [PC, #0x0174] [0x08004188] =0x2000075C 
+  0x08004014:  7005         STRB       R5, [R0]
+  0x08004016:  9820         LDR        R0, [SP, #128]
+  0x08004018:  6088         STR        R0, [R1, #8]
+  0x0800401A:  4955         LDR        R1, =onTimeCounter       ; [PC, #0x0154] [0x08004170] =0x200006A8 
+  0x0800401C:  20C8         MOVS       R0, #200
+  0x0800401E:  6008         STR        R0, [R1]
+  0x08004020:  4B54         LDR        R3, =0x50000818          ; [PC, #0x0150] [0x08004174] 
+  0x08004022:  991F         LDR        R1, [SP, #124]
+  0x08004024:  6019         STR        R1, [R3]
+  0x08004026:  4950         LDR        R1, =onTimeCounterGN     ; [PC, #0x0140] [0x08004168] =0x200006A4 
+  0x08004028:  2200         MOVS       R2, #0
+  0x0800402A:  600A         STR        R2, [R1]
+  0x0800402C:  494F         LDR        R1, =blinkModeGN         ; [PC, #0x013C] [0x0800416C] =0x20000758 
+  0x0800402E:  700A         STRB       R2, [R1]
+  0x08004030:  4956         LDR        R1, =offTimeCounterGN    ; [PC, #0x0158] [0x0800418C] =0x200006B4 
+  0x08004032:  600A         STR        R2, [R1]
+  0x08004034:  4956         LDR        R1, =onTimeRT            ; [PC, #0x0158] [0x08004190] =0x2000073C 
+  0x08004036:  700D         STRB       R5, [R1]
+  0x08004038:  4956         LDR        R1, =offTimeRT           ; [PC, #0x0158] [0x08004194] =0x20000748 
+  0x0800403A:  700D         STRB       R5, [R1]
+  0x0800403C:  4956         LDR        R1, =blinkModeRT         ; [PC, #0x0158] [0x08004198] =0x20000754 
+  0x0800403E:  700D         STRB       R5, [R1]
+  0x08004040:  4956         LDR        R1, =numberOfBlinks      ; [PC, #0x0158] [0x0800419C] =0x200006BC 
+  0x08004042:  600D         STR        R5, [R1]
+  0x08004044:  4956         LDR        R1, =blinkCounter        ; [PC, #0x0158] [0x080041A0] =0x200006EC 
+  0x08004046:  600D         STR        R5, [R1]
+  0x08004048:  4956         LDR        R1, =pauseTime           ; [PC, #0x0158] [0x080041A4] =0x20000734 
+  0x0800404A:  700D         STRB       R5, [R1]
+  0x0800404C:  991E         LDR        R1, [SP, #120]
+  0x0800404E:  6019         STR        R1, [R3]
+
.L246:
+  0x08004050:  4955         LDR        R1, =onTimeCounterRT     ; [PC, #0x0154] [0x080041A8] =0x2000069C 
+  0x08004052:  6008         STR        R0, [R1]
+  0x08004054:  485E         LDR        R0, =0x080066C9          ; [PC, #0x0178] [0x080041D0] 
+  0x08004056:  F001 F8CB    BL         puts                     ; 0x080051F0
+  0x0800405A:  2002         MOVS       R0, #2
+  0x0800405C:  495B         LDR        R1, =smState.122         ; [PC, #0x016C] [0x080041CC] =0x20000736 
+  0x0800405E:  E058         B          .L251                    ; 0x08004112
+
.L247:
+  0x08004060:  493B         LDR        R1, =0x50000410          ; [PC, #236] [0x08004150] 
+  0x08004062:  981A         LDR        R0, [SP, #104]
+  0x08004064:  6188         STR        R0, [R1, #24]
+  0x08004066:  981B         LDR        R0, [SP, #108]
+  0x08004068:  6088         STR        R0, [R1, #8]
+  0x0800406A:  483A         LDR        R0, =relaisState         ; [PC, #232] [0x08004154] =0x20000730 
+  0x0800406C:  7005         STRB       R5, [R0]
+  0x0800406E:  483A         LDR        R0, =onTimeCounterSET    ; [PC, #232] [0x08004158] =0x20000698 
+  0x08004070:  9A16         LDR        R2, [SP, #88]
+  0x08004072:  6002         STR        R2, [R0]
+  0x08004074:  9820         LDR        R0, [SP, #128]
+  0x08004076:  6088         STR        R0, [R1, #8]
+  0x08004078:  4838         LDR        R0, =offTimeGN           ; [PC, #224] [0x0800415C] =0x2000074C 
+  0x0800407A:  7005         STRB       R5, [R0]
+  0x0800407C:  4838         LDR        R0, =onTimeGN            ; [PC, #224] [0x08004160] =0x20000740 
+  0x0800407E:  7005         STRB       R5, [R0]
+  0x08004080:  4854         LDR        R0, =0x08006447          ; [PC, #0x0150] [0x080041D4] 
+  0x08004082:  4939         LDR        R1, =onTimeCounterGN     ; [PC, #228] [0x08004168] =0x200006A4 
+  0x08004084:  4B39         LDR        R3, =blinkModeGN         ; [PC, #228] [0x0800416C] =0x20000758 
+  0x08004086:  22C8         MOVS       R2, #200
+  0x08004088:  9E1F         LDR        R6, [SP, #124]
+  0x0800408A:  462F         MOV        R7, R5
+
.L248:
+  0x0800408C:  701D         STRB       R5, [R3]
+  0x0800408E:  4B38         LDR        R3, =onTimeCounter       ; [PC, #224] [0x08004170] =0x200006A8 
+  0x08004090:  601A         STR        R2, [R3]
+  0x08004092:  4A38         LDR        R2, =0x50000818          ; [PC, #224] [0x08004174] 
+  0x08004094:  6016         STR        R6, [R2]
+  0x08004096:  22C8         MOVS       R2, #200
+  0x08004098:  600A         STR        R2, [R1]
+  0x0800409A:  F001 F8A9    BL         puts                     ; 0x080051F0
+  0x0800409E:  4849         LDR        R0, =smState             ; [PC, #0x0124] [0x080041C4] =0x20000737 
+  0x080040A0:  7007         STRB       R7, [R0]
+  0x080040A2:  7820         LDRB       R0, [R4]
+  0x080040A4:  4F35         LDR        R7, =0x000003C7          ; [PC, #212] [0x0800417C] 
+
.L249:
+  0x080040A6:  2802         CMP        R0, #2
+  0x080040A8:  D134         BNE        .L252                    ; 0x08004114
+  0x080040AA:  4929         LDR        R1, =0x50000410          ; [PC, #164] [0x08004150] 
+  0x080040AC:  981A         LDR        R0, [SP, #104]
+  0x080040AE:  6188         STR        R0, [R1, #24]
+  0x080040B0:  981B         LDR        R0, [SP, #108]
+  0x080040B2:  6088         STR        R0, [R1, #8]
+  0x080040B4:  4827         LDR        R0, =relaisState         ; [PC, #156] [0x08004154] =0x20000730 
+  0x080040B6:  7005         STRB       R5, [R0]
+  0x080040B8:  4827         LDR        R0, =onTimeCounterSET    ; [PC, #156] [0x08004158] =0x20000698 
+  0x080040BA:  9A16         LDR        R2, [SP, #88]
+  0x080040BC:  6002         STR        R2, [R0]
+  0x080040BE:  4830         LDR        R0, =onTime              ; [PC, #192] [0x08004180] =0x20000744 
+  0x080040C0:  7005         STRB       R5, [R0]
+  0x080040C2:  4830         LDR        R0, =offTime             ; [PC, #192] [0x08004184] =0x20000750 
+  0x080040C4:  7005         STRB       R5, [R0]
+  0x080040C6:  4830         LDR        R0, =alarmMode           ; [PC, #192] [0x08004188] =0x2000075C 
+  0x080040C8:  7005         STRB       R5, [R0]
+  0x080040CA:  9820         LDR        R0, [SP, #128]
+  0x080040CC:  6088         STR        R0, [R1, #8]
+  0x080040CE:  4928         LDR        R1, =onTimeCounter       ; [PC, #160] [0x08004170] =0x200006A8 
+  0x080040D0:  20C8         MOVS       R0, #200
+  0x080040D2:  6008         STR        R0, [R1]
+  0x080040D4:  4B27         LDR        R3, =0x50000818          ; [PC, #156] [0x08004174] 
+  0x080040D6:  991F         LDR        R1, [SP, #124]
+  0x080040D8:  6019         STR        R1, [R3]
+  0x080040DA:  4923         LDR        R1, =onTimeCounterGN     ; [PC, #140] [0x08004168] =0x200006A4 
+  0x080040DC:  2200         MOVS       R2, #0
+  0x080040DE:  600A         STR        R2, [R1]
+  0x080040E0:  4922         LDR        R1, =blinkModeGN         ; [PC, #136] [0x0800416C] =0x20000758 
+  0x080040E2:  700A         STRB       R2, [R1]
+  0x080040E4:  4929         LDR        R1, =offTimeCounterGN    ; [PC, #164] [0x0800418C] =0x200006B4 
+  0x080040E6:  600A         STR        R2, [R1]
+  0x080040E8:  4929         LDR        R1, =onTimeRT            ; [PC, #164] [0x08004190] =0x2000073C 
+  0x080040EA:  700D         STRB       R5, [R1]
+  0x080040EC:  4929         LDR        R1, =offTimeRT           ; [PC, #164] [0x08004194] =0x20000748 
+  0x080040EE:  700D         STRB       R5, [R1]
+  0x080040F0:  4929         LDR        R1, =blinkModeRT         ; [PC, #164] [0x08004198] =0x20000754 
+  0x080040F2:  700D         STRB       R5, [R1]
+  0x080040F4:  4929         LDR        R1, =numberOfBlinks      ; [PC, #164] [0x0800419C] =0x200006BC 
+  0x080040F6:  600D         STR        R5, [R1]
+  0x080040F8:  4929         LDR        R1, =blinkCounter        ; [PC, #164] [0x080041A0] =0x200006EC 
+  0x080040FA:  600D         STR        R5, [R1]
+  0x080040FC:  4929         LDR        R1, =pauseTime           ; [PC, #164] [0x080041A4] =0x20000734 
+  0x080040FE:  700D         STRB       R5, [R1]
+  0x08004100:  991E         LDR        R1, [SP, #120]
+  0x08004102:  6019         STR        R1, [R3]
+
.L250:
+  0x08004104:  4928         LDR        R1, =onTimeCounterRT     ; [PC, #160] [0x080041A8] =0x2000069C 
+  0x08004106:  6008         STR        R0, [R1]
+  0x08004108:  4833         LDR        R0, =0x08006662          ; [PC, #204] [0x080041D8] 
+  0x0800410A:  F001 F871    BL         puts                     ; 0x080051F0
+  0x0800410E:  2002         MOVS       R0, #2
+  0x08004110:  492C         LDR        R1, =smState             ; [PC, #176] [0x080041C4] =0x20000737 
+
.L251:
+  0x08004112:  7008         STRB       R0, [R1]
+
.L252:
+  0x08004114:  4C31         LDR        R4, =modbusData          ; [PC, #196] [0x080041DC] =0x20000000 
+  0x08004116:  9822         LDR        R0, [SP, #136]
+  0x08004118:  5C20         LDRB       R0, [R4, R0]
+  0x0800411A:  4931         LDR        R1, =sys_data            ; [PC, #196] [0x080041E0] =0x20000234 
+  0x0800411C:  8B49         LDRH       R1, [R1, #26]
+  0x0800411E:  2900         CMP        R1, #0
+  0x08004120:  D101         BNE        .L253                    ; 0x08004126
+  0x08004122:  F7FE FAB6    BL         .L107                    ; 0x08002692
+
.L253:
+  0x08004126:  2800         CMP        R0, #0
+  0x08004128:  D001         BEQ        .L254                    ; 0x0800412E
+  0x0800412A:  F7FE FAB2    BL         .L107                    ; 0x08002692
+
.L254:
+  0x0800412E:  482C         LDR        R0, =sys_data            ; [PC, #176] [0x080041E0] =0x20000234 
+  0x08004130:  8B40         LDRH       R0, [R0, #26]
+  0x08004132:  1E41         SUBS       R1, R0, #1
+  0x08004134:  2905         CMP        R1, #5
+  0x08004136:  D858         BHI        .L255                    ; 0x080041EA
+  0x08004138:  0049         LSLS       R1, R1, #1
+  0x0800413A:  46C0         NOP
+  0x0800413C:  4479         ADD        R1, PC
+  0x0800413E:  8889         LDRH       R1, [R1, #4]
+  0x08004140:  0049         LSLS       R1, R1, #1
+  0x08004142:  448F         ADD        PC, R1
+  0x08004144:  5D           DC.B       0x5D                     ; ']'
+  0x08004145:  00           DC.B       0x00                     ; '\0'
+  0x08004146:  4F           DC.B       0x4F                     ; 'O'
+  0x08004147:  00           DC.B       0x00                     ; '\0'
+  0x08004148:  4F           DC.B       0x4F                     ; 'O'
+  0x08004149:  00           DC.B       0x00                     ; '\0'
+  0x0800414A:  5F           DC.B       0x5F                     ; '_'
+  0x0800414B:  00           DC.B       0x00                     ; '\0'
+  0x0800414C:  59           DC.B       0x59                     ; 'Y'
+  0x0800414D:  00           DC.B       0x00                     ; '\0'
+  0x0800414E:  53           DC.B       0x53                     ; 'S'
+  0x0800414F:  01           DC.B       0x01                     ; '\x01'
+  0x08004150:  50000410     DC.W       0x50000410
+  0x08004154:  20000730     DC.W       relaisState
+  0x08004158:  20000698     DC.W       onTimeCounterSET
+  0x0800415C:  2000074C     DC.W       offTimeGN
+  0x08004160:  20000740     DC.W       onTimeGN
+  0x08004164:  080064F3     DC.W       080064F3               ; R_ARM_ABS32
+  0x08004168:  200006A4     DC.W       onTimeCounterGN
+  0x0800416C:  20000758     DC.W       blinkModeGN
+  0x08004170:  200006A8     DC.W       onTimeCounter
+  0x08004174:  50000818     DC.W       0x50000818
+  0x08004178:  20000733     DC.W       smState.145
+  0x0800417C:  000003C7     DC.W       0x000003C7
+  0x08004180:  20000744     DC.W       onTime
+  0x08004184:  20000750     DC.W       offTime
+  0x08004188:  2000075C     DC.W       alarmMode
+  0x0800418C:  200006B4     DC.W       offTimeCounterGN
+  0x08004190:  2000073C     DC.W       onTimeRT
+  0x08004194:  20000748     DC.W       offTimeRT
+  0x08004198:  20000754     DC.W       blinkModeRT
+  0x0800419C:  200006BC     DC.W       numberOfBlinks
+  0x080041A0:  200006EC     DC.W       blinkCounter
+  0x080041A4:  20000734     DC.W       pauseTime
+  0x080041A8:  2000069C     DC.W       onTimeCounterRT
+  0x080041AC:  0800674A     DC.W       0800674A               ; R_ARM_ABS32
+  0x080041B0:  080066E6     DC.W       080066E6               ; R_ARM_ABS32
+  0x080041B4:  2000073A     DC.W       buttonState
+  0x080041B8:  08006928     DC.W       08006928               ; R_ARM_ABS32
+  0x080041BC:  200006B0     DC.W       offTimeCounterRT
+  0x080041C0:  08006465     DC.W       08006465               ; R_ARM_ABS32
+  0x080041C4:  20000737     DC.W       smState
+  0x080041C8:  08006477     DC.W       08006477               ; R_ARM_ABS32
+  0x080041CC:  20000736     DC.W       smState.122
+  0x080041D0:  080066C9     DC.W       080066C9               ; R_ARM_ABS32
+  0x080041D4:  08006447     DC.W       08006447               ; R_ARM_ABS32
+  0x080041D8:  08006662     DC.W       08006662               ; R_ARM_ABS32
+  0x080041DC:  20000000     DC.W       modbusData
+  0x080041E0:  20000234     DC.W       sys_data
+  0x080041E4:  F7FD FAE6    BL         EEPROM_WriteDefaults     ; 0x080017B4
+  0x080041E8:  E012         B          .L259                    ; 0x08004210
+
.L255:
+  0x080041EA:  49D6         LDR        R1, =0x000004D2          ; [PC, #0x0358] [0x08004544] 
+  0x080041EC:  4288         CMP        R0, R1
+  0x080041EE:  D00C         BEQ        .L257                    ; 0x0800420A
+  0x080041F0:  49D5         LDR        R1, =0x00001552          ; [PC, #0x0354] [0x08004548] 
+  0x080041F2:  4288         CMP        R0, R1
+  0x080041F4:  D100         BNE        .L256                    ; 0x080041F8
+  0x080041F6:  E174         B          .L288                    ; 0x080044E2
+
.L256:
+  0x080041F8:  48D4         LDR        R0, =0x080068A4          ; [PC, #0x0350] [0x0800454C] 
+  0x080041FA:  F000 FFF9    BL         puts                     ; 0x080051F0
+  0x080041FE:  E007         B          .L259                    ; 0x08004210
+  0x08004200:  2000         MOVS       R0, #0
+  0x08004202:  E003         B          .L258                    ; 0x0800420C
+  0x08004204:  F7FD FAEE    BL         EEPROM_ReadDeviceParameter ; 0x080017E4
+  0x08004208:  E002         B          .L259                    ; 0x08004210
+
.L257:
+  0x0800420A:  4628         MOV        R0, R5
+
.L258:
+  0x0800420C:  F7FD FAFC    BL         EEPROM_StoreConfig       ; 0x08001808
+
.L259:
+  0x08004210:  2000         MOVS       R0, #0
+  0x08004212:  49C6         LDR        R1, =sys_data            ; [PC, #0x0318] [0x0800452C] =0x20000234 
+  0x08004214:  8348         STRH       R0, [R1, #26]
+  0x08004216:  F7FE FA3C    BL         .L107                    ; 0x08002692
+
.L260:
+  0x0800421A:  9B08         LDR        R3, [SP, #32]
+  0x0800421C:  5CE3         LDRB       R3, [R4, R3]
+  0x0800421E:  9C05         LDR        R4, [SP, #20]
+  0x08004220:  00A4         LSLS       R4, R4, #2
+  0x08004222:  48C3         LDR        R0, =modbusData          ; [PC, #0x030C] [0x08004530] =0x20000000 
+  0x08004224:  5503         STRB       R3, [R0, R4]
+  0x08004226:  242B         MOVS       R4, #43
+  0x08004228:  5D04         LDRB       R4, [R0, R4]
+  0x0800422A:  9E13         LDR        R6, [SP, #76]
+  0x0800422C:  362C         ADDS       R6, #44
+  0x0800422E:  5584         STRB       R4, [R0, R6]
+  0x08004230:  2695         MOVS       R6, #149
+  0x08004232:  0076         LSLS       R6, R6, #1
+  0x08004234:  5582         STRB       R2, [R0, R6]
+  0x08004236:  2225         MOVS       R2, #37
+  0x08004238:  00D2         LSLS       R2, R2, #3
+  0x0800423A:  2606         MOVS       R6, #6
+  0x0800423C:  5286         STRH       R6, [R0, R2]
+  0x0800423E:  0049         LSLS       R1, R1, #1
+  0x08004240:  48BA         LDR        R0, =sys_data            ; [PC, #0x02E8] [0x0800452C] =0x20000234 
+  0x08004242:  1842         ADDS       R2, R0, R1
+  0x08004244:  7054         STRB       R4, [R2, #1]
+  0x08004246:  4CBA         LDR        R4, =modbusData          ; [PC, #0x02E8] [0x08004530] =0x20000000 
+  0x08004248:  5443         STRB       R3, [R0, R1]
+  0x0800424A:  E078         B          .L270                    ; 0x0800433E
+
.L261:
+  0x0800424C:  901C         STR        R0, [SP, #112]
+  0x0800424E:  222A         MOVS       R2, #42
+  0x08004250:  5CA0         LDRB       R0, [R4, R2]
+  0x08004252:  2229         MOVS       R2, #41
+  0x08004254:  5CA1         LDRB       R1, [R4, R2]
+  0x08004256:  020C         LSLS       R4, R1, #8
+  0x08004258:  1824         ADDS       R4, R4, R0
+  0x0800425A:  1936         ADDS       R6, R6, R4
+  0x0800425C:  4637         MOV        R7, R6
+  0x0800425E:  3F71         SUBS       R7, #113
+  0x08004260:  236F         MOVS       R3, #111
+  0x08004262:  43DB         MVNS       R3, R3
+  0x08004264:  429F         CMP        R7, R3
+  0x08004266:  D21A         BCS        .L263                    ; 0x0800429E
+  0x08004268:  2125         MOVS       R1, #37
+  0x0800426A:  00C9         LSLS       R1, R1, #3
+  0x0800426C:  0112         LSLS       R2, R2, #4
+  0x0800426E:  4CB0         LDR        R4, =modbusData          ; [PC, #0x02C0] [0x08004530] =0x20000000 
+  0x08004270:  5262         STRH       R2, [R4, R1]
+  0x08004272:  2603         MOVS       R6, #3
+  0x08004274:  E062         B          .L269                    ; 0x0800433C
+
.L262:
+  0x08004276:  9004         STR        R0, [SP, #16]
+  0x08004278:  222A         MOVS       R2, #42
+  0x0800427A:  48AD         LDR        R0, =modbusData          ; [PC, #0x02B4] [0x08004530] =0x20000000 
+  0x0800427C:  5C86         LDRB       R6, [R0, R2]
+  0x0800427E:  2229         MOVS       R2, #41
+  0x08004280:  5C82         LDRB       R2, [R0, R2]
+  0x08004282:  9202         STR        R2, [SP, #8]
+  0x08004284:  0212         LSLS       R2, R2, #8
+  0x08004286:  9603         STR        R6, [SP, #12]
+  0x08004288:  1992         ADDS       R2, R2, R6
+  0x0800428A:  18A4         ADDS       R4, R4, R2
+  0x0800428C:  941C         STR        R4, [SP, #112]
+  0x0800428E:  3C71         SUBS       R4, #113
+  0x08004290:  266F         MOVS       R6, #111
+  0x08004292:  43F6         MVNS       R6, R6
+  0x08004294:  42B4         CMP        R4, R6
+  0x08004296:  D22E         BCS        .L266                    ; 0x080042F6
+  0x08004298:  2202         MOVS       R2, #2
+  0x0800429A:  4604         MOV        R4, R0
+  0x0800429C:  E4B0         B          .L225                    ; 0x08003C00
+
.L263:
+  0x0800429E:  9003         STR        R0, [SP, #12]
+  0x080042A0:  0042         LSLS       R2, R0, #1
+  0x080042A2:  9104         STR        R1, [SP, #16]
+  0x080042A4:  024B         LSLS       R3, R1, #9
+  0x080042A6:  189A         ADDS       R2, R3, R2
+  0x080042A8:  4BA0         LDR        R3, =sys_data            ; [PC, #0x0280] [0x0800452C] =0x20000234 
+  0x080042AA:  189F         ADDS       R7, R3, R2
+  0x080042AC:  4AA0         LDR        R2, =modbusData          ; [PC, #0x0280] [0x08004530] =0x20000000 
+  0x080042AE:  322F         ADDS       R2, #47
+  0x080042B0:  981C         LDR        R0, [SP, #112]
+
.L264:
+  0x080042B2:  42B4         CMP        R4, R6
+  0x080042B4:  D208         BCS        .L265                    ; 0x080042C8
+  0x080042B6:  1E53         SUBS       R3, R2, #1
+  0x080042B8:  781B         LDRB       R3, [R3]
+  0x080042BA:  707B         STRB       R3, [R7, #1]
+  0x080042BC:  7813         LDRB       R3, [R2]
+  0x080042BE:  703B         STRB       R3, [R7]
+  0x080042C0:  1C92         ADDS       R2, R2, #2
+  0x080042C2:  1CBF         ADDS       R7, R7, #2
+  0x080042C4:  1C64         ADDS       R4, R4, #1
+  0x080042C6:  E7F4         B          .L264                    ; 0x080042B2
+
.L265:
+  0x080042C8:  9A05         LDR        R2, [SP, #20]
+  0x080042CA:  0092         LSLS       R2, R2, #2
+  0x080042CC:  4C98         LDR        R4, =modbusData          ; [PC, #0x0260] [0x08004530] =0x20000000 
+  0x080042CE:  54A0         STRB       R0, [R4, R2]
+  0x080042D0:  9B13         LDR        R3, [SP, #76]
+  0x080042D2:  4619         MOV        R1, R3
+  0x080042D4:  312C         ADDS       R1, #44
+  0x080042D6:  2200         MOVS       R2, #0
+  0x080042D8:  5462         STRB       R2, [R4, R1]
+  0x080042DA:  2195         MOVS       R1, #149
+  0x080042DC:  0049         LSLS       R1, R1, #1
+  0x080042DE:  9803         LDR        R0, [SP, #12]
+  0x080042E0:  5460         STRB       R0, [R4, R1]
+  0x080042E2:  4619         MOV        R1, R3
+  0x080042E4:  312A         ADDS       R1, #42
+  0x080042E6:  9804         LDR        R0, [SP, #16]
+  0x080042E8:  5460         STRB       R0, [R4, R1]
+  0x080042EA:  2125         MOVS       R1, #37
+  0x080042EC:  00C9         LSLS       R1, R1, #3
+  0x080042EE:  981A         LDR        R0, [SP, #104]
+  0x080042F0:  5460         STRB       R0, [R4, R1]
+  0x080042F2:  2606         MOVS       R6, #6
+  0x080042F4:  E022         B          .L269                    ; 0x0800433C
+
.L266:
+  0x080042F6:  9B13         LDR        R3, [SP, #76]
+  0x080042F8:  332A         ADDS       R3, #42
+  0x080042FA:  9C04         LDR        R4, [SP, #16]
+  0x080042FC:  0064         LSLS       R4, R4, #1
+  0x080042FE:  54C4         STRB       R4, [R0, R3]
+  0x08004300:  2325         MOVS       R3, #37
+  0x08004302:  00DB         LSLS       R3, R3, #3
+  0x08004304:  2403         MOVS       R4, #3
+  0x08004306:  54C4         STRB       R4, [R0, R3]
+  0x08004308:  9803         LDR        R0, [SP, #12]
+  0x0800430A:  0043         LSLS       R3, R0, #1
+  0x0800430C:  9802         LDR        R0, [SP, #8]
+  0x0800430E:  0244         LSLS       R4, R0, #9
+  0x08004310:  18E3         ADDS       R3, R4, R3
+  0x08004312:  4C86         LDR        R4, =sys_data            ; [PC, #0x0218] [0x0800452C] =0x20000234 
+  0x08004314:  18E3         ADDS       R3, R4, R3
+
.L267:
+  0x08004316:  981C         LDR        R0, [SP, #112]
+  0x08004318:  4282         CMP        R2, R0
+  0x0800431A:  D20D         BCS        .L268                    ; 0x08004338
+  0x0800431C:  4884         LDR        R0, =modbusData          ; [PC, #0x0210] [0x08004530] =0x20000000 
+  0x0800431E:  1844         ADDS       R4, R0, R1
+  0x08004320:  185E         ADDS       R6, R3, R1
+  0x08004322:  7876         LDRB       R6, [R6, #1]
+  0x08004324:  2795         MOVS       R7, #149
+  0x08004326:  007F         LSLS       R7, R7, #1
+  0x08004328:  55E6         STRB       R6, [R4, R7]
+  0x0800432A:  5C5E         LDRB       R6, [R3, R1]
+  0x0800432C:  9F13         LDR        R7, [SP, #76]
+  0x0800432E:  372C         ADDS       R7, #44
+  0x08004330:  55E6         STRB       R6, [R4, R7]
+  0x08004332:  1C89         ADDS       R1, R1, #2
+  0x08004334:  1C52         ADDS       R2, R2, #1
+  0x08004336:  E7EE         B          .L267                    ; 0x08004316
+
.L268:
+  0x08004338:  1CCE         ADDS       R6, R1, #3
+  0x0800433A:  4C7D         LDR        R4, =modbusData          ; [PC, #0x01F4] [0x08004530] =0x20000000 
+
.L269:
+  0x0800433C:  9F0C         LDR        R7, [SP, #48]
+
.L270:
+  0x0800433E:  19E7         ADDS       R7, R4, R7
+  0x08004340:  4638         MOV        R0, R7
+  0x08004342:  4631         MOV        R1, R6
+  0x08004344:  F000 F986    BL         mbCrc16                  ; 0x08004654
+  0x08004348:  55B8         STRB       R0, [R7, R6]
+  0x0800434A:  990E         LDR        R1, [SP, #56]
+  0x0800434C:  9A22         LDR        R2, [SP, #136]
+  0x0800434E:  54A1         STRB       R1, [R4, R2]
+  0x08004350:  19B9         ADDS       R1, R7, R6
+  0x08004352:  0A00         LSRS       R0, R0, #8
+  0x08004354:  7048         STRB       R0, [R1, #1]
+  0x08004356:  1CB0         ADDS       R0, R6, #2
+  0x08004358:  9911         LDR        R1, [SP, #68]
+  0x0800435A:  5060         STR        R0, [R4, R1]
+  0x0800435C:  6826         LDR        R6, [R4]
+  0x0800435E:  990D         LDR        R1, [SP, #52]
+  0x08004360:  5871         LDR        R1, [R6, R1]
+  0x08004362:  2920         CMP        R1, #32
+  0x08004364:  D13B         BNE        .L273                    ; 0x080043DE
+  0x08004366:  B283         UXTH       R3, R0
+  0x08004368:  2B00         CMP        R3, #0
+  0x0800436A:  D038         BEQ        .L273                    ; 0x080043DE
+  0x0800436C:  68B1         LDR        R1, [R6, #8]
+  0x0800436E:  9A14         LDR        R2, [SP, #80]
+  0x08004370:  4291         CMP        R1, R2
+  0x08004372:  D102         BNE        .L271                    ; 0x0800437A
+  0x08004374:  6931         LDR        R1, [R6, #16]
+  0x08004376:  2900         CMP        R1, #0
+  0x08004378:  D031         BEQ        .L273                    ; 0x080043DE
+
.L271:
+  0x0800437A:  4632         MOV        R2, R6
+  0x0800437C:  3254         ADDS       R2, #84
+  0x0800437E:  4634         MOV        R4, R6
+  0x08004380:  3488         ADDS       R4, #136
+  0x08004382:  8050         STRH       R0, [R2, #2]
+  0x08004384:  2100         MOVS       R1, #0
+  0x08004386:  60A1         STR        R1, [R4, #8]
+  0x08004388:  8010         STRH       R0, [R2]
+  0x0800438A:  6537         STR        R7, [R6, #80]
+  0x0800438C:  2021         MOVS       R0, #33
+  0x0800438E:  6020         STR        R0, [R4]
+  0x08004390:  6FF0         LDR        R0, [R6, #124]
+  0x08004392:  2800         CMP        R0, #0
+  0x08004394:  D014         BEQ        .L272                    ; 0x080043C0
+  0x08004396:  931C         STR        R3, [SP, #112]
+  0x08004398:  4B68         LDR        R3, =UART_DMATxHalfCplt  ; [PC, #0x01A0] [0x0800453C] =0x0800580F 
+  0x0800439A:  4A69         LDR        R2, =UART_DMATransmitCplt ; [PC, #0x01A4] [0x08004540] =0x08001501 
+  0x0800439C:  62C2         STR        R2, [R0, #44]
+  0x0800439E:  6303         STR        R3, [R0, #48]
+  0x080043A0:  4A65         LDR        R2, =UART_DMAError       ; [PC, #0x0194] [0x08004538] =0x08005811 
+  0x080043A2:  6342         STR        R2, [R0, #52]
+  0x080043A4:  6381         STR        R1, [R0, #56]
+  0x080043A6:  6832         LDR        R2, [R6]
+  0x080043A8:  3228         ADDS       R2, #40
+  0x080043AA:  4639         MOV        R1, R7
+  0x080043AC:  9B1C         LDR        R3, [SP, #112]
+  0x080043AE:  F7FC FB39    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080043B2:  2800         CMP        R0, #0
+  0x080043B4:  D004         BEQ        .L272                    ; 0x080043C0
+  0x080043B6:  981A         LDR        R0, [SP, #104]
+  0x080043B8:  60A0         STR        R0, [R4, #8]
+  0x080043BA:  9820         LDR        R0, [SP, #128]
+  0x080043BC:  6020         STR        R0, [R4]
+  0x080043BE:  E00E         B          .L273                    ; 0x080043DE
+
.L272:
+  0x080043C0:  6830         LDR        R0, [R6]
+  0x080043C2:  9907         LDR        R1, [SP, #28]
+  0x080043C4:  6201         STR        R1, [R0, #32]
+  0x080043C6:  F3EF 8010    MRS        R0, PRIMASK
+  0x080043CA:  2101         MOVS       R1, #1
+  0x080043CC:  F381 8810    MSR        PRIMASK, R1
+  0x080043D0:  6831         LDR        R1, [R6]
+  0x080043D2:  688A         LDR        R2, [R1, #8]
+  0x080043D4:  9B0A         LDR        R3, [SP, #40]
+  0x080043D6:  431A         ORRS       R2, R3
+  0x080043D8:  608A         STR        R2, [R1, #8]
+  0x080043DA:  F380 8810    MSR        PRIMASK, R0
+
.L273:
+  0x080043DE:  2000         MOVS       R0, #0
+  0x080043E0:  4953         LDR        R1, =modbusData          ; [PC, #0x014C] [0x08004530] =0x20000000 
+  0x080043E2:  9A21         LDR        R2, [SP, #132]
+  0x080043E4:  5088         STR        R0, [R1, R2]
+  0x080043E6:  7508         STRB       R0, [R1, #20]
+  0x080043E8:  F7FE F967    BL         .L109                    ; 0x080026BA
+
.L274:
+  0x080043EC:  E7FE         B          .L274                    ; 0x080043EC
+
.L275:
+  0x080043EE:  484B         LDR        R0, =SystemCoreClock     ; [PC, #0x012C] [0x0800451C] =0x20000BA4 
+  0x080043F0:  6800         LDR        R0, [R0]
+  0x080043F2:  494C         LDR        R1, =0x00030D40          ; [PC, #0x0130] [0x08004524] 
+  0x080043F4:  F001 FE45    BL         __aeabi_uidiv            ; 0x08006082
+  0x080043F8:  9A03         LDR        R2, [SP, #12]
+  0x080043FA:  9B21         LDR        R3, [SP, #132]
+  0x080043FC:  1C40         ADDS       R0, R0, #1
+
.L276:
+  0x080043FE:  9029         STR        R0, [SP, #164]
+  0x08004400:  9829         LDR        R0, [SP, #164]
+  0x08004402:  2800         CMP        R0, #0
+  0x08004404:  D101         BNE        .L277                    ; 0x0800440A
+  0x08004406:  F7FE F8CE    BL         .L98                     ; 0x080025A6
+
.L277:
+  0x0800440A:  9829         LDR        R0, [SP, #164]
+  0x0800440C:  1E40         SUBS       R0, R0, #1
+  0x0800440E:  E7F6         B          .L276                    ; 0x080043FE
+
.L278:
+  0x08004410:  4841         LDR        R0, =uwTick              ; [PC, #0x0104] [0x08004518] =0x2000068C 
+  0x08004412:  6800         LDR        R0, [R0]
+
.L279:
+  0x08004414:  6821         LDR        R1, [R4]
+  0x08004416:  07C9         LSLS       R1, R1, #31
+  0x08004418:  D001         BEQ        .L280                    ; 0x0800441E
+  0x0800441A:  F7FE F8C9    BL         .L99                     ; 0x080025B0
+
.L280:
+  0x0800441E:  68A1         LDR        R1, [R4, #8]
+  0x08004420:  07C9         LSLS       R1, R1, #31
+  0x08004422:  D105         BNE        .L281                    ; 0x08004430
+  0x08004424:  68A1         LDR        R1, [R4, #8]
+  0x08004426:  4A3E         LDR        R2, =0x7FFFFFE8          ; [PC, #248] [0x08004520] 
+  0x08004428:  4011         ANDS       R1, R2
+  0x0800442A:  9A03         LDR        R2, [SP, #12]
+  0x0800442C:  4311         ORRS       R1, R2
+  0x0800442E:  60A1         STR        R1, [R4, #8]
+
.L281:
+  0x08004430:  4939         LDR        R1, =uwTick              ; [PC, #228] [0x08004518] =0x2000068C 
+  0x08004432:  6809         LDR        R1, [R1]
+  0x08004434:  1A09         SUBS       R1, R1, R0
+  0x08004436:  2903         CMP        R1, #3
+  0x08004438:  D3EC         BCC        .L279                    ; 0x08004414
+  0x0800443A:  F7FE F8A0    BL         .L96                     ; 0x0800257E
+
.L282:
+  0x0800443E:  4001         ANDS       R1, R0
+  0x08004440:  9802         LDR        R0, [SP, #8]
+  0x08004442:  4301         ORRS       R1, R0
+  0x08004444:  60A1         STR        R1, [R4, #8]
+  0x08004446:  1D18         ADDS       R0, R3, #4
+  0x08004448:  08C3         LSRS       R3, R0, #3
+  0x0800444A:  6920         LDR        R0, [R4, #16]
+  0x0800444C:  0F80         LSRS       R0, R0, #30
+  0x0800444E:  4F31         LDR        R7, =0x000003C7          ; [PC, #196] [0x08004514] 
+  0x08004450:  D114         BNE        .L284                    ; 0x0800447C
+  0x08004452:  9803         LDR        R0, [SP, #12]
+  0x08004454:  0480         LSLS       R0, R0, #18
+  0x08004456:  4934         LDR        R1, =0x40012708          ; [PC, #208] [0x08004528] 
+  0x08004458:  6809         LDR        R1, [R1]
+  0x0800445A:  4001         ANDS       R1, R0
+  0x0800445C:  0C89         LSRS       R1, R1, #18
+  0x0800445E:  2907         CMP        R1, #7
+  0x08004460:  D30C         BCC        .L284                    ; 0x0800447C
+  0x08004462:  1EC8         SUBS       R0, R1, #3
+  0x08004464:  9902         LDR        R1, [SP, #8]
+  0x08004466:  4081         LSLS       R1, R0
+  0x08004468:  9130         STR        R1, [SP, #192]
+  0x0800446A:  9830         LDR        R0, [SP, #192]
+  0x0800446C:  0841         LSRS       R1, R0, #1
+
.L283:
+  0x0800446E:  9130         STR        R1, [SP, #192]
+  0x08004470:  9830         LDR        R0, [SP, #192]
+  0x08004472:  2800         CMP        R0, #0
+  0x08004474:  D002         BEQ        .L284                    ; 0x0800447C
+  0x08004476:  9830         LDR        R0, [SP, #192]
+  0x08004478:  1E41         SUBS       R1, R0, #1
+  0x0800447A:  E7F8         B          .L283                    ; 0x0800446E
+
.L284:
+  0x0800447C:  6810         LDR        R0, [R2]
+  0x0800447E:  217F         MOVS       R1, #127
+  0x08004480:  4388         BICS       R0, R1
+  0x08004482:  4318         ORRS       R0, R3
+  0x08004484:  6010         STR        R0, [R2]
+  0x08004486:  68A0         LDR        R0, [R4, #8]
+  0x08004488:  4925         LDR        R1, =0x7FFFFFE8          ; [PC, #148] [0x08004520] 
+  0x0800448A:  4008         ANDS       R0, R1
+  0x0800448C:  9912         LDR        R1, [SP, #72]
+  0x0800448E:  4308         ORRS       R0, R1
+  0x08004490:  60A0         STR        R0, [R4, #8]
+  0x08004492:  4821         LDR        R0, =uwTick              ; [PC, #132] [0x08004518] =0x2000068C 
+  0x08004494:  6802         LDR        R2, [R0]
+  0x08004496:  9B21         LDR        R3, [SP, #132]
+
.L285:
+  0x08004498:  68A0         LDR        R0, [R4, #8]
+  0x0800449A:  07C0         LSLS       R0, R0, #31
+  0x0800449C:  D012         BEQ        .L286                    ; 0x080044C4
+  0x0800449E:  481E         LDR        R0, =uwTick              ; [PC, #120] [0x08004518] =0x2000068C 
+  0x080044A0:  6800         LDR        R0, [R0]
+  0x080044A2:  1A80         SUBS       R0, R0, R2
+  0x080044A4:  2803         CMP        R0, #3
+  0x080044A6:  D3F7         BCC        .L285                    ; 0x08004498
+  0x080044A8:  68A0         LDR        R0, [R4, #8]
+  0x080044AA:  07C0         LSLS       R0, R0, #31
+  0x080044AC:  D0F4         BEQ        .L285                    ; 0x08004498
+  0x080044AE:  6DB0         LDR        R0, [R6, #88]
+  0x080044B0:  991A         LDR        R1, [SP, #104]
+  0x080044B2:  4308         ORRS       R0, R1
+  0x080044B4:  65B0         STR        R0, [R6, #88]
+  0x080044B6:  6DF0         LDR        R0, [R6, #92]
+  0x080044B8:  9902         LDR        R1, [SP, #8]
+  0x080044BA:  4308         ORRS       R0, R1
+  0x080044BC:  65F0         STR        R0, [R6, #92]
+  0x080044BE:  4628         MOV        R0, R5
+  0x080044C0:  F7FE F83C    BL         .L93                     ; 0x0800253C
+
.L286:
+  0x080044C4:  68E0         LDR        R0, [R4, #12]
+  0x080044C6:  9901         LDR        R1, [SP, #4]
+  0x080044C8:  4308         ORRS       R0, R1
+  0x080044CA:  60E0         STR        R0, [R4, #12]
+  0x080044CC:  6DB1         LDR        R1, [R6, #88]
+  0x080044CE:  9802         LDR        R0, [SP, #8]
+  0x080044D0:  4301         ORRS       R1, R0
+  0x080044D2:  9812         LDR        R0, [SP, #72]
+  0x080044D4:  4381         BICS       R1, R0
+  0x080044D6:  F7FE F823    BL         .L91                     ; 0x08002520
+
.L287:
+  0x080044DA:  2000         MOVS       R0, #0
+  0x080044DC:  7008         STRB       R0, [R1]
+  0x080044DE:  F000 F837    BL         JumpToBootloader         ; 0x08004550
+
.L288:
+  0x080044E2:  480B         LDR        R0, =bootLoaderMark      ; [PC, #44] [0x08004510] =0x20000B7C 
+  0x080044E4:  7005         STRB       R5, [R0]
+  0x080044E6:  F001 FC8E    BL         HAL_NVIC_SystemReset     ; 0x08005E06
+
.L289:
+  0x080044EA:  3658         ADDS       R6, #88
+  0x080044EC:  E007         B          .L291                    ; 0x080044FE
+
.L290:
+  0x080044EE:  6DB0         LDR        R0, [R6, #88]
+  0x080044F0:  2110         MOVS       R1, #16
+  0x080044F2:  4301         ORRS       R1, R0
+  0x080044F4:  43B9         BICS       R1, R7
+  0x080044F6:  65B1         STR        R1, [R6, #88]
+  0x080044F8:  6DF0         LDR        R0, [R6, #92]
+  0x080044FA:  365C         ADDS       R6, #92
+  0x080044FC:  4629         MOV        R1, R5
+
.L291:
+  0x080044FE:  4301         ORRS       R1, R0
+  0x08004500:  6031         STR        R1, [R6]
+  0x08004502:  F7FD FE18    BL         .L61                     ; 0x08002136
+
.L292:
+  0x08004506:  480B         LDR        R0, =0x08006606          ; [PC, #44] [0x08004534] 
+  0x08004508:  F000 FE72    BL         puts                     ; 0x080051F0
+  0x0800450C:  F001 FCEB    BL         Error_Handler            ; 0x08005EE6
+  0x08004510:  20000B7C     DC.W       bootLoaderMark
+  0x08004514:  000003C7     DC.W       0x000003C7
+  0x08004518:  2000068C     DC.W       uwTick
+  0x0800451C:  20000BA4     DC.W       SystemCoreClock
+  0x08004520:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08004524:  00030D40     DC.W       0x00030D40
+  0x08004528:  40012708     DC.W       0x40012708
+  0x0800452C:  20000234     DC.W       sys_data
+  0x08004530:  20000000     DC.W       modbusData
+  0x08004534:  08006606     DC.W       08006606               ; R_ARM_ABS32
+  0x08004538:  08005811     DC.W       UART_DMAError
+  0x0800453C:  0800580F     DC.W       UART_DMATxHalfCplt
+  0x08004540:  08001501     DC.W       UART_DMATransmitCplt
+  0x08004544:  000004D2     DC.W       0x000004D2
+  0x08004548:  00001552     DC.W       0x00001552
+  0x0800454C:  080068A4     DC.W       080068A4               ; R_ARM_ABS32
+
+

Section .text.JumpToBootloader from PowerPro_lto.o, size=92, align=4

+
+
JumpToBootloader:
+  0x08004550:  B082         SUB        SP, SP, #8
+  0x08004552:  B672         CPSID      i
+  0x08004554:  2000         MOVS       R0, #0
+  0x08004556:  43C0         MVNS       R0, R0
+  0x08004558:  490E         LDR        R1, =0xE000E180          ; [PC, #56] [0x08004594] 
+  0x0800455A:  6008         STR        R0, [R1]
+  0x0800455C:  490E         LDR        R1, =0xE000E280          ; [PC, #56] [0x08004598] 
+  0x0800455E:  6008         STR        R0, [R1]
+  0x08004560:  480E         LDR        R0, =0x1FFF0000          ; [PC, #56] [0x0800459C] 
+  0x08004562:  6801         LDR        R1, [R0]
+  0x08004564:  6840         LDR        R0, [R0, #4]
+  0x08004566:  F381 8808    MSR        MSP, R1
+  0x0800456A:  490D         LDR        R1, =0x40021040          ; [PC, #52] [0x080045A0] 
+  0x0800456C:  680A         LDR        R2, [R1]
+  0x0800456E:  2301         MOVS       R3, #1
+  0x08004570:  431A         ORRS       R2, R3
+  0x08004572:  600A         STR        R2, [R1]
+  0x08004574:  6809         LDR        R1, [R1]
+  0x08004576:  4019         ANDS       R1, R3
+  0x08004578:  9101         STR        R1, [SP, #4]
+  0x0800457A:  9901         LDR        R1, [SP, #4]
+  0x0800457C:  4909         LDR        R1, =0x40010000          ; [PC, #36] [0x080045A4] 
+  0x0800457E:  680A         LDR        R2, [R1]
+  0x08004580:  431A         ORRS       R2, R3
+  0x08004582:  2302         MOVS       R3, #2
+  0x08004584:  439A         BICS       R2, R3
+  0x08004586:  600A         STR        R2, [R1]
+  0x08004588:  B662         CPSIE      i
+  0x0800458A:  4780         BLX        R0
+
.L1:
+  0x0800458C:  4806         LDR        R0, =0x080065D3          ; [PC, #24] [0x080045A8] 
+  0x0800458E:  F000 FE2F    BL         puts                     ; 0x080051F0
+  0x08004592:  E7FB         B          .L1                      ; 0x0800458C
+  0x08004594:  E000E180     DC.W       0xE000E180
+  0x08004598:  E000E280     DC.W       0xE000E280
+  0x0800459C:  1FFF0000     DC.W       0x1FFF0000
+  0x080045A0:  40021040     DC.W       0x40021040
+  0x080045A4:  40010000     DC.W       0x40010000
+  0x080045A8:  080065D3     DC.W       080065D3               ; R_ARM_ABS32
+
+

Section .text.HAL_UART_ErrorCallback from PowerPro_lto.o, size=168, align=4

+
+
HAL_UART_ErrorCallback:
+  0x080045AC:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080045AE:  4604         MOV        R4, R0
+  0x080045B0:  4820         LDR        R0, =modbusData          ; [PC, #128] [0x08004634] =0x20000000 
+  0x080045B2:  2101         MOVS       R1, #1
+  0x080045B4:  7501         STRB       R1, [R0, #20]
+  0x080045B6:  4920         LDR        R1, =0x00000231          ; [PC, #128] [0x08004638] 
+  0x080045B8:  2200         MOVS       R2, #0
+  0x080045BA:  5442         STRB       R2, [R0, R1]
+  0x080045BC:  215C         MOVS       R1, #92
+  0x080045BE:  5A61         LDRH       R1, [R4, R1]
+  0x080045C0:  2280         MOVS       R2, #128
+  0x080045C2:  58A2         LDR        R2, [R4, R2]
+  0x080045C4:  6812         LDR        R2, [R2]
+  0x080045C6:  6852         LDR        R2, [R2, #4]
+  0x080045C8:  1A89         SUBS       R1, R1, R2
+  0x080045CA:  2245         MOVS       R2, #69
+  0x080045CC:  00D2         LSLS       R2, R2, #3
+  0x080045CE:  5081         STR        R1, [R0, R2]
+  0x080045D0:  4625         MOV        R5, R4
+  0x080045D2:  3580         ADDS       R5, #128
+  0x080045D4:  6928         LDR        R0, [R5, #16]
+  0x080045D6:  6928         LDR        R0, [R5, #16]
+  0x080045D8:  2804         CMP        R0, #4
+  0x080045DA:  D102         BNE        .L1                      ; 0x080045E2
+  0x080045DC:  4817         LDR        R0, =0x080068B4          ; [PC, #92] [0x0800463C] 
+  0x080045DE:  F000 FE61    BL         printf                   ; 0x080052A4
+
.L1:
+  0x080045E2:  6928         LDR        R0, [R5, #16]
+  0x080045E4:  2801         CMP        R0, #1
+  0x080045E6:  D102         BNE        .L2                      ; 0x080045EE
+  0x080045E8:  4815         LDR        R0, =0x080068C4          ; [PC, #84] [0x08004640] 
+  0x080045EA:  F000 FE5B    BL         printf                   ; 0x080052A4
+
.L2:
+  0x080045EE:  6928         LDR        R0, [R5, #16]
+  0x080045F0:  2802         CMP        R0, #2
+  0x080045F2:  D102         BNE        .L3                      ; 0x080045FA
+  0x080045F4:  4813         LDR        R0, =0x080068D4          ; [PC, #76] [0x08004644] 
+  0x080045F6:  F000 FE55    BL         printf                   ; 0x080052A4
+
.L3:
+  0x080045FA:  6928         LDR        R0, [R5, #16]
+  0x080045FC:  2810         CMP        R0, #16
+  0x080045FE:  D102         BNE        .L4                      ; 0x08004606
+  0x08004600:  4811         LDR        R0, =0x080065E4          ; [PC, #68] [0x08004648] 
+  0x08004602:  F000 FE4F    BL         printf                   ; 0x080052A4
+
.L4:
+  0x08004606:  6928         LDR        R0, [R5, #16]
+  0x08004608:  2810         CMP        R0, #16
+  0x0800460A:  D102         BNE        .L5                      ; 0x08004612
+  0x0800460C:  480E         LDR        R0, =0x080065E4          ; [PC, #56] [0x08004648] 
+  0x0800460E:  F000 FE49    BL         printf                   ; 0x080052A4
+
.L5:
+  0x08004612:  6928         LDR        R0, [R5, #16]
+  0x08004614:  2808         CMP        R0, #8
+  0x08004616:  D102         BNE        .L6                      ; 0x0800461E
+  0x08004618:  480C         LDR        R0, =0x080065F5          ; [PC, #48] [0x0800464C] 
+  0x0800461A:  F000 FE43    BL         printf                   ; 0x080052A4
+
.L6:
+  0x0800461E:  6DA1         LDR        R1, [R4, #88]
+  0x08004620:  4620         MOV        R0, R4
+  0x08004622:  F7FC FF95    BL         HAL_UART_Receive_DMA     ; 0x08001550
+  0x08004626:  2800         CMP        R0, #0
+  0x08004628:  D002         BEQ        .L7                      ; 0x08004630
+  0x0800462A:  4809         LDR        R0, =0x08006238          ; [PC, #36] [0x08004650] 
+  0x0800462C:  F000 FE3A    BL         printf                   ; 0x080052A4
+
.L7:
+  0x08004630:  BDB0         POP        {R4-R5, R7, PC}
+  0x08004632:  46C0         NOP
+  0x08004634:  20000000     DC.W       modbusData
+  0x08004638:  00000231     DC.W       0x00000231
+  0x0800463C:  080068B4     DC.W       080068B4               ; R_ARM_ABS32
+  0x08004640:  080068C4     DC.W       080068C4               ; R_ARM_ABS32
+  0x08004644:  080068D4     DC.W       080068D4               ; R_ARM_ABS32
+  0x08004648:  080065E4     DC.W       080065E4               ; R_ARM_ABS32
+  0x0800464C:  080065F5     DC.W       080065F5               ; R_ARM_ABS32
+  0x08004650:  08006238     DC.W       08006238               ; R_ARM_ABS32
+
+

Section .text.mbCrc16 from PowerPro_lto.o, size=56, align=4

+
+
mbCrc16:
+  0x08004654:  B530         PUSH       {R4-R5, LR}
+  0x08004656:  2200         MOVS       R2, #0
+  0x08004658:  4B0A         LDR        R3, =0x0000FFFF          ; [PC, #40] [0x08004684] 
+
.L1:
+  0x0800465A:  428A         CMP        R2, R1
+  0x0800465C:  D00F         BEQ        .L5                      ; 0x0800467E
+  0x0800465E:  5C84         LDRB       R4, [R0, R2]
+  0x08004660:  4063         EORS       R3, R4
+  0x08004662:  2407         MOVS       R4, #7
+  0x08004664:  43E4         MVNS       R4, R4
+
.L2:
+  0x08004666:  2C00         CMP        R4, #0
+  0x08004668:  D007         BEQ        .L4                      ; 0x0800467A
+  0x0800466A:  085D         LSRS       R5, R3, #1
+  0x0800466C:  07DB         LSLS       R3, R3, #31
+  0x0800466E:  D001         BEQ        .L3                      ; 0x08004674
+  0x08004670:  4B05         LDR        R3, =0x0000A001          ; [PC, #20] [0x08004688] 
+  0x08004672:  405D         EORS       R5, R3
+
.L3:
+  0x08004674:  462B         MOV        R3, R5
+  0x08004676:  1C64         ADDS       R4, R4, #1
+  0x08004678:  E7F5         B          .L2                      ; 0x08004666
+
.L4:
+  0x0800467A:  1C52         ADDS       R2, R2, #1
+  0x0800467C:  E7ED         B          .L1                      ; 0x0800465A
+
.L5:
+  0x0800467E:  B298         UXTH       R0, R3
+  0x08004680:  BD30         POP        {R4-R5, PC}
+  0x08004682:  46C0         NOP
+  0x08004684:  0000FFFF     DC.W       0x0000FFFF
+  0x08004688:  0000A001     DC.W       0x0000A001
+
+

Section .text.MODE_SECONDARYPROTECTION_Exec from PowerPro_lto.o, size=1660, align=4

+
+
MODE_SECONDARYPROTECTION_Exec:
+  0x0800468C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800468E:  B085         SUB        SP, SP, #20
+  0x08004690:  4F07         LDR        R7, =autoRetryMode       ; [PC, #28] [0x080046B0] =0x200006F4 
+  0x08004692:  6038         STR        R0, [R7]
+  0x08004694:  4D07         LDR        R5, =0x50000418          ; [PC, #28] [0x080046B4] 
+  0x08004696:  4628         MOV        R0, R5
+  0x08004698:  3808         SUBS       R0, #8
+  0x0800469A:  6800         LDR        R0, [R0]
+  0x0800469C:  0740         LSLS       R0, R0, #29
+  0x0800469E:  0FC0         LSRS       R0, R0, #31
+  0x080046A0:  4C05         LDR        R4, =smState.160         ; [PC, #20] [0x080046B8] =0x20000732 
+  0x080046A2:  7821         LDRB       R1, [R4]
+  0x080046A4:  4479         ADD        R1, PC
+  0x080046A6:  7909         LDRB       R1, [R1, #4]
+  0x080046A8:  0049         LSLS       R1, R1, #1
+  0x080046AA:  448F         ADD        PC, R1
+  0x080046AC:  07           DC.B       0x07                     ; '\x07'
+  0x080046AD:  A2           DC.B       0xA2                     ; '\xA2'
+  0x080046AE:  2C           DC.B       0x2C                     ; ','
+  0x080046AF:  91           DC.B       0x91                     ; '\x91'
+  0x080046B0:  200006F4     DC.W       autoRetryMode
+  0x080046B4:  50000418     DC.W       0x50000418
+  0x080046B8:  20000732     DC.W       smState.160
+  0x080046BC:  49DA         LDR        R1, =0x50000010          ; [PC, #0x0368] [0x08004A28] 
+  0x080046BE:  680A         LDR        R2, [R1]
+  0x080046C0:  07D2         LSLS       R2, R2, #31
+  0x080046C2:  D000         BEQ        .L1                      ; 0x080046C6
+  0x080046C4:  6809         LDR        R1, [R1]
+
.L1:
+  0x080046C6:  4AD9         LDR        R2, =buttonState         ; [PC, #0x0364] [0x08004A2C] =0x2000073A 
+  0x080046C8:  7811         LDRB       R1, [R2]
+  0x080046CA:  2901         CMP        R1, #1
+  0x080046CC:  D000         BEQ        .L2                      ; 0x080046D0
+  0x080046CE:  E27C         B          .L23                     ; 0x08004BCA
+
.L2:
+  0x080046D0:  2800         CMP        R0, #0
+  0x080046D2:  D000         BEQ        .L3                      ; 0x080046D6
+  0x080046D4:  E258         B          .L21                     ; 0x08004B88
+
.L3:
+  0x080046D6:  2020         MOVS       R0, #32
+  0x080046D8:  6028         STR        R0, [R5]
+  0x080046DA:  2000         MOVS       R0, #0
+  0x080046DC:  7010         STRB       R0, [R2]
+  0x080046DE:  207D         MOVS       R0, #125
+  0x080046E0:  0080         LSLS       R0, R0, #2
+  0x080046E2:  4AD3         LDR        R2, =onTimeCounter       ; [PC, #0x034C] [0x08004A30] =0x200006A8 
+  0x080046E4:  6010         STR        R0, [R2]
+  0x080046E6:  48D3         LDR        R0, =onTimeRT            ; [PC, #0x034C] [0x08004A34] =0x2000073C 
+  0x080046E8:  7001         STRB       R1, [R0]
+  0x080046EA:  48D3         LDR        R0, =offTimeRT           ; [PC, #0x034C] [0x08004A38] =0x20000748 
+  0x080046EC:  7001         STRB       R1, [R0]
+  0x080046EE:  48D3         LDR        R0, =blinkModeRT         ; [PC, #0x034C] [0x08004A3C] =0x20000754 
+  0x080046F0:  7001         STRB       R1, [R0]
+  0x080046F2:  48D3         LDR        R0, =numberOfBlinks      ; [PC, #0x034C] [0x08004A40] =0x200006BC 
+  0x080046F4:  2703         MOVS       R7, #3
+  0x080046F6:  6007         STR        R7, [R0]
+  0x080046F8:  48D2         LDR        R0, =blinkCounter        ; [PC, #0x0348] [0x08004A44] =0x200006EC 
+  0x080046FA:  6007         STR        R7, [R0]
+  0x080046FC:  03CA         LSLS       R2, R1, #15
+  0x080046FE:  48D2         LDR        R0, =0x080067A9          ; [PC, #0x0348] [0x08004A48] 
+  0x08004700:  4BD2         LDR        R3, =onTimeCounterRT     ; [PC, #0x0348] [0x08004A4C] =0x2000069C 
+  0x08004702:  4ED3         LDR        R6, =pauseTime           ; [PC, #0x034C] [0x08004A50] =0x20000734 
+  0x08004704:  E257         B          .L22                     ; 0x08004BB6
+  0x08004706:  2800         CMP        R0, #0
+  0x08004708:  D134         BNE        .L4                      ; 0x08004774
+  0x0800470A:  2008         MOVS       R0, #8
+  0x0800470C:  6128         STR        R0, [R5, #16]
+  0x0800470E:  2010         MOVS       R0, #16
+  0x08004710:  6028         STR        R0, [R5]
+  0x08004712:  49D0         LDR        R1, =relaisState         ; [PC, #0x0340] [0x08004A54] =0x20000730 
+  0x08004714:  2000         MOVS       R0, #0
+  0x08004716:  7008         STRB       R0, [R1]
+  0x08004718:  49CF         LDR        R1, =onTimeCounterRESET  ; [PC, #0x033C] [0x08004A58] =0x200006A0 
+  0x0800471A:  2232         MOVS       R2, #50
+  0x0800471C:  600A         STR        R2, [R1]
+  0x0800471E:  2120         MOVS       R1, #32
+  0x08004720:  6029         STR        R1, [R5]
+  0x08004722:  217D         MOVS       R1, #125
+  0x08004724:  0089         LSLS       R1, R1, #2
+  0x08004726:  4AC2         LDR        R2, =onTimeCounter       ; [PC, #0x0308] [0x08004A30] =0x200006A8 
+  0x08004728:  6011         STR        R1, [R2]
+  0x0800472A:  2101         MOVS       R1, #1
+  0x0800472C:  038B         LSLS       R3, R1, #14
+  0x0800472E:  4ACB         LDR        R2, =0x50000818          ; [PC, #0x032C] [0x08004A5C] 
+  0x08004730:  6113         STR        R3, [R2, #16]
+  0x08004732:  4BCB         LDR        R3, =offTimeCounterGN    ; [PC, #0x032C] [0x08004A60] =0x200006B4 
+  0x08004734:  6018         STR        R0, [R3]
+  0x08004736:  4BCB         LDR        R3, =blinkModeGN         ; [PC, #0x032C] [0x08004A64] =0x20000758 
+  0x08004738:  7018         STRB       R0, [R3]
+  0x0800473A:  4BCB         LDR        R3, =onTimeCounterGN     ; [PC, #0x032C] [0x08004A68] =0x200006A4 
+  0x0800473C:  6018         STR        R0, [R3]
+  0x0800473E:  4BBD         LDR        R3, =onTimeRT            ; [PC, #0x02F4] [0x08004A34] =0x2000073C 
+  0x08004740:  7019         STRB       R1, [R3]
+  0x08004742:  4BBD         LDR        R3, =offTimeRT           ; [PC, #0x02F4] [0x08004A38] =0x20000748 
+  0x08004744:  7019         STRB       R1, [R3]
+  0x08004746:  4BBD         LDR        R3, =blinkModeRT         ; [PC, #0x02F4] [0x08004A3C] =0x20000754 
+  0x08004748:  7019         STRB       R1, [R3]
+  0x0800474A:  4BBD         LDR        R3, =numberOfBlinks      ; [PC, #0x02F4] [0x08004A40] =0x200006BC 
+  0x0800474C:  2603         MOVS       R6, #3
+  0x0800474E:  601E         STR        R6, [R3]
+  0x08004750:  4BBC         LDR        R3, =blinkCounter        ; [PC, #0x02F0] [0x08004A44] =0x200006EC 
+  0x08004752:  601E         STR        R6, [R3]
+  0x08004754:  4BBE         LDR        R3, =pauseTime           ; [PC, #0x02F8] [0x08004A50] =0x20000734 
+  0x08004756:  7019         STRB       R1, [R3]
+  0x08004758:  03C9         LSLS       R1, R1, #15
+  0x0800475A:  6011         STR        R1, [R2]
+  0x0800475C:  49B3         LDR        R1, =buttonState         ; [PC, #0x02CC] [0x08004A2C] =0x2000073A 
+  0x0800475E:  7008         STRB       R0, [R1]
+  0x08004760:  48BA         LDR        R0, =onTimeCounterRT     ; [PC, #0x02E8] [0x08004A4C] =0x2000069C 
+  0x08004762:  21C8         MOVS       R1, #200
+  0x08004764:  6001         STR        R1, [R0]
+  0x08004766:  48C1         LDR        R0, =0x0800698C          ; [PC, #0x0304] [0x08004A6C] 
+  0x08004768:  F000 FD42    BL         puts                     ; 0x080051F0
+  0x0800476C:  48B6         LDR        R0, =0x080067A9          ; [PC, #0x02D8] [0x08004A48] 
+  0x0800476E:  F000 FD3F    BL         puts                     ; 0x080051F0
+  0x08004772:  7026         STRB       R6, [R4]
+
.L4:
+  0x08004774:  48AD         LDR        R0, =buttonState         ; [PC, #0x02B4] [0x08004A2C] =0x2000073A 
+  0x08004776:  7800         LDRB       R0, [R0]
+  0x08004778:  2800         CMP        R0, #0
+  0x0800477A:  D000         BEQ        .L5                      ; 0x0800477E
+  0x0800477C:  E25B         B          .L25                     ; 0x08004C36
+
.L5:
+  0x0800477E:  2008         MOVS       R0, #8
+  0x08004780:  6128         STR        R0, [R5, #16]
+  0x08004782:  2010         MOVS       R0, #16
+  0x08004784:  6028         STR        R0, [R5]
+  0x08004786:  48B3         LDR        R0, =relaisState         ; [PC, #0x02CC] [0x08004A54] =0x20000730 
+  0x08004788:  2600         MOVS       R6, #0
+  0x0800478A:  7006         STRB       R6, [R0]
+  0x0800478C:  48B2         LDR        R0, =onTimeCounterRESET  ; [PC, #0x02C8] [0x08004A58] =0x200006A0 
+  0x0800478E:  2132         MOVS       R1, #50
+  0x08004790:  6001         STR        R1, [R0]
+  0x08004792:  2020         MOVS       R0, #32
+  0x08004794:  6128         STR        R0, [R5, #16]
+  0x08004796:  48B6         LDR        R0, =offTimeCounter      ; [PC, #0x02D8] [0x08004A70] =0x200006B8 
+  0x08004798:  6006         STR        R6, [R0]
+  0x0800479A:  48B6         LDR        R0, =alarmMode           ; [PC, #0x02D8] [0x08004A74] =0x2000075C 
+  0x0800479C:  7006         STRB       R6, [R0]
+  0x0800479E:  48A4         LDR        R0, =onTimeCounter       ; [PC, #0x0290] [0x08004A30] =0x200006A8 
+  0x080047A0:  6006         STR        R6, [R0]
+  0x080047A2:  2001         MOVS       R0, #1
+  0x080047A4:  0381         LSLS       R1, R0, #14
+  0x080047A6:  4AAD         LDR        R2, =0x50000818          ; [PC, #0x02B4] [0x08004A5C] 
+  0x080047A8:  6111         STR        R1, [R2, #16]
+  0x080047AA:  49AD         LDR        R1, =offTimeCounterGN    ; [PC, #0x02B4] [0x08004A60] =0x200006B4 
+  0x080047AC:  600E         STR        R6, [R1]
+  0x080047AE:  49AD         LDR        R1, =blinkModeGN         ; [PC, #0x02B4] [0x08004A64] =0x20000758 
+  0x080047B0:  700E         STRB       R6, [R1]
+  0x080047B2:  49AD         LDR        R1, =onTimeCounterGN     ; [PC, #0x02B4] [0x08004A68] =0x200006A4 
+  0x080047B4:  600E         STR        R6, [R1]
+  0x080047B6:  03C0         LSLS       R0, R0, #15
+  0x080047B8:  6110         STR        R0, [R2, #16]
+  0x080047BA:  48AF         LDR        R0, =offTimeCounterRT    ; [PC, #0x02BC] [0x08004A78] =0x200006B0 
+  0x080047BC:  6006         STR        R6, [R0]
+  0x080047BE:  489F         LDR        R0, =blinkModeRT         ; [PC, #0x027C] [0x08004A3C] =0x20000754 
+  0x080047C0:  7006         STRB       R6, [R0]
+  0x080047C2:  48A2         LDR        R0, =onTimeCounterRT     ; [PC, #0x0288] [0x08004A4C] =0x2000069C 
+  0x080047C4:  6006         STR        R6, [R0]
+  0x080047C6:  48AD         LDR        R0, =0x08006309          ; [PC, #0x02B4] [0x08004A7C] 
+  0x080047C8:  F000 FD12    BL         puts                     ; 0x080051F0
+  0x080047CC:  7026         STRB       R6, [R4]
+  0x080047CE:  E232         B          .L25                     ; 0x08004C36
+  0x080047D0:  4E96         LDR        R6, =buttonState         ; [PC, #0x0258] [0x08004A2C] =0x2000073A 
+  0x080047D2:  7831         LDRB       R1, [R6]
+  0x080047D4:  2901         CMP        R1, #1
+  0x080047D6:  D000         BEQ        .L6                      ; 0x080047DA
+  0x080047D8:  E181         B          .L17                     ; 0x08004ADE
+
.L6:
+  0x080047DA:  2800         CMP        R0, #0
+  0x080047DC:  D000         BEQ        .L7                      ; 0x080047E0
+  0x080047DE:  E155         B          .L16                     ; 0x08004A8C
+
.L7:
+  0x080047E0:  2020         MOVS       R0, #32
+  0x080047E2:  6028         STR        R0, [R5]
+  0x080047E4:  2000         MOVS       R0, #0
+  0x080047E6:  7030         STRB       R0, [R6]
+  0x080047E8:  207D         MOVS       R0, #125
+  0x080047EA:  0080         LSLS       R0, R0, #2
+  0x080047EC:  4990         LDR        R1, =onTimeCounter       ; [PC, #0x0240] [0x08004A30] =0x200006A8 
+  0x080047EE:  6008         STR        R0, [R1]
+  0x080047F0:  E1AF         B          .L18                     ; 0x08004B52
+  0x080047F2:  217D         MOVS       R1, #125
+  0x080047F4:  008B         LSLS       R3, R1, #2
+  0x080047F6:  2701         MOVS       R7, #1
+  0x080047F8:  03BA         LSLS       R2, R7, #14
+  0x080047FA:  03FE         LSLS       R6, R7, #15
+  0x080047FC:  9604         STR        R6, [SP, #16]
+  0x080047FE:  2800         CMP        R0, #0
+  0x08004800:  4E96         LDR        R6, =0x50000818          ; [PC, #0x0258] [0x08004A5C] 
+  0x08004802:  D12F         BNE        .L8                      ; 0x08004864
+  0x08004804:  2008         MOVS       R0, #8
+  0x08004806:  6128         STR        R0, [R5, #16]
+  0x08004808:  2010         MOVS       R0, #16
+  0x0800480A:  6028         STR        R0, [R5]
+  0x0800480C:  4991         LDR        R1, =relaisState         ; [PC, #0x0244] [0x08004A54] =0x20000730 
+  0x0800480E:  2000         MOVS       R0, #0
+  0x08004810:  7008         STRB       R0, [R1]
+  0x08004812:  4991         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0244] [0x08004A58] =0x200006A0 
+  0x08004814:  4614         MOV        R4, R2
+  0x08004816:  2232         MOVS       R2, #50
+  0x08004818:  600A         STR        R2, [R1]
+  0x0800481A:  2120         MOVS       R1, #32
+  0x0800481C:  6029         STR        R1, [R5]
+  0x0800481E:  4984         LDR        R1, =onTimeCounter       ; [PC, #0x0210] [0x08004A30] =0x200006A8 
+  0x08004820:  600B         STR        R3, [R1]
+  0x08004822:  6134         STR        R4, [R6, #16]
+  0x08004824:  4C96         LDR        R4, =smState.160         ; [PC, #0x0258] [0x08004A80] =0x20000732 
+  0x08004826:  498E         LDR        R1, =offTimeCounterGN    ; [PC, #0x0238] [0x08004A60] =0x200006B4 
+  0x08004828:  6008         STR        R0, [R1]
+  0x0800482A:  498E         LDR        R1, =blinkModeGN         ; [PC, #0x0238] [0x08004A64] =0x20000758 
+  0x0800482C:  7008         STRB       R0, [R1]
+  0x0800482E:  498E         LDR        R1, =onTimeCounterGN     ; [PC, #0x0238] [0x08004A68] =0x200006A4 
+  0x08004830:  6008         STR        R0, [R1]
+  0x08004832:  4980         LDR        R1, =onTimeRT            ; [PC, #0x0200] [0x08004A34] =0x2000073C 
+  0x08004834:  700F         STRB       R7, [R1]
+  0x08004836:  4980         LDR        R1, =offTimeRT           ; [PC, #0x0200] [0x08004A38] =0x20000748 
+  0x08004838:  700F         STRB       R7, [R1]
+  0x0800483A:  4980         LDR        R1, =blinkModeRT         ; [PC, #0x0200] [0x08004A3C] =0x20000754 
+  0x0800483C:  700F         STRB       R7, [R1]
+  0x0800483E:  4980         LDR        R1, =numberOfBlinks      ; [PC, #0x0200] [0x08004A40] =0x200006BC 
+  0x08004840:  2203         MOVS       R2, #3
+  0x08004842:  600A         STR        R2, [R1]
+  0x08004844:  497F         LDR        R1, =blinkCounter        ; [PC, #0x01FC] [0x08004A44] =0x200006EC 
+  0x08004846:  600A         STR        R2, [R1]
+  0x08004848:  4981         LDR        R1, =pauseTime           ; [PC, #0x0204] [0x08004A50] =0x20000734 
+  0x0800484A:  700F         STRB       R7, [R1]
+  0x0800484C:  9904         LDR        R1, [SP, #16]
+  0x0800484E:  6031         STR        R1, [R6]
+  0x08004850:  4976         LDR        R1, =buttonState         ; [PC, #0x01D8] [0x08004A2C] =0x2000073A 
+  0x08004852:  7008         STRB       R0, [R1]
+  0x08004854:  487D         LDR        R0, =onTimeCounterRT     ; [PC, #0x01F4] [0x08004A4C] =0x2000069C 
+  0x08004856:  21C8         MOVS       R1, #200
+  0x08004858:  6001         STR        R1, [R0]
+  0x0800485A:  4884         LDR        R0, =0x0800698C          ; [PC, #0x0210] [0x08004A6C] 
+  0x0800485C:  F000 FCC8    BL         puts                     ; 0x080051F0
+  0x08004860:  4879         LDR        R0, =0x080067A9          ; [PC, #0x01E4] [0x08004A48] 
+  0x08004862:  E0DC         B          .L15                     ; 0x08004A1E
+
.L8:
+  0x08004864:  9100         STR        R1, [SP, #0]
+  0x08004866:  9302         STR        R3, [SP, #8]
+  0x08004868:  486F         LDR        R0, =0x50000010          ; [PC, #0x01BC] [0x08004A28] 
+  0x0800486A:  6801         LDR        R1, [R0]
+  0x0800486C:  07C9         LSLS       R1, R1, #31
+  0x0800486E:  9203         STR        R2, [SP, #12]
+  0x08004870:  9B04         LDR        R3, [SP, #16]
+  0x08004872:  D003         BEQ        .L9                      ; 0x0800487C
+  0x08004874:  6800         LDR        R0, [R0]
+  0x08004876:  0780         LSLS       R0, R0, #30
+  0x08004878:  D500         BPL        .L9                      ; 0x0800487C
+  0x0800487A:  E1DE         B          .L26                     ; 0x08004C3A
+
.L9:
+  0x0800487C:  4881         LDR        R0, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x0204] [0x08004A84] =0x20000704 
+  0x0800487E:  2100         MOVS       R1, #0
+  0x08004880:  6001         STR        R1, [R0]
+
.L10:
+  0x08004882:  9101         STR        R1, [SP, #4]
+  0x08004884:  48FB         LDR        R0, =buttonState         ; [PC, #0x03EC] [0x08004C74] =0x2000073A 
+  0x08004886:  7800         LDRB       R0, [R0]
+  0x08004888:  2800         CMP        R0, #0
+  0x0800488A:  D125         BNE        .L11                     ; 0x080048D8
+  0x0800488C:  2008         MOVS       R0, #8
+  0x0800488E:  6128         STR        R0, [R5, #16]
+  0x08004890:  2010         MOVS       R0, #16
+  0x08004892:  6028         STR        R0, [R5]
+  0x08004894:  48F8         LDR        R0, =relaisState         ; [PC, #0x03E0] [0x08004C78] =0x20000730 
+  0x08004896:  2600         MOVS       R6, #0
+  0x08004898:  7006         STRB       R6, [R0]
+  0x0800489A:  486F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01BC] [0x08004A58] =0x200006A0 
+  0x0800489C:  2132         MOVS       R1, #50
+  0x0800489E:  6001         STR        R1, [R0]
+  0x080048A0:  2020         MOVS       R0, #32
+  0x080048A2:  6028         STR        R0, [R5]
+  0x080048A4:  48F7         LDR        R0, =onTimeCounter       ; [PC, #0x03DC] [0x08004C84] =0x200006A8 
+  0x080048A6:  21C8         MOVS       R1, #200
+  0x080048A8:  6001         STR        R1, [R0]
+  0x080048AA:  48F9         LDR        R0, =0x50000818          ; [PC, #0x03E4] [0x08004C90] 
+  0x080048AC:  6102         STR        R2, [R0, #16]
+  0x080048AE:  486C         LDR        R0, =offTimeCounterGN    ; [PC, #0x01B0] [0x08004A60] =0x200006B4 
+  0x080048B0:  6006         STR        R6, [R0]
+  0x080048B2:  48F6         LDR        R0, =blinkModeGN         ; [PC, #0x03D8] [0x08004C8C] =0x20000758 
+  0x080048B4:  7006         STRB       R6, [R0]
+  0x080048B6:  48F7         LDR        R0, =onTimeCounterGN     ; [PC, #0x03DC] [0x08004C94] =0x200006A4 
+  0x080048B8:  6006         STR        R6, [R0]
+  0x080048BA:  48F5         LDR        R0, =0x50000818          ; [PC, #0x03D4] [0x08004C90] 
+  0x080048BC:  6103         STR        R3, [R0, #16]
+  0x080048BE:  48F6         LDR        R0, =offTimeCounterRT    ; [PC, #0x03D8] [0x08004C98] =0x200006B0 
+  0x080048C0:  6006         STR        R6, [R0]
+  0x080048C2:  48F6         LDR        R0, =blinkModeRT         ; [PC, #0x03D8] [0x08004C9C] =0x20000754 
+  0x080048C4:  7006         STRB       R6, [R0]
+  0x080048C6:  48F6         LDR        R0, =onTimeCounterRT     ; [PC, #0x03D8] [0x08004CA0] =0x2000069C 
+  0x080048C8:  6006         STR        R6, [R0]
+  0x080048CA:  486C         LDR        R0, =0x08006309          ; [PC, #0x01B0] [0x08004A7C] 
+  0x080048CC:  F000 FC90    BL         puts                     ; 0x080051F0
+  0x080048D0:  9A03         LDR        R2, [SP, #12]
+  0x080048D2:  9B04         LDR        R3, [SP, #16]
+  0x080048D4:  7026         STRB       R6, [R4]
+  0x080048D6:  4EEE         LDR        R6, =0x50000818          ; [PC, #0x03B8] [0x08004C90] 
+
.L11:
+  0x080048D8:  9800         LDR        R0, [SP, #0]
+  0x080048DA:  00C0         LSLS       R0, R0, #3
+  0x080048DC:  496A         LDR        R1, =dropLimitCounter    ; [PC, #0x01A8] [0x08004A88] =0x200006E4 
+  0x080048DE:  6809         LDR        R1, [R1]
+  0x080048E0:  4281         CMP        R1, R0
+  0x080048E2:  D136         BNE        .L12                     ; 0x08004952
+  0x080048E4:  2008         MOVS       R0, #8
+  0x080048E6:  6128         STR        R0, [R5, #16]
+  0x080048E8:  2010         MOVS       R0, #16
+  0x080048EA:  6028         STR        R0, [R5]
+  0x080048EC:  48E2         LDR        R0, =relaisState         ; [PC, #0x0388] [0x08004C78] =0x20000730 
+  0x080048EE:  2600         MOVS       R6, #0
+  0x080048F0:  7006         STRB       R6, [R0]
+  0x080048F2:  48FB         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03EC] [0x08004CE0] =0x200006A0 
+  0x080048F4:  2132         MOVS       R1, #50
+  0x080048F6:  6001         STR        R1, [R0]
+  0x080048F8:  2020         MOVS       R0, #32
+  0x080048FA:  6028         STR        R0, [R5]
+  0x080048FC:  48E1         LDR        R0, =onTimeCounter       ; [PC, #0x0384] [0x08004C84] =0x200006A8 
+  0x080048FE:  9902         LDR        R1, [SP, #8]
+  0x08004900:  6001         STR        R1, [R0]
+  0x08004902:  48E3         LDR        R0, =0x50000818          ; [PC, #0x038C] [0x08004C90] 
+  0x08004904:  6102         STR        R2, [R0, #16]
+  0x08004906:  48EB         LDR        R0, =offTimeCounterGN    ; [PC, #0x03AC] [0x08004CB4] =0x200006B4 
+  0x08004908:  6006         STR        R6, [R0]
+  0x0800490A:  48E0         LDR        R0, =blinkModeGN         ; [PC, #0x0380] [0x08004C8C] =0x20000758 
+  0x0800490C:  7006         STRB       R6, [R0]
+  0x0800490E:  48E1         LDR        R0, =onTimeCounterGN     ; [PC, #0x0384] [0x08004C94] =0x200006A4 
+  0x08004910:  6006         STR        R6, [R0]
+  0x08004912:  48E9         LDR        R0, =onTimeRT            ; [PC, #0x03A4] [0x08004CB8] =0x2000073C 
+  0x08004914:  7007         STRB       R7, [R0]
+  0x08004916:  48E9         LDR        R0, =offTimeRT           ; [PC, #0x03A4] [0x08004CBC] =0x20000748 
+  0x08004918:  7007         STRB       R7, [R0]
+  0x0800491A:  48E0         LDR        R0, =blinkModeRT         ; [PC, #0x0380] [0x08004C9C] =0x20000754 
+  0x0800491C:  7007         STRB       R7, [R0]
+  0x0800491E:  48E8         LDR        R0, =numberOfBlinks      ; [PC, #0x03A0] [0x08004CC0] =0x200006BC 
+  0x08004920:  2104         MOVS       R1, #4
+  0x08004922:  6001         STR        R1, [R0]
+  0x08004924:  48E7         LDR        R0, =blinkCounter        ; [PC, #0x039C] [0x08004CC4] =0x200006EC 
+  0x08004926:  6001         STR        R1, [R0]
+  0x08004928:  48E7         LDR        R0, =pauseTime           ; [PC, #0x039C] [0x08004CC8] =0x20000734 
+  0x0800492A:  7007         STRB       R7, [R0]
+  0x0800492C:  48D8         LDR        R0, =0x50000818          ; [PC, #0x0360] [0x08004C90] 
+  0x0800492E:  6003         STR        R3, [R0]
+  0x08004930:  48D0         LDR        R0, =buttonState         ; [PC, #0x0340] [0x08004C74] =0x2000073A 
+  0x08004932:  7006         STRB       R6, [R0]
+  0x08004934:  48DA         LDR        R0, =onTimeCounterRT     ; [PC, #0x0368] [0x08004CA0] =0x2000069C 
+  0x08004936:  21C8         MOVS       R1, #200
+  0x08004938:  6001         STR        R1, [R0]
+  0x0800493A:  48EF         LDR        R0, =0x0800678C          ; [PC, #0x03BC] [0x08004CF8] 
+  0x0800493C:  F000 FC58    BL         puts                     ; 0x080051F0
+  0x08004940:  48E8         LDR        R0, =0x080067A9          ; [PC, #0x03A0] [0x08004CE4] 
+  0x08004942:  F000 FC55    BL         puts                     ; 0x080051F0
+  0x08004946:  9B04         LDR        R3, [SP, #16]
+  0x08004948:  2003         MOVS       R0, #3
+  0x0800494A:  7020         STRB       R0, [R4]
+  0x0800494C:  48E9         LDR        R0, =dropLimitCounter    ; [PC, #0x03A4] [0x08004CF4] =0x200006E4 
+  0x0800494E:  6006         STR        R6, [R0]
+  0x08004950:  4ECF         LDR        R6, =0x50000818          ; [PC, #0x033C] [0x08004C90] 
+
.L12:
+  0x08004952:  9801         LDR        R0, [SP, #4]
+  0x08004954:  2800         CMP        R0, #0
+  0x08004956:  D032         BEQ        .L13                     ; 0x080049BE
+  0x08004958:  2008         MOVS       R0, #8
+  0x0800495A:  6128         STR        R0, [R5, #16]
+  0x0800495C:  2010         MOVS       R0, #16
+  0x0800495E:  6028         STR        R0, [R5]
+  0x08004960:  49C5         LDR        R1, =relaisState         ; [PC, #0x0314] [0x08004C78] =0x20000730 
+  0x08004962:  2000         MOVS       R0, #0
+  0x08004964:  7008         STRB       R0, [R1]
+  0x08004966:  49DE         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0378] [0x08004CE0] =0x200006A0 
+  0x08004968:  2232         MOVS       R2, #50
+  0x0800496A:  600A         STR        R2, [R1]
+  0x0800496C:  2120         MOVS       R1, #32
+  0x0800496E:  6029         STR        R1, [R5]
+  0x08004970:  49C4         LDR        R1, =onTimeCounter       ; [PC, #0x0310] [0x08004C84] =0x200006A8 
+  0x08004972:  9A02         LDR        R2, [SP, #8]
+  0x08004974:  600A         STR        R2, [R1]
+  0x08004976:  9903         LDR        R1, [SP, #12]
+  0x08004978:  6131         STR        R1, [R6, #16]
+  0x0800497A:  49CE         LDR        R1, =offTimeCounterGN    ; [PC, #0x0338] [0x08004CB4] =0x200006B4 
+  0x0800497C:  6008         STR        R0, [R1]
+  0x0800497E:  49C3         LDR        R1, =blinkModeGN         ; [PC, #0x030C] [0x08004C8C] =0x20000758 
+  0x08004980:  7008         STRB       R0, [R1]
+  0x08004982:  49C4         LDR        R1, =onTimeCounterGN     ; [PC, #0x0310] [0x08004C94] =0x200006A4 
+  0x08004984:  6008         STR        R0, [R1]
+  0x08004986:  49CC         LDR        R1, =onTimeRT            ; [PC, #0x0330] [0x08004CB8] =0x2000073C 
+  0x08004988:  700F         STRB       R7, [R1]
+  0x0800498A:  49CC         LDR        R1, =offTimeRT           ; [PC, #0x0330] [0x08004CBC] =0x20000748 
+  0x0800498C:  700F         STRB       R7, [R1]
+  0x0800498E:  49C3         LDR        R1, =blinkModeRT         ; [PC, #0x030C] [0x08004C9C] =0x20000754 
+  0x08004990:  700F         STRB       R7, [R1]
+  0x08004992:  49CB         LDR        R1, =numberOfBlinks      ; [PC, #0x032C] [0x08004CC0] =0x200006BC 
+  0x08004994:  2202         MOVS       R2, #2
+  0x08004996:  600A         STR        R2, [R1]
+  0x08004998:  49CA         LDR        R1, =blinkCounter        ; [PC, #0x0328] [0x08004CC4] =0x200006EC 
+  0x0800499A:  600A         STR        R2, [R1]
+  0x0800499C:  49CA         LDR        R1, =pauseTime           ; [PC, #0x0328] [0x08004CC8] =0x20000734 
+  0x0800499E:  700F         STRB       R7, [R1]
+  0x080049A0:  6033         STR        R3, [R6]
+  0x080049A2:  49B4         LDR        R1, =buttonState         ; [PC, #0x02D0] [0x08004C74] =0x2000073A 
+  0x080049A4:  7008         STRB       R0, [R1]
+  0x080049A6:  48BE         LDR        R0, =onTimeCounterRT     ; [PC, #0x02F8] [0x08004CA0] =0x2000069C 
+  0x080049A8:  21C8         MOVS       R1, #200
+  0x080049AA:  6001         STR        R1, [R0]
+  0x080049AC:  48D3         LDR        R0, =0x08006950          ; [PC, #0x034C] [0x08004CFC] 
+  0x080049AE:  F000 FC1F    BL         puts                     ; 0x080051F0
+  0x080049B2:  48CC         LDR        R0, =0x080067A9          ; [PC, #0x0330] [0x08004CE4] 
+  0x080049B4:  F000 FC1C    BL         puts                     ; 0x080051F0
+  0x080049B8:  9B04         LDR        R3, [SP, #16]
+  0x080049BA:  2003         MOVS       R0, #3
+  0x080049BC:  7020         STRB       R0, [R4]
+
.L13:
+  0x080049BE:  48D0         LDR        R0, =temp                ; [PC, #0x0340] [0x08004D00] =0x20000690 
+  0x080049C0:  6800         LDR        R0, [R0]
+  0x080049C2:  2851         CMP        R0, #81
+  0x080049C4:  DA00         BGE        .L14                     ; 0x080049C8
+  0x080049C6:  E136         B          .L25                     ; 0x08004C36
+
.L14:
+  0x080049C8:  2008         MOVS       R0, #8
+  0x080049CA:  6128         STR        R0, [R5, #16]
+  0x080049CC:  2010         MOVS       R0, #16
+  0x080049CE:  6028         STR        R0, [R5]
+  0x080049D0:  49A9         LDR        R1, =relaisState         ; [PC, #0x02A4] [0x08004C78] =0x20000730 
+  0x080049D2:  2000         MOVS       R0, #0
+  0x080049D4:  7008         STRB       R0, [R1]
+  0x080049D6:  49C2         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0308] [0x08004CE0] =0x200006A0 
+  0x080049D8:  2232         MOVS       R2, #50
+  0x080049DA:  600A         STR        R2, [R1]
+  0x080049DC:  2120         MOVS       R1, #32
+  0x080049DE:  6029         STR        R1, [R5]
+  0x080049E0:  49A8         LDR        R1, =onTimeCounter       ; [PC, #0x02A0] [0x08004C84] =0x200006A8 
+  0x080049E2:  9A02         LDR        R2, [SP, #8]
+  0x080049E4:  600A         STR        R2, [R1]
+  0x080049E6:  9903         LDR        R1, [SP, #12]
+  0x080049E8:  6131         STR        R1, [R6, #16]
+  0x080049EA:  49B2         LDR        R1, =offTimeCounterGN    ; [PC, #0x02C8] [0x08004CB4] =0x200006B4 
+  0x080049EC:  6008         STR        R0, [R1]
+  0x080049EE:  49A7         LDR        R1, =blinkModeGN         ; [PC, #0x029C] [0x08004C8C] =0x20000758 
+  0x080049F0:  7008         STRB       R0, [R1]
+  0x080049F2:  49A8         LDR        R1, =onTimeCounterGN     ; [PC, #0x02A0] [0x08004C94] =0x200006A4 
+  0x080049F4:  6008         STR        R0, [R1]
+  0x080049F6:  49B0         LDR        R1, =onTimeRT            ; [PC, #0x02C0] [0x08004CB8] =0x2000073C 
+  0x080049F8:  700F         STRB       R7, [R1]
+  0x080049FA:  49B0         LDR        R1, =offTimeRT           ; [PC, #0x02C0] [0x08004CBC] =0x20000748 
+  0x080049FC:  700F         STRB       R7, [R1]
+  0x080049FE:  49A7         LDR        R1, =blinkModeRT         ; [PC, #0x029C] [0x08004C9C] =0x20000754 
+  0x08004A00:  700F         STRB       R7, [R1]
+  0x08004A02:  49AF         LDR        R1, =numberOfBlinks      ; [PC, #0x02BC] [0x08004CC0] =0x200006BC 
+  0x08004A04:  2205         MOVS       R2, #5
+  0x08004A06:  600A         STR        R2, [R1]
+  0x08004A08:  49AE         LDR        R1, =blinkCounter        ; [PC, #0x02B8] [0x08004CC4] =0x200006EC 
+  0x08004A0A:  600A         STR        R2, [R1]
+  0x08004A0C:  49AE         LDR        R1, =pauseTime           ; [PC, #0x02B8] [0x08004CC8] =0x20000734 
+  0x08004A0E:  700F         STRB       R7, [R1]
+  0x08004A10:  6033         STR        R3, [R6]
+  0x08004A12:  4998         LDR        R1, =buttonState         ; [PC, #0x0260] [0x08004C74] =0x2000073A 
+  0x08004A14:  7008         STRB       R0, [R1]
+  0x08004A16:  48A2         LDR        R0, =onTimeCounterRT     ; [PC, #0x0288] [0x08004CA0] =0x2000069C 
+  0x08004A18:  21C8         MOVS       R1, #200
+  0x08004A1A:  6001         STR        R1, [R0]
+  0x08004A1C:  48B9         LDR        R0, =0x0800632C          ; [PC, #0x02E4] [0x08004D04] 
+
.L15:
+  0x08004A1E:  F000 FBE7    BL         puts                     ; 0x080051F0
+  0x08004A22:  2003         MOVS       R0, #3
+  0x08004A24:  E106         B          .L24                     ; 0x08004C34
+  0x08004A26:  46C0         NOP
+  0x08004A28:  50000010     DC.W       0x50000010
+  0x08004A2C:  2000073A     DC.W       buttonState
+  0x08004A30:  200006A8     DC.W       onTimeCounter
+  0x08004A34:  2000073C     DC.W       onTimeRT
+  0x08004A38:  20000748     DC.W       offTimeRT
+  0x08004A3C:  20000754     DC.W       blinkModeRT
+  0x08004A40:  200006BC     DC.W       numberOfBlinks
+  0x08004A44:  200006EC     DC.W       blinkCounter
+  0x08004A48:  080067A9     DC.W       080067A9               ; R_ARM_ABS32
+  0x08004A4C:  2000069C     DC.W       onTimeCounterRT
+  0x08004A50:  20000734     DC.W       pauseTime
+  0x08004A54:  20000730     DC.W       relaisState
+  0x08004A58:  200006A0     DC.W       onTimeCounterRESET
+  0x08004A5C:  50000818     DC.W       0x50000818
+  0x08004A60:  200006B4     DC.W       offTimeCounterGN
+  0x08004A64:  20000758     DC.W       blinkModeGN
+  0x08004A68:  200006A4     DC.W       onTimeCounterGN
+  0x08004A6C:  0800698C     DC.W       0800698C               ; R_ARM_ABS32
+  0x08004A70:  200006B8     DC.W       offTimeCounter
+  0x08004A74:  2000075C     DC.W       alarmMode
+  0x08004A78:  200006B0     DC.W       offTimeCounterRT
+  0x08004A7C:  08006309     DC.W       08006309               ; R_ARM_ABS32
+  0x08004A80:  20000732     DC.W       smState.160
+  0x08004A84:  20000704     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
+  0x08004A88:  200006E4     DC.W       dropLimitCounter
+
.L16:
+  0x08004A8C:  2010         MOVS       R0, #16
+  0x08004A8E:  6128         STR        R0, [R5, #16]
+  0x08004A90:  2008         MOVS       R0, #8
+  0x08004A92:  6028         STR        R0, [R5]
+  0x08004A94:  4878         LDR        R0, =relaisState         ; [PC, #0x01E0] [0x08004C78] =0x20000730 
+  0x08004A96:  2601         MOVS       R6, #1
+  0x08004A98:  7006         STRB       R6, [R0]
+  0x08004A9A:  4878         LDR        R0, =onTimeCounterSET    ; [PC, #0x01E0] [0x08004C7C] =0x20000698 
+  0x08004A9C:  2132         MOVS       R1, #50
+  0x08004A9E:  6001         STR        R1, [R0]
+  0x08004AA0:  2020         MOVS       R0, #32
+  0x08004AA2:  6028         STR        R0, [R5]
+  0x08004AA4:  4876         LDR        R0, =onTimeGN            ; [PC, #0x01D8] [0x08004C80] =0x20000740 
+  0x08004AA6:  7006         STRB       R6, [R0]
+  0x08004AA8:  4876         LDR        R0, =onTimeCounter       ; [PC, #0x01D8] [0x08004C84] =0x200006A8 
+  0x08004AAA:  21C8         MOVS       R1, #200
+  0x08004AAC:  6001         STR        R1, [R0]
+  0x08004AAE:  4876         LDR        R0, =offTimeGN           ; [PC, #0x01D8] [0x08004C88] =0x2000074C 
+  0x08004AB0:  7006         STRB       R6, [R0]
+  0x08004AB2:  4876         LDR        R0, =blinkModeGN         ; [PC, #0x01D8] [0x08004C8C] =0x20000758 
+  0x08004AB4:  7006         STRB       R6, [R0]
+  0x08004AB6:  03B0         LSLS       R0, R6, #14
+  0x08004AB8:  4A75         LDR        R2, =0x50000818          ; [PC, #0x01D4] [0x08004C90] 
+  0x08004ABA:  6010         STR        R0, [R2]
+  0x08004ABC:  4875         LDR        R0, =onTimeCounterGN     ; [PC, #0x01D4] [0x08004C94] =0x200006A4 
+  0x08004ABE:  6001         STR        R1, [R0]
+  0x08004AC0:  03F0         LSLS       R0, R6, #15
+  0x08004AC2:  6110         STR        R0, [R2, #16]
+  0x08004AC4:  4874         LDR        R0, =offTimeCounterRT    ; [PC, #0x01D0] [0x08004C98] =0x200006B0 
+  0x08004AC6:  2100         MOVS       R1, #0
+  0x08004AC8:  6001         STR        R1, [R0]
+  0x08004ACA:  4874         LDR        R0, =blinkModeRT         ; [PC, #0x01D0] [0x08004C9C] =0x20000754 
+  0x08004ACC:  7001         STRB       R1, [R0]
+  0x08004ACE:  4874         LDR        R0, =onTimeCounterRT     ; [PC, #0x01D0] [0x08004CA0] =0x2000069C 
+  0x08004AD0:  6001         STR        R1, [R0]
+  0x08004AD2:  4874         LDR        R0, =0x08006549          ; [PC, #0x01D0] [0x08004CA4] 
+  0x08004AD4:  F000 FB8C    BL         puts                     ; 0x080051F0
+  0x08004AD8:  7026         STRB       R6, [R4]
+  0x08004ADA:  4E66         LDR        R6, =buttonState         ; [PC, #0x0198] [0x08004C74] =0x2000073A 
+  0x08004ADC:  7831         LDRB       R1, [R6]
+
.L17:
+  0x08004ADE:  2902         CMP        R1, #2
+  0x08004AE0:  D137         BNE        .L18                     ; 0x08004B52
+  0x08004AE2:  2010         MOVS       R0, #16
+  0x08004AE4:  6128         STR        R0, [R5, #16]
+  0x08004AE6:  2008         MOVS       R0, #8
+  0x08004AE8:  6028         STR        R0, [R5]
+  0x08004AEA:  4963         LDR        R1, =relaisState         ; [PC, #0x018C] [0x08004C78] =0x20000730 
+  0x08004AEC:  2001         MOVS       R0, #1
+  0x08004AEE:  7008         STRB       R0, [R1]
+  0x08004AF0:  4962         LDR        R1, =onTimeCounterSET    ; [PC, #0x0188] [0x08004C7C] =0x20000698 
+  0x08004AF2:  2232         MOVS       R2, #50
+  0x08004AF4:  600A         STR        R2, [R1]
+  0x08004AF6:  496C         LDR        R1, =onTime              ; [PC, #0x01B0] [0x08004CA8] =0x20000744 
+  0x08004AF8:  7008         STRB       R0, [R1]
+  0x08004AFA:  496C         LDR        R1, =offTime             ; [PC, #0x01B0] [0x08004CAC] =0x20000750 
+  0x08004AFC:  7008         STRB       R0, [R1]
+  0x08004AFE:  496C         LDR        R1, =alarmMode           ; [PC, #0x01B0] [0x08004CB0] =0x2000075C 
+  0x08004B00:  7008         STRB       R0, [R1]
+  0x08004B02:  2120         MOVS       R1, #32
+  0x08004B04:  6029         STR        R1, [R5]
+  0x08004B06:  4A5F         LDR        R2, =onTimeCounter       ; [PC, #0x017C] [0x08004C84] =0x200006A8 
+  0x08004B08:  21C8         MOVS       R1, #200
+  0x08004B0A:  6011         STR        R1, [R2]
+  0x08004B0C:  0383         LSLS       R3, R0, #14
+  0x08004B0E:  4A60         LDR        R2, =0x50000818          ; [PC, #0x0180] [0x08004C90] 
+  0x08004B10:  6013         STR        R3, [R2]
+  0x08004B12:  4B60         LDR        R3, =onTimeCounterGN     ; [PC, #0x0180] [0x08004C94] =0x200006A4 
+  0x08004B14:  2500         MOVS       R5, #0
+  0x08004B16:  601D         STR        R5, [R3]
+  0x08004B18:  4B5C         LDR        R3, =blinkModeGN         ; [PC, #0x0170] [0x08004C8C] =0x20000758 
+  0x08004B1A:  701D         STRB       R5, [R3]
+  0x08004B1C:  4B65         LDR        R3, =offTimeCounterGN    ; [PC, #0x0194] [0x08004CB4] =0x200006B4 
+  0x08004B1E:  601D         STR        R5, [R3]
+  0x08004B20:  03C3         LSLS       R3, R0, #15
+  0x08004B22:  6113         STR        R3, [R2, #16]
+  0x08004B24:  4E64         LDR        R6, =onTimeRT            ; [PC, #0x0190] [0x08004CB8] =0x2000073C 
+  0x08004B26:  7030         STRB       R0, [R6]
+  0x08004B28:  4E5B         LDR        R6, =offTimeCounterRT    ; [PC, #0x016C] [0x08004C98] =0x200006B0 
+  0x08004B2A:  6035         STR        R5, [R6]
+  0x08004B2C:  4E51         LDR        R6, =buttonState         ; [PC, #0x0144] [0x08004C74] =0x2000073A 
+  0x08004B2E:  4D63         LDR        R5, =offTimeRT           ; [PC, #0x018C] [0x08004CBC] =0x20000748 
+  0x08004B30:  7028         STRB       R0, [R5]
+  0x08004B32:  4D5A         LDR        R5, =blinkModeRT         ; [PC, #0x0168] [0x08004C9C] =0x20000754 
+  0x08004B34:  7028         STRB       R0, [R5]
+  0x08004B36:  4D62         LDR        R5, =numberOfBlinks      ; [PC, #0x0188] [0x08004CC0] =0x200006BC 
+  0x08004B38:  6028         STR        R0, [R5]
+  0x08004B3A:  4D62         LDR        R5, =blinkCounter        ; [PC, #0x0188] [0x08004CC4] =0x200006EC 
+  0x08004B3C:  6028         STR        R0, [R5]
+  0x08004B3E:  4D62         LDR        R5, =pauseTime           ; [PC, #0x0188] [0x08004CC8] =0x20000734 
+  0x08004B40:  7028         STRB       R0, [R5]
+  0x08004B42:  6013         STR        R3, [R2]
+  0x08004B44:  4856         LDR        R0, =onTimeCounterRT     ; [PC, #0x0158] [0x08004CA0] =0x2000069C 
+  0x08004B46:  6001         STR        R1, [R0]
+  0x08004B48:  4860         LDR        R0, =0x08006763          ; [PC, #0x0180] [0x08004CCC] 
+  0x08004B4A:  F000 FB51    BL         puts                     ; 0x080051F0
+  0x08004B4E:  2002         MOVS       R0, #2
+  0x08004B50:  7020         STRB       R0, [R4]
+
.L18:
+  0x08004B52:  6838         LDR        R0, [R7]
+  0x08004B54:  2801         CMP        R0, #1
+  0x08004B56:  D16E         BNE        .L25                     ; 0x08004C36
+  0x08004B58:  485D         LDR        R0, =uwTick              ; [PC, #0x0174] [0x08004CD0] =0x2000068C 
+  0x08004B5A:  6802         LDR        R2, [R0]
+  0x08004B5C:  495D         LDR        R1, =SECONDARYPROTECTION_SM_Error.oldTimeMSTick ; [PC, #0x0174] [0x08004CD4] =0x20000714 
+  0x08004B5E:  680B         LDR        R3, [R1]
+  0x08004B60:  4293         CMP        R3, R2
+  0x08004B62:  D102         BNE        .L19                     ; 0x08004B6A
+  0x08004B64:  485C         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0170] [0x08004CD8] =0x2000070C 
+  0x08004B66:  6800         LDR        R0, [R0]
+  0x08004B68:  E005         B          .L20                     ; 0x08004B76
+
.L19:
+  0x08004B6A:  6800         LDR        R0, [R0]
+  0x08004B6C:  6008         STR        R0, [R1]
+  0x08004B6E:  495A         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0168] [0x08004CD8] =0x2000070C 
+  0x08004B70:  6808         LDR        R0, [R1]
+  0x08004B72:  1C40         ADDS       R0, R0, #1
+  0x08004B74:  6008         STR        R0, [R1]
+
.L20:
+  0x08004B76:  4959         LDR        R1, =0x0036EE81          ; [PC, #0x0164] [0x08004CDC] 
+  0x08004B78:  4288         CMP        R0, R1
+  0x08004B7A:  D35C         BCC        .L25                     ; 0x08004C36
+  0x08004B7C:  4856         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0158] [0x08004CD8] =0x2000070C 
+  0x08004B7E:  2100         MOVS       R1, #0
+  0x08004B80:  6001         STR        R1, [R0]
+  0x08004B82:  2001         MOVS       R0, #1
+  0x08004B84:  7030         STRB       R0, [R6]
+  0x08004B86:  E056         B          .L25                     ; 0x08004C36
+
.L21:
+  0x08004B88:  2010         MOVS       R0, #16
+  0x08004B8A:  6128         STR        R0, [R5, #16]
+  0x08004B8C:  2008         MOVS       R0, #8
+  0x08004B8E:  6028         STR        R0, [R5]
+  0x08004B90:  4839         LDR        R0, =relaisState         ; [PC, #228] [0x08004C78] =0x20000730 
+  0x08004B92:  7001         STRB       R1, [R0]
+  0x08004B94:  4839         LDR        R0, =onTimeCounterSET    ; [PC, #228] [0x08004C7C] =0x20000698 
+  0x08004B96:  2232         MOVS       R2, #50
+  0x08004B98:  6002         STR        R2, [R0]
+  0x08004B9A:  2020         MOVS       R0, #32
+  0x08004B9C:  6028         STR        R0, [R5]
+  0x08004B9E:  4838         LDR        R0, =onTimeGN            ; [PC, #224] [0x08004C80] =0x20000740 
+  0x08004BA0:  7001         STRB       R1, [R0]
+  0x08004BA2:  4838         LDR        R0, =onTimeCounter       ; [PC, #224] [0x08004C84] =0x200006A8 
+  0x08004BA4:  22C8         MOVS       R2, #200
+  0x08004BA6:  6002         STR        R2, [R0]
+  0x08004BA8:  4837         LDR        R0, =offTimeGN           ; [PC, #220] [0x08004C88] =0x2000074C 
+  0x08004BAA:  7001         STRB       R1, [R0]
+  0x08004BAC:  038A         LSLS       R2, R1, #14
+  0x08004BAE:  483D         LDR        R0, =0x08006549          ; [PC, #244] [0x08004CA4] 
+  0x08004BB0:  4B38         LDR        R3, =onTimeCounterGN     ; [PC, #224] [0x08004C94] =0x200006A4 
+  0x08004BB2:  4E36         LDR        R6, =blinkModeGN         ; [PC, #216] [0x08004C8C] =0x20000758 
+  0x08004BB4:  460F         MOV        R7, R1
+
.L22:
+  0x08004BB6:  7031         STRB       R1, [R6]
+  0x08004BB8:  4935         LDR        R1, =0x50000818          ; [PC, #212] [0x08004C90] 
+  0x08004BBA:  600A         STR        R2, [R1]
+  0x08004BBC:  21C8         MOVS       R1, #200
+  0x08004BBE:  6019         STR        R1, [R3]
+  0x08004BC0:  F000 FB16    BL         puts                     ; 0x080051F0
+  0x08004BC4:  7027         STRB       R7, [R4]
+  0x08004BC6:  482B         LDR        R0, =buttonState         ; [PC, #172] [0x08004C74] =0x2000073A 
+  0x08004BC8:  7801         LDRB       R1, [R0]
+
.L23:
+  0x08004BCA:  2902         CMP        R1, #2
+  0x08004BCC:  D133         BNE        .L25                     ; 0x08004C36
+  0x08004BCE:  2010         MOVS       R0, #16
+  0x08004BD0:  6128         STR        R0, [R5, #16]
+  0x08004BD2:  2008         MOVS       R0, #8
+  0x08004BD4:  6028         STR        R0, [R5]
+  0x08004BD6:  4928         LDR        R1, =relaisState         ; [PC, #160] [0x08004C78] =0x20000730 
+  0x08004BD8:  2001         MOVS       R0, #1
+  0x08004BDA:  7008         STRB       R0, [R1]
+  0x08004BDC:  4927         LDR        R1, =onTimeCounterSET    ; [PC, #156] [0x08004C7C] =0x20000698 
+  0x08004BDE:  2232         MOVS       R2, #50
+  0x08004BE0:  600A         STR        R2, [R1]
+  0x08004BE2:  4931         LDR        R1, =onTime              ; [PC, #196] [0x08004CA8] =0x20000744 
+  0x08004BE4:  7008         STRB       R0, [R1]
+  0x08004BE6:  4931         LDR        R1, =offTime             ; [PC, #196] [0x08004CAC] =0x20000750 
+  0x08004BE8:  7008         STRB       R0, [R1]
+  0x08004BEA:  4931         LDR        R1, =alarmMode           ; [PC, #196] [0x08004CB0] =0x2000075C 
+  0x08004BEC:  7008         STRB       R0, [R1]
+  0x08004BEE:  2120         MOVS       R1, #32
+  0x08004BF0:  6029         STR        R1, [R5]
+  0x08004BF2:  4A24         LDR        R2, =onTimeCounter       ; [PC, #144] [0x08004C84] =0x200006A8 
+  0x08004BF4:  21C8         MOVS       R1, #200
+  0x08004BF6:  6011         STR        R1, [R2]
+  0x08004BF8:  0383         LSLS       R3, R0, #14
+  0x08004BFA:  4A25         LDR        R2, =0x50000818          ; [PC, #148] [0x08004C90] 
+  0x08004BFC:  6013         STR        R3, [R2]
+  0x08004BFE:  4B25         LDR        R3, =onTimeCounterGN     ; [PC, #148] [0x08004C94] =0x200006A4 
+  0x08004C00:  2500         MOVS       R5, #0
+  0x08004C02:  601D         STR        R5, [R3]
+  0x08004C04:  4B21         LDR        R3, =blinkModeGN         ; [PC, #132] [0x08004C8C] =0x20000758 
+  0x08004C06:  701D         STRB       R5, [R3]
+  0x08004C08:  4B2A         LDR        R3, =offTimeCounterGN    ; [PC, #168] [0x08004CB4] =0x200006B4 
+  0x08004C0A:  601D         STR        R5, [R3]
+  0x08004C0C:  4B2A         LDR        R3, =onTimeRT            ; [PC, #168] [0x08004CB8] =0x2000073C 
+  0x08004C0E:  7018         STRB       R0, [R3]
+  0x08004C10:  4B2A         LDR        R3, =offTimeRT           ; [PC, #168] [0x08004CBC] =0x20000748 
+  0x08004C12:  7018         STRB       R0, [R3]
+  0x08004C14:  4B21         LDR        R3, =blinkModeRT         ; [PC, #132] [0x08004C9C] =0x20000754 
+  0x08004C16:  7018         STRB       R0, [R3]
+  0x08004C18:  4B29         LDR        R3, =numberOfBlinks      ; [PC, #164] [0x08004CC0] =0x200006BC 
+  0x08004C1A:  6018         STR        R0, [R3]
+  0x08004C1C:  4B29         LDR        R3, =blinkCounter        ; [PC, #164] [0x08004CC4] =0x200006EC 
+  0x08004C1E:  6018         STR        R0, [R3]
+  0x08004C20:  4B29         LDR        R3, =pauseTime           ; [PC, #164] [0x08004CC8] =0x20000734 
+  0x08004C22:  7018         STRB       R0, [R3]
+  0x08004C24:  03C0         LSLS       R0, R0, #15
+  0x08004C26:  6010         STR        R0, [R2]
+  0x08004C28:  481D         LDR        R0, =onTimeCounterRT     ; [PC, #116] [0x08004CA0] =0x2000069C 
+  0x08004C2A:  6001         STR        R1, [R0]
+  0x08004C2C:  4827         LDR        R0, =0x08006763          ; [PC, #156] [0x08004CCC] 
+  0x08004C2E:  F000 FADF    BL         puts                     ; 0x080051F0
+  0x08004C32:  2002         MOVS       R0, #2
+
.L24:
+  0x08004C34:  7020         STRB       R0, [R4]
+
.L25:
+  0x08004C36:  B005         ADD        SP, SP, #20
+  0x08004C38:  BDF0         POP        {R4-R7, PC}
+
.L26:
+  0x08004C3A:  482B         LDR        R0, =SECONDARYPROTECTION_SM_On.oldtime ; [PC, #172] [0x08004CE8] =0x200006FC 
+  0x08004C3C:  6802         LDR        R2, [R0]
+  0x08004C3E:  4924         LDR        R1, =uwTick              ; [PC, #144] [0x08004CD0] =0x2000068C 
+  0x08004C40:  680B         LDR        R3, [R1]
+  0x08004C42:  4293         CMP        R3, R2
+  0x08004C44:  D103         BNE        .L27                     ; 0x08004C4E
+  0x08004C46:  2100         MOVS       R1, #0
+  0x08004C48:  9B04         LDR        R3, [SP, #16]
+  0x08004C4A:  9A03         LDR        R2, [SP, #12]
+  0x08004C4C:  E619         B          .L10                     ; 0x08004882
+
.L27:
+  0x08004C4E:  6809         LDR        R1, [R1]
+  0x08004C50:  6001         STR        R1, [R0]
+  0x08004C52:  4926         LDR        R1, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter ; [PC, #152] [0x08004CEC] =0x20000704 
+  0x08004C54:  680B         LDR        R3, [R1]
+  0x08004C56:  1C5A         ADDS       R2, R3, #1
+  0x08004C58:  2000         MOVS       R0, #0
+  0x08004C5A:  4E25         LDR        R6, =0x0000752F          ; [PC, #148] [0x08004CF0] 
+  0x08004C5C:  42B3         CMP        R3, R6
+  0x08004C5E:  4603         MOV        R3, R0
+  0x08004C60:  DC00         BGT        .L28                     ; 0x08004C64
+  0x08004C62:  4613         MOV        R3, R2
+
.L28:
+  0x08004C64:  600B         STR        R3, [R1]
+  0x08004C66:  4639         MOV        R1, R7
+  0x08004C68:  DC00         BGT        .L29                     ; 0x08004C6C
+  0x08004C6A:  2100         MOVS       R1, #0
+
.L29:
+  0x08004C6C:  9B04         LDR        R3, [SP, #16]
+  0x08004C6E:  4E08         LDR        R6, =0x50000818          ; [PC, #32] [0x08004C90] 
+  0x08004C70:  9A03         LDR        R2, [SP, #12]
+  0x08004C72:  E606         B          .L10                     ; 0x08004882
+  0x08004C74:  2000073A     DC.W       buttonState
+  0x08004C78:  20000730     DC.W       relaisState
+  0x08004C7C:  20000698     DC.W       onTimeCounterSET
+  0x08004C80:  20000740     DC.W       onTimeGN
+  0x08004C84:  200006A8     DC.W       onTimeCounter
+  0x08004C88:  2000074C     DC.W       offTimeGN
+  0x08004C8C:  20000758     DC.W       blinkModeGN
+  0x08004C90:  50000818     DC.W       0x50000818
+  0x08004C94:  200006A4     DC.W       onTimeCounterGN
+  0x08004C98:  200006B0     DC.W       offTimeCounterRT
+  0x08004C9C:  20000754     DC.W       blinkModeRT
+  0x08004CA0:  2000069C     DC.W       onTimeCounterRT
+  0x08004CA4:  08006549     DC.W       08006549               ; R_ARM_ABS32
+  0x08004CA8:  20000744     DC.W       onTime
+  0x08004CAC:  20000750     DC.W       offTime
+  0x08004CB0:  2000075C     DC.W       alarmMode
+  0x08004CB4:  200006B4     DC.W       offTimeCounterGN
+  0x08004CB8:  2000073C     DC.W       onTimeRT
+  0x08004CBC:  20000748     DC.W       offTimeRT
+  0x08004CC0:  200006BC     DC.W       numberOfBlinks
+  0x08004CC4:  200006EC     DC.W       blinkCounter
+  0x08004CC8:  20000734     DC.W       pauseTime
+  0x08004CCC:  08006763     DC.W       08006763               ; R_ARM_ABS32
+  0x08004CD0:  2000068C     DC.W       uwTick
+  0x08004CD4:  20000714     DC.W       SECONDARYPROTECTION_SM_Error.oldTimeMSTick
+  0x08004CD8:  2000070C     DC.W       SECONDARYPROTECTION_SM_Error.retry_counter
+  0x08004CDC:  0036EE81     DC.W       0x0036EE81
+  0x08004CE0:  200006A0     DC.W       onTimeCounterRESET
+  0x08004CE4:  080067A9     DC.W       080067A9               ; R_ARM_ABS32
+  0x08004CE8:  200006FC     DC.W       SECONDARYPROTECTION_SM_On.oldtime
+  0x08004CEC:  20000704     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
+  0x08004CF0:  0000752F     DC.W       0x0000752F
+  0x08004CF4:  200006E4     DC.W       dropLimitCounter
+  0x08004CF8:  0800678C     DC.W       0800678C               ; R_ARM_ABS32
+  0x08004CFC:  08006950     DC.W       08006950               ; R_ARM_ABS32
+  0x08004D00:  20000690     DC.W       temp
+  0x08004D04:  0800632C     DC.W       0800632C               ; R_ARM_ABS32
+
+

Section .text.MODE_SECONDARYPROTECTION_PLUS_Exec from PowerPro_lto.o, size=1108, align=4

+
+
MODE_SECONDARYPROTECTION_PLUS_Exec:
+  0x08004D08:  B5F0         PUSH       {R4-R7, LR}
+  0x08004D0A:  B085         SUB        SP, SP, #20
+  0x08004D0C:  4EEC         LDR        R6, =autoRetryMode.170   ; [PC, #0x03B0] [0x080050C0] =0x200006F0 
+  0x08004D0E:  6030         STR        R0, [R6]
+  0x08004D10:  4DEC         LDR        R5, =0x50000418          ; [PC, #0x03B0] [0x080050C4] 
+  0x08004D12:  4628         MOV        R0, R5
+  0x08004D14:  3808         SUBS       R0, #8
+  0x08004D16:  6800         LDR        R0, [R0]
+  0x08004D18:  0740         LSLS       R0, R0, #29
+  0x08004D1A:  0FC0         LSRS       R0, R0, #31
+  0x08004D1C:  4BEA         LDR        R3, =smState.171         ; [PC, #0x03A8] [0x080050C8] =0x20000731 
+  0x08004D1E:  7819         LDRB       R1, [R3]
+  0x08004D20:  2902         CMP        R1, #2
+  0x08004D22:  D038         BEQ        .L1                      ; 0x08004D96
+  0x08004D24:  2901         CMP        R1, #1
+  0x08004D26:  D145         BNE        .L2                      ; 0x08004DB4
+  0x08004D28:  217D         MOVS       R1, #125
+  0x08004D2A:  008A         LSLS       R2, R1, #2
+  0x08004D2C:  2701         MOVS       R7, #1
+  0x08004D2E:  03BC         LSLS       R4, R7, #14
+  0x08004D30:  03FB         LSLS       R3, R7, #15
+  0x08004D32:  2800         CMP        R0, #0
+  0x08004D34:  4EED         LDR        R6, =0x50000818          ; [PC, #0x03B4] [0x080050EC] 
+  0x08004D36:  D162         BNE        .L5                      ; 0x08004DFE
+  0x08004D38:  2008         MOVS       R0, #8
+  0x08004D3A:  6128         STR        R0, [R5, #16]
+  0x08004D3C:  2010         MOVS       R0, #16
+  0x08004D3E:  6028         STR        R0, [R5]
+  0x08004D40:  49E4         LDR        R1, =relaisState         ; [PC, #0x0390] [0x080050D4] =0x20000730 
+  0x08004D42:  2000         MOVS       R0, #0
+  0x08004D44:  7008         STRB       R0, [R1]
+  0x08004D46:  49F6         LDR        R1, =onTimeCounterRESET  ; [PC, #0x03D8] [0x08005120] =0x200006A0 
+  0x08004D48:  4616         MOV        R6, R2
+  0x08004D4A:  2232         MOVS       R2, #50
+  0x08004D4C:  600A         STR        R2, [R1]
+  0x08004D4E:  2120         MOVS       R1, #32
+  0x08004D50:  6029         STR        R1, [R5]
+  0x08004D52:  49E3         LDR        R1, =onTimeCounter       ; [PC, #0x038C] [0x080050E0] =0x200006A8 
+  0x08004D54:  600E         STR        R6, [R1]
+  0x08004D56:  4DE5         LDR        R5, =0x50000818          ; [PC, #0x0394] [0x080050EC] 
+  0x08004D58:  612C         STR        R4, [R5, #16]
+  0x08004D5A:  49F2         LDR        R1, =offTimeCounterGN    ; [PC, #0x03C8] [0x08005124] =0x200006B4 
+  0x08004D5C:  6008         STR        R0, [R1]
+  0x08004D5E:  49E2         LDR        R1, =blinkModeGN         ; [PC, #0x0388] [0x080050E8] =0x20000758 
+  0x08004D60:  7008         STRB       R0, [R1]
+  0x08004D62:  49E3         LDR        R1, =onTimeCounterGN     ; [PC, #0x038C] [0x080050F0] =0x200006A4 
+  0x08004D64:  6008         STR        R0, [R1]
+  0x08004D66:  49F2         LDR        R1, =onTimeRT            ; [PC, #0x03C8] [0x08005130] =0x2000073C 
+  0x08004D68:  700F         STRB       R7, [R1]
+  0x08004D6A:  49F2         LDR        R1, =offTimeRT           ; [PC, #0x03C8] [0x08005134] =0x20000748 
+  0x08004D6C:  700F         STRB       R7, [R1]
+  0x08004D6E:  49E2         LDR        R1, =blinkModeRT         ; [PC, #0x0388] [0x080050F8] =0x20000754 
+  0x08004D70:  700F         STRB       R7, [R1]
+  0x08004D72:  49F1         LDR        R1, =numberOfBlinks      ; [PC, #0x03C4] [0x08005138] =0x200006BC 
+  0x08004D74:  2203         MOVS       R2, #3
+  0x08004D76:  600A         STR        R2, [R1]
+  0x08004D78:  49F0         LDR        R1, =blinkCounter        ; [PC, #0x03C0] [0x0800513C] =0x200006EC 
+  0x08004D7A:  600A         STR        R2, [R1]
+  0x08004D7C:  49F0         LDR        R1, =pauseTime           ; [PC, #0x03C0] [0x08005140] =0x20000734 
+  0x08004D7E:  700F         STRB       R7, [R1]
+  0x08004D80:  602B         STR        R3, [R5]
+  0x08004D82:  49D2         LDR        R1, =buttonState         ; [PC, #0x0348] [0x080050CC] =0x2000073A 
+  0x08004D84:  7008         STRB       R0, [R1]
+  0x08004D86:  48DD         LDR        R0, =onTimeCounterRT     ; [PC, #0x0374] [0x080050FC] =0x2000069C 
+  0x08004D88:  21C8         MOVS       R1, #200
+  0x08004D8A:  6001         STR        R1, [R0]
+  0x08004D8C:  48F2         LDR        R0, =0x0800698C          ; [PC, #0x03C8] [0x08005158] 
+  0x08004D8E:  F000 FA2F    BL         puts                     ; 0x080051F0
+  0x08004D92:  48ED         LDR        R0, =0x080067A9          ; [PC, #0x03B4] [0x08005148] 
+  0x08004D94:  E18C         B          .L23                     ; 0x080050B0
+
.L1:
+  0x08004D96:  4CCD         LDR        R4, =buttonState         ; [PC, #0x0334] [0x080050CC] =0x2000073A 
+  0x08004D98:  7821         LDRB       R1, [R4]
+  0x08004D9A:  2901         CMP        R1, #1
+  0x08004D9C:  D168         BNE        .L8                      ; 0x08004E70
+  0x08004D9E:  2800         CMP        R0, #0
+  0x08004DA0:  D13C         BNE        .L7                      ; 0x08004E1C
+  0x08004DA2:  2020         MOVS       R0, #32
+  0x08004DA4:  6028         STR        R0, [R5]
+  0x08004DA6:  2000         MOVS       R0, #0
+  0x08004DA8:  7020         STRB       R0, [R4]
+  0x08004DAA:  207D         MOVS       R0, #125
+  0x08004DAC:  0080         LSLS       R0, R0, #2
+  0x08004DAE:  49CC         LDR        R1, =onTimeCounter       ; [PC, #0x0330] [0x080050E0] =0x200006A8 
+  0x08004DB0:  6008         STR        R0, [R1]
+  0x08004DB2:  E05D         B          .L8                      ; 0x08004E70
+
.L2:
+  0x08004DB4:  49D6         LDR        R1, =0x50000010          ; [PC, #0x0358] [0x08005110] 
+  0x08004DB6:  680A         LDR        R2, [R1]
+  0x08004DB8:  07D2         LSLS       R2, R2, #31
+  0x08004DBA:  D000         BEQ        .L3                      ; 0x08004DBE
+  0x08004DBC:  6809         LDR        R1, [R1]
+
.L3:
+  0x08004DBE:  4AC3         LDR        R2, =buttonState         ; [PC, #0x030C] [0x080050CC] =0x2000073A 
+  0x08004DC0:  7811         LDRB       R1, [R2]
+  0x08004DC2:  2901         CMP        R1, #1
+  0x08004DC4:  D000         BEQ        .L4                      ; 0x08004DC8
+  0x08004DC6:  E178         B          .L24                     ; 0x080050BA
+
.L4:
+  0x08004DC8:  2800         CMP        R0, #0
+  0x08004DCA:  D16E         BNE        .L13                     ; 0x08004EAA
+  0x08004DCC:  2020         MOVS       R0, #32
+  0x08004DCE:  6028         STR        R0, [R5]
+  0x08004DD0:  2000         MOVS       R0, #0
+  0x08004DD2:  7010         STRB       R0, [R2]
+  0x08004DD4:  207D         MOVS       R0, #125
+  0x08004DD6:  0080         LSLS       R0, R0, #2
+  0x08004DD8:  4AC1         LDR        R2, =onTimeCounter       ; [PC, #0x0304] [0x080050E0] =0x200006A8 
+  0x08004DDA:  6010         STR        R0, [R2]
+  0x08004DDC:  48D4         LDR        R0, =onTimeRT            ; [PC, #0x0350] [0x08005130] =0x2000073C 
+  0x08004DDE:  7001         STRB       R1, [R0]
+  0x08004DE0:  48D4         LDR        R0, =offTimeRT           ; [PC, #0x0350] [0x08005134] =0x20000748 
+  0x08004DE2:  7001         STRB       R1, [R0]
+  0x08004DE4:  48C4         LDR        R0, =blinkModeRT         ; [PC, #0x0310] [0x080050F8] =0x20000754 
+  0x08004DE6:  7001         STRB       R1, [R0]
+  0x08004DE8:  48D3         LDR        R0, =numberOfBlinks      ; [PC, #0x034C] [0x08005138] =0x200006BC 
+  0x08004DEA:  2203         MOVS       R2, #3
+  0x08004DEC:  6002         STR        R2, [R0]
+  0x08004DEE:  48D3         LDR        R0, =blinkCounter        ; [PC, #0x034C] [0x0800513C] =0x200006EC 
+  0x08004DF0:  6002         STR        R2, [R0]
+  0x08004DF2:  03CA         LSLS       R2, R1, #15
+  0x08004DF4:  2402         MOVS       R4, #2
+  0x08004DF6:  48D4         LDR        R0, =0x080067A9          ; [PC, #0x0350] [0x08005148] 
+  0x08004DF8:  4BC0         LDR        R3, =onTimeCounterRT     ; [PC, #0x0300] [0x080050FC] =0x2000069C 
+  0x08004DFA:  4DD1         LDR        R5, =pauseTime           ; [PC, #0x0344] [0x08005140] =0x20000734 
+  0x08004DFC:  E06C         B          .L14                     ; 0x08004ED8
+
.L5:
+  0x08004DFE:  9101         STR        R1, [SP, #4]
+  0x08004E00:  48C3         LDR        R0, =0x50000010          ; [PC, #0x030C] [0x08005110] 
+  0x08004E02:  6801         LDR        R1, [R0]
+  0x08004E04:  07C9         LSLS       R1, R1, #31
+  0x08004E06:  9303         STR        R3, [SP, #12]
+  0x08004E08:  9404         STR        R4, [SP, #16]
+  0x08004E0A:  9202         STR        R2, [SP, #8]
+  0x08004E0C:  D002         BEQ        .L6                      ; 0x08004E14
+  0x08004E0E:  6800         LDR        R0, [R0]
+  0x08004E10:  0780         LSLS       R0, R0, #30
+  0x08004E12:  D46B         BMI        .L15                     ; 0x08004EEC
+
.L6:
+  0x08004E14:  48C0         LDR        R0, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 ; [PC, #0x0300] [0x08005118] =0x20000700 
+  0x08004E16:  2400         MOVS       R4, #0
+  0x08004E18:  6004         STR        R4, [R0]
+  0x08004E1A:  E07E         B          .L19                     ; 0x08004F1A
+
.L7:
+  0x08004E1C:  49AC         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x02B0] [0x080050D0] =0x20000708 
+  0x08004E1E:  2000         MOVS       R0, #0
+  0x08004E20:  6008         STR        R0, [R1]
+  0x08004E22:  2110         MOVS       R1, #16
+  0x08004E24:  6129         STR        R1, [R5, #16]
+  0x08004E26:  2108         MOVS       R1, #8
+  0x08004E28:  6029         STR        R1, [R5]
+  0x08004E2A:  49AA         LDR        R1, =relaisState         ; [PC, #0x02A8] [0x080050D4] =0x20000730 
+  0x08004E2C:  2701         MOVS       R7, #1
+  0x08004E2E:  700F         STRB       R7, [R1]
+  0x08004E30:  49A9         LDR        R1, =onTimeCounterSET    ; [PC, #0x02A4] [0x080050D8] =0x20000698 
+  0x08004E32:  2232         MOVS       R2, #50
+  0x08004E34:  600A         STR        R2, [R1]
+  0x08004E36:  2120         MOVS       R1, #32
+  0x08004E38:  6029         STR        R1, [R5]
+  0x08004E3A:  49A8         LDR        R1, =onTimeGN            ; [PC, #0x02A0] [0x080050DC] =0x20000740 
+  0x08004E3C:  700F         STRB       R7, [R1]
+  0x08004E3E:  49A8         LDR        R1, =onTimeCounter       ; [PC, #0x02A0] [0x080050E0] =0x200006A8 
+  0x08004E40:  22C8         MOVS       R2, #200
+  0x08004E42:  600A         STR        R2, [R1]
+  0x08004E44:  49A7         LDR        R1, =offTimeGN           ; [PC, #0x029C] [0x080050E4] =0x2000074C 
+  0x08004E46:  700F         STRB       R7, [R1]
+  0x08004E48:  49A7         LDR        R1, =blinkModeGN         ; [PC, #0x029C] [0x080050E8] =0x20000758 
+  0x08004E4A:  700F         STRB       R7, [R1]
+  0x08004E4C:  03B9         LSLS       R1, R7, #14
+  0x08004E4E:  461D         MOV        R5, R3
+  0x08004E50:  4BA6         LDR        R3, =0x50000818          ; [PC, #0x0298] [0x080050EC] 
+  0x08004E52:  6019         STR        R1, [R3]
+  0x08004E54:  49A6         LDR        R1, =onTimeCounterGN     ; [PC, #0x0298] [0x080050F0] =0x200006A4 
+  0x08004E56:  600A         STR        R2, [R1]
+  0x08004E58:  03F9         LSLS       R1, R7, #15
+  0x08004E5A:  6119         STR        R1, [R3, #16]
+  0x08004E5C:  49A5         LDR        R1, =offTimeCounterRT    ; [PC, #0x0294] [0x080050F4] =0x200006B0 
+  0x08004E5E:  6008         STR        R0, [R1]
+  0x08004E60:  49A5         LDR        R1, =blinkModeRT         ; [PC, #0x0294] [0x080050F8] =0x20000754 
+  0x08004E62:  7008         STRB       R0, [R1]
+  0x08004E64:  49A5         LDR        R1, =onTimeCounterRT     ; [PC, #0x0294] [0x080050FC] =0x2000069C 
+  0x08004E66:  6008         STR        R0, [R1]
+  0x08004E68:  48A5         LDR        R0, =0x08006549          ; [PC, #0x0294] [0x08005100] 
+  0x08004E6A:  F000 F9C1    BL         puts                     ; 0x080051F0
+  0x08004E6E:  702F         STRB       R7, [R5]
+
.L8:
+  0x08004E70:  6830         LDR        R0, [R6]
+  0x08004E72:  2801         CMP        R0, #1
+  0x08004E74:  D000         BEQ        .L9                      ; 0x08004E78
+  0x08004E76:  E120         B          .L24                     ; 0x080050BA
+
.L9:
+  0x08004E78:  48A2         LDR        R0, =uwTick              ; [PC, #0x0288] [0x08005104] =0x2000068C 
+  0x08004E7A:  6802         LDR        R2, [R0]
+  0x08004E7C:  49A2         LDR        R1, =SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182 ; [PC, #0x0288] [0x08005108] =0x20000710 
+  0x08004E7E:  680B         LDR        R3, [R1]
+  0x08004E80:  4293         CMP        R3, R2
+  0x08004E82:  D102         BNE        .L10                     ; 0x08004E8A
+  0x08004E84:  4892         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0248] [0x080050D0] =0x20000708 
+  0x08004E86:  6800         LDR        R0, [R0]
+  0x08004E88:  E005         B          .L11                     ; 0x08004E96
+
.L10:
+  0x08004E8A:  6800         LDR        R0, [R0]
+  0x08004E8C:  6008         STR        R0, [R1]
+  0x08004E8E:  4990         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0240] [0x080050D0] =0x20000708 
+  0x08004E90:  6808         LDR        R0, [R1]
+  0x08004E92:  1C40         ADDS       R0, R0, #1
+  0x08004E94:  6008         STR        R0, [R1]
+
.L11:
+  0x08004E96:  499D         LDR        R1, =0x0036EE81          ; [PC, #0x0274] [0x0800510C] 
+  0x08004E98:  4288         CMP        R0, R1
+  0x08004E9A:  D200         BCS        .L12                     ; 0x08004E9E
+  0x08004E9C:  E10D         B          .L24                     ; 0x080050BA
+
.L12:
+  0x08004E9E:  488C         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0230] [0x080050D0] =0x20000708 
+  0x08004EA0:  2100         MOVS       R1, #0
+  0x08004EA2:  6001         STR        R1, [R0]
+  0x08004EA4:  2001         MOVS       R0, #1
+  0x08004EA6:  7020         STRB       R0, [R4]
+  0x08004EA8:  E107         B          .L24                     ; 0x080050BA
+
.L13:
+  0x08004EAA:  2010         MOVS       R0, #16
+  0x08004EAC:  6128         STR        R0, [R5, #16]
+  0x08004EAE:  2008         MOVS       R0, #8
+  0x08004EB0:  6028         STR        R0, [R5]
+  0x08004EB2:  4888         LDR        R0, =relaisState         ; [PC, #0x0220] [0x080050D4] =0x20000730 
+  0x08004EB4:  7001         STRB       R1, [R0]
+  0x08004EB6:  4888         LDR        R0, =onTimeCounterSET    ; [PC, #0x0220] [0x080050D8] =0x20000698 
+  0x08004EB8:  2232         MOVS       R2, #50
+  0x08004EBA:  6002         STR        R2, [R0]
+  0x08004EBC:  2020         MOVS       R0, #32
+  0x08004EBE:  6028         STR        R0, [R5]
+  0x08004EC0:  4886         LDR        R0, =onTimeGN            ; [PC, #0x0218] [0x080050DC] =0x20000740 
+  0x08004EC2:  7001         STRB       R1, [R0]
+  0x08004EC4:  4886         LDR        R0, =onTimeCounter       ; [PC, #0x0218] [0x080050E0] =0x200006A8 
+  0x08004EC6:  22C8         MOVS       R2, #200
+  0x08004EC8:  6002         STR        R2, [R0]
+  0x08004ECA:  4886         LDR        R0, =offTimeGN           ; [PC, #0x0218] [0x080050E4] =0x2000074C 
+  0x08004ECC:  7001         STRB       R1, [R0]
+  0x08004ECE:  038A         LSLS       R2, R1, #14
+  0x08004ED0:  488B         LDR        R0, =0x08006549          ; [PC, #0x022C] [0x08005100] 
+  0x08004ED2:  4B87         LDR        R3, =onTimeCounterGN     ; [PC, #0x021C] [0x080050F0] =0x200006A4 
+  0x08004ED4:  4D84         LDR        R5, =blinkModeGN         ; [PC, #0x0210] [0x080050E8] =0x20000758 
+  0x08004ED6:  460C         MOV        R4, R1
+
.L14:
+  0x08004ED8:  7029         STRB       R1, [R5]
+  0x08004EDA:  4984         LDR        R1, =0x50000818          ; [PC, #0x0210] [0x080050EC] 
+  0x08004EDC:  600A         STR        R2, [R1]
+  0x08004EDE:  21C8         MOVS       R1, #200
+  0x08004EE0:  6019         STR        R1, [R3]
+  0x08004EE2:  F000 F985    BL         puts                     ; 0x080051F0
+  0x08004EE6:  4878         LDR        R0, =smState.171         ; [PC, #0x01E0] [0x080050C8] =0x20000731 
+  0x08004EE8:  7004         STRB       R4, [R0]
+  0x08004EEA:  E0E6         B          .L24                     ; 0x080050BA
+
.L15:
+  0x08004EEC:  4889         LDR        R0, =SECONDARYPROTECTION_SM_On.oldtime.175 ; [PC, #0x0224] [0x08005114] =0x200006F8 
+  0x08004EEE:  6802         LDR        R2, [R0]
+  0x08004EF0:  4984         LDR        R1, =uwTick              ; [PC, #0x0210] [0x08005104] =0x2000068C 
+  0x08004EF2:  680B         LDR        R3, [R1]
+  0x08004EF4:  4293         CMP        R3, R2
+  0x08004EF6:  D00D         BEQ        .L17                     ; 0x08004F14
+  0x08004EF8:  6809         LDR        R1, [R1]
+  0x08004EFA:  6001         STR        R1, [R0]
+  0x08004EFC:  4986         LDR        R1, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 ; [PC, #0x0218] [0x08005118] =0x20000700 
+  0x08004EFE:  680B         LDR        R3, [R1]
+  0x08004F00:  1C5A         ADDS       R2, R3, #1
+  0x08004F02:  2000         MOVS       R0, #0
+  0x08004F04:  4C85         LDR        R4, =0x0000752F          ; [PC, #0x0214] [0x0800511C] 
+  0x08004F06:  42A3         CMP        R3, R4
+  0x08004F08:  4603         MOV        R3, R0
+  0x08004F0A:  DC00         BGT        .L16                     ; 0x08004F0E
+  0x08004F0C:  4613         MOV        R3, R2
+
.L16:
+  0x08004F0E:  600B         STR        R3, [R1]
+  0x08004F10:  463C         MOV        R4, R7
+  0x08004F12:  DC00         BGT        .L18                     ; 0x08004F16
+
.L17:
+  0x08004F14:  2400         MOVS       R4, #0
+
.L18:
+  0x08004F16:  9B03         LDR        R3, [SP, #12]
+  0x08004F18:  9A02         LDR        R2, [SP, #8]
+
.L19:
+  0x08004F1A:  9901         LDR        R1, [SP, #4]
+  0x08004F1C:  486B         LDR        R0, =buttonState         ; [PC, #0x01AC] [0x080050CC] =0x2000073A 
+  0x08004F1E:  7800         LDRB       R0, [R0]
+  0x08004F20:  2800         CMP        R0, #0
+  0x08004F22:  9400         STR        R4, [SP, #0]
+  0x08004F24:  D125         BNE        .L20                     ; 0x08004F72
+  0x08004F26:  2008         MOVS       R0, #8
+  0x08004F28:  6128         STR        R0, [R5, #16]
+  0x08004F2A:  2010         MOVS       R0, #16
+  0x08004F2C:  6028         STR        R0, [R5]
+  0x08004F2E:  4869         LDR        R0, =relaisState         ; [PC, #0x01A4] [0x080050D4] =0x20000730 
+  0x08004F30:  2400         MOVS       R4, #0
+  0x08004F32:  7004         STRB       R4, [R0]
+  0x08004F34:  487A         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01E8] [0x08005120] =0x200006A0 
+  0x08004F36:  2132         MOVS       R1, #50
+  0x08004F38:  6001         STR        R1, [R0]
+  0x08004F3A:  2020         MOVS       R0, #32
+  0x08004F3C:  6028         STR        R0, [R5]
+  0x08004F3E:  4868         LDR        R0, =onTimeCounter       ; [PC, #0x01A0] [0x080050E0] =0x200006A8 
+  0x08004F40:  21C8         MOVS       R1, #200
+  0x08004F42:  6001         STR        R1, [R0]
+  0x08004F44:  9804         LDR        R0, [SP, #16]
+  0x08004F46:  6130         STR        R0, [R6, #16]
+  0x08004F48:  4876         LDR        R0, =offTimeCounterGN    ; [PC, #0x01D8] [0x08005124] =0x200006B4 
+  0x08004F4A:  6004         STR        R4, [R0]
+  0x08004F4C:  4866         LDR        R0, =blinkModeGN         ; [PC, #0x0198] [0x080050E8] =0x20000758 
+  0x08004F4E:  7004         STRB       R4, [R0]
+  0x08004F50:  4867         LDR        R0, =onTimeCounterGN     ; [PC, #0x019C] [0x080050F0] =0x200006A4 
+  0x08004F52:  6004         STR        R4, [R0]
+  0x08004F54:  6133         STR        R3, [R6, #16]
+  0x08004F56:  4867         LDR        R0, =offTimeCounterRT    ; [PC, #0x019C] [0x080050F4] =0x200006B0 
+  0x08004F58:  6004         STR        R4, [R0]
+  0x08004F5A:  4867         LDR        R0, =blinkModeRT         ; [PC, #0x019C] [0x080050F8] =0x20000754 
+  0x08004F5C:  7004         STRB       R4, [R0]
+  0x08004F5E:  4867         LDR        R0, =onTimeCounterRT     ; [PC, #0x019C] [0x080050FC] =0x2000069C 
+  0x08004F60:  6004         STR        R4, [R0]
+  0x08004F62:  4871         LDR        R0, =0x08006309          ; [PC, #0x01C4] [0x08005128] 
+  0x08004F64:  F000 F944    BL         puts                     ; 0x080051F0
+  0x08004F68:  A901         ADD        R1, SP, #4
+  0x08004F6A:  C90E         LDM        R1, {R1-R3}
+  0x08004F6C:  4856         LDR        R0, =smState.171         ; [PC, #0x0158] [0x080050C8] =0x20000731 
+  0x08004F6E:  7004         STRB       R4, [R0]
+  0x08004F70:  9C00         LDR        R4, [SP, #0]
+
.L20:
+  0x08004F72:  00C8         LSLS       R0, R1, #3
+  0x08004F74:  496D         LDR        R1, =dropLimitCounter    ; [PC, #0x01B4] [0x0800512C] =0x200006E4 
+  0x08004F76:  6809         LDR        R1, [R1]
+  0x08004F78:  4281         CMP        R1, R0
+  0x08004F7A:  D135         BNE        .L21                     ; 0x08004FE8
+  0x08004F7C:  2008         MOVS       R0, #8
+  0x08004F7E:  6128         STR        R0, [R5, #16]
+  0x08004F80:  2010         MOVS       R0, #16
+  0x08004F82:  6028         STR        R0, [R5]
+  0x08004F84:  4853         LDR        R0, =relaisState         ; [PC, #0x014C] [0x080050D4] =0x20000730 
+  0x08004F86:  2400         MOVS       R4, #0
+  0x08004F88:  7004         STRB       R4, [R0]
+  0x08004F8A:  4865         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0194] [0x08005120] =0x200006A0 
+  0x08004F8C:  2132         MOVS       R1, #50
+  0x08004F8E:  6001         STR        R1, [R0]
+  0x08004F90:  2020         MOVS       R0, #32
+  0x08004F92:  6028         STR        R0, [R5]
+  0x08004F94:  4852         LDR        R0, =onTimeCounter       ; [PC, #0x0148] [0x080050E0] =0x200006A8 
+  0x08004F96:  6002         STR        R2, [R0]
+  0x08004F98:  9804         LDR        R0, [SP, #16]
+  0x08004F9A:  6130         STR        R0, [R6, #16]
+  0x08004F9C:  4861         LDR        R0, =offTimeCounterGN    ; [PC, #0x0184] [0x08005124] =0x200006B4 
+  0x08004F9E:  6004         STR        R4, [R0]
+  0x08004FA0:  4851         LDR        R0, =blinkModeGN         ; [PC, #0x0144] [0x080050E8] =0x20000758 
+  0x08004FA2:  7004         STRB       R4, [R0]
+  0x08004FA4:  4852         LDR        R0, =onTimeCounterGN     ; [PC, #0x0148] [0x080050F0] =0x200006A4 
+  0x08004FA6:  6004         STR        R4, [R0]
+  0x08004FA8:  4861         LDR        R0, =onTimeRT            ; [PC, #0x0184] [0x08005130] =0x2000073C 
+  0x08004FAA:  7007         STRB       R7, [R0]
+  0x08004FAC:  4861         LDR        R0, =offTimeRT           ; [PC, #0x0184] [0x08005134] =0x20000748 
+  0x08004FAE:  7007         STRB       R7, [R0]
+  0x08004FB0:  4851         LDR        R0, =blinkModeRT         ; [PC, #0x0144] [0x080050F8] =0x20000754 
+  0x08004FB2:  7007         STRB       R7, [R0]
+  0x08004FB4:  4860         LDR        R0, =numberOfBlinks      ; [PC, #0x0180] [0x08005138] =0x200006BC 
+  0x08004FB6:  2104         MOVS       R1, #4
+  0x08004FB8:  6001         STR        R1, [R0]
+  0x08004FBA:  4860         LDR        R0, =blinkCounter        ; [PC, #0x0180] [0x0800513C] =0x200006EC 
+  0x08004FBC:  6001         STR        R1, [R0]
+  0x08004FBE:  4860         LDR        R0, =pauseTime           ; [PC, #0x0180] [0x08005140] =0x20000734 
+  0x08004FC0:  7007         STRB       R7, [R0]
+  0x08004FC2:  6033         STR        R3, [R6]
+  0x08004FC4:  4841         LDR        R0, =buttonState         ; [PC, #0x0104] [0x080050CC] =0x2000073A 
+  0x08004FC6:  7004         STRB       R4, [R0]
+  0x08004FC8:  484C         LDR        R0, =onTimeCounterRT     ; [PC, #0x0130] [0x080050FC] =0x2000069C 
+  0x08004FCA:  21C8         MOVS       R1, #200
+  0x08004FCC:  6001         STR        R1, [R0]
+  0x08004FCE:  485D         LDR        R0, =0x0800678C          ; [PC, #0x0174] [0x08005144] 
+  0x08004FD0:  F000 F90E    BL         puts                     ; 0x080051F0
+  0x08004FD4:  485C         LDR        R0, =0x080067A9          ; [PC, #0x0170] [0x08005148] 
+  0x08004FD6:  F000 F90B    BL         puts                     ; 0x080051F0
+  0x08004FDA:  9B03         LDR        R3, [SP, #12]
+  0x08004FDC:  2002         MOVS       R0, #2
+  0x08004FDE:  493A         LDR        R1, =smState.171         ; [PC, #232] [0x080050C8] =0x20000731 
+  0x08004FE0:  7008         STRB       R0, [R1]
+  0x08004FE2:  4852         LDR        R0, =dropLimitCounter    ; [PC, #0x0148] [0x0800512C] =0x200006E4 
+  0x08004FE4:  6004         STR        R4, [R0]
+  0x08004FE6:  9C00         LDR        R4, [SP, #0]
+
.L21:
+  0x08004FE8:  2C00         CMP        R4, #0
+  0x08004FEA:  D032         BEQ        .L22                     ; 0x08005052
+  0x08004FEC:  2008         MOVS       R0, #8
+  0x08004FEE:  6128         STR        R0, [R5, #16]
+  0x08004FF0:  2010         MOVS       R0, #16
+  0x08004FF2:  6028         STR        R0, [R5]
+  0x08004FF4:  4937         LDR        R1, =relaisState         ; [PC, #220] [0x080050D4] =0x20000730 
+  0x08004FF6:  2000         MOVS       R0, #0
+  0x08004FF8:  7008         STRB       R0, [R1]
+  0x08004FFA:  4949         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0124] [0x08005120] =0x200006A0 
+  0x08004FFC:  2232         MOVS       R2, #50
+  0x08004FFE:  600A         STR        R2, [R1]
+  0x08005000:  2120         MOVS       R1, #32
+  0x08005002:  6029         STR        R1, [R5]
+  0x08005004:  4936         LDR        R1, =onTimeCounter       ; [PC, #216] [0x080050E0] =0x200006A8 
+  0x08005006:  9A02         LDR        R2, [SP, #8]
+  0x08005008:  600A         STR        R2, [R1]
+  0x0800500A:  9904         LDR        R1, [SP, #16]
+  0x0800500C:  6131         STR        R1, [R6, #16]
+  0x0800500E:  4945         LDR        R1, =offTimeCounterGN    ; [PC, #0x0114] [0x08005124] =0x200006B4 
+  0x08005010:  6008         STR        R0, [R1]
+  0x08005012:  4935         LDR        R1, =blinkModeGN         ; [PC, #212] [0x080050E8] =0x20000758 
+  0x08005014:  7008         STRB       R0, [R1]
+  0x08005016:  4936         LDR        R1, =onTimeCounterGN     ; [PC, #216] [0x080050F0] =0x200006A4 
+  0x08005018:  6008         STR        R0, [R1]
+  0x0800501A:  4945         LDR        R1, =onTimeRT            ; [PC, #0x0114] [0x08005130] =0x2000073C 
+  0x0800501C:  700F         STRB       R7, [R1]
+  0x0800501E:  4945         LDR        R1, =offTimeRT           ; [PC, #0x0114] [0x08005134] =0x20000748 
+  0x08005020:  700F         STRB       R7, [R1]
+  0x08005022:  4935         LDR        R1, =blinkModeRT         ; [PC, #212] [0x080050F8] =0x20000754 
+  0x08005024:  700F         STRB       R7, [R1]
+  0x08005026:  4944         LDR        R1, =numberOfBlinks      ; [PC, #0x0110] [0x08005138] =0x200006BC 
+  0x08005028:  2402         MOVS       R4, #2
+  0x0800502A:  600C         STR        R4, [R1]
+  0x0800502C:  4943         LDR        R1, =blinkCounter        ; [PC, #0x010C] [0x0800513C] =0x200006EC 
+  0x0800502E:  600C         STR        R4, [R1]
+  0x08005030:  4943         LDR        R1, =pauseTime           ; [PC, #0x010C] [0x08005140] =0x20000734 
+  0x08005032:  700F         STRB       R7, [R1]
+  0x08005034:  6033         STR        R3, [R6]
+  0x08005036:  4925         LDR        R1, =buttonState         ; [PC, #148] [0x080050CC] =0x2000073A 
+  0x08005038:  7008         STRB       R0, [R1]
+  0x0800503A:  4830         LDR        R0, =onTimeCounterRT     ; [PC, #192] [0x080050FC] =0x2000069C 
+  0x0800503C:  21C8         MOVS       R1, #200
+  0x0800503E:  6001         STR        R1, [R0]
+  0x08005040:  4842         LDR        R0, =0x08006950          ; [PC, #0x0108] [0x0800514C] 
+  0x08005042:  F000 F8D5    BL         puts                     ; 0x080051F0
+  0x08005046:  4840         LDR        R0, =0x080067A9          ; [PC, #0x0100] [0x08005148] 
+  0x08005048:  F000 F8D2    BL         puts                     ; 0x080051F0
+  0x0800504C:  9B03         LDR        R3, [SP, #12]
+  0x0800504E:  481E         LDR        R0, =smState.171         ; [PC, #120] [0x080050C8] =0x20000731 
+  0x08005050:  7004         STRB       R4, [R0]
+
.L22:
+  0x08005052:  483F         LDR        R0, =temp                ; [PC, #252] [0x08005150] =0x20000690 
+  0x08005054:  6800         LDR        R0, [R0]
+  0x08005056:  2851         CMP        R0, #81
+  0x08005058:  9C04         LDR        R4, [SP, #16]
+  0x0800505A:  DB2E         BLT        .L24                     ; 0x080050BA
+  0x0800505C:  2008         MOVS       R0, #8
+  0x0800505E:  6128         STR        R0, [R5, #16]
+  0x08005060:  2010         MOVS       R0, #16
+  0x08005062:  6028         STR        R0, [R5]
+  0x08005064:  491B         LDR        R1, =relaisState         ; [PC, #108] [0x080050D4] =0x20000730 
+  0x08005066:  2000         MOVS       R0, #0
+  0x08005068:  7008         STRB       R0, [R1]
+  0x0800506A:  492D         LDR        R1, =onTimeCounterRESET  ; [PC, #180] [0x08005120] =0x200006A0 
+  0x0800506C:  2232         MOVS       R2, #50
+  0x0800506E:  600A         STR        R2, [R1]
+  0x08005070:  2120         MOVS       R1, #32
+  0x08005072:  6029         STR        R1, [R5]
+  0x08005074:  491A         LDR        R1, =onTimeCounter       ; [PC, #104] [0x080050E0] =0x200006A8 
+  0x08005076:  9A02         LDR        R2, [SP, #8]
+  0x08005078:  600A         STR        R2, [R1]
+  0x0800507A:  6134         STR        R4, [R6, #16]
+  0x0800507C:  4929         LDR        R1, =offTimeCounterGN    ; [PC, #164] [0x08005124] =0x200006B4 
+  0x0800507E:  6008         STR        R0, [R1]
+  0x08005080:  4919         LDR        R1, =blinkModeGN         ; [PC, #100] [0x080050E8] =0x20000758 
+  0x08005082:  7008         STRB       R0, [R1]
+  0x08005084:  491A         LDR        R1, =onTimeCounterGN     ; [PC, #104] [0x080050F0] =0x200006A4 
+  0x08005086:  6008         STR        R0, [R1]
+  0x08005088:  4929         LDR        R1, =onTimeRT            ; [PC, #164] [0x08005130] =0x2000073C 
+  0x0800508A:  700F         STRB       R7, [R1]
+  0x0800508C:  4929         LDR        R1, =offTimeRT           ; [PC, #164] [0x08005134] =0x20000748 
+  0x0800508E:  700F         STRB       R7, [R1]
+  0x08005090:  4919         LDR        R1, =blinkModeRT         ; [PC, #100] [0x080050F8] =0x20000754 
+  0x08005092:  700F         STRB       R7, [R1]
+  0x08005094:  4928         LDR        R1, =numberOfBlinks      ; [PC, #160] [0x08005138] =0x200006BC 
+  0x08005096:  2205         MOVS       R2, #5
+  0x08005098:  600A         STR        R2, [R1]
+  0x0800509A:  4928         LDR        R1, =blinkCounter        ; [PC, #160] [0x0800513C] =0x200006EC 
+  0x0800509C:  600A         STR        R2, [R1]
+  0x0800509E:  4928         LDR        R1, =pauseTime           ; [PC, #160] [0x08005140] =0x20000734 
+  0x080050A0:  700F         STRB       R7, [R1]
+  0x080050A2:  6033         STR        R3, [R6]
+  0x080050A4:  4909         LDR        R1, =buttonState         ; [PC, #36] [0x080050CC] =0x2000073A 
+  0x080050A6:  7008         STRB       R0, [R1]
+  0x080050A8:  4814         LDR        R0, =onTimeCounterRT     ; [PC, #80] [0x080050FC] =0x2000069C 
+  0x080050AA:  21C8         MOVS       R1, #200
+  0x080050AC:  6001         STR        R1, [R0]
+  0x080050AE:  4829         LDR        R0, =0x0800632C          ; [PC, #164] [0x08005154] 
+
.L23:
+  0x080050B0:  F000 F89E    BL         puts                     ; 0x080051F0
+  0x080050B4:  2002         MOVS       R0, #2
+  0x080050B6:  4904         LDR        R1, =smState.171         ; [PC, #16] [0x080050C8] =0x20000731 
+  0x080050B8:  7008         STRB       R0, [R1]
+
.L24:
+  0x080050BA:  B005         ADD        SP, SP, #20
+  0x080050BC:  BDF0         POP        {R4-R7, PC}
+  0x080050BE:  46C0         NOP
+  0x080050C0:  200006F0     DC.W       autoRetryMode.170
+  0x080050C4:  50000418     DC.W       0x50000418
+  0x080050C8:  20000731     DC.W       smState.171
+  0x080050CC:  2000073A     DC.W       buttonState
+  0x080050D0:  20000708     DC.W       SECONDARYPROTECTION_SM_Error.retry_counter.181
+  0x080050D4:  20000730     DC.W       relaisState
+  0x080050D8:  20000698     DC.W       onTimeCounterSET
+  0x080050DC:  20000740     DC.W       onTimeGN
+  0x080050E0:  200006A8     DC.W       onTimeCounter
+  0x080050E4:  2000074C     DC.W       offTimeGN
+  0x080050E8:  20000758     DC.W       blinkModeGN
+  0x080050EC:  50000818     DC.W       0x50000818
+  0x080050F0:  200006A4     DC.W       onTimeCounterGN
+  0x080050F4:  200006B0     DC.W       offTimeCounterRT
+  0x080050F8:  20000754     DC.W       blinkModeRT
+  0x080050FC:  2000069C     DC.W       onTimeCounterRT
+  0x08005100:  08006549     DC.W       08006549               ; R_ARM_ABS32
+  0x08005104:  2000068C     DC.W       uwTick
+  0x08005108:  20000710     DC.W       SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182
+  0x0800510C:  0036EE81     DC.W       0x0036EE81
+  0x08005110:  50000010     DC.W       0x50000010
+  0x08005114:  200006F8     DC.W       SECONDARYPROTECTION_SM_On.oldtime.175
+  0x08005118:  20000700     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176
+  0x0800511C:  0000752F     DC.W       0x0000752F
+  0x08005120:  200006A0     DC.W       onTimeCounterRESET
+  0x08005124:  200006B4     DC.W       offTimeCounterGN
+  0x08005128:  08006309     DC.W       08006309               ; R_ARM_ABS32
+  0x0800512C:  200006E4     DC.W       dropLimitCounter
+  0x08005130:  2000073C     DC.W       onTimeRT
+  0x08005134:  20000748     DC.W       offTimeRT
+  0x08005138:  200006BC     DC.W       numberOfBlinks
+  0x0800513C:  200006EC     DC.W       blinkCounter
+  0x08005140:  20000734     DC.W       pauseTime
+  0x08005144:  0800678C     DC.W       0800678C               ; R_ARM_ABS32
+  0x08005148:  080067A9     DC.W       080067A9               ; R_ARM_ABS32
+  0x0800514C:  08006950     DC.W       08006950               ; R_ARM_ABS32
+  0x08005150:  20000690     DC.W       temp
+  0x08005154:  0800632C     DC.W       0800632C               ; R_ARM_ABS32
+  0x08005158:  0800698C     DC.W       0800698C               ; R_ARM_ABS32
+
+

Section .rodata.AHBPrescTable from PowerPro_lto.o, size=64, align=4

+
+
AHBPrescTable:
+  0x0800515C:  00           DC.B       0x00                     ; '\0'
+  0x0800515D:  00           DC.B       0x00                     ; '\0'
+  0x0800515E:  00           DC.B       0x00                     ; '\0'
+  0x0800515F:  00           DC.B       0x00                     ; '\0'
+  0x08005160:  00           DC.B       0x00                     ; '\0'
+  0x08005161:  00           DC.B       0x00                     ; '\0'
+  0x08005162:  00           DC.B       0x00                     ; '\0'
+  0x08005163:  00           DC.B       0x00                     ; '\0'
+  0x08005164:  00           DC.B       0x00                     ; '\0'
+  0x08005165:  00           DC.B       0x00                     ; '\0'
+  0x08005166:  00           DC.B       0x00                     ; '\0'
+  0x08005167:  00           DC.B       0x00                     ; '\0'
+  0x08005168:  00           DC.B       0x00                     ; '\0'
+  0x08005169:  00           DC.B       0x00                     ; '\0'
+  0x0800516A:  00           DC.B       0x00                     ; '\0'
+  0x0800516B:  00           DC.B       0x00                     ; '\0'
+  0x0800516C:  00           DC.B       0x00                     ; '\0'
+  0x0800516D:  00           DC.B       0x00                     ; '\0'
+  0x0800516E:  00           DC.B       0x00                     ; '\0'
+  0x0800516F:  00           DC.B       0x00                     ; '\0'
+  0x08005170:  00           DC.B       0x00                     ; '\0'
+  0x08005171:  00           DC.B       0x00                     ; '\0'
+  0x08005172:  00           DC.B       0x00                     ; '\0'
+  0x08005173:  00           DC.B       0x00                     ; '\0'
+  0x08005174:  00           DC.B       0x00                     ; '\0'
+  0x08005175:  00           DC.B       0x00                     ; '\0'
+  0x08005176:  00           DC.B       0x00                     ; '\0'
+  0x08005177:  00           DC.B       0x00                     ; '\0'
+  0x08005178:  00           DC.B       0x00                     ; '\0'
+  0x08005179:  00           DC.B       0x00                     ; '\0'
+  0x0800517A:  00           DC.B       0x00                     ; '\0'
+  0x0800517B:  00           DC.B       0x00                     ; '\0'
+  0x0800517C:  01           DC.B       0x01                     ; '\x01'
+  0x0800517D:  00           DC.B       0x00                     ; '\0'
+  0x0800517E:  00           DC.B       0x00                     ; '\0'
+  0x0800517F:  00           DC.B       0x00                     ; '\0'
+  0x08005180:  02           DC.B       0x02                     ; '\x02'
+  0x08005181:  00           DC.B       0x00                     ; '\0'
+  0x08005182:  00           DC.B       0x00                     ; '\0'
+  0x08005183:  00           DC.B       0x00                     ; '\0'
+  0x08005184:  03           DC.B       0x03                     ; '\x03'
+  0x08005185:  00           DC.B       0x00                     ; '\0'
+  0x08005186:  00           DC.B       0x00                     ; '\0'
+  0x08005187:  00           DC.B       0x00                     ; '\0'
+  0x08005188:  04           DC.B       0x04                     ; '\x04'
+  0x08005189:  00           DC.B       0x00                     ; '\0'
+  0x0800518A:  00           DC.B       0x00                     ; '\0'
+  0x0800518B:  00           DC.B       0x00                     ; '\0'
+  0x0800518C:  06           DC.B       0x06                     ; '\x06'
+  0x0800518D:  00           DC.B       0x00                     ; '\0'
+  0x0800518E:  00           DC.B       0x00                     ; '\0'
+  0x0800518F:  00           DC.B       0x00                     ; '\0'
+  0x08005190:  07           DC.B       0x07                     ; '\x07'
+  0x08005191:  00           DC.B       0x00                     ; '\0'
+  0x08005192:  00           DC.B       0x00                     ; '\0'
+  0x08005193:  00           DC.B       0x00                     ; '\0'
+  0x08005194:  08           DC.B       0x08                     ; '\b'
+  0x08005195:  00           DC.B       0x00                     ; '\0'
+  0x08005196:  00           DC.B       0x00                     ; '\0'
+  0x08005197:  00           DC.B       0x00                     ; '\0'
+  0x08005198:  09           DC.B       0x09                     ; '\t'
+  0x08005199:  00           DC.B       0x00                     ; '\0'
+  0x0800519A:  00           DC.B       0x00                     ; '\0'
+  0x0800519B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.APBPrescTable from PowerPro_lto.o, size=32, align=4

+
+
APBPrescTable:
+  0x0800519C:  00           DC.B       0x00                     ; '\0'
+  0x0800519D:  00           DC.B       0x00                     ; '\0'
+  0x0800519E:  00           DC.B       0x00                     ; '\0'
+  0x0800519F:  00           DC.B       0x00                     ; '\0'
+  0x080051A0:  00           DC.B       0x00                     ; '\0'
+  0x080051A1:  00           DC.B       0x00                     ; '\0'
+  0x080051A2:  00           DC.B       0x00                     ; '\0'
+  0x080051A3:  00           DC.B       0x00                     ; '\0'
+  0x080051A4:  00           DC.B       0x00                     ; '\0'
+  0x080051A5:  00           DC.B       0x00                     ; '\0'
+  0x080051A6:  00           DC.B       0x00                     ; '\0'
+  0x080051A7:  00           DC.B       0x00                     ; '\0'
+  0x080051A8:  00           DC.B       0x00                     ; '\0'
+  0x080051A9:  00           DC.B       0x00                     ; '\0'
+  0x080051AA:  00           DC.B       0x00                     ; '\0'
+  0x080051AB:  00           DC.B       0x00                     ; '\0'
+  0x080051AC:  01           DC.B       0x01                     ; '\x01'
+  0x080051AD:  00           DC.B       0x00                     ; '\0'
+  0x080051AE:  00           DC.B       0x00                     ; '\0'
+  0x080051AF:  00           DC.B       0x00                     ; '\0'
+  0x080051B0:  02           DC.B       0x02                     ; '\x02'
+  0x080051B1:  00           DC.B       0x00                     ; '\0'
+  0x080051B2:  00           DC.B       0x00                     ; '\0'
+  0x080051B3:  00           DC.B       0x00                     ; '\0'
+  0x080051B4:  03           DC.B       0x03                     ; '\x03'
+  0x080051B5:  00           DC.B       0x00                     ; '\0'
+  0x080051B6:  00           DC.B       0x00                     ; '\0'
+  0x080051B7:  00           DC.B       0x00                     ; '\0'
+  0x080051B8:  04           DC.B       0x04                     ; '\x04'
+  0x080051B9:  00           DC.B       0x00                     ; '\0'
+  0x080051BA:  00           DC.B       0x00                     ; '\0'
+  0x080051BB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lswitch.table.UART_SetConfig from PowerPro_lto.o, size=16, align=4

+
+  0x080051BC:  00           DC.B       0x00                     ; '\0'
+  0x080051BD:  00           DC.B       0x00                     ; '\0'
+  0x080051BE:  00           DC.B       0x00                     ; '\0'
+  0x080051BF:  00           DC.B       0x00                     ; '\0'
+  0x080051C0:  04           DC.B       0x04                     ; '\x04'
+  0x080051C1:  00           DC.B       0x00                     ; '\0'
+  0x080051C2:  00           DC.B       0x00                     ; '\0'
+  0x080051C3:  00           DC.B       0x00                     ; '\0'
+  0x080051C4:  02           DC.B       0x02                     ; '\x02'
+  0x080051C5:  00           DC.B       0x00                     ; '\0'
+  0x080051C6:  00           DC.B       0x00                     ; '\0'
+  0x080051C7:  00           DC.B       0x00                     ; '\0'
+  0x080051C8:  08           DC.B       0x08                     ; '\b'
+  0x080051C9:  00           DC.B       0x00                     ; '\0'
+  0x080051CA:  00           DC.B       0x00                     ; '\0'
+  0x080051CB:  00           DC.B       0x00                     ; '\0'
+
+

Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

+
+
_start:
+  0x080051CC:  4C03         LDR        R4, =0x08006A6C          ; [PC, #12] [0x080051DC] 
+
.L1:
+  0x080051CE:  6820         LDR        R0, [R4]
+  0x080051D0:  3404         ADDS       R4, #4
+  0x080051D2:  4780         BLX        R0
+  0x080051D4:  E7FB         B          .L1                      ; 0x080051CE
+
__SEGGER_init_done:
+__startup_complete:
+  0x080051D6:  F7FC FB35    BL         main                     ; 0x08001844
+
exit:
+  0x080051DA:  E7FE         B          exit                     ; 0x080051DA
+  0x080051DC:  08006A6C     DC.W       08006A6C               ; R_ARM_ABS32
+
+

Section .text.libc.putchar from fileops.o (libc_v6m_t_le_eabi_small.a), size=16, align=4

+
+
putchar:
+  0x080051E0:  B580         PUSH       {R7, LR}
+  0x080051E2:  4902         LDR        R1, =stdout              ; [PC, #8] [0x080051EC] =0x20000B98 
+  0x080051E4:  6809         LDR        R1, [R1]
+  0x080051E6:  F000 FB69    BL         fputc                    ; 0x080058BC
+  0x080051EA:  BD80         POP        {R7, PC}
+  0x080051EC:  20000B98     DC.W       stdout
+
+

Section .text.libc.puts from fileops.o (libc_v6m_t_le_eabi_small.a), size=44, align=4

+
+
puts:
+  0x080051F0:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080051F2:  4604         MOV        R4, R0
+  0x080051F4:  4808         LDR        R0, =stdout              ; [PC, #32] [0x08005218] =0x20000B98 
+  0x080051F6:  6805         LDR        R5, [R0]
+  0x080051F8:  4620         MOV        R0, R4
+  0x080051FA:  F000 FD95    BL         strlen                   ; 0x08005D28
+  0x080051FE:  4602         MOV        R2, R0
+  0x08005200:  4628         MOV        R0, R5
+  0x08005202:  4621         MOV        R1, R4
+  0x08005204:  F000 FD4C    BL         __SEGGER_RTL_X_file_write ; 0x08005CA0
+  0x08005208:  1C40         ADDS       R0, R0, #1
+  0x0800520A:  D003         BEQ        .L1                      ; 0x08005214
+  0x0800520C:  200A         MOVS       R0, #10
+  0x0800520E:  F7FF FFE7    BL         putchar                  ; 0x080051E0
+  0x08005212:  BDB0         POP        {R4-R5, R7, PC}
+
.L1:
+  0x08005214:  43C0         MVNS       R0, R0
+  0x08005216:  BDB0         POP        {R4-R5, R7, PC}
+  0x08005218:  20000B98     DC.W       stdout
+
+

Section .text.libc.__aeabi_i2d from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__aeabi_i2d:
+  0x0800521C:  4B05         LDR        R3, =__aeabi_ui2d        ; [PC, #20] [0x08005234] =0x08006027 
+  0x0800521E:  4200         TST        R0, R0
+  0x08005220:  D506         BPL        .L1                      ; 0x08005230
+  0x08005222:  4240         RSBS       R0, R0, #0
+  0x08005224:  B500         PUSH       {LR}
+  0x08005226:  4798         BLX        R3
+  0x08005228:  BC08         POP        {R3}
+  0x0800522A:  2201         MOVS       R2, #1
+  0x0800522C:  07D2         LSLS       R2, R2, #31
+  0x0800522E:  4311         ORRS       R1, R2
+
.L1:
+  0x08005230:  4718         BX         R3
+  0x08005232:  0000         NOP
+  0x08005234:  08006027     DC.W       __aeabi_ui2d
+
+

Section .text.libc.vfprintf_l from prinops.o (libc_v6m_t_le_eabi_small.a), size=108, align=4

+
+
vfprintf_l:
+  0x08005238:  B5F0         PUSH       {R4-R7, LR}
+  0x0800523A:  AF03         ADD        R7, SP, #12
+  0x0800523C:  B091         SUB        SP, SP, #68
+  0x0800523E:  466E         MOV        R6, SP
+  0x08005240:  1DF5         ADDS       R5, R6, #7
+  0x08005242:  3519         ADDS       R5, #25
+  0x08005244:  61B3         STR        R3, [R6, #24]
+  0x08005246:  6172         STR        R2, [R6, #20]
+  0x08005248:  6071         STR        R1, [R6, #4]
+  0x0800524A:  60F0         STR        R0, [R6, #12]
+  0x0800524C:  F000 FF81    BL         __SEGGER_RTL_X_file_bufsize ; 0x08006152
+  0x08005250:  60B0         STR        R0, [R6, #8]
+  0x08005252:  1DC2         ADDS       R2, R0, #7
+  0x08005254:  2107         MOVS       R1, #7
+  0x08005256:  438A         BICS       R2, R1
+  0x08005258:  4669         MOV        R1, SP
+  0x0800525A:  6131         STR        R1, [R6, #16]
+  0x0800525C:  4669         MOV        R1, SP
+  0x0800525E:  1A88         SUBS       R0, R1, R2
+  0x08005260:  6030         STR        R0, [R6]
+  0x08005262:  4685         MOV        SP, R0
+  0x08005264:  1DF4         ADDS       R4, R6, #7
+  0x08005266:  3415         ADDS       R4, #21
+  0x08005268:  4620         MOV        R0, R4
+  0x0800526A:  6871         LDR        R1, [R6, #4]
+  0x0800526C:  F000 FD02    BL         __SEGGER_RTL_init_prin_l ; 0x08005C74
+  0x08005270:  480A         LDR        R0, =__SEGGER_RTL_stream_write ; [PC, #40] [0x0800529C] =0x08006143 
+  0x08005272:  63F0         STR        R0, [R6, #60]
+  0x08005274:  480A         LDR        R0, =0x7FFFFFFF          ; [PC, #40] [0x080052A0] 
+  0x08005276:  6028         STR        R0, [R5]
+  0x08005278:  68F0         LDR        R0, [R6, #12]
+  0x0800527A:  6228         STR        R0, [R5, #32]
+  0x0800527C:  68B0         LDR        R0, [R6, #8]
+  0x0800527E:  6168         STR        R0, [R5, #20]
+  0x08005280:  6830         LDR        R0, [R6]
+  0x08005282:  60E8         STR        R0, [R5, #12]
+  0x08005284:  4620         MOV        R0, R4
+  0x08005286:  6971         LDR        R1, [R6, #20]
+  0x08005288:  69B2         LDR        R2, [R6, #24]
+  0x0800528A:  F000 F81F    BL         __SEGGER_RTL_vfprintf_int_nwp ; 0x080052CC
+  0x0800528E:  6931         LDR        R1, [R6, #16]
+  0x08005290:  468D         MOV        SP, R1
+  0x08005292:  1FFE         SUBS       R6, R7, #7
+  0x08005294:  3E05         SUBS       R6, #5
+  0x08005296:  46B5         MOV        SP, R6
+  0x08005298:  BDF0         POP        {R4-R7, PC}
+  0x0800529A:  46C0         NOP
+  0x0800529C:  08006143     DC.W       __SEGGER_RTL_stream_write
+  0x080052A0:  7FFFFFFF     DC.W       0x7FFFFFFF
+
+

Section .text.libc.printf from prinops.o (libc_v6m_t_le_eabi_small.a), size=40, align=4

+
+
printf:
+  0x080052A4:  B083         SUB        SP, SP, #12
+  0x080052A6:  B510         PUSH       {R4, LR}
+  0x080052A8:  B081         SUB        SP, SP, #4
+  0x080052AA:  4604         MOV        R4, R0
+  0x080052AC:  A803         ADD        R0, SP, #12
+  0x080052AE:  C00E         STM        R0!, {R1-R3}
+  0x080052B0:  4805         LDR        R0, =stdout              ; [PC, #20] [0x080052C8] =0x20000B98 
+  0x080052B2:  6800         LDR        R0, [R0]
+  0x080052B4:  AA03         ADD        R2, SP, #12
+  0x080052B6:  9200         STR        R2, [SP, #0]
+  0x080052B8:  4621         MOV        R1, R4
+  0x080052BA:  F000 FCE4    BL         vfprintf                 ; 0x08005C86
+  0x080052BE:  B001         ADD        SP, SP, #4
+  0x080052C0:  BC10         POP        {R4}
+  0x080052C2:  BC02         POP        {R1}
+  0x080052C4:  B003         ADD        SP, SP, #12
+  0x080052C6:  4708         BX         R1
+  0x080052C8:  20000B98     DC.W       stdout
+
+

Section .text.libc.__SEGGER_RTL_vfprintf_int_nwp from __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a), size=840, align=4

+
+
__SEGGER_RTL_vfprintf_int_nwp:
+__SEGGER_RTL_vfprintf:
+  0x080052CC:  B5F0         PUSH       {R4-R7, LR}
+  0x080052CE:  B093         SUB        SP, SP, #76
+  0x080052D0:  9208         STR        R2, [SP, #32]
+  0x080052D2:  9109         STR        R1, [SP, #36]
+  0x080052D4:  4605         MOV        R5, R0
+  0x080052D6:  2000         MOVS       R0, #0
+  0x080052D8:  9006         STR        R0, [SP, #24]
+  0x080052DA:  6028         STR        R0, [R5]
+  0x080052DC:  2001         MOVS       R0, #1
+  0x080052DE:  0341         LSLS       R1, R0, #13
+  0x080052E0:  9102         STR        R1, [SP, #8]
+  0x080052E2:  0381         LSLS       R1, R0, #14
+  0x080052E4:  9105         STR        R1, [SP, #20]
+  0x080052E6:  9001         STR        R0, [SP, #4]
+  0x080052E8:  03C0         LSLS       R0, R0, #15
+  0x080052EA:  9003         STR        R0, [SP, #12]
+  0x080052EC:  9504         STR        R5, [SP, #16]
+
.L1:
+  0x080052EE:  9809         LDR        R0, [SP, #36]
+  0x080052F0:  1C44         ADDS       R4, R0, #1
+  0x080052F2:  7801         LDRB       R1, [R0]
+  0x080052F4:  2925         CMP        R1, #37
+  0x080052F6:  D007         BEQ        .L3                      ; 0x08005308
+  0x080052F8:  2900         CMP        R1, #0
+  0x080052FA:  D100         BNE        .L2                      ; 0x080052FE
+  0x080052FC:  E16E         B          .L63                     ; 0x080055DC
+
.L2:
+  0x080052FE:  4628         MOV        R0, R5
+  0x08005300:  F000 FC66    BL         __SEGGER_RTL_putc        ; 0x08005BD0
+  0x08005304:  9409         STR        R4, [SP, #36]
+  0x08005306:  E7F2         B          .L1                      ; 0x080052EE
+
.L3:
+  0x08005308:  9F06         LDR        R7, [SP, #24]
+
.L4:
+  0x0800530A:  1C61         ADDS       R1, R4, #1
+  0x0800530C:  7820         LDRB       R0, [R4]
+  0x0800530E:  285E         CMP        R0, #94
+  0x08005310:  460C         MOV        R4, R1
+  0x08005312:  D0FA         BEQ        .L4                      ; 0x0800530A
+  0x08005314:  287A         CMP        R0, #122
+  0x08005316:  D01A         BEQ        .L10                     ; 0x0800534E
+  0x08005318:  2823         CMP        R0, #35
+  0x0800531A:  D013         BEQ        .L7                      ; 0x08005344
+  0x0800531C:  2827         CMP        R0, #39
+  0x0800531E:  D00D         BEQ        .L5                      ; 0x0800533C
+  0x08005320:  282B         CMP        R0, #43
+  0x08005322:  D00D         BEQ        .L6                      ; 0x08005340
+  0x08005324:  2868         CMP        R0, #104
+  0x08005326:  D015         BEQ        .L12                     ; 0x08005354
+  0x08005328:  286A         CMP        R0, #106
+  0x0800532A:  D00E         BEQ        .L9                      ; 0x0800534A
+  0x0800532C:  286C         CMP        R0, #108
+  0x0800532E:  D016         BEQ        .L13                     ; 0x0800535E
+  0x08005330:  2874         CMP        R0, #116
+  0x08005332:  D00C         BEQ        .L10                     ; 0x0800534E
+  0x08005334:  2820         CMP        R0, #32
+  0x08005336:  D119         BNE        .L15                     ; 0x0800536C
+  0x08005338:  2040         MOVS       R0, #64
+  0x0800533A:  E004         B          .L8                      ; 0x08005346
+
.L5:
+  0x0800533C:  9803         LDR        R0, [SP, #12]
+  0x0800533E:  E002         B          .L8                      ; 0x08005346
+
.L6:
+  0x08005340:  2020         MOVS       R0, #32
+  0x08005342:  E000         B          .L8                      ; 0x08005346
+
.L7:
+  0x08005344:  2080         MOVS       R0, #128
+
.L8:
+  0x08005346:  4307         ORRS       R7, R0
+  0x08005348:  E7DF         B          .L4                      ; 0x0800530A
+
.L9:
+  0x0800534A:  2002         MOVS       R0, #2
+  0x0800534C:  4307         ORRS       R7, R0
+
.L10:
+  0x0800534E:  7808         LDRB       R0, [R1]
+
.L11:
+  0x08005350:  1C49         ADDS       R1, R1, #1
+  0x08005352:  E00B         B          .L15                     ; 0x0800536C
+
.L12:
+  0x08005354:  7808         LDRB       R0, [R1]
+  0x08005356:  2868         CMP        R0, #104
+  0x08005358:  D15A         BNE        .L23                     ; 0x08005410
+  0x0800535A:  2008         MOVS       R0, #8
+  0x0800535C:  E003         B          .L14                     ; 0x08005366
+
.L13:
+  0x0800535E:  7808         LDRB       R0, [R1]
+  0x08005360:  286C         CMP        R0, #108
+  0x08005362:  D1F5         BNE        .L11                     ; 0x08005350
+  0x08005364:  2002         MOVS       R0, #2
+
.L14:
+  0x08005366:  4307         ORRS       R7, R0
+  0x08005368:  7848         LDRB       R0, [R1, #1]
+  0x0800536A:  1C89         ADDS       R1, R1, #2
+
.L15:
+  0x0800536C:  9109         STR        R1, [SP, #36]
+
.L16:
+  0x0800536E:  4601         MOV        R1, R0
+  0x08005370:  3963         SUBS       R1, #99
+  0x08005372:  2300         MOVS       R3, #0
+  0x08005374:  2915         CMP        R1, #21
+  0x08005376:  D812         BHI        .L17                     ; 0x0800539E
+  0x08005378:  4479         ADD        R1, PC
+  0x0800537A:  7909         LDRB       R1, [R1, #4]
+  0x0800537C:  0049         LSLS       R1, R1, #1
+  0x0800537E:  448F         ADD        PC, R1
+  0x08005380:  16           DC.B       0x16                     ; '\x16'
+  0x08005381:  0B           DC.B       0x0B                     ; '\v'
+  0x08005382:  0A           DC.B       0x0A                     ; '\n'
+  0x08005383:  0A           DC.B       0x0A                     ; '\n'
+  0x08005384:  0A           DC.B       0x0A                     ; '\n'
+  0x08005385:  0A           DC.B       0x0A                     ; '\n'
+  0x08005386:  0B           DC.B       0x0B                     ; '\v'
+  0x08005387:  0A           DC.B       0x0A                     ; '\n'
+  0x08005388:  0A           DC.B       0x0A                     ; '\n'
+  0x08005389:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538A:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538B:  28           DC.B       0x28                     ; '('
+  0x0800538C:  35           DC.B       0x35                     ; '5'
+  0x0800538D:  1E           DC.B       0x1E                     ; '\x1E'
+  0x0800538E:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538F:  0A           DC.B       0x0A                     ; '\n'
+  0x08005390:  3A           DC.B       0x3A                     ; ':'
+  0x08005391:  0A           DC.B       0x0A                     ; '\n'
+  0x08005392:  59           DC.B       0x59                     ; 'Y'
+  0x08005393:  0A           DC.B       0x0A                     ; '\n'
+  0x08005394:  0A           DC.B       0x0A                     ; '\n'
+  0x08005395:  53           DC.B       0x53                     ; 'S'
+  0x08005396:  E7AA         B          .L1                      ; 0x080052EE
+  0x08005398:  9905         LDR        R1, [SP, #20]
+  0x0800539A:  430F         ORRS       R7, R1
+  0x0800539C:  E04A         B          .L26                     ; 0x08005434
+
.L17:
+  0x0800539E:  2825         CMP        R0, #37
+  0x080053A0:  D03B         BEQ        .L24                     ; 0x0800541A
+  0x080053A2:  2858         CMP        R0, #88
+  0x080053A4:  D03E         BEQ        .L25                     ; 0x08005424
+  0x080053A6:  2800         CMP        R0, #0
+  0x080053A8:  D000         BEQ        .L18                     ; 0x080053AC
+  0x080053AA:  E7A0         B          .L1                      ; 0x080052EE
+
.L18:
+  0x080053AC:  E125         B          .L66                     ; 0x080055FA
+  0x080053AE:  9C08         LDR        R4, [SP, #32]
+  0x080053B0:  7821         LDRB       R1, [R4]
+  0x080053B2:  4628         MOV        R0, R5
+  0x080053B4:  F000 FC0C    BL         __SEGGER_RTL_putc        ; 0x08005BD0
+  0x080053B8:  1D24         ADDS       R4, R4, #4
+  0x080053BA:  9408         STR        R4, [SP, #32]
+  0x080053BC:  E797         B          .L1                      ; 0x080052EE
+  0x080053BE:  0638         LSLS       R0, R7, #24
+  0x080053C0:  17C0         ASRS       R0, R0, #31
+  0x080053C2:  2123         MOVS       R1, #35
+  0x080053C4:  4001         ANDS       R1, R0
+  0x080053C6:  9107         STR        R1, [SP, #28]
+  0x080053C8:  9808         LDR        R0, [SP, #32]
+  0x080053CA:  C820         LDM        R0!, {R5}
+  0x080053CC:  9008         STR        R0, [SP, #32]
+  0x080053CE:  2400         MOVS       R4, #0
+  0x080053D0:  E0A1         B          .L46                     ; 0x08005516
+  0x080053D2:  9B08         LDR        R3, [SP, #32]
+  0x080053D4:  6818         LDR        R0, [R3]
+  0x080053D6:  0739         LSLS       R1, R7, #28
+  0x080053D8:  6829         LDR        R1, [R5]
+  0x080053DA:  D500         BPL        .L19                     ; 0x080053DE
+  0x080053DC:  E0F0         B          .L58                     ; 0x080055C0
+
.L19:
+  0x080053DE:  07BA         LSLS       R2, R7, #30
+  0x080053E0:  6001         STR        R1, [R0]
+  0x080053E2:  D400         BMI        .L20                     ; 0x080053E6
+  0x080053E4:  E0ED         B          .L59                     ; 0x080055C2
+
.L20:
+  0x080053E6:  2100         MOVS       R1, #0
+  0x080053E8:  6041         STR        R1, [R0, #4]
+  0x080053EA:  E0EA         B          .L59                     ; 0x080055C2
+  0x080053EC:  0639         LSLS       R1, R7, #24
+  0x080053EE:  17C9         ASRS       R1, R1, #31
+  0x080053F0:  2330         MOVS       R3, #48
+  0x080053F2:  400B         ANDS       R3, R1
+  0x080053F4:  E01E         B          .L26                     ; 0x08005434
+  0x080053F6:  9E08         LDR        R6, [SP, #32]
+  0x080053F8:  6834         LDR        R4, [R6]
+
.L21:
+  0x080053FA:  7821         LDRB       R1, [R4]
+  0x080053FC:  2900         CMP        R1, #0
+  0x080053FE:  D004         BEQ        .L22                     ; 0x0800540A
+  0x08005400:  4628         MOV        R0, R5
+  0x08005402:  F000 FBE5    BL         __SEGGER_RTL_putc        ; 0x08005BD0
+  0x08005406:  1C64         ADDS       R4, R4, #1
+  0x08005408:  E7F7         B          .L21                     ; 0x080053FA
+
.L22:
+  0x0800540A:  1D36         ADDS       R6, R6, #4
+  0x0800540C:  9608         STR        R6, [SP, #32]
+  0x0800540E:  E76E         B          .L1                      ; 0x080052EE
+
.L23:
+  0x08005410:  1C49         ADDS       R1, R1, #1
+  0x08005412:  9109         STR        R1, [SP, #36]
+  0x08005414:  2104         MOVS       R1, #4
+  0x08005416:  430F         ORRS       R7, R1
+  0x08005418:  E7A9         B          .L16                     ; 0x0800536E
+
.L24:
+  0x0800541A:  2125         MOVS       R1, #37
+  0x0800541C:  4628         MOV        R0, R5
+  0x0800541E:  F000 FBD7    BL         __SEGGER_RTL_putc        ; 0x08005BD0
+  0x08005422:  E764         B          .L1                      ; 0x080052EE
+
.L25:
+  0x08005424:  9902         LDR        R1, [SP, #8]
+  0x08005426:  430F         ORRS       R7, R1
+  0x08005428:  0639         LSLS       R1, R7, #24
+  0x0800542A:  D503         BPL        .L26                     ; 0x08005434
+  0x0800542C:  4B76         LDR        R3, =0x00003058          ; [PC, #0x01D8] [0x08005608] 
+  0x0800542E:  2878         CMP        R0, #120
+  0x08005430:  D100         BNE        .L26                     ; 0x08005434
+  0x08005432:  3320         ADDS       R3, #32
+
.L26:
+  0x08005434:  9307         STR        R3, [SP, #28]
+  0x08005436:  2102         MOVS       R1, #2
+  0x08005438:  4039         ANDS       R1, R7
+  0x0800543A:  9A05         LDR        R2, [SP, #20]
+  0x0800543C:  4217         TST        R7, R2
+  0x0800543E:  D105         BNE        .L27                     ; 0x0800544C
+  0x08005440:  2900         CMP        R1, #0
+  0x08005442:  9A08         LDR        R2, [SP, #32]
+  0x08005444:  D108         BNE        .L28                     ; 0x08005458
+  0x08005446:  1D11         ADDS       R1, R2, #4
+  0x08005448:  2400         MOVS       R4, #0
+  0x0800544A:  E00B         B          .L29                     ; 0x08005464
+
.L27:
+  0x0800544C:  2900         CMP        R1, #0
+  0x0800544E:  9B08         LDR        R3, [SP, #32]
+  0x08005450:  D10F         BNE        .L30                     ; 0x08005472
+  0x08005452:  CB02         LDM        R3!, {R1}
+  0x08005454:  17CC         ASRS       R4, R1, #31
+  0x08005456:  E011         B          .L31                     ; 0x0800547C
+
.L28:
+  0x08005458:  1DD2         ADDS       R2, R2, #7
+  0x0800545A:  2107         MOVS       R1, #7
+  0x0800545C:  438A         BICS       R2, R1
+  0x0800545E:  6854         LDR        R4, [R2, #4]
+  0x08005460:  4611         MOV        R1, R2
+  0x08005462:  3108         ADDS       R1, #8
+
.L29:
+  0x08005464:  6815         LDR        R5, [R2]
+  0x08005466:  077A         LSLS       R2, R7, #29
+  0x08005468:  D40E         BMI        .L32                     ; 0x08005488
+  0x0800546A:  073A         LSLS       R2, R7, #28
+  0x0800546C:  D50E         BPL        .L34                     ; 0x0800548C
+  0x0800546E:  B2ED         UXTB       R5, R5
+  0x08005470:  E00B         B          .L33                     ; 0x0800548A
+
.L30:
+  0x08005472:  1DDB         ADDS       R3, R3, #7
+  0x08005474:  2107         MOVS       R1, #7
+  0x08005476:  438B         BICS       R3, R1
+  0x08005478:  CB12         LDM        R3!, {R1, R4}
+  0x0800547A:  3300         ADDS       R3, #0
+
.L31:
+  0x0800547C:  077A         LSLS       R2, R7, #29
+  0x0800547E:  D407         BMI        .L35                     ; 0x08005490
+  0x08005480:  073A         LSLS       R2, R7, #28
+  0x08005482:  D408         BMI        .L36                     ; 0x08005496
+  0x08005484:  460D         MOV        R5, R1
+  0x08005486:  E009         B          .L38                     ; 0x0800549C
+
.L32:
+  0x08005488:  B2AD         UXTH       R5, R5
+
.L33:
+  0x0800548A:  2400         MOVS       R4, #0
+
.L34:
+  0x0800548C:  9108         STR        R1, [SP, #32]
+  0x0800548E:  E017         B          .L42                     ; 0x080054C0
+
.L35:
+  0x08005490:  B20D         SXTH       R5, R1
+  0x08005492:  0409         LSLS       R1, R1, #16
+  0x08005494:  E001         B          .L37                     ; 0x0800549A
+
.L36:
+  0x08005496:  B24D         SXTB       R5, R1
+  0x08005498:  0609         LSLS       R1, R1, #24
+
.L37:
+  0x0800549A:  17CC         ASRS       R4, R1, #31
+
.L38:
+  0x0800549C:  2C00         CMP        R4, #0
+  0x0800549E:  9308         STR        R3, [SP, #32]
+  0x080054A0:  D405         BMI        .L39                     ; 0x080054AE
+  0x080054A2:  06B9         LSLS       R1, R7, #26
+  0x080054A4:  D40A         BMI        .L40                     ; 0x080054BC
+  0x080054A6:  0679         LSLS       R1, R7, #25
+  0x080054A8:  D50A         BPL        .L42                     ; 0x080054C0
+  0x080054AA:  2120         MOVS       R1, #32
+  0x080054AC:  E007         B          .L41                     ; 0x080054BE
+
.L39:
+  0x080054AE:  2100         MOVS       R1, #0
+  0x080054B0:  426D         RSBS       R5, R5, #0
+  0x080054B2:  41A1         SBCS       R1, R4
+  0x080054B4:  222D         MOVS       R2, #45
+  0x080054B6:  9207         STR        R2, [SP, #28]
+  0x080054B8:  460C         MOV        R4, R1
+  0x080054BA:  E001         B          .L42                     ; 0x080054C0
+
.L40:
+  0x080054BC:  212B         MOVS       R1, #43
+
.L41:
+  0x080054BE:  9107         STR        R1, [SP, #28]
+
.L42:
+  0x080054C0:  4601         MOV        R1, R0
+  0x080054C2:  396F         SUBS       R1, #111
+  0x080054C4:  2600         MOVS       R6, #0
+  0x080054C6:  2909         CMP        R1, #9
+  0x080054C8:  D81F         BHI        .L45                     ; 0x0800550A
+  0x080054CA:  46C0         NOP
+  0x080054CC:  4479         ADD        R1, PC
+  0x080054CE:  7909         LDRB       R1, [R1, #4]
+  0x080054D0:  0049         LSLS       R1, R1, #1
+  0x080054D2:  448F         ADD        PC, R1
+  0x080054D4:  04           DC.B       0x04                     ; '\x04'
+  0x080054D5:  20           DC.B       0x20                     ; ' '
+  0x080054D6:  6A           DC.B       0x6A                     ; 'j'
+  0x080054D7:  6A           DC.B       0x6A                     ; 'j'
+  0x080054D8:  6A           DC.B       0x6A                     ; 'j'
+  0x080054D9:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DA:  25           DC.B       0x25                     ; '%'
+  0x080054DB:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DC:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DD:  20           DC.B       0x20                     ; ' '
+  0x080054DE:  4628         MOV        R0, R5
+  0x080054E0:  4320         ORRS       R0, R4
+  0x080054E2:  D10E         BNE        .L44                     ; 0x08005502
+  0x080054E4:  A80D         ADD        R0, SP, #52
+  0x080054E6:  2130         MOVS       R1, #48
+  0x080054E8:  7001         STRB       R1, [R0]
+  0x080054EA:  2601         MOVS       R6, #1
+  0x080054EC:  E009         B          .L44                     ; 0x08005502
+
.L43:
+  0x080054EE:  2007         MOVS       R0, #7
+  0x080054F0:  4028         ANDS       R0, R5
+  0x080054F2:  3030         ADDS       R0, #48
+  0x080054F4:  A90D         ADD        R1, SP, #52
+  0x080054F6:  5588         STRB       R0, [R1, R6]
+  0x080054F8:  08E8         LSRS       R0, R5, #3
+  0x080054FA:  0761         LSLS       R1, R4, #29
+  0x080054FC:  1845         ADDS       R5, R0, R1
+  0x080054FE:  08E4         LSRS       R4, R4, #3
+  0x08005500:  1C76         ADDS       R6, R6, #1
+
.L44:
+  0x08005502:  4628         MOV        R0, R5
+  0x08005504:  4320         ORRS       R0, R4
+  0x08005506:  D050         BEQ        .L56                     ; 0x080055AA
+  0x08005508:  E7F1         B          .L43                     ; 0x080054EE
+
.L45:
+  0x0800550A:  2869         CMP        R0, #105
+  0x0800550C:  D008         BEQ        .L47                     ; 0x08005520
+  0x0800550E:  2864         CMP        R0, #100
+  0x08005510:  D006         BEQ        .L47                     ; 0x08005520
+  0x08005512:  2858         CMP        R0, #88
+  0x08005514:  D149         BNE        .L56                     ; 0x080055AA
+
.L46:
+  0x08005516:  4628         MOV        R0, R5
+  0x08005518:  4320         ORRS       R0, R4
+  0x0800551A:  D02E         BEQ        .L51                     ; 0x0800557A
+  0x0800551C:  2600         MOVS       R6, #0
+  0x0800551E:  E030         B          .L52                     ; 0x08005582
+
.L47:
+  0x08005520:  4628         MOV        R0, R5
+  0x08005522:  4320         ORRS       R0, R4
+  0x08005524:  D103         BNE        .L48                     ; 0x0800552E
+  0x08005526:  A80D         ADD        R0, SP, #52
+  0x08005528:  2130         MOVS       R1, #48
+  0x0800552A:  7001         STRB       R1, [R0]
+  0x0800552C:  2601         MOVS       R6, #1
+
.L48:
+  0x0800552E:  9803         LDR        R0, [SP, #12]
+  0x08005530:  4007         ANDS       R7, R0
+  0x08005532:  970A         STR        R7, [SP, #40]
+
.L49:
+  0x08005534:  4628         MOV        R0, R5
+  0x08005536:  4320         ORRS       R0, R4
+  0x08005538:  D037         BEQ        .L56                     ; 0x080055AA
+  0x0800553A:  2F00         CMP        R7, #0
+  0x0800553C:  D007         BEQ        .L50                     ; 0x0800554E
+  0x0800553E:  2003         MOVS       R0, #3
+  0x08005540:  4030         ANDS       R0, R6
+  0x08005542:  2803         CMP        R0, #3
+  0x08005544:  D103         BNE        .L50                     ; 0x0800554E
+  0x08005546:  A80D         ADD        R0, SP, #52
+  0x08005548:  212C         MOVS       R1, #44
+  0x0800554A:  5581         STRB       R1, [R0, R6]
+  0x0800554C:  1C76         ADDS       R6, R6, #1
+
.L50:
+  0x0800554E:  220A         MOVS       R2, #10
+  0x08005550:  920B         STR        R2, [SP, #44]
+  0x08005552:  2300         MOVS       R3, #0
+  0x08005554:  4628         MOV        R0, R5
+  0x08005556:  4621         MOV        R1, R4
+  0x08005558:  F000 FDAF    BL         __aeabi_uldivmod         ; 0x080060BA
+  0x0800555C:  900C         STR        R0, [SP, #48]
+  0x0800555E:  460C         MOV        R4, R1
+  0x08005560:  9A0B         LDR        R2, [SP, #44]
+  0x08005562:  2300         MOVS       R3, #0
+  0x08005564:  F000 FB1A    BL         __aeabi_lmul             ; 0x08005B9C
+  0x08005568:  1A28         SUBS       R0, R5, R0
+  0x0800556A:  2130         MOVS       R1, #48
+  0x0800556C:  4301         ORRS       R1, R0
+  0x0800556E:  A80D         ADD        R0, SP, #52
+  0x08005570:  5581         STRB       R1, [R0, R6]
+  0x08005572:  1C76         ADDS       R6, R6, #1
+  0x08005574:  9D0C         LDR        R5, [SP, #48]
+  0x08005576:  9F0A         LDR        R7, [SP, #40]
+  0x08005578:  E7DC         B          .L49                     ; 0x08005534
+
.L51:
+  0x0800557A:  A80D         ADD        R0, SP, #52
+  0x0800557C:  2130         MOVS       R1, #48
+  0x0800557E:  7001         STRB       R1, [R0]
+  0x08005580:  9E01         LDR        R6, [SP, #4]
+
.L52:
+  0x08005582:  9802         LDR        R0, [SP, #8]
+  0x08005584:  4207         TST        R7, R0
+  0x08005586:  D001         BEQ        .L53                     ; 0x0800558C
+  0x08005588:  4821         LDR        R0, =__SEGGER_RTL_hex_uc ; [PC, #132] [0x08005610] =0x080069A8 
+  0x0800558A:  E00B         B          .L55                     ; 0x080055A4
+
.L53:
+  0x0800558C:  481F         LDR        R0, =__SEGGER_RTL_hex_lc ; [PC, #124] [0x0800560C] =0x080069B8 
+  0x0800558E:  E009         B          .L55                     ; 0x080055A4
+
.L54:
+  0x08005590:  210F         MOVS       R1, #15
+  0x08005592:  4029         ANDS       R1, R5
+  0x08005594:  5C41         LDRB       R1, [R0, R1]
+  0x08005596:  AA0D         ADD        R2, SP, #52
+  0x08005598:  5591         STRB       R1, [R2, R6]
+  0x0800559A:  0929         LSRS       R1, R5, #4
+  0x0800559C:  0722         LSLS       R2, R4, #28
+  0x0800559E:  188D         ADDS       R5, R1, R2
+  0x080055A0:  0924         LSRS       R4, R4, #4
+  0x080055A2:  1C76         ADDS       R6, R6, #1
+
.L55:
+  0x080055A4:  4629         MOV        R1, R5
+  0x080055A6:  4321         ORRS       R1, R4
+  0x080055A8:  D1F2         BNE        .L54                     ; 0x08005590
+
.L56:
+  0x080055AA:  9C07         LDR        R4, [SP, #28]
+  0x080055AC:  0A21         LSRS       R1, R4, #8
+  0x080055AE:  9D04         LDR        R5, [SP, #16]
+  0x080055B0:  D003         BEQ        .L57                     ; 0x080055BA
+  0x080055B2:  4628         MOV        R0, R5
+  0x080055B4:  F000 FB0C    BL         __SEGGER_RTL_putc        ; 0x08005BD0
+  0x080055B8:  E006         B          .L60                     ; 0x080055C8
+
.L57:
+  0x080055BA:  2C00         CMP        R4, #0
+  0x080055BC:  D008         BEQ        .L61                     ; 0x080055D0
+  0x080055BE:  E003         B          .L60                     ; 0x080055C8
+
.L58:
+  0x080055C0:  7001         STRB       R1, [R0]
+
.L59:
+  0x080055C2:  1D1B         ADDS       R3, R3, #4
+  0x080055C4:  9308         STR        R3, [SP, #32]
+  0x080055C6:  E692         B          .L1                      ; 0x080052EE
+
.L60:
+  0x080055C8:  4628         MOV        R0, R5
+  0x080055CA:  4621         MOV        R1, R4
+  0x080055CC:  F000 FB00    BL         __SEGGER_RTL_putc        ; 0x08005BD0
+
.L61:
+  0x080055D0:  1E76         SUBS       R6, R6, #1
+  0x080055D2:  DA00         BGE        .L62                     ; 0x080055D6
+  0x080055D4:  E68B         B          .L1                      ; 0x080052EE
+
.L62:
+  0x080055D6:  A80D         ADD        R0, SP, #52
+  0x080055D8:  5D84         LDRB       R4, [R0, R6]
+  0x080055DA:  E7F5         B          .L60                     ; 0x080055C8
+
.L63:
+  0x080055DC:  68E8         LDR        R0, [R5, #12]
+  0x080055DE:  2800         CMP        R0, #0
+  0x080055E0:  D005         BEQ        .L64                     ; 0x080055EE
+  0x080055E2:  CD06         LDM        R5!, {R1-R2}
+  0x080055E4:  3D08         SUBS       R5, #8
+  0x080055E6:  4291         CMP        R1, R2
+  0x080055E8:  D201         BCS        .L64                     ; 0x080055EE
+  0x080055EA:  9A06         LDR        R2, [SP, #24]
+  0x080055EC:  5442         STRB       R2, [R0, R1]
+
.L64:
+  0x080055EE:  4628         MOV        R0, R5
+  0x080055F0:  F000 FB33    BL         __SEGGER_RTL_prin_flush  ; 0x08005C5A
+  0x080055F4:  6828         LDR        R0, [R5]
+
.L65:
+  0x080055F6:  B013         ADD        SP, SP, #76
+  0x080055F8:  BDF0         POP        {R4-R7, PC}
+
.L66:
+  0x080055FA:  4628         MOV        R0, R5
+  0x080055FC:  F000 FB2D    BL         __SEGGER_RTL_prin_flush  ; 0x08005C5A
+  0x08005600:  2000         MOVS       R0, #0
+  0x08005602:  43C0         MVNS       R0, R0
+  0x08005604:  E7F7         B          .L65                     ; 0x080055F6
+  0x08005606:  46C0         NOP
+  0x08005608:  00003058     DC.W       0x00003058
+  0x0800560C:  080069B8     DC.W       __SEGGER_RTL_hex_lc
+  0x08005610:  080069A8     DC.W       __SEGGER_RTL_hex_uc
+
+

Section .text.libc.__SEGGER_RTL_X_file_stat from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=44, align=4

+
+
__SEGGER_RTL_X_file_stat:
+  0x08005614:  4601         MOV        R1, R0
+  0x08005616:  4807         LDR        R0, =stdin               ; [PC, #28] [0x08005634] =0x20000B9C 
+  0x08005618:  6802         LDR        R2, [R0]
+  0x0800561A:  2000         MOVS       R0, #0
+  0x0800561C:  4291         CMP        R1, R2
+  0x0800561E:  D008         BEQ        .L1                      ; 0x08005632
+  0x08005620:  4A05         LDR        R2, =stdout              ; [PC, #20] [0x08005638] =0x20000B98 
+  0x08005622:  6812         LDR        R2, [R2]
+  0x08005624:  4291         CMP        R1, R2
+  0x08005626:  D004         BEQ        .L1                      ; 0x08005632
+  0x08005628:  4A04         LDR        R2, =stderr              ; [PC, #16] [0x0800563C] =0x20000BA0 
+  0x0800562A:  6812         LDR        R2, [R2]
+  0x0800562C:  4291         CMP        R1, R2
+  0x0800562E:  D000         BEQ        .L1                      ; 0x08005632
+  0x08005630:  43C0         MVNS       R0, R0
+
.L1:
+  0x08005632:  4770         BX         LR
+  0x08005634:  20000B9C     DC.W       stdin
+  0x08005638:  20000B98     DC.W       stdout
+  0x0800563C:  20000BA0     DC.W       stderr
+
+

Section .text.libc._DoInit from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=84, align=4

+
+
_DoInit:
+  0x08005640:  480F         LDR        R0, =_SEGGER_RTT         ; [PC, #60] [0x08005680] =0x20000314 
+  0x08005642:  2103         MOVS       R1, #3
+  0x08005644:  6101         STR        R1, [R0, #16]
+  0x08005646:  6141         STR        R1, [R0, #20]
+  0x08005648:  4A0E         LDR        R2, =0x080067E8          ; [PC, #56] [0x08005684] 
+  0x0800564A:  6182         STR        R2, [R0, #24]
+  0x0800564C:  490E         LDR        R1, =_acUpBuffer         ; [PC, #56] [0x08005688] =0x20000769 
+  0x0800564E:  61C1         STR        R1, [R0, #28]
+  0x08005650:  2101         MOVS       R1, #1
+  0x08005652:  0289         LSLS       R1, R1, #10
+  0x08005654:  6201         STR        R1, [R0, #32]
+  0x08005656:  2100         MOVS       R1, #0
+  0x08005658:  6281         STR        R1, [R0, #40]
+  0x0800565A:  6241         STR        R1, [R0, #36]
+  0x0800565C:  62C1         STR        R1, [R0, #44]
+  0x0800565E:  6602         STR        R2, [R0, #96]
+  0x08005660:  4A0A         LDR        R2, =_acDownBuffer       ; [PC, #40] [0x0800568C] =0x20000B69 
+  0x08005662:  6642         STR        R2, [R0, #100]
+  0x08005664:  2210         MOVS       R2, #16
+  0x08005666:  6682         STR        R2, [R0, #104]
+  0x08005668:  6701         STR        R1, [R0, #112]
+  0x0800566A:  66C1         STR        R1, [R0, #108]
+  0x0800566C:  6741         STR        R1, [R0, #116]
+  0x0800566E:  4A08         LDR        R2, =0x080067E6          ; [PC, #32] [0x08005690] 
+
.L1:
+  0x08005670:  2910         CMP        R1, #16
+  0x08005672:  D004         BEQ        .L2                      ; 0x0800567E
+  0x08005674:  7813         LDRB       R3, [R2]
+  0x08005676:  5443         STRB       R3, [R0, R1]
+  0x08005678:  1E52         SUBS       R2, R2, #1
+  0x0800567A:  1C49         ADDS       R1, R1, #1
+  0x0800567C:  E7F8         B          .L1                      ; 0x08005670
+
.L2:
+  0x0800567E:  4770         BX         LR
+  0x08005680:  20000314     DC.W       _SEGGER_RTT
+  0x08005684:  080067E8     DC.W       080067E8               ; R_ARM_ABS32
+  0x08005688:  20000769     DC.W       _acUpBuffer
+  0x0800568C:  20000B69     DC.W       _acDownBuffer
+  0x08005690:  080067E6     DC.W       080067E6               ; R_ARM_ABS32
+
+

Section .text.libc.SEGGER_RTT_WriteNoLock from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=104, align=4

+
+
SEGGER_RTT_WriteNoLock:
+  0x08005694:  B5F0         PUSH       {R4-R7, LR}
+  0x08005696:  B081         SUB        SP, SP, #4
+  0x08005698:  460D         MOV        R5, R1
+  0x0800569A:  2118         MOVS       R1, #24
+  0x0800569C:  4341         MULS       R1, R0, R1
+  0x0800569E:  4816         LDR        R0, =_SEGGER_RTT         ; [PC, #88] [0x080056F8] =0x20000314 
+  0x080056A0:  1846         ADDS       R6, R0, R1
+  0x080056A2:  6AF0         LDR        R0, [R6, #44]
+  0x080056A4:  3618         ADDS       R6, #24
+  0x080056A6:  2802         CMP        R0, #2
+  0x080056A8:  D01E         BEQ        .L3                      ; 0x080056E8
+  0x080056AA:  4614         MOV        R4, R2
+  0x080056AC:  2801         CMP        R0, #1
+  0x080056AE:  D00E         BEQ        .L1                      ; 0x080056CE
+  0x080056B0:  2700         MOVS       R7, #0
+  0x080056B2:  2800         CMP        R0, #0
+  0x080056B4:  D11D         BNE        .L4                      ; 0x080056F2
+  0x080056B6:  4630         MOV        R0, R6
+  0x080056B8:  F000 FAF7    BL         _GetAvailWriteSpace      ; 0x08005CAA
+  0x080056BC:  42A0         CMP        R0, R4
+  0x080056BE:  D318         BCC        .L4                      ; 0x080056F2
+  0x080056C0:  4630         MOV        R0, R6
+  0x080056C2:  4629         MOV        R1, R5
+  0x080056C4:  4622         MOV        R2, R4
+  0x080056C6:  F000 FAFB    BL         _WriteNoCheck            ; 0x08005CC0
+  0x080056CA:  4627         MOV        R7, R4
+  0x080056CC:  E011         B          .L4                      ; 0x080056F2
+
.L1:
+  0x080056CE:  4630         MOV        R0, R6
+  0x080056D0:  F000 FAEB    BL         _GetAvailWriteSpace      ; 0x08005CAA
+  0x080056D4:  4607         MOV        R7, R0
+  0x080056D6:  42A0         CMP        R0, R4
+  0x080056D8:  D300         BCC        .L2                      ; 0x080056DC
+  0x080056DA:  4627         MOV        R7, R4
+
.L2:
+  0x080056DC:  4630         MOV        R0, R6
+  0x080056DE:  4629         MOV        R1, R5
+  0x080056E0:  463A         MOV        R2, R7
+  0x080056E2:  F000 FAED    BL         _WriteNoCheck            ; 0x08005CC0
+  0x080056E6:  E004         B          .L4                      ; 0x080056F2
+
.L3:
+  0x080056E8:  4630         MOV        R0, R6
+  0x080056EA:  4629         MOV        R1, R5
+  0x080056EC:  F000 FD33    BL         _WriteBlocking           ; 0x08006156
+  0x080056F0:  4607         MOV        R7, R0
+
.L4:
+  0x080056F2:  4638         MOV        R0, R7
+  0x080056F4:  B001         ADD        SP, SP, #4
+  0x080056F6:  BDF0         POP        {R4-R7, PC}
+  0x080056F8:  20000314     DC.W       _SEGGER_RTT
+
+

Section .text.libc.SEGGER_RTT_Write from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=56, align=4

+
+
SEGGER_RTT_Write:
+  0x080056FC:  B5F0         PUSH       {R4-R7, LR}
+  0x080056FE:  B081         SUB        SP, SP, #4
+  0x08005700:  4614         MOV        R4, R2
+  0x08005702:  460D         MOV        R5, R1
+  0x08005704:  4606         MOV        R6, R0
+  0x08005706:  480A         LDR        R0, =_SEGGER_RTT         ; [PC, #40] [0x08005730] =0x20000314 
+  0x08005708:  7800         LDRB       R0, [R0]
+  0x0800570A:  2800         CMP        R0, #0
+  0x0800570C:  D101         BNE        .L1                      ; 0x08005712
+  0x0800570E:  F7FF FF97    BL         _DoInit                  ; 0x08005640
+
.L1:
+  0x08005712:  F3EF 8710    MRS        R7, PRIMASK
+  0x08005716:  2101         MOVS       R1, #1
+  0x08005718:  F381 8810    MSR        PRIMASK, R1
+  0x0800571C:  4630         MOV        R0, R6
+  0x0800571E:  4629         MOV        R1, R5
+  0x08005720:  4622         MOV        R2, R4
+  0x08005722:  F7FF FFB7    BL         SEGGER_RTT_WriteNoLock   ; 0x08005694
+  0x08005726:  F387 8810    MSR        PRIMASK, R7
+  0x0800572A:  B001         ADD        SP, SP, #4
+  0x0800572C:  BDF0         POP        {R4-R7, PC}
+  0x0800572E:  46C0         NOP
+  0x08005730:  20000314     DC.W       _SEGGER_RTT
+
+

Section .text.libc.__SEGGER_RTL_current_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=20, align=4

+
+
__SEGGER_RTL_current_locale:
+  0x08005734:  4802         LDR        R0, =__SEGGER_RTL_locale_ptr ; [PC, #8] [0x08005740] =0x200006D8 
+  0x08005736:  6800         LDR        R0, [R0]
+  0x08005738:  2800         CMP        R0, #0
+  0x0800573A:  D100         BNE        .L1                      ; 0x0800573E
+  0x0800573C:  4801         LDR        R0, =__SEGGER_RTL_global_locale ; [PC, #4] [0x08005744] =0x20000B80 
+
.L1:
+  0x0800573E:  4770         BX         LR
+  0x08005740:  200006D8     DC.W       __SEGGER_RTL_locale_ptr
+  0x08005744:  20000B80     DC.W       __SEGGER_RTL_global_locale
+
+

Section .text.libc.__SEGGER_RTL_ascii_isctype from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__SEGGER_RTL_ascii_isctype:
+  0x08005748:  287F         CMP        R0, #127
+  0x0800574A:  D805         BHI        .L1                      ; 0x08005758
+  0x0800574C:  4A03         LDR        R2, =__SEGGER_RTL_ascii_ctype_map ; [PC, #12] [0x0800575C] =0x080069C8 
+  0x0800574E:  5C12         LDRB       R2, [R2, R0]
+  0x08005750:  4803         LDR        R0, =__SEGGER_RTL_ascii_ctype_mask ; [PC, #12] [0x08005760] =0x08006852 
+  0x08005752:  5C40         LDRB       R0, [R0, R1]
+  0x08005754:  4010         ANDS       R0, R2
+  0x08005756:  4770         BX         LR
+
.L1:
+  0x08005758:  2000         MOVS       R0, #0
+  0x0800575A:  4770         BX         LR
+  0x0800575C:  080069C8     DC.W       __SEGGER_RTL_ascii_ctype_map
+  0x08005760:  08006852     DC.W       __SEGGER_RTL_ascii_ctype_mask
+
+

Section .text.libc.__SEGGER_RTL_ascii_iswctype from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__SEGGER_RTL_ascii_iswctype:
+  0x08005764:  287F         CMP        R0, #127
+  0x08005766:  D805         BHI        .L1                      ; 0x08005774
+  0x08005768:  4A03         LDR        R2, =__SEGGER_RTL_ascii_ctype_map ; [PC, #12] [0x08005778] =0x080069C8 
+  0x0800576A:  5C12         LDRB       R2, [R2, R0]
+  0x0800576C:  4803         LDR        R0, =__SEGGER_RTL_ascii_ctype_mask ; [PC, #12] [0x0800577C] =0x08006852 
+  0x0800576E:  5C40         LDRB       R0, [R0, R1]
+  0x08005770:  4010         ANDS       R0, R2
+  0x08005772:  4770         BX         LR
+
.L1:
+  0x08005774:  2000         MOVS       R0, #0
+  0x08005776:  4770         BX         LR
+  0x08005778:  080069C8     DC.W       __SEGGER_RTL_ascii_ctype_map
+  0x0800577C:  08006852     DC.W       __SEGGER_RTL_ascii_ctype_mask
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=4

+
+
__SEGGER_RTL_c_locale:
+  0x08005780:  080065A5     DC.W       080065A5               ; R_ARM_ABS32
+  0x08005784:  080057AC     DC.W       __SEGGER_RTL_c_locale_data
+  0x08005788:  0800578C     DC.W       __SEGGER_RTL_codeset_ascii
+
+

Section .rodata.libc.__SEGGER_RTL_codeset_ascii from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=32, align=4

+
+
__SEGGER_RTL_codeset_ascii:
+  0x0800578C:  08005749     DC.W       __SEGGER_RTL_ascii_isctype
+  0x08005790:  080061D3     DC.W       __SEGGER_RTL_ascii_toupper
+  0x08005794:  08005D73     DC.W       __SEGGER_RTL_ascii_tolower
+  0x08005798:  08005765     DC.W       __SEGGER_RTL_ascii_iswctype
+  0x0800579C:  080061DF     DC.W       __SEGGER_RTL_ascii_towupper
+  0x080057A0:  08005D81     DC.W       __SEGGER_RTL_ascii_towlower
+  0x080057A4:  080061C3     DC.W       __SEGGER_RTL_ascii_wctomb
+  0x080057A8:  08005D45     DC.W       __SEGGER_RTL_ascii_mbtowc
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_data from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=88, align=4

+
+
__SEGGER_RTL_c_locale_data:
+  0x080057AC:  080065A7     DC.W       __SEGGER_RTL_data_utf8_period
+  0x080057B0:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057B4:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057B8:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057BC:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057C0:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057C4:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057C8:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057CC:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057D0:  08006851     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057D4:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057D5:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057D6:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057D7:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057D8:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057D9:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DA:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DB:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DC:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DD:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DE:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DF:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E0:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E1:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E2:  00           DC.B       0x00                     ; '\0'
+  0x080057E3:  00           DC.B       0x00                     ; '\0'
+  0x080057E4:  0800656B     DC.W       __SEGGER_RTL_c_locale_day_names
+  0x080057E8:  08006803     DC.W       __SEGGER_RTL_c_locale_abbrev_day_names
+  0x080057EC:  0800637A     DC.W       __SEGGER_RTL_c_locale_month_names
+  0x080057F0:  08006820     DC.W       __SEGGER_RTL_c_locale_abbrev_month_names
+  0x080057F4:  080063D1     DC.W       __SEGGER_RTL_c_locale_am_pm_indicator
+  0x080057F8:  080067F1     DC.W       __SEGGER_RTL_c_locale_date_format
+  0x080057FC:  080067FA     DC.W       __SEGGER_RTL_c_locale_time_format
+  0x08005800:  080063D8     DC.W       __SEGGER_RTL_c_locale_date_time_format
+
+

Section .text.NMI_Handler from PowerPro_lto.o, size=2, align=2

+
+
NMI_Handler:
+  0x08005804:  E7FE         B          NMI_Handler              ; 0x08005804
+
+

Section .text.HardFault_Handler from PowerPro_lto.o, size=2, align=2

+
+
HardFault_Handler:
+  0x08005806:  E7FE         B          HardFault_Handler        ; 0x08005806
+
+

Section .text.SVC_Handler from PowerPro_lto.o, size=2, align=2

+
+
SVC_Handler:
+  0x08005808:  4770         BX         LR
+
+

Section .text.PendSV_Handler from PowerPro_lto.o, size=2, align=2

+
+
PendSV_Handler:
+  0x0800580A:  4770         BX         LR
+
+

Section .text.ADC_DMAHalfConvCplt from PowerPro_lto.o, size=2, align=2

+
+
ADC_DMAHalfConvCplt:
+  0x0800580C:  4770         BX         LR
+
+

Section .text.UART_DMATxHalfCplt from PowerPro_lto.o, size=2, align=2

+
+
UART_DMATxHalfCplt:
+  0x0800580E:  4770         BX         LR
+
+

Section .text.UART_DMAError from PowerPro_lto.o, size=138, align=2

+
+
UART_DMAError:
+  0x08005810:  B5F0         PUSH       {R4-R7, LR}
+  0x08005812:  B081         SUB        SP, SP, #4
+  0x08005814:  6A84         LDR        R4, [R0, #40]
+  0x08005816:  2088         MOVS       R0, #136
+  0x08005818:  5823         LDR        R3, [R4, R0]
+  0x0800581A:  4625         MOV        R5, R4
+  0x0800581C:  3588         ADDS       R5, #136
+  0x0800581E:  686F         LDR        R7, [R5, #4]
+  0x08005820:  4620         MOV        R0, R4
+  0x08005822:  3056         ADDS       R0, #86
+  0x08005824:  6822         LDR        R2, [R4]
+  0x08005826:  6896         LDR        R6, [R2, #8]
+  0x08005828:  0636         LSLS       R6, R6, #24
+  0x0800582A:  D523         BPL        .L1                      ; 0x08005874
+  0x0800582C:  2B21         CMP        R3, #33
+  0x0800582E:  D121         BNE        .L1                      ; 0x08005874
+  0x08005830:  2200         MOVS       R2, #0
+  0x08005832:  8002         STRH       R2, [R0]
+  0x08005834:  F3EF 8110    MRS        R1, PRIMASK
+  0x08005838:  9100         STR        R1, [SP, #0]
+  0x0800583A:  2301         MOVS       R3, #1
+  0x0800583C:  F383 8810    MSR        PRIMASK, R3
+  0x08005840:  6826         LDR        R6, [R4]
+  0x08005842:  4602         MOV        R2, R0
+  0x08005844:  4638         MOV        R0, R7
+  0x08005846:  6837         LDR        R7, [R6]
+  0x08005848:  21C0         MOVS       R1, #192
+  0x0800584A:  438F         BICS       R7, R1
+  0x0800584C:  6037         STR        R7, [R6]
+  0x0800584E:  4607         MOV        R7, R0
+  0x08005850:  4610         MOV        R0, R2
+  0x08005852:  9900         LDR        R1, [SP, #0]
+  0x08005854:  F381 8810    MSR        PRIMASK, R1
+  0x08005858:  F3EF 8110    MRS        R1, PRIMASK
+  0x0800585C:  F383 8810    MSR        PRIMASK, R3
+  0x08005860:  05DA         LSLS       R2, R3, #23
+  0x08005862:  6823         LDR        R3, [R4]
+  0x08005864:  689E         LDR        R6, [R3, #8]
+  0x08005866:  4396         BICS       R6, R2
+  0x08005868:  609E         STR        R6, [R3, #8]
+  0x0800586A:  F381 8810    MSR        PRIMASK, R1
+  0x0800586E:  2120         MOVS       R1, #32
+  0x08005870:  6029         STR        R1, [R5]
+  0x08005872:  6822         LDR        R2, [R4]
+
.L1:
+  0x08005874:  6891         LDR        R1, [R2, #8]
+  0x08005876:  0649         LSLS       R1, R1, #25
+  0x08005878:  D506         BPL        .L2                      ; 0x08005888
+  0x0800587A:  2F22         CMP        R7, #34
+  0x0800587C:  D104         BNE        .L2                      ; 0x08005888
+  0x0800587E:  2100         MOVS       R1, #0
+  0x08005880:  8101         STRH       R1, [R0, #8]
+  0x08005882:  4620         MOV        R0, R4
+  0x08005884:  F7FB FE0C    BL         UART_EndRxTransfer       ; 0x080014A0
+
.L2:
+  0x08005888:  68A8         LDR        R0, [R5, #8]
+  0x0800588A:  2110         MOVS       R1, #16
+  0x0800588C:  4301         ORRS       R1, R0
+  0x0800588E:  60A9         STR        R1, [R5, #8]
+  0x08005890:  4620         MOV        R0, R4
+  0x08005892:  F7FE FE8B    BL         HAL_UART_ErrorCallback   ; 0x080045AC
+  0x08005896:  B001         ADD        SP, SP, #4
+  0x08005898:  BDF0         POP        {R4-R7, PC}
+
+

Section .init.WWDG_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
WWDG_IRQHandler:
+  0x0800589A:  E7FE         B          WWDG_IRQHandler          ; 0x0800589A
+
+

Section .init.RTC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
RTC_IRQHandler:
+  0x0800589C:  E7FE         B          RTC_IRQHandler           ; 0x0800589C
+
+

Section .init.FLASH_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
FLASH_IRQHandler:
+  0x0800589E:  E7FE         B          FLASH_IRQHandler         ; 0x0800589E
+
+

Section .init.RCC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
RCC_IRQHandler:
+  0x080058A0:  E7FE         B          RCC_IRQHandler           ; 0x080058A0
+
+

Section .init.EXTI0_1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI0_1_IRQHandler:
+  0x080058A2:  E7FE         B          EXTI0_1_IRQHandler       ; 0x080058A2
+
+

Section .init.EXTI2_3_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI2_3_IRQHandler:
+  0x080058A4:  E7FE         B          EXTI2_3_IRQHandler       ; 0x080058A4
+
+

Section .init.EXTI4_15_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI4_15_IRQHandler:
+  0x080058A6:  E7FE         B          EXTI4_15_IRQHandler      ; 0x080058A6
+
+

Section .init.DMAMUX1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
DMAMUX1_IRQHandler:
+  0x080058A8:  E7FE         B          DMAMUX1_IRQHandler       ; 0x080058A8
+
+

Section .init.ADC1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
ADC1_IRQHandler:
+  0x080058AA:  E7FE         B          ADC1_IRQHandler          ; 0x080058AA
+
+

Section .init.TIM1_BRK_UP_TRG_COM_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM1_BRK_UP_TRG_COM_IRQHandler:
+  0x080058AC:  E7FE         B          TIM1_BRK_UP_TRG_COM_IRQHandler ; 0x080058AC
+
+

Section .init.TIM1_CC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM1_CC_IRQHandler:
+  0x080058AE:  E7FE         B          TIM1_CC_IRQHandler       ; 0x080058AE
+
+

Section .init.TIM3_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM3_IRQHandler:
+  0x080058B0:  E7FE         B          TIM3_IRQHandler          ; 0x080058B0
+
+

Section .init.TIM14_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM14_IRQHandler:
+  0x080058B2:  E7FE         B          TIM14_IRQHandler         ; 0x080058B2
+
+

Section .init.TIM17_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM17_IRQHandler:
+  0x080058B4:  E7FE         B          TIM17_IRQHandler         ; 0x080058B4
+
+

Section .init.I2C1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
I2C1_IRQHandler:
+  0x080058B6:  E7FE         B          I2C1_IRQHandler          ; 0x080058B6
+
+

Section .init.SPI1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
SPI1_IRQHandler:
+  0x080058B8:  E7FE         B          SPI1_IRQHandler          ; 0x080058B8
+
+

Section .init.USART2_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
USART2_IRQHandler:
+  0x080058BA:  E7FE         B          USART2_IRQHandler        ; 0x080058BA
+
+

Section .text.libc.fputc from fileops.o (libc_v6m_t_le_eabi_small.a), size=34, align=2

+
+
fputc:
+  0x080058BC:  B510         PUSH       {R4, LR}
+  0x080058BE:  B082         SUB        SP, SP, #8
+  0x080058C0:  460B         MOV        R3, R1
+  0x080058C2:  AC01         ADD        R4, SP, #4
+  0x080058C4:  7020         STRB       R0, [R4]
+  0x080058C6:  2101         MOVS       R1, #1
+  0x080058C8:  4620         MOV        R0, R4
+  0x080058CA:  460A         MOV        R2, R1
+  0x080058CC:  F000 F807    BL         fwrite                   ; 0x080058DE
+  0x080058D0:  2800         CMP        R0, #0
+  0x080058D2:  D001         BEQ        .L1                      ; 0x080058D8
+  0x080058D4:  7820         LDRB       R0, [R4]
+  0x080058D6:  E000         B          .L2                      ; 0x080058DA
+
.L1:
+  0x080058D8:  43C0         MVNS       R0, R0
+
.L2:
+  0x080058DA:  B002         ADD        SP, SP, #8
+  0x080058DC:  BD10         POP        {R4, PC}
+
+

Section .text.libc.fwrite from fileops.o (libc_v6m_t_le_eabi_small.a), size=50, align=2

+
+
fwrite:
+  0x080058DE:  B5F0         PUSH       {R4-R7, LR}
+  0x080058E0:  B081         SUB        SP, SP, #4
+  0x080058E2:  B40E         PUSH       {R1-R3}
+  0x080058E4:  BC70         POP        {R4-R6}
+  0x080058E6:  4607         MOV        R7, R0
+  0x080058E8:  4618         MOV        R0, R3
+  0x080058EA:  F7FF FE93    BL         __SEGGER_RTL_X_file_stat ; 0x08005614
+  0x080058EE:  4601         MOV        R1, R0
+  0x080058F0:  2000         MOVS       R0, #0
+  0x080058F2:  2900         CMP        R1, #0
+  0x080058F4:  D40A         BMI        .L1                      ; 0x0800590C
+  0x080058F6:  4365         MULS       R5, R4, R5
+  0x080058F8:  42A5         CMP        R5, R4
+  0x080058FA:  D307         BCC        .L1                      ; 0x0800590C
+  0x080058FC:  4630         MOV        R0, R6
+  0x080058FE:  4639         MOV        R1, R7
+  0x08005900:  462A         MOV        R2, R5
+  0x08005902:  F000 F9CD    BL         __SEGGER_RTL_X_file_write ; 0x08005CA0
+  0x08005906:  4621         MOV        R1, R4
+  0x08005908:  F000 FBBB    BL         __aeabi_uidiv            ; 0x08006082
+
.L1:
+  0x0800590C:  B001         ADD        SP, SP, #4
+  0x0800590E:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.__aeabi_fmul from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=182, align=2

+
+
__aeabi_fmul:
+  0x08005910:  B430         PUSH       {R4-R5}
+  0x08005912:  0005         MOVS       R5, R0
+  0x08005914:  404D         EORS       R5, R1
+  0x08005916:  2401         MOVS       R4, #1
+  0x08005918:  07E4         LSLS       R4, R4, #31
+  0x0800591A:  4025         ANDS       R5, R4
+  0x0800591C:  0042         LSLS       R2, R0, #1
+  0x0800591E:  004B         LSLS       R3, R1, #1
+  0x08005920:  0E12         LSRS       R2, R2, #24
+  0x08005922:  D032         BEQ        .L6                      ; 0x0800598A
+  0x08005924:  0E1B         LSRS       R3, R3, #24
+  0x08005926:  D03C         BEQ        .L9                      ; 0x080059A2
+  0x08005928:  2AFF         CMP        R2, #255
+  0x0800592A:  D033         BEQ        .L8                      ; 0x08005994
+  0x0800592C:  2BFF         CMP        R3, #255
+  0x0800592E:  D03F         BEQ        .L11                     ; 0x080059B0
+  0x08005930:  18D2         ADDS       R2, R2, R3
+  0x08005932:  0200         LSLS       R0, R0, #8
+  0x08005934:  4320         ORRS       R0, R4
+  0x08005936:  0A00         LSRS       R0, R0, #8
+  0x08005938:  0209         LSLS       R1, R1, #8
+  0x0800593A:  4321         ORRS       R1, R4
+  0x0800593C:  0A09         LSRS       R1, R1, #8
+  0x0800593E:  B2C4         UXTB       R4, R0
+  0x08005940:  434C         MULS       R4, R1, R4
+  0x08005942:  0A00         LSRS       R0, R0, #8
+  0x08005944:  B2C3         UXTB       R3, R0
+  0x08005946:  434B         MULS       R3, R1, R3
+  0x08005948:  0A00         LSRS       R0, R0, #8
+  0x0800594A:  4348         MULS       R0, R1, R0
+  0x0800594C:  0A21         LSRS       R1, R4, #8
+  0x0800594E:  185B         ADDS       R3, R3, R1
+  0x08005950:  0A19         LSRS       R1, R3, #8
+  0x08005952:  1809         ADDS       R1, R1, R0
+  0x08005954:  D401         BMI        .L1                      ; 0x0800595A
+  0x08005956:  0049         LSLS       R1, R1, #1
+  0x08005958:  1E52         SUBS       R2, R2, #1
+
.L1:
+  0x0800595A:  0A08         LSRS       R0, R1, #8
+  0x0800595C:  3A7F         SUBS       R2, #127
+  0x0800595E:  DB2A         BLT        .L12                     ; 0x080059B6
+  0x08005960:  2AFE         CMP        R2, #254
+  0x08005962:  D20F         BCS        .L5                      ; 0x08005984
+  0x08005964:  05D2         LSLS       R2, R2, #23
+  0x08005966:  431C         ORRS       R4, R3
+  0x08005968:  0624         LSLS       R4, R4, #24
+  0x0800596A:  D001         BEQ        .L2                      ; 0x08005970
+  0x0800596C:  2401         MOVS       R4, #1
+  0x0800596E:  4321         ORRS       R1, R4
+
.L2:
+  0x08005970:  B2C9         UXTB       R1, R1
+  0x08005972:  2980         CMP        R1, #128
+  0x08005974:  4150         ADCS       R0, R2
+  0x08005976:  2980         CMP        R1, #128
+  0x08005978:  D101         BNE        .L3                      ; 0x0800597E
+  0x0800597A:  0840         LSRS       R0, R0, #1
+  0x0800597C:  0040         LSLS       R0, R0, #1
+
.L3:
+  0x0800597E:  4328         ORRS       R0, R5
+
.L4:
+  0x08005980:  BC30         POP        {R4-R5}
+  0x08005982:  4770         BX         LR
+
.L5:
+  0x08005984:  20FF         MOVS       R0, #255
+  0x08005986:  05C0         LSLS       R0, R0, #23
+  0x08005988:  E7F9         B          .L3                      ; 0x0800597E
+
.L6:
+  0x0800598A:  0E1B         LSRS       R3, R3, #24
+  0x0800598C:  2BFF         CMP        R3, #255
+  0x0800598E:  D00A         BEQ        .L10                     ; 0x080059A6
+
.L7:
+  0x08005990:  0028         MOVS       R0, R5
+  0x08005992:  E7F5         B          .L4                      ; 0x08005980
+
.L8:
+  0x08005994:  0240         LSLS       R0, R0, #9
+  0x08005996:  D106         BNE        .L10                     ; 0x080059A6
+  0x08005998:  2BFF         CMP        R3, #255
+  0x0800599A:  D1F3         BNE        .L5                      ; 0x08005984
+  0x0800599C:  0249         LSLS       R1, R1, #9
+  0x0800599E:  D102         BNE        .L10                     ; 0x080059A6
+  0x080059A0:  E7F0         B          .L5                      ; 0x08005984
+
.L9:
+  0x080059A2:  2AFF         CMP        R2, #255
+  0x080059A4:  D1F4         BNE        .L7                      ; 0x08005990
+
.L10:
+  0x080059A6:  207F         MOVS       R0, #127
+  0x080059A8:  0100         LSLS       R0, R0, #4
+  0x080059AA:  300C         ADDS       R0, #12
+  0x080059AC:  0500         LSLS       R0, R0, #20
+  0x080059AE:  E7E7         B          .L4                      ; 0x08005980
+
.L11:
+  0x080059B0:  0249         LSLS       R1, R1, #9
+  0x080059B2:  D1F8         BNE        .L10                     ; 0x080059A6
+  0x080059B4:  E7E6         B          .L5                      ; 0x08005984
+
.L12:
+  0x080059B6:  0243         LSLS       R3, R0, #9
+  0x080059B8:  1C52         ADDS       R2, R2, #1
+  0x080059BA:  D1E9         BNE        .L7                      ; 0x08005990
+  0x080059BC:  125B         ASRS       R3, R3, #9
+  0x080059BE:  1C9B         ADDS       R3, R3, #2
+  0x080059C0:  D9E6         BLS        .L7                      ; 0x08005990
+  0x080059C2:  05D8         LSLS       R0, R3, #23
+  0x080059C4:  E7E4         B          .L7                      ; 0x08005990
+
+

Section .text.libc.__aeabi_dmul_aux from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=394, align=2

+
+
__aeabi_dmul_aux:
+  0x080059C6:  D108         BNE        .L2                      ; 0x080059DA
+  0x080059C8:  2800         CMP        R0, #0
+  0x080059CA:  D106         BNE        .L2                      ; 0x080059DA
+  0x080059CC:  42F5         CMN        R5, R6
+  0x080059CE:  D804         BHI        .L2                      ; 0x080059DA
+  0x080059D0:  D301         BCC        .L1                      ; 0x080059D6
+  0x080059D2:  2A00         CMP        R2, #0
+  0x080059D4:  D101         BNE        .L2                      ; 0x080059DA
+
.L1:
+  0x080059D6:  0D6D         LSRS       R5, R5, #21
+  0x080059D8:  D109         BNE        .L4                      ; 0x080059EE
+
.L2:
+  0x080059DA:  2000         MOVS       R0, #0
+  0x080059DC:  43C1         MVNS       R1, R0
+  0x080059DE:  0D09         LSRS       R1, R1, #20
+  0x080059E0:  04C9         LSLS       R1, R1, #19
+  0x080059E2:  BDF0         POP        {R4-R7, PC}
+
.L3:
+  0x080059E4:  D1F9         BNE        .L2                      ; 0x080059DA
+  0x080059E6:  4212         TST        R2, R2
+  0x080059E8:  D1F7         BNE        .L2                      ; 0x080059DA
+  0x080059EA:  0D64         LSRS       R4, R4, #21
+  0x080059EC:  D0F5         BEQ        .L2                      ; 0x080059DA
+
.L4:
+  0x080059EE:  2000         MOVS       R0, #0
+  0x080059F0:  43C1         MVNS       R1, R0
+  0x080059F2:  0549         LSLS       R1, R1, #21
+  0x080059F4:  0849         LSRS       R1, R1, #1
+  0x080059F6:  E0A6         B          .L7                      ; 0x08005B46
+
.L5:
+  0x080059F8:  2000         MOVS       R0, #0
+  0x080059FA:  4661         MOV        R1, R12
+  0x080059FC:  BDF0         POP        {R4-R7, PC}
+
__aeabi_dmul:
+  0x080059FE:  B5F0         PUSH       {R4-R7, LR}
+  0x08005A00:  2701         MOVS       R7, #1
+  0x08005A02:  07FF         LSLS       R7, R7, #31
+  0x08005A04:  000E         MOVS       R6, R1
+  0x08005A06:  405E         EORS       R6, R3
+  0x08005A08:  403E         ANDS       R6, R7
+  0x08005A0A:  46B4         MOV        R12, R6
+  0x08005A0C:  0ABE         LSRS       R6, R7, #10
+  0x08005A0E:  184C         ADDS       R4, R1, R1
+  0x08005A10:  18DD         ADDS       R5, R3, R3
+  0x08005A12:  42F4         CMN        R4, R6
+  0x08005A14:  D2D7         BCS        __aeabi_dmul_aux         ; 0x080059C6
+  0x08005A16:  42F5         CMN        R5, R6
+  0x08005A18:  D2E4         BCS        .L3                      ; 0x080059E4
+  0x08005A1A:  0D64         LSRS       R4, R4, #21
+  0x08005A1C:  D0EC         BEQ        .L5                      ; 0x080059F8
+  0x08005A1E:  0D6D         LSRS       R5, R5, #21
+  0x08005A20:  D0EA         BEQ        .L5                      ; 0x080059F8
+  0x08005A22:  1964         ADDS       R4, R4, R5
+  0x08005A24:  02C9         LSLS       R1, R1, #11
+  0x08005A26:  4339         ORRS       R1, R7
+  0x08005A28:  0D46         LSRS       R6, R0, #21
+  0x08005A2A:  02C0         LSLS       R0, R0, #11
+  0x08005A2C:  4331         ORRS       R1, R6
+  0x08005A2E:  02DB         LSLS       R3, R3, #11
+  0x08005A30:  433B         ORRS       R3, R7
+  0x08005A32:  0ADB         LSRS       R3, R3, #11
+  0x08005A34:  B410         PUSH       {R4}
+  0x08005A36:  468E         MOV        LR, R1
+  0x08005A38:  B285         UXTH       R5, R0
+  0x08005A3A:  B297         UXTH       R7, R2
+  0x08005A3C:  436F         MULS       R7, R5, R7
+  0x08005A3E:  0C14         LSRS       R4, R2, #16
+  0x08005A40:  436C         MULS       R4, R5, R4
+  0x08005A42:  0C3E         LSRS       R6, R7, #16
+  0x08005A44:  19A4         ADDS       R4, R4, R6
+  0x08005A46:  0C26         LSRS       R6, R4, #16
+  0x08005A48:  0424         LSLS       R4, R4, #16
+  0x08005A4A:  B2BF         UXTH       R7, R7
+  0x08005A4C:  4327         ORRS       R7, R4
+  0x08005A4E:  B29C         UXTH       R4, R3
+  0x08005A50:  436C         MULS       R4, R5, R4
+  0x08005A52:  19A4         ADDS       R4, R4, R6
+  0x08005A54:  0C19         LSRS       R1, R3, #16
+  0x08005A56:  4369         MULS       R1, R5, R1
+  0x08005A58:  0C25         LSRS       R5, R4, #16
+  0x08005A5A:  B2A4         UXTH       R4, R4
+  0x08005A5C:  1949         ADDS       R1, R1, R5
+  0x08005A5E:  040D         LSLS       R5, R1, #16
+  0x08005A60:  0C09         LSRS       R1, R1, #16
+  0x08005A62:  1964         ADDS       R4, R4, R5
+  0x08005A64:  0C00         LSRS       R0, R0, #16
+  0x08005A66:  B295         UXTH       R5, R2
+  0x08005A68:  4345         MULS       R5, R0, R5
+  0x08005A6A:  0C3E         LSRS       R6, R7, #16
+  0x08005A6C:  1976         ADDS       R6, R6, R5
+  0x08005A6E:  4337         ORRS       R7, R6
+  0x08005A70:  B2BF         UXTH       R7, R7
+  0x08005A72:  0C36         LSRS       R6, R6, #16
+  0x08005A74:  0C15         LSRS       R5, R2, #16
+  0x08005A76:  4345         MULS       R5, R0, R5
+  0x08005A78:  19AD         ADDS       R5, R5, R6
+  0x08005A7A:  B2A6         UXTH       R6, R4
+  0x08005A7C:  0C24         LSRS       R4, R4, #16
+  0x08005A7E:  19AD         ADDS       R5, R5, R6
+  0x08005A80:  042E         LSLS       R6, R5, #16
+  0x08005A82:  4337         ORRS       R7, R6
+  0x08005A84:  0C2E         LSRS       R6, R5, #16
+  0x08005A86:  1936         ADDS       R6, R6, R4
+  0x08005A88:  B29D         UXTH       R5, R3
+  0x08005A8A:  4345         MULS       R5, R0, R5
+  0x08005A8C:  19AD         ADDS       R5, R5, R6
+  0x08005A8E:  B2AC         UXTH       R4, R5
+  0x08005A90:  0C2E         LSRS       R6, R5, #16
+  0x08005A92:  1989         ADDS       R1, R1, R6
+  0x08005A94:  0C1D         LSRS       R5, R3, #16
+  0x08005A96:  4345         MULS       R5, R0, R5
+  0x08005A98:  186D         ADDS       R5, R5, R1
+  0x08005A9A:  042E         LSLS       R6, R5, #16
+  0x08005A9C:  0C29         LSRS       R1, R5, #16
+  0x08005A9E:  4334         ORRS       R4, R6
+  0x08005AA0:  4670         MOV        R0, LR
+  0x08005AA2:  B280         UXTH       R0, R0
+  0x08005AA4:  B295         UXTH       R5, R2
+  0x08005AA6:  4345         MULS       R5, R0, R5
+  0x08005AA8:  0C3E         LSRS       R6, R7, #16
+  0x08005AAA:  1976         ADDS       R6, R6, R5
+  0x08005AAC:  4337         ORRS       R7, R6
+  0x08005AAE:  B2BF         UXTH       R7, R7
+  0x08005AB0:  0C36         LSRS       R6, R6, #16
+  0x08005AB2:  0C15         LSRS       R5, R2, #16
+  0x08005AB4:  4345         MULS       R5, R0, R5
+  0x08005AB6:  19AD         ADDS       R5, R5, R6
+  0x08005AB8:  B2A6         UXTH       R6, R4
+  0x08005ABA:  19AD         ADDS       R5, R5, R6
+  0x08005ABC:  0C24         LSRS       R4, R4, #16
+  0x08005ABE:  042E         LSLS       R6, R5, #16
+  0x08005AC0:  4337         ORRS       R7, R6
+  0x08005AC2:  0C2E         LSRS       R6, R5, #16
+  0x08005AC4:  1936         ADDS       R6, R6, R4
+  0x08005AC6:  B29D         UXTH       R5, R3
+  0x08005AC8:  4345         MULS       R5, R0, R5
+  0x08005ACA:  19AD         ADDS       R5, R5, R6
+  0x08005ACC:  B2AC         UXTH       R4, R5
+  0x08005ACE:  0C2E         LSRS       R6, R5, #16
+  0x08005AD0:  1989         ADDS       R1, R1, R6
+  0x08005AD2:  0C1D         LSRS       R5, R3, #16
+  0x08005AD4:  4345         MULS       R5, R0, R5
+  0x08005AD6:  186D         ADDS       R5, R5, R1
+  0x08005AD8:  042E         LSLS       R6, R5, #16
+  0x08005ADA:  4334         ORRS       R4, R6
+  0x08005ADC:  0C29         LSRS       R1, R5, #16
+  0x08005ADE:  4675         MOV        R5, LR
+  0x08005AE0:  0C2D         LSRS       R5, R5, #16
+  0x08005AE2:  B290         UXTH       R0, R2
+  0x08005AE4:  4368         MULS       R0, R5, R0
+  0x08005AE6:  0C3E         LSRS       R6, R7, #16
+  0x08005AE8:  1980         ADDS       R0, R0, R6
+  0x08005AEA:  0406         LSLS       R6, R0, #16
+  0x08005AEC:  B2BF         UXTH       R7, R7
+  0x08005AEE:  433E         ORRS       R6, R7
+  0x08005AF0:  0C07         LSRS       R7, R0, #16
+  0x08005AF2:  B2A0         UXTH       R0, R4
+  0x08005AF4:  183F         ADDS       R7, R7, R0
+  0x08005AF6:  0C12         LSRS       R2, R2, #16
+  0x08005AF8:  436A         MULS       R2, R5, R2
+  0x08005AFA:  19D0         ADDS       R0, R2, R7
+  0x08005AFC:  0C02         LSRS       R2, R0, #16
+  0x08005AFE:  B280         UXTH       R0, R0
+  0x08005B00:  0C24         LSRS       R4, R4, #16
+  0x08005B02:  18A4         ADDS       R4, R4, R2
+  0x08005B04:  B29A         UXTH       R2, R3
+  0x08005B06:  436A         MULS       R2, R5, R2
+  0x08005B08:  1912         ADDS       R2, R2, R4
+  0x08005B0A:  0414         LSLS       R4, R2, #16
+  0x08005B0C:  4320         ORRS       R0, R4
+  0x08005B0E:  0C12         LSRS       R2, R2, #16
+  0x08005B10:  1889         ADDS       R1, R1, R2
+  0x08005B12:  0C1B         LSRS       R3, R3, #16
+  0x08005B14:  436B         MULS       R3, R5, R3
+  0x08005B16:  18C9         ADDS       R1, R1, R3
+  0x08005B18:  BC10         POP        {R4}
+  0x08005B1A:  2701         MOVS       R7, #1
+  0x08005B1C:  053D         LSLS       R5, R7, #20
+  0x08005B1E:  4229         TST        R1, R5
+  0x08005B20:  D103         BNE        .L6                      ; 0x08005B2A
+  0x08005B22:  19B6         ADDS       R6, R6, R6
+  0x08005B24:  4140         ADCS       R0, R0
+  0x08005B26:  4149         ADCS       R1, R1
+  0x08005B28:  1E64         SUBS       R4, R4, #1
+
.L6:
+  0x08005B2A:  07FF         LSLS       R7, R7, #31
+  0x08005B2C:  0D7D         LSRS       R5, R7, #21
+  0x08005B2E:  1E6D         SUBS       R5, R5, #1
+  0x08005B30:  1B64         SUBS       R4, R4, R5
+  0x08005B32:  DB0B         BLT        .L8                      ; 0x08005B4C
+  0x08005B34:  006D         LSLS       R5, R5, #1
+  0x08005B36:  42AC         CMP        R4, R5
+  0x08005B38:  DA09         BGE        .L9                      ; 0x08005B4E
+  0x08005B3A:  0524         LSLS       R4, R4, #20
+  0x08005B3C:  2500         MOVS       R5, #0
+  0x08005B3E:  0842         LSRS       R2, R0, #1
+  0x08005B40:  41BE         SBCS       R6, R7
+  0x08005B42:  4168         ADCS       R0, R5
+  0x08005B44:  4161         ADCS       R1, R4
+
.L7:
+  0x08005B46:  4666         MOV        R6, R12
+  0x08005B48:  4331         ORRS       R1, R6
+  0x08005B4A:  BDF0         POP        {R4-R7, PC}
+
.L8:
+  0x08005B4C:  E754         B          .L5                      ; 0x080059F8
+
.L9:
+  0x08005B4E:  E74E         B          .L4                      ; 0x080059EE
+
+

Section .text.libc.__aeabi_d2uiz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__aeabi_d2uiz:
+  0x08005B50:  004A         LSLS       R2, R1, #1
+  0x08005B52:  D210         BCS        .L1                      ; 0x08005B76
+  0x08005B54:  0D52         LSRS       R2, R2, #21
+  0x08005B56:  2303         MOVS       R3, #3
+  0x08005B58:  021B         LSLS       R3, R3, #8
+  0x08005B5A:  33FF         ADDS       R3, #255
+  0x08005B5C:  1AD2         SUBS       R2, R2, R3
+  0x08005B5E:  D40A         BMI        .L1                      ; 0x08005B76
+  0x08005B60:  4252         RSBS       R2, R2, #0
+  0x08005B62:  321F         ADDS       R2, #31
+  0x08005B64:  D409         BMI        .L2                      ; 0x08005B7A
+  0x08005B66:  0D40         LSRS       R0, R0, #21
+  0x08005B68:  02C9         LSLS       R1, R1, #11
+  0x08005B6A:  4308         ORRS       R0, R1
+  0x08005B6C:  2301         MOVS       R3, #1
+  0x08005B6E:  07DB         LSLS       R3, R3, #31
+  0x08005B70:  4318         ORRS       R0, R3
+  0x08005B72:  40D0         LSRS       R0, R2
+  0x08005B74:  4770         BX         LR
+
.L1:
+  0x08005B76:  2000         MOVS       R0, #0
+  0x08005B78:  4770         BX         LR
+
.L2:
+  0x08005B7A:  17D0         ASRS       R0, R2, #31
+  0x08005B7C:  4770         BX         LR
+
+

Section .text.libc.__aeabi_ui2f from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=30, align=2

+
+
__aeabi_ui2f:
+  0x08005B7E:  229D         MOVS       R2, #157
+  0x08005B80:  0001         MOVS       R1, R0
+  0x08005B82:  D00A         BEQ        .L4                      ; 0x08005B9A
+  0x08005B84:  D402         BMI        .L2                      ; 0x08005B8C
+
.L1:
+  0x08005B86:  1E52         SUBS       R2, R2, #1
+  0x08005B88:  0049         LSLS       R1, R1, #1
+  0x08005B8A:  D5FC         BPL        .L1                      ; 0x08005B86
+
.L2:
+  0x08005B8C:  05D2         LSLS       R2, R2, #23
+  0x08005B8E:  0A08         LSRS       R0, R1, #8
+  0x08005B90:  0609         LSLS       R1, R1, #24
+  0x08005B92:  4149         ADCS       R1, R1
+  0x08005B94:  D300         BCC        .L3                      ; 0x08005B98
+  0x08005B96:  2901         CMP        R1, #1
+
.L3:
+  0x08005B98:  4150         ADCS       R0, R2
+
.L4:
+  0x08005B9A:  4770         BX         LR
+
+

Section .text.libc.__aeabi_lmul from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__aeabi_lmul:
+  0x08005B9C:  B530         PUSH       {R4-R5, LR}
+  0x08005B9E:  4351         MULS       R1, R2, R1
+  0x08005BA0:  4343         MULS       R3, R0, R3
+  0x08005BA2:  185C         ADDS       R4, R3, R1
+  0x08005BA4:  0C01         LSRS       R1, R0, #16
+  0x08005BA6:  0C13         LSRS       R3, R2, #16
+  0x08005BA8:  000D         MOVS       R5, R1
+  0x08005BAA:  435D         MULS       R5, R3, R5
+  0x08005BAC:  1964         ADDS       R4, R4, R5
+  0x08005BAE:  B292         UXTH       R2, R2
+  0x08005BB0:  4351         MULS       R1, R2, R1
+  0x08005BB2:  B280         UXTH       R0, R0
+  0x08005BB4:  4342         MULS       R2, R0, R2
+  0x08005BB6:  0C0D         LSRS       R5, R1, #16
+  0x08005BB8:  0409         LSLS       R1, R1, #16
+  0x08005BBA:  1852         ADDS       R2, R2, R1
+  0x08005BBC:  4165         ADCS       R5, R4
+  0x08005BBE:  4358         MULS       R0, R3, R0
+  0x08005BC0:  0C01         LSRS       R1, R0, #16
+  0x08005BC2:  0400         LSLS       R0, R0, #16
+  0x08005BC4:  1880         ADDS       R0, R0, R2
+  0x08005BC6:  4169         ADCS       R1, R5
+  0x08005BC8:  BD30         POP        {R4-R5, PC}
+
+

Section .text.libc.__aeabi_idiv0 from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=6, align=2

+
+
__aeabi_idiv0:
+  0x08005BCA:  2000         MOVS       R0, #0
+  0x08005BCC:  2100         MOVS       R1, #0
+  0x08005BCE:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_putc from prinops.o (libc_v6m_t_le_eabi_small.a), size=138, align=2

+
+
__SEGGER_RTL_putc:
+  0x08005BD0:  B530         PUSH       {R4-R5, LR}
+  0x08005BD2:  B081         SUB        SP, SP, #4
+  0x08005BD4:  4604         MOV        R4, R0
+  0x08005BD6:  4668         MOV        R0, SP
+  0x08005BD8:  7001         STRB       R1, [R0]
+  0x08005BDA:  6920         LDR        R0, [R4, #16]
+  0x08005BDC:  2800         CMP        R0, #0
+  0x08005BDE:  D00F         BEQ        .L1                      ; 0x08005C00
+  0x08005BE0:  CC0C         LDM        R4!, {R2-R3}
+  0x08005BE2:  3C08         SUBS       R4, #8
+  0x08005BE4:  429A         CMP        R2, R3
+  0x08005BE6:  D233         BCS        .L7                      ; 0x08005C50
+  0x08005BE8:  6962         LDR        R2, [R4, #20]
+  0x08005BEA:  1C53         ADDS       R3, R2, #1
+  0x08005BEC:  6163         STR        R3, [R4, #20]
+  0x08005BEE:  5481         STRB       R1, [R0, R2]
+  0x08005BF0:  69A0         LDR        R0, [R4, #24]
+  0x08005BF2:  6961         LDR        R1, [R4, #20]
+  0x08005BF4:  4281         CMP        R1, R0
+  0x08005BF6:  D12B         BNE        .L7                      ; 0x08005C50
+  0x08005BF8:  4620         MOV        R0, R4
+  0x08005BFA:  F000 F82E    BL         __SEGGER_RTL_prin_flush  ; 0x08005C5A
+  0x08005BFE:  E027         B          .L7                      ; 0x08005C50
+
.L1:
+  0x08005C00:  68E0         LDR        R0, [R4, #12]
+  0x08005C02:  2800         CMP        R0, #0
+  0x08005C04:  D009         BEQ        .L3                      ; 0x08005C1A
+  0x08005C06:  CC0C         LDM        R4!, {R2-R3}
+  0x08005C08:  3C08         SUBS       R4, #8
+  0x08005C0A:  429A         CMP        R2, R3
+  0x08005C0C:  D220         BCS        .L7                      ; 0x08005C50
+  0x08005C0E:  1C55         ADDS       R5, R2, #1
+  0x08005C10:  429D         CMP        R5, R3
+  0x08005C12:  D100         BNE        .L2                      ; 0x08005C16
+  0x08005C14:  2100         MOVS       R1, #0
+
.L2:
+  0x08005C16:  5481         STRB       R1, [R0, R2]
+  0x08005C18:  E01A         B          .L7                      ; 0x08005C50
+
.L3:
+  0x08005C1A:  68A0         LDR        R0, [R4, #8]
+  0x08005C1C:  2800         CMP        R0, #0
+  0x08005C1E:  D008         BEQ        .L4                      ; 0x08005C32
+  0x08005C20:  CC0C         LDM        R4!, {R2-R3}
+  0x08005C22:  3C08         SUBS       R4, #8
+  0x08005C24:  429A         CMP        R2, R3
+  0x08005C26:  D213         BCS        .L7                      ; 0x08005C50
+  0x08005C28:  1C55         ADDS       R5, R2, #1
+  0x08005C2A:  429D         CMP        R5, R3
+  0x08005C2C:  D00D         BEQ        .L5                      ; 0x08005C4A
+  0x08005C2E:  B2C9         UXTB       R1, R1
+  0x08005C30:  E00C         B          .L6                      ; 0x08005C4C
+
.L4:
+  0x08005C32:  6A23         LDR        R3, [R4, #32]
+  0x08005C34:  2B00         CMP        R3, #0
+  0x08005C36:  D00B         BEQ        .L7                      ; 0x08005C50
+  0x08005C38:  CC03         LDM        R4!, {R0-R1}
+  0x08005C3A:  3C08         SUBS       R4, #8
+  0x08005C3C:  4288         CMP        R0, R1
+  0x08005C3E:  D207         BCS        .L7                      ; 0x08005C50
+  0x08005C40:  4669         MOV        R1, SP
+  0x08005C42:  2201         MOVS       R2, #1
+  0x08005C44:  4620         MOV        R0, R4
+  0x08005C46:  4798         BLX        R3
+  0x08005C48:  E002         B          .L7                      ; 0x08005C50
+
.L5:
+  0x08005C4A:  2100         MOVS       R1, #0
+
.L6:
+  0x08005C4C:  0092         LSLS       R2, R2, #2
+  0x08005C4E:  5081         STR        R1, [R0, R2]
+
.L7:
+  0x08005C50:  6820         LDR        R0, [R4]
+  0x08005C52:  1C40         ADDS       R0, R0, #1
+  0x08005C54:  6020         STR        R0, [R4]
+  0x08005C56:  B001         ADD        SP, SP, #4
+  0x08005C58:  BD30         POP        {R4-R5, PC}
+
+

Section .text.libc.__SEGGER_RTL_prin_flush from prinops.o (libc_v6m_t_le_eabi_small.a), size=26, align=2

+
+
__SEGGER_RTL_prin_flush:
+  0x08005C5A:  B510         PUSH       {R4, LR}
+  0x08005C5C:  6942         LDR        R2, [R0, #20]
+  0x08005C5E:  2A00         CMP        R2, #0
+  0x08005C60:  D007         BEQ        .L2                      ; 0x08005C72
+  0x08005C62:  4604         MOV        R4, R0
+  0x08005C64:  6A03         LDR        R3, [R0, #32]
+  0x08005C66:  2B00         CMP        R3, #0
+  0x08005C68:  D001         BEQ        .L1                      ; 0x08005C6E
+  0x08005C6A:  6921         LDR        R1, [R4, #16]
+  0x08005C6C:  4798         BLX        R3
+
.L1:
+  0x08005C6E:  2000         MOVS       R0, #0
+  0x08005C70:  6160         STR        R0, [R4, #20]
+
.L2:
+  0x08005C72:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_init_prin_l from prinops.o (libc_v6m_t_le_eabi_small.a), size=18, align=2

+
+
__SEGGER_RTL_init_prin_l:
+  0x08005C74:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x08005C76:  460C         MOV        R4, R1
+  0x08005C78:  4605         MOV        R5, R0
+  0x08005C7A:  2100         MOVS       R1, #0
+  0x08005C7C:  2224         MOVS       R2, #36
+  0x08005C7E:  F000 FA9A    BL         memset                   ; 0x080061B6
+  0x08005C82:  61EC         STR        R4, [R5, #28]
+  0x08005C84:  BDB0         POP        {R4-R5, R7, PC}
+
+

Section .text.libc.vfprintf from prinops.o (libc_v6m_t_le_eabi_small.a), size=26, align=2

+
+
vfprintf:
+  0x08005C86:  B570         PUSH       {R4-R6, LR}
+  0x08005C88:  4614         MOV        R4, R2
+  0x08005C8A:  460D         MOV        R5, R1
+  0x08005C8C:  4606         MOV        R6, R0
+  0x08005C8E:  F7FF FD51    BL         __SEGGER_RTL_current_locale ; 0x08005734
+  0x08005C92:  4601         MOV        R1, R0
+  0x08005C94:  4630         MOV        R0, R6
+  0x08005C96:  462A         MOV        R2, R5
+  0x08005C98:  4623         MOV        R3, R4
+  0x08005C9A:  F7FF FACD    BL         vfprintf_l               ; 0x08005238
+  0x08005C9E:  BD70         POP        {R4-R6, PC}
+
+

Section .text.libc.__SEGGER_RTL_X_file_write from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=10, align=2

+
+
__SEGGER_RTL_X_file_write:
+  0x08005CA0:  B580         PUSH       {R7, LR}
+  0x08005CA2:  6800         LDR        R0, [R0]
+  0x08005CA4:  F7FF FD2A    BL         SEGGER_RTT_Write         ; 0x080056FC
+  0x08005CA8:  BD80         POP        {R7, PC}
+
+

Section .text.libc._GetAvailWriteSpace from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=22, align=2

+
+
_GetAvailWriteSpace:
+  0x08005CAA:  68C2         LDR        R2, [R0, #12]
+  0x08005CAC:  6901         LDR        R1, [R0, #16]
+  0x08005CAE:  4291         CMP        R1, R2
+  0x08005CB0:  D901         BLS        .L1                      ; 0x08005CB6
+  0x08005CB2:  43D0         MVNS       R0, R2
+  0x08005CB4:  E002         B          .L2                      ; 0x08005CBC
+
.L1:
+  0x08005CB6:  43D2         MVNS       R2, R2
+  0x08005CB8:  1889         ADDS       R1, R1, R2
+  0x08005CBA:  6880         LDR        R0, [R0, #8]
+
.L2:
+  0x08005CBC:  1808         ADDS       R0, R1, R0
+  0x08005CBE:  4770         BX         LR
+
+

Section .text.libc._WriteNoCheck from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=58, align=2

+
+
_WriteNoCheck:
+  0x08005CC0:  B5F0         PUSH       {R4-R7, LR}
+  0x08005CC2:  B081         SUB        SP, SP, #4
+  0x08005CC4:  4615         MOV        R5, R2
+  0x08005CC6:  4604         MOV        R4, R0
+  0x08005CC8:  6840         LDR        R0, [R0, #4]
+  0x08005CCA:  68A2         LDR        R2, [R4, #8]
+  0x08005CCC:  68E6         LDR        R6, [R4, #12]
+  0x08005CCE:  1980         ADDS       R0, R0, R6
+  0x08005CD0:  1B97         SUBS       R7, R2, R6
+  0x08005CD2:  42BD         CMP        R5, R7
+  0x08005CD4:  D204         BCS        .L1                      ; 0x08005CE0
+  0x08005CD6:  462A         MOV        R2, R5
+  0x08005CD8:  F000 F82D    BL         memcpy                   ; 0x08005D36
+  0x08005CDC:  1975         ADDS       R5, R6, R5
+  0x08005CDE:  E009         B          .L2                      ; 0x08005CF4
+
.L1:
+  0x08005CE0:  460E         MOV        R6, R1
+  0x08005CE2:  463A         MOV        R2, R7
+  0x08005CE4:  F000 F827    BL         memcpy                   ; 0x08005D36
+  0x08005CE8:  19F1         ADDS       R1, R6, R7
+  0x08005CEA:  1BED         SUBS       R5, R5, R7
+  0x08005CEC:  6860         LDR        R0, [R4, #4]
+  0x08005CEE:  462A         MOV        R2, R5
+  0x08005CF0:  F000 F821    BL         memcpy                   ; 0x08005D36
+
.L2:
+  0x08005CF4:  60E5         STR        R5, [R4, #12]
+  0x08005CF6:  B001         ADD        SP, SP, #4
+  0x08005CF8:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.memcmp from strops.o (strops_v6m_t_le_eabi_small.a), size=46, align=2

+
+
memcmp:
+  0x08005CFA:  B5F0         PUSH       {R4-R7, LR}
+  0x08005CFC:  2A00         CMP        R2, #0
+  0x08005CFE:  D00D         BEQ        .L2                      ; 0x08005D1C
+  0x08005D00:  1E52         SUBS       R2, R2, #1
+  0x08005D02:  4613         MOV        R3, R2
+  0x08005D04:  4604         MOV        R4, R0
+  0x08005D06:  460D         MOV        R5, R1
+
.L1:
+  0x08005D08:  2B00         CMP        R3, #0
+  0x08005D0A:  D009         BEQ        .L3                      ; 0x08005D20
+  0x08005D0C:  782E         LDRB       R6, [R5]
+  0x08005D0E:  7827         LDRB       R7, [R4]
+  0x08005D10:  42B7         CMP        R7, R6
+  0x08005D12:  D107         BNE        .L4                      ; 0x08005D24
+  0x08005D14:  1E5B         SUBS       R3, R3, #1
+  0x08005D16:  1C6D         ADDS       R5, R5, #1
+  0x08005D18:  1C64         ADDS       R4, R4, #1
+  0x08005D1A:  E7F5         B          .L1                      ; 0x08005D08
+
.L2:
+  0x08005D1C:  2000         MOVS       R0, #0
+  0x08005D1E:  BDF0         POP        {R4-R7, PC}
+
.L3:
+  0x08005D20:  5C8E         LDRB       R6, [R1, R2]
+  0x08005D22:  5C87         LDRB       R7, [R0, R2]
+
.L4:
+  0x08005D24:  1BB8         SUBS       R0, R7, R6
+  0x08005D26:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.strlen from strops.o (strops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
strlen:
+  0x08005D28:  2100         MOVS       R1, #0
+
.L1:
+  0x08005D2A:  5C42         LDRB       R2, [R0, R1]
+  0x08005D2C:  1C49         ADDS       R1, R1, #1
+  0x08005D2E:  2A00         CMP        R2, #0
+  0x08005D30:  D1FB         BNE        .L1                      ; 0x08005D2A
+  0x08005D32:  1E48         SUBS       R0, R1, #1
+  0x08005D34:  4770         BX         LR
+
+

Section .text.libc.memcpy from strasmops_arm.o (strops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
memcpy:
+__aeabi_memcpy:
+__aeabi_memcpy4:
+__aeabi_memcpy8:
+  0x08005D36:  2A00         CMP        R2, #0
+  0x08005D38:  D003         BEQ        .L2                      ; 0x08005D42
+
.L1:
+  0x08005D3A:  1E52         SUBS       R2, R2, #1
+  0x08005D3C:  5C8B         LDRB       R3, [R1, R2]
+  0x08005D3E:  5483         STRB       R3, [R0, R2]
+  0x08005D40:  D1FB         BNE        .L1                      ; 0x08005D3A
+
.L2:
+  0x08005D42:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_mbtowc from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__SEGGER_RTL_ascii_mbtowc:
+  0x08005D44:  B510         PUSH       {R4, LR}
+  0x08005D46:  4604         MOV        R4, R0
+  0x08005D48:  2000         MOVS       R0, #0
+  0x08005D4A:  2900         CMP        R1, #0
+  0x08005D4C:  D010         BEQ        .L3                      ; 0x08005D70
+  0x08005D4E:  2A00         CMP        R2, #0
+  0x08005D50:  D00E         BEQ        .L3                      ; 0x08005D70
+  0x08005D52:  7809         LDRB       R1, [R1]
+  0x08005D54:  B248         SXTB       R0, R1
+  0x08005D56:  2800         CMP        R0, #0
+  0x08005D58:  D408         BMI        .L2                      ; 0x08005D6C
+  0x08005D5A:  2C00         CMP        R4, #0
+  0x08005D5C:  D000         BEQ        .L1                      ; 0x08005D60
+  0x08005D5E:  6021         STR        R1, [R4]
+
.L1:
+  0x08005D60:  2100         MOVS       R1, #0
+  0x08005D62:  6019         STR        R1, [R3]
+  0x08005D64:  6059         STR        R1, [R3, #4]
+  0x08005D66:  1E41         SUBS       R1, R0, #1
+  0x08005D68:  4188         SBCS       R0, R1
+  0x08005D6A:  BD10         POP        {R4, PC}
+
.L2:
+  0x08005D6C:  2001         MOVS       R0, #1
+  0x08005D6E:  43C0         MVNS       R0, R0
+
.L3:
+  0x08005D70:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_ascii_tolower from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
__SEGGER_RTL_ascii_tolower:
+  0x08005D72:  4601         MOV        R1, R0
+  0x08005D74:  3941         SUBS       R1, #65
+  0x08005D76:  291A         CMP        R1, #26
+  0x08005D78:  D201         BCS        .L1                      ; 0x08005D7E
+  0x08005D7A:  2120         MOVS       R1, #32
+  0x08005D7C:  4308         ORRS       R0, R1
+
.L1:
+  0x08005D7E:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_towlower from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
__SEGGER_RTL_ascii_towlower:
+  0x08005D80:  4601         MOV        R1, R0
+  0x08005D82:  3941         SUBS       R1, #65
+  0x08005D84:  291A         CMP        R1, #26
+  0x08005D86:  D201         BCS        .L1                      ; 0x08005D8C
+  0x08005D88:  2120         MOVS       R1, #32
+  0x08005D8A:  4308         ORRS       R0, R1
+
.L1:
+  0x08005D8C:  4770         BX         LR
+
+

Section .text.ADC_DMAConvCplt from PowerPro_lto.o, size=100, align=2

+
+
ADC_DMAConvCplt:
+  0x08005D8E:  B580         PUSH       {R7, LR}
+  0x08005D90:  6A81         LDR        R1, [R0, #40]
+  0x08005D92:  6D8A         LDR        R2, [R1, #88]
+  0x08005D94:  2350         MOVS       R3, #80
+  0x08005D96:  421A         TST        R2, R3
+  0x08005D98:  6D8A         LDR        R2, [R1, #88]
+  0x08005D9A:  D005         BEQ        .L1                      ; 0x08005DA8
+  0x08005D9C:  06D2         LSLS       R2, R2, #27
+  0x08005D9E:  D427         BMI        .L3                      ; 0x08005DF0
+  0x08005DA0:  6D09         LDR        R1, [R1, #80]
+  0x08005DA2:  6B49         LDR        R1, [R1, #52]
+  0x08005DA4:  4788         BLX        R1
+  0x08005DA6:  BD80         POP        {R7, PC}
+
.L1:
+  0x08005DA8:  2001         MOVS       R0, #1
+  0x08005DAA:  0243         LSLS       R3, R0, #9
+  0x08005DAC:  431A         ORRS       R2, R3
+  0x08005DAE:  658A         STR        R2, [R1, #88]
+  0x08005DB0:  680A         LDR        R2, [R1]
+  0x08005DB2:  68D3         LDR        R3, [R2, #12]
+  0x08005DB4:  051B         LSLS       R3, R3, #20
+  0x08005DB6:  0F9B         LSRS       R3, R3, #30
+  0x08005DB8:  D11A         BNE        .L3                      ; 0x08005DF0
+  0x08005DBA:  7E8B         LDRB       R3, [R1, #26]
+  0x08005DBC:  2B00         CMP        R3, #0
+  0x08005DBE:  D117         BNE        .L3                      ; 0x08005DF0
+  0x08005DC0:  6813         LDR        R3, [R2]
+  0x08005DC2:  071B         LSLS       R3, R3, #28
+  0x08005DC4:  D514         BPL        .L3                      ; 0x08005DF0
+  0x08005DC6:  6893         LDR        R3, [R2, #8]
+  0x08005DC8:  075B         LSLS       R3, R3, #29
+  0x08005DCA:  D40A         BMI        .L2                      ; 0x08005DE2
+  0x08005DCC:  6850         LDR        R0, [R2, #4]
+  0x08005DCE:  230C         MOVS       R3, #12
+  0x08005DD0:  4398         BICS       R0, R3
+  0x08005DD2:  6050         STR        R0, [R2, #4]
+  0x08005DD4:  20FF         MOVS       R0, #255
+  0x08005DD6:  3002         ADDS       R0, #2
+  0x08005DD8:  6D8A         LDR        R2, [R1, #88]
+  0x08005DDA:  4382         BICS       R2, R0
+  0x08005DDC:  1C50         ADDS       R0, R2, #1
+  0x08005DDE:  6588         STR        R0, [R1, #88]
+  0x08005DE0:  BD80         POP        {R7, PC}
+
.L2:
+  0x08005DE2:  6D8A         LDR        R2, [R1, #88]
+  0x08005DE4:  2320         MOVS       R3, #32
+  0x08005DE6:  4313         ORRS       R3, R2
+  0x08005DE8:  658B         STR        R3, [R1, #88]
+  0x08005DEA:  6DCA         LDR        R2, [R1, #92]
+  0x08005DEC:  4302         ORRS       R2, R0
+  0x08005DEE:  65CA         STR        R2, [R1, #92]
+
.L3:
+  0x08005DF0:  BD80         POP        {R7, PC}
+
+

Section .text.ADC_DMAError from PowerPro_lto.o, size=20, align=2

+
+
ADC_DMAError:
+  0x08005DF2:  6A80         LDR        R0, [R0, #40]
+  0x08005DF4:  6D81         LDR        R1, [R0, #88]
+  0x08005DF6:  2240         MOVS       R2, #64
+  0x08005DF8:  430A         ORRS       R2, R1
+  0x08005DFA:  6582         STR        R2, [R0, #88]
+  0x08005DFC:  6DC1         LDR        R1, [R0, #92]
+  0x08005DFE:  2204         MOVS       R2, #4
+  0x08005E00:  430A         ORRS       R2, R1
+  0x08005E02:  65C2         STR        R2, [R0, #92]
+  0x08005E04:  4770         BX         LR
+
+

Section .text.HAL_NVIC_SystemReset from PowerPro_lto.o, size=4, align=2

+
+
HAL_NVIC_SystemReset:
+  0x08005E06:  F7FA FD8F    BL         __NVIC_SystemReset       ; 0x08000928
+
+

Section .text.UART_DMAReceiveCplt from PowerPro_lto.o, size=168, align=2

+
+
UART_DMAReceiveCplt:
+  0x08005E0A:  B5F0         PUSH       {R4-R7, LR}
+  0x08005E0C:  B082         SUB        SP, SP, #8
+  0x08005E0E:  6A82         LDR        R2, [R0, #40]
+  0x08005E10:  4611         MOV        R1, R2
+  0x08005E12:  315C         ADDS       R1, #92
+  0x08005E14:  6803         LDR        R3, [R0]
+  0x08005E16:  681B         LDR        R3, [R3]
+  0x08005E18:  069B         LSLS       R3, R3, #26
+  0x08005E1A:  D43A         BMI        .L1                      ; 0x08005E92
+  0x08005E1C:  4614         MOV        R4, R2
+  0x08005E1E:  348C         ADDS       R4, #140
+  0x08005E20:  2300         MOVS       R3, #0
+  0x08005E22:  804B         STRH       R3, [R1, #2]
+  0x08005E24:  F3EF 8310    MRS        R3, PRIMASK
+  0x08005E28:  9300         STR        R3, [SP, #0]
+  0x08005E2A:  2301         MOVS       R3, #1
+  0x08005E2C:  F383 8810    MSR        PRIMASK, R3
+  0x08005E30:  9001         STR        R0, [SP, #4]
+  0x08005E32:  021E         LSLS       R6, R3, #8
+  0x08005E34:  6817         LDR        R7, [R2]
+  0x08005E36:  683D         LDR        R5, [R7]
+  0x08005E38:  43B5         BICS       R5, R6
+  0x08005E3A:  603D         STR        R5, [R7]
+  0x08005E3C:  9800         LDR        R0, [SP, #0]
+  0x08005E3E:  F380 8810    MSR        PRIMASK, R0
+  0x08005E42:  F3EF 8010    MRS        R0, PRIMASK
+  0x08005E46:  F383 8810    MSR        PRIMASK, R3
+  0x08005E4A:  6815         LDR        R5, [R2]
+  0x08005E4C:  68AE         LDR        R6, [R5, #8]
+  0x08005E4E:  439E         BICS       R6, R3
+  0x08005E50:  60AE         STR        R6, [R5, #8]
+  0x08005E52:  F380 8810    MSR        PRIMASK, R0
+  0x08005E56:  F3EF 8010    MRS        R0, PRIMASK
+  0x08005E5A:  9000         STR        R0, [SP, #0]
+  0x08005E5C:  F383 8810    MSR        PRIMASK, R3
+  0x08005E60:  6815         LDR        R5, [R2]
+  0x08005E62:  68AE         LDR        R6, [R5, #8]
+  0x08005E64:  2740         MOVS       R7, #64
+  0x08005E66:  43BE         BICS       R6, R7
+  0x08005E68:  60AE         STR        R6, [R5, #8]
+  0x08005E6A:  9801         LDR        R0, [SP, #4]
+  0x08005E6C:  9D00         LDR        R5, [SP, #0]
+  0x08005E6E:  F385 8810    MSR        PRIMASK, R5
+  0x08005E72:  2520         MOVS       R5, #32
+  0x08005E74:  6025         STR        R5, [R4]
+  0x08005E76:  6ED4         LDR        R4, [R2, #108]
+  0x08005E78:  2C01         CMP        R4, #1
+  0x08005E7A:  D10A         BNE        .L1                      ; 0x08005E92
+  0x08005E7C:  F3EF 8610    MRS        R6, PRIMASK
+  0x08005E80:  F383 8810    MSR        PRIMASK, R3
+  0x08005E84:  6813         LDR        R3, [R2]
+  0x08005E86:  681C         LDR        R4, [R3]
+  0x08005E88:  2510         MOVS       R5, #16
+  0x08005E8A:  43AC         BICS       R4, R5
+  0x08005E8C:  601C         STR        R4, [R3]
+  0x08005E8E:  F386 8810    MSR        PRIMASK, R6
+
.L1:
+  0x08005E92:  2300         MOVS       R3, #0
+  0x08005E94:  6713         STR        R3, [R2, #112]
+  0x08005E96:  6ED2         LDR        R2, [R2, #108]
+  0x08005E98:  2A01         CMP        R2, #1
+  0x08005E9A:  D108         BNE        .L3                      ; 0x08005EAE
+  0x08005E9C:  804B         STRH       R3, [R1, #2]
+  0x08005E9E:  880A         LDRH       R2, [R1]
+  0x08005EA0:  6800         LDR        R0, [R0]
+  0x08005EA2:  6840         LDR        R0, [R0, #4]
+  0x08005EA4:  B283         UXTH       R3, R0
+  0x08005EA6:  4293         CMP        R3, R2
+  0x08005EA8:  D200         BCS        .L2                      ; 0x08005EAC
+  0x08005EAA:  8048         STRH       R0, [R1, #2]
+
.L2:
+  0x08005EAC:  8848         LDRH       R0, [R1, #2]
+
.L3:
+  0x08005EAE:  B002         ADD        SP, SP, #8
+  0x08005EB0:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.UART_DMARxHalfCplt from PowerPro_lto.o, size=36, align=2

+
+
UART_DMARxHalfCplt:
+  0x08005EB2:  6A81         LDR        R1, [R0, #40]
+  0x08005EB4:  2201         MOVS       R2, #1
+  0x08005EB6:  670A         STR        R2, [R1, #112]
+  0x08005EB8:  6ECA         LDR        R2, [R1, #108]
+  0x08005EBA:  2A01         CMP        R2, #1
+  0x08005EBC:  D10A         BNE        .L2                      ; 0x08005ED4
+  0x08005EBE:  315C         ADDS       R1, #92
+  0x08005EC0:  880A         LDRH       R2, [R1]
+  0x08005EC2:  0853         LSRS       R3, R2, #1
+  0x08005EC4:  804B         STRH       R3, [R1, #2]
+  0x08005EC6:  6800         LDR        R0, [R0]
+  0x08005EC8:  6840         LDR        R0, [R0, #4]
+  0x08005ECA:  B283         UXTH       R3, R0
+  0x08005ECC:  4293         CMP        R3, R2
+  0x08005ECE:  D800         BHI        .L1                      ; 0x08005ED2
+  0x08005ED0:  8048         STRH       R0, [R1, #2]
+
.L1:
+  0x08005ED2:  8848         LDRH       R0, [R1, #2]
+
.L2:
+  0x08005ED4:  4770         BX         LR
+
+

Section .text.UART_DMAAbortOnError from PowerPro_lto.o, size=16, align=2

+
+
UART_DMAAbortOnError:
+  0x08005ED6:  B580         PUSH       {R7, LR}
+  0x08005ED8:  6A80         LDR        R0, [R0, #40]
+  0x08005EDA:  215E         MOVS       R1, #94
+  0x08005EDC:  2200         MOVS       R2, #0
+  0x08005EDE:  5242         STRH       R2, [R0, R1]
+  0x08005EE0:  F7FE FB64    BL         HAL_UART_ErrorCallback   ; 0x080045AC
+  0x08005EE4:  BD80         POP        {R7, PC}
+
+

Section .text.Error_Handler from PowerPro_lto.o, size=4, align=2

+
+
Error_Handler:
+  0x08005EE6:  B672         CPSID      i
+
.L1:
+  0x08005EE8:  E7FE         B          .L1                      ; 0x08005EE8
+
+

Section .rodata.UARTPrescTable from PowerPro_lto.o, size=24, align=2

+
+
UARTPrescTable:
+  0x08005EEA:  01           DC.B       0x01                     ; '\x01'
+  0x08005EEB:  00           DC.B       0x00                     ; '\0'
+  0x08005EEC:  02           DC.B       0x02                     ; '\x02'
+  0x08005EED:  00           DC.B       0x00                     ; '\0'
+  0x08005EEE:  04           DC.B       0x04                     ; '\x04'
+  0x08005EEF:  00           DC.B       0x00                     ; '\0'
+  0x08005EF0:  06           DC.B       0x06                     ; '\x06'
+  0x08005EF1:  00           DC.B       0x00                     ; '\0'
+  0x08005EF2:  08           DC.B       0x08                     ; '\b'
+  0x08005EF3:  00           DC.B       0x00                     ; '\0'
+  0x08005EF4:  0A           DC.B       0x0A                     ; '\n'
+  0x08005EF5:  00           DC.B       0x00                     ; '\0'
+  0x08005EF6:  0C           DC.B       0x0C                     ; '\x0C'
+  0x08005EF7:  00           DC.B       0x00                     ; '\0'
+  0x08005EF8:  10           DC.B       0x10                     ; '\x10'
+  0x08005EF9:  00           DC.B       0x00                     ; '\0'
+  0x08005EFA:  20           DC.B       0x20                     ; ' '
+  0x08005EFB:  00           DC.B       0x00                     ; '\0'
+  0x08005EFC:  40           DC.B       0x40                     ; '@'
+  0x08005EFD:  00           DC.B       0x00                     ; '\0'
+  0x08005EFE:  80           DC.B       0x80                     ; '\x80'
+  0x08005EFF:  00           DC.B       0x00                     ; '\0'
+  0x08005F00:  00           DC.B       0x00                     ; '\0'
+  0x08005F01:  01           DC.B       0x01                     ; '\x01'
+
+

Section .init.Reset_Handler from STM32C0xx_Startup.o, size=8, align=2

+
+
reset_handler:
+Reset_Handler:
+  0x08005F02:  F7FA FB77    BL         SystemInit               ; 0x080005F4
+  0x08005F06:  F7FF F961    BL         _start                   ; 0x080051CC
+
+

Section .text.libc.__aeabi_ddiv from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=196, align=2

+
+
__aeabi_ddiv:
+  0x08005F0A:  B4F0         PUSH       {R4-R7}
+  0x08005F0C:  2501         MOVS       R5, #1
+  0x08005F0E:  07ED         LSLS       R5, R5, #31
+  0x08005F10:  000C         MOVS       R4, R1
+  0x08005F12:  405C         EORS       R4, R3
+  0x08005F14:  402C         ANDS       R4, R5
+  0x08005F16:  46A4         MOV        R12, R4
+  0x08005F18:  0AAE         LSRS       R6, R5, #10
+  0x08005F1A:  184C         ADDS       R4, R1, R1
+  0x08005F1C:  18DF         ADDS       R7, R3, R3
+  0x08005F1E:  42F4         CMN        R4, R6
+  0x08005F20:  D23D         BCS        .L8                      ; 0x08005F9E
+  0x08005F22:  42F7         CMN        R7, R6
+  0x08005F24:  D245         BCS        .L10                     ; 0x08005FB2
+  0x08005F26:  0D64         LSRS       R4, R4, #21
+  0x08005F28:  D04C         BEQ        .L12                     ; 0x08005FC4
+  0x08005F2A:  0D7F         LSRS       R7, R7, #21
+  0x08005F2C:  D03C         BEQ        .L9                      ; 0x08005FA8
+  0x08005F2E:  1BE4         SUBS       R4, R4, R7
+  0x08005F30:  02C9         LSLS       R1, R1, #11
+  0x08005F32:  4329         ORRS       R1, R5
+  0x08005F34:  0ACF         LSRS       R7, R1, #11
+  0x08005F36:  02DB         LSLS       R3, R3, #11
+  0x08005F38:  432B         ORRS       R3, R5
+  0x08005F3A:  0ADB         LSRS       R3, R3, #11
+  0x08005F3C:  0006         MOVS       R6, R0
+  0x08005F3E:  1AB6         SUBS       R6, R6, R2
+  0x08005F40:  419F         SBCS       R7, R3
+  0x08005F42:  D204         BCS        .L1                      ; 0x08005F4E
+  0x08005F44:  1E64         SUBS       R4, R4, #1
+  0x08005F46:  19B6         ADDS       R6, R6, R6
+  0x08005F48:  417F         ADCS       R7, R7
+  0x08005F4A:  18B6         ADDS       R6, R6, R2
+  0x08005F4C:  415F         ADCS       R7, R3
+
.L1:
+  0x08005F4E:  1268         ASRS       R0, R5, #9
+  0x08005F50:  0D80         LSRS       R0, R0, #22
+  0x08005F52:  1824         ADDS       R4, R4, R0
+  0x08005F54:  DD38         BLE        .L13                     ; 0x08005FC8
+  0x08005F56:  1800         ADDS       R0, R0, R0
+  0x08005F58:  4284         CMP        R4, R0
+  0x08005F5A:  D825         BHI        .L9                      ; 0x08005FA8
+  0x08005F5C:  0CE8         LSRS       R0, R5, #19
+  0x08005F5E:  2100         MOVS       R1, #0
+
.L2:
+  0x08005F60:  19B6         ADDS       R6, R6, R6
+  0x08005F62:  417F         ADCS       R7, R7
+  0x08005F64:  1AB6         SUBS       R6, R6, R2
+  0x08005F66:  419F         SBCS       R7, R3
+  0x08005F68:  D303         BCC        .L3                      ; 0x08005F72
+  0x08005F6A:  4140         ADCS       R0, R0
+  0x08005F6C:  4149         ADCS       R1, R1
+  0x08005F6E:  D3F7         BCC        .L2                      ; 0x08005F60
+  0x08005F70:  E004         B          .L4                      ; 0x08005F7C
+
.L3:
+  0x08005F72:  18B6         ADDS       R6, R6, R2
+  0x08005F74:  415F         ADCS       R7, R3
+  0x08005F76:  1800         ADDS       R0, R0, R0
+  0x08005F78:  4149         ADCS       R1, R1
+  0x08005F7A:  D3F1         BCC        .L2                      ; 0x08005F60
+
.L4:
+  0x08005F7C:  0524         LSLS       R4, R4, #20
+  0x08005F7E:  19B6         ADDS       R6, R6, R6
+  0x08005F80:  417F         ADCS       R7, R7
+  0x08005F82:  1AB6         SUBS       R6, R6, R2
+  0x08005F84:  419F         SBCS       R7, R3
+  0x08005F86:  D305         BCC        .L5                      ; 0x08005F94
+  0x08005F88:  4337         ORRS       R7, R6
+  0x08005F8A:  07C2         LSLS       R2, R0, #31
+  0x08005F8C:  4317         ORRS       R7, R2
+  0x08005F8E:  2200         MOVS       R2, #0
+  0x08005F90:  2F01         CMP        R7, #1
+  0x08005F92:  4150         ADCS       R0, R2
+
.L5:
+  0x08005F94:  4161         ADCS       R1, R4
+
.L6:
+  0x08005F96:  4662         MOV        R2, R12
+  0x08005F98:  4311         ORRS       R1, R2
+
.L7:
+  0x08005F9A:  BCF0         POP        {R4-R7}
+  0x08005F9C:  4770         BX         LR
+
.L8:
+  0x08005F9E:  D10C         BNE        .L11                     ; 0x08005FBA
+  0x08005FA0:  2800         CMP        R0, #0
+  0x08005FA2:  D10A         BNE        .L11                     ; 0x08005FBA
+  0x08005FA4:  42F7         CMN        R7, R6
+  0x08005FA6:  D208         BCS        .L11                     ; 0x08005FBA
+
.L9:
+  0x08005FA8:  2000         MOVS       R0, #0
+  0x08005FAA:  43C1         MVNS       R1, R0
+  0x08005FAC:  0D49         LSRS       R1, R1, #21
+  0x08005FAE:  0509         LSLS       R1, R1, #20
+  0x08005FB0:  E7F1         B          .L6                      ; 0x08005F96
+
.L10:
+  0x08005FB2:  2A00         CMP        R2, #0
+  0x08005FB4:  D101         BNE        .L11                     ; 0x08005FBA
+  0x08005FB6:  42F7         CMN        R7, R6
+  0x08005FB8:  D006         BEQ        .L13                     ; 0x08005FC8
+
.L11:
+  0x08005FBA:  2000         MOVS       R0, #0
+  0x08005FBC:  43C1         MVNS       R1, R0
+  0x08005FBE:  0D09         LSRS       R1, R1, #20
+  0x08005FC0:  04C9         LSLS       R1, R1, #19
+  0x08005FC2:  E7EA         B          .L7                      ; 0x08005F9A
+
.L12:
+  0x08005FC4:  0D7F         LSRS       R7, R7, #21
+  0x08005FC6:  D0F8         BEQ        .L11                     ; 0x08005FBA
+
.L13:
+  0x08005FC8:  2000         MOVS       R0, #0
+  0x08005FCA:  4661         MOV        R1, R12
+  0x08005FCC:  E7E5         B          .L7                      ; 0x08005F9A
+
+

Section .text.libc.__aeabi_d2iz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=52, align=2

+
+
__aeabi_d2iz:
+  0x08005FCE:  46F4         MOV        R12, LR
+  0x08005FD0:  184A         ADDS       R2, R1, R1
+  0x08005FD2:  D205         BCS        .L2                      ; 0x08005FE0
+  0x08005FD4:  F7FF FDBE    BL         0x08005B54               ; 0x08005B55 = .text.libc.__aeabi_d2uiz+5
+  0x08005FD8:  D501         BPL        .L1                      ; 0x08005FDE
+  0x08005FDA:  17C0         ASRS       R0, R0, #31
+  0x08005FDC:  0840         LSRS       R0, R0, #1
+
.L1:
+  0x08005FDE:  4760         BX         R12
+
.L2:
+  0x08005FE0:  2301         MOVS       R3, #1
+  0x08005FE2:  055B         LSLS       R3, R3, #21
+  0x08005FE4:  42D3         CMN        R3, R2
+  0x08005FE6:  D206         BCS        .L5                      ; 0x08005FF6
+
.L3:
+  0x08005FE8:  F7FF FDB4    BL         0x08005B54               ; 0x08005B55 = .text.libc.__aeabi_d2uiz+5
+  0x08005FEC:  D501         BPL        .L4                      ; 0x08005FF2
+  0x08005FEE:  2001         MOVS       R0, #1
+  0x08005FF0:  07C0         LSLS       R0, R0, #31
+
.L4:
+  0x08005FF2:  4240         RSBS       R0, R0, #0
+  0x08005FF4:  4760         BX         R12
+
.L5:
+  0x08005FF6:  D101         BNE        .L6                      ; 0x08005FFC
+  0x08005FF8:  4200         TST        R0, R0
+  0x08005FFA:  D0F5         BEQ        .L3                      ; 0x08005FE8
+
.L6:
+  0x08005FFC:  17D0         ASRS       R0, R2, #31
+  0x08005FFE:  0840         LSRS       R0, R0, #1
+  0x08006000:  4770         BX         LR
+
+

Section .text.libc.__aeabi_f2uiz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=36, align=2

+
+
__aeabi_f2uiz:
+  0x08006002:  0041         LSLS       R1, R0, #1
+  0x08006004:  D20D         BCS        .L2                      ; 0x08006022
+  0x08006006:  0E09         LSRS       R1, R1, #24
+  0x08006008:  397F         SUBS       R1, #127
+  0x0800600A:  D40A         BMI        .L2                      ; 0x08006022
+  0x0800600C:  4249         RSBS       R1, R1, #0
+  0x0800600E:  311F         ADDS       R1, #31
+  0x08006010:  D405         BMI        .L1                      ; 0x0800601E
+  0x08006012:  0200         LSLS       R0, R0, #8
+  0x08006014:  2201         MOVS       R2, #1
+  0x08006016:  07D2         LSLS       R2, R2, #31
+  0x08006018:  4310         ORRS       R0, R2
+  0x0800601A:  40C8         LSRS       R0, R1
+  0x0800601C:  4770         BX         LR
+
.L1:
+  0x0800601E:  17C8         ASRS       R0, R1, #31
+  0x08006020:  4770         BX         LR
+
.L2:
+  0x08006022:  2000         MOVS       R0, #0
+  0x08006024:  4770         BX         LR
+
+

Section .text.libc.__aeabi_ui2d from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=28, align=2

+
+
__aeabi_ui2d:
+  0x08006026:  2242         MOVS       R2, #66
+  0x08006028:  0112         LSLS       R2, R2, #4
+  0x0800602A:  1ED2         SUBS       R2, R2, #3
+  0x0800602C:  0001         MOVS       R1, R0
+  0x0800602E:  D007         BEQ        .L3                      ; 0x08006040
+  0x08006030:  D402         BMI        .L2                      ; 0x08006038
+
.L1:
+  0x08006032:  1E52         SUBS       R2, R2, #1
+  0x08006034:  1800         ADDS       R0, R0, R0
+  0x08006036:  D5FC         BPL        .L1                      ; 0x08006032
+
.L2:
+  0x08006038:  0512         LSLS       R2, R2, #20
+  0x0800603A:  0AC3         LSRS       R3, R0, #11
+  0x0800603C:  0540         LSLS       R0, R0, #21
+  0x0800603E:  1899         ADDS       R1, R3, R2
+
.L3:
+  0x08006040:  4770         BX         LR
+
+

Section .text.libc.__aeabi_idiv from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=64, align=2

+
+
__aeabi_idiv:
+  0x08006042:  17CA         ASRS       R2, R1, #31
+  0x08006044:  4051         EORS       R1, R2
+  0x08006046:  1A8B         SUBS       R3, R1, R2
+  0x08006048:  D017         BEQ        .L6                      ; 0x0800607A
+  0x0800604A:  17C1         ASRS       R1, R0, #31
+  0x0800604C:  404A         EORS       R2, R1
+  0x0800604E:  4694         MOV        R12, R2
+  0x08006050:  4048         EORS       R0, R1
+  0x08006052:  1A41         SUBS       R1, R0, R1
+  0x08006054:  0848         LSRS       R0, R1, #1
+  0x08006056:  001A         MOVS       R2, R3
+  0x08006058:  E000         B          .L2                      ; 0x0800605C
+
.L1:
+  0x0800605A:  0052         LSLS       R2, R2, #1
+
.L2:
+  0x0800605C:  4282         CMP        R2, R0
+  0x0800605E:  D9FC         BLS        .L1                      ; 0x0800605A
+  0x08006060:  2000         MOVS       R0, #0
+  0x08006062:  E000         B          .L4                      ; 0x08006066
+
.L3:
+  0x08006064:  0852         LSRS       R2, R2, #1
+
.L4:
+  0x08006066:  4291         CMP        R1, R2
+  0x08006068:  D300         BCC        .L5                      ; 0x0800606C
+  0x0800606A:  1A89         SUBS       R1, R1, R2
+
.L5:
+  0x0800606C:  4140         ADCS       R0, R0
+  0x0800606E:  429A         CMP        R2, R3
+  0x08006070:  D1F8         BNE        .L3                      ; 0x08006064
+  0x08006072:  4662         MOV        R2, R12
+  0x08006074:  4050         EORS       R0, R2
+  0x08006076:  1A80         SUBS       R0, R0, R2
+  0x08006078:  4770         BX         LR
+
.L6:
+  0x0800607A:  B510         PUSH       {R4, LR}
+  0x0800607C:  F7FF FDA5    BL         __aeabi_idiv0            ; 0x08005BCA
+  0x08006080:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__aeabi_uidiv from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=56, align=2

+
+
__aeabi_uidiv:
+  0x08006082:  000A         MOVS       R2, R1
+  0x08006084:  D015         BEQ        .L8                      ; 0x080060B2
+  0x08006086:  0003         MOVS       R3, R0
+  0x08006088:  0840         LSRS       R0, R0, #1
+  0x0800608A:  E000         B          .L2                      ; 0x0800608E
+
.L1:
+  0x0800608C:  0052         LSLS       R2, R2, #1
+
.L2:
+  0x0800608E:  4282         CMP        R2, R0
+  0x08006090:  D9FC         BLS        .L1                      ; 0x0800608C
+  0x08006092:  2000         MOVS       R0, #0
+  0x08006094:  E000         B          .L4                      ; 0x08006098
+
.L3:
+  0x08006096:  0852         LSRS       R2, R2, #1
+
.L4:
+  0x08006098:  1A9B         SUBS       R3, R3, R2
+  0x0800609A:  D306         BCC        .L7                      ; 0x080060AA
+
.L5:
+  0x0800609C:  4140         ADCS       R0, R0
+  0x0800609E:  428A         CMP        R2, R1
+  0x080060A0:  D1F9         BNE        .L3                      ; 0x08006096
+  0x080060A2:  4770         BX         LR
+
.L6:
+  0x080060A4:  0852         LSRS       R2, R2, #1
+  0x080060A6:  189B         ADDS       R3, R3, R2
+  0x080060A8:  D2F8         BCS        .L5                      ; 0x0800609C
+
.L7:
+  0x080060AA:  1800         ADDS       R0, R0, R0
+  0x080060AC:  428A         CMP        R2, R1
+  0x080060AE:  D1F9         BNE        .L6                      ; 0x080060A4
+  0x080060B0:  4770         BX         LR
+
.L8:
+  0x080060B2:  B510         PUSH       {R4, LR}
+  0x080060B4:  F7FF FD89    BL         __aeabi_idiv0            ; 0x08005BCA
+  0x080060B8:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__aeabi_uldivmod from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=136, align=2

+
+
__aeabi_uldivmod:
+  0x080060BA:  B470         PUSH       {R4-R6}
+  0x080060BC:  2400         MOVS       R4, #0
+  0x080060BE:  2501         MOVS       R5, #1
+  0x080060C0:  07ED         LSLS       R5, R5, #31
+  0x080060C2:  2B00         CMP        R3, #0
+  0x080060C4:  D107         BNE        .L1                      ; 0x080060D6
+  0x080060C6:  2900         CMP        R1, #0
+  0x080060C8:  D005         BEQ        .L1                      ; 0x080060D6
+  0x080060CA:  4283         CMP        R3, R0
+  0x080060CC:  D203         BCS        .L1                      ; 0x080060D6
+  0x080060CE:  0013         MOVS       R3, R2
+  0x080060D0:  2200         MOVS       R2, #0
+  0x080060D2:  002C         MOVS       R4, R5
+  0x080060D4:  2500         MOVS       R5, #0
+
.L1:
+  0x080060D6:  2600         MOVS       R6, #0
+
.L2:
+  0x080060D8:  19A4         ADDS       R4, R4, R6
+  0x080060DA:  4299         CMP        R1, R3
+  0x080060DC:  D100         BNE        .L3                      ; 0x080060E0
+  0x080060DE:  4290         CMP        R0, R2
+
.L3:
+  0x080060E0:  D912         BLS        .L6                      ; 0x08006108
+  0x080060E2:  1892         ADDS       R2, R2, R2
+  0x080060E4:  415B         ADCS       R3, R3
+  0x080060E6:  D203         BCS        .L4                      ; 0x080060F0
+  0x080060E8:  07EE         LSLS       R6, R5, #31
+  0x080060EA:  086D         LSRS       R5, R5, #1
+  0x080060EC:  0864         LSRS       R4, R4, #1
+  0x080060EE:  E7F3         B          .L2                      ; 0x080060D8
+
.L4:
+  0x080060F0:  07DE         LSLS       R6, R3, #31
+  0x080060F2:  085B         LSRS       R3, R3, #1
+  0x080060F4:  0852         LSRS       R2, R2, #1
+  0x080060F6:  1992         ADDS       R2, R2, R6
+  0x080060F8:  2601         MOVS       R6, #1
+  0x080060FA:  07F6         LSLS       R6, R6, #31
+  0x080060FC:  199B         ADDS       R3, R3, R6
+  0x080060FE:  E003         B          .L6                      ; 0x08006108
+
.L5:
+  0x08006100:  07DE         LSLS       R6, R3, #31
+  0x08006102:  085B         LSRS       R3, R3, #1
+  0x08006104:  0852         LSRS       R2, R2, #1
+  0x08006106:  1992         ADDS       R2, R2, R6
+
.L6:
+  0x08006108:  1A80         SUBS       R0, R0, R2
+  0x0800610A:  4199         SBCS       R1, R3
+  0x0800610C:  D303         BCC        .L7                      ; 0x08006116
+  0x0800610E:  4164         ADCS       R4, R4
+  0x08006110:  416D         ADCS       R5, R5
+  0x08006112:  D3F5         BCC        .L5                      ; 0x08006100
+  0x08006114:  E00F         B          .L9                      ; 0x08006136
+
.L7:
+  0x08006116:  1924         ADDS       R4, R4, R4
+  0x08006118:  416D         ADCS       R5, R5
+  0x0800611A:  D20A         BCS        .L8                      ; 0x08006132
+  0x0800611C:  07DE         LSLS       R6, R3, #31
+  0x0800611E:  085B         LSRS       R3, R3, #1
+  0x08006120:  0852         LSRS       R2, R2, #1
+  0x08006122:  1992         ADDS       R2, R2, R6
+  0x08006124:  1880         ADDS       R0, R0, R2
+  0x08006126:  4159         ADCS       R1, R3
+  0x08006128:  D3F5         BCC        .L7                      ; 0x08006116
+  0x0800612A:  4164         ADCS       R4, R4
+  0x0800612C:  416D         ADCS       R5, R5
+  0x0800612E:  D3E7         BCC        .L5                      ; 0x08006100
+  0x08006130:  E001         B          .L9                      ; 0x08006136
+
.L8:
+  0x08006132:  1880         ADDS       R0, R0, R2
+  0x08006134:  4159         ADCS       R1, R3
+
.L9:
+  0x08006136:  0002         MOVS       R2, R0
+  0x08006138:  000B         MOVS       R3, R1
+  0x0800613A:  0020         MOVS       R0, R4
+  0x0800613C:  0029         MOVS       R1, R5
+  0x0800613E:  BC70         POP        {R4-R6}
+  0x08006140:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_stream_write from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=2

+
+
__SEGGER_RTL_stream_write:
+  0x08006142:  B510         PUSH       {R4, LR}
+  0x08006144:  460C         MOV        R4, R1
+  0x08006146:  6A43         LDR        R3, [R0, #36]
+  0x08006148:  2101         MOVS       R1, #1
+  0x0800614A:  4620         MOV        R0, R4
+  0x0800614C:  F7FF FBC7    BL         fwrite                   ; 0x080058DE
+  0x08006150:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_X_file_bufsize from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=2

+
+
__SEGGER_RTL_X_file_bufsize:
+  0x08006152:  2040         MOVS       R0, #64
+  0x08006154:  4770         BX         LR
+
+

Section .text.libc._WriteBlocking from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=88, align=2

+
+
_WriteBlocking:
+  0x08006156:  B5F0         PUSH       {R4-R7, LR}
+  0x08006158:  B083         SUB        SP, SP, #12
+  0x0800615A:  4617         MOV        R7, R2
+  0x0800615C:  4606         MOV        R6, R0
+  0x0800615E:  68C5         LDR        R5, [R0, #12]
+  0x08006160:  2000         MOVS       R0, #0
+
.L1:
+  0x08006162:  9001         STR        R0, [SP, #4]
+  0x08006164:  6933         LDR        R3, [R6, #16]
+  0x08006166:  42AB         CMP        R3, R5
+  0x08006168:  68B0         LDR        R0, [R6, #8]
+  0x0800616A:  D902         BLS        .L2                      ; 0x08006172
+  0x0800616C:  43EA         MVNS       R2, R5
+  0x0800616E:  189C         ADDS       R4, R3, R2
+  0x08006170:  E002         B          .L3                      ; 0x08006178
+
.L2:
+  0x08006172:  43EA         MVNS       R2, R5
+  0x08006174:  189A         ADDS       R2, R3, R2
+  0x08006176:  1814         ADDS       R4, R2, R0
+
.L3:
+  0x08006178:  1B40         SUBS       R0, R0, R5
+  0x0800617A:  4284         CMP        R4, R0
+  0x0800617C:  D300         BCC        .L4                      ; 0x08006180
+  0x0800617E:  4604         MOV        R4, R0
+
.L4:
+  0x08006180:  42BC         CMP        R4, R7
+  0x08006182:  D300         BCC        .L5                      ; 0x08006186
+  0x08006184:  463C         MOV        R4, R7
+
.L5:
+  0x08006186:  6870         LDR        R0, [R6, #4]
+  0x08006188:  1940         ADDS       R0, R0, R5
+  0x0800618A:  9102         STR        R1, [SP, #8]
+  0x0800618C:  4622         MOV        R2, R4
+  0x0800618E:  F7FF FDD2    BL         memcpy                   ; 0x08005D36
+  0x08006192:  1965         ADDS       R5, R4, R5
+  0x08006194:  68B0         LDR        R0, [R6, #8]
+  0x08006196:  4285         CMP        R5, R0
+  0x08006198:  D100         BNE        .L6                      ; 0x0800619C
+  0x0800619A:  2500         MOVS       R5, #0
+
.L6:
+  0x0800619C:  9801         LDR        R0, [SP, #4]
+  0x0800619E:  60F5         STR        R5, [R6, #12]
+  0x080061A0:  9902         LDR        R1, [SP, #8]
+  0x080061A2:  1909         ADDS       R1, R1, R4
+  0x080061A4:  1820         ADDS       R0, R4, R0
+  0x080061A6:  1B3F         SUBS       R7, R7, R4
+  0x080061A8:  D1DB         BNE        .L1                      ; 0x08006162
+  0x080061AA:  B003         ADD        SP, SP, #12
+  0x080061AC:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_v6m_t_le_eabi_small.a), size=20, align=2

+
+
__aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x080061AE:  2200         MOVS       R2, #0
+
__aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x080061B0:  000B         MOVS       R3, R1
+  0x080061B2:  0011         MOVS       R1, R2
+  0x080061B4:  001A         MOVS       R2, R3
+
memset:
+  0x080061B6:  2A00         CMP        R2, #0
+  0x080061B8:  D002         BEQ        .L2                      ; 0x080061C0
+
.L1:
+  0x080061BA:  1E52         SUBS       R2, R2, #1
+  0x080061BC:  5481         STRB       R1, [R0, R2]
+  0x080061BE:  D1FC         BNE        .L1                      ; 0x080061BA
+
.L2:
+  0x080061C0:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_wctomb from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=16, align=2

+
+
__SEGGER_RTL_ascii_wctomb:
+  0x080061C2:  4602         MOV        R2, R0
+  0x080061C4:  2001         MOVS       R0, #1
+  0x080061C6:  297F         CMP        R1, #127
+  0x080061C8:  D901         BLS        .L1                      ; 0x080061CE
+  0x080061CA:  43C0         MVNS       R0, R0
+  0x080061CC:  4770         BX         LR
+
.L1:
+  0x080061CE:  7011         STRB       R1, [R2]
+  0x080061D0:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_toupper from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=2

+
+
__SEGGER_RTL_ascii_toupper:
+  0x080061D2:  4601         MOV        R1, R0
+  0x080061D4:  3961         SUBS       R1, #97
+  0x080061D6:  291A         CMP        R1, #26
+  0x080061D8:  D200         BCS        .L1                      ; 0x080061DC
+  0x080061DA:  3820         SUBS       R0, #32
+
.L1:
+  0x080061DC:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_towupper from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=2

+
+
__SEGGER_RTL_ascii_towupper:
+  0x080061DE:  4601         MOV        R1, R0
+  0x080061E0:  3961         SUBS       R1, #97
+  0x080061E2:  291A         CMP        R1, #26
+  0x080061E4:  D200         BCS        .L1                      ; 0x080061E8
+  0x080061E6:  3820         SUBS       R0, #32
+
.L1:
+  0x080061E8:  4770         BX         LR
+
+

Section .rodata..Lstr.99 from PowerPro_lto.o, size=19, align=1

+
+  0x080061EA:  73           DC.B       0x73                     ; 's'
+  0x080061EB:  65           DC.B       0x65                     ; 'e'
+  0x080061EC:  74           DC.B       0x74                     ; 't'
+  0x080061ED:  7A           DC.B       0x7A                     ; 'z'
+  0x080061EE:  65           DC.B       0x65                     ; 'e'
+  0x080061EF:  20           DC.B       0x20                     ; ' '
+  0x080061F0:  6F           DC.B       0x6F                     ; 'o'
+  0x080061F1:  70           DC.B       0x70                     ; 'p'
+  0x080061F2:  74           DC.B       0x74                     ; 't'
+  0x080061F3:  69           DC.B       0x69                     ; 'i'
+  0x080061F4:  6F           DC.B       0x6F                     ; 'o'
+  0x080061F5:  6E           DC.B       0x6E                     ; 'n'
+  0x080061F6:  20           DC.B       0x20                     ; ' '
+  0x080061F7:  62           DC.B       0x62                     ; 'b'
+  0x080061F8:  79           DC.B       0x79                     ; 'y'
+  0x080061F9:  74           DC.B       0x74                     ; 't'
+  0x080061FA:  65           DC.B       0x65                     ; 'e'
+  0x080061FB:  0D           DC.B       0x0D                     ; '\r'
+  0x080061FC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.9 from PowerPro_lto.o, size=59, align=1

+
+  0x080061FD:  4E           DC.B       0x4E                     ; 'N'
+  0x080061FE:  65           DC.B       0x65                     ; 'e'
+  0x080061FF:  75           DC.B       0x75                     ; 'u'
+  0x08006200:  65           DC.B       0x65                     ; 'e'
+  0x08006201:  20           DC.B       0x20                     ; ' '
+  0x08006202:  56           DC.B       0x56                     ; 'V'
+  0x08006203:  65           DC.B       0x65                     ; 'e'
+  0x08006204:  72           DC.B       0x72                     ; 'r'
+  0x08006205:  73           DC.B       0x73                     ; 's'
+  0x08006206:  69           DC.B       0x69                     ; 'i'
+  0x08006207:  6F           DC.B       0x6F                     ; 'o'
+  0x08006208:  6E           DC.B       0x6E                     ; 'n'
+  0x08006209:  20           DC.B       0x20                     ; ' '
+  0x0800620A:  50           DC.B       0x50                     ; 'P'
+  0x0800620B:  61           DC.B       0x61                     ; 'a'
+  0x0800620C:  72           DC.B       0x72                     ; 'r'
+  0x0800620D:  61           DC.B       0x61                     ; 'a'
+  0x0800620E:  6D           DC.B       0x6D                     ; 'm'
+  0x0800620F:  65           DC.B       0x65                     ; 'e'
+  0x08006210:  74           DC.B       0x74                     ; 't'
+  0x08006211:  65           DC.B       0x65                     ; 'e'
+  0x08006212:  72           DC.B       0x72                     ; 'r'
+  0x08006213:  20           DC.B       0x20                     ; ' '
+  0x08006214:  65           DC.B       0x65                     ; 'e'
+  0x08006215:  72           DC.B       0x72                     ; 'r'
+  0x08006216:  6B           DC.B       0x6B                     ; 'k'
+  0x08006217:  61           DC.B       0x61                     ; 'a'
+  0x08006218:  6E           DC.B       0x6E                     ; 'n'
+  0x08006219:  6E           DC.B       0x6E                     ; 'n'
+  0x0800621A:  74           DC.B       0x74                     ; 't'
+  0x0800621B:  2C           DC.B       0x2C                     ; ','
+  0x0800621C:  20           DC.B       0x20                     ; ' '
+  0x0800621D:  73           DC.B       0x73                     ; 's'
+  0x0800621E:  63           DC.B       0x63                     ; 'c'
+  0x0800621F:  68           DC.B       0x68                     ; 'h'
+  0x08006220:  72           DC.B       0x72                     ; 'r'
+  0x08006221:  65           DC.B       0x65                     ; 'e'
+  0x08006222:  69           DC.B       0x69                     ; 'i'
+  0x08006223:  62           DC.B       0x62                     ; 'b'
+  0x08006224:  65           DC.B       0x65                     ; 'e'
+  0x08006225:  20           DC.B       0x20                     ; ' '
+  0x08006226:  57           DC.B       0x57                     ; 'W'
+  0x08006227:  65           DC.B       0x65                     ; 'e'
+  0x08006228:  72           DC.B       0x72                     ; 'r'
+  0x08006229:  6B           DC.B       0x6B                     ; 'k'
+  0x0800622A:  73           DC.B       0x73                     ; 's'
+  0x0800622B:  65           DC.B       0x65                     ; 'e'
+  0x0800622C:  69           DC.B       0x69                     ; 'i'
+  0x0800622D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800622E:  73           DC.B       0x73                     ; 's'
+  0x0800622F:  74           DC.B       0x74                     ; 't'
+  0x08006230:  65           DC.B       0x65                     ; 'e'
+  0x08006231:  6C           DC.B       0x6C                     ; 'l'
+  0x08006232:  6C           DC.B       0x6C                     ; 'l'
+  0x08006233:  75           DC.B       0x75                     ; 'u'
+  0x08006234:  6E           DC.B       0x6E                     ; 'n'
+  0x08006235:  67           DC.B       0x67                     ; 'g'
+  0x08006236:  0D           DC.B       0x0D                     ; '\r'
+  0x08006237:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.7 from PowerPro_lto.o, size=39, align=1

+
+  0x08006238:  55           DC.B       0x55                     ; 'U'
+  0x08006239:  61           DC.B       0x61                     ; 'a'
+  0x0800623A:  72           DC.B       0x72                     ; 'r'
+  0x0800623B:  74           DC.B       0x74                     ; 't'
+  0x0800623C:  20           DC.B       0x20                     ; ' '
+  0x0800623D:  45           DC.B       0x45                     ; 'E'
+  0x0800623E:  72           DC.B       0x72                     ; 'r'
+  0x0800623F:  72           DC.B       0x72                     ; 'r'
+  0x08006240:  6F           DC.B       0x6F                     ; 'o'
+  0x08006241:  72           DC.B       0x72                     ; 'r'
+  0x08006242:  20           DC.B       0x20                     ; ' '
+  0x08006243:  62           DC.B       0x62                     ; 'b'
+  0x08006244:  65           DC.B       0x65                     ; 'e'
+  0x08006245:  69           DC.B       0x69                     ; 'i'
+  0x08006246:  20           DC.B       0x20                     ; ' '
+  0x08006247:  6E           DC.B       0x6E                     ; 'n'
+  0x08006248:  65           DC.B       0x65                     ; 'e'
+  0x08006249:  75           DC.B       0x75                     ; 'u'
+  0x0800624A:  73           DC.B       0x73                     ; 's'
+  0x0800624B:  74           DC.B       0x74                     ; 't'
+  0x0800624C:  61           DC.B       0x61                     ; 'a'
+  0x0800624D:  72           DC.B       0x72                     ; 'r'
+  0x0800624E:  74           DC.B       0x74                     ; 't'
+  0x0800624F:  20           DC.B       0x20                     ; ' '
+  0x08006250:  6E           DC.B       0x6E                     ; 'n'
+  0x08006251:  61           DC.B       0x61                     ; 'a'
+  0x08006252:  63           DC.B       0x63                     ; 'c'
+  0x08006253:  68           DC.B       0x68                     ; 'h'
+  0x08006254:  20           DC.B       0x20                     ; ' '
+  0x08006255:  46           DC.B       0x46                     ; 'F'
+  0x08006256:  65           DC.B       0x65                     ; 'e'
+  0x08006257:  68           DC.B       0x68                     ; 'h'
+  0x08006258:  6C           DC.B       0x6C                     ; 'l'
+  0x08006259:  65           DC.B       0x65                     ; 'e'
+  0x0800625A:  72           DC.B       0x72                     ; 'r'
+  0x0800625B:  20           DC.B       0x20                     ; ' '
+  0x0800625C:  0A           DC.B       0x0A                     ; '\n'
+  0x0800625D:  0D           DC.B       0x0D                     ; '\r'
+  0x0800625E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18 from PowerPro_lto.o, size=35, align=1

+
+  0x0800625F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006260:  45           DC.B       0x45                     ; 'E'
+  0x08006261:  57           DC.B       0x57                     ; 'W'
+  0x08006262:  5F           DC.B       0x5F                     ; '_'
+  0x08006263:  53           DC.B       0x53                     ; 'S'
+  0x08006264:  54           DC.B       0x54                     ; 'T'
+  0x08006265:  41           DC.B       0x41                     ; 'A'
+  0x08006266:  54           DC.B       0x54                     ; 'T'
+  0x08006267:  45           DC.B       0x45                     ; 'E'
+  0x08006268:  3A           DC.B       0x3A                     ; ':'
+  0x08006269:  20           DC.B       0x20                     ; ' '
+  0x0800626A:  4C           DC.B       0x4C                     ; 'L'
+  0x0800626B:  56           DC.B       0x56                     ; 'V'
+  0x0800626C:  50           DC.B       0x50                     ; 'P'
+  0x0800626D:  5F           DC.B       0x5F                     ; '_'
+  0x0800626E:  41           DC.B       0x41                     ; 'A'
+  0x0800626F:  75           DC.B       0x75                     ; 'u'
+  0x08006270:  74           DC.B       0x74                     ; 't'
+  0x08006271:  6F           DC.B       0x6F                     ; 'o'
+  0x08006272:  20           DC.B       0x20                     ; ' '
+  0x08006273:  4F           DC.B       0x4F                     ; 'O'
+  0x08006274:  6E           DC.B       0x6E                     ; 'n'
+  0x08006275:  2C           DC.B       0x2C                     ; ','
+  0x08006276:  20           DC.B       0x20                     ; ' '
+  0x08006277:  52           DC.B       0x52                     ; 'R'
+  0x08006278:  65           DC.B       0x65                     ; 'e'
+  0x08006279:  6C           DC.B       0x6C                     ; 'l'
+  0x0800627A:  61           DC.B       0x61                     ; 'a'
+  0x0800627B:  69           DC.B       0x69                     ; 'i'
+  0x0800627C:  73           DC.B       0x73                     ; 's'
+  0x0800627D:  20           DC.B       0x20                     ; ' '
+  0x0800627E:  6F           DC.B       0x6F                     ; 'o'
+  0x0800627F:  66           DC.B       0x66                     ; 'f'
+  0x08006280:  66           DC.B       0x66                     ; 'f'
+  0x08006281:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22 from PowerPro_lto.o, size=19, align=1

+
+  0x08006282:  4E           DC.B       0x4E                     ; 'N'
+  0x08006283:  45           DC.B       0x45                     ; 'E'
+  0x08006284:  57           DC.B       0x57                     ; 'W'
+  0x08006285:  5F           DC.B       0x5F                     ; '_'
+  0x08006286:  53           DC.B       0x53                     ; 'S'
+  0x08006287:  54           DC.B       0x54                     ; 'T'
+  0x08006288:  41           DC.B       0x41                     ; 'A'
+  0x08006289:  54           DC.B       0x54                     ; 'T'
+  0x0800628A:  45           DC.B       0x45                     ; 'E'
+  0x0800628B:  3A           DC.B       0x3A                     ; ':'
+  0x0800628C:  20           DC.B       0x20                     ; ' '
+  0x0800628D:  4C           DC.B       0x4C                     ; 'L'
+  0x0800628E:  56           DC.B       0x56                     ; 'V'
+  0x0800628F:  50           DC.B       0x50                     ; 'P'
+  0x08006290:  5F           DC.B       0x5F                     ; '_'
+  0x08006291:  4F           DC.B       0x4F                     ; 'O'
+  0x08006292:  46           DC.B       0x46                     ; 'F'
+  0x08006293:  46           DC.B       0x46                     ; 'F'
+  0x08006294:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18.130 from PowerPro_lto.o, size=39, align=1

+
+  0x08006295:  4E           DC.B       0x4E                     ; 'N'
+  0x08006296:  45           DC.B       0x45                     ; 'E'
+  0x08006297:  57           DC.B       0x57                     ; 'W'
+  0x08006298:  5F           DC.B       0x5F                     ; '_'
+  0x08006299:  53           DC.B       0x53                     ; 'S'
+  0x0800629A:  54           DC.B       0x54                     ; 'T'
+  0x0800629B:  41           DC.B       0x41                     ; 'A'
+  0x0800629C:  54           DC.B       0x54                     ; 'T'
+  0x0800629D:  45           DC.B       0x45                     ; 'E'
+  0x0800629E:  3A           DC.B       0x3A                     ; ':'
+  0x0800629F:  20           DC.B       0x20                     ; ' '
+  0x080062A0:  4C           DC.B       0x4C                     ; 'L'
+  0x080062A1:  56           DC.B       0x56                     ; 'V'
+  0x080062A2:  50           DC.B       0x50                     ; 'P'
+  0x080062A3:  5F           DC.B       0x5F                     ; '_'
+  0x080062A4:  4F           DC.B       0x4F                     ; 'O'
+  0x080062A5:  56           DC.B       0x56                     ; 'V'
+  0x080062A6:  50           DC.B       0x50                     ; 'P'
+  0x080062A7:  5F           DC.B       0x5F                     ; '_'
+  0x080062A8:  41           DC.B       0x41                     ; 'A'
+  0x080062A9:  75           DC.B       0x75                     ; 'u'
+  0x080062AA:  74           DC.B       0x74                     ; 't'
+  0x080062AB:  6F           DC.B       0x6F                     ; 'o'
+  0x080062AC:  20           DC.B       0x20                     ; ' '
+  0x080062AD:  4F           DC.B       0x4F                     ; 'O'
+  0x080062AE:  6E           DC.B       0x6E                     ; 'n'
+  0x080062AF:  2C           DC.B       0x2C                     ; ','
+  0x080062B0:  20           DC.B       0x20                     ; ' '
+  0x080062B1:  52           DC.B       0x52                     ; 'R'
+  0x080062B2:  65           DC.B       0x65                     ; 'e'
+  0x080062B3:  6C           DC.B       0x6C                     ; 'l'
+  0x080062B4:  61           DC.B       0x61                     ; 'a'
+  0x080062B5:  69           DC.B       0x69                     ; 'i'
+  0x080062B6:  73           DC.B       0x73                     ; 's'
+  0x080062B7:  20           DC.B       0x20                     ; ' '
+  0x080062B8:  6F           DC.B       0x6F                     ; 'o'
+  0x080062B9:  66           DC.B       0x66                     ; 'f'
+  0x080062BA:  66           DC.B       0x66                     ; 'f'
+  0x080062BB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.133 from PowerPro_lto.o, size=23, align=1

+
+  0x080062BC:  4E           DC.B       0x4E                     ; 'N'
+  0x080062BD:  45           DC.B       0x45                     ; 'E'
+  0x080062BE:  57           DC.B       0x57                     ; 'W'
+  0x080062BF:  5F           DC.B       0x5F                     ; '_'
+  0x080062C0:  53           DC.B       0x53                     ; 'S'
+  0x080062C1:  54           DC.B       0x54                     ; 'T'
+  0x080062C2:  41           DC.B       0x41                     ; 'A'
+  0x080062C3:  54           DC.B       0x54                     ; 'T'
+  0x080062C4:  45           DC.B       0x45                     ; 'E'
+  0x080062C5:  3A           DC.B       0x3A                     ; ':'
+  0x080062C6:  20           DC.B       0x20                     ; ' '
+  0x080062C7:  4C           DC.B       0x4C                     ; 'L'
+  0x080062C8:  56           DC.B       0x56                     ; 'V'
+  0x080062C9:  50           DC.B       0x50                     ; 'P'
+  0x080062CA:  5F           DC.B       0x5F                     ; '_'
+  0x080062CB:  4F           DC.B       0x4F                     ; 'O'
+  0x080062CC:  56           DC.B       0x56                     ; 'V'
+  0x080062CD:  50           DC.B       0x50                     ; 'P'
+  0x080062CE:  5F           DC.B       0x5F                     ; '_'
+  0x080062CF:  4F           DC.B       0x4F                     ; 'O'
+  0x080062D0:  46           DC.B       0x46                     ; 'F'
+  0x080062D1:  46           DC.B       0x46                     ; 'F'
+  0x080062D2:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18.153 from PowerPro_lto.o, size=35, align=1

+
+  0x080062D3:  4E           DC.B       0x4E                     ; 'N'
+  0x080062D4:  45           DC.B       0x45                     ; 'E'
+  0x080062D5:  57           DC.B       0x57                     ; 'W'
+  0x080062D6:  5F           DC.B       0x5F                     ; '_'
+  0x080062D7:  53           DC.B       0x53                     ; 'S'
+  0x080062D8:  54           DC.B       0x54                     ; 'T'
+  0x080062D9:  41           DC.B       0x41                     ; 'A'
+  0x080062DA:  54           DC.B       0x54                     ; 'T'
+  0x080062DB:  45           DC.B       0x45                     ; 'E'
+  0x080062DC:  3A           DC.B       0x3A                     ; ':'
+  0x080062DD:  20           DC.B       0x20                     ; ' '
+  0x080062DE:  4F           DC.B       0x4F                     ; 'O'
+  0x080062DF:  56           DC.B       0x56                     ; 'V'
+  0x080062E0:  50           DC.B       0x50                     ; 'P'
+  0x080062E1:  5F           DC.B       0x5F                     ; '_'
+  0x080062E2:  41           DC.B       0x41                     ; 'A'
+  0x080062E3:  75           DC.B       0x75                     ; 'u'
+  0x080062E4:  74           DC.B       0x74                     ; 't'
+  0x080062E5:  6F           DC.B       0x6F                     ; 'o'
+  0x080062E6:  20           DC.B       0x20                     ; ' '
+  0x080062E7:  4F           DC.B       0x4F                     ; 'O'
+  0x080062E8:  6E           DC.B       0x6E                     ; 'n'
+  0x080062E9:  2C           DC.B       0x2C                     ; ','
+  0x080062EA:  20           DC.B       0x20                     ; ' '
+  0x080062EB:  52           DC.B       0x52                     ; 'R'
+  0x080062EC:  65           DC.B       0x65                     ; 'e'
+  0x080062ED:  6C           DC.B       0x6C                     ; 'l'
+  0x080062EE:  61           DC.B       0x61                     ; 'a'
+  0x080062EF:  69           DC.B       0x69                     ; 'i'
+  0x080062F0:  73           DC.B       0x73                     ; 's'
+  0x080062F1:  20           DC.B       0x20                     ; ' '
+  0x080062F2:  6F           DC.B       0x6F                     ; 'o'
+  0x080062F3:  66           DC.B       0x66                     ; 'f'
+  0x080062F4:  66           DC.B       0x66                     ; 'f'
+  0x080062F5:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.156 from PowerPro_lto.o, size=19, align=1

+
+  0x080062F6:  4E           DC.B       0x4E                     ; 'N'
+  0x080062F7:  45           DC.B       0x45                     ; 'E'
+  0x080062F8:  57           DC.B       0x57                     ; 'W'
+  0x080062F9:  5F           DC.B       0x5F                     ; '_'
+  0x080062FA:  53           DC.B       0x53                     ; 'S'
+  0x080062FB:  54           DC.B       0x54                     ; 'T'
+  0x080062FC:  41           DC.B       0x41                     ; 'A'
+  0x080062FD:  54           DC.B       0x54                     ; 'T'
+  0x080062FE:  45           DC.B       0x45                     ; 'E'
+  0x080062FF:  3A           DC.B       0x3A                     ; ':'
+  0x08006300:  20           DC.B       0x20                     ; ' '
+  0x08006301:  4F           DC.B       0x4F                     ; 'O'
+  0x08006302:  56           DC.B       0x56                     ; 'V'
+  0x08006303:  50           DC.B       0x50                     ; 'P'
+  0x08006304:  5F           DC.B       0x5F                     ; '_'
+  0x08006305:  4F           DC.B       0x4F                     ; 'O'
+  0x08006306:  46           DC.B       0x46                     ; 'F'
+  0x08006307:  46           DC.B       0x46                     ; 'F'
+  0x08006308:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8.177 from PowerPro_lto.o, size=35, align=1

+
+  0x08006309:  4E           DC.B       0x4E                     ; 'N'
+  0x0800630A:  45           DC.B       0x45                     ; 'E'
+  0x0800630B:  57           DC.B       0x57                     ; 'W'
+  0x0800630C:  5F           DC.B       0x5F                     ; '_'
+  0x0800630D:  53           DC.B       0x53                     ; 'S'
+  0x0800630E:  54           DC.B       0x54                     ; 'T'
+  0x0800630F:  41           DC.B       0x41                     ; 'A'
+  0x08006310:  54           DC.B       0x54                     ; 'T'
+  0x08006311:  45           DC.B       0x45                     ; 'E'
+  0x08006312:  3A           DC.B       0x3A                     ; ':'
+  0x08006313:  20           DC.B       0x20                     ; ' '
+  0x08006314:  53           DC.B       0x53                     ; 'S'
+  0x08006315:  45           DC.B       0x45                     ; 'E'
+  0x08006316:  43           DC.B       0x43                     ; 'C'
+  0x08006317:  4F           DC.B       0x4F                     ; 'O'
+  0x08006318:  4E           DC.B       0x4E                     ; 'N'
+  0x08006319:  44           DC.B       0x44                     ; 'D'
+  0x0800631A:  41           DC.B       0x41                     ; 'A'
+  0x0800631B:  52           DC.B       0x52                     ; 'R'
+  0x0800631C:  59           DC.B       0x59                     ; 'Y'
+  0x0800631D:  50           DC.B       0x50                     ; 'P'
+  0x0800631E:  52           DC.B       0x52                     ; 'R'
+  0x0800631F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006320:  54           DC.B       0x54                     ; 'T'
+  0x08006321:  45           DC.B       0x45                     ; 'E'
+  0x08006322:  43           DC.B       0x43                     ; 'C'
+  0x08006323:  54           DC.B       0x54                     ; 'T'
+  0x08006324:  49           DC.B       0x49                     ; 'I'
+  0x08006325:  4F           DC.B       0x4F                     ; 'O'
+  0x08006326:  4E           DC.B       0x4E                     ; 'N'
+  0x08006327:  5F           DC.B       0x5F                     ; '_'
+  0x08006328:  4F           DC.B       0x4F                     ; 'O'
+  0x08006329:  46           DC.B       0x46                     ; 'F'
+  0x0800632A:  46           DC.B       0x46                     ; 'F'
+  0x0800632B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.13.180 from PowerPro_lto.o, size=43, align=1

+
+  0x0800632C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800632D:  45           DC.B       0x45                     ; 'E'
+  0x0800632E:  57           DC.B       0x57                     ; 'W'
+  0x0800632F:  5F           DC.B       0x5F                     ; '_'
+  0x08006330:  53           DC.B       0x53                     ; 'S'
+  0x08006331:  54           DC.B       0x54                     ; 'T'
+  0x08006332:  41           DC.B       0x41                     ; 'A'
+  0x08006333:  54           DC.B       0x54                     ; 'T'
+  0x08006334:  45           DC.B       0x45                     ; 'E'
+  0x08006335:  3A           DC.B       0x3A                     ; ':'
+  0x08006336:  20           DC.B       0x20                     ; ' '
+  0x08006337:  4D           DC.B       0x4D                     ; 'M'
+  0x08006338:  41           DC.B       0x41                     ; 'A'
+  0x08006339:  49           DC.B       0x49                     ; 'I'
+  0x0800633A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800633B:  53           DC.B       0x53                     ; 'S'
+  0x0800633C:  57           DC.B       0x57                     ; 'W'
+  0x0800633D:  49           DC.B       0x49                     ; 'I'
+  0x0800633E:  54           DC.B       0x54                     ; 'T'
+  0x0800633F:  43           DC.B       0x43                     ; 'C'
+  0x08006340:  48           DC.B       0x48                     ; 'H'
+  0x08006341:  5F           DC.B       0x5F                     ; '_'
+  0x08006342:  45           DC.B       0x45                     ; 'E'
+  0x08006343:  52           DC.B       0x52                     ; 'R'
+  0x08006344:  52           DC.B       0x52                     ; 'R'
+  0x08006345:  4F           DC.B       0x4F                     ; 'O'
+  0x08006346:  52           DC.B       0x52                     ; 'R'
+  0x08006347:  2C           DC.B       0x2C                     ; ','
+  0x08006348:  20           DC.B       0x20                     ; ' '
+  0x08006349:  54           DC.B       0x54                     ; 'T'
+  0x0800634A:  65           DC.B       0x65                     ; 'e'
+  0x0800634B:  6D           DC.B       0x6D                     ; 'm'
+  0x0800634C:  70           DC.B       0x70                     ; 'p'
+  0x0800634D:  20           DC.B       0x20                     ; ' '
+  0x0800634E:  74           DC.B       0x74                     ; 't'
+  0x0800634F:  6F           DC.B       0x6F                     ; 'o'
+  0x08006350:  6F           DC.B       0x6F                     ; 'o'
+  0x08006351:  20           DC.B       0x20                     ; ' '
+  0x08006352:  68           DC.B       0x68                     ; 'h'
+  0x08006353:  69           DC.B       0x69                     ; 'i'
+  0x08006354:  67           DC.B       0x67                     ; 'g'
+  0x08006355:  68           DC.B       0x68                     ; 'h'
+  0x08006356:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.203 from PowerPro_lto.o, size=35, align=1

+
+  0x08006357:  76           DC.B       0x76                     ; 'v'
+  0x08006358:  6F           DC.B       0x6F                     ; 'o'
+  0x08006359:  6C           DC.B       0x6C                     ; 'l'
+  0x0800635A:  74           DC.B       0x74                     ; 't'
+  0x0800635B:  61           DC.B       0x61                     ; 'a'
+  0x0800635C:  67           DC.B       0x67                     ; 'g'
+  0x0800635D:  65           DC.B       0x65                     ; 'e'
+  0x0800635E:  20           DC.B       0x20                     ; ' '
+  0x0800635F:  69           DC.B       0x69                     ; 'i'
+  0x08006360:  6E           DC.B       0x6E                     ; 'n'
+  0x08006361:  3D           DC.B       0x3D                     ; '='
+  0x08006362:  20           DC.B       0x20                     ; ' '
+  0x08006363:  25           DC.B       0x25                     ; '%'
+  0x08006364:  64           DC.B       0x64                     ; 'd'
+  0x08006365:  2C           DC.B       0x2C                     ; ','
+  0x08006366:  20           DC.B       0x20                     ; ' '
+  0x08006367:  6F           DC.B       0x6F                     ; 'o'
+  0x08006368:  75           DC.B       0x75                     ; 'u'
+  0x08006369:  74           DC.B       0x74                     ; 't'
+  0x0800636A:  3D           DC.B       0x3D                     ; '='
+  0x0800636B:  20           DC.B       0x20                     ; ' '
+  0x0800636C:  25           DC.B       0x25                     ; '%'
+  0x0800636D:  64           DC.B       0x64                     ; 'd'
+  0x0800636E:  2C           DC.B       0x2C                     ; ','
+  0x0800636F:  20           DC.B       0x20                     ; ' '
+  0x08006370:  64           DC.B       0x64                     ; 'd'
+  0x08006371:  72           DC.B       0x72                     ; 'r'
+  0x08006372:  6F           DC.B       0x6F                     ; 'o'
+  0x08006373:  70           DC.B       0x70                     ; 'p'
+  0x08006374:  20           DC.B       0x20                     ; ' '
+  0x08006375:  25           DC.B       0x25                     ; '%'
+  0x08006376:  64           DC.B       0x64                     ; 'd'
+  0x08006377:  0D           DC.B       0x0D                     ; '\r'
+  0x08006378:  0A           DC.B       0x0A                     ; '\n'
+  0x08006379:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_month_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=87, align=1

+
+
__SEGGER_RTL_c_locale_month_names:
+  0x0800637A:  4A           DC.B       0x4A                     ; 'J'
+  0x0800637B:  61           DC.B       0x61                     ; 'a'
+  0x0800637C:  6E           DC.B       0x6E                     ; 'n'
+  0x0800637D:  75           DC.B       0x75                     ; 'u'
+  0x0800637E:  61           DC.B       0x61                     ; 'a'
+  0x0800637F:  72           DC.B       0x72                     ; 'r'
+  0x08006380:  79           DC.B       0x79                     ; 'y'
+  0x08006381:  00           DC.B       0x00                     ; '\0'
+  0x08006382:  46           DC.B       0x46                     ; 'F'
+  0x08006383:  65           DC.B       0x65                     ; 'e'
+  0x08006384:  62           DC.B       0x62                     ; 'b'
+  0x08006385:  72           DC.B       0x72                     ; 'r'
+  0x08006386:  75           DC.B       0x75                     ; 'u'
+  0x08006387:  61           DC.B       0x61                     ; 'a'
+  0x08006388:  72           DC.B       0x72                     ; 'r'
+  0x08006389:  79           DC.B       0x79                     ; 'y'
+  0x0800638A:  00           DC.B       0x00                     ; '\0'
+  0x0800638B:  4D           DC.B       0x4D                     ; 'M'
+  0x0800638C:  61           DC.B       0x61                     ; 'a'
+  0x0800638D:  72           DC.B       0x72                     ; 'r'
+  0x0800638E:  63           DC.B       0x63                     ; 'c'
+  0x0800638F:  68           DC.B       0x68                     ; 'h'
+  0x08006390:  00           DC.B       0x00                     ; '\0'
+  0x08006391:  41           DC.B       0x41                     ; 'A'
+  0x08006392:  70           DC.B       0x70                     ; 'p'
+  0x08006393:  72           DC.B       0x72                     ; 'r'
+  0x08006394:  69           DC.B       0x69                     ; 'i'
+  0x08006395:  6C           DC.B       0x6C                     ; 'l'
+  0x08006396:  00           DC.B       0x00                     ; '\0'
+  0x08006397:  4D           DC.B       0x4D                     ; 'M'
+  0x08006398:  61           DC.B       0x61                     ; 'a'
+  0x08006399:  79           DC.B       0x79                     ; 'y'
+  0x0800639A:  00           DC.B       0x00                     ; '\0'
+  0x0800639B:  4A           DC.B       0x4A                     ; 'J'
+  0x0800639C:  75           DC.B       0x75                     ; 'u'
+  0x0800639D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800639E:  65           DC.B       0x65                     ; 'e'
+  0x0800639F:  00           DC.B       0x00                     ; '\0'
+  0x080063A0:  4A           DC.B       0x4A                     ; 'J'
+  0x080063A1:  75           DC.B       0x75                     ; 'u'
+  0x080063A2:  6C           DC.B       0x6C                     ; 'l'
+  0x080063A3:  79           DC.B       0x79                     ; 'y'
+  0x080063A4:  00           DC.B       0x00                     ; '\0'
+  0x080063A5:  41           DC.B       0x41                     ; 'A'
+  0x080063A6:  75           DC.B       0x75                     ; 'u'
+  0x080063A7:  67           DC.B       0x67                     ; 'g'
+  0x080063A8:  75           DC.B       0x75                     ; 'u'
+  0x080063A9:  73           DC.B       0x73                     ; 's'
+  0x080063AA:  74           DC.B       0x74                     ; 't'
+  0x080063AB:  00           DC.B       0x00                     ; '\0'
+  0x080063AC:  53           DC.B       0x53                     ; 'S'
+  0x080063AD:  65           DC.B       0x65                     ; 'e'
+  0x080063AE:  70           DC.B       0x70                     ; 'p'
+  0x080063AF:  74           DC.B       0x74                     ; 't'
+  0x080063B0:  65           DC.B       0x65                     ; 'e'
+  0x080063B1:  6D           DC.B       0x6D                     ; 'm'
+  0x080063B2:  62           DC.B       0x62                     ; 'b'
+  0x080063B3:  65           DC.B       0x65                     ; 'e'
+  0x080063B4:  72           DC.B       0x72                     ; 'r'
+  0x080063B5:  00           DC.B       0x00                     ; '\0'
+  0x080063B6:  4F           DC.B       0x4F                     ; 'O'
+  0x080063B7:  63           DC.B       0x63                     ; 'c'
+  0x080063B8:  74           DC.B       0x74                     ; 't'
+  0x080063B9:  6F           DC.B       0x6F                     ; 'o'
+  0x080063BA:  62           DC.B       0x62                     ; 'b'
+  0x080063BB:  65           DC.B       0x65                     ; 'e'
+  0x080063BC:  72           DC.B       0x72                     ; 'r'
+  0x080063BD:  00           DC.B       0x00                     ; '\0'
+  0x080063BE:  4E           DC.B       0x4E                     ; 'N'
+  0x080063BF:  6F           DC.B       0x6F                     ; 'o'
+  0x080063C0:  76           DC.B       0x76                     ; 'v'
+  0x080063C1:  65           DC.B       0x65                     ; 'e'
+  0x080063C2:  6D           DC.B       0x6D                     ; 'm'
+  0x080063C3:  62           DC.B       0x62                     ; 'b'
+  0x080063C4:  65           DC.B       0x65                     ; 'e'
+  0x080063C5:  72           DC.B       0x72                     ; 'r'
+  0x080063C6:  00           DC.B       0x00                     ; '\0'
+  0x080063C7:  44           DC.B       0x44                     ; 'D'
+  0x080063C8:  65           DC.B       0x65                     ; 'e'
+  0x080063C9:  63           DC.B       0x63                     ; 'c'
+  0x080063CA:  65           DC.B       0x65                     ; 'e'
+  0x080063CB:  6D           DC.B       0x6D                     ; 'm'
+  0x080063CC:  62           DC.B       0x62                     ; 'b'
+  0x080063CD:  65           DC.B       0x65                     ; 'e'
+  0x080063CE:  72           DC.B       0x72                     ; 'r'
+  0x080063CF:  00           DC.B       0x00                     ; '\0'
+  0x080063D0:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_am_pm_indicator from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=7, align=1

+
+
__SEGGER_RTL_c_locale_am_pm_indicator:
+  0x080063D1:  41           DC.B       0x41                     ; 'A'
+  0x080063D2:  4D           DC.B       0x4D                     ; 'M'
+  0x080063D3:  00           DC.B       0x00                     ; '\0'
+  0x080063D4:  50           DC.B       0x50                     ; 'P'
+  0x080063D5:  4D           DC.B       0x4D                     ; 'M'
+  0x080063D6:  00           DC.B       0x00                     ; '\0'
+  0x080063D7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_date_time_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=15, align=1

+
+
__SEGGER_RTL_c_locale_date_time_format:
+  0x080063D8:  25           DC.B       0x25                     ; '%'
+  0x080063D9:  61           DC.B       0x61                     ; 'a'
+  0x080063DA:  20           DC.B       0x20                     ; ' '
+  0x080063DB:  25           DC.B       0x25                     ; '%'
+  0x080063DC:  62           DC.B       0x62                     ; 'b'
+  0x080063DD:  20           DC.B       0x20                     ; ' '
+  0x080063DE:  25           DC.B       0x25                     ; '%'
+  0x080063DF:  65           DC.B       0x65                     ; 'e'
+  0x080063E0:  20           DC.B       0x20                     ; ' '
+  0x080063E1:  25           DC.B       0x25                     ; '%'
+  0x080063E2:  54           DC.B       0x54                     ; 'T'
+  0x080063E3:  20           DC.B       0x20                     ; ' '
+  0x080063E4:  25           DC.B       0x25                     ; '%'
+  0x080063E5:  59           DC.B       0x59                     ; 'Y'
+  0x080063E6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr from PowerPro_lto.o, size=18, align=1

+
+  0x080063E7:  42           DC.B       0x42                     ; 'B'
+  0x080063E8:  55           DC.B       0x55                     ; 'U'
+  0x080063E9:  54           DC.B       0x54                     ; 'T'
+  0x080063EA:  54           DC.B       0x54                     ; 'T'
+  0x080063EB:  4F           DC.B       0x4F                     ; 'O'
+  0x080063EC:  4E           DC.B       0x4E                     ; 'N'
+  0x080063ED:  3A           DC.B       0x3A                     ; ':'
+  0x080063EE:  20           DC.B       0x20                     ; ' '
+  0x080063EF:  41           DC.B       0x41                     ; 'A'
+  0x080063F0:  75           DC.B       0x75                     ; 'u'
+  0x080063F1:  74           DC.B       0x74                     ; 't'
+  0x080063F2:  6F           DC.B       0x6F                     ; 'o'
+  0x080063F3:  20           DC.B       0x20                     ; ' '
+  0x080063F4:  4D           DC.B       0x4D                     ; 'M'
+  0x080063F5:  6F           DC.B       0x6F                     ; 'o'
+  0x080063F6:  64           DC.B       0x64                     ; 'd'
+  0x080063F7:  65           DC.B       0x65                     ; 'e'
+  0x080063F8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8 from PowerPro_lto.o, size=18, align=1

+
+  0x080063F9:  4B           DC.B       0x4B                     ; 'K'
+  0x080063FA:  6F           DC.B       0x6F                     ; 'o'
+  0x080063FB:  6E           DC.B       0x6E                     ; 'n'
+  0x080063FC:  66           DC.B       0x66                     ; 'f'
+  0x080063FD:  69           DC.B       0x69                     ; 'i'
+  0x080063FE:  67           DC.B       0x67                     ; 'g'
+  0x080063FF:  20           DC.B       0x20                     ; ' '
+  0x08006400:  76           DC.B       0x76                     ; 'v'
+  0x08006401:  6F           DC.B       0x6F                     ; 'o'
+  0x08006402:  72           DC.B       0x72                     ; 'r'
+  0x08006403:  68           DC.B       0x68                     ; 'h'
+  0x08006404:  61           DC.B       0x61                     ; 'a'
+  0x08006405:  6E           DC.B       0x6E                     ; 'n'
+  0x08006406:  64           DC.B       0x64                     ; 'd'
+  0x08006407:  65           DC.B       0x65                     ; 'e'
+  0x08006408:  6E           DC.B       0x6E                     ; 'n'
+  0x08006409:  0D           DC.B       0x0D                     ; '\r'
+  0x0800640A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.10 from PowerPro_lto.o, size=46, align=1

+
+  0x0800640B:  45           DC.B       0x45                     ; 'E'
+  0x0800640C:  72           DC.B       0x72                     ; 'r'
+  0x0800640D:  73           DC.B       0x73                     ; 's'
+  0x0800640E:  74           DC.B       0x74                     ; 't'
+  0x0800640F:  73           DC.B       0x73                     ; 's'
+  0x08006410:  74           DC.B       0x74                     ; 't'
+  0x08006411:  61           DC.B       0x61                     ; 'a'
+  0x08006412:  72           DC.B       0x72                     ; 'r'
+  0x08006413:  74           DC.B       0x74                     ; 't'
+  0x08006414:  20           DC.B       0x20                     ; ' '
+  0x08006415:  65           DC.B       0x65                     ; 'e'
+  0x08006416:  72           DC.B       0x72                     ; 'r'
+  0x08006417:  6B           DC.B       0x6B                     ; 'k'
+  0x08006418:  61           DC.B       0x61                     ; 'a'
+  0x08006419:  6E           DC.B       0x6E                     ; 'n'
+  0x0800641A:  6E           DC.B       0x6E                     ; 'n'
+  0x0800641B:  74           DC.B       0x74                     ; 't'
+  0x0800641C:  2C           DC.B       0x2C                     ; ','
+  0x0800641D:  20           DC.B       0x20                     ; ' '
+  0x0800641E:  73           DC.B       0x73                     ; 's'
+  0x0800641F:  63           DC.B       0x63                     ; 'c'
+  0x08006420:  68           DC.B       0x68                     ; 'h'
+  0x08006421:  72           DC.B       0x72                     ; 'r'
+  0x08006422:  65           DC.B       0x65                     ; 'e'
+  0x08006423:  69           DC.B       0x69                     ; 'i'
+  0x08006424:  62           DC.B       0x62                     ; 'b'
+  0x08006425:  65           DC.B       0x65                     ; 'e'
+  0x08006426:  20           DC.B       0x20                     ; ' '
+  0x08006427:  57           DC.B       0x57                     ; 'W'
+  0x08006428:  65           DC.B       0x65                     ; 'e'
+  0x08006429:  72           DC.B       0x72                     ; 'r'
+  0x0800642A:  6B           DC.B       0x6B                     ; 'k'
+  0x0800642B:  73           DC.B       0x73                     ; 's'
+  0x0800642C:  65           DC.B       0x65                     ; 'e'
+  0x0800642D:  69           DC.B       0x69                     ; 'i'
+  0x0800642E:  6E           DC.B       0x6E                     ; 'n'
+  0x0800642F:  73           DC.B       0x73                     ; 's'
+  0x08006430:  74           DC.B       0x74                     ; 't'
+  0x08006431:  65           DC.B       0x65                     ; 'e'
+  0x08006432:  6C           DC.B       0x6C                     ; 'l'
+  0x08006433:  6C           DC.B       0x6C                     ; 'l'
+  0x08006434:  75           DC.B       0x75                     ; 'u'
+  0x08006435:  6E           DC.B       0x6E                     ; 'n'
+  0x08006436:  67           DC.B       0x67                     ; 'g'
+  0x08006437:  0D           DC.B       0x0D                     ; '\r'
+  0x08006438:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.1 from PowerPro_lto.o, size=14, align=1

+
+  0x08006439:  75           DC.B       0x75                     ; 'u'
+  0x0800643A:  61           DC.B       0x61                     ; 'a'
+  0x0800643B:  72           DC.B       0x72                     ; 'r'
+  0x0800643C:  74           DC.B       0x74                     ; 't'
+  0x0800643D:  20           DC.B       0x20                     ; ' '
+  0x0800643E:  65           DC.B       0x65                     ; 'e'
+  0x0800643F:  72           DC.B       0x72                     ; 'r'
+  0x08006440:  72           DC.B       0x72                     ; 'r'
+  0x08006441:  6F           DC.B       0x6F                     ; 'o'
+  0x08006442:  72           DC.B       0x72                     ; 'r'
+  0x08006443:  20           DC.B       0x20                     ; ' '
+  0x08006444:  0A           DC.B       0x0A                     ; '\n'
+  0x08006445:  0D           DC.B       0x0D                     ; '\r'
+  0x08006446:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.117 from PowerPro_lto.o, size=30, align=1

+
+  0x08006447:  4C           DC.B       0x4C                     ; 'L'
+  0x08006448:  56           DC.B       0x56                     ; 'V'
+  0x08006449:  50           DC.B       0x50                     ; 'P'
+  0x0800644A:  5F           DC.B       0x5F                     ; '_'
+  0x0800644B:  53           DC.B       0x53                     ; 'S'
+  0x0800644C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800644D:  5F           DC.B       0x5F                     ; '_'
+  0x0800644E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800644F:  66           DC.B       0x66                     ; 'f'
+  0x08006450:  66           DC.B       0x66                     ; 'f'
+  0x08006451:  3A           DC.B       0x3A                     ; ':'
+  0x08006452:  20           DC.B       0x20                     ; ' '
+  0x08006453:  4E           DC.B       0x4E                     ; 'N'
+  0x08006454:  45           DC.B       0x45                     ; 'E'
+  0x08006455:  57           DC.B       0x57                     ; 'W'
+  0x08006456:  5F           DC.B       0x5F                     ; '_'
+  0x08006457:  53           DC.B       0x53                     ; 'S'
+  0x08006458:  54           DC.B       0x54                     ; 'T'
+  0x08006459:  41           DC.B       0x41                     ; 'A'
+  0x0800645A:  54           DC.B       0x54                     ; 'T'
+  0x0800645B:  45           DC.B       0x45                     ; 'E'
+  0x0800645C:  3A           DC.B       0x3A                     ; ':'
+  0x0800645D:  20           DC.B       0x20                     ; ' '
+  0x0800645E:  4C           DC.B       0x4C                     ; 'L'
+  0x0800645F:  56           DC.B       0x56                     ; 'V'
+  0x08006460:  50           DC.B       0x50                     ; 'P'
+  0x08006461:  5F           DC.B       0x5F                     ; '_'
+  0x08006462:  4F           DC.B       0x4F                     ; 'O'
+  0x08006463:  4E           DC.B       0x4E                     ; 'N'
+  0x08006464:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23 from PowerPro_lto.o, size=18, align=1

+
+  0x08006465:  4E           DC.B       0x4E                     ; 'N'
+  0x08006466:  45           DC.B       0x45                     ; 'E'
+  0x08006467:  57           DC.B       0x57                     ; 'W'
+  0x08006468:  5F           DC.B       0x5F                     ; '_'
+  0x08006469:  53           DC.B       0x53                     ; 'S'
+  0x0800646A:  54           DC.B       0x54                     ; 'T'
+  0x0800646B:  41           DC.B       0x41                     ; 'A'
+  0x0800646C:  54           DC.B       0x54                     ; 'T'
+  0x0800646D:  45           DC.B       0x45                     ; 'E'
+  0x0800646E:  3A           DC.B       0x3A                     ; ':'
+  0x0800646F:  20           DC.B       0x20                     ; ' '
+  0x08006470:  4C           DC.B       0x4C                     ; 'L'
+  0x08006471:  56           DC.B       0x56                     ; 'V'
+  0x08006472:  50           DC.B       0x50                     ; 'P'
+  0x08006473:  5F           DC.B       0x5F                     ; '_'
+  0x08006474:  4F           DC.B       0x4F                     ; 'O'
+  0x08006475:  4E           DC.B       0x4E                     ; 'N'
+  0x08006476:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.123 from PowerPro_lto.o, size=38, align=1

+
+  0x08006477:  4C           DC.B       0x4C                     ; 'L'
+  0x08006478:  56           DC.B       0x56                     ; 'V'
+  0x08006479:  50           DC.B       0x50                     ; 'P'
+  0x0800647A:  5F           DC.B       0x5F                     ; '_'
+  0x0800647B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800647C:  56           DC.B       0x56                     ; 'V'
+  0x0800647D:  50           DC.B       0x50                     ; 'P'
+  0x0800647E:  5F           DC.B       0x5F                     ; '_'
+  0x0800647F:  53           DC.B       0x53                     ; 'S'
+  0x08006480:  4D           DC.B       0x4D                     ; 'M'
+  0x08006481:  5F           DC.B       0x5F                     ; '_'
+  0x08006482:  4F           DC.B       0x4F                     ; 'O'
+  0x08006483:  66           DC.B       0x66                     ; 'f'
+  0x08006484:  66           DC.B       0x66                     ; 'f'
+  0x08006485:  3A           DC.B       0x3A                     ; ':'
+  0x08006486:  20           DC.B       0x20                     ; ' '
+  0x08006487:  4E           DC.B       0x4E                     ; 'N'
+  0x08006488:  45           DC.B       0x45                     ; 'E'
+  0x08006489:  57           DC.B       0x57                     ; 'W'
+  0x0800648A:  5F           DC.B       0x5F                     ; '_'
+  0x0800648B:  53           DC.B       0x53                     ; 'S'
+  0x0800648C:  54           DC.B       0x54                     ; 'T'
+  0x0800648D:  41           DC.B       0x41                     ; 'A'
+  0x0800648E:  54           DC.B       0x54                     ; 'T'
+  0x0800648F:  45           DC.B       0x45                     ; 'E'
+  0x08006490:  3A           DC.B       0x3A                     ; ':'
+  0x08006491:  20           DC.B       0x20                     ; ' '
+  0x08006492:  4C           DC.B       0x4C                     ; 'L'
+  0x08006493:  56           DC.B       0x56                     ; 'V'
+  0x08006494:  50           DC.B       0x50                     ; 'P'
+  0x08006495:  5F           DC.B       0x5F                     ; '_'
+  0x08006496:  4F           DC.B       0x4F                     ; 'O'
+  0x08006497:  56           DC.B       0x56                     ; 'V'
+  0x08006498:  50           DC.B       0x50                     ; 'P'
+  0x08006499:  5F           DC.B       0x5F                     ; '_'
+  0x0800649A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800649B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800649C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.20.132 from PowerPro_lto.o, size=38, align=1

+
+  0x0800649D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800649E:  45           DC.B       0x45                     ; 'E'
+  0x0800649F:  57           DC.B       0x57                     ; 'W'
+  0x080064A0:  5F           DC.B       0x5F                     ; '_'
+  0x080064A1:  53           DC.B       0x53                     ; 'S'
+  0x080064A2:  54           DC.B       0x54                     ; 'T'
+  0x080064A3:  41           DC.B       0x41                     ; 'A'
+  0x080064A4:  54           DC.B       0x54                     ; 'T'
+  0x080064A5:  45           DC.B       0x45                     ; 'E'
+  0x080064A6:  3A           DC.B       0x3A                     ; ':'
+  0x080064A7:  20           DC.B       0x20                     ; ' '
+  0x080064A8:  4C           DC.B       0x4C                     ; 'L'
+  0x080064A9:  56           DC.B       0x56                     ; 'V'
+  0x080064AA:  50           DC.B       0x50                     ; 'P'
+  0x080064AB:  5F           DC.B       0x5F                     ; '_'
+  0x080064AC:  4F           DC.B       0x4F                     ; 'O'
+  0x080064AD:  56           DC.B       0x56                     ; 'V'
+  0x080064AE:  50           DC.B       0x50                     ; 'P'
+  0x080064AF:  5F           DC.B       0x5F                     ; '_'
+  0x080064B0:  41           DC.B       0x41                     ; 'A'
+  0x080064B1:  75           DC.B       0x75                     ; 'u'
+  0x080064B2:  74           DC.B       0x74                     ; 't'
+  0x080064B3:  6F           DC.B       0x6F                     ; 'o'
+  0x080064B4:  20           DC.B       0x20                     ; ' '
+  0x080064B5:  4F           DC.B       0x4F                     ; 'O'
+  0x080064B6:  6E           DC.B       0x6E                     ; 'n'
+  0x080064B7:  2C           DC.B       0x2C                     ; ','
+  0x080064B8:  20           DC.B       0x20                     ; ' '
+  0x080064B9:  52           DC.B       0x52                     ; 'R'
+  0x080064BA:  65           DC.B       0x65                     ; 'e'
+  0x080064BB:  6C           DC.B       0x6C                     ; 'l'
+  0x080064BC:  61           DC.B       0x61                     ; 'a'
+  0x080064BD:  69           DC.B       0x69                     ; 'i'
+  0x080064BE:  73           DC.B       0x73                     ; 's'
+  0x080064BF:  20           DC.B       0x20                     ; ' '
+  0x080064C0:  6F           DC.B       0x6F                     ; 'o'
+  0x080064C1:  6E           DC.B       0x6E                     ; 'n'
+  0x080064C2:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23.134 from PowerPro_lto.o, size=22, align=1

+
+  0x080064C3:  4E           DC.B       0x4E                     ; 'N'
+  0x080064C4:  45           DC.B       0x45                     ; 'E'
+  0x080064C5:  57           DC.B       0x57                     ; 'W'
+  0x080064C6:  5F           DC.B       0x5F                     ; '_'
+  0x080064C7:  53           DC.B       0x53                     ; 'S'
+  0x080064C8:  54           DC.B       0x54                     ; 'T'
+  0x080064C9:  41           DC.B       0x41                     ; 'A'
+  0x080064CA:  54           DC.B       0x54                     ; 'T'
+  0x080064CB:  45           DC.B       0x45                     ; 'E'
+  0x080064CC:  3A           DC.B       0x3A                     ; ':'
+  0x080064CD:  20           DC.B       0x20                     ; ' '
+  0x080064CE:  4C           DC.B       0x4C                     ; 'L'
+  0x080064CF:  56           DC.B       0x56                     ; 'V'
+  0x080064D0:  50           DC.B       0x50                     ; 'P'
+  0x080064D1:  5F           DC.B       0x5F                     ; '_'
+  0x080064D2:  4F           DC.B       0x4F                     ; 'O'
+  0x080064D3:  56           DC.B       0x56                     ; 'V'
+  0x080064D4:  50           DC.B       0x50                     ; 'P'
+  0x080064D5:  5F           DC.B       0x5F                     ; '_'
+  0x080064D6:  4F           DC.B       0x4F                     ; 'O'
+  0x080064D7:  4E           DC.B       0x4E                     ; 'N'
+  0x080064D8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.10.139 from PowerPro_lto.o, size=26, align=1

+
+  0x080064D9:  4E           DC.B       0x4E                     ; 'N'
+  0x080064DA:  45           DC.B       0x45                     ; 'E'
+  0x080064DB:  57           DC.B       0x57                     ; 'W'
+  0x080064DC:  5F           DC.B       0x5F                     ; '_'
+  0x080064DD:  53           DC.B       0x53                     ; 'S'
+  0x080064DE:  54           DC.B       0x54                     ; 'T'
+  0x080064DF:  41           DC.B       0x41                     ; 'A'
+  0x080064E0:  54           DC.B       0x54                     ; 'T'
+  0x080064E1:  45           DC.B       0x45                     ; 'E'
+  0x080064E2:  3A           DC.B       0x3A                     ; ':'
+  0x080064E3:  20           DC.B       0x20                     ; ' '
+  0x080064E4:  4D           DC.B       0x4D                     ; 'M'
+  0x080064E5:  41           DC.B       0x41                     ; 'A'
+  0x080064E6:  49           DC.B       0x49                     ; 'I'
+  0x080064E7:  4E           DC.B       0x4E                     ; 'N'
+  0x080064E8:  53           DC.B       0x53                     ; 'S'
+  0x080064E9:  57           DC.B       0x57                     ; 'W'
+  0x080064EA:  49           DC.B       0x49                     ; 'I'
+  0x080064EB:  54           DC.B       0x54                     ; 'T'
+  0x080064EC:  43           DC.B       0x43                     ; 'C'
+  0x080064ED:  48           DC.B       0x48                     ; 'H'
+  0x080064EE:  5F           DC.B       0x5F                     ; '_'
+  0x080064EF:  4F           DC.B       0x4F                     ; 'O'
+  0x080064F0:  46           DC.B       0x46                     ; 'F'
+  0x080064F1:  46           DC.B       0x46                     ; 'F'
+  0x080064F2:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.146 from PowerPro_lto.o, size=30, align=1

+
+  0x080064F3:  4F           DC.B       0x4F                     ; 'O'
+  0x080064F4:  56           DC.B       0x56                     ; 'V'
+  0x080064F5:  50           DC.B       0x50                     ; 'P'
+  0x080064F6:  5F           DC.B       0x5F                     ; '_'
+  0x080064F7:  53           DC.B       0x53                     ; 'S'
+  0x080064F8:  4D           DC.B       0x4D                     ; 'M'
+  0x080064F9:  5F           DC.B       0x5F                     ; '_'
+  0x080064FA:  4F           DC.B       0x4F                     ; 'O'
+  0x080064FB:  66           DC.B       0x66                     ; 'f'
+  0x080064FC:  66           DC.B       0x66                     ; 'f'
+  0x080064FD:  3A           DC.B       0x3A                     ; ':'
+  0x080064FE:  20           DC.B       0x20                     ; ' '
+  0x080064FF:  4E           DC.B       0x4E                     ; 'N'
+  0x08006500:  45           DC.B       0x45                     ; 'E'
+  0x08006501:  57           DC.B       0x57                     ; 'W'
+  0x08006502:  5F           DC.B       0x5F                     ; '_'
+  0x08006503:  53           DC.B       0x53                     ; 'S'
+  0x08006504:  54           DC.B       0x54                     ; 'T'
+  0x08006505:  41           DC.B       0x41                     ; 'A'
+  0x08006506:  54           DC.B       0x54                     ; 'T'
+  0x08006507:  45           DC.B       0x45                     ; 'E'
+  0x08006508:  3A           DC.B       0x3A                     ; ':'
+  0x08006509:  20           DC.B       0x20                     ; ' '
+  0x0800650A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800650B:  56           DC.B       0x56                     ; 'V'
+  0x0800650C:  50           DC.B       0x50                     ; 'P'
+  0x0800650D:  5F           DC.B       0x5F                     ; '_'
+  0x0800650E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800650F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006510:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.20.155 from PowerPro_lto.o, size=38, align=1

+
+  0x08006511:  4E           DC.B       0x4E                     ; 'N'
+  0x08006512:  45           DC.B       0x45                     ; 'E'
+  0x08006513:  57           DC.B       0x57                     ; 'W'
+  0x08006514:  5F           DC.B       0x5F                     ; '_'
+  0x08006515:  53           DC.B       0x53                     ; 'S'
+  0x08006516:  54           DC.B       0x54                     ; 'T'
+  0x08006517:  41           DC.B       0x41                     ; 'A'
+  0x08006518:  54           DC.B       0x54                     ; 'T'
+  0x08006519:  45           DC.B       0x45                     ; 'E'
+  0x0800651A:  3A           DC.B       0x3A                     ; ':'
+  0x0800651B:  20           DC.B       0x20                     ; ' '
+  0x0800651C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800651D:  56           DC.B       0x56                     ; 'V'
+  0x0800651E:  50           DC.B       0x50                     ; 'P'
+  0x0800651F:  5F           DC.B       0x5F                     ; '_'
+  0x08006520:  4F           DC.B       0x4F                     ; 'O'
+  0x08006521:  56           DC.B       0x56                     ; 'V'
+  0x08006522:  50           DC.B       0x50                     ; 'P'
+  0x08006523:  5F           DC.B       0x5F                     ; '_'
+  0x08006524:  41           DC.B       0x41                     ; 'A'
+  0x08006525:  75           DC.B       0x75                     ; 'u'
+  0x08006526:  74           DC.B       0x74                     ; 't'
+  0x08006527:  6F           DC.B       0x6F                     ; 'o'
+  0x08006528:  20           DC.B       0x20                     ; ' '
+  0x08006529:  4F           DC.B       0x4F                     ; 'O'
+  0x0800652A:  6E           DC.B       0x6E                     ; 'n'
+  0x0800652B:  2C           DC.B       0x2C                     ; ','
+  0x0800652C:  20           DC.B       0x20                     ; ' '
+  0x0800652D:  52           DC.B       0x52                     ; 'R'
+  0x0800652E:  65           DC.B       0x65                     ; 'e'
+  0x0800652F:  6C           DC.B       0x6C                     ; 'l'
+  0x08006530:  61           DC.B       0x61                     ; 'a'
+  0x08006531:  69           DC.B       0x69                     ; 'i'
+  0x08006532:  73           DC.B       0x73                     ; 's'
+  0x08006533:  20           DC.B       0x20                     ; ' '
+  0x08006534:  6F           DC.B       0x6F                     ; 'o'
+  0x08006535:  6E           DC.B       0x6E                     ; 'n'
+  0x08006536:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23.157 from PowerPro_lto.o, size=18, align=1

+
+  0x08006537:  4E           DC.B       0x4E                     ; 'N'
+  0x08006538:  45           DC.B       0x45                     ; 'E'
+  0x08006539:  57           DC.B       0x57                     ; 'W'
+  0x0800653A:  5F           DC.B       0x5F                     ; '_'
+  0x0800653B:  53           DC.B       0x53                     ; 'S'
+  0x0800653C:  54           DC.B       0x54                     ; 'T'
+  0x0800653D:  41           DC.B       0x41                     ; 'A'
+  0x0800653E:  54           DC.B       0x54                     ; 'T'
+  0x0800653F:  45           DC.B       0x45                     ; 'E'
+  0x08006540:  3A           DC.B       0x3A                     ; ':'
+  0x08006541:  20           DC.B       0x20                     ; ' '
+  0x08006542:  4F           DC.B       0x4F                     ; 'O'
+  0x08006543:  56           DC.B       0x56                     ; 'V'
+  0x08006544:  50           DC.B       0x50                     ; 'P'
+  0x08006545:  5F           DC.B       0x5F                     ; '_'
+  0x08006546:  4F           DC.B       0x4F                     ; 'O'
+  0x08006547:  4E           DC.B       0x4E                     ; 'N'
+  0x08006548:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.16.172 from PowerPro_lto.o, size=34, align=1

+
+  0x08006549:  4E           DC.B       0x4E                     ; 'N'
+  0x0800654A:  45           DC.B       0x45                     ; 'E'
+  0x0800654B:  57           DC.B       0x57                     ; 'W'
+  0x0800654C:  5F           DC.B       0x5F                     ; '_'
+  0x0800654D:  53           DC.B       0x53                     ; 'S'
+  0x0800654E:  54           DC.B       0x54                     ; 'T'
+  0x0800654F:  41           DC.B       0x41                     ; 'A'
+  0x08006550:  54           DC.B       0x54                     ; 'T'
+  0x08006551:  45           DC.B       0x45                     ; 'E'
+  0x08006552:  3A           DC.B       0x3A                     ; ':'
+  0x08006553:  20           DC.B       0x20                     ; ' '
+  0x08006554:  53           DC.B       0x53                     ; 'S'
+  0x08006555:  45           DC.B       0x45                     ; 'E'
+  0x08006556:  43           DC.B       0x43                     ; 'C'
+  0x08006557:  4F           DC.B       0x4F                     ; 'O'
+  0x08006558:  4E           DC.B       0x4E                     ; 'N'
+  0x08006559:  44           DC.B       0x44                     ; 'D'
+  0x0800655A:  41           DC.B       0x41                     ; 'A'
+  0x0800655B:  52           DC.B       0x52                     ; 'R'
+  0x0800655C:  59           DC.B       0x59                     ; 'Y'
+  0x0800655D:  50           DC.B       0x50                     ; 'P'
+  0x0800655E:  52           DC.B       0x52                     ; 'R'
+  0x0800655F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006560:  54           DC.B       0x54                     ; 'T'
+  0x08006561:  45           DC.B       0x45                     ; 'E'
+  0x08006562:  43           DC.B       0x43                     ; 'C'
+  0x08006563:  54           DC.B       0x54                     ; 'T'
+  0x08006564:  49           DC.B       0x49                     ; 'I'
+  0x08006565:  4F           DC.B       0x4F                     ; 'O'
+  0x08006566:  4E           DC.B       0x4E                     ; 'N'
+  0x08006567:  5F           DC.B       0x5F                     ; '_'
+  0x08006568:  4F           DC.B       0x4F                     ; 'O'
+  0x08006569:  4E           DC.B       0x4E                     ; 'N'
+  0x0800656A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_day_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=58, align=1

+
+
__SEGGER_RTL_c_locale_day_names:
+  0x0800656B:  53           DC.B       0x53                     ; 'S'
+  0x0800656C:  75           DC.B       0x75                     ; 'u'
+  0x0800656D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800656E:  64           DC.B       0x64                     ; 'd'
+  0x0800656F:  61           DC.B       0x61                     ; 'a'
+  0x08006570:  79           DC.B       0x79                     ; 'y'
+  0x08006571:  00           DC.B       0x00                     ; '\0'
+  0x08006572:  4D           DC.B       0x4D                     ; 'M'
+  0x08006573:  6F           DC.B       0x6F                     ; 'o'
+  0x08006574:  6E           DC.B       0x6E                     ; 'n'
+  0x08006575:  64           DC.B       0x64                     ; 'd'
+  0x08006576:  61           DC.B       0x61                     ; 'a'
+  0x08006577:  79           DC.B       0x79                     ; 'y'
+  0x08006578:  00           DC.B       0x00                     ; '\0'
+  0x08006579:  54           DC.B       0x54                     ; 'T'
+  0x0800657A:  75           DC.B       0x75                     ; 'u'
+  0x0800657B:  65           DC.B       0x65                     ; 'e'
+  0x0800657C:  73           DC.B       0x73                     ; 's'
+  0x0800657D:  64           DC.B       0x64                     ; 'd'
+  0x0800657E:  61           DC.B       0x61                     ; 'a'
+  0x0800657F:  79           DC.B       0x79                     ; 'y'
+  0x08006580:  00           DC.B       0x00                     ; '\0'
+  0x08006581:  57           DC.B       0x57                     ; 'W'
+  0x08006582:  65           DC.B       0x65                     ; 'e'
+  0x08006583:  64           DC.B       0x64                     ; 'd'
+  0x08006584:  6E           DC.B       0x6E                     ; 'n'
+  0x08006585:  65           DC.B       0x65                     ; 'e'
+  0x08006586:  73           DC.B       0x73                     ; 's'
+  0x08006587:  64           DC.B       0x64                     ; 'd'
+  0x08006588:  61           DC.B       0x61                     ; 'a'
+  0x08006589:  79           DC.B       0x79                     ; 'y'
+  0x0800658A:  00           DC.B       0x00                     ; '\0'
+  0x0800658B:  54           DC.B       0x54                     ; 'T'
+  0x0800658C:  68           DC.B       0x68                     ; 'h'
+  0x0800658D:  75           DC.B       0x75                     ; 'u'
+  0x0800658E:  72           DC.B       0x72                     ; 'r'
+  0x0800658F:  73           DC.B       0x73                     ; 's'
+  0x08006590:  64           DC.B       0x64                     ; 'd'
+  0x08006591:  61           DC.B       0x61                     ; 'a'
+  0x08006592:  79           DC.B       0x79                     ; 'y'
+  0x08006593:  00           DC.B       0x00                     ; '\0'
+  0x08006594:  46           DC.B       0x46                     ; 'F'
+  0x08006595:  72           DC.B       0x72                     ; 'r'
+  0x08006596:  69           DC.B       0x69                     ; 'i'
+  0x08006597:  64           DC.B       0x64                     ; 'd'
+  0x08006598:  61           DC.B       0x61                     ; 'a'
+  0x08006599:  79           DC.B       0x79                     ; 'y'
+  0x0800659A:  00           DC.B       0x00                     ; '\0'
+  0x0800659B:  53           DC.B       0x53                     ; 'S'
+  0x0800659C:  61           DC.B       0x61                     ; 'a'
+  0x0800659D:  74           DC.B       0x74                     ; 't'
+  0x0800659E:  75           DC.B       0x75                     ; 'u'
+  0x0800659F:  72           DC.B       0x72                     ; 'r'
+  0x080065A0:  64           DC.B       0x64                     ; 'd'
+  0x080065A1:  61           DC.B       0x61                     ; 'a'
+  0x080065A2:  79           DC.B       0x79                     ; 'y'
+  0x080065A3:  00           DC.B       0x00                     ; '\0'
+  0x080065A4:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc..L.str from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=2, align=1

+
+  0x080065A5:  43           DC.B       0x43                     ; 'C'
+  0x080065A6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_data_utf8_period from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=2, align=1

+
+
__SEGGER_RTL_data_utf8_period:
+  0x080065A7:  2E           DC.B       0x2E                     ; '.'
+  0x080065A8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.4 from PowerPro_lto.o, size=17, align=1

+
+  0x080065A9:  42           DC.B       0x42                     ; 'B'
+  0x080065AA:  55           DC.B       0x55                     ; 'U'
+  0x080065AB:  54           DC.B       0x54                     ; 'T'
+  0x080065AC:  54           DC.B       0x54                     ; 'T'
+  0x080065AD:  4F           DC.B       0x4F                     ; 'O'
+  0x080065AE:  4E           DC.B       0x4E                     ; 'N'
+  0x080065AF:  3A           DC.B       0x3A                     ; ':'
+  0x080065B0:  20           DC.B       0x20                     ; ' '
+  0x080065B1:  4F           DC.B       0x4F                     ; 'O'
+  0x080065B2:  66           DC.B       0x66                     ; 'f'
+  0x080065B3:  66           DC.B       0x66                     ; 'f'
+  0x080065B4:  20           DC.B       0x20                     ; ' '
+  0x080065B5:  4D           DC.B       0x4D                     ; 'M'
+  0x080065B6:  6F           DC.B       0x6F                     ; 'o'
+  0x080065B7:  64           DC.B       0x64                     ; 'd'
+  0x080065B8:  65           DC.B       0x65                     ; 'e'
+  0x080065B9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12 from PowerPro_lto.o, size=25, align=1

+
+  0x080065BA:  6D           DC.B       0x6D                     ; 'm'
+  0x080065BB:  6F           DC.B       0x6F                     ; 'o'
+  0x080065BC:  64           DC.B       0x64                     ; 'd'
+  0x080065BD:  65           DC.B       0x65                     ; 'e'
+  0x080065BE:  20           DC.B       0x20                     ; ' '
+  0x080065BF:  6E           DC.B       0x6E                     ; 'n'
+  0x080065C0:  6F           DC.B       0x6F                     ; 'o'
+  0x080065C1:  74           DC.B       0x74                     ; 't'
+  0x080065C2:  20           DC.B       0x20                     ; ' '
+  0x080065C3:  79           DC.B       0x79                     ; 'y'
+  0x080065C4:  65           DC.B       0x65                     ; 'e'
+  0x080065C5:  74           DC.B       0x74                     ; 't'
+  0x080065C6:  20           DC.B       0x20                     ; ' '
+  0x080065C7:  69           DC.B       0x69                     ; 'i'
+  0x080065C8:  6D           DC.B       0x6D                     ; 'm'
+  0x080065C9:  70           DC.B       0x70                     ; 'p'
+  0x080065CA:  6C           DC.B       0x6C                     ; 'l'
+  0x080065CB:  65           DC.B       0x65                     ; 'e'
+  0x080065CC:  6D           DC.B       0x6D                     ; 'm'
+  0x080065CD:  65           DC.B       0x65                     ; 'e'
+  0x080065CE:  6E           DC.B       0x6E                     ; 'n'
+  0x080065CF:  74           DC.B       0x74                     ; 't'
+  0x080065D0:  65           DC.B       0x65                     ; 'e'
+  0x080065D1:  64           DC.B       0x64                     ; 'd'
+  0x080065D2:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.14 from PowerPro_lto.o, size=17, align=1

+
+  0x080065D3:  4A           DC.B       0x4A                     ; 'J'
+  0x080065D4:  75           DC.B       0x75                     ; 'u'
+  0x080065D5:  6D           DC.B       0x6D                     ; 'm'
+  0x080065D6:  70           DC.B       0x70                     ; 'p'
+  0x080065D7:  20           DC.B       0x20                     ; ' '
+  0x080065D8:  68           DC.B       0x68                     ; 'h'
+  0x080065D9:  61           DC.B       0x61                     ; 'a'
+  0x080065DA:  73           DC.B       0x73                     ; 's'
+  0x080065DB:  20           DC.B       0x20                     ; ' '
+  0x080065DC:  66           DC.B       0x66                     ; 'f'
+  0x080065DD:  61           DC.B       0x61                     ; 'a'
+  0x080065DE:  69           DC.B       0x69                     ; 'i'
+  0x080065DF:  6C           DC.B       0x6C                     ; 'l'
+  0x080065E0:  65           DC.B       0x65                     ; 'e'
+  0x080065E1:  64           DC.B       0x64                     ; 'd'
+  0x080065E2:  21           DC.B       0x21                     ; '!'
+  0x080065E3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.5 from PowerPro_lto.o, size=17, align=1

+
+  0x080065E4:  4D           DC.B       0x4D                     ; 'M'
+  0x080065E5:  42           DC.B       0x42                     ; 'B'
+  0x080065E6:  20           DC.B       0x20                     ; ' '
+  0x080065E7:  44           DC.B       0x44                     ; 'D'
+  0x080065E8:  4D           DC.B       0x4D                     ; 'M'
+  0x080065E9:  41           DC.B       0x41                     ; 'A'
+  0x080065EA:  20           DC.B       0x20                     ; ' '
+  0x080065EB:  45           DC.B       0x45                     ; 'E'
+  0x080065EC:  72           DC.B       0x72                     ; 'r'
+  0x080065ED:  72           DC.B       0x72                     ; 'r'
+  0x080065EE:  6F           DC.B       0x6F                     ; 'o'
+  0x080065EF:  72           DC.B       0x72                     ; 'r'
+  0x080065F0:  21           DC.B       0x21                     ; '!'
+  0x080065F1:  20           DC.B       0x20                     ; ' '
+  0x080065F2:  0A           DC.B       0x0A                     ; '\n'
+  0x080065F3:  0D           DC.B       0x0D                     ; '\r'
+  0x080065F4:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.6 from PowerPro_lto.o, size=17, align=1

+
+  0x080065F5:  4D           DC.B       0x4D                     ; 'M'
+  0x080065F6:  42           DC.B       0x42                     ; 'B'
+  0x080065F7:  20           DC.B       0x20                     ; ' '
+  0x080065F8:  4F           DC.B       0x4F                     ; 'O'
+  0x080065F9:  52           DC.B       0x52                     ; 'R'
+  0x080065FA:  45           DC.B       0x45                     ; 'E'
+  0x080065FB:  20           DC.B       0x20                     ; ' '
+  0x080065FC:  45           DC.B       0x45                     ; 'E'
+  0x080065FD:  72           DC.B       0x72                     ; 'r'
+  0x080065FE:  72           DC.B       0x72                     ; 'r'
+  0x080065FF:  6F           DC.B       0x6F                     ; 'o'
+  0x08006600:  72           DC.B       0x72                     ; 'r'
+  0x08006601:  21           DC.B       0x21                     ; '!'
+  0x08006602:  20           DC.B       0x20                     ; ' '
+  0x08006603:  0A           DC.B       0x0A                     ; '\n'
+  0x08006604:  0D           DC.B       0x0D                     ; '\r'
+  0x08006605:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.104 from PowerPro_lto.o, size=17, align=1

+
+  0x08006606:  45           DC.B       0x45                     ; 'E'
+  0x08006607:  52           DC.B       0x52                     ; 'R'
+  0x08006608:  52           DC.B       0x52                     ; 'R'
+  0x08006609:  4F           DC.B       0x4F                     ; 'O'
+  0x0800660A:  52           DC.B       0x52                     ; 'R'
+  0x0800660B:  20           DC.B       0x20                     ; ' '
+  0x0800660C:  55           DC.B       0x55                     ; 'U'
+  0x0800660D:  61           DC.B       0x61                     ; 'a'
+  0x0800660E:  72           DC.B       0x72                     ; 'r'
+  0x0800660F:  74           DC.B       0x74                     ; 't'
+  0x08006610:  20           DC.B       0x20                     ; ' '
+  0x08006611:  49           DC.B       0x49                     ; 'I'
+  0x08006612:  4E           DC.B       0x4E                     ; 'N'
+  0x08006613:  49           DC.B       0x49                     ; 'I'
+  0x08006614:  54           DC.B       0x54                     ; 'T'
+  0x08006615:  0D           DC.B       0x0D                     ; '\r'
+  0x08006616:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.118 from PowerPro_lto.o, size=45, align=1

+
+  0x08006617:  4C           DC.B       0x4C                     ; 'L'
+  0x08006618:  56           DC.B       0x56                     ; 'V'
+  0x08006619:  50           DC.B       0x50                     ; 'P'
+  0x0800661A:  5F           DC.B       0x5F                     ; '_'
+  0x0800661B:  53           DC.B       0x53                     ; 'S'
+  0x0800661C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800661D:  5F           DC.B       0x5F                     ; '_'
+  0x0800661E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800661F:  66           DC.B       0x66                     ; 'f'
+  0x08006620:  66           DC.B       0x66                     ; 'f'
+  0x08006621:  3A           DC.B       0x3A                     ; ':'
+  0x08006622:  20           DC.B       0x20                     ; ' '
+  0x08006623:  4E           DC.B       0x4E                     ; 'N'
+  0x08006624:  45           DC.B       0x45                     ; 'E'
+  0x08006625:  57           DC.B       0x57                     ; 'W'
+  0x08006626:  5F           DC.B       0x5F                     ; '_'
+  0x08006627:  53           DC.B       0x53                     ; 'S'
+  0x08006628:  54           DC.B       0x54                     ; 'T'
+  0x08006629:  41           DC.B       0x41                     ; 'A'
+  0x0800662A:  54           DC.B       0x54                     ; 'T'
+  0x0800662B:  45           DC.B       0x45                     ; 'E'
+  0x0800662C:  3A           DC.B       0x3A                     ; ':'
+  0x0800662D:  20           DC.B       0x20                     ; ' '
+  0x0800662E:  4C           DC.B       0x4C                     ; 'L'
+  0x0800662F:  56           DC.B       0x56                     ; 'V'
+  0x08006630:  50           DC.B       0x50                     ; 'P'
+  0x08006631:  5F           DC.B       0x5F                     ; '_'
+  0x08006632:  45           DC.B       0x45                     ; 'E'
+  0x08006633:  52           DC.B       0x52                     ; 'R'
+  0x08006634:  52           DC.B       0x52                     ; 'R'
+  0x08006635:  4F           DC.B       0x4F                     ; 'O'
+  0x08006636:  52           DC.B       0x52                     ; 'R'
+  0x08006637:  5F           DC.B       0x5F                     ; '_'
+  0x08006638:  46           DC.B       0x46                     ; 'F'
+  0x08006639:  41           DC.B       0x41                     ; 'A'
+  0x0800663A:  55           DC.B       0x55                     ; 'U'
+  0x0800663B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800663C:  54           DC.B       0x54                     ; 'T'
+  0x0800663D:  5F           DC.B       0x5F                     ; '_'
+  0x0800663E:  49           DC.B       0x49                     ; 'I'
+  0x0800663F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006640:  50           DC.B       0x50                     ; 'P'
+  0x08006641:  55           DC.B       0x55                     ; 'U'
+  0x08006642:  54           DC.B       0x54                     ; 'T'
+  0x08006643:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15 from PowerPro_lto.o, size=21, align=1

+
+  0x08006644:  4E           DC.B       0x4E                     ; 'N'
+  0x08006645:  45           DC.B       0x45                     ; 'E'
+  0x08006646:  57           DC.B       0x57                     ; 'W'
+  0x08006647:  5F           DC.B       0x5F                     ; '_'
+  0x08006648:  53           DC.B       0x53                     ; 'S'
+  0x08006649:  54           DC.B       0x54                     ; 'T'
+  0x0800664A:  41           DC.B       0x41                     ; 'A'
+  0x0800664B:  54           DC.B       0x54                     ; 'T'
+  0x0800664C:  45           DC.B       0x45                     ; 'E'
+  0x0800664D:  3A           DC.B       0x3A                     ; ':'
+  0x0800664E:  20           DC.B       0x20                     ; ' '
+  0x0800664F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006650:  56           DC.B       0x56                     ; 'V'
+  0x08006651:  50           DC.B       0x50                     ; 'P'
+  0x08006652:  5F           DC.B       0x5F                     ; '_'
+  0x08006653:  45           DC.B       0x45                     ; 'E'
+  0x08006654:  52           DC.B       0x52                     ; 'R'
+  0x08006655:  52           DC.B       0x52                     ; 'R'
+  0x08006656:  4F           DC.B       0x4F                     ; 'O'
+  0x08006657:  52           DC.B       0x52                     ; 'R'
+  0x08006658:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17 from PowerPro_lto.o, size=9, align=1

+
+  0x08006659:  4C           DC.B       0x4C                     ; 'L'
+  0x0800665A:  56           DC.B       0x56                     ; 'V'
+  0x0800665B:  50           DC.B       0x50                     ; 'P'
+  0x0800665C:  20           DC.B       0x20                     ; ' '
+  0x0800665D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800665E:  46           DC.B       0x46                     ; 'F'
+  0x0800665F:  46           DC.B       0x46                     ; 'F'
+  0x08006660:  21           DC.B       0x21                     ; '!'
+  0x08006661:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24 from PowerPro_lto.o, size=25, align=1

+
+  0x08006662:  4E           DC.B       0x4E                     ; 'N'
+  0x08006663:  45           DC.B       0x45                     ; 'E'
+  0x08006664:  57           DC.B       0x57                     ; 'W'
+  0x08006665:  5F           DC.B       0x5F                     ; '_'
+  0x08006666:  53           DC.B       0x53                     ; 'S'
+  0x08006667:  54           DC.B       0x54                     ; 'T'
+  0x08006668:  41           DC.B       0x41                     ; 'A'
+  0x08006669:  54           DC.B       0x54                     ; 'T'
+  0x0800666A:  45           DC.B       0x45                     ; 'E'
+  0x0800666B:  3A           DC.B       0x3A                     ; ':'
+  0x0800666C:  20           DC.B       0x20                     ; ' '
+  0x0800666D:  4C           DC.B       0x4C                     ; 'L'
+  0x0800666E:  56           DC.B       0x56                     ; 'V'
+  0x0800666F:  50           DC.B       0x50                     ; 'P'
+  0x08006670:  5F           DC.B       0x5F                     ; '_'
+  0x08006671:  4D           DC.B       0x4D                     ; 'M'
+  0x08006672:  41           DC.B       0x41                     ; 'A'
+  0x08006673:  4E           DC.B       0x4E                     ; 'N'
+  0x08006674:  55           DC.B       0x55                     ; 'U'
+  0x08006675:  41           DC.B       0x41                     ; 'A'
+  0x08006676:  4C           DC.B       0x4C                     ; 'L'
+  0x08006677:  5F           DC.B       0x5F                     ; '_'
+  0x08006678:  4F           DC.B       0x4F                     ; 'O'
+  0x08006679:  4E           DC.B       0x4E                     ; 'N'
+  0x0800667A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.124 from PowerPro_lto.o, size=53, align=1

+
+  0x0800667B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800667C:  56           DC.B       0x56                     ; 'V'
+  0x0800667D:  50           DC.B       0x50                     ; 'P'
+  0x0800667E:  5F           DC.B       0x5F                     ; '_'
+  0x0800667F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006680:  56           DC.B       0x56                     ; 'V'
+  0x08006681:  50           DC.B       0x50                     ; 'P'
+  0x08006682:  5F           DC.B       0x5F                     ; '_'
+  0x08006683:  53           DC.B       0x53                     ; 'S'
+  0x08006684:  4D           DC.B       0x4D                     ; 'M'
+  0x08006685:  5F           DC.B       0x5F                     ; '_'
+  0x08006686:  4F           DC.B       0x4F                     ; 'O'
+  0x08006687:  66           DC.B       0x66                     ; 'f'
+  0x08006688:  66           DC.B       0x66                     ; 'f'
+  0x08006689:  3A           DC.B       0x3A                     ; ':'
+  0x0800668A:  20           DC.B       0x20                     ; ' '
+  0x0800668B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800668C:  45           DC.B       0x45                     ; 'E'
+  0x0800668D:  57           DC.B       0x57                     ; 'W'
+  0x0800668E:  5F           DC.B       0x5F                     ; '_'
+  0x0800668F:  53           DC.B       0x53                     ; 'S'
+  0x08006690:  54           DC.B       0x54                     ; 'T'
+  0x08006691:  41           DC.B       0x41                     ; 'A'
+  0x08006692:  54           DC.B       0x54                     ; 'T'
+  0x08006693:  45           DC.B       0x45                     ; 'E'
+  0x08006694:  3A           DC.B       0x3A                     ; ':'
+  0x08006695:  20           DC.B       0x20                     ; ' '
+  0x08006696:  4C           DC.B       0x4C                     ; 'L'
+  0x08006697:  56           DC.B       0x56                     ; 'V'
+  0x08006698:  50           DC.B       0x50                     ; 'P'
+  0x08006699:  5F           DC.B       0x5F                     ; '_'
+  0x0800669A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800669B:  56           DC.B       0x56                     ; 'V'
+  0x0800669C:  50           DC.B       0x50                     ; 'P'
+  0x0800669D:  5F           DC.B       0x5F                     ; '_'
+  0x0800669E:  45           DC.B       0x45                     ; 'E'
+  0x0800669F:  52           DC.B       0x52                     ; 'R'
+  0x080066A0:  52           DC.B       0x52                     ; 'R'
+  0x080066A1:  4F           DC.B       0x4F                     ; 'O'
+  0x080066A2:  52           DC.B       0x52                     ; 'R'
+  0x080066A3:  5F           DC.B       0x5F                     ; '_'
+  0x080066A4:  46           DC.B       0x46                     ; 'F'
+  0x080066A5:  41           DC.B       0x41                     ; 'A'
+  0x080066A6:  55           DC.B       0x55                     ; 'U'
+  0x080066A7:  4C           DC.B       0x4C                     ; 'L'
+  0x080066A8:  54           DC.B       0x54                     ; 'T'
+  0x080066A9:  5F           DC.B       0x5F                     ; '_'
+  0x080066AA:  49           DC.B       0x49                     ; 'I'
+  0x080066AB:  4E           DC.B       0x4E                     ; 'N'
+  0x080066AC:  50           DC.B       0x50                     ; 'P'
+  0x080066AD:  55           DC.B       0x55                     ; 'U'
+  0x080066AE:  54           DC.B       0x54                     ; 'T'
+  0x080066AF:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.127 from PowerPro_lto.o, size=25, align=1

+
+  0x080066B0:  4E           DC.B       0x4E                     ; 'N'
+  0x080066B1:  45           DC.B       0x45                     ; 'E'
+  0x080066B2:  57           DC.B       0x57                     ; 'W'
+  0x080066B3:  5F           DC.B       0x5F                     ; '_'
+  0x080066B4:  53           DC.B       0x53                     ; 'S'
+  0x080066B5:  54           DC.B       0x54                     ; 'T'
+  0x080066B6:  41           DC.B       0x41                     ; 'A'
+  0x080066B7:  54           DC.B       0x54                     ; 'T'
+  0x080066B8:  45           DC.B       0x45                     ; 'E'
+  0x080066B9:  3A           DC.B       0x3A                     ; ':'
+  0x080066BA:  20           DC.B       0x20                     ; ' '
+  0x080066BB:  4C           DC.B       0x4C                     ; 'L'
+  0x080066BC:  56           DC.B       0x56                     ; 'V'
+  0x080066BD:  50           DC.B       0x50                     ; 'P'
+  0x080066BE:  5F           DC.B       0x5F                     ; '_'
+  0x080066BF:  4F           DC.B       0x4F                     ; 'O'
+  0x080066C0:  56           DC.B       0x56                     ; 'V'
+  0x080066C1:  50           DC.B       0x50                     ; 'P'
+  0x080066C2:  5F           DC.B       0x5F                     ; '_'
+  0x080066C3:  45           DC.B       0x45                     ; 'E'
+  0x080066C4:  52           DC.B       0x52                     ; 'R'
+  0x080066C5:  52           DC.B       0x52                     ; 'R'
+  0x080066C6:  4F           DC.B       0x4F                     ; 'O'
+  0x080066C7:  52           DC.B       0x52                     ; 'R'
+  0x080066C8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24.125 from PowerPro_lto.o, size=29, align=1

+
+  0x080066C9:  4E           DC.B       0x4E                     ; 'N'
+  0x080066CA:  45           DC.B       0x45                     ; 'E'
+  0x080066CB:  57           DC.B       0x57                     ; 'W'
+  0x080066CC:  5F           DC.B       0x5F                     ; '_'
+  0x080066CD:  53           DC.B       0x53                     ; 'S'
+  0x080066CE:  54           DC.B       0x54                     ; 'T'
+  0x080066CF:  41           DC.B       0x41                     ; 'A'
+  0x080066D0:  54           DC.B       0x54                     ; 'T'
+  0x080066D1:  45           DC.B       0x45                     ; 'E'
+  0x080066D2:  3A           DC.B       0x3A                     ; ':'
+  0x080066D3:  20           DC.B       0x20                     ; ' '
+  0x080066D4:  4C           DC.B       0x4C                     ; 'L'
+  0x080066D5:  56           DC.B       0x56                     ; 'V'
+  0x080066D6:  50           DC.B       0x50                     ; 'P'
+  0x080066D7:  5F           DC.B       0x5F                     ; '_'
+  0x080066D8:  4F           DC.B       0x4F                     ; 'O'
+  0x080066D9:  56           DC.B       0x56                     ; 'V'
+  0x080066DA:  50           DC.B       0x50                     ; 'P'
+  0x080066DB:  5F           DC.B       0x5F                     ; '_'
+  0x080066DC:  4D           DC.B       0x4D                     ; 'M'
+  0x080066DD:  41           DC.B       0x41                     ; 'A'
+  0x080066DE:  4E           DC.B       0x4E                     ; 'N'
+  0x080066DF:  55           DC.B       0x55                     ; 'U'
+  0x080066E0:  41           DC.B       0x41                     ; 'A'
+  0x080066E1:  4C           DC.B       0x4C                     ; 'L'
+  0x080066E2:  5F           DC.B       0x5F                     ; '_'
+  0x080066E3:  4F           DC.B       0x4F                     ; 'O'
+  0x080066E4:  4E           DC.B       0x4E                     ; 'N'
+  0x080066E5:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11.135 from PowerPro_lto.o, size=25, align=1

+
+  0x080066E6:  4E           DC.B       0x4E                     ; 'N'
+  0x080066E7:  45           DC.B       0x45                     ; 'E'
+  0x080066E8:  57           DC.B       0x57                     ; 'W'
+  0x080066E9:  5F           DC.B       0x5F                     ; '_'
+  0x080066EA:  53           DC.B       0x53                     ; 'S'
+  0x080066EB:  54           DC.B       0x54                     ; 'T'
+  0x080066EC:  41           DC.B       0x41                     ; 'A'
+  0x080066ED:  54           DC.B       0x54                     ; 'T'
+  0x080066EE:  45           DC.B       0x45                     ; 'E'
+  0x080066EF:  3A           DC.B       0x3A                     ; ':'
+  0x080066F0:  20           DC.B       0x20                     ; ' '
+  0x080066F1:  4D           DC.B       0x4D                     ; 'M'
+  0x080066F2:  41           DC.B       0x41                     ; 'A'
+  0x080066F3:  49           DC.B       0x49                     ; 'I'
+  0x080066F4:  4E           DC.B       0x4E                     ; 'N'
+  0x080066F5:  53           DC.B       0x53                     ; 'S'
+  0x080066F6:  57           DC.B       0x57                     ; 'W'
+  0x080066F7:  49           DC.B       0x49                     ; 'I'
+  0x080066F8:  54           DC.B       0x54                     ; 'T'
+  0x080066F9:  43           DC.B       0x43                     ; 'C'
+  0x080066FA:  48           DC.B       0x48                     ; 'H'
+  0x080066FB:  5F           DC.B       0x5F                     ; '_'
+  0x080066FC:  4F           DC.B       0x4F                     ; 'O'
+  0x080066FD:  4E           DC.B       0x4E                     ; 'N'
+  0x080066FE:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.147 from PowerPro_lto.o, size=45, align=1

+
+  0x080066FF:  4F           DC.B       0x4F                     ; 'O'
+  0x08006700:  56           DC.B       0x56                     ; 'V'
+  0x08006701:  50           DC.B       0x50                     ; 'P'
+  0x08006702:  5F           DC.B       0x5F                     ; '_'
+  0x08006703:  53           DC.B       0x53                     ; 'S'
+  0x08006704:  4D           DC.B       0x4D                     ; 'M'
+  0x08006705:  5F           DC.B       0x5F                     ; '_'
+  0x08006706:  4F           DC.B       0x4F                     ; 'O'
+  0x08006707:  66           DC.B       0x66                     ; 'f'
+  0x08006708:  66           DC.B       0x66                     ; 'f'
+  0x08006709:  3A           DC.B       0x3A                     ; ':'
+  0x0800670A:  20           DC.B       0x20                     ; ' '
+  0x0800670B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800670C:  45           DC.B       0x45                     ; 'E'
+  0x0800670D:  57           DC.B       0x57                     ; 'W'
+  0x0800670E:  5F           DC.B       0x5F                     ; '_'
+  0x0800670F:  53           DC.B       0x53                     ; 'S'
+  0x08006710:  54           DC.B       0x54                     ; 'T'
+  0x08006711:  41           DC.B       0x41                     ; 'A'
+  0x08006712:  54           DC.B       0x54                     ; 'T'
+  0x08006713:  45           DC.B       0x45                     ; 'E'
+  0x08006714:  3A           DC.B       0x3A                     ; ':'
+  0x08006715:  20           DC.B       0x20                     ; ' '
+  0x08006716:  4F           DC.B       0x4F                     ; 'O'
+  0x08006717:  56           DC.B       0x56                     ; 'V'
+  0x08006718:  50           DC.B       0x50                     ; 'P'
+  0x08006719:  5F           DC.B       0x5F                     ; '_'
+  0x0800671A:  45           DC.B       0x45                     ; 'E'
+  0x0800671B:  52           DC.B       0x52                     ; 'R'
+  0x0800671C:  52           DC.B       0x52                     ; 'R'
+  0x0800671D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800671E:  52           DC.B       0x52                     ; 'R'
+  0x0800671F:  5F           DC.B       0x5F                     ; '_'
+  0x08006720:  46           DC.B       0x46                     ; 'F'
+  0x08006721:  41           DC.B       0x41                     ; 'A'
+  0x08006722:  55           DC.B       0x55                     ; 'U'
+  0x08006723:  4C           DC.B       0x4C                     ; 'L'
+  0x08006724:  54           DC.B       0x54                     ; 'T'
+  0x08006725:  5F           DC.B       0x5F                     ; '_'
+  0x08006726:  49           DC.B       0x49                     ; 'I'
+  0x08006727:  4E           DC.B       0x4E                     ; 'N'
+  0x08006728:  50           DC.B       0x50                     ; 'P'
+  0x08006729:  55           DC.B       0x55                     ; 'U'
+  0x0800672A:  54           DC.B       0x54                     ; 'T'
+  0x0800672B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.150 from PowerPro_lto.o, size=21, align=1

+
+  0x0800672C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800672D:  45           DC.B       0x45                     ; 'E'
+  0x0800672E:  57           DC.B       0x57                     ; 'W'
+  0x0800672F:  5F           DC.B       0x5F                     ; '_'
+  0x08006730:  53           DC.B       0x53                     ; 'S'
+  0x08006731:  54           DC.B       0x54                     ; 'T'
+  0x08006732:  41           DC.B       0x41                     ; 'A'
+  0x08006733:  54           DC.B       0x54                     ; 'T'
+  0x08006734:  45           DC.B       0x45                     ; 'E'
+  0x08006735:  3A           DC.B       0x3A                     ; ':'
+  0x08006736:  20           DC.B       0x20                     ; ' '
+  0x08006737:  4F           DC.B       0x4F                     ; 'O'
+  0x08006738:  56           DC.B       0x56                     ; 'V'
+  0x08006739:  50           DC.B       0x50                     ; 'P'
+  0x0800673A:  5F           DC.B       0x5F                     ; '_'
+  0x0800673B:  45           DC.B       0x45                     ; 'E'
+  0x0800673C:  52           DC.B       0x52                     ; 'R'
+  0x0800673D:  52           DC.B       0x52                     ; 'R'
+  0x0800673E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800673F:  52           DC.B       0x52                     ; 'R'
+  0x08006740:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17.152 from PowerPro_lto.o, size=9, align=1

+
+  0x08006741:  4F           DC.B       0x4F                     ; 'O'
+  0x08006742:  56           DC.B       0x56                     ; 'V'
+  0x08006743:  50           DC.B       0x50                     ; 'P'
+  0x08006744:  20           DC.B       0x20                     ; ' '
+  0x08006745:  4F           DC.B       0x4F                     ; 'O'
+  0x08006746:  46           DC.B       0x46                     ; 'F'
+  0x08006747:  46           DC.B       0x46                     ; 'F'
+  0x08006748:  21           DC.B       0x21                     ; '!'
+  0x08006749:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24.148 from PowerPro_lto.o, size=25, align=1

+
+  0x0800674A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800674B:  45           DC.B       0x45                     ; 'E'
+  0x0800674C:  57           DC.B       0x57                     ; 'W'
+  0x0800674D:  5F           DC.B       0x5F                     ; '_'
+  0x0800674E:  53           DC.B       0x53                     ; 'S'
+  0x0800674F:  54           DC.B       0x54                     ; 'T'
+  0x08006750:  41           DC.B       0x41                     ; 'A'
+  0x08006751:  54           DC.B       0x54                     ; 'T'
+  0x08006752:  45           DC.B       0x45                     ; 'E'
+  0x08006753:  3A           DC.B       0x3A                     ; ':'
+  0x08006754:  20           DC.B       0x20                     ; ' '
+  0x08006755:  4F           DC.B       0x4F                     ; 'O'
+  0x08006756:  56           DC.B       0x56                     ; 'V'
+  0x08006757:  50           DC.B       0x50                     ; 'P'
+  0x08006758:  5F           DC.B       0x5F                     ; '_'
+  0x08006759:  4D           DC.B       0x4D                     ; 'M'
+  0x0800675A:  41           DC.B       0x41                     ; 'A'
+  0x0800675B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800675C:  55           DC.B       0x55                     ; 'U'
+  0x0800675D:  41           DC.B       0x41                     ; 'A'
+  0x0800675E:  4C           DC.B       0x4C                     ; 'L'
+  0x0800675F:  5F           DC.B       0x5F                     ; '_'
+  0x08006760:  4F           DC.B       0x4F                     ; 'O'
+  0x08006761:  4E           DC.B       0x4E                     ; 'N'
+  0x08006762:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.162 from PowerPro_lto.o, size=41, align=1

+
+  0x08006763:  4E           DC.B       0x4E                     ; 'N'
+  0x08006764:  45           DC.B       0x45                     ; 'E'
+  0x08006765:  57           DC.B       0x57                     ; 'W'
+  0x08006766:  5F           DC.B       0x5F                     ; '_'
+  0x08006767:  53           DC.B       0x53                     ; 'S'
+  0x08006768:  54           DC.B       0x54                     ; 'T'
+  0x08006769:  41           DC.B       0x41                     ; 'A'
+  0x0800676A:  54           DC.B       0x54                     ; 'T'
+  0x0800676B:  45           DC.B       0x45                     ; 'E'
+  0x0800676C:  3A           DC.B       0x3A                     ; ':'
+  0x0800676D:  20           DC.B       0x20                     ; ' '
+  0x0800676E:  53           DC.B       0x53                     ; 'S'
+  0x0800676F:  45           DC.B       0x45                     ; 'E'
+  0x08006770:  43           DC.B       0x43                     ; 'C'
+  0x08006771:  4F           DC.B       0x4F                     ; 'O'
+  0x08006772:  4E           DC.B       0x4E                     ; 'N'
+  0x08006773:  44           DC.B       0x44                     ; 'D'
+  0x08006774:  41           DC.B       0x41                     ; 'A'
+  0x08006775:  52           DC.B       0x52                     ; 'R'
+  0x08006776:  59           DC.B       0x59                     ; 'Y'
+  0x08006777:  50           DC.B       0x50                     ; 'P'
+  0x08006778:  52           DC.B       0x52                     ; 'R'
+  0x08006779:  4F           DC.B       0x4F                     ; 'O'
+  0x0800677A:  54           DC.B       0x54                     ; 'T'
+  0x0800677B:  45           DC.B       0x45                     ; 'E'
+  0x0800677C:  43           DC.B       0x43                     ; 'C'
+  0x0800677D:  54           DC.B       0x54                     ; 'T'
+  0x0800677E:  49           DC.B       0x49                     ; 'I'
+  0x0800677F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006780:  4E           DC.B       0x4E                     ; 'N'
+  0x08006781:  5F           DC.B       0x5F                     ; '_'
+  0x08006782:  4D           DC.B       0x4D                     ; 'M'
+  0x08006783:  41           DC.B       0x41                     ; 'A'
+  0x08006784:  4E           DC.B       0x4E                     ; 'N'
+  0x08006785:  55           DC.B       0x55                     ; 'U'
+  0x08006786:  41           DC.B       0x41                     ; 'A'
+  0x08006787:  4C           DC.B       0x4C                     ; 'L'
+  0x08006788:  5F           DC.B       0x5F                     ; '_'
+  0x08006789:  4F           DC.B       0x4F                     ; 'O'
+  0x0800678A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800678B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.9.178 from PowerPro_lto.o, size=29, align=1

+
+  0x0800678C:  46           DC.B       0x46                     ; 'F'
+  0x0800678D:  41           DC.B       0x41                     ; 'A'
+  0x0800678E:  55           DC.B       0x55                     ; 'U'
+  0x0800678F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006790:  54           DC.B       0x54                     ; 'T'
+  0x08006791:  20           DC.B       0x20                     ; ' '
+  0x08006792:  56           DC.B       0x56                     ; 'V'
+  0x08006793:  4F           DC.B       0x4F                     ; 'O'
+  0x08006794:  4C           DC.B       0x4C                     ; 'L'
+  0x08006795:  54           DC.B       0x54                     ; 'T'
+  0x08006796:  41           DC.B       0x41                     ; 'A'
+  0x08006797:  47           DC.B       0x47                     ; 'G'
+  0x08006798:  45           DC.B       0x45                     ; 'E'
+  0x08006799:  20           DC.B       0x20                     ; ' '
+  0x0800679A:  44           DC.B       0x44                     ; 'D'
+  0x0800679B:  52           DC.B       0x52                     ; 'R'
+  0x0800679C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800679D:  50           DC.B       0x50                     ; 'P'
+  0x0800679E:  20           DC.B       0x20                     ; ' '
+  0x0800679F:  44           DC.B       0x44                     ; 'D'
+  0x080067A0:  45           DC.B       0x45                     ; 'E'
+  0x080067A1:  54           DC.B       0x54                     ; 'T'
+  0x080067A2:  45           DC.B       0x45                     ; 'E'
+  0x080067A3:  43           DC.B       0x43                     ; 'C'
+  0x080067A4:  54           DC.B       0x54                     ; 'T'
+  0x080067A5:  45           DC.B       0x45                     ; 'E'
+  0x080067A6:  44           DC.B       0x44                     ; 'D'
+  0x080067A7:  21           DC.B       0x21                     ; '!'
+  0x080067A8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.173 from PowerPro_lto.o, size=37, align=1

+
+  0x080067A9:  4E           DC.B       0x4E                     ; 'N'
+  0x080067AA:  45           DC.B       0x45                     ; 'E'
+  0x080067AB:  57           DC.B       0x57                     ; 'W'
+  0x080067AC:  5F           DC.B       0x5F                     ; '_'
+  0x080067AD:  53           DC.B       0x53                     ; 'S'
+  0x080067AE:  54           DC.B       0x54                     ; 'T'
+  0x080067AF:  41           DC.B       0x41                     ; 'A'
+  0x080067B0:  54           DC.B       0x54                     ; 'T'
+  0x080067B1:  45           DC.B       0x45                     ; 'E'
+  0x080067B2:  3A           DC.B       0x3A                     ; ':'
+  0x080067B3:  20           DC.B       0x20                     ; ' '
+  0x080067B4:  53           DC.B       0x53                     ; 'S'
+  0x080067B5:  45           DC.B       0x45                     ; 'E'
+  0x080067B6:  43           DC.B       0x43                     ; 'C'
+  0x080067B7:  4F           DC.B       0x4F                     ; 'O'
+  0x080067B8:  4E           DC.B       0x4E                     ; 'N'
+  0x080067B9:  44           DC.B       0x44                     ; 'D'
+  0x080067BA:  41           DC.B       0x41                     ; 'A'
+  0x080067BB:  52           DC.B       0x52                     ; 'R'
+  0x080067BC:  59           DC.B       0x59                     ; 'Y'
+  0x080067BD:  50           DC.B       0x50                     ; 'P'
+  0x080067BE:  52           DC.B       0x52                     ; 'R'
+  0x080067BF:  4F           DC.B       0x4F                     ; 'O'
+  0x080067C0:  54           DC.B       0x54                     ; 'T'
+  0x080067C1:  45           DC.B       0x45                     ; 'E'
+  0x080067C2:  43           DC.B       0x43                     ; 'C'
+  0x080067C3:  54           DC.B       0x54                     ; 'T'
+  0x080067C4:  49           DC.B       0x49                     ; 'I'
+  0x080067C5:  4F           DC.B       0x4F                     ; 'O'
+  0x080067C6:  4E           DC.B       0x4E                     ; 'N'
+  0x080067C7:  5F           DC.B       0x5F                     ; '_'
+  0x080067C8:  45           DC.B       0x45                     ; 'E'
+  0x080067C9:  52           DC.B       0x52                     ; 'R'
+  0x080067CA:  52           DC.B       0x52                     ; 'R'
+  0x080067CB:  4F           DC.B       0x4F                     ; 'O'
+  0x080067CC:  52           DC.B       0x52                     ; 'R'
+  0x080067CD:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str from PowerPro_lto.o, size=9, align=1

+
+  0x080067CE:  6D           DC.B       0x6D                     ; 'm'
+  0x080067CF:  6F           DC.B       0x6F                     ; 'o'
+  0x080067D0:  64           DC.B       0x64                     ; 'd'
+  0x080067D1:  65           DC.B       0x65                     ; 'e'
+  0x080067D2:  3D           DC.B       0x3D                     ; '='
+  0x080067D3:  25           DC.B       0x25                     ; '%'
+  0x080067D4:  69           DC.B       0x69                     ; 'i'
+  0x080067D5:  0A           DC.B       0x0A                     ; '\n'
+  0x080067D6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc._DoInit._aInitStr from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=17, align=1

+
+
_DoInit._aInitStr:
+  0x080067D7:  00           DC.B       0x00                     ; '\0'
+  0x080067D8:  00           DC.B       0x00                     ; '\0'
+  0x080067D9:  00           DC.B       0x00                     ; '\0'
+  0x080067DA:  00           DC.B       0x00                     ; '\0'
+  0x080067DB:  00           DC.B       0x00                     ; '\0'
+  0x080067DC:  00           DC.B       0x00                     ; '\0'
+  0x080067DD:  54           DC.B       0x54                     ; 'T'
+  0x080067DE:  54           DC.B       0x54                     ; 'T'
+  0x080067DF:  52           DC.B       0x52                     ; 'R'
+  0x080067E0:  20           DC.B       0x20                     ; ' '
+  0x080067E1:  52           DC.B       0x52                     ; 'R'
+  0x080067E2:  45           DC.B       0x45                     ; 'E'
+  0x080067E3:  47           DC.B       0x47                     ; 'G'
+  0x080067E4:  47           DC.B       0x47                     ; 'G'
+  0x080067E5:  45           DC.B       0x45                     ; 'E'
+  0x080067E6:  53           DC.B       0x53                     ; 'S'
+  0x080067E7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc..L.str from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=9, align=1

+
+  0x080067E8:  54           DC.B       0x54                     ; 'T'
+  0x080067E9:  65           DC.B       0x65                     ; 'e'
+  0x080067EA:  72           DC.B       0x72                     ; 'r'
+  0x080067EB:  6D           DC.B       0x6D                     ; 'm'
+  0x080067EC:  69           DC.B       0x69                     ; 'i'
+  0x080067ED:  6E           DC.B       0x6E                     ; 'n'
+  0x080067EE:  61           DC.B       0x61                     ; 'a'
+  0x080067EF:  6C           DC.B       0x6C                     ; 'l'
+  0x080067F0:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_date_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=9, align=1

+
+
__SEGGER_RTL_c_locale_date_format:
+  0x080067F1:  25           DC.B       0x25                     ; '%'
+  0x080067F2:  6D           DC.B       0x6D                     ; 'm'
+  0x080067F3:  2F           DC.B       0x2F                     ; '/'
+  0x080067F4:  25           DC.B       0x25                     ; '%'
+  0x080067F5:  64           DC.B       0x64                     ; 'd'
+  0x080067F6:  2F           DC.B       0x2F                     ; '/'
+  0x080067F7:  25           DC.B       0x25                     ; '%'
+  0x080067F8:  79           DC.B       0x79                     ; 'y'
+  0x080067F9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_time_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=9, align=1

+
+
__SEGGER_RTL_c_locale_time_format:
+  0x080067FA:  25           DC.B       0x25                     ; '%'
+  0x080067FB:  48           DC.B       0x48                     ; 'H'
+  0x080067FC:  3A           DC.B       0x3A                     ; ':'
+  0x080067FD:  25           DC.B       0x25                     ; '%'
+  0x080067FE:  4D           DC.B       0x4D                     ; 'M'
+  0x080067FF:  3A           DC.B       0x3A                     ; ':'
+  0x08006800:  25           DC.B       0x25                     ; '%'
+  0x08006801:  53           DC.B       0x53                     ; 'S'
+  0x08006802:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_abbrev_day_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=29, align=1

+
+
__SEGGER_RTL_c_locale_abbrev_day_names:
+  0x08006803:  53           DC.B       0x53                     ; 'S'
+  0x08006804:  75           DC.B       0x75                     ; 'u'
+  0x08006805:  6E           DC.B       0x6E                     ; 'n'
+  0x08006806:  00           DC.B       0x00                     ; '\0'
+  0x08006807:  4D           DC.B       0x4D                     ; 'M'
+  0x08006808:  6F           DC.B       0x6F                     ; 'o'
+  0x08006809:  6E           DC.B       0x6E                     ; 'n'
+  0x0800680A:  00           DC.B       0x00                     ; '\0'
+  0x0800680B:  54           DC.B       0x54                     ; 'T'
+  0x0800680C:  75           DC.B       0x75                     ; 'u'
+  0x0800680D:  65           DC.B       0x65                     ; 'e'
+  0x0800680E:  00           DC.B       0x00                     ; '\0'
+  0x0800680F:  57           DC.B       0x57                     ; 'W'
+  0x08006810:  65           DC.B       0x65                     ; 'e'
+  0x08006811:  64           DC.B       0x64                     ; 'd'
+  0x08006812:  00           DC.B       0x00                     ; '\0'
+  0x08006813:  54           DC.B       0x54                     ; 'T'
+  0x08006814:  68           DC.B       0x68                     ; 'h'
+  0x08006815:  75           DC.B       0x75                     ; 'u'
+  0x08006816:  00           DC.B       0x00                     ; '\0'
+  0x08006817:  46           DC.B       0x46                     ; 'F'
+  0x08006818:  72           DC.B       0x72                     ; 'r'
+  0x08006819:  69           DC.B       0x69                     ; 'i'
+  0x0800681A:  00           DC.B       0x00                     ; '\0'
+  0x0800681B:  53           DC.B       0x53                     ; 'S'
+  0x0800681C:  61           DC.B       0x61                     ; 'a'
+  0x0800681D:  74           DC.B       0x74                     ; 't'
+  0x0800681E:  00           DC.B       0x00                     ; '\0'
+  0x0800681F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_abbrev_month_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=49, align=1

+
+
__SEGGER_RTL_c_locale_abbrev_month_names:
+  0x08006820:  4A           DC.B       0x4A                     ; 'J'
+  0x08006821:  61           DC.B       0x61                     ; 'a'
+  0x08006822:  6E           DC.B       0x6E                     ; 'n'
+  0x08006823:  00           DC.B       0x00                     ; '\0'
+  0x08006824:  46           DC.B       0x46                     ; 'F'
+  0x08006825:  65           DC.B       0x65                     ; 'e'
+  0x08006826:  62           DC.B       0x62                     ; 'b'
+  0x08006827:  00           DC.B       0x00                     ; '\0'
+  0x08006828:  4D           DC.B       0x4D                     ; 'M'
+  0x08006829:  61           DC.B       0x61                     ; 'a'
+  0x0800682A:  72           DC.B       0x72                     ; 'r'
+  0x0800682B:  00           DC.B       0x00                     ; '\0'
+  0x0800682C:  41           DC.B       0x41                     ; 'A'
+  0x0800682D:  70           DC.B       0x70                     ; 'p'
+  0x0800682E:  72           DC.B       0x72                     ; 'r'
+  0x0800682F:  00           DC.B       0x00                     ; '\0'
+  0x08006830:  4D           DC.B       0x4D                     ; 'M'
+  0x08006831:  61           DC.B       0x61                     ; 'a'
+  0x08006832:  79           DC.B       0x79                     ; 'y'
+  0x08006833:  00           DC.B       0x00                     ; '\0'
+  0x08006834:  4A           DC.B       0x4A                     ; 'J'
+  0x08006835:  75           DC.B       0x75                     ; 'u'
+  0x08006836:  6E           DC.B       0x6E                     ; 'n'
+  0x08006837:  00           DC.B       0x00                     ; '\0'
+  0x08006838:  4A           DC.B       0x4A                     ; 'J'
+  0x08006839:  75           DC.B       0x75                     ; 'u'
+  0x0800683A:  6C           DC.B       0x6C                     ; 'l'
+  0x0800683B:  00           DC.B       0x00                     ; '\0'
+  0x0800683C:  41           DC.B       0x41                     ; 'A'
+  0x0800683D:  75           DC.B       0x75                     ; 'u'
+  0x0800683E:  67           DC.B       0x67                     ; 'g'
+  0x0800683F:  00           DC.B       0x00                     ; '\0'
+  0x08006840:  53           DC.B       0x53                     ; 'S'
+  0x08006841:  65           DC.B       0x65                     ; 'e'
+  0x08006842:  70           DC.B       0x70                     ; 'p'
+  0x08006843:  00           DC.B       0x00                     ; '\0'
+  0x08006844:  4F           DC.B       0x4F                     ; 'O'
+  0x08006845:  63           DC.B       0x63                     ; 'c'
+  0x08006846:  74           DC.B       0x74                     ; 't'
+  0x08006847:  00           DC.B       0x00                     ; '\0'
+  0x08006848:  4E           DC.B       0x4E                     ; 'N'
+  0x08006849:  6F           DC.B       0x6F                     ; 'o'
+  0x0800684A:  76           DC.B       0x76                     ; 'v'
+  0x0800684B:  00           DC.B       0x00                     ; '\0'
+  0x0800684C:  44           DC.B       0x44                     ; 'D'
+  0x0800684D:  65           DC.B       0x65                     ; 'e'
+  0x0800684E:  63           DC.B       0x63                     ; 'c'
+  0x0800684F:  00           DC.B       0x00                     ; '\0'
+  0x08006850:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_data_empty_string from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=1, align=1

+
+
__SEGGER_RTL_data_empty_string:
+  0x08006851:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_ascii_ctype_mask from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=13, align=1

+
+
__SEGGER_RTL_ascii_ctype_mask:
+  0x08006852:  00           DC.B       0x00                     ; '\0'
+  0x08006853:  07           DC.B       0x07                     ; '\x07'
+  0x08006854:  03           DC.B       0x03                     ; '\x03'
+  0x08006855:  20           DC.B       0x20                     ; ' '
+  0x08006856:  04           DC.B       0x04                     ; '\x04'
+  0x08006857:  17           DC.B       0x17                     ; '\x17'
+  0x08006858:  02           DC.B       0x02                     ; '\x02'
+  0x08006859:  01           DC.B       0x01                     ; '\x01'
+  0x0800685A:  08           DC.B       0x08                     ; '\b'
+  0x0800685B:  57           DC.B       0x57                     ; 'W'
+  0x0800685C:  10           DC.B       0x10                     ; '\x10'
+  0x0800685D:  40           DC.B       0x40                     ; '@'
+  0x0800685E:  80           DC.B       0x80                     ; '\x80'
+
+

Section .init_array from STM32C0xx_Startup.o, size=4, align=4

+
+  0x08006860:  08000605     DC.W       SystemCoreClockUpdate
+
+

Section .rodata.UARTEx_SetNbDataToProcess.numerator from PowerPro_lto.o, size=8, align=1

+
+
UARTEx_SetNbDataToProcess.numerator:
+  0x08006864:  01           DC.B       0x01                     ; '\x01'
+  0x08006865:  01           DC.B       0x01                     ; '\x01'
+  0x08006866:  01           DC.B       0x01                     ; '\x01'
+  0x08006867:  03           DC.B       0x03                     ; '\x03'
+  0x08006868:  07           DC.B       0x07                     ; '\x07'
+  0x08006869:  01           DC.B       0x01                     ; '\x01'
+  0x0800686A:  00           DC.B       0x00                     ; '\0'
+  0x0800686B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.UARTEx_SetNbDataToProcess.denominator from PowerPro_lto.o, size=8, align=1

+
+
UARTEx_SetNbDataToProcess.denominator:
+  0x0800686C:  08           DC.B       0x08                     ; '\b'
+  0x0800686D:  04           DC.B       0x04                     ; '\x04'
+  0x0800686E:  02           DC.B       0x02                     ; '\x02'
+  0x0800686F:  04           DC.B       0x04                     ; '\x04'
+  0x08006870:  08           DC.B       0x08                     ; '\b'
+  0x08006871:  01           DC.B       0x01                     ; '\x01'
+  0x08006872:  01           DC.B       0x01                     ; '\x01'
+  0x08006873:  01           DC.B       0x01                     ; '\x01'
+
+

Section .rodata..Lstr.3 from PowerPro_lto.o, size=28, align=1

+
+  0x08006874:  42           DC.B       0x42                     ; 'B'
+  0x08006875:  55           DC.B       0x55                     ; 'U'
+  0x08006876:  54           DC.B       0x54                     ; 'T'
+  0x08006877:  54           DC.B       0x54                     ; 'T'
+  0x08006878:  4F           DC.B       0x4F                     ; 'O'
+  0x08006879:  4E           DC.B       0x4E                     ; 'N'
+  0x0800687A:  3A           DC.B       0x3A                     ; ':'
+  0x0800687B:  20           DC.B       0x20                     ; ' '
+  0x0800687C:  41           DC.B       0x41                     ; 'A'
+  0x0800687D:  75           DC.B       0x75                     ; 'u'
+  0x0800687E:  74           DC.B       0x74                     ; 't'
+  0x0800687F:  6F           DC.B       0x6F                     ; 'o'
+  0x08006880:  20           DC.B       0x20                     ; ' '
+  0x08006881:  4D           DC.B       0x4D                     ; 'M'
+  0x08006882:  6F           DC.B       0x6F                     ; 'o'
+  0x08006883:  64           DC.B       0x64                     ; 'd'
+  0x08006884:  65           DC.B       0x65                     ; 'e'
+  0x08006885:  20           DC.B       0x20                     ; ' '
+  0x08006886:  4D           DC.B       0x4D                     ; 'M'
+  0x08006887:  61           DC.B       0x61                     ; 'a'
+  0x08006888:  6E           DC.B       0x6E                     ; 'n'
+  0x08006889:  75           DC.B       0x75                     ; 'u'
+  0x0800688A:  61           DC.B       0x61                     ; 'a'
+  0x0800688B:  6C           DC.B       0x6C                     ; 'l'
+  0x0800688C:  20           DC.B       0x20                     ; ' '
+  0x0800688D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800688E:  6E           DC.B       0x6E                     ; 'n'
+  0x0800688F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11 from PowerPro_lto.o, size=20, align=1

+
+  0x08006890:  64           DC.B       0x64                     ; 'd'
+  0x08006891:  65           DC.B       0x65                     ; 'e'
+  0x08006892:  62           DC.B       0x62                     ; 'b'
+  0x08006893:  75           DC.B       0x75                     ; 'u'
+  0x08006894:  67           DC.B       0x67                     ; 'g'
+  0x08006895:  20           DC.B       0x20                     ; ' '
+  0x08006896:  69           DC.B       0x69                     ; 'i'
+  0x08006897:  6F           DC.B       0x6F                     ; 'o'
+  0x08006898:  20           DC.B       0x20                     ; ' '
+  0x08006899:  74           DC.B       0x74                     ; 't'
+  0x0800689A:  65           DC.B       0x65                     ; 'e'
+  0x0800689B:  73           DC.B       0x73                     ; 's'
+  0x0800689C:  74           DC.B       0x74                     ; 't'
+  0x0800689D:  2E           DC.B       0x2E                     ; '.'
+  0x0800689E:  2E           DC.B       0x2E                     ; '.'
+  0x0800689F:  2E           DC.B       0x2E                     ; '.'
+  0x080068A0:  6F           DC.B       0x6F                     ; 'o'
+  0x080068A1:  6B           DC.B       0x6B                     ; 'k'
+  0x080068A2:  0D           DC.B       0x0D                     ; '\r'
+  0x080068A3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.13 from PowerPro_lto.o, size=16, align=1

+
+  0x080068A4:  55           DC.B       0x55                     ; 'U'
+  0x080068A5:  4E           DC.B       0x4E                     ; 'N'
+  0x080068A6:  4B           DC.B       0x4B                     ; 'K'
+  0x080068A7:  4E           DC.B       0x4E                     ; 'N'
+  0x080068A8:  4F           DC.B       0x4F                     ; 'O'
+  0x080068A9:  57           DC.B       0x57                     ; 'W'
+  0x080068AA:  4E           DC.B       0x4E                     ; 'N'
+  0x080068AB:  20           DC.B       0x20                     ; ' '
+  0x080068AC:  43           DC.B       0x43                     ; 'C'
+  0x080068AD:  4F           DC.B       0x4F                     ; 'O'
+  0x080068AE:  4D           DC.B       0x4D                     ; 'M'
+  0x080068AF:  4D           DC.B       0x4D                     ; 'M'
+  0x080068B0:  41           DC.B       0x41                     ; 'A'
+  0x080068B1:  4E           DC.B       0x4E                     ; 'N'
+  0x080068B2:  44           DC.B       0x44                     ; 'D'
+  0x080068B3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.2 from PowerPro_lto.o, size=16, align=1

+
+  0x080068B4:  4D           DC.B       0x4D                     ; 'M'
+  0x080068B5:  42           DC.B       0x42                     ; 'B'
+  0x080068B6:  20           DC.B       0x20                     ; ' '
+  0x080068B7:  46           DC.B       0x46                     ; 'F'
+  0x080068B8:  45           DC.B       0x45                     ; 'E'
+  0x080068B9:  20           DC.B       0x20                     ; ' '
+  0x080068BA:  45           DC.B       0x45                     ; 'E'
+  0x080068BB:  72           DC.B       0x72                     ; 'r'
+  0x080068BC:  72           DC.B       0x72                     ; 'r'
+  0x080068BD:  6F           DC.B       0x6F                     ; 'o'
+  0x080068BE:  72           DC.B       0x72                     ; 'r'
+  0x080068BF:  21           DC.B       0x21                     ; '!'
+  0x080068C0:  20           DC.B       0x20                     ; ' '
+  0x080068C1:  0A           DC.B       0x0A                     ; '\n'
+  0x080068C2:  0D           DC.B       0x0D                     ; '\r'
+  0x080068C3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.3 from PowerPro_lto.o, size=16, align=1

+
+  0x080068C4:  4D           DC.B       0x4D                     ; 'M'
+  0x080068C5:  42           DC.B       0x42                     ; 'B'
+  0x080068C6:  20           DC.B       0x20                     ; ' '
+  0x080068C7:  50           DC.B       0x50                     ; 'P'
+  0x080068C8:  45           DC.B       0x45                     ; 'E'
+  0x080068C9:  20           DC.B       0x20                     ; ' '
+  0x080068CA:  45           DC.B       0x45                     ; 'E'
+  0x080068CB:  72           DC.B       0x72                     ; 'r'
+  0x080068CC:  72           DC.B       0x72                     ; 'r'
+  0x080068CD:  6F           DC.B       0x6F                     ; 'o'
+  0x080068CE:  72           DC.B       0x72                     ; 'r'
+  0x080068CF:  21           DC.B       0x21                     ; '!'
+  0x080068D0:  20           DC.B       0x20                     ; ' '
+  0x080068D1:  0A           DC.B       0x0A                     ; '\n'
+  0x080068D2:  0D           DC.B       0x0D                     ; '\r'
+  0x080068D3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.4 from PowerPro_lto.o, size=16, align=1

+
+  0x080068D4:  4D           DC.B       0x4D                     ; 'M'
+  0x080068D5:  42           DC.B       0x42                     ; 'B'
+  0x080068D6:  20           DC.B       0x20                     ; ' '
+  0x080068D7:  4E           DC.B       0x4E                     ; 'N'
+  0x080068D8:  45           DC.B       0x45                     ; 'E'
+  0x080068D9:  20           DC.B       0x20                     ; ' '
+  0x080068DA:  45           DC.B       0x45                     ; 'E'
+  0x080068DB:  72           DC.B       0x72                     ; 'r'
+  0x080068DC:  72           DC.B       0x72                     ; 'r'
+  0x080068DD:  6F           DC.B       0x6F                     ; 'o'
+  0x080068DE:  72           DC.B       0x72                     ; 'r'
+  0x080068DF:  21           DC.B       0x21                     ; '!'
+  0x080068E0:  20           DC.B       0x20                     ; ' '
+  0x080068E1:  0A           DC.B       0x0A                     ; '\n'
+  0x080068E2:  0D           DC.B       0x0D                     ; '\r'
+  0x080068E3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19 from PowerPro_lto.o, size=8, align=1

+
+  0x080068E4:  4C           DC.B       0x4C                     ; 'L'
+  0x080068E5:  56           DC.B       0x56                     ; 'V'
+  0x080068E6:  50           DC.B       0x50                     ; 'P'
+  0x080068E7:  20           DC.B       0x20                     ; ' '
+  0x080068E8:  4F           DC.B       0x4F                     ; 'O'
+  0x080068E9:  4E           DC.B       0x4E                     ; 'N'
+  0x080068EA:  21           DC.B       0x21                     ; '!'
+  0x080068EB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17.129 from PowerPro_lto.o, size=16, align=1

+
+  0x080068EC:  4C           DC.B       0x4C                     ; 'L'
+  0x080068ED:  56           DC.B       0x56                     ; 'V'
+  0x080068EE:  50           DC.B       0x50                     ; 'P'
+  0x080068EF:  20           DC.B       0x20                     ; ' '
+  0x080068F0:  4F           DC.B       0x4F                     ; 'O'
+  0x080068F1:  52           DC.B       0x52                     ; 'R'
+  0x080068F2:  20           DC.B       0x20                     ; ' '
+  0x080068F3:  4F           DC.B       0x4F                     ; 'O'
+  0x080068F4:  56           DC.B       0x56                     ; 'V'
+  0x080068F5:  50           DC.B       0x50                     ; 'P'
+  0x080068F6:  20           DC.B       0x20                     ; ' '
+  0x080068F7:  4F           DC.B       0x4F                     ; 'O'
+  0x080068F8:  46           DC.B       0x46                     ; 'F'
+  0x080068F9:  46           DC.B       0x46                     ; 'F'
+  0x080068FA:  21           DC.B       0x21                     ; '!'
+  0x080068FB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19.131 from PowerPro_lto.o, size=16, align=1

+
+  0x080068FC:  4C           DC.B       0x4C                     ; 'L'
+  0x080068FD:  56           DC.B       0x56                     ; 'V'
+  0x080068FE:  50           DC.B       0x50                     ; 'P'
+  0x080068FF:  20           DC.B       0x20                     ; ' '
+  0x08006900:  41           DC.B       0x41                     ; 'A'
+  0x08006901:  4E           DC.B       0x4E                     ; 'N'
+  0x08006902:  44           DC.B       0x44                     ; 'D'
+  0x08006903:  20           DC.B       0x20                     ; ' '
+  0x08006904:  4F           DC.B       0x4F                     ; 'O'
+  0x08006905:  56           DC.B       0x56                     ; 'V'
+  0x08006906:  50           DC.B       0x50                     ; 'P'
+  0x08006907:  20           DC.B       0x20                     ; ' '
+  0x08006908:  4F           DC.B       0x4F                     ; 'O'
+  0x08006909:  4E           DC.B       0x4E                     ; 'N'
+  0x0800690A:  21           DC.B       0x21                     ; '!'
+  0x0800690B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8.136 from PowerPro_lto.o, size=28, align=1

+
+  0x0800690C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800690D:  45           DC.B       0x45                     ; 'E'
+  0x0800690E:  57           DC.B       0x57                     ; 'W'
+  0x0800690F:  5F           DC.B       0x5F                     ; '_'
+  0x08006910:  53           DC.B       0x53                     ; 'S'
+  0x08006911:  54           DC.B       0x54                     ; 'T'
+  0x08006912:  41           DC.B       0x41                     ; 'A'
+  0x08006913:  54           DC.B       0x54                     ; 'T'
+  0x08006914:  45           DC.B       0x45                     ; 'E'
+  0x08006915:  3A           DC.B       0x3A                     ; ':'
+  0x08006916:  20           DC.B       0x20                     ; ' '
+  0x08006917:  4D           DC.B       0x4D                     ; 'M'
+  0x08006918:  41           DC.B       0x41                     ; 'A'
+  0x08006919:  49           DC.B       0x49                     ; 'I'
+  0x0800691A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800691B:  53           DC.B       0x53                     ; 'S'
+  0x0800691C:  57           DC.B       0x57                     ; 'W'
+  0x0800691D:  49           DC.B       0x49                     ; 'I'
+  0x0800691E:  54           DC.B       0x54                     ; 'T'
+  0x0800691F:  43           DC.B       0x43                     ; 'C'
+  0x08006920:  48           DC.B       0x48                     ; 'H'
+  0x08006921:  5F           DC.B       0x5F                     ; '_'
+  0x08006922:  45           DC.B       0x45                     ; 'E'
+  0x08006923:  52           DC.B       0x52                     ; 'R'
+  0x08006924:  52           DC.B       0x52                     ; 'R'
+  0x08006925:  4F           DC.B       0x4F                     ; 'O'
+  0x08006926:  52           DC.B       0x52                     ; 'R'
+  0x08006927:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.138 from PowerPro_lto.o, size=32, align=1

+
+  0x08006928:  4E           DC.B       0x4E                     ; 'N'
+  0x08006929:  45           DC.B       0x45                     ; 'E'
+  0x0800692A:  57           DC.B       0x57                     ; 'W'
+  0x0800692B:  5F           DC.B       0x5F                     ; '_'
+  0x0800692C:  53           DC.B       0x53                     ; 'S'
+  0x0800692D:  54           DC.B       0x54                     ; 'T'
+  0x0800692E:  41           DC.B       0x41                     ; 'A'
+  0x0800692F:  54           DC.B       0x54                     ; 'T'
+  0x08006930:  45           DC.B       0x45                     ; 'E'
+  0x08006931:  3A           DC.B       0x3A                     ; ':'
+  0x08006932:  20           DC.B       0x20                     ; ' '
+  0x08006933:  4D           DC.B       0x4D                     ; 'M'
+  0x08006934:  41           DC.B       0x41                     ; 'A'
+  0x08006935:  49           DC.B       0x49                     ; 'I'
+  0x08006936:  4E           DC.B       0x4E                     ; 'N'
+  0x08006937:  53           DC.B       0x53                     ; 'S'
+  0x08006938:  57           DC.B       0x57                     ; 'W'
+  0x08006939:  49           DC.B       0x49                     ; 'I'
+  0x0800693A:  54           DC.B       0x54                     ; 'T'
+  0x0800693B:  43           DC.B       0x43                     ; 'C'
+  0x0800693C:  48           DC.B       0x48                     ; 'H'
+  0x0800693D:  5F           DC.B       0x5F                     ; '_'
+  0x0800693E:  4D           DC.B       0x4D                     ; 'M'
+  0x0800693F:  41           DC.B       0x41                     ; 'A'
+  0x08006940:  4E           DC.B       0x4E                     ; 'N'
+  0x08006941:  55           DC.B       0x55                     ; 'U'
+  0x08006942:  41           DC.B       0x41                     ; 'A'
+  0x08006943:  4C           DC.B       0x4C                     ; 'L'
+  0x08006944:  5F           DC.B       0x5F                     ; '_'
+  0x08006945:  4F           DC.B       0x4F                     ; 'O'
+  0x08006946:  4E           DC.B       0x4E                     ; 'N'
+  0x08006947:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19.154 from PowerPro_lto.o, size=8, align=1

+
+  0x08006948:  4F           DC.B       0x4F                     ; 'O'
+  0x08006949:  56           DC.B       0x56                     ; 'V'
+  0x0800694A:  50           DC.B       0x50                     ; 'P'
+  0x0800694B:  20           DC.B       0x20                     ; ' '
+  0x0800694C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800694D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800694E:  21           DC.B       0x21                     ; '!'
+  0x0800694F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11.179 from PowerPro_lto.o, size=60, align=1

+
+  0x08006950:  42           DC.B       0x42                     ; 'B'
+  0x08006951:  4D           DC.B       0x4D                     ; 'M'
+  0x08006952:  53           DC.B       0x53                     ; 'S'
+  0x08006953:  20           DC.B       0x20                     ; ' '
+  0x08006954:  53           DC.B       0x53                     ; 'S'
+  0x08006955:  45           DC.B       0x45                     ; 'E'
+  0x08006956:  43           DC.B       0x43                     ; 'C'
+  0x08006957:  4F           DC.B       0x4F                     ; 'O'
+  0x08006958:  4E           DC.B       0x4E                     ; 'N'
+  0x08006959:  44           DC.B       0x44                     ; 'D'
+  0x0800695A:  41           DC.B       0x41                     ; 'A'
+  0x0800695B:  52           DC.B       0x52                     ; 'R'
+  0x0800695C:  59           DC.B       0x59                     ; 'Y'
+  0x0800695D:  20           DC.B       0x20                     ; ' '
+  0x0800695E:  50           DC.B       0x50                     ; 'P'
+  0x0800695F:  52           DC.B       0x52                     ; 'R'
+  0x08006960:  4F           DC.B       0x4F                     ; 'O'
+  0x08006961:  54           DC.B       0x54                     ; 'T'
+  0x08006962:  45           DC.B       0x45                     ; 'E'
+  0x08006963:  43           DC.B       0x43                     ; 'C'
+  0x08006964:  54           DC.B       0x54                     ; 'T'
+  0x08006965:  49           DC.B       0x49                     ; 'I'
+  0x08006966:  4F           DC.B       0x4F                     ; 'O'
+  0x08006967:  4E           DC.B       0x4E                     ; 'N'
+  0x08006968:  20           DC.B       0x20                     ; ' '
+  0x08006969:  46           DC.B       0x46                     ; 'F'
+  0x0800696A:  41           DC.B       0x41                     ; 'A'
+  0x0800696B:  55           DC.B       0x55                     ; 'U'
+  0x0800696C:  4C           DC.B       0x4C                     ; 'L'
+  0x0800696D:  54           DC.B       0x54                     ; 'T'
+  0x0800696E:  20           DC.B       0x20                     ; ' '
+  0x0800696F:  45           DC.B       0x45                     ; 'E'
+  0x08006970:  56           DC.B       0x56                     ; 'V'
+  0x08006971:  45           DC.B       0x45                     ; 'E'
+  0x08006972:  4E           DC.B       0x4E                     ; 'N'
+  0x08006973:  54           DC.B       0x54                     ; 'T'
+  0x08006974:  20           DC.B       0x20                     ; ' '
+  0x08006975:  44           DC.B       0x44                     ; 'D'
+  0x08006976:  45           DC.B       0x45                     ; 'E'
+  0x08006977:  54           DC.B       0x54                     ; 'T'
+  0x08006978:  45           DC.B       0x45                     ; 'E'
+  0x08006979:  43           DC.B       0x43                     ; 'C'
+  0x0800697A:  54           DC.B       0x54                     ; 'T'
+  0x0800697B:  45           DC.B       0x45                     ; 'E'
+  0x0800697C:  44           DC.B       0x44                     ; 'D'
+  0x0800697D:  20           DC.B       0x20                     ; ' '
+  0x0800697E:  28           DC.B       0x28                     ; '('
+  0x0800697F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006980:  56           DC.B       0x56                     ; 'V'
+  0x08006981:  50           DC.B       0x50                     ; 'P'
+  0x08006982:  20           DC.B       0x20                     ; ' '
+  0x08006983:  26           DC.B       0x26                     ; '&'
+  0x08006984:  20           DC.B       0x20                     ; ' '
+  0x08006985:  4F           DC.B       0x4F                     ; 'O'
+  0x08006986:  56           DC.B       0x56                     ; 'V'
+  0x08006987:  50           DC.B       0x50                     ; 'P'
+  0x08006988:  20           DC.B       0x20                     ; ' '
+  0x08006989:  29           DC.B       0x29                     ; ')'
+  0x0800698A:  21           DC.B       0x21                     ; '!'
+  0x0800698B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.14.174 from PowerPro_lto.o, size=28, align=1

+
+  0x0800698C:  46           DC.B       0x46                     ; 'F'
+  0x0800698D:  41           DC.B       0x41                     ; 'A'
+  0x0800698E:  55           DC.B       0x55                     ; 'U'
+  0x0800698F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006990:  54           DC.B       0x54                     ; 'T'
+  0x08006991:  20           DC.B       0x20                     ; ' '
+  0x08006992:  49           DC.B       0x49                     ; 'I'
+  0x08006993:  4E           DC.B       0x4E                     ; 'N'
+  0x08006994:  50           DC.B       0x50                     ; 'P'
+  0x08006995:  55           DC.B       0x55                     ; 'U'
+  0x08006996:  54           DC.B       0x54                     ; 'T'
+  0x08006997:  20           DC.B       0x20                     ; ' '
+  0x08006998:  45           DC.B       0x45                     ; 'E'
+  0x08006999:  56           DC.B       0x56                     ; 'V'
+  0x0800699A:  45           DC.B       0x45                     ; 'E'
+  0x0800699B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800699C:  54           DC.B       0x54                     ; 'T'
+  0x0800699D:  20           DC.B       0x20                     ; ' '
+  0x0800699E:  44           DC.B       0x44                     ; 'D'
+  0x0800699F:  45           DC.B       0x45                     ; 'E'
+  0x080069A0:  54           DC.B       0x54                     ; 'T'
+  0x080069A1:  45           DC.B       0x45                     ; 'E'
+  0x080069A2:  43           DC.B       0x43                     ; 'C'
+  0x080069A3:  54           DC.B       0x54                     ; 'T'
+  0x080069A4:  45           DC.B       0x45                     ; 'E'
+  0x080069A5:  44           DC.B       0x44                     ; 'D'
+  0x080069A6:  21           DC.B       0x21                     ; '!'
+  0x080069A7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_hex_uc from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=1

+
+
__SEGGER_RTL_hex_uc:
+  0x080069A8:  30           DC.B       0x30                     ; '0'
+  0x080069A9:  31           DC.B       0x31                     ; '1'
+  0x080069AA:  32           DC.B       0x32                     ; '2'
+  0x080069AB:  33           DC.B       0x33                     ; '3'
+  0x080069AC:  34           DC.B       0x34                     ; '4'
+  0x080069AD:  35           DC.B       0x35                     ; '5'
+  0x080069AE:  36           DC.B       0x36                     ; '6'
+  0x080069AF:  37           DC.B       0x37                     ; '7'
+  0x080069B0:  38           DC.B       0x38                     ; '8'
+  0x080069B1:  39           DC.B       0x39                     ; '9'
+  0x080069B2:  41           DC.B       0x41                     ; 'A'
+  0x080069B3:  42           DC.B       0x42                     ; 'B'
+  0x080069B4:  43           DC.B       0x43                     ; 'C'
+  0x080069B5:  44           DC.B       0x44                     ; 'D'
+  0x080069B6:  45           DC.B       0x45                     ; 'E'
+  0x080069B7:  46           DC.B       0x46                     ; 'F'
+
+

Section .rodata.libc.__SEGGER_RTL_hex_lc from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=1

+
+
__SEGGER_RTL_hex_lc:
+  0x080069B8:  30           DC.B       0x30                     ; '0'
+  0x080069B9:  31           DC.B       0x31                     ; '1'
+  0x080069BA:  32           DC.B       0x32                     ; '2'
+  0x080069BB:  33           DC.B       0x33                     ; '3'
+  0x080069BC:  34           DC.B       0x34                     ; '4'
+  0x080069BD:  35           DC.B       0x35                     ; '5'
+  0x080069BE:  36           DC.B       0x36                     ; '6'
+  0x080069BF:  37           DC.B       0x37                     ; '7'
+  0x080069C0:  38           DC.B       0x38                     ; '8'
+  0x080069C1:  39           DC.B       0x39                     ; '9'
+  0x080069C2:  61           DC.B       0x61                     ; 'a'
+  0x080069C3:  62           DC.B       0x62                     ; 'b'
+  0x080069C4:  63           DC.B       0x63                     ; 'c'
+  0x080069C5:  64           DC.B       0x64                     ; 'd'
+  0x080069C6:  65           DC.B       0x65                     ; 'e'
+  0x080069C7:  66           DC.B       0x66                     ; 'f'
+
+

Section .rodata.libc.__SEGGER_RTL_ascii_ctype_map from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=128, align=1

+
+
__SEGGER_RTL_ascii_ctype_map:
+  0x080069C8:  20           DC.B       0x20                     ; ' '
+  0x080069C9:  20           DC.B       0x20                     ; ' '
+  0x080069CA:  20           DC.B       0x20                     ; ' '
+  0x080069CB:  20           DC.B       0x20                     ; ' '
+  0x080069CC:  20           DC.B       0x20                     ; ' '
+  0x080069CD:  20           DC.B       0x20                     ; ' '
+  0x080069CE:  20           DC.B       0x20                     ; ' '
+  0x080069CF:  20           DC.B       0x20                     ; ' '
+  0x080069D0:  20           DC.B       0x20                     ; ' '
+  0x080069D1:  68           DC.B       0x68                     ; 'h'
+  0x080069D2:  28           DC.B       0x28                     ; '('
+  0x080069D3:  28           DC.B       0x28                     ; '('
+  0x080069D4:  28           DC.B       0x28                     ; '('
+  0x080069D5:  28           DC.B       0x28                     ; '('
+  0x080069D6:  20           DC.B       0x20                     ; ' '
+  0x080069D7:  20           DC.B       0x20                     ; ' '
+  0x080069D8:  20           DC.B       0x20                     ; ' '
+  0x080069D9:  20           DC.B       0x20                     ; ' '
+  0x080069DA:  20           DC.B       0x20                     ; ' '
+  0x080069DB:  20           DC.B       0x20                     ; ' '
+  0x080069DC:  20           DC.B       0x20                     ; ' '
+  0x080069DD:  20           DC.B       0x20                     ; ' '
+  0x080069DE:  20           DC.B       0x20                     ; ' '
+  0x080069DF:  20           DC.B       0x20                     ; ' '
+  0x080069E0:  20           DC.B       0x20                     ; ' '
+  0x080069E1:  20           DC.B       0x20                     ; ' '
+  0x080069E2:  20           DC.B       0x20                     ; ' '
+  0x080069E3:  20           DC.B       0x20                     ; ' '
+  0x080069E4:  20           DC.B       0x20                     ; ' '
+  0x080069E5:  20           DC.B       0x20                     ; ' '
+  0x080069E6:  20           DC.B       0x20                     ; ' '
+  0x080069E7:  20           DC.B       0x20                     ; ' '
+  0x080069E8:  48           DC.B       0x48                     ; 'H'
+  0x080069E9:  10           DC.B       0x10                     ; '\x10'
+  0x080069EA:  10           DC.B       0x10                     ; '\x10'
+  0x080069EB:  10           DC.B       0x10                     ; '\x10'
+  0x080069EC:  10           DC.B       0x10                     ; '\x10'
+  0x080069ED:  10           DC.B       0x10                     ; '\x10'
+  0x080069EE:  10           DC.B       0x10                     ; '\x10'
+  0x080069EF:  10           DC.B       0x10                     ; '\x10'
+  0x080069F0:  10           DC.B       0x10                     ; '\x10'
+  0x080069F1:  10           DC.B       0x10                     ; '\x10'
+  0x080069F2:  10           DC.B       0x10                     ; '\x10'
+  0x080069F3:  10           DC.B       0x10                     ; '\x10'
+  0x080069F4:  10           DC.B       0x10                     ; '\x10'
+  0x080069F5:  10           DC.B       0x10                     ; '\x10'
+  0x080069F6:  10           DC.B       0x10                     ; '\x10'
+  0x080069F7:  10           DC.B       0x10                     ; '\x10'
+  0x080069F8:  84           DC.B       0x84                     ; '\x84'
+  0x080069F9:  84           DC.B       0x84                     ; '\x84'
+  0x080069FA:  84           DC.B       0x84                     ; '\x84'
+  0x080069FB:  84           DC.B       0x84                     ; '\x84'
+  0x080069FC:  84           DC.B       0x84                     ; '\x84'
+  0x080069FD:  84           DC.B       0x84                     ; '\x84'
+  0x080069FE:  84           DC.B       0x84                     ; '\x84'
+  0x080069FF:  84           DC.B       0x84                     ; '\x84'
+  0x08006A00:  84           DC.B       0x84                     ; '\x84'
+  0x08006A01:  84           DC.B       0x84                     ; '\x84'
+  0x08006A02:  10           DC.B       0x10                     ; '\x10'
+  0x08006A03:  10           DC.B       0x10                     ; '\x10'
+  0x08006A04:  10           DC.B       0x10                     ; '\x10'
+  0x08006A05:  10           DC.B       0x10                     ; '\x10'
+  0x08006A06:  10           DC.B       0x10                     ; '\x10'
+  0x08006A07:  10           DC.B       0x10                     ; '\x10'
+  0x08006A08:  10           DC.B       0x10                     ; '\x10'
+  0x08006A09:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0A:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0B:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0C:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0D:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0E:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0F:  01           DC.B       0x01                     ; '\x01'
+  0x08006A10:  01           DC.B       0x01                     ; '\x01'
+  0x08006A11:  01           DC.B       0x01                     ; '\x01'
+  0x08006A12:  01           DC.B       0x01                     ; '\x01'
+  0x08006A13:  01           DC.B       0x01                     ; '\x01'
+  0x08006A14:  01           DC.B       0x01                     ; '\x01'
+  0x08006A15:  01           DC.B       0x01                     ; '\x01'
+  0x08006A16:  01           DC.B       0x01                     ; '\x01'
+  0x08006A17:  01           DC.B       0x01                     ; '\x01'
+  0x08006A18:  01           DC.B       0x01                     ; '\x01'
+  0x08006A19:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1A:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1B:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1C:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1D:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1E:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1F:  01           DC.B       0x01                     ; '\x01'
+  0x08006A20:  01           DC.B       0x01                     ; '\x01'
+  0x08006A21:  01           DC.B       0x01                     ; '\x01'
+  0x08006A22:  01           DC.B       0x01                     ; '\x01'
+  0x08006A23:  10           DC.B       0x10                     ; '\x10'
+  0x08006A24:  10           DC.B       0x10                     ; '\x10'
+  0x08006A25:  10           DC.B       0x10                     ; '\x10'
+  0x08006A26:  10           DC.B       0x10                     ; '\x10'
+  0x08006A27:  10           DC.B       0x10                     ; '\x10'
+  0x08006A28:  10           DC.B       0x10                     ; '\x10'
+  0x08006A29:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2A:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2B:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2C:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2D:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2E:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2F:  02           DC.B       0x02                     ; '\x02'
+  0x08006A30:  02           DC.B       0x02                     ; '\x02'
+  0x08006A31:  02           DC.B       0x02                     ; '\x02'
+  0x08006A32:  02           DC.B       0x02                     ; '\x02'
+  0x08006A33:  02           DC.B       0x02                     ; '\x02'
+  0x08006A34:  02           DC.B       0x02                     ; '\x02'
+  0x08006A35:  02           DC.B       0x02                     ; '\x02'
+  0x08006A36:  02           DC.B       0x02                     ; '\x02'
+  0x08006A37:  02           DC.B       0x02                     ; '\x02'
+  0x08006A38:  02           DC.B       0x02                     ; '\x02'
+  0x08006A39:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3A:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3B:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3C:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3D:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3E:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3F:  02           DC.B       0x02                     ; '\x02'
+  0x08006A40:  02           DC.B       0x02                     ; '\x02'
+  0x08006A41:  02           DC.B       0x02                     ; '\x02'
+  0x08006A42:  02           DC.B       0x02                     ; '\x02'
+  0x08006A43:  10           DC.B       0x10                     ; '\x10'
+  0x08006A44:  10           DC.B       0x10                     ; '\x10'
+  0x08006A45:  10           DC.B       0x10                     ; '\x10'
+  0x08006A46:  10           DC.B       0x10                     ; '\x10'
+  0x08006A47:  20           DC.B       0x20                     ; ' '
+
+

Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=36, align=4

+
+
__SEGGER_init_ctors:
+  0x08006A48:  B500         PUSH       {LR}
+  0x08006A4A:  4806         LDR        R0, =0x08006860          ; [PC, #24] [0x08006A64] 
+  0x08006A4C:  4906         LDR        R1, =UARTEx_SetNbDataToProcess.numerator ; [PC, #24] [0x08006A68] =0x08006864 
+
.L1:
+  0x08006A4E:  4288         CMP        R0, R1
+  0x08006A50:  D005         BEQ        .L2                      ; 0x08006A5E
+  0x08006A52:  6802         LDR        R2, [R0]
+  0x08006A54:  3004         ADDS       R0, #4
+  0x08006A56:  B403         PUSH       {R0-R1}
+  0x08006A58:  4790         BLX        R2
+  0x08006A5A:  BC03         POP        {R0-R1}
+  0x08006A5C:  E7F7         B          .L1                      ; 0x08006A4E
+
.L2:
+  0x08006A5E:  BC08         POP        {R3}
+  0x08006A60:  4718         BX         R3
+  0x08006A62:  0000         NOP
+  0x08006A64:  08006860     DC.W       08006860               ; R_ARM_ABS32
+  0x08006A68:  08006864     DC.W       UARTEx_SetNbDataToProcess.numerator
+
+

Section .segger.init.table from [ Linker created ], size=180, align=4

+
+  0x08006A6C:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006A70:  00           DC.B       0x00                     ; '\0'
+  0x08006A71:  00           DC.B       0x00                     ; '\0'
+  0x08006A72:  00           DC.B       0x00                     ; '\0'
+  0x08006A73:  20           DC.B       0x20                     ; ' '
+  0x08006A74:  3B           DC.B       0x3B                     ; ';'
+  0x08006A75:  07           DC.B       0x07                     ; '\x07'
+  0x08006A76:  00           DC.B       0x00                     ; '\0'
+  0x08006A77:  00           DC.B       0x00                     ; '\0'
+  0x08006A78:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006A7C:  3C           DC.B       0x3C                     ; '<'
+  0x08006A7D:  07           DC.B       0x07                     ; '\x07'
+  0x08006A7E:  00           DC.B       0x00                     ; '\0'
+  0x08006A7F:  20           DC.B       0x20                     ; ' '
+  0x08006A80:  01           DC.B       0x01                     ; '\x01'
+  0x08006A81:  00           DC.B       0x00                     ; '\0'
+  0x08006A82:  00           DC.B       0x00                     ; '\0'
+  0x08006A83:  00           DC.B       0x00                     ; '\0'
+  0x08006A84:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006A88:  40           DC.B       0x40                     ; '@'
+  0x08006A89:  07           DC.B       0x07                     ; '\x07'
+  0x08006A8A:  00           DC.B       0x00                     ; '\0'
+  0x08006A8B:  20           DC.B       0x20                     ; ' '
+  0x08006A8C:  01           DC.B       0x01                     ; '\x01'
+  0x08006A8D:  00           DC.B       0x00                     ; '\0'
+  0x08006A8E:  00           DC.B       0x00                     ; '\0'
+  0x08006A8F:  00           DC.B       0x00                     ; '\0'
+  0x08006A90:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006A94:  44           DC.B       0x44                     ; 'D'
+  0x08006A95:  07           DC.B       0x07                     ; '\x07'
+  0x08006A96:  00           DC.B       0x00                     ; '\0'
+  0x08006A97:  20           DC.B       0x20                     ; ' '
+  0x08006A98:  01           DC.B       0x01                     ; '\x01'
+  0x08006A99:  00           DC.B       0x00                     ; '\0'
+  0x08006A9A:  00           DC.B       0x00                     ; '\0'
+  0x08006A9B:  00           DC.B       0x00                     ; '\0'
+  0x08006A9C:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AA0:  48           DC.B       0x48                     ; 'H'
+  0x08006AA1:  07           DC.B       0x07                     ; '\x07'
+  0x08006AA2:  00           DC.B       0x00                     ; '\0'
+  0x08006AA3:  20           DC.B       0x20                     ; ' '
+  0x08006AA4:  01           DC.B       0x01                     ; '\x01'
+  0x08006AA5:  00           DC.B       0x00                     ; '\0'
+  0x08006AA6:  00           DC.B       0x00                     ; '\0'
+  0x08006AA7:  00           DC.B       0x00                     ; '\0'
+  0x08006AA8:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AAC:  4C           DC.B       0x4C                     ; 'L'
+  0x08006AAD:  07           DC.B       0x07                     ; '\x07'
+  0x08006AAE:  00           DC.B       0x00                     ; '\0'
+  0x08006AAF:  20           DC.B       0x20                     ; ' '
+  0x08006AB0:  01           DC.B       0x01                     ; '\x01'
+  0x08006AB1:  00           DC.B       0x00                     ; '\0'
+  0x08006AB2:  00           DC.B       0x00                     ; '\0'
+  0x08006AB3:  00           DC.B       0x00                     ; '\0'
+  0x08006AB4:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AB8:  50           DC.B       0x50                     ; 'P'
+  0x08006AB9:  07           DC.B       0x07                     ; '\x07'
+  0x08006ABA:  00           DC.B       0x00                     ; '\0'
+  0x08006ABB:  20           DC.B       0x20                     ; ' '
+  0x08006ABC:  01           DC.B       0x01                     ; '\x01'
+  0x08006ABD:  00           DC.B       0x00                     ; '\0'
+  0x08006ABE:  00           DC.B       0x00                     ; '\0'
+  0x08006ABF:  00           DC.B       0x00                     ; '\0'
+  0x08006AC0:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AC4:  54           DC.B       0x54                     ; 'T'
+  0x08006AC5:  07           DC.B       0x07                     ; '\x07'
+  0x08006AC6:  00           DC.B       0x00                     ; '\0'
+  0x08006AC7:  20           DC.B       0x20                     ; ' '
+  0x08006AC8:  01           DC.B       0x01                     ; '\x01'
+  0x08006AC9:  00           DC.B       0x00                     ; '\0'
+  0x08006ACA:  00           DC.B       0x00                     ; '\0'
+  0x08006ACB:  00           DC.B       0x00                     ; '\0'
+  0x08006ACC:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AD0:  58           DC.B       0x58                     ; 'X'
+  0x08006AD1:  07           DC.B       0x07                     ; '\x07'
+  0x08006AD2:  00           DC.B       0x00                     ; '\0'
+  0x08006AD3:  20           DC.B       0x20                     ; ' '
+  0x08006AD4:  01           DC.B       0x01                     ; '\x01'
+  0x08006AD5:  00           DC.B       0x00                     ; '\0'
+  0x08006AD6:  00           DC.B       0x00                     ; '\0'
+  0x08006AD7:  00           DC.B       0x00                     ; '\0'
+  0x08006AD8:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006ADC:  5C           DC.B       0x5C                     ; '\\'
+  0x08006ADD:  07           DC.B       0x07                     ; '\x07'
+  0x08006ADE:  00           DC.B       0x00                     ; '\0'
+  0x08006ADF:  20           DC.B       0x20                     ; ' '
+  0x08006AE0:  01           DC.B       0x01                     ; '\x01'
+  0x08006AE1:  00           DC.B       0x00                     ; '\0'
+  0x08006AE2:  00           DC.B       0x00                     ; '\0'
+  0x08006AE3:  00           DC.B       0x00                     ; '\0'
+  0x08006AE4:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AE8:  60           DC.B       0x60                     ; '`'
+  0x08006AE9:  07           DC.B       0x07                     ; '\x07'
+  0x08006AEA:  00           DC.B       0x00                     ; '\0'
+  0x08006AEB:  20           DC.B       0x20                     ; ' '
+  0x08006AEC:  01           DC.B       0x01                     ; '\x01'
+  0x08006AED:  00           DC.B       0x00                     ; '\0'
+  0x08006AEE:  00           DC.B       0x00                     ; '\0'
+  0x08006AEF:  00           DC.B       0x00                     ; '\0'
+  0x08006AF0:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006AF4:  64           DC.B       0x64                     ; 'd'
+  0x08006AF5:  07           DC.B       0x07                     ; '\x07'
+  0x08006AF6:  00           DC.B       0x00                     ; '\0'
+  0x08006AF7:  20           DC.B       0x20                     ; ' '
+  0x08006AF8:  01           DC.B       0x01                     ; '\x01'
+  0x08006AF9:  00           DC.B       0x00                     ; '\0'
+  0x08006AFA:  00           DC.B       0x00                     ; '\0'
+  0x08006AFB:  00           DC.B       0x00                     ; '\0'
+  0x08006AFC:  08006B49     DC.W       __SEGGER_init_zero
+  0x08006B00:  68           DC.B       0x68                     ; 'h'
+  0x08006B01:  07           DC.B       0x07                     ; '\x07'
+  0x08006B02:  00           DC.B       0x00                     ; '\0'
+  0x08006B03:  20           DC.B       0x20                     ; ' '
+  0x08006B04:  11           DC.B       0x11                     ; '\x11'
+  0x08006B05:  04           DC.B       0x04                     ; '\x04'
+  0x08006B06:  00           DC.B       0x00                     ; '\0'
+  0x08006B07:  00           DC.B       0x00                     ; '\0'
+  0x08006B08:  08006B5B     DC.W       __SEGGER_init_copy
+  0x08006B0C:  80           DC.B       0x80                     ; '\x80'
+  0x08006B0D:  0B           DC.B       0x0B                     ; '\v'
+  0x08006B0E:  00           DC.B       0x00                     ; '\0'
+  0x08006B0F:  20           DC.B       0x20                     ; ' '
+  0x08006B10:  08006B20     DC.W       08006B20               ; R_ARM_ABS32
+  0x08006B14:  28           DC.B       0x28                     ; '('
+  0x08006B15:  00           DC.B       0x00                     ; '\0'
+  0x08006B16:  00           DC.B       0x00                     ; '\0'
+  0x08006B17:  00           DC.B       0x00                     ; '\0'
+  0x08006B18:  08006A49     DC.W       __SEGGER_init_ctors
+  0x08006B1C:  080051D7     DC.W       __SEGGER_init_done
+
+

Section .segger.init.data from [ Linker created ], size=40, align=4

+
+  0x08006B20:  80           DC.B       0x80                     ; '\x80'
+  0x08006B21:  57           DC.B       0x57                     ; 'W'
+  0x08006B22:  00           DC.B       0x00                     ; '\0'
+  0x08006B23:  08           DC.B       0x08                     ; '\b'
+  0x08006B24:  80           DC.B       0x80                     ; '\x80'
+  0x08006B25:  57           DC.B       0x57                     ; 'W'
+  0x08006B26:  00           DC.B       0x00                     ; '\0'
+  0x08006B27:  08           DC.B       0x08                     ; '\b'
+  0x08006B28:  80           DC.B       0x80                     ; '\x80'
+  0x08006B29:  57           DC.B       0x57                     ; 'W'
+  0x08006B2A:  00           DC.B       0x00                     ; '\0'
+  0x08006B2B:  08           DC.B       0x08                     ; '\b'
+  0x08006B2C:  80           DC.B       0x80                     ; '\x80'
+  0x08006B2D:  57           DC.B       0x57                     ; 'W'
+  0x08006B2E:  00           DC.B       0x00                     ; '\0'
+  0x08006B2F:  08           DC.B       0x08                     ; '\b'
+  0x08006B30:  80           DC.B       0x80                     ; '\x80'
+  0x08006B31:  57           DC.B       0x57                     ; 'W'
+  0x08006B32:  00           DC.B       0x00                     ; '\0'
+  0x08006B33:  08           DC.B       0x08                     ; '\b'
+  0x08006B34:  04           DC.B       0x04                     ; '\x04'
+  0x08006B35:  00           DC.B       0x00                     ; '\0'
+  0x08006B36:  00           DC.B       0x00                     ; '\0'
+  0x08006B37:  00           DC.B       0x00                     ; '\0'
+  0x08006B38:  CC           DC.B       0xCC                     ; '\xCC'
+  0x08006B39:  06           DC.B       0x06                     ; '\x06'
+  0x08006B3A:  00           DC.B       0x00                     ; '\0'
+  0x08006B3B:  20           DC.B       0x20                     ; ' '
+  0x08006B3C:  D0           DC.B       0xD0                     ; '\xD0'
+  0x08006B3D:  06           DC.B       0x06                     ; '\x06'
+  0x08006B3E:  00           DC.B       0x00                     ; '\0'
+  0x08006B3F:  20           DC.B       0x20                     ; ' '
+  0x08006B40:  D4           DC.B       0xD4                     ; '\xD4'
+  0x08006B41:  06           DC.B       0x06                     ; '\x06'
+  0x08006B42:  00           DC.B       0x00                     ; '\0'
+  0x08006B43:  20           DC.B       0x20                     ; ' '
+  0x08006B44:  00           DC.B       0x00                     ; '\0'
+  0x08006B45:  1B           DC.B       0x1B                     ; '\x1B'
+  0x08006B46:  B7           DC.B       0xB7                     ; '\xB7'
+  0x08006B47:  00           DC.B       0x00                     ; '\0'
+
+

Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=18, align=2

+
+
__SEGGER_init_zero:
+  0x08006B48:  6820         LDR        R0, [R4]
+  0x08006B4A:  6861         LDR        R1, [R4, #4]
+  0x08006B4C:  3408         ADDS       R4, #8
+  0x08006B4E:  2200         MOVS       R2, #0
+  0x08006B50:  E000         B          .L2                      ; 0x08006B54
+
.L1:
+  0x08006B52:  5442         STRB       R2, [R0, R1]
+
.L2:
+  0x08006B54:  1E49         SUBS       R1, R1, #1
+  0x08006B56:  D5FC         BPL        .L1                      ; 0x08006B52
+  0x08006B58:  4770         BX         LR
+
+

Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=20, align=2

+
+
__SEGGER_init_copy:
+  0x08006B5A:  6820         LDR        R0, [R4]
+  0x08006B5C:  6861         LDR        R1, [R4, #4]
+  0x08006B5E:  68A2         LDR        R2, [R4, #8]
+  0x08006B60:  340C         ADDS       R4, #12
+  0x08006B62:  E001         B          .L2                      ; 0x08006B68
+
.L1:
+  0x08006B64:  5C8B         LDRB       R3, [R1, R2]
+  0x08006B66:  5483         STRB       R3, [R0, R2]
+
.L2:
+  0x08006B68:  1E52         SUBS       R2, R2, #1
+  0x08006B6A:  D5FB         BPL        .L1                      ; 0x08006B64
+  0x08006B6C:  4770         BX         LR
+
+

Section .RAM1 from PowerPro_lto.o, size=564, align=4

+
+
modbusData:
+  0x20000000:  00           DC.B       0x00                     ; '\0'
+  0x20000001:  00           DC.B       0x00                     ; '\0'
+  0x20000002:  00           DC.B       0x00                     ; '\0'
+  0x20000003:  00           DC.B       0x00                     ; '\0'
+  0x20000004:  00           DC.B       0x00                     ; '\0'
+  0x20000005:  00           DC.B       0x00                     ; '\0'
+  0x20000006:  00           DC.B       0x00                     ; '\0'
+  0x20000007:  00           DC.B       0x00                     ; '\0'
+  0x20000008:  00           DC.B       0x00                     ; '\0'
+  0x20000009:  00           DC.B       0x00                     ; '\0'
+  0x2000000A:  00           DC.B       0x00                     ; '\0'
+  0x2000000B:  00           DC.B       0x00                     ; '\0'
+  0x2000000C:  00           DC.B       0x00                     ; '\0'
+  0x2000000D:  00           DC.B       0x00                     ; '\0'
+  0x2000000E:  00           DC.B       0x00                     ; '\0'
+  0x2000000F:  00           DC.B       0x00                     ; '\0'
+  0x20000010:  00           DC.B       0x00                     ; '\0'
+  0x20000011:  00           DC.B       0x00                     ; '\0'
+  0x20000012:  00           DC.B       0x00                     ; '\0'
+  0x20000013:  00           DC.B       0x00                     ; '\0'
+  0x20000014:  00           DC.B       0x00                     ; '\0'
+  0x20000015:  00           DC.B       0x00                     ; '\0'
+  0x20000016:  00           DC.B       0x00                     ; '\0'
+  0x20000017:  00           DC.B       0x00                     ; '\0'
+  0x20000018:  00           DC.B       0x00                     ; '\0'
+  0x20000019:  00           DC.B       0x00                     ; '\0'
+  0x2000001A:  00           DC.B       0x00                     ; '\0'
+  0x2000001B:  00           DC.B       0x00                     ; '\0'
+  0x2000001C:  00           DC.B       0x00                     ; '\0'
+  0x2000001D:  00           DC.B       0x00                     ; '\0'
+  0x2000001E:  00           DC.B       0x00                     ; '\0'
+  0x2000001F:  00           DC.B       0x00                     ; '\0'
+  0x20000020:  00           DC.B       0x00                     ; '\0'
+  0x20000021:  00           DC.B       0x00                     ; '\0'
+  0x20000022:  00           DC.B       0x00                     ; '\0'
+  0x20000023:  00           DC.B       0x00                     ; '\0'
+  0x20000024:  00           DC.B       0x00                     ; '\0'
+  0x20000025:  00           DC.B       0x00                     ; '\0'
+  0x20000026:  00           DC.B       0x00                     ; '\0'
+  0x20000027:  00           DC.B       0x00                     ; '\0'
+  0x20000028:  00           DC.B       0x00                     ; '\0'
+  0x20000029:  00           DC.B       0x00                     ; '\0'
+  0x2000002A:  00           DC.B       0x00                     ; '\0'
+  0x2000002B:  00           DC.B       0x00                     ; '\0'
+  0x2000002C:  00           DC.B       0x00                     ; '\0'
+  0x2000002D:  00           DC.B       0x00                     ; '\0'
+  0x2000002E:  00           DC.B       0x00                     ; '\0'
+  0x2000002F:  00           DC.B       0x00                     ; '\0'
+  0x20000030:  00           DC.B       0x00                     ; '\0'
+  0x20000031:  00           DC.B       0x00                     ; '\0'
+  0x20000032:  00           DC.B       0x00                     ; '\0'
+  0x20000033:  00           DC.B       0x00                     ; '\0'
+  0x20000034:  00           DC.B       0x00                     ; '\0'
+  0x20000035:  00           DC.B       0x00                     ; '\0'
+  0x20000036:  00           DC.B       0x00                     ; '\0'
+  0x20000037:  00           DC.B       0x00                     ; '\0'
+  0x20000038:  00           DC.B       0x00                     ; '\0'
+  0x20000039:  00           DC.B       0x00                     ; '\0'
+  0x2000003A:  00           DC.B       0x00                     ; '\0'
+  0x2000003B:  00           DC.B       0x00                     ; '\0'
+  0x2000003C:  00           DC.B       0x00                     ; '\0'
+  0x2000003D:  00           DC.B       0x00                     ; '\0'
+  0x2000003E:  00           DC.B       0x00                     ; '\0'
+  0x2000003F:  00           DC.B       0x00                     ; '\0'
+  0x20000040:  00           DC.B       0x00                     ; '\0'
+  0x20000041:  00           DC.B       0x00                     ; '\0'
+  0x20000042:  00           DC.B       0x00                     ; '\0'
+  0x20000043:  00           DC.B       0x00                     ; '\0'
+  0x20000044:  00           DC.B       0x00                     ; '\0'
+  0x20000045:  00           DC.B       0x00                     ; '\0'
+  0x20000046:  00           DC.B       0x00                     ; '\0'
+  0x20000047:  00           DC.B       0x00                     ; '\0'
+  0x20000048:  00           DC.B       0x00                     ; '\0'
+  0x20000049:  00           DC.B       0x00                     ; '\0'
+  0x2000004A:  00           DC.B       0x00                     ; '\0'
+  0x2000004B:  00           DC.B       0x00                     ; '\0'
+  0x2000004C:  00           DC.B       0x00                     ; '\0'
+  0x2000004D:  00           DC.B       0x00                     ; '\0'
+  0x2000004E:  00           DC.B       0x00                     ; '\0'
+  0x2000004F:  00           DC.B       0x00                     ; '\0'
+  0x20000050:  00           DC.B       0x00                     ; '\0'
+  0x20000051:  00           DC.B       0x00                     ; '\0'
+  0x20000052:  00           DC.B       0x00                     ; '\0'
+  0x20000053:  00           DC.B       0x00                     ; '\0'
+  0x20000054:  00           DC.B       0x00                     ; '\0'
+  0x20000055:  00           DC.B       0x00                     ; '\0'
+  0x20000056:  00           DC.B       0x00                     ; '\0'
+  0x20000057:  00           DC.B       0x00                     ; '\0'
+  0x20000058:  00           DC.B       0x00                     ; '\0'
+  0x20000059:  00           DC.B       0x00                     ; '\0'
+  0x2000005A:  00           DC.B       0x00                     ; '\0'
+  0x2000005B:  00           DC.B       0x00                     ; '\0'
+  0x2000005C:  00           DC.B       0x00                     ; '\0'
+  0x2000005D:  00           DC.B       0x00                     ; '\0'
+  0x2000005E:  00           DC.B       0x00                     ; '\0'
+  0x2000005F:  00           DC.B       0x00                     ; '\0'
+  0x20000060:  00           DC.B       0x00                     ; '\0'
+  0x20000061:  00           DC.B       0x00                     ; '\0'
+  0x20000062:  00           DC.B       0x00                     ; '\0'
+  0x20000063:  00           DC.B       0x00                     ; '\0'
+  0x20000064:  00           DC.B       0x00                     ; '\0'
+  0x20000065:  00           DC.B       0x00                     ; '\0'
+  0x20000066:  00           DC.B       0x00                     ; '\0'
+  0x20000067:  00           DC.B       0x00                     ; '\0'
+  0x20000068:  00           DC.B       0x00                     ; '\0'
+  0x20000069:  00           DC.B       0x00                     ; '\0'
+  0x2000006A:  00           DC.B       0x00                     ; '\0'
+  0x2000006B:  00           DC.B       0x00                     ; '\0'
+  0x2000006C:  00           DC.B       0x00                     ; '\0'
+  0x2000006D:  00           DC.B       0x00                     ; '\0'
+  0x2000006E:  00           DC.B       0x00                     ; '\0'
+  0x2000006F:  00           DC.B       0x00                     ; '\0'
+  0x20000070:  00           DC.B       0x00                     ; '\0'
+  0x20000071:  00           DC.B       0x00                     ; '\0'
+  0x20000072:  00           DC.B       0x00                     ; '\0'
+  0x20000073:  00           DC.B       0x00                     ; '\0'
+  0x20000074:  00           DC.B       0x00                     ; '\0'
+  0x20000075:  00           DC.B       0x00                     ; '\0'
+  0x20000076:  00           DC.B       0x00                     ; '\0'
+  0x20000077:  00           DC.B       0x00                     ; '\0'
+  0x20000078:  00           DC.B       0x00                     ; '\0'
+  0x20000079:  00           DC.B       0x00                     ; '\0'
+  0x2000007A:  00           DC.B       0x00                     ; '\0'
+  0x2000007B:  00           DC.B       0x00                     ; '\0'
+  0x2000007C:  00           DC.B       0x00                     ; '\0'
+  0x2000007D:  00           DC.B       0x00                     ; '\0'
+  0x2000007E:  00           DC.B       0x00                     ; '\0'
+  0x2000007F:  00           DC.B       0x00                     ; '\0'
+  0x20000080:  00           DC.B       0x00                     ; '\0'
+  0x20000081:  00           DC.B       0x00                     ; '\0'
+  0x20000082:  00           DC.B       0x00                     ; '\0'
+  0x20000083:  00           DC.B       0x00                     ; '\0'
+  0x20000084:  00           DC.B       0x00                     ; '\0'
+  0x20000085:  00           DC.B       0x00                     ; '\0'
+  0x20000086:  00           DC.B       0x00                     ; '\0'
+  0x20000087:  00           DC.B       0x00                     ; '\0'
+  0x20000088:  00           DC.B       0x00                     ; '\0'
+  0x20000089:  00           DC.B       0x00                     ; '\0'
+  0x2000008A:  00           DC.B       0x00                     ; '\0'
+  0x2000008B:  00           DC.B       0x00                     ; '\0'
+  0x2000008C:  00           DC.B       0x00                     ; '\0'
+  0x2000008D:  00           DC.B       0x00                     ; '\0'
+  0x2000008E:  00           DC.B       0x00                     ; '\0'
+  0x2000008F:  00           DC.B       0x00                     ; '\0'
+  0x20000090:  00           DC.B       0x00                     ; '\0'
+  0x20000091:  00           DC.B       0x00                     ; '\0'
+  0x20000092:  00           DC.B       0x00                     ; '\0'
+  0x20000093:  00           DC.B       0x00                     ; '\0'
+  0x20000094:  00           DC.B       0x00                     ; '\0'
+  0x20000095:  00           DC.B       0x00                     ; '\0'
+  0x20000096:  00           DC.B       0x00                     ; '\0'
+  0x20000097:  00           DC.B       0x00                     ; '\0'
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+  0x200001D7:  00           DC.B       0x00                     ; '\0'
+  0x200001D8:  00           DC.B       0x00                     ; '\0'
+  0x200001D9:  00           DC.B       0x00                     ; '\0'
+  0x200001DA:  00           DC.B       0x00                     ; '\0'
+  0x200001DB:  00           DC.B       0x00                     ; '\0'
+  0x200001DC:  00           DC.B       0x00                     ; '\0'
+  0x200001DD:  00           DC.B       0x00                     ; '\0'
+  0x200001DE:  00           DC.B       0x00                     ; '\0'
+  0x200001DF:  00           DC.B       0x00                     ; '\0'
+  0x200001E0:  00           DC.B       0x00                     ; '\0'
+  0x200001E1:  00           DC.B       0x00                     ; '\0'
+  0x200001E2:  00           DC.B       0x00                     ; '\0'
+  0x200001E3:  00           DC.B       0x00                     ; '\0'
+  0x200001E4:  00           DC.B       0x00                     ; '\0'
+  0x200001E5:  00           DC.B       0x00                     ; '\0'
+  0x200001E6:  00           DC.B       0x00                     ; '\0'
+  0x200001E7:  00           DC.B       0x00                     ; '\0'
+  0x200001E8:  00           DC.B       0x00                     ; '\0'
+  0x200001E9:  00           DC.B       0x00                     ; '\0'
+  0x200001EA:  00           DC.B       0x00                     ; '\0'
+  0x200001EB:  00           DC.B       0x00                     ; '\0'
+  0x200001EC:  00           DC.B       0x00                     ; '\0'
+  0x200001ED:  00           DC.B       0x00                     ; '\0'
+  0x200001EE:  00           DC.B       0x00                     ; '\0'
+  0x200001EF:  00           DC.B       0x00                     ; '\0'
+  0x200001F0:  00           DC.B       0x00                     ; '\0'
+  0x200001F1:  00           DC.B       0x00                     ; '\0'
+  0x200001F2:  00           DC.B       0x00                     ; '\0'
+  0x200001F3:  00           DC.B       0x00                     ; '\0'
+  0x200001F4:  00           DC.B       0x00                     ; '\0'
+  0x200001F5:  00           DC.B       0x00                     ; '\0'
+  0x200001F6:  00           DC.B       0x00                     ; '\0'
+  0x200001F7:  00           DC.B       0x00                     ; '\0'
+  0x200001F8:  00           DC.B       0x00                     ; '\0'
+  0x200001F9:  00           DC.B       0x00                     ; '\0'
+  0x200001FA:  00           DC.B       0x00                     ; '\0'
+  0x200001FB:  00           DC.B       0x00                     ; '\0'
+  0x200001FC:  00           DC.B       0x00                     ; '\0'
+  0x200001FD:  00           DC.B       0x00                     ; '\0'
+  0x200001FE:  00           DC.B       0x00                     ; '\0'
+  0x200001FF:  00           DC.B       0x00                     ; '\0'
+  0x20000200:  00           DC.B       0x00                     ; '\0'
+  0x20000201:  00           DC.B       0x00                     ; '\0'
+  0x20000202:  00           DC.B       0x00                     ; '\0'
+  0x20000203:  00           DC.B       0x00                     ; '\0'
+  0x20000204:  00           DC.B       0x00                     ; '\0'
+  0x20000205:  00           DC.B       0x00                     ; '\0'
+  0x20000206:  00           DC.B       0x00                     ; '\0'
+  0x20000207:  00           DC.B       0x00                     ; '\0'
+  0x20000208:  00           DC.B       0x00                     ; '\0'
+  0x20000209:  00           DC.B       0x00                     ; '\0'
+  0x2000020A:  00           DC.B       0x00                     ; '\0'
+  0x2000020B:  00           DC.B       0x00                     ; '\0'
+  0x2000020C:  00           DC.B       0x00                     ; '\0'
+  0x2000020D:  00           DC.B       0x00                     ; '\0'
+  0x2000020E:  00           DC.B       0x00                     ; '\0'
+  0x2000020F:  00           DC.B       0x00                     ; '\0'
+  0x20000210:  00           DC.B       0x00                     ; '\0'
+  0x20000211:  00           DC.B       0x00                     ; '\0'
+  0x20000212:  00           DC.B       0x00                     ; '\0'
+  0x20000213:  00           DC.B       0x00                     ; '\0'
+  0x20000214:  00           DC.B       0x00                     ; '\0'
+  0x20000215:  00           DC.B       0x00                     ; '\0'
+  0x20000216:  00           DC.B       0x00                     ; '\0'
+  0x20000217:  00           DC.B       0x00                     ; '\0'
+  0x20000218:  00           DC.B       0x00                     ; '\0'
+  0x20000219:  00           DC.B       0x00                     ; '\0'
+  0x2000021A:  00           DC.B       0x00                     ; '\0'
+  0x2000021B:  00           DC.B       0x00                     ; '\0'
+  0x2000021C:  00           DC.B       0x00                     ; '\0'
+  0x2000021D:  00           DC.B       0x00                     ; '\0'
+  0x2000021E:  00           DC.B       0x00                     ; '\0'
+  0x2000021F:  00           DC.B       0x00                     ; '\0'
+  0x20000220:  00           DC.B       0x00                     ; '\0'
+  0x20000221:  00           DC.B       0x00                     ; '\0'
+  0x20000222:  00           DC.B       0x00                     ; '\0'
+  0x20000223:  00           DC.B       0x00                     ; '\0'
+  0x20000224:  00           DC.B       0x00                     ; '\0'
+  0x20000225:  00           DC.B       0x00                     ; '\0'
+  0x20000226:  00           DC.B       0x00                     ; '\0'
+  0x20000227:  00           DC.B       0x00                     ; '\0'
+  0x20000228:  00           DC.B       0x00                     ; '\0'
+  0x20000229:  00           DC.B       0x00                     ; '\0'
+  0x2000022A:  00           DC.B       0x00                     ; '\0'
+  0x2000022B:  00           DC.B       0x00                     ; '\0'
+  0x2000022C:  00           DC.B       0x00                     ; '\0'
+  0x2000022D:  00           DC.B       0x00                     ; '\0'
+  0x2000022E:  00           DC.B       0x00                     ; '\0'
+  0x2000022F:  00           DC.B       0x00                     ; '\0'
+  0x20000230:  00           DC.B       0x00                     ; '\0'
+  0x20000231:  00           DC.B       0x00                     ; '\0'
+  0x20000232:  00           DC.B       0x00                     ; '\0'
+  0x20000233:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.sys_data from PowerPro_lto.o, size=224, align=4

+
+
sys_data:
+  0x20000234:  76           DC.B       0x76                     ; 'v'
+  0x20000235:  6F           DC.B       0x6F                     ; 'o'
+  0x20000236:  6C           DC.B       0x6C                     ; 'l'
+  0x20000237:  74           DC.B       0x74                     ; 't'
+  0x20000238:  61           DC.B       0x61                     ; 'a'
+  0x20000239:  67           DC.B       0x67                     ; 'g'
+  0x2000023A:  65           DC.B       0x65                     ; 'e'
+  0x2000023B:  20           DC.B       0x20                     ; ' '
+  0x2000023C:  69           DC.B       0x69                     ; 'i'
+  0x2000023D:  6E           DC.B       0x6E                     ; 'n'
+  0x2000023E:  3D           DC.B       0x3D                     ; '='
+  0x2000023F:  20           DC.B       0x20                     ; ' '
+  0x20000240:  25           DC.B       0x25                     ; '%'
+  0x20000241:  64           DC.B       0x64                     ; 'd'
+  0x20000242:  2C           DC.B       0x2C                     ; ','
+  0x20000243:  20           DC.B       0x20                     ; ' '
+  0x20000244:  6F           DC.B       0x6F                     ; 'o'
+  0x20000245:  75           DC.B       0x75                     ; 'u'
+  0x20000246:  74           DC.B       0x74                     ; 't'
+  0x20000247:  3D           DC.B       0x3D                     ; '='
+  0x20000248:  20           DC.B       0x20                     ; ' '
+  0x20000249:  25           DC.B       0x25                     ; '%'
+  0x2000024A:  64           DC.B       0x64                     ; 'd'
+  0x2000024B:  2C           DC.B       0x2C                     ; ','
+  0x2000024C:  20           DC.B       0x20                     ; ' '
+  0x2000024D:  64           DC.B       0x64                     ; 'd'
+  0x2000024E:  72           DC.B       0x72                     ; 'r'
+  0x2000024F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000250:  70           DC.B       0x70                     ; 'p'
+  0x20000251:  20           DC.B       0x20                     ; ' '
+  0x20000252:  25           DC.B       0x25                     ; '%'
+  0x20000253:  64           DC.B       0x64                     ; 'd'
+  0x20000254:  0D           DC.B       0x0D                     ; '\r'
+  0x20000255:  0A           DC.B       0x0A                     ; '\n'
+  0x20000256:  00           DC.B       0x00                     ; '\0'
+  0x20000257:  00           DC.B       0x00                     ; '\0'
+  0x20000258:  53           DC.B       0x53                     ; 'S'
+  0x20000259:  45           DC.B       0x45                     ; 'E'
+  0x2000025A:  47           DC.B       0x47                     ; 'G'
+  0x2000025B:  47           DC.B       0x47                     ; 'G'
+  0x2000025C:  45           DC.B       0x45                     ; 'E'
+  0x2000025D:  52           DC.B       0x52                     ; 'R'
+  0x2000025E:  20           DC.B       0x20                     ; ' '
+  0x2000025F:  43           DC.B       0x43                     ; 'C'
+  0x20000260:  2F           DC.B       0x2F                     ; '/'
+  0x20000261:  43           DC.B       0x43                     ; 'C'
+  0x20000262:  2B           DC.B       0x2B                     ; '+'
+  0x20000263:  2B           DC.B       0x2B                     ; '+'
+  0x20000264:  20           DC.B       0x20                     ; ' '
+  0x20000265:  63           DC.B       0x63                     ; 'c'
+  0x20000266:  6F           DC.B       0x6F                     ; 'o'
+  0x20000267:  6D           DC.B       0x6D                     ; 'm'
+  0x20000268:  70           DC.B       0x70                     ; 'p'
+  0x20000269:  69           DC.B       0x69                     ; 'i'
+  0x2000026A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000026B:  65           DC.B       0x65                     ; 'e'
+  0x2000026C:  72           DC.B       0x72                     ; 'r'
+  0x2000026D:  20           DC.B       0x20                     ; ' '
+  0x2000026E:  76           DC.B       0x76                     ; 'v'
+  0x2000026F:  65           DC.B       0x65                     ; 'e'
+  0x20000270:  72           DC.B       0x72                     ; 'r'
+  0x20000271:  73           DC.B       0x73                     ; 's'
+  0x20000272:  69           DC.B       0x69                     ; 'i'
+  0x20000273:  6F           DC.B       0x6F                     ; 'o'
+  0x20000274:  6E           DC.B       0x6E                     ; 'n'
+  0x20000275:  20           DC.B       0x20                     ; ' '
+  0x20000276:  32           DC.B       0x32                     ; '2'
+  0x20000277:  30           DC.B       0x30                     ; '0'
+  0x20000278:  2E           DC.B       0x2E                     ; '.'
+  0x20000279:  31           DC.B       0x31                     ; '1'
+  0x2000027A:  2E           DC.B       0x2E                     ; '.'
+  0x2000027B:  32           DC.B       0x32                     ; '2'
+  0x2000027C:  20           DC.B       0x20                     ; ' '
+  0x2000027D:  28           DC.B       0x28                     ; '('
+  0x2000027E:  62           DC.B       0x62                     ; 'b'
+  0x2000027F:  61           DC.B       0x61                     ; 'a'
+  0x20000280:  73           DC.B       0x73                     ; 's'
+  0x20000281:  65           DC.B       0x65                     ; 'e'
+  0x20000282:  64           DC.B       0x64                     ; 'd'
+  0x20000283:  20           DC.B       0x20                     ; ' '
+  0x20000284:  6F           DC.B       0x6F                     ; 'o'
+  0x20000285:  6E           DC.B       0x6E                     ; 'n'
+  0x20000286:  20           DC.B       0x20                     ; ' '
+  0x20000287:  63           DC.B       0x63                     ; 'c'
+  0x20000288:  6C           DC.B       0x6C                     ; 'l'
+  0x20000289:  61           DC.B       0x61                     ; 'a'
+  0x2000028A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000028B:  67           DC.B       0x67                     ; 'g'
+  0x2000028C:  20           DC.B       0x20                     ; ' '
+  0x2000028D:  32           DC.B       0x32                     ; '2'
+  0x2000028E:  30           DC.B       0x30                     ; '0'
+  0x2000028F:  2E           DC.B       0x2E                     ; '.'
+  0x20000290:  31           DC.B       0x31                     ; '1'
+  0x20000291:  2E           DC.B       0x2E                     ; '.'
+  0x20000292:  38           DC.B       0x38                     ; '8'
+  0x20000293:  29           DC.B       0x29                     ; ')'
+  0x20000294:  00           DC.B       0x00                     ; '\0'
+  0x20000295:  53           DC.B       0x53                     ; 'S'
+  0x20000296:  45           DC.B       0x45                     ; 'E'
+  0x20000297:  47           DC.B       0x47                     ; 'G'
+  0x20000298:  47           DC.B       0x47                     ; 'G'
+  0x20000299:  45           DC.B       0x45                     ; 'E'
+  0x2000029A:  52           DC.B       0x52                     ; 'R'
+  0x2000029B:  20           DC.B       0x20                     ; ' '
+  0x2000029C:  43           DC.B       0x43                     ; 'C'
+  0x2000029D:  2F           DC.B       0x2F                     ; '/'
+  0x2000029E:  43           DC.B       0x43                     ; 'C'
+  0x2000029F:  2B           DC.B       0x2B                     ; '+'
+  0x200002A0:  2B           DC.B       0x2B                     ; '+'
+  0x200002A1:  20           DC.B       0x20                     ; ' '
+  0x200002A2:  63           DC.B       0x63                     ; 'c'
+  0x200002A3:  6F           DC.B       0x6F                     ; 'o'
+  0x200002A4:  6D           DC.B       0x6D                     ; 'm'
+  0x200002A5:  70           DC.B       0x70                     ; 'p'
+  0x200002A6:  69           DC.B       0x69                     ; 'i'
+  0x200002A7:  6C           DC.B       0x6C                     ; 'l'
+  0x200002A8:  65           DC.B       0x65                     ; 'e'
+  0x200002A9:  72           DC.B       0x72                     ; 'r'
+  0x200002AA:  20           DC.B       0x20                     ; ' '
+  0x200002AB:  76           DC.B       0x76                     ; 'v'
+  0x200002AC:  65           DC.B       0x65                     ; 'e'
+  0x200002AD:  72           DC.B       0x72                     ; 'r'
+  0x200002AE:  73           DC.B       0x73                     ; 's'
+  0x200002AF:  69           DC.B       0x69                     ; 'i'
+  0x200002B0:  6F           DC.B       0x6F                     ; 'o'
+  0x200002B1:  6E           DC.B       0x6E                     ; 'n'
+  0x200002B2:  20           DC.B       0x20                     ; ' '
+  0x200002B3:  32           DC.B       0x32                     ; '2'
+  0x200002B4:  30           DC.B       0x30                     ; '0'
+  0x200002B5:  2E           DC.B       0x2E                     ; '.'
+  0x200002B6:  31           DC.B       0x31                     ; '1'
+  0x200002B7:  2E           DC.B       0x2E                     ; '.'
+  0x200002B8:  32           DC.B       0x32                     ; '2'
+  0x200002B9:  20           DC.B       0x20                     ; ' '
+  0x200002BA:  28           DC.B       0x28                     ; '('
+  0x200002BB:  62           DC.B       0x62                     ; 'b'
+  0x200002BC:  61           DC.B       0x61                     ; 'a'
+  0x200002BD:  73           DC.B       0x73                     ; 's'
+  0x200002BE:  65           DC.B       0x65                     ; 'e'
+  0x200002BF:  64           DC.B       0x64                     ; 'd'
+  0x200002C0:  20           DC.B       0x20                     ; ' '
+  0x200002C1:  6F           DC.B       0x6F                     ; 'o'
+  0x200002C2:  6E           DC.B       0x6E                     ; 'n'
+  0x200002C3:  20           DC.B       0x20                     ; ' '
+  0x200002C4:  63           DC.B       0x63                     ; 'c'
+  0x200002C5:  6C           DC.B       0x6C                     ; 'l'
+  0x200002C6:  61           DC.B       0x61                     ; 'a'
+  0x200002C7:  6E           DC.B       0x6E                     ; 'n'
+  0x200002C8:  67           DC.B       0x67                     ; 'g'
+  0x200002C9:  20           DC.B       0x20                     ; ' '
+  0x200002CA:  32           DC.B       0x32                     ; '2'
+  0x200002CB:  30           DC.B       0x30                     ; '0'
+  0x200002CC:  2E           DC.B       0x2E                     ; '.'
+  0x200002CD:  31           DC.B       0x31                     ; '1'
+  0x200002CE:  2E           DC.B       0x2E                     ; '.'
+  0x200002CF:  38           DC.B       0x38                     ; '8'
+  0x200002D0:  29           DC.B       0x29                     ; ')'
+  0x200002D1:  00           DC.B       0x00                     ; '\0'
+  0x200002D2:  53           DC.B       0x53                     ; 'S'
+  0x200002D3:  45           DC.B       0x45                     ; 'E'
+  0x200002D4:  47           DC.B       0x47                     ; 'G'
+  0x200002D5:  47           DC.B       0x47                     ; 'G'
+  0x200002D6:  45           DC.B       0x45                     ; 'E'
+  0x200002D7:  52           DC.B       0x52                     ; 'R'
+  0x200002D8:  20           DC.B       0x20                     ; ' '
+  0x200002D9:  43           DC.B       0x43                     ; 'C'
+  0x200002DA:  2F           DC.B       0x2F                     ; '/'
+  0x200002DB:  43           DC.B       0x43                     ; 'C'
+  0x200002DC:  2B           DC.B       0x2B                     ; '+'
+  0x200002DD:  2B           DC.B       0x2B                     ; '+'
+  0x200002DE:  20           DC.B       0x20                     ; ' '
+  0x200002DF:  63           DC.B       0x63                     ; 'c'
+  0x200002E0:  6F           DC.B       0x6F                     ; 'o'
+  0x200002E1:  6D           DC.B       0x6D                     ; 'm'
+  0x200002E2:  70           DC.B       0x70                     ; 'p'
+  0x200002E3:  69           DC.B       0x69                     ; 'i'
+  0x200002E4:  6C           DC.B       0x6C                     ; 'l'
+  0x200002E5:  65           DC.B       0x65                     ; 'e'
+  0x200002E6:  72           DC.B       0x72                     ; 'r'
+  0x200002E7:  20           DC.B       0x20                     ; ' '
+  0x200002E8:  76           DC.B       0x76                     ; 'v'
+  0x200002E9:  65           DC.B       0x65                     ; 'e'
+  0x200002EA:  72           DC.B       0x72                     ; 'r'
+  0x200002EB:  73           DC.B       0x73                     ; 's'
+  0x200002EC:  69           DC.B       0x69                     ; 'i'
+  0x200002ED:  6F           DC.B       0x6F                     ; 'o'
+  0x200002EE:  6E           DC.B       0x6E                     ; 'n'
+  0x200002EF:  20           DC.B       0x20                     ; ' '
+  0x200002F0:  32           DC.B       0x32                     ; '2'
+  0x200002F1:  30           DC.B       0x30                     ; '0'
+  0x200002F2:  2E           DC.B       0x2E                     ; '.'
+  0x200002F3:  31           DC.B       0x31                     ; '1'
+  0x200002F4:  2E           DC.B       0x2E                     ; '.'
+  0x200002F5:  32           DC.B       0x32                     ; '2'
+  0x200002F6:  20           DC.B       0x20                     ; ' '
+  0x200002F7:  28           DC.B       0x28                     ; '('
+  0x200002F8:  62           DC.B       0x62                     ; 'b'
+  0x200002F9:  61           DC.B       0x61                     ; 'a'
+  0x200002FA:  73           DC.B       0x73                     ; 's'
+  0x200002FB:  65           DC.B       0x65                     ; 'e'
+  0x200002FC:  64           DC.B       0x64                     ; 'd'
+  0x200002FD:  20           DC.B       0x20                     ; ' '
+  0x200002FE:  6F           DC.B       0x6F                     ; 'o'
+  0x200002FF:  6E           DC.B       0x6E                     ; 'n'
+  0x20000300:  20           DC.B       0x20                     ; ' '
+  0x20000301:  63           DC.B       0x63                     ; 'c'
+  0x20000302:  6C           DC.B       0x6C                     ; 'l'
+  0x20000303:  61           DC.B       0x61                     ; 'a'
+  0x20000304:  6E           DC.B       0x6E                     ; 'n'
+  0x20000305:  67           DC.B       0x67                     ; 'g'
+  0x20000306:  20           DC.B       0x20                     ; ' '
+  0x20000307:  32           DC.B       0x32                     ; '2'
+  0x20000308:  30           DC.B       0x30                     ; '0'
+  0x20000309:  2E           DC.B       0x2E                     ; '.'
+  0x2000030A:  31           DC.B       0x31                     ; '1'
+  0x2000030B:  2E           DC.B       0x2E                     ; '.'
+  0x2000030C:  38           DC.B       0x38                     ; '8'
+  0x2000030D:  29           DC.B       0x29                     ; ')'
+  0x2000030E:  00           DC.B       0x00                     ; '\0'
+  0x2000030F:  53           DC.B       0x53                     ; 'S'
+  0x20000310:  45           DC.B       0x45                     ; 'E'
+  0x20000311:  47           DC.B       0x47                     ; 'G'
+  0x20000312:  47           DC.B       0x47                     ; 'G'
+  0x20000313:  45           DC.B       0x45                     ; 'E'
+
+

Section .bss.libc._SEGGER_RTT from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=168, align=4

+
+
_SEGGER_RTT:
+  0x20000314:  30           DC.B       0x30                     ; '0'
+  0x20000315:  31           DC.B       0x31                     ; '1'
+  0x20000316:  32           DC.B       0x32                     ; '2'
+  0x20000317:  33           DC.B       0x33                     ; '3'
+  0x20000318:  34           DC.B       0x34                     ; '4'
+  0x20000319:  35           DC.B       0x35                     ; '5'
+  0x2000031A:  36           DC.B       0x36                     ; '6'
+  0x2000031B:  37           DC.B       0x37                     ; '7'
+  0x2000031C:  38           DC.B       0x38                     ; '8'
+  0x2000031D:  39           DC.B       0x39                     ; '9'
+  0x2000031E:  41           DC.B       0x41                     ; 'A'
+  0x2000031F:  42           DC.B       0x42                     ; 'B'
+  0x20000320:  43           DC.B       0x43                     ; 'C'
+  0x20000321:  44           DC.B       0x44                     ; 'D'
+  0x20000322:  45           DC.B       0x45                     ; 'E'
+  0x20000323:  46           DC.B       0x46                     ; 'F'
+  0x20000324:  00           DC.B       0x00                     ; '\0'
+  0x20000325:  00           DC.B       0x00                     ; '\0'
+  0x20000326:  00           DC.B       0x00                     ; '\0'
+  0x20000327:  00           DC.B       0x00                     ; '\0'
+  0x20000328:  00           DC.B       0x00                     ; '\0'
+  0x20000329:  00           DC.B       0x00                     ; '\0'
+  0x2000032A:  54           DC.B       0x54                     ; 'T'
+  0x2000032B:  54           DC.B       0x54                     ; 'T'
+  0x2000032C:  52           DC.B       0x52                     ; 'R'
+  0x2000032D:  20           DC.B       0x20                     ; ' '
+  0x2000032E:  52           DC.B       0x52                     ; 'R'
+  0x2000032F:  45           DC.B       0x45                     ; 'E'
+  0x20000330:  47           DC.B       0x47                     ; 'G'
+  0x20000331:  47           DC.B       0x47                     ; 'G'
+  0x20000332:  45           DC.B       0x45                     ; 'E'
+  0x20000333:  53           DC.B       0x53                     ; 'S'
+  0x20000334:  00           DC.B       0x00                     ; '\0'
+  0x20000335:  54           DC.B       0x54                     ; 'T'
+  0x20000336:  65           DC.B       0x65                     ; 'e'
+  0x20000337:  72           DC.B       0x72                     ; 'r'
+  0x20000338:  6D           DC.B       0x6D                     ; 'm'
+  0x20000339:  69           DC.B       0x69                     ; 'i'
+  0x2000033A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000033B:  61           DC.B       0x61                     ; 'a'
+  0x2000033C:  6C           DC.B       0x6C                     ; 'l'
+  0x2000033D:  00           DC.B       0x00                     ; '\0'
+  0x2000033E:  00           DC.B       0x00                     ; '\0'
+  0x2000033F:  53           DC.B       0x53                     ; 'S'
+  0x20000340:  45           DC.B       0x45                     ; 'E'
+  0x20000341:  47           DC.B       0x47                     ; 'G'
+  0x20000342:  47           DC.B       0x47                     ; 'G'
+  0x20000343:  45           DC.B       0x45                     ; 'E'
+  0x20000344:  52           DC.B       0x52                     ; 'R'
+  0x20000345:  20           DC.B       0x20                     ; ' '
+  0x20000346:  43           DC.B       0x43                     ; 'C'
+  0x20000347:  2F           DC.B       0x2F                     ; '/'
+  0x20000348:  43           DC.B       0x43                     ; 'C'
+  0x20000349:  2B           DC.B       0x2B                     ; '+'
+  0x2000034A:  2B           DC.B       0x2B                     ; '+'
+  0x2000034B:  20           DC.B       0x20                     ; ' '
+  0x2000034C:  63           DC.B       0x63                     ; 'c'
+  0x2000034D:  6F           DC.B       0x6F                     ; 'o'
+  0x2000034E:  6D           DC.B       0x6D                     ; 'm'
+  0x2000034F:  70           DC.B       0x70                     ; 'p'
+  0x20000350:  69           DC.B       0x69                     ; 'i'
+  0x20000351:  6C           DC.B       0x6C                     ; 'l'
+  0x20000352:  65           DC.B       0x65                     ; 'e'
+  0x20000353:  72           DC.B       0x72                     ; 'r'
+  0x20000354:  20           DC.B       0x20                     ; ' '
+  0x20000355:  76           DC.B       0x76                     ; 'v'
+  0x20000356:  65           DC.B       0x65                     ; 'e'
+  0x20000357:  72           DC.B       0x72                     ; 'r'
+  0x20000358:  73           DC.B       0x73                     ; 's'
+  0x20000359:  69           DC.B       0x69                     ; 'i'
+  0x2000035A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000035B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000035C:  20           DC.B       0x20                     ; ' '
+  0x2000035D:  32           DC.B       0x32                     ; '2'
+  0x2000035E:  30           DC.B       0x30                     ; '0'
+  0x2000035F:  2E           DC.B       0x2E                     ; '.'
+  0x20000360:  31           DC.B       0x31                     ; '1'
+  0x20000361:  2E           DC.B       0x2E                     ; '.'
+  0x20000362:  32           DC.B       0x32                     ; '2'
+  0x20000363:  20           DC.B       0x20                     ; ' '
+  0x20000364:  28           DC.B       0x28                     ; '('
+  0x20000365:  62           DC.B       0x62                     ; 'b'
+  0x20000366:  61           DC.B       0x61                     ; 'a'
+  0x20000367:  73           DC.B       0x73                     ; 's'
+  0x20000368:  65           DC.B       0x65                     ; 'e'
+  0x20000369:  64           DC.B       0x64                     ; 'd'
+  0x2000036A:  20           DC.B       0x20                     ; ' '
+  0x2000036B:  6F           DC.B       0x6F                     ; 'o'
+  0x2000036C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000036D:  20           DC.B       0x20                     ; ' '
+  0x2000036E:  63           DC.B       0x63                     ; 'c'
+  0x2000036F:  6C           DC.B       0x6C                     ; 'l'
+  0x20000370:  61           DC.B       0x61                     ; 'a'
+  0x20000371:  6E           DC.B       0x6E                     ; 'n'
+  0x20000372:  67           DC.B       0x67                     ; 'g'
+  0x20000373:  20           DC.B       0x20                     ; ' '
+  0x20000374:  32           DC.B       0x32                     ; '2'
+  0x20000375:  30           DC.B       0x30                     ; '0'
+  0x20000376:  2E           DC.B       0x2E                     ; '.'
+  0x20000377:  31           DC.B       0x31                     ; '1'
+  0x20000378:  2E           DC.B       0x2E                     ; '.'
+  0x20000379:  38           DC.B       0x38                     ; '8'
+  0x2000037A:  29           DC.B       0x29                     ; ')'
+  0x2000037B:  00           DC.B       0x00                     ; '\0'
+  0x2000037C:  41           DC.B       0x41                     ; 'A'
+  0x2000037D:  35           DC.B       0x35                     ; '5'
+  0x2000037E:  00           DC.B       0x00                     ; '\0'
+  0x2000037F:  00           DC.B       0x00                     ; '\0'
+  0x20000380:  00           DC.B       0x00                     ; '\0'
+  0x20000381:  61           DC.B       0x61                     ; 'a'
+  0x20000382:  65           DC.B       0x65                     ; 'e'
+  0x20000383:  61           DC.B       0x61                     ; 'a'
+  0x20000384:  62           DC.B       0x62                     ; 'b'
+  0x20000385:  69           DC.B       0x69                     ; 'i'
+  0x20000386:  00           DC.B       0x00                     ; '\0'
+  0x20000387:  01           DC.B       0x01                     ; '\x01'
+  0x20000388:  2B           DC.B       0x2B                     ; '+'
+  0x20000389:  00           DC.B       0x00                     ; '\0'
+  0x2000038A:  00           DC.B       0x00                     ; '\0'
+  0x2000038B:  00           DC.B       0x00                     ; '\0'
+  0x2000038C:  43           DC.B       0x43                     ; 'C'
+  0x2000038D:  32           DC.B       0x32                     ; '2'
+  0x2000038E:  2E           DC.B       0x2E                     ; '.'
+  0x2000038F:  30           DC.B       0x30                     ; '0'
+  0x20000390:  39           DC.B       0x39                     ; '9'
+  0x20000391:  00           DC.B       0x00                     ; '\0'
+  0x20000392:  06           DC.B       0x06                     ; '\x06'
+  0x20000393:  0C           DC.B       0x0C                     ; '\x0C'
+  0x20000394:  07           DC.B       0x07                     ; '\x07'
+  0x20000395:  4D           DC.B       0x4D                     ; 'M'
+  0x20000396:  08           DC.B       0x08                     ; '\b'
+  0x20000397:  00           DC.B       0x00                     ; '\0'
+  0x20000398:  09           DC.B       0x09                     ; '\t'
+  0x20000399:  01           DC.B       0x01                     ; '\x01'
+  0x2000039A:  0E           DC.B       0x0E                     ; '\x0E'
+  0x2000039B:  00           DC.B       0x00                     ; '\0'
+  0x2000039C:  11           DC.B       0x11                     ; '\x11'
+  0x2000039D:  01           DC.B       0x01                     ; '\x01'
+  0x2000039E:  12           DC.B       0x12                     ; '\x12'
+  0x2000039F:  04           DC.B       0x04                     ; '\x04'
+  0x200003A0:  14           DC.B       0x14                     ; '\x14'
+  0x200003A1:  01           DC.B       0x01                     ; '\x01'
+  0x200003A2:  15           DC.B       0x15                     ; '\x15'
+  0x200003A3:  00           DC.B       0x00                     ; '\0'
+  0x200003A4:  17           DC.B       0x17                     ; '\x17'
+  0x200003A5:  03           DC.B       0x03                     ; '\x03'
+  0x200003A6:  18           DC.B       0x18                     ; '\x18'
+  0x200003A7:  01           DC.B       0x01                     ; '\x01'
+  0x200003A8:  19           DC.B       0x19                     ; '\x19'
+  0x200003A9:  01           DC.B       0x01                     ; '\x01'
+  0x200003AA:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200003AB:  01           DC.B       0x01                     ; '\x01'
+  0x200003AC:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200003AD:  04           DC.B       0x04                     ; '\x04'
+  0x200003AE:  22           DC.B       0x22                     ; '\"'
+  0x200003AF:  00           DC.B       0x00                     ; '\0'
+  0x200003B0:  26           DC.B       0x26                     ; '&'
+  0x200003B1:  01           DC.B       0x01                     ; '\x01'
+  0x200003B2:  00           DC.B       0x00                     ; '\0'
+  0x200003B3:  00           DC.B       0x00                     ; '\0'
+  0x200003B4:  00           DC.B       0x00                     ; '\0'
+  0x200003B5:  00           DC.B       0x00                     ; '\0'
+  0x200003B6:  00           DC.B       0x00                     ; '\0'
+  0x200003B7:  00           DC.B       0x00                     ; '\0'
+  0x200003B8:  00           DC.B       0x00                     ; '\0'
+  0x200003B9:  00           DC.B       0x00                     ; '\0'
+  0x200003BA:  00           DC.B       0x00                     ; '\0'
+  0x200003BB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.huart1 from PowerPro_lto.o, size=148, align=4

+
+
huart1:
+  0x200003BC:  73           DC.B       0x73                     ; 's'
+  0x200003BD:  65           DC.B       0x65                     ; 'e'
+  0x200003BE:  74           DC.B       0x74                     ; 't'
+  0x200003BF:  7A           DC.B       0x7A                     ; 'z'
+  0x200003C0:  65           DC.B       0x65                     ; 'e'
+  0x200003C1:  20           DC.B       0x20                     ; ' '
+  0x200003C2:  6F           DC.B       0x6F                     ; 'o'
+  0x200003C3:  70           DC.B       0x70                     ; 'p'
+  0x200003C4:  74           DC.B       0x74                     ; 't'
+  0x200003C5:  69           DC.B       0x69                     ; 'i'
+  0x200003C6:  6F           DC.B       0x6F                     ; 'o'
+  0x200003C7:  6E           DC.B       0x6E                     ; 'n'
+  0x200003C8:  20           DC.B       0x20                     ; ' '
+  0x200003C9:  62           DC.B       0x62                     ; 'b'
+  0x200003CA:  79           DC.B       0x79                     ; 'y'
+  0x200003CB:  74           DC.B       0x74                     ; 't'
+  0x200003CC:  65           DC.B       0x65                     ; 'e'
+  0x200003CD:  0D           DC.B       0x0D                     ; '\r'
+  0x200003CE:  00           DC.B       0x00                     ; '\0'
+  0x200003CF:  4B           DC.B       0x4B                     ; 'K'
+  0x200003D0:  6F           DC.B       0x6F                     ; 'o'
+  0x200003D1:  6E           DC.B       0x6E                     ; 'n'
+  0x200003D2:  66           DC.B       0x66                     ; 'f'
+  0x200003D3:  69           DC.B       0x69                     ; 'i'
+  0x200003D4:  67           DC.B       0x67                     ; 'g'
+  0x200003D5:  20           DC.B       0x20                     ; ' '
+  0x200003D6:  76           DC.B       0x76                     ; 'v'
+  0x200003D7:  6F           DC.B       0x6F                     ; 'o'
+  0x200003D8:  72           DC.B       0x72                     ; 'r'
+  0x200003D9:  68           DC.B       0x68                     ; 'h'
+  0x200003DA:  61           DC.B       0x61                     ; 'a'
+  0x200003DB:  6E           DC.B       0x6E                     ; 'n'
+  0x200003DC:  64           DC.B       0x64                     ; 'd'
+  0x200003DD:  65           DC.B       0x65                     ; 'e'
+  0x200003DE:  6E           DC.B       0x6E                     ; 'n'
+  0x200003DF:  0D           DC.B       0x0D                     ; '\r'
+  0x200003E0:  00           DC.B       0x00                     ; '\0'
+  0x200003E1:  4E           DC.B       0x4E                     ; 'N'
+  0x200003E2:  65           DC.B       0x65                     ; 'e'
+  0x200003E3:  75           DC.B       0x75                     ; 'u'
+  0x200003E4:  65           DC.B       0x65                     ; 'e'
+  0x200003E5:  20           DC.B       0x20                     ; ' '
+  0x200003E6:  56           DC.B       0x56                     ; 'V'
+  0x200003E7:  65           DC.B       0x65                     ; 'e'
+  0x200003E8:  72           DC.B       0x72                     ; 'r'
+  0x200003E9:  73           DC.B       0x73                     ; 's'
+  0x200003EA:  69           DC.B       0x69                     ; 'i'
+  0x200003EB:  6F           DC.B       0x6F                     ; 'o'
+  0x200003EC:  6E           DC.B       0x6E                     ; 'n'
+  0x200003ED:  20           DC.B       0x20                     ; ' '
+  0x200003EE:  50           DC.B       0x50                     ; 'P'
+  0x200003EF:  61           DC.B       0x61                     ; 'a'
+  0x200003F0:  72           DC.B       0x72                     ; 'r'
+  0x200003F1:  61           DC.B       0x61                     ; 'a'
+  0x200003F2:  6D           DC.B       0x6D                     ; 'm'
+  0x200003F3:  65           DC.B       0x65                     ; 'e'
+  0x200003F4:  74           DC.B       0x74                     ; 't'
+  0x200003F5:  65           DC.B       0x65                     ; 'e'
+  0x200003F6:  72           DC.B       0x72                     ; 'r'
+  0x200003F7:  20           DC.B       0x20                     ; ' '
+  0x200003F8:  65           DC.B       0x65                     ; 'e'
+  0x200003F9:  72           DC.B       0x72                     ; 'r'
+  0x200003FA:  6B           DC.B       0x6B                     ; 'k'
+  0x200003FB:  61           DC.B       0x61                     ; 'a'
+  0x200003FC:  6E           DC.B       0x6E                     ; 'n'
+  0x200003FD:  6E           DC.B       0x6E                     ; 'n'
+  0x200003FE:  74           DC.B       0x74                     ; 't'
+  0x200003FF:  2C           DC.B       0x2C                     ; ','
+  0x20000400:  20           DC.B       0x20                     ; ' '
+  0x20000401:  73           DC.B       0x73                     ; 's'
+  0x20000402:  63           DC.B       0x63                     ; 'c'
+  0x20000403:  68           DC.B       0x68                     ; 'h'
+  0x20000404:  72           DC.B       0x72                     ; 'r'
+  0x20000405:  65           DC.B       0x65                     ; 'e'
+  0x20000406:  69           DC.B       0x69                     ; 'i'
+  0x20000407:  62           DC.B       0x62                     ; 'b'
+  0x20000408:  65           DC.B       0x65                     ; 'e'
+  0x20000409:  20           DC.B       0x20                     ; ' '
+  0x2000040A:  57           DC.B       0x57                     ; 'W'
+  0x2000040B:  65           DC.B       0x65                     ; 'e'
+  0x2000040C:  72           DC.B       0x72                     ; 'r'
+  0x2000040D:  6B           DC.B       0x6B                     ; 'k'
+  0x2000040E:  73           DC.B       0x73                     ; 's'
+  0x2000040F:  65           DC.B       0x65                     ; 'e'
+  0x20000410:  69           DC.B       0x69                     ; 'i'
+  0x20000411:  6E           DC.B       0x6E                     ; 'n'
+  0x20000412:  73           DC.B       0x73                     ; 's'
+  0x20000413:  74           DC.B       0x74                     ; 't'
+  0x20000414:  65           DC.B       0x65                     ; 'e'
+  0x20000415:  6C           DC.B       0x6C                     ; 'l'
+  0x20000416:  6C           DC.B       0x6C                     ; 'l'
+  0x20000417:  75           DC.B       0x75                     ; 'u'
+  0x20000418:  6E           DC.B       0x6E                     ; 'n'
+  0x20000419:  67           DC.B       0x67                     ; 'g'
+  0x2000041A:  0D           DC.B       0x0D                     ; '\r'
+  0x2000041B:  00           DC.B       0x00                     ; '\0'
+  0x2000041C:  45           DC.B       0x45                     ; 'E'
+  0x2000041D:  72           DC.B       0x72                     ; 'r'
+  0x2000041E:  73           DC.B       0x73                     ; 's'
+  0x2000041F:  74           DC.B       0x74                     ; 't'
+  0x20000420:  73           DC.B       0x73                     ; 's'
+  0x20000421:  74           DC.B       0x74                     ; 't'
+  0x20000422:  61           DC.B       0x61                     ; 'a'
+  0x20000423:  72           DC.B       0x72                     ; 'r'
+  0x20000424:  74           DC.B       0x74                     ; 't'
+  0x20000425:  20           DC.B       0x20                     ; ' '
+  0x20000426:  65           DC.B       0x65                     ; 'e'
+  0x20000427:  72           DC.B       0x72                     ; 'r'
+  0x20000428:  6B           DC.B       0x6B                     ; 'k'
+  0x20000429:  61           DC.B       0x61                     ; 'a'
+  0x2000042A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000042B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000042C:  74           DC.B       0x74                     ; 't'
+  0x2000042D:  2C           DC.B       0x2C                     ; ','
+  0x2000042E:  20           DC.B       0x20                     ; ' '
+  0x2000042F:  73           DC.B       0x73                     ; 's'
+  0x20000430:  63           DC.B       0x63                     ; 'c'
+  0x20000431:  68           DC.B       0x68                     ; 'h'
+  0x20000432:  72           DC.B       0x72                     ; 'r'
+  0x20000433:  65           DC.B       0x65                     ; 'e'
+  0x20000434:  69           DC.B       0x69                     ; 'i'
+  0x20000435:  62           DC.B       0x62                     ; 'b'
+  0x20000436:  65           DC.B       0x65                     ; 'e'
+  0x20000437:  20           DC.B       0x20                     ; ' '
+  0x20000438:  57           DC.B       0x57                     ; 'W'
+  0x20000439:  65           DC.B       0x65                     ; 'e'
+  0x2000043A:  72           DC.B       0x72                     ; 'r'
+  0x2000043B:  6B           DC.B       0x6B                     ; 'k'
+  0x2000043C:  73           DC.B       0x73                     ; 's'
+  0x2000043D:  65           DC.B       0x65                     ; 'e'
+  0x2000043E:  69           DC.B       0x69                     ; 'i'
+  0x2000043F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000440:  73           DC.B       0x73                     ; 's'
+  0x20000441:  74           DC.B       0x74                     ; 't'
+  0x20000442:  65           DC.B       0x65                     ; 'e'
+  0x20000443:  6C           DC.B       0x6C                     ; 'l'
+  0x20000444:  6C           DC.B       0x6C                     ; 'l'
+  0x20000445:  75           DC.B       0x75                     ; 'u'
+  0x20000446:  6E           DC.B       0x6E                     ; 'n'
+  0x20000447:  67           DC.B       0x67                     ; 'g'
+  0x20000448:  0D           DC.B       0x0D                     ; '\r'
+  0x20000449:  00           DC.B       0x00                     ; '\0'
+  0x2000044A:  64           DC.B       0x64                     ; 'd'
+  0x2000044B:  65           DC.B       0x65                     ; 'e'
+  0x2000044C:  62           DC.B       0x62                     ; 'b'
+  0x2000044D:  75           DC.B       0x75                     ; 'u'
+  0x2000044E:  67           DC.B       0x67                     ; 'g'
+  0x2000044F:  20           DC.B       0x20                     ; ' '
+
+

Section .bss.hadc1 from PowerPro_lto.o, size=100, align=4

+
+
hadc1:
+  0x20000450:  73           DC.B       0x73                     ; 's'
+  0x20000451:  65           DC.B       0x65                     ; 'e'
+  0x20000452:  74           DC.B       0x74                     ; 't'
+  0x20000453:  7A           DC.B       0x7A                     ; 'z'
+  0x20000454:  65           DC.B       0x65                     ; 'e'
+  0x20000455:  20           DC.B       0x20                     ; ' '
+  0x20000456:  6F           DC.B       0x6F                     ; 'o'
+  0x20000457:  70           DC.B       0x70                     ; 'p'
+  0x20000458:  74           DC.B       0x74                     ; 't'
+  0x20000459:  69           DC.B       0x69                     ; 'i'
+  0x2000045A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000045B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000045C:  20           DC.B       0x20                     ; ' '
+  0x2000045D:  62           DC.B       0x62                     ; 'b'
+  0x2000045E:  79           DC.B       0x79                     ; 'y'
+  0x2000045F:  74           DC.B       0x74                     ; 't'
+  0x20000460:  65           DC.B       0x65                     ; 'e'
+  0x20000461:  0D           DC.B       0x0D                     ; '\r'
+  0x20000462:  00           DC.B       0x00                     ; '\0'
+  0x20000463:  4B           DC.B       0x4B                     ; 'K'
+  0x20000464:  6F           DC.B       0x6F                     ; 'o'
+  0x20000465:  6E           DC.B       0x6E                     ; 'n'
+  0x20000466:  66           DC.B       0x66                     ; 'f'
+  0x20000467:  69           DC.B       0x69                     ; 'i'
+  0x20000468:  67           DC.B       0x67                     ; 'g'
+  0x20000469:  20           DC.B       0x20                     ; ' '
+  0x2000046A:  76           DC.B       0x76                     ; 'v'
+  0x2000046B:  6F           DC.B       0x6F                     ; 'o'
+  0x2000046C:  72           DC.B       0x72                     ; 'r'
+  0x2000046D:  68           DC.B       0x68                     ; 'h'
+  0x2000046E:  61           DC.B       0x61                     ; 'a'
+  0x2000046F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000470:  64           DC.B       0x64                     ; 'd'
+  0x20000471:  65           DC.B       0x65                     ; 'e'
+  0x20000472:  6E           DC.B       0x6E                     ; 'n'
+  0x20000473:  0D           DC.B       0x0D                     ; '\r'
+  0x20000474:  00           DC.B       0x00                     ; '\0'
+  0x20000475:  4E           DC.B       0x4E                     ; 'N'
+  0x20000476:  65           DC.B       0x65                     ; 'e'
+  0x20000477:  75           DC.B       0x75                     ; 'u'
+  0x20000478:  65           DC.B       0x65                     ; 'e'
+  0x20000479:  20           DC.B       0x20                     ; ' '
+  0x2000047A:  56           DC.B       0x56                     ; 'V'
+  0x2000047B:  65           DC.B       0x65                     ; 'e'
+  0x2000047C:  72           DC.B       0x72                     ; 'r'
+  0x2000047D:  73           DC.B       0x73                     ; 's'
+  0x2000047E:  69           DC.B       0x69                     ; 'i'
+  0x2000047F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000480:  6E           DC.B       0x6E                     ; 'n'
+  0x20000481:  20           DC.B       0x20                     ; ' '
+  0x20000482:  50           DC.B       0x50                     ; 'P'
+  0x20000483:  61           DC.B       0x61                     ; 'a'
+  0x20000484:  72           DC.B       0x72                     ; 'r'
+  0x20000485:  61           DC.B       0x61                     ; 'a'
+  0x20000486:  6D           DC.B       0x6D                     ; 'm'
+  0x20000487:  65           DC.B       0x65                     ; 'e'
+  0x20000488:  74           DC.B       0x74                     ; 't'
+  0x20000489:  65           DC.B       0x65                     ; 'e'
+  0x2000048A:  72           DC.B       0x72                     ; 'r'
+  0x2000048B:  20           DC.B       0x20                     ; ' '
+  0x2000048C:  65           DC.B       0x65                     ; 'e'
+  0x2000048D:  72           DC.B       0x72                     ; 'r'
+  0x2000048E:  6B           DC.B       0x6B                     ; 'k'
+  0x2000048F:  61           DC.B       0x61                     ; 'a'
+  0x20000490:  6E           DC.B       0x6E                     ; 'n'
+  0x20000491:  6E           DC.B       0x6E                     ; 'n'
+  0x20000492:  74           DC.B       0x74                     ; 't'
+  0x20000493:  2C           DC.B       0x2C                     ; ','
+  0x20000494:  20           DC.B       0x20                     ; ' '
+  0x20000495:  73           DC.B       0x73                     ; 's'
+  0x20000496:  63           DC.B       0x63                     ; 'c'
+  0x20000497:  68           DC.B       0x68                     ; 'h'
+  0x20000498:  72           DC.B       0x72                     ; 'r'
+  0x20000499:  65           DC.B       0x65                     ; 'e'
+  0x2000049A:  69           DC.B       0x69                     ; 'i'
+  0x2000049B:  62           DC.B       0x62                     ; 'b'
+  0x2000049C:  65           DC.B       0x65                     ; 'e'
+  0x2000049D:  20           DC.B       0x20                     ; ' '
+  0x2000049E:  57           DC.B       0x57                     ; 'W'
+  0x2000049F:  65           DC.B       0x65                     ; 'e'
+  0x200004A0:  72           DC.B       0x72                     ; 'r'
+  0x200004A1:  6B           DC.B       0x6B                     ; 'k'
+  0x200004A2:  73           DC.B       0x73                     ; 's'
+  0x200004A3:  65           DC.B       0x65                     ; 'e'
+  0x200004A4:  69           DC.B       0x69                     ; 'i'
+  0x200004A5:  6E           DC.B       0x6E                     ; 'n'
+  0x200004A6:  73           DC.B       0x73                     ; 's'
+  0x200004A7:  74           DC.B       0x74                     ; 't'
+  0x200004A8:  65           DC.B       0x65                     ; 'e'
+  0x200004A9:  6C           DC.B       0x6C                     ; 'l'
+  0x200004AA:  6C           DC.B       0x6C                     ; 'l'
+  0x200004AB:  75           DC.B       0x75                     ; 'u'
+  0x200004AC:  6E           DC.B       0x6E                     ; 'n'
+  0x200004AD:  67           DC.B       0x67                     ; 'g'
+  0x200004AE:  0D           DC.B       0x0D                     ; '\r'
+  0x200004AF:  00           DC.B       0x00                     ; '\0'
+  0x200004B0:  45           DC.B       0x45                     ; 'E'
+  0x200004B1:  72           DC.B       0x72                     ; 'r'
+  0x200004B2:  73           DC.B       0x73                     ; 's'
+  0x200004B3:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.hdma_usart1_tx from PowerPro_lto.o, size=92, align=4

+
+
hdma_usart1_tx:
+  0x200004B4:  00           DC.B       0x00                     ; '\0'
+  0x200004B5:  1B           DC.B       0x1B                     ; '\x1B'
+  0x200004B6:  B7           DC.B       0xB7                     ; '\xB7'
+  0x200004B7:  00           DC.B       0x00                     ; '\0'
+  0x200004B8:  04           DC.B       0x04                     ; '\x04'
+  0x200004B9:  00           DC.B       0x00                     ; '\0'
+  0x200004BA:  00           DC.B       0x00                     ; '\0'
+  0x200004BB:  00           DC.B       0x00                     ; '\0'
+  0x200004BC:  00           DC.B       0x00                     ; '\0'
+  0x200004BD:  00           DC.B       0x00                     ; '\0'
+  0x200004BE:  00           DC.B       0x00                     ; '\0'
+  0x200004BF:  00           DC.B       0x00                     ; '\0'
+  0x200004C0:  00           DC.B       0x00                     ; '\0'
+  0x200004C1:  00           DC.B       0x00                     ; '\0'
+  0x200004C2:  00           DC.B       0x00                     ; '\0'
+  0x200004C3:  00           DC.B       0x00                     ; '\0'
+  0x200004C4:  00           DC.B       0x00                     ; '\0'
+  0x200004C5:  00           DC.B       0x00                     ; '\0'
+  0x200004C6:  00           DC.B       0x00                     ; '\0'
+  0x200004C7:  00           DC.B       0x00                     ; '\0'
+  0x200004C8:  00           DC.B       0x00                     ; '\0'
+  0x200004C9:  00           DC.B       0x00                     ; '\0'
+  0x200004CA:  00           DC.B       0x00                     ; '\0'
+  0x200004CB:  00           DC.B       0x00                     ; '\0'
+  0x200004CC:  00           DC.B       0x00                     ; '\0'
+  0x200004CD:  00           DC.B       0x00                     ; '\0'
+  0x200004CE:  00           DC.B       0x00                     ; '\0'
+  0x200004CF:  00           DC.B       0x00                     ; '\0'
+  0x200004D0:  00           DC.B       0x00                     ; '\0'
+  0x200004D1:  00           DC.B       0x00                     ; '\0'
+  0x200004D2:  00           DC.B       0x00                     ; '\0'
+  0x200004D3:  00           DC.B       0x00                     ; '\0'
+  0x200004D4:  00           DC.B       0x00                     ; '\0'
+  0x200004D5:  00           DC.B       0x00                     ; '\0'
+  0x200004D6:  00           DC.B       0x00                     ; '\0'
+  0x200004D7:  00           DC.B       0x00                     ; '\0'
+  0x200004D8:  00           DC.B       0x00                     ; '\0'
+  0x200004D9:  00           DC.B       0x00                     ; '\0'
+  0x200004DA:  00           DC.B       0x00                     ; '\0'
+  0x200004DB:  00           DC.B       0x00                     ; '\0'
+  0x200004DC:  01           DC.B       0x01                     ; '\x01'
+  0x200004DD:  00           DC.B       0x00                     ; '\0'
+  0x200004DE:  00           DC.B       0x00                     ; '\0'
+  0x200004DF:  00           DC.B       0x00                     ; '\0'
+  0x200004E0:  02           DC.B       0x02                     ; '\x02'
+  0x200004E1:  00           DC.B       0x00                     ; '\0'
+  0x200004E2:  00           DC.B       0x00                     ; '\0'
+  0x200004E3:  00           DC.B       0x00                     ; '\0'
+  0x200004E4:  03           DC.B       0x03                     ; '\x03'
+  0x200004E5:  00           DC.B       0x00                     ; '\0'
+  0x200004E6:  00           DC.B       0x00                     ; '\0'
+  0x200004E7:  00           DC.B       0x00                     ; '\0'
+  0x200004E8:  04           DC.B       0x04                     ; '\x04'
+  0x200004E9:  00           DC.B       0x00                     ; '\0'
+  0x200004EA:  00           DC.B       0x00                     ; '\0'
+  0x200004EB:  00           DC.B       0x00                     ; '\0'
+  0x200004EC:  06           DC.B       0x06                     ; '\x06'
+  0x200004ED:  00           DC.B       0x00                     ; '\0'
+  0x200004EE:  00           DC.B       0x00                     ; '\0'
+  0x200004EF:  00           DC.B       0x00                     ; '\0'
+  0x200004F0:  07           DC.B       0x07                     ; '\x07'
+  0x200004F1:  00           DC.B       0x00                     ; '\0'
+  0x200004F2:  00           DC.B       0x00                     ; '\0'
+  0x200004F3:  00           DC.B       0x00                     ; '\0'
+  0x200004F4:  08           DC.B       0x08                     ; '\b'
+  0x200004F5:  00           DC.B       0x00                     ; '\0'
+  0x200004F6:  00           DC.B       0x00                     ; '\0'
+  0x200004F7:  00           DC.B       0x00                     ; '\0'
+  0x200004F8:  09           DC.B       0x09                     ; '\t'
+  0x200004F9:  00           DC.B       0x00                     ; '\0'
+  0x200004FA:  00           DC.B       0x00                     ; '\0'
+  0x200004FB:  00           DC.B       0x00                     ; '\0'
+  0x200004FC:  00           DC.B       0x00                     ; '\0'
+  0x200004FD:  00           DC.B       0x00                     ; '\0'
+  0x200004FE:  00           DC.B       0x00                     ; '\0'
+  0x200004FF:  00           DC.B       0x00                     ; '\0'
+  0x20000500:  00           DC.B       0x00                     ; '\0'
+  0x20000501:  00           DC.B       0x00                     ; '\0'
+  0x20000502:  00           DC.B       0x00                     ; '\0'
+  0x20000503:  00           DC.B       0x00                     ; '\0'
+  0x20000504:  00           DC.B       0x00                     ; '\0'
+  0x20000505:  00           DC.B       0x00                     ; '\0'
+  0x20000506:  00           DC.B       0x00                     ; '\0'
+  0x20000507:  00           DC.B       0x00                     ; '\0'
+  0x20000508:  00           DC.B       0x00                     ; '\0'
+  0x20000509:  00           DC.B       0x00                     ; '\0'
+  0x2000050A:  00           DC.B       0x00                     ; '\0'
+  0x2000050B:  00           DC.B       0x00                     ; '\0'
+  0x2000050C:  01           DC.B       0x01                     ; '\x01'
+  0x2000050D:  00           DC.B       0x00                     ; '\0'
+  0x2000050E:  00           DC.B       0x00                     ; '\0'
+  0x2000050F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.hdma_usart1_rx from PowerPro_lto.o, size=92, align=4

+
+
hdma_usart1_rx:
+  0x20000510:  00           DC.B       0x00                     ; '\0'
+  0x20000511:  1B           DC.B       0x1B                     ; '\x1B'
+  0x20000512:  B7           DC.B       0xB7                     ; '\xB7'
+  0x20000513:  00           DC.B       0x00                     ; '\0'
+  0x20000514:  04           DC.B       0x04                     ; '\x04'
+  0x20000515:  00           DC.B       0x00                     ; '\0'
+  0x20000516:  00           DC.B       0x00                     ; '\0'
+  0x20000517:  00           DC.B       0x00                     ; '\0'
+  0x20000518:  00           DC.B       0x00                     ; '\0'
+  0x20000519:  00           DC.B       0x00                     ; '\0'
+  0x2000051A:  00           DC.B       0x00                     ; '\0'
+  0x2000051B:  00           DC.B       0x00                     ; '\0'
+  0x2000051C:  00           DC.B       0x00                     ; '\0'
+  0x2000051D:  00           DC.B       0x00                     ; '\0'
+  0x2000051E:  00           DC.B       0x00                     ; '\0'
+  0x2000051F:  00           DC.B       0x00                     ; '\0'
+  0x20000520:  00           DC.B       0x00                     ; '\0'
+  0x20000521:  00           DC.B       0x00                     ; '\0'
+  0x20000522:  00           DC.B       0x00                     ; '\0'
+  0x20000523:  00           DC.B       0x00                     ; '\0'
+  0x20000524:  00           DC.B       0x00                     ; '\0'
+  0x20000525:  00           DC.B       0x00                     ; '\0'
+  0x20000526:  00           DC.B       0x00                     ; '\0'
+  0x20000527:  00           DC.B       0x00                     ; '\0'
+  0x20000528:  00           DC.B       0x00                     ; '\0'
+  0x20000529:  00           DC.B       0x00                     ; '\0'
+  0x2000052A:  00           DC.B       0x00                     ; '\0'
+  0x2000052B:  00           DC.B       0x00                     ; '\0'
+  0x2000052C:  00           DC.B       0x00                     ; '\0'
+  0x2000052D:  00           DC.B       0x00                     ; '\0'
+  0x2000052E:  00           DC.B       0x00                     ; '\0'
+  0x2000052F:  00           DC.B       0x00                     ; '\0'
+  0x20000530:  00           DC.B       0x00                     ; '\0'
+  0x20000531:  00           DC.B       0x00                     ; '\0'
+  0x20000532:  00           DC.B       0x00                     ; '\0'
+  0x20000533:  00           DC.B       0x00                     ; '\0'
+  0x20000534:  00           DC.B       0x00                     ; '\0'
+  0x20000535:  00           DC.B       0x00                     ; '\0'
+  0x20000536:  00           DC.B       0x00                     ; '\0'
+  0x20000537:  00           DC.B       0x00                     ; '\0'
+  0x20000538:  01           DC.B       0x01                     ; '\x01'
+  0x20000539:  00           DC.B       0x00                     ; '\0'
+  0x2000053A:  00           DC.B       0x00                     ; '\0'
+  0x2000053B:  00           DC.B       0x00                     ; '\0'
+  0x2000053C:  02           DC.B       0x02                     ; '\x02'
+  0x2000053D:  00           DC.B       0x00                     ; '\0'
+  0x2000053E:  00           DC.B       0x00                     ; '\0'
+  0x2000053F:  00           DC.B       0x00                     ; '\0'
+  0x20000540:  03           DC.B       0x03                     ; '\x03'
+  0x20000541:  00           DC.B       0x00                     ; '\0'
+  0x20000542:  00           DC.B       0x00                     ; '\0'
+  0x20000543:  00           DC.B       0x00                     ; '\0'
+  0x20000544:  04           DC.B       0x04                     ; '\x04'
+  0x20000545:  00           DC.B       0x00                     ; '\0'
+  0x20000546:  00           DC.B       0x00                     ; '\0'
+  0x20000547:  00           DC.B       0x00                     ; '\0'
+  0x20000548:  06           DC.B       0x06                     ; '\x06'
+  0x20000549:  00           DC.B       0x00                     ; '\0'
+  0x2000054A:  00           DC.B       0x00                     ; '\0'
+  0x2000054B:  00           DC.B       0x00                     ; '\0'
+  0x2000054C:  07           DC.B       0x07                     ; '\x07'
+  0x2000054D:  00           DC.B       0x00                     ; '\0'
+  0x2000054E:  00           DC.B       0x00                     ; '\0'
+  0x2000054F:  00           DC.B       0x00                     ; '\0'
+  0x20000550:  08           DC.B       0x08                     ; '\b'
+  0x20000551:  00           DC.B       0x00                     ; '\0'
+  0x20000552:  00           DC.B       0x00                     ; '\0'
+  0x20000553:  00           DC.B       0x00                     ; '\0'
+  0x20000554:  09           DC.B       0x09                     ; '\t'
+  0x20000555:  00           DC.B       0x00                     ; '\0'
+  0x20000556:  00           DC.B       0x00                     ; '\0'
+  0x20000557:  00           DC.B       0x00                     ; '\0'
+  0x20000558:  00           DC.B       0x00                     ; '\0'
+  0x20000559:  00           DC.B       0x00                     ; '\0'
+  0x2000055A:  00           DC.B       0x00                     ; '\0'
+  0x2000055B:  00           DC.B       0x00                     ; '\0'
+  0x2000055C:  00           DC.B       0x00                     ; '\0'
+  0x2000055D:  00           DC.B       0x00                     ; '\0'
+  0x2000055E:  00           DC.B       0x00                     ; '\0'
+  0x2000055F:  00           DC.B       0x00                     ; '\0'
+  0x20000560:  00           DC.B       0x00                     ; '\0'
+  0x20000561:  00           DC.B       0x00                     ; '\0'
+  0x20000562:  00           DC.B       0x00                     ; '\0'
+  0x20000563:  00           DC.B       0x00                     ; '\0'
+  0x20000564:  00           DC.B       0x00                     ; '\0'
+  0x20000565:  00           DC.B       0x00                     ; '\0'
+  0x20000566:  00           DC.B       0x00                     ; '\0'
+  0x20000567:  00           DC.B       0x00                     ; '\0'
+  0x20000568:  01           DC.B       0x01                     ; '\x01'
+  0x20000569:  00           DC.B       0x00                     ; '\0'
+  0x2000056A:  00           DC.B       0x00                     ; '\0'
+  0x2000056B:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.hdma_adc1 from PowerPro_lto.o, size=92, align=4

+
+
hdma_adc1:
+  0x2000056C:  00           DC.B       0x00                     ; '\0'
+  0x2000056D:  1B           DC.B       0x1B                     ; '\x1B'
+  0x2000056E:  B7           DC.B       0xB7                     ; '\xB7'
+  0x2000056F:  00           DC.B       0x00                     ; '\0'
+  0x20000570:  04           DC.B       0x04                     ; '\x04'
+  0x20000571:  00           DC.B       0x00                     ; '\0'
+  0x20000572:  00           DC.B       0x00                     ; '\0'
+  0x20000573:  00           DC.B       0x00                     ; '\0'
+  0x20000574:  00           DC.B       0x00                     ; '\0'
+  0x20000575:  00           DC.B       0x00                     ; '\0'
+  0x20000576:  00           DC.B       0x00                     ; '\0'
+  0x20000577:  00           DC.B       0x00                     ; '\0'
+  0x20000578:  00           DC.B       0x00                     ; '\0'
+  0x20000579:  00           DC.B       0x00                     ; '\0'
+  0x2000057A:  00           DC.B       0x00                     ; '\0'
+  0x2000057B:  00           DC.B       0x00                     ; '\0'
+  0x2000057C:  00           DC.B       0x00                     ; '\0'
+  0x2000057D:  00           DC.B       0x00                     ; '\0'
+  0x2000057E:  00           DC.B       0x00                     ; '\0'
+  0x2000057F:  00           DC.B       0x00                     ; '\0'
+  0x20000580:  00           DC.B       0x00                     ; '\0'
+  0x20000581:  00           DC.B       0x00                     ; '\0'
+  0x20000582:  00           DC.B       0x00                     ; '\0'
+  0x20000583:  00           DC.B       0x00                     ; '\0'
+  0x20000584:  00           DC.B       0x00                     ; '\0'
+  0x20000585:  00           DC.B       0x00                     ; '\0'
+  0x20000586:  00           DC.B       0x00                     ; '\0'
+  0x20000587:  00           DC.B       0x00                     ; '\0'
+  0x20000588:  00           DC.B       0x00                     ; '\0'
+  0x20000589:  00           DC.B       0x00                     ; '\0'
+  0x2000058A:  00           DC.B       0x00                     ; '\0'
+  0x2000058B:  00           DC.B       0x00                     ; '\0'
+  0x2000058C:  00           DC.B       0x00                     ; '\0'
+  0x2000058D:  00           DC.B       0x00                     ; '\0'
+  0x2000058E:  00           DC.B       0x00                     ; '\0'
+  0x2000058F:  00           DC.B       0x00                     ; '\0'
+  0x20000590:  00           DC.B       0x00                     ; '\0'
+  0x20000591:  00           DC.B       0x00                     ; '\0'
+  0x20000592:  00           DC.B       0x00                     ; '\0'
+  0x20000593:  00           DC.B       0x00                     ; '\0'
+  0x20000594:  01           DC.B       0x01                     ; '\x01'
+  0x20000595:  00           DC.B       0x00                     ; '\0'
+  0x20000596:  00           DC.B       0x00                     ; '\0'
+  0x20000597:  00           DC.B       0x00                     ; '\0'
+  0x20000598:  02           DC.B       0x02                     ; '\x02'
+  0x20000599:  00           DC.B       0x00                     ; '\0'
+  0x2000059A:  00           DC.B       0x00                     ; '\0'
+  0x2000059B:  00           DC.B       0x00                     ; '\0'
+  0x2000059C:  03           DC.B       0x03                     ; '\x03'
+  0x2000059D:  00           DC.B       0x00                     ; '\0'
+  0x2000059E:  00           DC.B       0x00                     ; '\0'
+  0x2000059F:  00           DC.B       0x00                     ; '\0'
+  0x200005A0:  04           DC.B       0x04                     ; '\x04'
+  0x200005A1:  00           DC.B       0x00                     ; '\0'
+  0x200005A2:  00           DC.B       0x00                     ; '\0'
+  0x200005A3:  00           DC.B       0x00                     ; '\0'
+  0x200005A4:  06           DC.B       0x06                     ; '\x06'
+  0x200005A5:  00           DC.B       0x00                     ; '\0'
+  0x200005A6:  00           DC.B       0x00                     ; '\0'
+  0x200005A7:  00           DC.B       0x00                     ; '\0'
+  0x200005A8:  07           DC.B       0x07                     ; '\x07'
+  0x200005A9:  00           DC.B       0x00                     ; '\0'
+  0x200005AA:  00           DC.B       0x00                     ; '\0'
+  0x200005AB:  00           DC.B       0x00                     ; '\0'
+  0x200005AC:  08           DC.B       0x08                     ; '\b'
+  0x200005AD:  00           DC.B       0x00                     ; '\0'
+  0x200005AE:  00           DC.B       0x00                     ; '\0'
+  0x200005AF:  00           DC.B       0x00                     ; '\0'
+  0x200005B0:  09           DC.B       0x09                     ; '\t'
+  0x200005B1:  00           DC.B       0x00                     ; '\0'
+  0x200005B2:  00           DC.B       0x00                     ; '\0'
+  0x200005B3:  00           DC.B       0x00                     ; '\0'
+  0x200005B4:  00           DC.B       0x00                     ; '\0'
+  0x200005B5:  00           DC.B       0x00                     ; '\0'
+  0x200005B6:  00           DC.B       0x00                     ; '\0'
+  0x200005B7:  00           DC.B       0x00                     ; '\0'
+  0x200005B8:  00           DC.B       0x00                     ; '\0'
+  0x200005B9:  00           DC.B       0x00                     ; '\0'
+  0x200005BA:  00           DC.B       0x00                     ; '\0'
+  0x200005BB:  00           DC.B       0x00                     ; '\0'
+  0x200005BC:  00           DC.B       0x00                     ; '\0'
+  0x200005BD:  00           DC.B       0x00                     ; '\0'
+  0x200005BE:  00           DC.B       0x00                     ; '\0'
+  0x200005BF:  00           DC.B       0x00                     ; '\0'
+  0x200005C0:  00           DC.B       0x00                     ; '\0'
+  0x200005C1:  00           DC.B       0x00                     ; '\0'
+  0x200005C2:  00           DC.B       0x00                     ; '\0'
+  0x200005C3:  00           DC.B       0x00                     ; '\0'
+  0x200005C4:  01           DC.B       0x01                     ; '\x01'
+  0x200005C5:  00           DC.B       0x00                     ; '\0'
+  0x200005C6:  00           DC.B       0x00                     ; '\0'
+  0x200005C7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.htim17 from PowerPro_lto.o, size=76, align=4

+
+
htim17:
+  0x200005C8:  00           DC.B       0x00                     ; '\0'
+  0x200005C9:  00           DC.B       0x00                     ; '\0'
+  0x200005CA:  00           DC.B       0x00                     ; '\0'
+  0x200005CB:  00           DC.B       0x00                     ; '\0'
+  0x200005CC:  73           DC.B       0x73                     ; 's'
+  0x200005CD:  65           DC.B       0x65                     ; 'e'
+  0x200005CE:  74           DC.B       0x74                     ; 't'
+  0x200005CF:  7A           DC.B       0x7A                     ; 'z'
+  0x200005D0:  65           DC.B       0x65                     ; 'e'
+  0x200005D1:  20           DC.B       0x20                     ; ' '
+  0x200005D2:  6F           DC.B       0x6F                     ; 'o'
+  0x200005D3:  70           DC.B       0x70                     ; 'p'
+  0x200005D4:  74           DC.B       0x74                     ; 't'
+  0x200005D5:  69           DC.B       0x69                     ; 'i'
+  0x200005D6:  6F           DC.B       0x6F                     ; 'o'
+  0x200005D7:  6E           DC.B       0x6E                     ; 'n'
+  0x200005D8:  20           DC.B       0x20                     ; ' '
+  0x200005D9:  62           DC.B       0x62                     ; 'b'
+  0x200005DA:  79           DC.B       0x79                     ; 'y'
+  0x200005DB:  74           DC.B       0x74                     ; 't'
+  0x200005DC:  65           DC.B       0x65                     ; 'e'
+  0x200005DD:  0D           DC.B       0x0D                     ; '\r'
+  0x200005DE:  00           DC.B       0x00                     ; '\0'
+  0x200005DF:  4B           DC.B       0x4B                     ; 'K'
+  0x200005E0:  6F           DC.B       0x6F                     ; 'o'
+  0x200005E1:  6E           DC.B       0x6E                     ; 'n'
+  0x200005E2:  66           DC.B       0x66                     ; 'f'
+  0x200005E3:  69           DC.B       0x69                     ; 'i'
+  0x200005E4:  67           DC.B       0x67                     ; 'g'
+  0x200005E5:  20           DC.B       0x20                     ; ' '
+  0x200005E6:  76           DC.B       0x76                     ; 'v'
+  0x200005E7:  6F           DC.B       0x6F                     ; 'o'
+  0x200005E8:  72           DC.B       0x72                     ; 'r'
+  0x200005E9:  68           DC.B       0x68                     ; 'h'
+  0x200005EA:  61           DC.B       0x61                     ; 'a'
+  0x200005EB:  6E           DC.B       0x6E                     ; 'n'
+  0x200005EC:  64           DC.B       0x64                     ; 'd'
+  0x200005ED:  65           DC.B       0x65                     ; 'e'
+  0x200005EE:  6E           DC.B       0x6E                     ; 'n'
+  0x200005EF:  0D           DC.B       0x0D                     ; '\r'
+  0x200005F0:  00           DC.B       0x00                     ; '\0'
+  0x200005F1:  4E           DC.B       0x4E                     ; 'N'
+  0x200005F2:  65           DC.B       0x65                     ; 'e'
+  0x200005F3:  75           DC.B       0x75                     ; 'u'
+  0x200005F4:  65           DC.B       0x65                     ; 'e'
+  0x200005F5:  20           DC.B       0x20                     ; ' '
+  0x200005F6:  56           DC.B       0x56                     ; 'V'
+  0x200005F7:  65           DC.B       0x65                     ; 'e'
+  0x200005F8:  72           DC.B       0x72                     ; 'r'
+  0x200005F9:  73           DC.B       0x73                     ; 's'
+  0x200005FA:  69           DC.B       0x69                     ; 'i'
+  0x200005FB:  6F           DC.B       0x6F                     ; 'o'
+  0x200005FC:  6E           DC.B       0x6E                     ; 'n'
+  0x200005FD:  20           DC.B       0x20                     ; ' '
+  0x200005FE:  50           DC.B       0x50                     ; 'P'
+  0x200005FF:  61           DC.B       0x61                     ; 'a'
+  0x20000600:  72           DC.B       0x72                     ; 'r'
+  0x20000601:  61           DC.B       0x61                     ; 'a'
+  0x20000602:  6D           DC.B       0x6D                     ; 'm'
+  0x20000603:  65           DC.B       0x65                     ; 'e'
+  0x20000604:  74           DC.B       0x74                     ; 't'
+  0x20000605:  65           DC.B       0x65                     ; 'e'
+  0x20000606:  72           DC.B       0x72                     ; 'r'
+  0x20000607:  20           DC.B       0x20                     ; ' '
+  0x20000608:  65           DC.B       0x65                     ; 'e'
+  0x20000609:  72           DC.B       0x72                     ; 'r'
+  0x2000060A:  6B           DC.B       0x6B                     ; 'k'
+  0x2000060B:  61           DC.B       0x61                     ; 'a'
+  0x2000060C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000060D:  6E           DC.B       0x6E                     ; 'n'
+  0x2000060E:  74           DC.B       0x74                     ; 't'
+  0x2000060F:  2C           DC.B       0x2C                     ; ','
+  0x20000610:  20           DC.B       0x20                     ; ' '
+  0x20000611:  73           DC.B       0x73                     ; 's'
+  0x20000612:  63           DC.B       0x63                     ; 'c'
+  0x20000613:  68           DC.B       0x68                     ; 'h'
+
+

Section .bss.htim16 from PowerPro_lto.o, size=76, align=4

+
+
htim16:
+  0x20000614:  73           DC.B       0x73                     ; 's'
+  0x20000615:  65           DC.B       0x65                     ; 'e'
+  0x20000616:  74           DC.B       0x74                     ; 't'
+  0x20000617:  7A           DC.B       0x7A                     ; 'z'
+  0x20000618:  65           DC.B       0x65                     ; 'e'
+  0x20000619:  20           DC.B       0x20                     ; ' '
+  0x2000061A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000061B:  70           DC.B       0x70                     ; 'p'
+  0x2000061C:  74           DC.B       0x74                     ; 't'
+  0x2000061D:  69           DC.B       0x69                     ; 'i'
+  0x2000061E:  6F           DC.B       0x6F                     ; 'o'
+  0x2000061F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000620:  20           DC.B       0x20                     ; ' '
+  0x20000621:  62           DC.B       0x62                     ; 'b'
+  0x20000622:  79           DC.B       0x79                     ; 'y'
+  0x20000623:  74           DC.B       0x74                     ; 't'
+  0x20000624:  65           DC.B       0x65                     ; 'e'
+  0x20000625:  0D           DC.B       0x0D                     ; '\r'
+  0x20000626:  00           DC.B       0x00                     ; '\0'
+  0x20000627:  4B           DC.B       0x4B                     ; 'K'
+  0x20000628:  6F           DC.B       0x6F                     ; 'o'
+  0x20000629:  6E           DC.B       0x6E                     ; 'n'
+  0x2000062A:  66           DC.B       0x66                     ; 'f'
+  0x2000062B:  69           DC.B       0x69                     ; 'i'
+  0x2000062C:  67           DC.B       0x67                     ; 'g'
+  0x2000062D:  20           DC.B       0x20                     ; ' '
+  0x2000062E:  76           DC.B       0x76                     ; 'v'
+  0x2000062F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000630:  72           DC.B       0x72                     ; 'r'
+  0x20000631:  68           DC.B       0x68                     ; 'h'
+  0x20000632:  61           DC.B       0x61                     ; 'a'
+  0x20000633:  6E           DC.B       0x6E                     ; 'n'
+  0x20000634:  64           DC.B       0x64                     ; 'd'
+  0x20000635:  65           DC.B       0x65                     ; 'e'
+  0x20000636:  6E           DC.B       0x6E                     ; 'n'
+  0x20000637:  0D           DC.B       0x0D                     ; '\r'
+  0x20000638:  00           DC.B       0x00                     ; '\0'
+  0x20000639:  4E           DC.B       0x4E                     ; 'N'
+  0x2000063A:  65           DC.B       0x65                     ; 'e'
+  0x2000063B:  75           DC.B       0x75                     ; 'u'
+  0x2000063C:  65           DC.B       0x65                     ; 'e'
+  0x2000063D:  20           DC.B       0x20                     ; ' '
+  0x2000063E:  56           DC.B       0x56                     ; 'V'
+  0x2000063F:  65           DC.B       0x65                     ; 'e'
+  0x20000640:  72           DC.B       0x72                     ; 'r'
+  0x20000641:  73           DC.B       0x73                     ; 's'
+  0x20000642:  69           DC.B       0x69                     ; 'i'
+  0x20000643:  6F           DC.B       0x6F                     ; 'o'
+  0x20000644:  6E           DC.B       0x6E                     ; 'n'
+  0x20000645:  20           DC.B       0x20                     ; ' '
+  0x20000646:  50           DC.B       0x50                     ; 'P'
+  0x20000647:  61           DC.B       0x61                     ; 'a'
+  0x20000648:  72           DC.B       0x72                     ; 'r'
+  0x20000649:  61           DC.B       0x61                     ; 'a'
+  0x2000064A:  6D           DC.B       0x6D                     ; 'm'
+  0x2000064B:  65           DC.B       0x65                     ; 'e'
+  0x2000064C:  74           DC.B       0x74                     ; 't'
+  0x2000064D:  65           DC.B       0x65                     ; 'e'
+  0x2000064E:  72           DC.B       0x72                     ; 'r'
+  0x2000064F:  20           DC.B       0x20                     ; ' '
+  0x20000650:  65           DC.B       0x65                     ; 'e'
+  0x20000651:  72           DC.B       0x72                     ; 'r'
+  0x20000652:  6B           DC.B       0x6B                     ; 'k'
+  0x20000653:  61           DC.B       0x61                     ; 'a'
+  0x20000654:  6E           DC.B       0x6E                     ; 'n'
+  0x20000655:  6E           DC.B       0x6E                     ; 'n'
+  0x20000656:  74           DC.B       0x74                     ; 't'
+  0x20000657:  2C           DC.B       0x2C                     ; ','
+  0x20000658:  20           DC.B       0x20                     ; ' '
+  0x20000659:  73           DC.B       0x73                     ; 's'
+  0x2000065A:  63           DC.B       0x63                     ; 'c'
+  0x2000065B:  68           DC.B       0x68                     ; 'h'
+  0x2000065C:  72           DC.B       0x72                     ; 'r'
+  0x2000065D:  65           DC.B       0x65                     ; 'e'
+  0x2000065E:  69           DC.B       0x69                     ; 'i'
+  0x2000065F:  62           DC.B       0x62                     ; 'b'
+
+

Section .bss.adcData from PowerPro_lto.o, size=20, align=4

+
+
adcData:
+  0x20000660:  73           DC.B       0x73                     ; 's'
+  0x20000661:  65           DC.B       0x65                     ; 'e'
+  0x20000662:  74           DC.B       0x74                     ; 't'
+  0x20000663:  7A           DC.B       0x7A                     ; 'z'
+  0x20000664:  65           DC.B       0x65                     ; 'e'
+  0x20000665:  20           DC.B       0x20                     ; ' '
+  0x20000666:  6F           DC.B       0x6F                     ; 'o'
+  0x20000667:  70           DC.B       0x70                     ; 'p'
+  0x20000668:  74           DC.B       0x74                     ; 't'
+  0x20000669:  69           DC.B       0x69                     ; 'i'
+  0x2000066A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000066B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000066C:  20           DC.B       0x20                     ; ' '
+  0x2000066D:  62           DC.B       0x62                     ; 'b'
+  0x2000066E:  79           DC.B       0x79                     ; 'y'
+  0x2000066F:  74           DC.B       0x74                     ; 't'
+  0x20000670:  65           DC.B       0x65                     ; 'e'
+  0x20000671:  0D           DC.B       0x0D                     ; '\r'
+  0x20000672:  00           DC.B       0x00                     ; '\0'
+  0x20000673:  4B           DC.B       0x4B                     ; 'K'
+
+

Section .bss.flash_device_parameter_default from PowerPro_lto.o, size=16, align=4

+
+
flash_device_parameter_default:
+  0x20000674:  00           DC.B       0x00                     ; '\0'
+  0x20000675:  00           DC.B       0x00                     ; '\0'
+  0x20000676:  00           DC.B       0x00                     ; '\0'
+  0x20000677:  00           DC.B       0x00                     ; '\0'
+  0x20000678:  73           DC.B       0x73                     ; 's'
+  0x20000679:  65           DC.B       0x65                     ; 'e'
+  0x2000067A:  74           DC.B       0x74                     ; 't'
+  0x2000067B:  7A           DC.B       0x7A                     ; 'z'
+  0x2000067C:  65           DC.B       0x65                     ; 'e'
+  0x2000067D:  20           DC.B       0x20                     ; ' '
+  0x2000067E:  6F           DC.B       0x6F                     ; 'o'
+  0x2000067F:  70           DC.B       0x70                     ; 'p'
+  0x20000680:  74           DC.B       0x74                     ; 't'
+  0x20000681:  69           DC.B       0x69                     ; 'i'
+  0x20000682:  6F           DC.B       0x6F                     ; 'o'
+  0x20000683:  6E           DC.B       0x6E                     ; 'n'
+
+

Section .bss.voltageUout from PowerPro_lto.o, size=4, align=4

+
+
voltageUout:
+  0x20000684:  76           DC.B       0x76                     ; 'v'
+  0x20000685:  6F           DC.B       0x6F                     ; 'o'
+  0x20000686:  6C           DC.B       0x6C                     ; 'l'
+  0x20000687:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.voltageUin from PowerPro_lto.o, size=4, align=4

+
+
voltageUin:
+  0x20000688:  76           DC.B       0x76                     ; 'v'
+  0x20000689:  6F           DC.B       0x6F                     ; 'o'
+  0x2000068A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000068B:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.uwTick from PowerPro_lto.o, size=4, align=4

+
+
uwTick:
+  0x2000068C:  00           DC.B       0x00                     ; '\0'
+  0x2000068D:  1B           DC.B       0x1B                     ; '\x1B'
+  0x2000068E:  B7           DC.B       0xB7                     ; '\xB7'
+  0x2000068F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.temp from PowerPro_lto.o, size=4, align=4

+
+
temp:
+  0x20000690:  00           DC.B       0x00                     ; '\0'
+  0x20000691:  00           DC.B       0x00                     ; '\0'
+  0x20000692:  00           DC.B       0x00                     ; '\0'
+  0x20000693:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.relais_temperature from PowerPro_lto.o, size=4, align=4

+
+
relais_temperature:
+  0x20000694:  76           DC.B       0x76                     ; 'v'
+  0x20000695:  6F           DC.B       0x6F                     ; 'o'
+  0x20000696:  6C           DC.B       0x6C                     ; 'l'
+  0x20000697:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterSET from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterSET:
+  0x20000698:  76           DC.B       0x76                     ; 'v'
+  0x20000699:  6F           DC.B       0x6F                     ; 'o'
+  0x2000069A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000069B:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterRT from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterRT:
+  0x2000069C:  00           DC.B       0x00                     ; '\0'
+  0x2000069D:  00           DC.B       0x00                     ; '\0'
+  0x2000069E:  00           DC.B       0x00                     ; '\0'
+  0x2000069F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeCounterRESET from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterRESET:
+  0x200006A0:  76           DC.B       0x76                     ; 'v'
+  0x200006A1:  6F           DC.B       0x6F                     ; 'o'
+  0x200006A2:  6C           DC.B       0x6C                     ; 'l'
+  0x200006A3:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterGN from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterGN:
+  0x200006A4:  00           DC.B       0x00                     ; '\0'
+  0x200006A5:  00           DC.B       0x00                     ; '\0'
+  0x200006A6:  00           DC.B       0x00                     ; '\0'
+  0x200006A7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounter:
+  0x200006A8:  00           DC.B       0x00                     ; '\0'
+  0x200006A9:  00           DC.B       0x00                     ; '\0'
+  0x200006AA:  00           DC.B       0x00                     ; '\0'
+  0x200006AB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.oldTimeMSTick from PowerPro_lto.o, size=4, align=4

+
+
oldTimeMSTick:
+  0x200006AC:  73           DC.B       0x73                     ; 's'
+  0x200006AD:  65           DC.B       0x65                     ; 'e'
+  0x200006AE:  74           DC.B       0x74                     ; 't'
+  0x200006AF:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.offTimeCounterRT from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounterRT:
+  0x200006B0:  00           DC.B       0x00                     ; '\0'
+  0x200006B1:  00           DC.B       0x00                     ; '\0'
+  0x200006B2:  00           DC.B       0x00                     ; '\0'
+  0x200006B3:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeCounterGN from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounterGN:
+  0x200006B4:  00           DC.B       0x00                     ; '\0'
+  0x200006B5:  00           DC.B       0x00                     ; '\0'
+  0x200006B6:  00           DC.B       0x00                     ; '\0'
+  0x200006B7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounter:
+  0x200006B8:  00           DC.B       0x00                     ; '\0'
+  0x200006B9:  00           DC.B       0x00                     ; '\0'
+  0x200006BA:  00           DC.B       0x00                     ; '\0'
+  0x200006BB:  00           DC.B       0x00                     ; '\0'
+
+ +
+
numberOfBlinks:
+  0x200006BC:  00           DC.B       0x00                     ; '\0'
+  0x200006BD:  00           DC.B       0x00                     ; '\0'
+  0x200006BE:  00           DC.B       0x00                     ; '\0'
+  0x200006BF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.msCounter from PowerPro_lto.o, size=4, align=4

+
+
msCounter:
+  0x200006C0:  73           DC.B       0x73                     ; 's'
+  0x200006C1:  65           DC.B       0x65                     ; 'e'
+  0x200006C2:  74           DC.B       0x74                     ; 't'
+  0x200006C3:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.longPressCounterButtonOn from PowerPro_lto.o, size=4, align=4

+
+
longPressCounterButtonOn:
+  0x200006C4:  42           DC.B       0x42                     ; 'B'
+  0x200006C5:  55           DC.B       0x55                     ; 'U'
+  0x200006C6:  54           DC.B       0x54                     ; 'T'
+  0x200006C7:  54           DC.B       0x54                     ; 'T'
+
+

Section .bss.longPressCounterButtonOff from PowerPro_lto.o, size=4, align=4

+
+
longPressCounterButtonOff:
+  0x200006C8:  42           DC.B       0x42                     ; 'B'
+  0x200006C9:  55           DC.B       0x55                     ; 'U'
+  0x200006CA:  54           DC.B       0x54                     ; 'T'
+  0x200006CB:  54           DC.B       0x54                     ; 'T'
+
+

Section .bss.libc.__SEGGER_RTL_stdout_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stdout_file:
+  0x200006CC:  00           DC.B       0x00                     ; '\0'
+  0x200006CD:  00           DC.B       0x00                     ; '\0'
+  0x200006CE:  00           DC.B       0x00                     ; '\0'
+  0x200006CF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_stdin_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stdin_file:
+  0x200006D0:  00           DC.B       0x00                     ; '\0'
+  0x200006D1:  00           DC.B       0x00                     ; '\0'
+  0x200006D2:  00           DC.B       0x00                     ; '\0'
+  0x200006D3:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_stderr_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stderr_file:
+  0x200006D4:  00           DC.B       0x00                     ; '\0'
+  0x200006D5:  00           DC.B       0x00                     ; '\0'
+  0x200006D6:  00           DC.B       0x00                     ; '\0'
+  0x200006D7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_locale_ptr from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_locale_ptr:
+  0x200006D8:  43           DC.B       0x43                     ; 'C'
+  0x200006D9:  00           DC.B       0x00                     ; '\0'
+  0x200006DA:  50           DC.B       0x50                     ; 'P'
+  0x200006DB:  4F           DC.B       0x4F                     ; 'O'
+
+

Section .bss.ic_overflows from PowerPro_lto.o, size=4, align=4

+
+
ic_overflows:
+  0x200006DC:  73           DC.B       0x73                     ; 's'
+  0x200006DD:  65           DC.B       0x65                     ; 'e'
+  0x200006DE:  74           DC.B       0x74                     ; 't'
+  0x200006DF:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.frequency from PowerPro_lto.o, size=4, align=4

+
+
frequency:
+  0x200006E0:  73           DC.B       0x73                     ; 's'
+  0x200006E1:  65           DC.B       0x65                     ; 'e'
+  0x200006E2:  74           DC.B       0x74                     ; 't'
+  0x200006E3:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.dropLimitCounter from PowerPro_lto.o, size=4, align=4

+
+
dropLimitCounter:
+  0x200006E4:  76           DC.B       0x76                     ; 'v'
+  0x200006E5:  6F           DC.B       0x6F                     ; 'o'
+  0x200006E6:  6C           DC.B       0x6C                     ; 'l'
+  0x200006E7:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.calTemperatureSensor30Value from PowerPro_lto.o, size=4, align=4

+
+
calTemperatureSensor30Value:
+  0x200006E8:  00           DC.B       0x00                     ; '\0'
+  0x200006E9:  00           DC.B       0x00                     ; '\0'
+  0x200006EA:  00           DC.B       0x00                     ; '\0'
+  0x200006EB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkCounter from PowerPro_lto.o, size=4, align=4

+
+
blinkCounter:
+  0x200006EC:  00           DC.B       0x00                     ; '\0'
+  0x200006ED:  00           DC.B       0x00                     ; '\0'
+  0x200006EE:  00           DC.B       0x00                     ; '\0'
+  0x200006EF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.autoRetryMode.170 from PowerPro_lto.o, size=4, align=4

+
+
autoRetryMode.170:
+  0x200006F0:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F1:  45           DC.B       0x45                     ; 'E'
+  0x200006F2:  57           DC.B       0x57                     ; 'W'
+  0x200006F3:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.autoRetryMode from PowerPro_lto.o, size=4, align=4

+
+
autoRetryMode:
+  0x200006F4:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F5:  45           DC.B       0x45                     ; 'E'
+  0x200006F6:  57           DC.B       0x57                     ; 'W'
+  0x200006F7:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.oldtime.175 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.oldtime.175:
+  0x200006F8:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F9:  45           DC.B       0x45                     ; 'E'
+  0x200006FA:  57           DC.B       0x57                     ; 'W'
+  0x200006FB:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.oldtime:
+  0x200006FC:  4E           DC.B       0x4E                     ; 'N'
+  0x200006FD:  45           DC.B       0x45                     ; 'E'
+  0x200006FE:  57           DC.B       0x57                     ; 'W'
+  0x200006FF:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176:
+  0x20000700:  4E           DC.B       0x4E                     ; 'N'
+  0x20000701:  45           DC.B       0x45                     ; 'E'
+  0x20000702:  57           DC.B       0x57                     ; 'W'
+  0x20000703:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter:
+  0x20000704:  4E           DC.B       0x4E                     ; 'N'
+  0x20000705:  45           DC.B       0x45                     ; 'E'
+  0x20000706:  57           DC.B       0x57                     ; 'W'
+  0x20000707:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.retry_counter.181 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.retry_counter.181:
+  0x20000708:  4E           DC.B       0x4E                     ; 'N'
+  0x20000709:  45           DC.B       0x45                     ; 'E'
+  0x2000070A:  57           DC.B       0x57                     ; 'W'
+  0x2000070B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.retry_counter from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.retry_counter:
+  0x2000070C:  4E           DC.B       0x4E                     ; 'N'
+  0x2000070D:  45           DC.B       0x45                     ; 'E'
+  0x2000070E:  57           DC.B       0x57                     ; 'W'
+  0x2000070F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182:
+  0x20000710:  4E           DC.B       0x4E                     ; 'N'
+  0x20000711:  45           DC.B       0x45                     ; 'E'
+  0x20000712:  57           DC.B       0x57                     ; 'W'
+  0x20000713:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.oldTimeMSTick from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.oldTimeMSTick:
+  0x20000714:  4E           DC.B       0x4E                     ; 'N'
+  0x20000715:  45           DC.B       0x45                     ; 'E'
+  0x20000716:  57           DC.B       0x57                     ; 'W'
+  0x20000717:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.OVP_SM_On.ovpTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
OVP_SM_On.ovpTimeCounter:
+  0x20000718:  4F           DC.B       0x4F                     ; 'O'
+  0x20000719:  56           DC.B       0x56                     ; 'V'
+  0x2000071A:  50           DC.B       0x50                     ; 'P'
+  0x2000071B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.OVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
OVP_SM_On.oldtime:
+  0x2000071C:  4F           DC.B       0x4F                     ; 'O'
+  0x2000071D:  56           DC.B       0x56                     ; 'V'
+  0x2000071E:  50           DC.B       0x50                     ; 'P'
+  0x2000071F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
LVP_SM_On.oldtime:
+  0x20000720:  4C           DC.B       0x4C                     ; 'L'
+  0x20000721:  56           DC.B       0x56                     ; 'V'
+  0x20000722:  50           DC.B       0x50                     ; 'P'
+  0x20000723:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_SM_On.lvpTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
LVP_SM_On.lvpTimeCounter:
+  0x20000724:  4C           DC.B       0x4C                     ; 'L'
+  0x20000725:  56           DC.B       0x56                     ; 'V'
+  0x20000726:  50           DC.B       0x50                     ; 'P'
+  0x20000727:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_OVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
LVP_OVP_SM_On.oldtime:
+  0x20000728:  4C           DC.B       0x4C                     ; 'L'
+  0x20000729:  56           DC.B       0x56                     ; 'V'
+  0x2000072A:  50           DC.B       0x50                     ; 'P'
+  0x2000072B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_OVP_SM_On.lvpAndOvpInputTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter:
+  0x2000072C:  4C           DC.B       0x4C                     ; 'L'
+  0x2000072D:  56           DC.B       0x56                     ; 'V'
+  0x2000072E:  50           DC.B       0x50                     ; 'P'
+  0x2000072F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.relaisState from PowerPro_lto.o, size=1, align=4

+
+
relaisState:
+  0x20000730:  76           DC.B       0x76                     ; 'v'
+
+

Section .bss.smState.171 from PowerPro_lto.o, size=1, align=1

+
+
smState.171:
+  0x20000731:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.160 from PowerPro_lto.o, size=1, align=1

+
+
smState.160:
+  0x20000732:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.145 from PowerPro_lto.o, size=1, align=1

+
+
smState.145:
+  0x20000733:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.pauseTime from PowerPro_lto.o, size=1, align=4

+
+
pauseTime:
+  0x20000734:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.smState.137 from PowerPro_lto.o, size=1, align=1

+
+
smState.137:
+  0x20000735:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.122 from PowerPro_lto.o, size=1, align=1

+
+
smState.122:
+  0x20000736:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.smState from PowerPro_lto.o, size=1, align=1

+
+
smState:
+  0x20000737:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.pFlash.0 from PowerPro_lto.o, size=1, align=4

+
+
pFlash.0:
+  0x20000738:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.mode from PowerPro_lto.o, size=1, align=1

+
+
mode:
+  0x20000739:  6D           DC.B       0x6D                     ; 'm'
+
+

Section .bss.buttonState from PowerPro_lto.o, size=1, align=1

+
+
buttonState:
+  0x2000073A:  42           DC.B       0x42                     ; 'B'
+
+

Section .bss.onTimeRT from PowerPro_lto.o, size=1, align=4

+
+
onTimeRT:
+  0x2000073C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeGN from PowerPro_lto.o, size=1, align=4

+
+
onTimeGN:
+  0x20000740:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTime from PowerPro_lto.o, size=1, align=4

+
+
onTime:
+  0x20000744:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeRT from PowerPro_lto.o, size=1, align=4

+
+
offTimeRT:
+  0x20000748:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeGN from PowerPro_lto.o, size=1, align=4

+
+
offTimeGN:
+  0x2000074C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTime from PowerPro_lto.o, size=1, align=4

+
+
offTime:
+  0x20000750:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkModeRT from PowerPro_lto.o, size=1, align=4

+
+
blinkModeRT:
+  0x20000754:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkModeGN from PowerPro_lto.o, size=1, align=4

+
+
blinkModeGN:
+  0x20000758:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.alarmMode from PowerPro_lto.o, size=1, align=4

+
+
alarmMode:
+  0x2000075C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.OVP_SM_On.ovpInput from PowerPro_lto.o, size=1, align=4

+
+
OVP_SM_On.ovpInput:
+  0x20000760:  4F           DC.B       0x4F                     ; 'O'
+
+

Section .bss.LVP_SM_On.lvpInput from PowerPro_lto.o, size=1, align=4

+
+
LVP_SM_On.lvpInput:
+  0x20000764:  4C           DC.B       0x4C                     ; 'L'
+
+

Section .bss.LVP_OVP_SM_On.lvpOROvpInput from PowerPro_lto.o, size=1, align=4

+
+
LVP_OVP_SM_On.lvpOROvpInput:
+  0x20000768:  4C           DC.B       0x4C                     ; 'L'
+
+

Section .bss.libc._acUpBuffer from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=1024, align=1

+
+
_acUpBuffer:
+  0x20000769:  00           DC.B       0x00                     ; '\0'
+  0x2000076A:  53           DC.B       0x53                     ; 'S'
+  0x2000076B:  45           DC.B       0x45                     ; 'E'
+  0x2000076C:  47           DC.B       0x47                     ; 'G'
+  0x2000076D:  47           DC.B       0x47                     ; 'G'
+  0x2000076E:  45           DC.B       0x45                     ; 'E'
+  0x2000076F:  52           DC.B       0x52                     ; 'R'
+  0x20000770:  20           DC.B       0x20                     ; ' '
+  0x20000771:  43           DC.B       0x43                     ; 'C'
+  0x20000772:  2F           DC.B       0x2F                     ; '/'
+  0x20000773:  43           DC.B       0x43                     ; 'C'
+  0x20000774:  2B           DC.B       0x2B                     ; '+'
+  0x20000775:  2B           DC.B       0x2B                     ; '+'
+  0x20000776:  20           DC.B       0x20                     ; ' '
+  0x20000777:  63           DC.B       0x63                     ; 'c'
+  0x20000778:  6F           DC.B       0x6F                     ; 'o'
+  0x20000779:  6D           DC.B       0x6D                     ; 'm'
+  0x2000077A:  70           DC.B       0x70                     ; 'p'
+  0x2000077B:  69           DC.B       0x69                     ; 'i'
+  0x2000077C:  6C           DC.B       0x6C                     ; 'l'
+  0x2000077D:  65           DC.B       0x65                     ; 'e'
+  0x2000077E:  72           DC.B       0x72                     ; 'r'
+  0x2000077F:  20           DC.B       0x20                     ; ' '
+  0x20000780:  76           DC.B       0x76                     ; 'v'
+  0x20000781:  65           DC.B       0x65                     ; 'e'
+  0x20000782:  72           DC.B       0x72                     ; 'r'
+  0x20000783:  73           DC.B       0x73                     ; 's'
+  0x20000784:  69           DC.B       0x69                     ; 'i'
+  0x20000785:  6F           DC.B       0x6F                     ; 'o'
+  0x20000786:  6E           DC.B       0x6E                     ; 'n'
+  0x20000787:  20           DC.B       0x20                     ; ' '
+  0x20000788:  32           DC.B       0x32                     ; '2'
+  0x20000789:  30           DC.B       0x30                     ; '0'
+  0x2000078A:  2E           DC.B       0x2E                     ; '.'
+  0x2000078B:  31           DC.B       0x31                     ; '1'
+  0x2000078C:  2E           DC.B       0x2E                     ; '.'
+  0x2000078D:  32           DC.B       0x32                     ; '2'
+  0x2000078E:  20           DC.B       0x20                     ; ' '
+  0x2000078F:  28           DC.B       0x28                     ; '('
+  0x20000790:  62           DC.B       0x62                     ; 'b'
+  0x20000791:  61           DC.B       0x61                     ; 'a'
+  0x20000792:  73           DC.B       0x73                     ; 's'
+  0x20000793:  65           DC.B       0x65                     ; 'e'
+  0x20000794:  64           DC.B       0x64                     ; 'd'
+  0x20000795:  20           DC.B       0x20                     ; ' '
+  0x20000796:  6F           DC.B       0x6F                     ; 'o'
+  0x20000797:  6E           DC.B       0x6E                     ; 'n'
+  0x20000798:  20           DC.B       0x20                     ; ' '
+  0x20000799:  63           DC.B       0x63                     ; 'c'
+  0x2000079A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000079B:  61           DC.B       0x61                     ; 'a'
+  0x2000079C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000079D:  67           DC.B       0x67                     ; 'g'
+  0x2000079E:  20           DC.B       0x20                     ; ' '
+  0x2000079F:  32           DC.B       0x32                     ; '2'
+  0x200007A0:  30           DC.B       0x30                     ; '0'
+  0x200007A1:  2E           DC.B       0x2E                     ; '.'
+  0x200007A2:  31           DC.B       0x31                     ; '1'
+  0x200007A3:  2E           DC.B       0x2E                     ; '.'
+  0x200007A4:  38           DC.B       0x38                     ; '8'
+  0x200007A5:  29           DC.B       0x29                     ; ')'
+  0x200007A6:  00           DC.B       0x00                     ; '\0'
+  0x200007A7:  41           DC.B       0x41                     ; 'A'
+  0x200007A8:  35           DC.B       0x35                     ; '5'
+  0x200007A9:  00           DC.B       0x00                     ; '\0'
+  0x200007AA:  00           DC.B       0x00                     ; '\0'
+  0x200007AB:  00           DC.B       0x00                     ; '\0'
+  0x200007AC:  61           DC.B       0x61                     ; 'a'
+  0x200007AD:  65           DC.B       0x65                     ; 'e'
+  0x200007AE:  61           DC.B       0x61                     ; 'a'
+  0x200007AF:  62           DC.B       0x62                     ; 'b'
+  0x200007B0:  69           DC.B       0x69                     ; 'i'
+  0x200007B1:  00           DC.B       0x00                     ; '\0'
+  0x200007B2:  01           DC.B       0x01                     ; '\x01'
+  0x200007B3:  2B           DC.B       0x2B                     ; '+'
+  0x200007B4:  00           DC.B       0x00                     ; '\0'
+  0x200007B5:  00           DC.B       0x00                     ; '\0'
+  0x200007B6:  00           DC.B       0x00                     ; '\0'
+  0x200007B7:  43           DC.B       0x43                     ; 'C'
+  0x200007B8:  32           DC.B       0x32                     ; '2'
+  0x200007B9:  2E           DC.B       0x2E                     ; '.'
+  0x200007BA:  30           DC.B       0x30                     ; '0'
+  0x200007BB:  39           DC.B       0x39                     ; '9'
+  0x200007BC:  00           DC.B       0x00                     ; '\0'
+  0x200007BD:  06           DC.B       0x06                     ; '\x06'
+  0x200007BE:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200007BF:  07           DC.B       0x07                     ; '\x07'
+  0x200007C0:  4D           DC.B       0x4D                     ; 'M'
+  0x200007C1:  08           DC.B       0x08                     ; '\b'
+  0x200007C2:  00           DC.B       0x00                     ; '\0'
+  0x200007C3:  09           DC.B       0x09                     ; '\t'
+  0x200007C4:  01           DC.B       0x01                     ; '\x01'
+  0x200007C5:  0E           DC.B       0x0E                     ; '\x0E'
+  0x200007C6:  00           DC.B       0x00                     ; '\0'
+  0x200007C7:  11           DC.B       0x11                     ; '\x11'
+  0x200007C8:  01           DC.B       0x01                     ; '\x01'
+  0x200007C9:  12           DC.B       0x12                     ; '\x12'
+  0x200007CA:  04           DC.B       0x04                     ; '\x04'
+  0x200007CB:  14           DC.B       0x14                     ; '\x14'
+  0x200007CC:  01           DC.B       0x01                     ; '\x01'
+  0x200007CD:  15           DC.B       0x15                     ; '\x15'
+  0x200007CE:  00           DC.B       0x00                     ; '\0'
+  0x200007CF:  17           DC.B       0x17                     ; '\x17'
+  0x200007D0:  03           DC.B       0x03                     ; '\x03'
+  0x200007D1:  18           DC.B       0x18                     ; '\x18'
+  0x200007D2:  01           DC.B       0x01                     ; '\x01'
+  0x200007D3:  19           DC.B       0x19                     ; '\x19'
+  0x200007D4:  01           DC.B       0x01                     ; '\x01'
+  0x200007D5:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200007D6:  01           DC.B       0x01                     ; '\x01'
+  0x200007D7:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200007D8:  04           DC.B       0x04                     ; '\x04'
+  0x200007D9:  22           DC.B       0x22                     ; '\"'
+  0x200007DA:  00           DC.B       0x00                     ; '\0'
+  0x200007DB:  26           DC.B       0x26                     ; '&'
+  0x200007DC:  01           DC.B       0x01                     ; '\x01'
+  0x200007DD:  00           DC.B       0x00                     ; '\0'
+  0x200007DE:  00           DC.B       0x00                     ; '\0'
+  0x200007DF:  00           DC.B       0x00                     ; '\0'
+  0x200007E0:  00           DC.B       0x00                     ; '\0'
+  0x200007E1:  00           DC.B       0x00                     ; '\0'
+  0x200007E2:  00           DC.B       0x00                     ; '\0'
+  0x200007E3:  00           DC.B       0x00                     ; '\0'
+  0x200007E4:  00           DC.B       0x00                     ; '\0'
+  0x200007E5:  00           DC.B       0x00                     ; '\0'
+  0x200007E6:  00           DC.B       0x00                     ; '\0'
+  0x200007E7:  00           DC.B       0x00                     ; '\0'
+  0x200007E8:  00           DC.B       0x00                     ; '\0'
+  0x200007E9:  00           DC.B       0x00                     ; '\0'
+  0x200007EA:  00           DC.B       0x00                     ; '\0'
+  0x200007EB:  00           DC.B       0x00                     ; '\0'
+  0x200007EC:  00           DC.B       0x00                     ; '\0'
+  0x200007ED:  00           DC.B       0x00                     ; '\0'
+  0x200007EE:  00           DC.B       0x00                     ; '\0'
+  0x200007EF:  40           DC.B       0x40                     ; '@'
+  0x200007F0:  06           DC.B       0x06                     ; '\x06'
+  0x200007F1:  00           DC.B       0x00                     ; '\0'
+  0x200007F2:  00           DC.B       0x00                     ; '\0'
+  0x200007F3:  00           DC.B       0x00                     ; '\0'
+  0x200007F4:  00           DC.B       0x00                     ; '\0'
+  0x200007F5:  00           DC.B       0x00                     ; '\0'
+  0x200007F6:  00           DC.B       0x00                     ; '\0'
+  0x200007F7:  00           DC.B       0x00                     ; '\0'
+  0x200007F8:  00           DC.B       0x00                     ; '\0'
+  0x200007F9:  00           DC.B       0x00                     ; '\0'
+  0x200007FA:  00           DC.B       0x00                     ; '\0'
+  0x200007FB:  04           DC.B       0x04                     ; '\x04'
+  0x200007FC:  00           DC.B       0x00                     ; '\0'
+  0x200007FD:  F1           DC.B       0xF1                     ; '\xF1'
+  0x200007FE:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200007FF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000800:  00           DC.B       0x00                     ; '\0'
+  0x20000801:  00           DC.B       0x00                     ; '\0'
+  0x20000802:  00           DC.B       0x00                     ; '\0'
+  0x20000803:  00           DC.B       0x00                     ; '\0'
+  0x20000804:  00           DC.B       0x00                     ; '\0'
+  0x20000805:  00           DC.B       0x00                     ; '\0'
+  0x20000806:  00           DC.B       0x00                     ; '\0'
+  0x20000807:  00           DC.B       0x00                     ; '\0'
+  0x20000808:  00           DC.B       0x00                     ; '\0'
+  0x20000809:  00           DC.B       0x00                     ; '\0'
+  0x2000080A:  00           DC.B       0x00                     ; '\0'
+  0x2000080B:  00           DC.B       0x00                     ; '\0'
+  0x2000080C:  00           DC.B       0x00                     ; '\0'
+  0x2000080D:  03           DC.B       0x03                     ; '\x03'
+  0x2000080E:  00           DC.B       0x00                     ; '\0'
+  0x2000080F:  AA           DC.B       0xAA                     ; '\xAA'
+  0x20000810:  00           DC.B       0x00                     ; '\0'
+  0x20000811:  00           DC.B       0x00                     ; '\0'
+  0x20000812:  00           DC.B       0x00                     ; '\0'
+  0x20000813:  01           DC.B       0x01                     ; '\x01'
+  0x20000814:  00           DC.B       0x00                     ; '\0'
+  0x20000815:  00           DC.B       0x00                     ; '\0'
+  0x20000816:  00           DC.B       0x00                     ; '\0'
+  0x20000817:  54           DC.B       0x54                     ; 'T'
+  0x20000818:  00           DC.B       0x00                     ; '\0'
+  0x20000819:  00           DC.B       0x00                     ; '\0'
+  0x2000081A:  00           DC.B       0x00                     ; '\0'
+  0x2000081B:  02           DC.B       0x02                     ; '\x02'
+  0x2000081C:  00           DC.B       0x00                     ; '\0'
+  0x2000081D:  05           DC.B       0x05                     ; '\x05'
+  0x2000081E:  00           DC.B       0x00                     ; '\0'
+  0x2000081F:  32           DC.B       0x32                     ; '2'
+  0x20000820:  06           DC.B       0x06                     ; '\x06'
+  0x20000821:  00           DC.B       0x00                     ; '\0'
+  0x20000822:  00           DC.B       0x00                     ; '\0'
+  0x20000823:  84           DC.B       0x84                     ; '\x84'
+  0x20000824:  00           DC.B       0x00                     ; '\0'
+  0x20000825:  00           DC.B       0x00                     ; '\0'
+  0x20000826:  00           DC.B       0x00                     ; '\0'
+  0x20000827:  00           DC.B       0x00                     ; '\0'
+  0x20000828:  00           DC.B       0x00                     ; '\0'
+  0x20000829:  00           DC.B       0x00                     ; '\0'
+  0x2000082A:  00           DC.B       0x00                     ; '\0'
+  0x2000082B:  00           DC.B       0x00                     ; '\0'
+  0x2000082C:  00           DC.B       0x00                     ; '\0'
+  0x2000082D:  03           DC.B       0x03                     ; '\x03'
+  0x2000082E:  00           DC.B       0x00                     ; '\0'
+  0x2000082F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000830:  00           DC.B       0x00                     ; '\0'
+  0x20000831:  00           DC.B       0x00                     ; '\0'
+  0x20000832:  00           DC.B       0x00                     ; '\0'
+  0x20000833:  00           DC.B       0x00                     ; '\0'
+  0x20000834:  00           DC.B       0x00                     ; '\0'
+  0x20000835:  00           DC.B       0x00                     ; '\0'
+  0x20000836:  00           DC.B       0x00                     ; '\0'
+  0x20000837:  00           DC.B       0x00                     ; '\0'
+  0x20000838:  00           DC.B       0x00                     ; '\0'
+  0x20000839:  00           DC.B       0x00                     ; '\0'
+  0x2000083A:  00           DC.B       0x00                     ; '\0'
+  0x2000083B:  00           DC.B       0x00                     ; '\0'
+  0x2000083C:  00           DC.B       0x00                     ; '\0'
+  0x2000083D:  05           DC.B       0x05                     ; '\x05'
+  0x2000083E:  00           DC.B       0x00                     ; '\0'
+  0x2000083F:  32           DC.B       0x32                     ; '2'
+  0x20000840:  06           DC.B       0x06                     ; '\x06'
+  0x20000841:  00           DC.B       0x00                     ; '\0'
+  0x20000842:  00           DC.B       0x00                     ; '\0'
+  0x20000843:  40           DC.B       0x40                     ; '@'
+  0x20000844:  00           DC.B       0x00                     ; '\0'
+  0x20000845:  00           DC.B       0x00                     ; '\0'
+  0x20000846:  00           DC.B       0x00                     ; '\0'
+  0x20000847:  00           DC.B       0x00                     ; '\0'
+  0x20000848:  00           DC.B       0x00                     ; '\0'
+  0x20000849:  00           DC.B       0x00                     ; '\0'
+  0x2000084A:  00           DC.B       0x00                     ; '\0'
+  0x2000084B:  00           DC.B       0x00                     ; '\0'
+  0x2000084C:  00           DC.B       0x00                     ; '\0'
+  0x2000084D:  05           DC.B       0x05                     ; '\x05'
+  0x2000084E:  00           DC.B       0x00                     ; '\0'
+  0x2000084F:  EE           DC.B       0xEE                     ; '\xEE'
+  0x20000850:  01           DC.B       0x01                     ; '\x01'
+  0x20000851:  00           DC.B       0x00                     ; '\0'
+  0x20000852:  00           DC.B       0x00                     ; '\0'
+  0x20000853:  00           DC.B       0x00                     ; '\0'
+  0x20000854:  00           DC.B       0x00                     ; '\0'
+  0x20000855:  00           DC.B       0x00                     ; '\0'
+  0x20000856:  00           DC.B       0x00                     ; '\0'
+  0x20000857:  00           DC.B       0x00                     ; '\0'
+  0x20000858:  04           DC.B       0x04                     ; '\x04'
+  0x20000859:  00           DC.B       0x00                     ; '\0'
+  0x2000085A:  00           DC.B       0x00                     ; '\0'
+  0x2000085B:  01           DC.B       0x01                     ; '\x01'
+  0x2000085C:  00           DC.B       0x00                     ; '\0'
+  0x2000085D:  51           DC.B       0x51                     ; 'Q'
+  0x2000085E:  00           DC.B       0x00                     ; '\0'
+  0x2000085F:  DC           DC.B       0xDC                     ; '\xDC'
+  0x20000860:  02           DC.B       0x02                     ; '\x02'
+  0x20000861:  00           DC.B       0x00                     ; '\0'
+  0x20000862:  00           DC.B       0x00                     ; '\0'
+  0x20000863:  00           DC.B       0x00                     ; '\0'
+  0x20000864:  00           DC.B       0x00                     ; '\0'
+  0x20000865:  00           DC.B       0x00                     ; '\0'
+  0x20000866:  00           DC.B       0x00                     ; '\0'
+  0x20000867:  10           DC.B       0x10                     ; '\x10'
+  0x20000868:  00           DC.B       0x00                     ; '\0'
+  0x20000869:  00           DC.B       0x00                     ; '\0'
+  0x2000086A:  00           DC.B       0x00                     ; '\0'
+  0x2000086B:  01           DC.B       0x01                     ; '\x01'
+  0x2000086C:  00           DC.B       0x00                     ; '\0'
+  0x2000086D:  52           DC.B       0x52                     ; 'R'
+  0x2000086E:  00           DC.B       0x00                     ; '\0'
+  0x2000086F:  05           DC.B       0x05                     ; '\x05'
+  0x20000870:  01           DC.B       0x01                     ; '\x01'
+  0x20000871:  00           DC.B       0x00                     ; '\0'
+  0x20000872:  00           DC.B       0x00                     ; '\0'
+  0x20000873:  00           DC.B       0x00                     ; '\0'
+  0x20000874:  00           DC.B       0x00                     ; '\0'
+  0x20000875:  00           DC.B       0x00                     ; '\0'
+  0x20000876:  00           DC.B       0x00                     ; '\0'
+  0x20000877:  11           DC.B       0x11                     ; '\x11'
+  0x20000878:  00           DC.B       0x00                     ; '\0'
+  0x20000879:  00           DC.B       0x00                     ; '\0'
+  0x2000087A:  00           DC.B       0x00                     ; '\0'
+  0x2000087B:  01           DC.B       0x01                     ; '\x01'
+  0x2000087C:  00           DC.B       0x00                     ; '\0'
+  0x2000087D:  4F           DC.B       0x4F                     ; 'O'
+  0x2000087E:  00           DC.B       0x00                     ; '\0'
+  0x2000087F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000880:  00           DC.B       0x00                     ; '\0'
+  0x20000881:  00           DC.B       0x00                     ; '\0'
+  0x20000882:  00           DC.B       0x00                     ; '\0'
+  0x20000883:  00           DC.B       0x00                     ; '\0'
+  0x20000884:  00           DC.B       0x00                     ; '\0'
+  0x20000885:  00           DC.B       0x00                     ; '\0'
+  0x20000886:  00           DC.B       0x00                     ; '\0'
+  0x20000887:  00           DC.B       0x00                     ; '\0'
+  0x20000888:  00           DC.B       0x00                     ; '\0'
+  0x20000889:  00           DC.B       0x00                     ; '\0'
+  0x2000088A:  00           DC.B       0x00                     ; '\0'
+  0x2000088B:  00           DC.B       0x00                     ; '\0'
+  0x2000088C:  00           DC.B       0x00                     ; '\0'
+  0x2000088D:  07           DC.B       0x07                     ; '\x07'
+  0x2000088E:  00           DC.B       0x00                     ; '\0'
+  0x2000088F:  32           DC.B       0x32                     ; '2'
+  0x20000890:  06           DC.B       0x06                     ; '\x06'
+  0x20000891:  00           DC.B       0x00                     ; '\0'
+  0x20000892:  00           DC.B       0x00                     ; '\0'
+  0x20000893:  84           DC.B       0x84                     ; '\x84'
+  0x20000894:  00           DC.B       0x00                     ; '\0'
+  0x20000895:  00           DC.B       0x00                     ; '\0'
+  0x20000896:  00           DC.B       0x00                     ; '\0'
+  0x20000897:  00           DC.B       0x00                     ; '\0'
+  0x20000898:  00           DC.B       0x00                     ; '\0'
+  0x20000899:  00           DC.B       0x00                     ; '\0'
+  0x2000089A:  00           DC.B       0x00                     ; '\0'
+  0x2000089B:  00           DC.B       0x00                     ; '\0'
+  0x2000089C:  00           DC.B       0x00                     ; '\0'
+  0x2000089D:  07           DC.B       0x07                     ; '\x07'
+  0x2000089E:  00           DC.B       0x00                     ; '\0'
+  0x2000089F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008A0:  00           DC.B       0x00                     ; '\0'
+  0x200008A1:  00           DC.B       0x00                     ; '\0'
+  0x200008A2:  00           DC.B       0x00                     ; '\0'
+  0x200008A3:  00           DC.B       0x00                     ; '\0'
+  0x200008A4:  00           DC.B       0x00                     ; '\0'
+  0x200008A5:  00           DC.B       0x00                     ; '\0'
+  0x200008A6:  00           DC.B       0x00                     ; '\0'
+  0x200008A7:  00           DC.B       0x00                     ; '\0'
+  0x200008A8:  00           DC.B       0x00                     ; '\0'
+  0x200008A9:  00           DC.B       0x00                     ; '\0'
+  0x200008AA:  00           DC.B       0x00                     ; '\0'
+  0x200008AB:  00           DC.B       0x00                     ; '\0'
+  0x200008AC:  00           DC.B       0x00                     ; '\0'
+  0x200008AD:  09           DC.B       0x09                     ; '\t'
+  0x200008AE:  00           DC.B       0x00                     ; '\0'
+  0x200008AF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008B0:  00           DC.B       0x00                     ; '\0'
+  0x200008B1:  00           DC.B       0x00                     ; '\0'
+  0x200008B2:  00           DC.B       0x00                     ; '\0'
+  0x200008B3:  00           DC.B       0x00                     ; '\0'
+  0x200008B4:  00           DC.B       0x00                     ; '\0'
+  0x200008B5:  00           DC.B       0x00                     ; '\0'
+  0x200008B6:  00           DC.B       0x00                     ; '\0'
+  0x200008B7:  00           DC.B       0x00                     ; '\0'
+  0x200008B8:  00           DC.B       0x00                     ; '\0'
+  0x200008B9:  00           DC.B       0x00                     ; '\0'
+  0x200008BA:  00           DC.B       0x00                     ; '\0'
+  0x200008BB:  00           DC.B       0x00                     ; '\0'
+  0x200008BC:  00           DC.B       0x00                     ; '\0'
+  0x200008BD:  0B           DC.B       0x0B                     ; '\v'
+  0x200008BE:  00           DC.B       0x00                     ; '\0'
+  0x200008BF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008C0:  00           DC.B       0x00                     ; '\0'
+  0x200008C1:  00           DC.B       0x00                     ; '\0'
+  0x200008C2:  00           DC.B       0x00                     ; '\0'
+  0x200008C3:  00           DC.B       0x00                     ; '\0'
+  0x200008C4:  00           DC.B       0x00                     ; '\0'
+  0x200008C5:  00           DC.B       0x00                     ; '\0'
+  0x200008C6:  00           DC.B       0x00                     ; '\0'
+  0x200008C7:  00           DC.B       0x00                     ; '\0'
+  0x200008C8:  00           DC.B       0x00                     ; '\0'
+  0x200008C9:  00           DC.B       0x00                     ; '\0'
+  0x200008CA:  00           DC.B       0x00                     ; '\0'
+  0x200008CB:  00           DC.B       0x00                     ; '\0'
+  0x200008CC:  00           DC.B       0x00                     ; '\0'
+  0x200008CD:  0D           DC.B       0x0D                     ; '\r'
+  0x200008CE:  00           DC.B       0x00                     ; '\0'
+  0x200008CF:  32           DC.B       0x32                     ; '2'
+  0x200008D0:  06           DC.B       0x06                     ; '\x06'
+  0x200008D1:  00           DC.B       0x00                     ; '\0'
+  0x200008D2:  00           DC.B       0x00                     ; '\0'
+  0x200008D3:  84           DC.B       0x84                     ; '\x84'
+  0x200008D4:  00           DC.B       0x00                     ; '\0'
+  0x200008D5:  00           DC.B       0x00                     ; '\0'
+  0x200008D6:  00           DC.B       0x00                     ; '\0'
+  0x200008D7:  00           DC.B       0x00                     ; '\0'
+  0x200008D8:  00           DC.B       0x00                     ; '\0'
+  0x200008D9:  00           DC.B       0x00                     ; '\0'
+  0x200008DA:  00           DC.B       0x00                     ; '\0'
+  0x200008DB:  00           DC.B       0x00                     ; '\0'
+  0x200008DC:  00           DC.B       0x00                     ; '\0'
+  0x200008DD:  0D           DC.B       0x0D                     ; '\r'
+  0x200008DE:  00           DC.B       0x00                     ; '\0'
+  0x200008DF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008E0:  00           DC.B       0x00                     ; '\0'
+  0x200008E1:  00           DC.B       0x00                     ; '\0'
+  0x200008E2:  00           DC.B       0x00                     ; '\0'
+  0x200008E3:  00           DC.B       0x00                     ; '\0'
+  0x200008E4:  00           DC.B       0x00                     ; '\0'
+  0x200008E5:  00           DC.B       0x00                     ; '\0'
+  0x200008E6:  00           DC.B       0x00                     ; '\0'
+  0x200008E7:  00           DC.B       0x00                     ; '\0'
+  0x200008E8:  00           DC.B       0x00                     ; '\0'
+  0x200008E9:  00           DC.B       0x00                     ; '\0'
+  0x200008EA:  00           DC.B       0x00                     ; '\0'
+  0x200008EB:  00           DC.B       0x00                     ; '\0'
+  0x200008EC:  00           DC.B       0x00                     ; '\0'
+  0x200008ED:  0F           DC.B       0x0F                     ; '\x0F'
+  0x200008EE:  00           DC.B       0x00                     ; '\0'
+  0x200008EF:  32           DC.B       0x32                     ; '2'
+  0x200008F0:  06           DC.B       0x06                     ; '\x06'
+  0x200008F1:  00           DC.B       0x00                     ; '\0'
+  0x200008F2:  00           DC.B       0x00                     ; '\0'
+  0x200008F3:  68           DC.B       0x68                     ; 'h'
+  0x200008F4:  00           DC.B       0x00                     ; '\0'
+  0x200008F5:  00           DC.B       0x00                     ; '\0'
+  0x200008F6:  00           DC.B       0x00                     ; '\0'
+  0x200008F7:  00           DC.B       0x00                     ; '\0'
+  0x200008F8:  00           DC.B       0x00                     ; '\0'
+  0x200008F9:  00           DC.B       0x00                     ; '\0'
+  0x200008FA:  00           DC.B       0x00                     ; '\0'
+  0x200008FB:  00           DC.B       0x00                     ; '\0'
+  0x200008FC:  00           DC.B       0x00                     ; '\0'
+  0x200008FD:  0F           DC.B       0x0F                     ; '\x0F'
+  0x200008FE:  00           DC.B       0x00                     ; '\0'
+  0x200008FF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000900:  00           DC.B       0x00                     ; '\0'
+  0x20000901:  00           DC.B       0x00                     ; '\0'
+  0x20000902:  00           DC.B       0x00                     ; '\0'
+  0x20000903:  00           DC.B       0x00                     ; '\0'
+  0x20000904:  00           DC.B       0x00                     ; '\0'
+  0x20000905:  00           DC.B       0x00                     ; '\0'
+  0x20000906:  00           DC.B       0x00                     ; '\0'
+  0x20000907:  00           DC.B       0x00                     ; '\0'
+  0x20000908:  00           DC.B       0x00                     ; '\0'
+  0x20000909:  00           DC.B       0x00                     ; '\0'
+  0x2000090A:  00           DC.B       0x00                     ; '\0'
+  0x2000090B:  00           DC.B       0x00                     ; '\0'
+  0x2000090C:  00           DC.B       0x00                     ; '\0'
+  0x2000090D:  11           DC.B       0x11                     ; '\x11'
+  0x2000090E:  00           DC.B       0x00                     ; '\0'
+  0x2000090F:  E5           DC.B       0xE5                     ; '\xE5'
+  0x20000910:  05           DC.B       0x05                     ; '\x05'
+  0x20000911:  00           DC.B       0x00                     ; '\0'
+  0x20000912:  00           DC.B       0x00                     ; '\0'
+  0x20000913:  01           DC.B       0x01                     ; '\x01'
+  0x20000914:  00           DC.B       0x00                     ; '\0'
+  0x20000915:  00           DC.B       0x00                     ; '\0'
+  0x20000916:  00           DC.B       0x00                     ; '\0'
+  0x20000917:  16           DC.B       0x16                     ; '\x16'
+  0x20000918:  00           DC.B       0x00                     ; '\0'
+  0x20000919:  00           DC.B       0x00                     ; '\0'
+  0x2000091A:  00           DC.B       0x00                     ; '\0'
+  0x2000091B:  02           DC.B       0x02                     ; '\x02'
+  0x2000091C:  00           DC.B       0x00                     ; '\0'
+  0x2000091D:  13           DC.B       0x13                     ; '\x13'
+  0x2000091E:  00           DC.B       0x00                     ; '\0'
+  0x2000091F:  08           DC.B       0x08                     ; '\b'
+  0x20000920:  05           DC.B       0x05                     ; '\x05'
+  0x20000921:  00           DC.B       0x00                     ; '\0'
+  0x20000922:  00           DC.B       0x00                     ; '\0'
+  0x20000923:  01           DC.B       0x01                     ; '\x01'
+  0x20000924:  00           DC.B       0x00                     ; '\0'
+  0x20000925:  00           DC.B       0x00                     ; '\0'
+  0x20000926:  00           DC.B       0x00                     ; '\0'
+  0x20000927:  3A           DC.B       0x3A                     ; ':'
+  0x20000928:  00           DC.B       0x00                     ; '\0'
+  0x20000929:  00           DC.B       0x00                     ; '\0'
+  0x2000092A:  00           DC.B       0x00                     ; '\0'
+  0x2000092B:  02           DC.B       0x02                     ; '\x02'
+  0x2000092C:  00           DC.B       0x00                     ; '\0'
+  0x2000092D:  14           DC.B       0x14                     ; '\x14'
+  0x2000092E:  00           DC.B       0x00                     ; '\0'
+  0x2000092F:  7E           DC.B       0x7E                     ; '~'
+  0x20000930:  05           DC.B       0x05                     ; '\x05'
+  0x20000931:  00           DC.B       0x00                     ; '\0'
+  0x20000932:  00           DC.B       0x00                     ; '\0'
+  0x20000933:  01           DC.B       0x01                     ; '\x01'
+  0x20000934:  00           DC.B       0x00                     ; '\0'
+  0x20000935:  00           DC.B       0x00                     ; '\0'
+  0x20000936:  00           DC.B       0x00                     ; '\0'
+  0x20000937:  58           DC.B       0x58                     ; 'X'
+  0x20000938:  00           DC.B       0x00                     ; '\0'
+  0x20000939:  00           DC.B       0x00                     ; '\0'
+  0x2000093A:  00           DC.B       0x00                     ; '\0'
+  0x2000093B:  02           DC.B       0x02                     ; '\x02'
+  0x2000093C:  00           DC.B       0x00                     ; '\0'
+  0x2000093D:  16           DC.B       0x16                     ; '\x16'
+  0x2000093E:  00           DC.B       0x00                     ; '\0'
+  0x2000093F:  32           DC.B       0x32                     ; '2'
+  0x20000940:  06           DC.B       0x06                     ; '\x06'
+  0x20000941:  00           DC.B       0x00                     ; '\0'
+  0x20000942:  00           DC.B       0x00                     ; '\0'
+  0x20000943:  64           DC.B       0x64                     ; 'd'
+  0x20000944:  00           DC.B       0x00                     ; '\0'
+  0x20000945:  00           DC.B       0x00                     ; '\0'
+  0x20000946:  00           DC.B       0x00                     ; '\0'
+  0x20000947:  00           DC.B       0x00                     ; '\0'
+  0x20000948:  00           DC.B       0x00                     ; '\0'
+  0x20000949:  00           DC.B       0x00                     ; '\0'
+  0x2000094A:  00           DC.B       0x00                     ; '\0'
+  0x2000094B:  00           DC.B       0x00                     ; '\0'
+  0x2000094C:  00           DC.B       0x00                     ; '\0'
+  0x2000094D:  11           DC.B       0x11                     ; '\x11'
+  0x2000094E:  00           DC.B       0x00                     ; '\0'
+  0x2000094F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000950:  00           DC.B       0x00                     ; '\0'
+  0x20000951:  00           DC.B       0x00                     ; '\0'
+  0x20000952:  00           DC.B       0x00                     ; '\0'
+  0x20000953:  00           DC.B       0x00                     ; '\0'
+  0x20000954:  00           DC.B       0x00                     ; '\0'
+  0x20000955:  00           DC.B       0x00                     ; '\0'
+  0x20000956:  00           DC.B       0x00                     ; '\0'
+  0x20000957:  00           DC.B       0x00                     ; '\0'
+  0x20000958:  00           DC.B       0x00                     ; '\0'
+  0x20000959:  00           DC.B       0x00                     ; '\0'
+  0x2000095A:  00           DC.B       0x00                     ; '\0'
+  0x2000095B:  00           DC.B       0x00                     ; '\0'
+  0x2000095C:  00           DC.B       0x00                     ; '\0'
+  0x2000095D:  13           DC.B       0x13                     ; '\x13'
+  0x2000095E:  00           DC.B       0x00                     ; '\0'
+  0x2000095F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000960:  00           DC.B       0x00                     ; '\0'
+  0x20000961:  00           DC.B       0x00                     ; '\0'
+  0x20000962:  00           DC.B       0x00                     ; '\0'
+  0x20000963:  00           DC.B       0x00                     ; '\0'
+  0x20000964:  00           DC.B       0x00                     ; '\0'
+  0x20000965:  00           DC.B       0x00                     ; '\0'
+  0x20000966:  00           DC.B       0x00                     ; '\0'
+  0x20000967:  00           DC.B       0x00                     ; '\0'
+  0x20000968:  00           DC.B       0x00                     ; '\0'
+  0x20000969:  00           DC.B       0x00                     ; '\0'
+  0x2000096A:  00           DC.B       0x00                     ; '\0'
+  0x2000096B:  00           DC.B       0x00                     ; '\0'
+  0x2000096C:  00           DC.B       0x00                     ; '\0'
+  0x2000096D:  14           DC.B       0x14                     ; '\x14'
+  0x2000096E:  00           DC.B       0x00                     ; '\0'
+  0x2000096F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000970:  00           DC.B       0x00                     ; '\0'
+  0x20000971:  00           DC.B       0x00                     ; '\0'
+  0x20000972:  00           DC.B       0x00                     ; '\0'
+  0x20000973:  00           DC.B       0x00                     ; '\0'
+  0x20000974:  00           DC.B       0x00                     ; '\0'
+  0x20000975:  00           DC.B       0x00                     ; '\0'
+  0x20000976:  00           DC.B       0x00                     ; '\0'
+  0x20000977:  00           DC.B       0x00                     ; '\0'
+  0x20000978:  00           DC.B       0x00                     ; '\0'
+  0x20000979:  00           DC.B       0x00                     ; '\0'
+  0x2000097A:  00           DC.B       0x00                     ; '\0'
+  0x2000097B:  00           DC.B       0x00                     ; '\0'
+  0x2000097C:  00           DC.B       0x00                     ; '\0'
+  0x2000097D:  16           DC.B       0x16                     ; '\x16'
+  0x2000097E:  00           DC.B       0x00                     ; '\0'
+  0x2000097F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000980:  00           DC.B       0x00                     ; '\0'
+  0x20000981:  00           DC.B       0x00                     ; '\0'
+  0x20000982:  00           DC.B       0x00                     ; '\0'
+  0x20000983:  00           DC.B       0x00                     ; '\0'
+  0x20000984:  00           DC.B       0x00                     ; '\0'
+  0x20000985:  00           DC.B       0x00                     ; '\0'
+  0x20000986:  00           DC.B       0x00                     ; '\0'
+  0x20000987:  00           DC.B       0x00                     ; '\0'
+  0x20000988:  00           DC.B       0x00                     ; '\0'
+  0x20000989:  00           DC.B       0x00                     ; '\0'
+  0x2000098A:  00           DC.B       0x00                     ; '\0'
+  0x2000098B:  00           DC.B       0x00                     ; '\0'
+  0x2000098C:  00           DC.B       0x00                     ; '\0'
+  0x2000098D:  18           DC.B       0x18                     ; '\x18'
+  0x2000098E:  00           DC.B       0x00                     ; '\0'
+  0x2000098F:  32           DC.B       0x32                     ; '2'
+  0x20000990:  06           DC.B       0x06                     ; '\x06'
+  0x20000991:  00           DC.B       0x00                     ; '\0'
+  0x20000992:  00           DC.B       0x00                     ; '\0'
+  0x20000993:  64           DC.B       0x64                     ; 'd'
+  0x20000994:  00           DC.B       0x00                     ; '\0'
+  0x20000995:  00           DC.B       0x00                     ; '\0'
+  0x20000996:  00           DC.B       0x00                     ; '\0'
+  0x20000997:  00           DC.B       0x00                     ; '\0'
+  0x20000998:  00           DC.B       0x00                     ; '\0'
+  0x20000999:  00           DC.B       0x00                     ; '\0'
+  0x2000099A:  00           DC.B       0x00                     ; '\0'
+  0x2000099B:  00           DC.B       0x00                     ; '\0'
+  0x2000099C:  00           DC.B       0x00                     ; '\0'
+  0x2000099D:  18           DC.B       0x18                     ; '\x18'
+  0x2000099E:  00           DC.B       0x00                     ; '\0'
+  0x2000099F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009A0:  00           DC.B       0x00                     ; '\0'
+  0x200009A1:  00           DC.B       0x00                     ; '\0'
+  0x200009A2:  00           DC.B       0x00                     ; '\0'
+  0x200009A3:  00           DC.B       0x00                     ; '\0'
+  0x200009A4:  00           DC.B       0x00                     ; '\0'
+  0x200009A5:  00           DC.B       0x00                     ; '\0'
+  0x200009A6:  00           DC.B       0x00                     ; '\0'
+  0x200009A7:  00           DC.B       0x00                     ; '\0'
+  0x200009A8:  00           DC.B       0x00                     ; '\0'
+  0x200009A9:  00           DC.B       0x00                     ; '\0'
+  0x200009AA:  00           DC.B       0x00                     ; '\0'
+  0x200009AB:  00           DC.B       0x00                     ; '\0'
+  0x200009AC:  00           DC.B       0x00                     ; '\0'
+  0x200009AD:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200009AE:  00           DC.B       0x00                     ; '\0'
+  0x200009AF:  32           DC.B       0x32                     ; '2'
+  0x200009B0:  06           DC.B       0x06                     ; '\x06'
+  0x200009B1:  00           DC.B       0x00                     ; '\0'
+  0x200009B2:  00           DC.B       0x00                     ; '\0'
+  0x200009B3:  34           DC.B       0x34                     ; '4'
+  0x200009B4:  00           DC.B       0x00                     ; '\0'
+  0x200009B5:  00           DC.B       0x00                     ; '\0'
+  0x200009B6:  00           DC.B       0x00                     ; '\0'
+  0x200009B7:  00           DC.B       0x00                     ; '\0'
+  0x200009B8:  00           DC.B       0x00                     ; '\0'
+  0x200009B9:  00           DC.B       0x00                     ; '\0'
+  0x200009BA:  00           DC.B       0x00                     ; '\0'
+  0x200009BB:  00           DC.B       0x00                     ; '\0'
+  0x200009BC:  00           DC.B       0x00                     ; '\0'
+  0x200009BD:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200009BE:  00           DC.B       0x00                     ; '\0'
+  0x200009BF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009C0:  00           DC.B       0x00                     ; '\0'
+  0x200009C1:  00           DC.B       0x00                     ; '\0'
+  0x200009C2:  00           DC.B       0x00                     ; '\0'
+  0x200009C3:  00           DC.B       0x00                     ; '\0'
+  0x200009C4:  00           DC.B       0x00                     ; '\0'
+  0x200009C5:  00           DC.B       0x00                     ; '\0'
+  0x200009C6:  00           DC.B       0x00                     ; '\0'
+  0x200009C7:  00           DC.B       0x00                     ; '\0'
+  0x200009C8:  00           DC.B       0x00                     ; '\0'
+  0x200009C9:  00           DC.B       0x00                     ; '\0'
+  0x200009CA:  00           DC.B       0x00                     ; '\0'
+  0x200009CB:  00           DC.B       0x00                     ; '\0'
+  0x200009CC:  00           DC.B       0x00                     ; '\0'
+  0x200009CD:  1C           DC.B       0x1C                     ; '\x1C'
+  0x200009CE:  00           DC.B       0x00                     ; '\0'
+  0x200009CF:  32           DC.B       0x32                     ; '2'
+  0x200009D0:  06           DC.B       0x06                     ; '\x06'
+  0x200009D1:  00           DC.B       0x00                     ; '\0'
+  0x200009D2:  00           DC.B       0x00                     ; '\0'
+  0x200009D3:  34           DC.B       0x34                     ; '4'
+  0x200009D4:  00           DC.B       0x00                     ; '\0'
+  0x200009D5:  00           DC.B       0x00                     ; '\0'
+  0x200009D6:  00           DC.B       0x00                     ; '\0'
+  0x200009D7:  00           DC.B       0x00                     ; '\0'
+  0x200009D8:  00           DC.B       0x00                     ; '\0'
+  0x200009D9:  00           DC.B       0x00                     ; '\0'
+  0x200009DA:  00           DC.B       0x00                     ; '\0'
+  0x200009DB:  00           DC.B       0x00                     ; '\0'
+  0x200009DC:  00           DC.B       0x00                     ; '\0'
+  0x200009DD:  1C           DC.B       0x1C                     ; '\x1C'
+  0x200009DE:  00           DC.B       0x00                     ; '\0'
+  0x200009DF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009E0:  00           DC.B       0x00                     ; '\0'
+  0x200009E1:  00           DC.B       0x00                     ; '\0'
+  0x200009E2:  00           DC.B       0x00                     ; '\0'
+  0x200009E3:  00           DC.B       0x00                     ; '\0'
+  0x200009E4:  00           DC.B       0x00                     ; '\0'
+  0x200009E5:  00           DC.B       0x00                     ; '\0'
+  0x200009E6:  00           DC.B       0x00                     ; '\0'
+  0x200009E7:  00           DC.B       0x00                     ; '\0'
+  0x200009E8:  00           DC.B       0x00                     ; '\0'
+  0x200009E9:  00           DC.B       0x00                     ; '\0'
+  0x200009EA:  00           DC.B       0x00                     ; '\0'
+  0x200009EB:  00           DC.B       0x00                     ; '\0'
+  0x200009EC:  00           DC.B       0x00                     ; '\0'
+  0x200009ED:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200009EE:  00           DC.B       0x00                     ; '\0'
+  0x200009EF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009F0:  00           DC.B       0x00                     ; '\0'
+  0x200009F1:  00           DC.B       0x00                     ; '\0'
+  0x200009F2:  00           DC.B       0x00                     ; '\0'
+  0x200009F3:  00           DC.B       0x00                     ; '\0'
+  0x200009F4:  00           DC.B       0x00                     ; '\0'
+  0x200009F5:  00           DC.B       0x00                     ; '\0'
+  0x200009F6:  00           DC.B       0x00                     ; '\0'
+  0x200009F7:  00           DC.B       0x00                     ; '\0'
+  0x200009F8:  00           DC.B       0x00                     ; '\0'
+  0x200009F9:  00           DC.B       0x00                     ; '\0'
+  0x200009FA:  00           DC.B       0x00                     ; '\0'
+  0x200009FB:  00           DC.B       0x00                     ; '\0'
+  0x200009FC:  00           DC.B       0x00                     ; '\0'
+  0x200009FD:  20           DC.B       0x20                     ; ' '
+  0x200009FE:  00           DC.B       0x00                     ; '\0'
+  0x200009FF:  32           DC.B       0x32                     ; '2'
+  0x20000A00:  06           DC.B       0x06                     ; '\x06'
+  0x20000A01:  00           DC.B       0x00                     ; '\0'
+  0x20000A02:  00           DC.B       0x00                     ; '\0'
+  0x20000A03:  2C           DC.B       0x2C                     ; ','
+  0x20000A04:  00           DC.B       0x00                     ; '\0'
+  0x20000A05:  00           DC.B       0x00                     ; '\0'
+  0x20000A06:  00           DC.B       0x00                     ; '\0'
+  0x20000A07:  00           DC.B       0x00                     ; '\0'
+  0x20000A08:  00           DC.B       0x00                     ; '\0'
+  0x20000A09:  00           DC.B       0x00                     ; '\0'
+  0x20000A0A:  00           DC.B       0x00                     ; '\0'
+  0x20000A0B:  00           DC.B       0x00                     ; '\0'
+  0x20000A0C:  00           DC.B       0x00                     ; '\0'
+  0x20000A0D:  20           DC.B       0x20                     ; ' '
+  0x20000A0E:  00           DC.B       0x00                     ; '\0'
+  0x20000A0F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A10:  00           DC.B       0x00                     ; '\0'
+  0x20000A11:  00           DC.B       0x00                     ; '\0'
+  0x20000A12:  00           DC.B       0x00                     ; '\0'
+  0x20000A13:  00           DC.B       0x00                     ; '\0'
+  0x20000A14:  00           DC.B       0x00                     ; '\0'
+  0x20000A15:  00           DC.B       0x00                     ; '\0'
+  0x20000A16:  00           DC.B       0x00                     ; '\0'
+  0x20000A17:  00           DC.B       0x00                     ; '\0'
+  0x20000A18:  00           DC.B       0x00                     ; '\0'
+  0x20000A19:  00           DC.B       0x00                     ; '\0'
+  0x20000A1A:  00           DC.B       0x00                     ; '\0'
+  0x20000A1B:  00           DC.B       0x00                     ; '\0'
+  0x20000A1C:  00           DC.B       0x00                     ; '\0'
+  0x20000A1D:  22           DC.B       0x22                     ; '\"'
+  0x20000A1E:  00           DC.B       0x00                     ; '\0'
+  0x20000A1F:  32           DC.B       0x32                     ; '2'
+  0x20000A20:  06           DC.B       0x06                     ; '\x06'
+  0x20000A21:  00           DC.B       0x00                     ; '\0'
+  0x20000A22:  00           DC.B       0x00                     ; '\0'
+  0x20000A23:  48           DC.B       0x48                     ; 'H'
+  0x20000A24:  00           DC.B       0x00                     ; '\0'
+  0x20000A25:  00           DC.B       0x00                     ; '\0'
+  0x20000A26:  00           DC.B       0x00                     ; '\0'
+  0x20000A27:  00           DC.B       0x00                     ; '\0'
+  0x20000A28:  00           DC.B       0x00                     ; '\0'
+  0x20000A29:  00           DC.B       0x00                     ; '\0'
+  0x20000A2A:  00           DC.B       0x00                     ; '\0'
+  0x20000A2B:  00           DC.B       0x00                     ; '\0'
+  0x20000A2C:  00           DC.B       0x00                     ; '\0'
+  0x20000A2D:  22           DC.B       0x22                     ; '\"'
+  0x20000A2E:  00           DC.B       0x00                     ; '\0'
+  0x20000A2F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A30:  00           DC.B       0x00                     ; '\0'
+  0x20000A31:  00           DC.B       0x00                     ; '\0'
+  0x20000A32:  00           DC.B       0x00                     ; '\0'
+  0x20000A33:  00           DC.B       0x00                     ; '\0'
+  0x20000A34:  00           DC.B       0x00                     ; '\0'
+  0x20000A35:  00           DC.B       0x00                     ; '\0'
+  0x20000A36:  00           DC.B       0x00                     ; '\0'
+  0x20000A37:  00           DC.B       0x00                     ; '\0'
+  0x20000A38:  00           DC.B       0x00                     ; '\0'
+  0x20000A39:  00           DC.B       0x00                     ; '\0'
+  0x20000A3A:  00           DC.B       0x00                     ; '\0'
+  0x20000A3B:  00           DC.B       0x00                     ; '\0'
+  0x20000A3C:  00           DC.B       0x00                     ; '\0'
+  0x20000A3D:  24           DC.B       0x24                     ; '$'
+  0x20000A3E:  00           DC.B       0x00                     ; '\0'
+  0x20000A3F:  32           DC.B       0x32                     ; '2'
+  0x20000A40:  06           DC.B       0x06                     ; '\x06'
+  0x20000A41:  00           DC.B       0x00                     ; '\0'
+  0x20000A42:  00           DC.B       0x00                     ; '\0'
+  0x20000A43:  54           DC.B       0x54                     ; 'T'
+  0x20000A44:  00           DC.B       0x00                     ; '\0'
+  0x20000A45:  00           DC.B       0x00                     ; '\0'
+  0x20000A46:  00           DC.B       0x00                     ; '\0'
+  0x20000A47:  00           DC.B       0x00                     ; '\0'
+  0x20000A48:  00           DC.B       0x00                     ; '\0'
+  0x20000A49:  00           DC.B       0x00                     ; '\0'
+  0x20000A4A:  00           DC.B       0x00                     ; '\0'
+  0x20000A4B:  00           DC.B       0x00                     ; '\0'
+  0x20000A4C:  00           DC.B       0x00                     ; '\0'
+  0x20000A4D:  24           DC.B       0x24                     ; '$'
+  0x20000A4E:  00           DC.B       0x00                     ; '\0'
+  0x20000A4F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A50:  00           DC.B       0x00                     ; '\0'
+  0x20000A51:  00           DC.B       0x00                     ; '\0'
+  0x20000A52:  00           DC.B       0x00                     ; '\0'
+  0x20000A53:  00           DC.B       0x00                     ; '\0'
+  0x20000A54:  00           DC.B       0x00                     ; '\0'
+  0x20000A55:  00           DC.B       0x00                     ; '\0'
+  0x20000A56:  00           DC.B       0x00                     ; '\0'
+  0x20000A57:  00           DC.B       0x00                     ; '\0'
+  0x20000A58:  00           DC.B       0x00                     ; '\0'
+  0x20000A59:  00           DC.B       0x00                     ; '\0'
+  0x20000A5A:  00           DC.B       0x00                     ; '\0'
+  0x20000A5B:  00           DC.B       0x00                     ; '\0'
+  0x20000A5C:  00           DC.B       0x00                     ; '\0'
+  0x20000A5D:  26           DC.B       0x26                     ; '&'
+  0x20000A5E:  00           DC.B       0x00                     ; '\0'
+  0x20000A5F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A60:  00           DC.B       0x00                     ; '\0'
+  0x20000A61:  00           DC.B       0x00                     ; '\0'
+  0x20000A62:  00           DC.B       0x00                     ; '\0'
+  0x20000A63:  00           DC.B       0x00                     ; '\0'
+  0x20000A64:  00           DC.B       0x00                     ; '\0'
+  0x20000A65:  00           DC.B       0x00                     ; '\0'
+  0x20000A66:  00           DC.B       0x00                     ; '\0'
+  0x20000A67:  00           DC.B       0x00                     ; '\0'
+  0x20000A68:  00           DC.B       0x00                     ; '\0'
+  0x20000A69:  00           DC.B       0x00                     ; '\0'
+  0x20000A6A:  00           DC.B       0x00                     ; '\0'
+  0x20000A6B:  00           DC.B       0x00                     ; '\0'
+  0x20000A6C:  00           DC.B       0x00                     ; '\0'
+  0x20000A6D:  28           DC.B       0x28                     ; '('
+  0x20000A6E:  00           DC.B       0x00                     ; '\0'
+  0x20000A6F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A70:  00           DC.B       0x00                     ; '\0'
+  0x20000A71:  00           DC.B       0x00                     ; '\0'
+  0x20000A72:  00           DC.B       0x00                     ; '\0'
+  0x20000A73:  00           DC.B       0x00                     ; '\0'
+  0x20000A74:  00           DC.B       0x00                     ; '\0'
+  0x20000A75:  00           DC.B       0x00                     ; '\0'
+  0x20000A76:  00           DC.B       0x00                     ; '\0'
+  0x20000A77:  00           DC.B       0x00                     ; '\0'
+  0x20000A78:  00           DC.B       0x00                     ; '\0'
+  0x20000A79:  00           DC.B       0x00                     ; '\0'
+  0x20000A7A:  00           DC.B       0x00                     ; '\0'
+  0x20000A7B:  00           DC.B       0x00                     ; '\0'
+  0x20000A7C:  00           DC.B       0x00                     ; '\0'
+  0x20000A7D:  2A           DC.B       0x2A                     ; '*'
+  0x20000A7E:  00           DC.B       0x00                     ; '\0'
+  0x20000A7F:  32           DC.B       0x32                     ; '2'
+  0x20000A80:  06           DC.B       0x06                     ; '\x06'
+  0x20000A81:  00           DC.B       0x00                     ; '\0'
+  0x20000A82:  00           DC.B       0x00                     ; '\0'
+  0x20000A83:  1C           DC.B       0x1C                     ; '\x1C'
+  0x20000A84:  00           DC.B       0x00                     ; '\0'
+  0x20000A85:  00           DC.B       0x00                     ; '\0'
+  0x20000A86:  00           DC.B       0x00                     ; '\0'
+  0x20000A87:  00           DC.B       0x00                     ; '\0'
+  0x20000A88:  00           DC.B       0x00                     ; '\0'
+  0x20000A89:  00           DC.B       0x00                     ; '\0'
+  0x20000A8A:  00           DC.B       0x00                     ; '\0'
+  0x20000A8B:  00           DC.B       0x00                     ; '\0'
+  0x20000A8C:  00           DC.B       0x00                     ; '\0'
+  0x20000A8D:  2A           DC.B       0x2A                     ; '*'
+  0x20000A8E:  00           DC.B       0x00                     ; '\0'
+  0x20000A8F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A90:  00           DC.B       0x00                     ; '\0'
+  0x20000A91:  00           DC.B       0x00                     ; '\0'
+  0x20000A92:  00           DC.B       0x00                     ; '\0'
+  0x20000A93:  00           DC.B       0x00                     ; '\0'
+  0x20000A94:  00           DC.B       0x00                     ; '\0'
+  0x20000A95:  00           DC.B       0x00                     ; '\0'
+  0x20000A96:  00           DC.B       0x00                     ; '\0'
+  0x20000A97:  00           DC.B       0x00                     ; '\0'
+  0x20000A98:  00           DC.B       0x00                     ; '\0'
+  0x20000A99:  00           DC.B       0x00                     ; '\0'
+  0x20000A9A:  00           DC.B       0x00                     ; '\0'
+  0x20000A9B:  00           DC.B       0x00                     ; '\0'
+  0x20000A9C:  00           DC.B       0x00                     ; '\0'
+  0x20000A9D:  2C           DC.B       0x2C                     ; ','
+  0x20000A9E:  00           DC.B       0x00                     ; '\0'
+  0x20000A9F:  32           DC.B       0x32                     ; '2'
+  0x20000AA0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AA1:  00           DC.B       0x00                     ; '\0'
+  0x20000AA2:  00           DC.B       0x00                     ; '\0'
+  0x20000AA3:  10           DC.B       0x10                     ; '\x10'
+  0x20000AA4:  00           DC.B       0x00                     ; '\0'
+  0x20000AA5:  00           DC.B       0x00                     ; '\0'
+  0x20000AA6:  00           DC.B       0x00                     ; '\0'
+  0x20000AA7:  00           DC.B       0x00                     ; '\0'
+  0x20000AA8:  00           DC.B       0x00                     ; '\0'
+  0x20000AA9:  00           DC.B       0x00                     ; '\0'
+  0x20000AAA:  00           DC.B       0x00                     ; '\0'
+  0x20000AAB:  00           DC.B       0x00                     ; '\0'
+  0x20000AAC:  00           DC.B       0x00                     ; '\0'
+  0x20000AAD:  2C           DC.B       0x2C                     ; ','
+  0x20000AAE:  00           DC.B       0x00                     ; '\0'
+  0x20000AAF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AB0:  00           DC.B       0x00                     ; '\0'
+  0x20000AB1:  00           DC.B       0x00                     ; '\0'
+  0x20000AB2:  00           DC.B       0x00                     ; '\0'
+  0x20000AB3:  00           DC.B       0x00                     ; '\0'
+  0x20000AB4:  00           DC.B       0x00                     ; '\0'
+  0x20000AB5:  00           DC.B       0x00                     ; '\0'
+  0x20000AB6:  00           DC.B       0x00                     ; '\0'
+  0x20000AB7:  00           DC.B       0x00                     ; '\0'
+  0x20000AB8:  00           DC.B       0x00                     ; '\0'
+  0x20000AB9:  00           DC.B       0x00                     ; '\0'
+  0x20000ABA:  00           DC.B       0x00                     ; '\0'
+  0x20000ABB:  00           DC.B       0x00                     ; '\0'
+  0x20000ABC:  00           DC.B       0x00                     ; '\0'
+  0x20000ABD:  2E           DC.B       0x2E                     ; '.'
+  0x20000ABE:  00           DC.B       0x00                     ; '\0'
+  0x20000ABF:  32           DC.B       0x32                     ; '2'
+  0x20000AC0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AC1:  00           DC.B       0x00                     ; '\0'
+  0x20000AC2:  00           DC.B       0x00                     ; '\0'
+  0x20000AC3:  10           DC.B       0x10                     ; '\x10'
+  0x20000AC4:  00           DC.B       0x00                     ; '\0'
+  0x20000AC5:  00           DC.B       0x00                     ; '\0'
+  0x20000AC6:  00           DC.B       0x00                     ; '\0'
+  0x20000AC7:  00           DC.B       0x00                     ; '\0'
+  0x20000AC8:  00           DC.B       0x00                     ; '\0'
+  0x20000AC9:  00           DC.B       0x00                     ; '\0'
+  0x20000ACA:  00           DC.B       0x00                     ; '\0'
+  0x20000ACB:  00           DC.B       0x00                     ; '\0'
+  0x20000ACC:  00           DC.B       0x00                     ; '\0'
+  0x20000ACD:  2E           DC.B       0x2E                     ; '.'
+  0x20000ACE:  00           DC.B       0x00                     ; '\0'
+  0x20000ACF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AD0:  00           DC.B       0x00                     ; '\0'
+  0x20000AD1:  00           DC.B       0x00                     ; '\0'
+  0x20000AD2:  00           DC.B       0x00                     ; '\0'
+  0x20000AD3:  00           DC.B       0x00                     ; '\0'
+  0x20000AD4:  00           DC.B       0x00                     ; '\0'
+  0x20000AD5:  00           DC.B       0x00                     ; '\0'
+  0x20000AD6:  00           DC.B       0x00                     ; '\0'
+  0x20000AD7:  00           DC.B       0x00                     ; '\0'
+  0x20000AD8:  00           DC.B       0x00                     ; '\0'
+  0x20000AD9:  00           DC.B       0x00                     ; '\0'
+  0x20000ADA:  00           DC.B       0x00                     ; '\0'
+  0x20000ADB:  00           DC.B       0x00                     ; '\0'
+  0x20000ADC:  00           DC.B       0x00                     ; '\0'
+  0x20000ADD:  30           DC.B       0x30                     ; '0'
+  0x20000ADE:  00           DC.B       0x00                     ; '\0'
+  0x20000ADF:  32           DC.B       0x32                     ; '2'
+  0x20000AE0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AE1:  00           DC.B       0x00                     ; '\0'
+  0x20000AE2:  00           DC.B       0x00                     ; '\0'
+  0x20000AE3:  60           DC.B       0x60                     ; '`'
+  0x20000AE4:  00           DC.B       0x00                     ; '\0'
+  0x20000AE5:  00           DC.B       0x00                     ; '\0'
+  0x20000AE6:  00           DC.B       0x00                     ; '\0'
+  0x20000AE7:  00           DC.B       0x00                     ; '\0'
+  0x20000AE8:  00           DC.B       0x00                     ; '\0'
+  0x20000AE9:  00           DC.B       0x00                     ; '\0'
+  0x20000AEA:  00           DC.B       0x00                     ; '\0'
+  0x20000AEB:  00           DC.B       0x00                     ; '\0'
+  0x20000AEC:  00           DC.B       0x00                     ; '\0'
+  0x20000AED:  30           DC.B       0x30                     ; '0'
+  0x20000AEE:  00           DC.B       0x00                     ; '\0'
+  0x20000AEF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AF0:  00           DC.B       0x00                     ; '\0'
+  0x20000AF1:  00           DC.B       0x00                     ; '\0'
+  0x20000AF2:  00           DC.B       0x00                     ; '\0'
+  0x20000AF3:  00           DC.B       0x00                     ; '\0'
+  0x20000AF4:  00           DC.B       0x00                     ; '\0'
+  0x20000AF5:  00           DC.B       0x00                     ; '\0'
+  0x20000AF6:  00           DC.B       0x00                     ; '\0'
+  0x20000AF7:  00           DC.B       0x00                     ; '\0'
+  0x20000AF8:  00           DC.B       0x00                     ; '\0'
+  0x20000AF9:  00           DC.B       0x00                     ; '\0'
+  0x20000AFA:  00           DC.B       0x00                     ; '\0'
+  0x20000AFB:  00           DC.B       0x00                     ; '\0'
+  0x20000AFC:  00           DC.B       0x00                     ; '\0'
+  0x20000AFD:  32           DC.B       0x32                     ; '2'
+  0x20000AFE:  00           DC.B       0x00                     ; '\0'
+  0x20000AFF:  32           DC.B       0x32                     ; '2'
+  0x20000B00:  06           DC.B       0x06                     ; '\x06'
+  0x20000B01:  00           DC.B       0x00                     ; '\0'
+  0x20000B02:  00           DC.B       0x00                     ; '\0'
+  0x20000B03:  60           DC.B       0x60                     ; '`'
+  0x20000B04:  00           DC.B       0x00                     ; '\0'
+  0x20000B05:  00           DC.B       0x00                     ; '\0'
+  0x20000B06:  00           DC.B       0x00                     ; '\0'
+  0x20000B07:  00           DC.B       0x00                     ; '\0'
+  0x20000B08:  00           DC.B       0x00                     ; '\0'
+  0x20000B09:  00           DC.B       0x00                     ; '\0'
+  0x20000B0A:  00           DC.B       0x00                     ; '\0'
+  0x20000B0B:  00           DC.B       0x00                     ; '\0'
+  0x20000B0C:  00           DC.B       0x00                     ; '\0'
+  0x20000B0D:  32           DC.B       0x32                     ; '2'
+  0x20000B0E:  00           DC.B       0x00                     ; '\0'
+  0x20000B0F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B10:  00           DC.B       0x00                     ; '\0'
+  0x20000B11:  00           DC.B       0x00                     ; '\0'
+  0x20000B12:  00           DC.B       0x00                     ; '\0'
+  0x20000B13:  00           DC.B       0x00                     ; '\0'
+  0x20000B14:  00           DC.B       0x00                     ; '\0'
+  0x20000B15:  00           DC.B       0x00                     ; '\0'
+  0x20000B16:  00           DC.B       0x00                     ; '\0'
+  0x20000B17:  00           DC.B       0x00                     ; '\0'
+  0x20000B18:  00           DC.B       0x00                     ; '\0'
+  0x20000B19:  00           DC.B       0x00                     ; '\0'
+  0x20000B1A:  00           DC.B       0x00                     ; '\0'
+  0x20000B1B:  00           DC.B       0x00                     ; '\0'
+  0x20000B1C:  00           DC.B       0x00                     ; '\0'
+  0x20000B1D:  34           DC.B       0x34                     ; '4'
+  0x20000B1E:  00           DC.B       0x00                     ; '\0'
+  0x20000B1F:  32           DC.B       0x32                     ; '2'
+  0x20000B20:  06           DC.B       0x06                     ; '\x06'
+  0x20000B21:  00           DC.B       0x00                     ; '\0'
+  0x20000B22:  00           DC.B       0x00                     ; '\0'
+  0x20000B23:  50           DC.B       0x50                     ; 'P'
+  0x20000B24:  00           DC.B       0x00                     ; '\0'
+  0x20000B25:  00           DC.B       0x00                     ; '\0'
+  0x20000B26:  00           DC.B       0x00                     ; '\0'
+  0x20000B27:  00           DC.B       0x00                     ; '\0'
+  0x20000B28:  00           DC.B       0x00                     ; '\0'
+  0x20000B29:  00           DC.B       0x00                     ; '\0'
+  0x20000B2A:  00           DC.B       0x00                     ; '\0'
+  0x20000B2B:  00           DC.B       0x00                     ; '\0'
+  0x20000B2C:  00           DC.B       0x00                     ; '\0'
+  0x20000B2D:  34           DC.B       0x34                     ; '4'
+  0x20000B2E:  00           DC.B       0x00                     ; '\0'
+  0x20000B2F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B30:  00           DC.B       0x00                     ; '\0'
+  0x20000B31:  00           DC.B       0x00                     ; '\0'
+  0x20000B32:  00           DC.B       0x00                     ; '\0'
+  0x20000B33:  00           DC.B       0x00                     ; '\0'
+  0x20000B34:  00           DC.B       0x00                     ; '\0'
+  0x20000B35:  00           DC.B       0x00                     ; '\0'
+  0x20000B36:  00           DC.B       0x00                     ; '\0'
+  0x20000B37:  00           DC.B       0x00                     ; '\0'
+  0x20000B38:  00           DC.B       0x00                     ; '\0'
+  0x20000B39:  00           DC.B       0x00                     ; '\0'
+  0x20000B3A:  00           DC.B       0x00                     ; '\0'
+  0x20000B3B:  00           DC.B       0x00                     ; '\0'
+  0x20000B3C:  00           DC.B       0x00                     ; '\0'
+  0x20000B3D:  36           DC.B       0x36                     ; '6'
+  0x20000B3E:  00           DC.B       0x00                     ; '\0'
+  0x20000B3F:  32           DC.B       0x32                     ; '2'
+  0x20000B40:  06           DC.B       0x06                     ; '\x06'
+  0x20000B41:  00           DC.B       0x00                     ; '\0'
+  0x20000B42:  00           DC.B       0x00                     ; '\0'
+  0x20000B43:  50           DC.B       0x50                     ; 'P'
+  0x20000B44:  00           DC.B       0x00                     ; '\0'
+  0x20000B45:  00           DC.B       0x00                     ; '\0'
+  0x20000B46:  00           DC.B       0x00                     ; '\0'
+  0x20000B47:  00           DC.B       0x00                     ; '\0'
+  0x20000B48:  00           DC.B       0x00                     ; '\0'
+  0x20000B49:  00           DC.B       0x00                     ; '\0'
+  0x20000B4A:  00           DC.B       0x00                     ; '\0'
+  0x20000B4B:  00           DC.B       0x00                     ; '\0'
+  0x20000B4C:  00           DC.B       0x00                     ; '\0'
+  0x20000B4D:  36           DC.B       0x36                     ; '6'
+  0x20000B4E:  00           DC.B       0x00                     ; '\0'
+  0x20000B4F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B50:  00           DC.B       0x00                     ; '\0'
+  0x20000B51:  00           DC.B       0x00                     ; '\0'
+  0x20000B52:  00           DC.B       0x00                     ; '\0'
+  0x20000B53:  00           DC.B       0x00                     ; '\0'
+  0x20000B54:  00           DC.B       0x00                     ; '\0'
+  0x20000B55:  00           DC.B       0x00                     ; '\0'
+  0x20000B56:  00           DC.B       0x00                     ; '\0'
+  0x20000B57:  00           DC.B       0x00                     ; '\0'
+  0x20000B58:  00           DC.B       0x00                     ; '\0'
+  0x20000B59:  00           DC.B       0x00                     ; '\0'
+  0x20000B5A:  00           DC.B       0x00                     ; '\0'
+  0x20000B5B:  00           DC.B       0x00                     ; '\0'
+  0x20000B5C:  00           DC.B       0x00                     ; '\0'
+  0x20000B5D:  38           DC.B       0x38                     ; '8'
+  0x20000B5E:  00           DC.B       0x00                     ; '\0'
+  0x20000B5F:  32           DC.B       0x32                     ; '2'
+  0x20000B60:  06           DC.B       0x06                     ; '\x06'
+  0x20000B61:  00           DC.B       0x00                     ; '\0'
+  0x20000B62:  00           DC.B       0x00                     ; '\0'
+  0x20000B63:  34           DC.B       0x34                     ; '4'
+  0x20000B64:  00           DC.B       0x00                     ; '\0'
+  0x20000B65:  00           DC.B       0x00                     ; '\0'
+  0x20000B66:  00           DC.B       0x00                     ; '\0'
+  0x20000B67:  00           DC.B       0x00                     ; '\0'
+  0x20000B68:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc._acDownBuffer from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=16, align=1

+
+
_acDownBuffer:
+  0x20000B69:  00           DC.B       0x00                     ; '\0'
+  0x20000B6A:  53           DC.B       0x53                     ; 'S'
+  0x20000B6B:  45           DC.B       0x45                     ; 'E'
+  0x20000B6C:  47           DC.B       0x47                     ; 'G'
+  0x20000B6D:  47           DC.B       0x47                     ; 'G'
+  0x20000B6E:  45           DC.B       0x45                     ; 'E'
+  0x20000B6F:  52           DC.B       0x52                     ; 'R'
+  0x20000B70:  20           DC.B       0x20                     ; ' '
+  0x20000B71:  43           DC.B       0x43                     ; 'C'
+  0x20000B72:  2F           DC.B       0x2F                     ; '/'
+  0x20000B73:  43           DC.B       0x43                     ; 'C'
+  0x20000B74:  2B           DC.B       0x2B                     ; '+'
+  0x20000B75:  2B           DC.B       0x2B                     ; '+'
+  0x20000B76:  20           DC.B       0x20                     ; ' '
+  0x20000B77:  63           DC.B       0x63                     ; 'c'
+  0x20000B78:  6F           DC.B       0x6F                     ; 'o'
+
+

Section .no_init from PowerPro_lto.o, size=1, align=4

+
+
bootLoaderMark:
+  0x20000B7C:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.libc.__SEGGER_RTL_global_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=20, align=4

+
+
__SEGGER_RTL_global_locale:
+__RAL_global_locale:
+  0x20000B80:  08005780     DC.W       __SEGGER_RTL_c_locale
+  0x20000B84:  08005780     DC.W       __SEGGER_RTL_c_locale
+  0x20000B88:  08005780     DC.W       __SEGGER_RTL_c_locale
+  0x20000B8C:  08005780     DC.W       __SEGGER_RTL_c_locale
+  0x20000B90:  08005780     DC.W       __SEGGER_RTL_c_locale
+
+

Section .data.uwTickPrio from PowerPro_lto.o, size=4, align=4

+
+
uwTickPrio:
+  0x20000B94:  04           DC.B       0x04                     ; '\x04'
+  0x20000B95:  00           DC.B       0x00                     ; '\0'
+  0x20000B96:  00           DC.B       0x00                     ; '\0'
+  0x20000B97:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.libc.stdout from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stdout:
+  0x20000B98:  200006CC     DC.W       __SEGGER_RTL_stdout_file
+
+

Section .data.libc.stdin from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stdin:
+  0x20000B9C:  200006D0     DC.W       __SEGGER_RTL_stdin_file
+
+

Section .data.libc.stderr from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stderr:
+  0x20000BA0:  200006D4     DC.W       __SEGGER_RTL_stderr_file
+
+

Section .data.SystemCoreClock from PowerPro_lto.o, size=4, align=4

+
+
SystemCoreClock:
+  0x20000BA4:  00           DC.B       0x00                     ; '\0'
+  0x20000BA5:  1B           DC.B       0x1B                     ; '\x1B'
+  0x20000BA6:  B7           DC.B       0xB7                     ; '\xB7'
+  0x20000BA7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.block.stack from [ Linker created ], size=2048, align=8

+
+  0x20002800:  00           DC.B       0x00                     ; '\0'
+  0x20002801:  00           DC.B       0x00                     ; '\0'
+  0x20002802:  00           DC.B       0x00                     ; '\0'
+  0x20002803:  00           DC.B       0x00                     ; '\0'
+  0x20002804:  00           DC.B       0x00                     ; '\0'
+  0x20002805:  00           DC.B       0x00                     ; '\0'
+  0x20002806:  00           DC.B       0x00                     ; '\0'
+  0x20002807:  00           DC.B       0x00                     ; '\0'
+  0x20002808:  00           DC.B       0x00                     ; '\0'
+  0x20002809:  00           DC.B       0x00                     ; '\0'
+  0x2000280A:  00           DC.B       0x00                     ; '\0'
+  0x2000280B:  00           DC.B       0x00                     ; '\0'
+  0x2000280C:  00           DC.B       0x00                     ; '\0'
+  0x2000280D:  00           DC.B       0x00                     ; '\0'
+  0x2000280E:  00           DC.B       0x00                     ; '\0'
+  0x2000280F:  00           DC.B       0x00                     ; '\0'
+  0x20002810:  00           DC.B       0x00                     ; '\0'
+  0x20002811:  00           DC.B       0x00                     ; '\0'
+  0x20002812:  00           DC.B       0x00                     ; '\0'
+  0x20002813:  00           DC.B       0x00                     ; '\0'
+  0x20002814:  00           DC.B       0x00                     ; '\0'
+  0x20002815:  00           DC.B       0x00                     ; '\0'
+  0x20002816:  00           DC.B       0x00                     ; '\0'
+  0x20002817:  00           DC.B       0x00                     ; '\0'
+  0x20002818:  00           DC.B       0x00                     ; '\0'
+  0x20002819:  00           DC.B       0x00                     ; '\0'
+  0x2000281A:  00           DC.B       0x00                     ; '\0'
+  0x2000281B:  00           DC.B       0x00                     ; '\0'
+  0x2000281C:  00           DC.B       0x00                     ; '\0'
+  0x2000281D:  00           DC.B       0x00                     ; '\0'
+  0x2000281E:  00           DC.B       0x00                     ; '\0'
+  0x2000281F:  00           DC.B       0x00                     ; '\0'
+  0x20002820:  00           DC.B       0x00                     ; '\0'
+  0x20002821:  00           DC.B       0x00                     ; '\0'
+  0x20002822:  00           DC.B       0x00                     ; '\0'
+  0x20002823:  00           DC.B       0x00                     ; '\0'
+  0x20002824:  00           DC.B       0x00                     ; '\0'
+  0x20002825:  00           DC.B       0x00                     ; '\0'
+  0x20002826:  00           DC.B       0x00                     ; '\0'
+  0x20002827:  00           DC.B       0x00                     ; '\0'
+  0x20002828:  00           DC.B       0x00                     ; '\0'
+  0x20002829:  00           DC.B       0x00                     ; '\0'
+  0x2000282A:  00           DC.B       0x00                     ; '\0'
+  0x2000282B:  00           DC.B       0x00                     ; '\0'
+  0x2000282C:  00           DC.B       0x00                     ; '\0'
+  0x2000282D:  00           DC.B       0x00                     ; '\0'
+  0x2000282E:  00           DC.B       0x00                     ; '\0'
+  0x2000282F:  00           DC.B       0x00                     ; '\0'
+  0x20002830:  00           DC.B       0x00                     ; '\0'
+  0x20002831:  00           DC.B       0x00                     ; '\0'
+  0x20002832:  00           DC.B       0x00                     ; '\0'
+  0x20002833:  00           DC.B       0x00                     ; '\0'
+  0x20002834:  00           DC.B       0x00                     ; '\0'
+  0x20002835:  00           DC.B       0x00                     ; '\0'
+  0x20002836:  00           DC.B       0x00                     ; '\0'
+  0x20002837:  00           DC.B       0x00                     ; '\0'
+  0x20002838:  00           DC.B       0x00                     ; '\0'
+  0x20002839:  00           DC.B       0x00                     ; '\0'
+  0x2000283A:  00           DC.B       0x00                     ; '\0'
+  0x2000283B:  00           DC.B       0x00                     ; '\0'
+  0x2000283C:  00           DC.B       0x00                     ; '\0'
+  0x2000283D:  00           DC.B       0x00                     ; '\0'
+  0x2000283E:  00           DC.B       0x00                     ; '\0'
+  0x2000283F:  00           DC.B       0x00                     ; '\0'
+  0x20002840:  00           DC.B       0x00                     ; '\0'
+  0x20002841:  00           DC.B       0x00                     ; '\0'
+  0x20002842:  00           DC.B       0x00                     ; '\0'
+  0x20002843:  00           DC.B       0x00                     ; '\0'
+  0x20002844:  00           DC.B       0x00                     ; '\0'
+  0x20002845:  00           DC.B       0x00                     ; '\0'
+  0x20002846:  00           DC.B       0x00                     ; '\0'
+  0x20002847:  00           DC.B       0x00                     ; '\0'
+  0x20002848:  00           DC.B       0x00                     ; '\0'
+  0x20002849:  00           DC.B       0x00                     ; '\0'
+  0x2000284A:  00           DC.B       0x00                     ; '\0'
+  0x2000284B:  00           DC.B       0x00                     ; '\0'
+  0x2000284C:  00           DC.B       0x00                     ; '\0'
+  0x2000284D:  00           DC.B       0x00                     ; '\0'
+  0x2000284E:  00           DC.B       0x00                     ; '\0'
+  0x2000284F:  00           DC.B       0x00                     ; '\0'
+  0x20002850:  00           DC.B       0x00                     ; '\0'
+  0x20002851:  00           DC.B       0x00                     ; '\0'
+  0x20002852:  00           DC.B       0x00                     ; '\0'
+  0x20002853:  00           DC.B       0x00                     ; '\0'
+  0x20002854:  00           DC.B       0x00                     ; '\0'
+  0x20002855:  00           DC.B       0x00                     ; '\0'
+  0x20002856:  00           DC.B       0x00                     ; '\0'
+  0x20002857:  00           DC.B       0x00                     ; '\0'
+  0x20002858:  00           DC.B       0x00                     ; '\0'
+  0x20002859:  00           DC.B       0x00                     ; '\0'
+  0x2000285A:  00           DC.B       0x00                     ; '\0'
+  0x2000285B:  00           DC.B       0x00                     ; '\0'
+  0x2000285C:  00           DC.B       0x00                     ; '\0'
+  0x2000285D:  00           DC.B       0x00                     ; '\0'
+  0x2000285E:  00           DC.B       0x00                     ; '\0'
+  0x2000285F:  00           DC.B       0x00                     ; '\0'
+  0x20002860:  00           DC.B       0x00                     ; '\0'
+  0x20002861:  00           DC.B       0x00                     ; '\0'
+  0x20002862:  00           DC.B       0x00                     ; '\0'
+  0x20002863:  00           DC.B       0x00                     ; '\0'
+  0x20002864:  00           DC.B       0x00                     ; '\0'
+  0x20002865:  00           DC.B       0x00                     ; '\0'
+  0x20002866:  00           DC.B       0x00                     ; '\0'
+  0x20002867:  00           DC.B       0x00                     ; '\0'
+  0x20002868:  00           DC.B       0x00                     ; '\0'
+  0x20002869:  00           DC.B       0x00                     ; '\0'
+  0x2000286A:  00           DC.B       0x00                     ; '\0'
+  0x2000286B:  00           DC.B       0x00                     ; '\0'
+  0x2000286C:  00           DC.B       0x00                     ; '\0'
+  0x2000286D:  00           DC.B       0x00                     ; '\0'
+  0x2000286E:  00           DC.B       0x00                     ; '\0'
+  0x2000286F:  00           DC.B       0x00                     ; '\0'
+  0x20002870:  00           DC.B       0x00                     ; '\0'
+  0x20002871:  00           DC.B       0x00                     ; '\0'
+  0x20002872:  00           DC.B       0x00                     ; '\0'
+  0x20002873:  00           DC.B       0x00                     ; '\0'
+  0x20002874:  00           DC.B       0x00                     ; '\0'
+  0x20002875:  00           DC.B       0x00                     ; '\0'
+  0x20002876:  00           DC.B       0x00                     ; '\0'
+  0x20002877:  00           DC.B       0x00                     ; '\0'
+  0x20002878:  00           DC.B       0x00                     ; '\0'
+  0x20002879:  00           DC.B       0x00                     ; '\0'
+  0x2000287A:  00           DC.B       0x00                     ; '\0'
+  0x2000287B:  00           DC.B       0x00                     ; '\0'
+  0x2000287C:  00           DC.B       0x00                     ; '\0'
+  0x2000287D:  00           DC.B       0x00                     ; '\0'
+  0x2000287E:  00           DC.B       0x00                     ; '\0'
+  0x2000287F:  00           DC.B       0x00                     ; '\0'
+  0x20002880:  00           DC.B       0x00                     ; '\0'
+  0x20002881:  00           DC.B       0x00                     ; '\0'
+  0x20002882:  00           DC.B       0x00                     ; '\0'
+  0x20002883:  00           DC.B       0x00                     ; '\0'
+  0x20002884:  00           DC.B       0x00                     ; '\0'
+  0x20002885:  00           DC.B       0x00                     ; '\0'
+  0x20002886:  00           DC.B       0x00                     ; '\0'
+  0x20002887:  00           DC.B       0x00                     ; '\0'
+  0x20002888:  00           DC.B       0x00                     ; '\0'
+  0x20002889:  00           DC.B       0x00                     ; '\0'
+  0x2000288A:  00           DC.B       0x00                     ; '\0'
+  0x2000288B:  00           DC.B       0x00                     ; '\0'
+  0x2000288C:  00           DC.B       0x00                     ; '\0'
+  0x2000288D:  00           DC.B       0x00                     ; '\0'
+  0x2000288E:  00           DC.B       0x00                     ; '\0'
+  0x2000288F:  00           DC.B       0x00                     ; '\0'
+  0x20002890:  00           DC.B       0x00                     ; '\0'
+  0x20002891:  00           DC.B       0x00                     ; '\0'
+  0x20002892:  00           DC.B       0x00                     ; '\0'
+  0x20002893:  00           DC.B       0x00                     ; '\0'
+  0x20002894:  00           DC.B       0x00                     ; '\0'
+  0x20002895:  00           DC.B       0x00                     ; '\0'
+  0x20002896:  00           DC.B       0x00                     ; '\0'
+  0x20002897:  00           DC.B       0x00                     ; '\0'
+  0x20002898:  00           DC.B       0x00                     ; '\0'
+  0x20002899:  00           DC.B       0x00                     ; '\0'
+  0x2000289A:  00           DC.B       0x00                     ; '\0'
+  0x2000289B:  00           DC.B       0x00                     ; '\0'
+  0x2000289C:  00           DC.B       0x00                     ; '\0'
+  0x2000289D:  00           DC.B       0x00                     ; '\0'
+  0x2000289E:  00           DC.B       0x00                     ; '\0'
+  0x2000289F:  00           DC.B       0x00                     ; '\0'
+  0x200028A0:  00           DC.B       0x00                     ; '\0'
+  0x200028A1:  00           DC.B       0x00                     ; '\0'
+  0x200028A2:  00           DC.B       0x00                     ; '\0'
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+  0x20002FF6:  00           DC.B       0x00                     ; '\0'
+  0x20002FF7:  00           DC.B       0x00                     ; '\0'
+  0x20002FF8:  00           DC.B       0x00                     ; '\0'
+  0x20002FF9:  00           DC.B       0x00                     ; '\0'
+  0x20002FFA:  00           DC.B       0x00                     ; '\0'
+  0x20002FFB:  00           DC.B       0x00                     ; '\0'
+  0x20002FFC:  00           DC.B       0x00                     ; '\0'
+  0x20002FFD:  00           DC.B       0x00                     ; '\0'
+  0x20002FFE:  00           DC.B       0x00                     ; '\0'
+  0x20002FFF:  00           DC.B       0x00                     ; '\0'
+
+

LINK SUMMARY

+ +
+ 24 872 bytes read-only  code    + 
+  2 625 bytes read-only  data    =  27 497 bytes read-only (total)
+  4 992 bytes read-write data
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSizeUsedUnusedAlignment Loss
FLASH08000000-080077FF30 72027 501 89.52%3 219 10.48%0 0.00%
RAM20000000-20002FFF12 2884 992 40.62%7 260 59.08%36 0.29%
+ +
+Link complete: 0 error.
+
+ Index: /trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1330 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49 + Copyright (c) 2017-2025 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 16 442 1 049 8 1 629 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 214 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 16 684 1 049 8 1 629 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_balanced.a 2 812 32 + mbops_timeops_v6m_t_le_eabi_balanced.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 478 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 74 + strops_v6m_t_le_eabi_balanced.a 414 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 3 968 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 196 2 048 + ============================================= ========== ========== ========== ========== + Total: 20 652 1 844 40 4 901 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 960 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 146 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 992 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 348 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 412 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 34 + strops.o (strops_v6m_t_le_eabi_balanced.a) 380 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (11 members from 5 archives) 3 968 599 32 1 224 + Objects (4 files) 16 684 1 049 8 1 629 + Linker created (shared data, fills, blocks): 196 2 048 + ============================================= ========== ========== ========== ========== + Total: 20 652 1 844 40 4 901 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 196 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 196 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 16 684 1 049 8 1 629 + Archives (5 files) 3 968 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 20 652 1 844 40 4 901 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000B3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000B4-080000C3 SysTick_Handler 16 4 Code RX PowerPro_lto.o + 080000C4-080000D3 DMA1_Channel1_IRQHandler 16 4 Code RX PowerPro_lto.o + 080000D4-080000EB DMA1_Channel2_3_IRQHandler + 24 4 Code RX PowerPro_lto.o + 080000EC-08000293 TIM16_IRQHandler 424 4 Code RX PowerPro_lto.o + 08000294-08000687 USART1_IRQHandler 1 012 4 Code RX PowerPro_lto.o + 08000688-080006BF HAL_TIM_IC_CaptureCallback + 56 4 Code RX PowerPro_lto.o + 080006C0-080006CF SystemInit 16 4 Code RX PowerPro_lto.o + 080006D0-0800071F SystemCoreClockUpdate 80 4 Code RX PowerPro_lto.o + 08000720-0800077F HAL_InitTick 96 4 Code RX PowerPro_lto.o + 08000780-080009DB HAL_ADC_ConfigChannel 604 4 Code RX PowerPro_lto.o + 080009DC-08000ABF HAL_DMA_Init 228 4 Code RX PowerPro_lto.o + 08000AC0-08000B7F HAL_DMA_Start_IT 192 4 Code RX PowerPro_lto.o + 08000B80-08000BF7 HAL_DMA_Abort_IT 120 4 Code RX PowerPro_lto.o + 08000BF8-08000CD3 HAL_DMA_IRQHandler 220 4 Code RX PowerPro_lto.o + 08000CD4-08000D23 FLASH_WaitForLastOperation + 80 4 Code RX PowerPro_lto.o + 08000D24-08000EAB HAL_GPIO_Init 392 4 Code RX PowerPro_lto.o + 08000EAC-08000EFF HAL_RCC_GetSysClockFreq 84 4 Code RX PowerPro_lto.o + 08000F00-08000F3F HAL_RCC_GetPCLK1Freq 64 4 Code RX PowerPro_lto.o + 08000F40-0800104B HAL_RCCEx_PeriphCLKConfig 268 4 Code RX PowerPro_lto.o + 0800104C-08001117 HAL_TIM_Base_Init 204 4 Code RX PowerPro_lto.o + 08001118-080011AF TIM_Base_SetConfig 152 4 Code RX PowerPro_lto.o + 080011B0-08001583 HAL_UART_Init 980 4 Code RX PowerPro_lto.o + 08001584-080015F7 UART_WaitOnFlagUntilTimeout + 116 4 Code RX PowerPro_lto.o + 080015F8-08001657 UART_EndRxTransfer 96 4 Code RX PowerPro_lto.o + 08001658-080016A7 UART_DMATransmitCplt 80 4 Code RX PowerPro_lto.o + 080016A8-0800179F HAL_UART_Receive_DMA 248 4 Code RX PowerPro_lto.o + 080017A0-080017F3 UARTEx_SetNbDataToProcess 84 4 Code RX PowerPro_lto.o + 080017F4-08001947 EEPROM_Write 340 4 Code RX PowerPro_lto.o + 08001948-08001977 EEPROM_WriteDefaults 48 4 Code RX PowerPro_lto.o + 08001978-0800199B EEPROM_ReadDeviceParameter + 36 4 Code RX PowerPro_lto.o + 0800199C-080019D7 EEPROM_StoreConfig 60 4 Code RX PowerPro_lto.o + 080019D8-08003747 main 7 536 4 Code RX PowerPro_lto.o + 08003748-080037A3 JumpToBootloader 92 4 Code RX PowerPro_lto.o + 080037A4-0800384B HAL_UART_ErrorCallback 168 4 Code RX PowerPro_lto.o + 0800384C-08003887 mbCrc16 60 4 Code RX PowerPro_lto.o + 08003888-08003F0B MODE_SECONDARYPROTECTION_Exec + 1 668 4 Code RX PowerPro_lto.o + 08003F0C-08003F4B AHBPrescTable 64 4 Cnst RO PowerPro_lto.o + 08003F4C-08003F6B APBPrescTable 32 4 Cnst RO PowerPro_lto.o + 08003F6C-08003F7B [.rodata..Lswitch.table.UART_SetConfig] + 16 4 Cnst RO PowerPro_lto.o + 08003F7C-08003F8F _start 20 4 Code RX SEGGER_THUMB_Startup.o + 08003F90-08003F9F putchar 16 4 Code RX fileops.o (libc_v6m_t_le_eabi_balanced.a) + 08003FA0-08003FCB puts 44 4 Code RX fileops.o (libc_v6m_t_le_eabi_balanced.a) + 08003FCC-0800408F __aeabi_ddiv 196 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004090-080040C3 __aeabi_d2iz 52 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080040C4-080040E7 __aeabi_f2uiz 36 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080040E8-08004103 __aeabi_i2d 28 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004104-0800411F __aeabi_ui2d 28 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004120-0800415F __aeabi_idiv 64 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004160-08004197 __aeabi_uidiv 56 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004198-080041A7 __aeabi_uidivmod 16 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080041A8-08004247 __aeabi_uldivmod 160 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004248-080042BF vfprintf_l 120 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 080042C0-080042E7 printf 40 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 080042E8-080046A7 __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code RX __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 080046A8-080046DB __SEGGER_RTL_X_file_stat 52 4 Code RX prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 080046DC-0800472F _DoInit 84 4 Code RX SEGGER_RTT.o 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(strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 0x0800483F 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 0x0800483F 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 0x08004105 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 0x08004A09 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 0x08004161 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 0x08004199 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uldivmod 0x080041A9 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __startup_complete 0x08003F87 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x08003F7D 14 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x08003F8B 2 4 Code Gb SEGGER_THUMB_Startup.o + fputc 0x08004B19 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 0x08004F97 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x080019D9 7 536 4 Code Gb PowerPro_lto.o + mbCrc16 0x0800384D 60 4 Code Lc PowerPro_lto.o + memcmp 0x08005037 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + memcpy 0x08004A61 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + memset 0x08004845 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + printf 0x080042C1 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + putchar 0x08003F91 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + puts 0x08003FA1 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x08004F8F 2 Code Gb STM32C0xx_Startup.o + strlen 0x080047D1 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + vfprintf 0x08004D69 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x08004249 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 SysTick_Handler 16 4 Code Gb PowerPro_lto.o + 0x080000C5 DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080000D5 DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + 0x080000ED TIM16_IRQHandler 424 4 Code Gb PowerPro_lto.o + 0x08000295 USART1_IRQHandler 1 012 4 Code Gb PowerPro_lto.o + 0x08000689 HAL_TIM_IC_CaptureCallback + 56 4 Code Lc PowerPro_lto.o + 0x080006C1 SystemInit 16 4 Code Gb PowerPro_lto.o + 0x080006D1 SystemCoreClockUpdate 80 4 Code Gb PowerPro_lto.o + 0x08000721 HAL_InitTick 96 4 Code Lc PowerPro_lto.o + 0x08000781 HAL_ADC_ConfigChannel 604 4 Code Lc PowerPro_lto.o + 0x080009DD HAL_DMA_Init 228 4 Code Lc PowerPro_lto.o + 0x08000AC1 HAL_DMA_Start_IT 192 4 Code Lc PowerPro_lto.o + 0x08000B81 HAL_DMA_Abort_IT 120 4 Code Lc PowerPro_lto.o + 0x08000BF9 HAL_DMA_IRQHandler 220 4 Code Lc PowerPro_lto.o + 0x08000CD5 FLASH_WaitForLastOperation + 80 4 Code Lc PowerPro_lto.o + 0x08000D25 HAL_GPIO_Init 392 4 Code Lc PowerPro_lto.o + 0x08000EAD HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + 0x08000F01 HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + 0x08000F41 HAL_RCCEx_PeriphCLKConfig 268 4 Code Lc PowerPro_lto.o + 0x0800104D HAL_TIM_Base_Init 204 4 Code Lc PowerPro_lto.o + 0x08001119 TIM_Base_SetConfig 152 4 Code Lc PowerPro_lto.o + 0x080011B1 HAL_UART_Init 980 4 Code Lc PowerPro_lto.o + 0x08001585 UART_WaitOnFlagUntilTimeout + 116 4 Code Lc PowerPro_lto.o + 0x080015F9 UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + 0x08001659 UART_DMATransmitCplt 80 4 Code Lc PowerPro_lto.o + 0x080016A9 HAL_UART_Receive_DMA 248 4 Code Lc PowerPro_lto.o + 0x080017A1 UARTEx_SetNbDataToProcess 84 4 Code Lc PowerPro_lto.o + 0x080017F5 EEPROM_Write 340 4 Code Lc PowerPro_lto.o + 0x08001949 EEPROM_WriteDefaults 48 4 Code Lc PowerPro_lto.o + 0x08001979 EEPROM_ReadDeviceParameter + 36 4 Code Lc PowerPro_lto.o + 0x0800199D EEPROM_StoreConfig 60 4 Code Lc PowerPro_lto.o + 0x080019D9 main 7 536 4 Code Gb PowerPro_lto.o + 0x08003749 JumpToBootloader 92 4 Code Lc PowerPro_lto.o + 0x080037A5 HAL_UART_ErrorCallback 168 4 Code Lc PowerPro_lto.o + 0x0800384D mbCrc16 60 4 Code Lc PowerPro_lto.o + 0x08003889 MODE_SECONDARYPROTECTION_Exec + 1 668 4 Code Lc PowerPro_lto.o + 0x08003F7D _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003F87 __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003F87 __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003F8B exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003F91 putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003FA1 puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003FCD __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004091 __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080040C5 __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080040E9 __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004105 __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004121 __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004161 __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004199 __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080041A9 __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004249 vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x080042C1 printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x080042E9 __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x080042E9 __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x080046A9 __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080046DD _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004731 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004799 SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080047D1 strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x0800483D __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x0800483D __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x0800483D __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x0800483F __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x0800483F __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x0800483F __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004845 memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004851 __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004865 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004881 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004921 __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080049D7 NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x080049D9 __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004A07 HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004A09 __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004A27 SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004A29 __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004A57 PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x08004A59 __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004A5F ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + 0x08004A61 memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004A61 __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004A61 __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004A61 __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08004A6F UART_DMATxHalfCplt 2 2 Code Lc PowerPro_lto.o + 0x08004A71 UART_DMAError 134 2 Code Lc PowerPro_lto.o + 0x08004AF7 WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004AF9 RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004AFB FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004AFD RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004AFF EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B01 EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B03 EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B05 DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B07 ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B09 TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x08004B0B TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B0D TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B0F TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B11 TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B13 I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B15 SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B17 USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08004B19 fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004B3B __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004B73 __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004CC5 __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D4F __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D69 vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D83 __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004D8D _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004DA3 _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004DDD __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004E0B __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004E19 __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004E27 ADC_DMAConvCplt 100 2 Code Lc PowerPro_lto.o + 0x08004E8B ADC_DMAError 20 2 Code Lc PowerPro_lto.o + 0x08004E9F UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + 0x08004F43 UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + 0x08004F67 UART_DMAAbortOnError 16 2 Code Lc PowerPro_lto.o + 0x08004F8F reset_handler 2 Code Gb STM32C0xx_Startup.o + 0x08004F8F Reset_Handler 2 Code Gb STM32C0xx_Startup.o + 0x08004F97 fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004FCB __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004FDB __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004FDF _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005037 memcmp 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005147 __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005157 __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005163 __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080056D9 __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0x080057C1 __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0x080057D3 __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + +Function symbols by descending size: + + Symbol name Size Align Type Bd Object File + ------------------------- ---------- ----- ---- -- ----------- + main 7 536 4 Code Gb PowerPro_lto.o + MODE_SECONDARYPROTECTION_Exec + 1 668 4 Code Lc PowerPro_lto.o + USART1_IRQHandler 1 012 4 Code Gb PowerPro_lto.o + HAL_UART_Init 980 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + HAL_ADC_ConfigChannel 604 4 Code Lc PowerPro_lto.o + TIM16_IRQHandler 424 4 Code Gb PowerPro_lto.o + __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_GPIO_Init 392 4 Code Lc PowerPro_lto.o + EEPROM_Write 340 4 Code Lc PowerPro_lto.o + memcmp 272 2 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + HAL_RCCEx_PeriphCLKConfig 268 4 Code Lc PowerPro_lto.o + HAL_UART_Receive_DMA 248 4 Code Lc PowerPro_lto.o + HAL_DMA_Init 228 4 Code Lc PowerPro_lto.o + HAL_DMA_IRQHandler 220 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 204 4 Code Lc PowerPro_lto.o + __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_DMA_Start_IT 192 4 Code Lc PowerPro_lto.o + __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_UART_ErrorCallback 168 4 Code Lc PowerPro_lto.o + UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + TIM_Base_SetConfig 152 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_DMAError 134 2 Code Lc PowerPro_lto.o + HAL_DMA_Abort_IT 120 4 Code Lc PowerPro_lto.o + vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_WaitOnFlagUntilTimeout + 116 4 Code Lc PowerPro_lto.o + strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + ADC_DMAConvCplt 100 2 Code Lc PowerPro_lto.o + HAL_InitTick 96 4 Code Lc PowerPro_lto.o + UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + JumpToBootloader 92 4 Code Lc PowerPro_lto.o + _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + UARTEx_SetNbDataToProcess 84 4 Code Lc PowerPro_lto.o + _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + FLASH_WaitForLastOperation + 80 4 Code Lc PowerPro_lto.o + SystemCoreClockUpdate 80 4 Code Gb PowerPro_lto.o + UART_DMATransmitCplt 80 4 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + EEPROM_StoreConfig 60 4 Code Lc PowerPro_lto.o + mbCrc16 60 4 Code Lc PowerPro_lto.o + _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_TIM_IC_CaptureCallback + 56 4 Code Lc PowerPro_lto.o + SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + EEPROM_WriteDefaults 48 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + EEPROM_ReadDeviceParameter + 36 4 Code Lc PowerPro_lto.o + UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ADC_DMAError 20 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + SysTick_Handler 16 4 Code Gb PowerPro_lto.o + SystemInit 16 4 Code Gb PowerPro_lto.o + UART_DMAAbortOnError 16 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_tolower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towlower + 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + _start 14 4 Code Gb SEGGER_THUMB_Startup.o + memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_bufsize + 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + HardFault_Handler 2 2 Code Gb PowerPro_lto.o + NMI_Handler 2 2 Code Gb PowerPro_lto.o + PendSV_Handler 2 2 Code Gb PowerPro_lto.o + SVC_Handler 2 2 Code Gb PowerPro_lto.o + UART_DMATxHalfCplt 2 2 Code Lc PowerPro_lto.o + exit 2 4 Code Gb SEGGER_THUMB_Startup.o + ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + Reset_Handler 2 Code Gb STM32C0xx_Startup.o + SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + reset_handler 2 Code Gb STM32C0xx_Startup.o + +Read-write data symbols by name: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + SECONDARYPROTECTION_SM_Error.oldTimeMSTick + 0x20000700 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_Error.retry_counter + 0x200006FC 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter + 0x200006F8 4 4 Zero Lc PowerPro_lto.o + SECONDARYPROTECTION_SM_On.oldtime + 0x200006F4 4 4 Zero Lc PowerPro_lto.o + SystemCoreClock 0x20000B6C 4 4 Init Lc PowerPro_lto.o + _SEGGER_RTT 0x20000314 168 4 Zero Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __RAL_global_locale 0x20000B48 20 4 Init Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_global_locale + 0x20000B48 20 4 Init Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_locale_ptr 0x200006D8 4 4 Zero Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_stderr_file 0x200006D4 4 4 Zero Lc prinops_rtt.o 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(prinops_rtt_v6m_t_le_eabi_balanced.a) + stdin 0x20000B64 4 4 Init Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + stdout 0x20000B60 4 4 Init Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + sys_data 0x20000234 224 4 Zero Lc PowerPro_lto.o + temp 0x20000690 4 4 Zero Lc PowerPro_lto.o + uwTick 0x2000068C 4 4 Zero Lc PowerPro_lto.o + uwTickPrio 0x20000B5C 4 4 Init Lc PowerPro_lto.o + voltageUin 0x20000688 4 4 Zero Lc PowerPro_lto.o + voltageUout 0x20000684 4 4 Zero Lc PowerPro_lto.o + +Read-write data symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x20000000 modbusData 564 4 Zero Lc PowerPro_lto.o + 0x20000234 sys_data 224 4 Zero Lc PowerPro_lto.o + 0x20000314 _SEGGER_RTT 168 4 Zero Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x200003BC huart1 148 4 Zero Lc PowerPro_lto.o + 0x20000450 hadc1 100 4 Zero Lc PowerPro_lto.o + 0x200004B4 hdma_usart1_tx 92 4 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blinkCounter 4 4 Zero Lc PowerPro_lto.o + 0x200006F0 autoRetryMode 4 4 Zero Lc PowerPro_lto.o + 0x200006F4 SECONDARYPROTECTION_SM_On.oldtime + 4 4 Zero Lc PowerPro_lto.o + 0x200006F8 SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter + 4 4 Zero Lc PowerPro_lto.o + 0x200006FC SECONDARYPROTECTION_SM_Error.retry_counter + 4 4 Zero Lc PowerPro_lto.o + 0x20000700 SECONDARYPROTECTION_SM_Error.oldTimeMSTick + 4 4 Zero Lc PowerPro_lto.o + 0x20000704 relaisState 1 4 Zero Lc PowerPro_lto.o + 0x20000705 smState.154 1 Zero Lc PowerPro_lto.o + 0x20000706 smState.133 1 Zero Lc PowerPro_lto.o + 0x20000707 mode 1 Zero Lc PowerPro_lto.o + 0x20000708 pauseTime 1 4 Zero Lc PowerPro_lto.o + 0x20000709 buttonState 1 Zero Lc PowerPro_lto.o + 0x2000070C pFlash.0 1 4 Zero Lc PowerPro_lto.o + 0x20000710 onTimeRT 1 4 Zero Lc PowerPro_lto.o + 0x20000714 onTimeGN 1 4 Zero Lc PowerPro_lto.o + 0x20000718 onTime 1 4 Zero Lc PowerPro_lto.o + 0x2000071C offTimeRT 1 4 Zero Lc PowerPro_lto.o + 0x20000720 offTimeGN 1 4 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Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/PowerPro_link.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/PowerPro_link.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/PowerPro_link.ind (revision 41) @@ -0,0 +1,10 @@ +Output/Release_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o +Output/Release_12V/Obj/PowerPro/stm32c031xx_Vectors.o +Output/Release_12V/Obj/PowerPro/STM32C0xx_Startup.o +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a" Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_12V/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_12V/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_12V/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_12V/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/eeprom.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/eeprom.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/eeprom.d (revision 41) @@ -0,0 +1,49 @@ +Output/Release_12V/Obj/PowerPro/eeprom.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\eeprom.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\string.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_12V/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,70 @@ +Output/Release_12V/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/modbus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/modbus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/modbus.d (revision 41) @@ -0,0 +1,48 @@ +Output/Release_12V/Obj/PowerPro/modbus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modbus.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_12V/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_12V/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_12V/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_12V/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,53 @@ +Output/Release_12V/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,53 @@ +Output/Release_12V/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_12V/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_12V/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_12V/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release_12V/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/sysdata.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/sysdata.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/sysdata.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release_12V/Obj/PowerPro/sysdata.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\sysdata.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Release_12V/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_12V/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_12V/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_12V/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,49 @@ +Output/Release_12V/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.htm =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.htm (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.htm (revision 41) @@ -0,0 +1,37690 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ +
+SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49
+Copyright (c) 2017-2025 SEGGER Microcontroller GmbH    www.segger.com
+
+ +
+--add-region:FLASH1=0x00007800@0x08000000
+--add-region:RAM1=0x00003000@0x20000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Release_24V/Exe/PowerPro.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=6-M
+--silent
+-TD:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf
+--defsym=__STACKSIZE__=2048
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=1024
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_int_nwp
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.elf
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/PowerPro_lto.o
+Output/Release_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o
+Output/Release_24V/Obj/PowerPro/stm32c031xx_Vectors.o
+Output/Release_24V/Obj/PowerPro/STM32C0xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf'

+
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32C0xx_Flash.icf
+Purpose : STM32C0xx linker script for application placement in Flash,
+          for use with the SEGGER Linker.
+Maps    : STM32C011D6Yx, STM32C011F4Px, STM32C011F4Ux, STM32C011F6Px, 
+          STM32C011F6Ux, STM32C011J4Mx, STM32C011J6Mx, STM32C031C4Tx, 
+          STM32C031C4Ux, STM32C031C6Tx, STM32C031C6Ux, STM32C031F4Px, 
+          STM32C031F6Px, STM32C031G4Ux, STM32C031G6Ux, STM32C031K4Tx, 
+          STM32C031K4Ux, STM32C031K6Tx, STM32C031K6Ux
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM   = RAM1;
+
+//
+// Block definitions
+//
+define block vectors                        { section .vectors };                                   // Vector table section
+define block vectors_ram                    { section .vectors_ram };                               // Vector table section
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { block vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1                             { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { block vectors };                                      // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1                               { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM                       { block vectors_ram };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x08000000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x08000000180256stm32c031xx_Vectors.o
+

place at 0x20003000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#5> at line 111, col 45": place in [0x08000000 to 0x080077ff] with maximum packing

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
SysTick_HandlerCode0x080000B4164PowerPro_lto.o
DMA1_Channel1_IRQHandlerCode0x080000C4164PowerPro_lto.o
DMA1_Channel2_3_IRQHandlerCode0x080000D4244PowerPro_lto.o
TIM16_IRQHandlerCode0x080000EC2884PowerPro_lto.o
USART1_IRQHandlerCode0x0800020C9444PowerPro_lto.o
HAL_TIM_IC_CaptureCallbackCode0x080005BC564PowerPro_lto.o
SystemInitCode0x080005F4164PowerPro_lto.o
SystemCoreClockUpdateCode0x08000604804PowerPro_lto.o
HAL_InitTickCode0x08000654964PowerPro_lto.o
HAL_DelayCode0x080006B4204PowerPro_lto.o
HAL_ADC_ConfigChannelCode0x080006C86084PowerPro_lto.o
__NVIC_SystemResetCode0x08000928284PowerPro_lto.o
HAL_DMA_InitCode0x080009442244PowerPro_lto.o
HAL_DMA_Start_ITCode0x08000A241964PowerPro_lto.o
HAL_DMA_IRQHandlerCode0x08000AE81644PowerPro_lto.o
FLASH_WaitForLastOperationCode0x08000B8C804PowerPro_lto.o
HAL_FLASH_UnlockCode0x08000BDC324PowerPro_lto.o
HAL_GPIO_InitCode0x08000BFC3804PowerPro_lto.o
HAL_RCC_GetSysClockFreqCode0x08000D78844PowerPro_lto.o
HAL_RCC_GetPCLK1FreqCode0x08000DCC644PowerPro_lto.o
HAL_RCCEx_PeriphCLKConfigCode0x08000E0C2684PowerPro_lto.o
HAL_TIM_Base_InitCode0x08000F182044PowerPro_lto.o
TIM_Base_SetConfigCode0x08000FE41444PowerPro_lto.o
HAL_UART_InitCode0x080010749724PowerPro_lto.o
UART_WaitOnFlagUntilTimeoutCode0x08001440964PowerPro_lto.o
UART_EndRxTransferCode0x080014A0964PowerPro_lto.o
UART_DMATransmitCpltCode0x08001500804PowerPro_lto.o
HAL_UART_Receive_DMACode0x080015502484PowerPro_lto.o
UARTEx_SetNbDataToProcessCode0x08001648844PowerPro_lto.o
EEPROM_WriteCode0x0800169C2804PowerPro_lto.o
EEPROM_WriteDefaultsCode0x080017B4484PowerPro_lto.o
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dropLimitCounterZero0x200006E444PowerPro_lto.o
calTemperatureSensor30ValueZero0x200006E844PowerPro_lto.o
blinkCounterZero0x200006EC44PowerPro_lto.o
autoRetryMode.170Zero0x200006F044PowerPro_lto.o
autoRetryModeZero0x200006F444PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.175Zero0x200006F844PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtimeZero0x200006FC44PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176Zero0x2000070044PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounterZero0x2000070444PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.181Zero0x2000070844PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counterZero0x2000070C44PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182Zero0x2000071044PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTickZero0x2000071444PowerPro_lto.o
OVP_SM_On.ovpTimeCounterZero0x2000071844PowerPro_lto.o
OVP_SM_On.oldtimeZero0x2000071C44PowerPro_lto.o
LVP_SM_On.oldtimeZero0x2000072044PowerPro_lto.o
LVP_SM_On.lvpTimeCounterZero0x2000072444PowerPro_lto.o
LVP_OVP_SM_On.oldtimeZero0x2000072844PowerPro_lto.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounterZero0x2000072C44PowerPro_lto.o
relaisStateZero0x2000073014PowerPro_lto.o
smState.171Zero0x2000073111PowerPro_lto.o
smState.160Zero0x2000073211PowerPro_lto.o
smState.145Zero0x2000073311PowerPro_lto.o
pauseTimeZero0x2000073414PowerPro_lto.o
smState.137Zero0x2000073511PowerPro_lto.o
smState.122Zero0x2000073611PowerPro_lto.o
smStateZero0x2000073711PowerPro_lto.o
pFlash.0Zero0x2000073814PowerPro_lto.o
modeZero0x2000073911PowerPro_lto.o
buttonStateZero0x2000073A11PowerPro_lto.o
onTimeRTZero0x2000073C14PowerPro_lto.o
onTimeGNZero0x2000074014PowerPro_lto.o
[.bss.block.heap]None0x200007408[ Linker created ]
onTimeZero0x2000074414PowerPro_lto.o
offTimeRTZero0x2000074814PowerPro_lto.o
offTimeGNZero0x2000074C14PowerPro_lto.o
offTimeZero0x2000075014PowerPro_lto.o
blinkModeRTZero0x2000075414PowerPro_lto.o
blinkModeGNZero0x2000075814PowerPro_lto.o
alarmModeZero0x2000075C14PowerPro_lto.o
OVP_SM_On.ovpInputZero0x2000076014PowerPro_lto.o
LVP_SM_On.lvpInputZero0x2000076414PowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInputZero0x2000076814PowerPro_lto.o
_acUpBufferZero0x200007691 0241SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBufferZero0x20000B69161SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
bootLoaderMarkNone0x20000B7C14PowerPro_lto.o
__SEGGER_RTL_global_localeInit0x20000B80204mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
uwTickPrioInit0x20000B9444PowerPro_lto.o
stdoutInit0x20000B9844prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdinInit0x20000B9C44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stderrInit0x20000BA044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
SystemCoreClockInit0x20000BA444PowerPro_lto.o
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#10> at line 132, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x200007408[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
PowerPro_lto.o20 9941 80681 680
SEGGER_THUMB_Startup.o20
stm32c031xx_Vectors.o214
STM32C0xx_Startup.o8
Subtotal (4 objects)21 2361 80681 680
libc_v6m_t_le_eabi_small.a2 65632
mbops_timeops_v6m_t_le_eabi_small.a190541204
prinops_rtt_v6m_t_le_eabi_small.a47026121 220
SEGGER_crtinit_v6m_t_le_eabi_small.a74
strops_v6m_t_le_eabi_small.a94
Subtotal (5 archives)3 484599321 224
Linker created (shared data, fills, blocks):2202 048
Total:24 7202 625404 952
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)840
fileops.o (libc_v6m_t_le_eabi_small.a)144
floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)992
intasmops_arm.o (libc_v6m_t_le_eabi_small.a)308
mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)190541204
prinops.o (libc_v6m_t_le_eabi_small.a)37232
prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)581212
SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)74
SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)412261 208
strasmops_arm.o (strops_v6m_t_le_eabi_small.a)34
strops.o (strops_v6m_t_le_eabi_small.a)60
Subtotal (11 members from 5 archives)3 484599321 224
Objects (4 files)21 2361 80681 680
Linker created (shared data, fills, blocks):2202 048
Total:24 7202 625404 952
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table220
Memory for block 'stack'2 048
Subtotal (linker created):2202 048
Objects (4 files)21 2361 80681 680
Archives (5 files)3 484599321 224
Total:24 7202 625404 952
+

MODULE DETAIL

+

Module PowerPro_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
main11 380
MODE_SECONDARYPROTECTION_Exec1 660
MODE_SECONDARYPROTECTION_PLUS_Exec1 108
HAL_UART_Init972
USART1_IRQHandler944
HAL_ADC_ConfigChannel608
HAL_GPIO_Init380
TIM16_IRQHandler288
EEPROM_Write280
HAL_RCCEx_PeriphCLKConfig268
HAL_UART_Receive_DMA248
HAL_DMA_Init224
HAL_TIM_Base_Init204
HAL_DMA_Start_IT196
UART_DMAReceiveCplt168
HAL_UART_ErrorCallback168
HAL_DMA_IRQHandler164
TIM_Base_SetConfig144
UART_DMAError138
ADC_DMAConvCplt100
HAL_InitTick96
UART_WaitOnFlagUntilTimeout96
UART_EndRxTransfer96
JumpToBootloader92
HAL_RCC_GetSysClockFreq84
UARTEx_SetNbDataToProcess84
SystemCoreClockUpdate80
FLASH_WaitForLastOperation80
UART_DMATransmitCplt80
HAL_RCC_GetPCLK1Freq64
EEPROM_StoreConfig60
HAL_TIM_IC_CaptureCallback56
mbCrc1656
EEPROM_WriteDefaults48
UART_DMARxHalfCplt36
EEPROM_ReadDeviceParameter36
HAL_FLASH_Unlock32
__NVIC_SystemReset28
DMA1_Channel2_3_IRQHandler24
HAL_Delay20
ADC_DMAError20
SysTick_Handler16
DMA1_Channel1_IRQHandler16
SystemInit16
UART_DMAAbortOnError16
HAL_NVIC_SystemReset4
Error_Handler4
NMI_Handler2
HardFault_Handler2
SVC_Handler2
PendSV_Handler2
ADC_DMAHalfConvCplt2
UART_DMATxHalfCplt2
AHBPrescTable64
[.rodata..Lstr.11.179]60
[.rodata..Lstr.9]59
[.rodata..Lstr.124]53
[.rodata..Lstr.10]46
[.rodata..Lstr.118]45
[.rodata..Lstr.147]45
[.rodata..Lstr.13.180]43
[.rodata..Lstr.22.162]41
[.rodata..L.str.7]39
[.rodata..Lstr.18.130]39
[.rodata..Lstr.12.123]38
[.rodata..Lstr.20.132]38
[.rodata..Lstr.20.155]38
[.rodata..Lstr.15.173]37
[.rodata..Lstr.18]35
[.rodata..Lstr.18.153]35
[.rodata..Lstr.8.177]35
[.rodata..L.str.203]35
[.rodata..Lstr.16.172]34
APBPrescTable32
[.rodata..Lstr.12.138]32
[.rodata..Lstr.12.117]30
[.rodata..Lstr.12.146]30
[.rodata..Lstr.24.125]29
[.rodata..Lstr.9.178]29
[.rodata..Lstr.3]28
[.rodata..Lstr.8.136]28
[.rodata..Lstr.14.174]28
[.rodata..Lstr.10.139]26
[.rodata..Lstr.12]25
[.rodata..Lstr.24]25
[.rodata..Lstr.15.127]25
[.rodata..Lstr.11.135]25
[.rodata..Lstr.24.148]25
UARTPrescTable24
[.rodata..Lstr.22.133]23
[.rodata..Lstr.23.134]22
[.rodata..Lstr.15]21
[.rodata..Lstr.15.150]21
[.rodata..Lstr.11]20
[.rodata..Lstr.99]19
[.rodata..Lstr.22]19
[.rodata..Lstr.22.156]19
[.rodata..Lstr]18
[.rodata..Lstr.8]18
[.rodata..Lstr.23]18
[.rodata..Lstr.23.157]18
[.rodata..Lstr.4]17
[.rodata..Lstr.14]17
[.rodata..L.str.5]17
[.rodata..L.str.6]17
[.rodata..Lstr.104]17
[.rodata..Lswitch.table.UART_SetConfig]16
[.rodata..Lstr.13]16
[.rodata..L.str.2]16
[.rodata..L.str.3]16
[.rodata..L.str.4]16
[.rodata..Lstr.17.129]16
[.rodata..Lstr.19.131]16
[.rodata..L.str.1]14
[.rodata..Lstr.17]9
[.rodata..Lstr.17.152]9
[.rodata..L.str]9
UARTEx_SetNbDataToProcess.numerator8
UARTEx_SetNbDataToProcess.denominator8
[.rodata..Lstr.19]8
[.rodata..Lstr.19.154]8
SystemCoreClock4
uwTickPrio4
modbusData564
sys_data224
huart1148
hadc1100
hdma_adc192
hdma_usart1_rx92
hdma_usart1_tx92
htim1776
htim1676
adcData20
flash_device_parameter_default16
uwTick4
longPressCounterButtonOn4
longPressCounterButtonOff4
onTimeCounter4
offTimeCounter4
calTemperatureSensor30Value4
temp4
onTimeCounterGN4
offTimeCounterGN4
onTimeCounterRT4
offTimeCounterRT4
blinkCounter4
numberOfBlinks4
ic_overflows4
oldTimeMSTick4
msCounter4
frequency4
LVP_SM_On.lvpTimeCounter4
LVP_SM_On.oldtime4
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter4
LVP_OVP_SM_On.oldtime4
OVP_SM_On.ovpTimeCounter4
OVP_SM_On.oldtime4
autoRetryMode4
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter4
SECONDARYPROTECTION_SM_On.oldtime4
SECONDARYPROTECTION_SM_Error.retry_counter4
SECONDARYPROTECTION_SM_Error.oldTimeMSTick4
autoRetryMode.1704
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1764
SECONDARYPROTECTION_SM_On.oldtime.1754
SECONDARYPROTECTION_SM_Error.retry_counter.1814
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.1824
relais_temperature4
onTimeCounterSET4
onTimeCounterRESET4
dropLimitCounter4
voltageUin4
voltageUout4
pFlash.01
buttonState1
alarmMode1
offTime1
onTime1
blinkModeGN1
offTimeGN1
onTimeGN1
blinkModeRT1
offTimeRT1
pauseTime1
onTimeRT1
bootLoaderMark1
smState1
LVP_SM_On.lvpInput1
smState.1221
LVP_OVP_SM_On.lvpOROvpInput1
smState.1371
smState.1451
OVP_SM_On.ovpInput1
smState.1601
smState.1711
mode1
relaisState1
Total:20 9941 80681 680
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32c031xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors180
WWDG_IRQHandler2
RTC_IRQHandler2
FLASH_IRQHandler2
RCC_IRQHandler2
EXTI0_1_IRQHandler2
EXTI2_3_IRQHandler2
EXTI4_15_IRQHandler2
DMAMUX1_IRQHandler2
ADC1_IRQHandler2
TIM1_BRK_UP_TRG_COM_IRQHandler2
TIM1_CC_IRQHandler2
TIM3_IRQHandler2
TIM14_IRQHandler2
TIM17_IRQHandler2
I2C1_IRQHandler2
SPI1_IRQHandler2
USART2_IRQHandler2
Total:214
+

Module STM32C0xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler8
Total:8
+

Module fileops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
fwrite50
puts44
fputc34
putchar16
Total:144
+

Module floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_dmul_aux394
__aeabi_ddiv196
__aeabi_fmul182
__aeabi_d2iz52
__aeabi_d2uiz46
__aeabi_f2uiz36
__aeabi_ui2f30
__aeabi_i2d28
__aeabi_ui2d28
Total:992
+

Module intasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_uldivmod136
__aeabi_idiv64
__aeabi_uidiv56
__aeabi_lmul46
__aeabi_idiv06
Total:308
+

Module prinops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_putc138
vfprintf_l108
printf40
__SEGGER_RTL_prin_flush26
vfprintf26
__SEGGER_RTL_init_prin_l18
__SEGGER_RTL_stream_write16
__SEGGER_RTL_hex_uc16
__SEGGER_RTL_hex_lc16
Total:37232
+

Module __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp840
Total:840
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_X_file_stat44
__SEGGER_RTL_X_file_write10
__SEGGER_RTL_X_file_bufsize4
stdin4
stdout4
stderr4
__SEGGER_RTL_stdin_file4
__SEGGER_RTL_stdout_file4
__SEGGER_RTL_stderr_file4
Total:581212
+

Module SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SEGGER_RTT_WriteNoLock104
_WriteBlocking88
_DoInit84
_WriteNoCheck58
SEGGER_RTT_Write56
_GetAvailWriteSpace22
_DoInit._aInitStr17
[.rodata.libc..L.str]9
_acUpBuffer1 024
_SEGGER_RTT168
_acDownBuffer16
Total:412261 208
+

Module strops.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
memcmp46
strlen14
Total:60
+

Module strasmops_arm.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr20
memcpy14
Total:34
+

Module mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_ascii_mbtowc46
__SEGGER_RTL_ascii_isctype28
__SEGGER_RTL_ascii_iswctype28
__SEGGER_RTL_current_locale20
__SEGGER_RTL_ascii_wctomb16
__SEGGER_RTL_ascii_tolower14
__SEGGER_RTL_ascii_towlower14
__SEGGER_RTL_ascii_toupper12
__SEGGER_RTL_ascii_towupper12
__SEGGER_RTL_ascii_ctype_map128
__SEGGER_RTL_c_locale_data88
__SEGGER_RTL_c_locale_month_names87
__SEGGER_RTL_c_locale_day_names58
__SEGGER_RTL_c_locale_abbrev_month_names49
__SEGGER_RTL_codeset_ascii32
__SEGGER_RTL_c_locale_abbrev_day_names29
__SEGGER_RTL_c_locale_date_time_format15
__SEGGER_RTL_ascii_ctype_mask13
__SEGGER_RTL_c_locale12
__SEGGER_RTL_c_locale_date_format9
__SEGGER_RTL_c_locale_time_format9
__SEGGER_RTL_c_locale_am_pm_indicator7
[.rodata.libc..L.str]2
__SEGGER_RTL_data_utf8_period2
__SEGGER_RTL_data_empty_string1
__SEGGER_RTL_global_locale20
__SEGGER_RTL_locale_ptr4
Total:190541204
+

All modules

+ + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:24 7202 405402 904
+

SECTION DETAIL

+

Sections by address

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RangeSymbol or [section] NameSizeAlInitAcObject File
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0800020C-080005BBUSART1_IRQHandler9444CodeRXPowerPro_lto.o
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08005824-08005845fputc342CodeRXfileops.o (libc_v6m_t_le_eabi_small.a)
08005846-08005877fwrite502CodeRXfileops.o (libc_v6m_t_le_eabi_small.a)
08005878-0800592D__aeabi_fmul1822CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0800592E-08005AB7__aeabi_dmul_aux3942CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
08005AB8-08005AE5__aeabi_d2uiz462CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
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08005C62-08005C8Fmemcmp462CodeRXstrops.o (strops_v6m_t_le_eabi_small.a)
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08005E52-08005E69UARTPrescTable242CnstROPowerPro_lto.o
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08005E72-08005F35__aeabi_ddiv1962CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
08005F36-08005F69__aeabi_d2iz522CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
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08005F8E-08005FA9__aeabi_ui2d282CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
08005FAA-08005FE9__aeabi_idiv642CodeRXintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
08005FEA-08006021__aeabi_uidiv562CodeRXintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
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0800657F-080065AB[.rodata..Lstr.118]451CnstROPowerPro_lto.o
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080065C1-080065C9[.rodata..Lstr.17]91CnstROPowerPro_lto.o
080065CA-080065E2[.rodata..Lstr.24]251CnstROPowerPro_lto.o
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08006618-08006630[.rodata..Lstr.15.127]251CnstROPowerPro_lto.o
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08006694-080066A8[.rodata..Lstr.15.150]211CnstROPowerPro_lto.o
080066A9-080066B1[.rodata..Lstr.17.152]91CnstROPowerPro_lto.o
080066B2-080066CA[.rodata..Lstr.24.148]251CnstROPowerPro_lto.o
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08006762-0800676A__SEGGER_RTL_c_locale_time_format91CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0800676B-08006787__SEGGER_RTL_c_locale_abbrev_day_names291CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
08006788-080067B8__SEGGER_RTL_c_locale_abbrev_month_names491CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
080067B9-080067B9__SEGGER_RTL_data_empty_string11CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
080067BA-080067C6__SEGGER_RTL_ascii_ctype_mask131CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
080067C7-080067C7( UNUSED .=.+1 )1-------
080067C8-080067CB[.init_array]44------STM32C0xx_Startup.o
080067CC-080067D3UARTEx_SetNbDataToProcess.numerator81CnstROPowerPro_lto.o
080067D4-080067DBUARTEx_SetNbDataToProcess.denominator81CnstROPowerPro_lto.o
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08006864-08006873[.rodata..Lstr.19.131]161CnstROPowerPro_lto.o
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08006890-080068AF[.rodata..Lstr.12.138]321CnstROPowerPro_lto.o
080068B0-080068B7[.rodata..Lstr.19.154]81CnstROPowerPro_lto.o
080068B8-080068F3[.rodata..Lstr.11.179]601CnstROPowerPro_lto.o
080068F4-0800690F[.rodata..Lstr.14.174]281CnstROPowerPro_lto.o
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08006920-0800692F__SEGGER_RTL_hex_lc161CnstROprinops.o (libc_v6m_t_le_eabi_small.a)
08006930-080069AF__SEGGER_RTL_ascii_ctype_map1281CnstROmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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080069D4-08006A87__SEGGER_init_table__1804CnstRO[ Linker created ]
08006A88-08006AAF__SEGGER_init_data__404CnstRO[ Linker created ]
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08006AC2-08006AD5__SEGGER_init_copy202CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
08006AD6-1FFFFFFF( UNUSED .=.+402625834 )402 625 834-------
20000000-20000233modbusData5644ZeroZIPowerPro_lto.o
20000234-20000313sys_data2244ZeroZIPowerPro_lto.o
20000314-200003BB_SEGGER_RTT1684ZeroZISEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
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20000688-2000068BvoltageUin44ZeroZIPowerPro_lto.o
2000068C-2000068FuwTick44ZeroZIPowerPro_lto.o
20000690-20000693temp44ZeroZIPowerPro_lto.o
20000694-20000697relais_temperature44ZeroZIPowerPro_lto.o
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2000069C-2000069FonTimeCounterRT44ZeroZIPowerPro_lto.o
200006A0-200006A3onTimeCounterRESET44ZeroZIPowerPro_lto.o
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200006A8-200006ABonTimeCounter44ZeroZIPowerPro_lto.o
200006AC-200006AFoldTimeMSTick44ZeroZIPowerPro_lto.o
200006B0-200006B3offTimeCounterRT44ZeroZIPowerPro_lto.o
200006B4-200006B7offTimeCounterGN44ZeroZIPowerPro_lto.o
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200006BC-200006BFnumberOfBlinks44ZeroZIPowerPro_lto.o
200006C0-200006C3msCounter44ZeroZIPowerPro_lto.o
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200006D0-200006D3__SEGGER_RTL_stdin_file44ZeroZIprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
200006D4-200006D7__SEGGER_RTL_stderr_file44ZeroZIprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
200006D8-200006DB__SEGGER_RTL_locale_ptr44ZeroZImbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
200006DC-200006DFic_overflows44ZeroZIPowerPro_lto.o
200006E0-200006E3frequency44ZeroZIPowerPro_lto.o
200006E4-200006E7dropLimitCounter44ZeroZIPowerPro_lto.o
200006E8-200006EBcalTemperatureSensor30Value44ZeroZIPowerPro_lto.o
200006EC-200006EFblinkCounter44ZeroZIPowerPro_lto.o
200006F0-200006F3autoRetryMode.17044ZeroZIPowerPro_lto.o
200006F4-200006F7autoRetryMode44ZeroZIPowerPro_lto.o
200006F8-200006FBSECONDARYPROTECTION_SM_On.oldtime.17544ZeroZIPowerPro_lto.o
200006FC-200006FFSECONDARYPROTECTION_SM_On.oldtime44ZeroZIPowerPro_lto.o
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20000704-20000707SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter44ZeroZIPowerPro_lto.o
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20000737-20000737smState11ZeroZIPowerPro_lto.o
20000738-20000738pFlash.014ZeroZIPowerPro_lto.o
20000739-20000739mode11ZeroZIPowerPro_lto.o
2000073A-2000073AbuttonState11ZeroZIPowerPro_lto.o
2000073B-2000073B( UNUSED .=.+1 )1-------
2000073C-2000073ConTimeRT14ZeroZIPowerPro_lto.o
2000073D-2000073F( ALIGN .=.+3 )3-------
20000740-20000740onTimeGN14ZeroZIPowerPro_lto.o
20000741-20000743( ALIGN .=.+3 )3-------
20000744-20000744onTime14ZeroZIPowerPro_lto.o
20000745-20000747( ALIGN .=.+3 )3-------
20000748-20000748offTimeRT14ZeroZIPowerPro_lto.o
20000749-2000074B( ALIGN .=.+3 )3-------
2000074C-2000074CoffTimeGN14ZeroZIPowerPro_lto.o
2000074D-2000074F( ALIGN .=.+3 )3-------
20000750-20000750offTime14ZeroZIPowerPro_lto.o
20000751-20000753( ALIGN .=.+3 )3-------
20000754-20000754blinkModeRT14ZeroZIPowerPro_lto.o
20000755-20000757( ALIGN .=.+3 )3-------
20000758-20000758blinkModeGN14ZeroZIPowerPro_lto.o
20000759-2000075B( ALIGN .=.+3 )3-------
2000075C-2000075CalarmMode14ZeroZIPowerPro_lto.o
2000075D-2000075F( ALIGN .=.+3 )3-------
20000760-20000760OVP_SM_On.ovpInput14ZeroZIPowerPro_lto.o
20000761-20000763( ALIGN .=.+3 )3-------
20000764-20000764LVP_SM_On.lvpInput14ZeroZIPowerPro_lto.o
20000765-20000767( ALIGN .=.+3 )3-------
20000768-20000768LVP_OVP_SM_On.lvpOROvpInput14ZeroZIPowerPro_lto.o
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20000B79-20000B7B( UNUSED .=.+3 )3-------
20000B7C-20000B7CbootLoaderMark14NoneZIPowerPro_lto.o
20000B7D-20000B7F( ALIGN .=.+3 )3-------
20000B80-20000B93__SEGGER_RTL_global_locale204InitRWmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
20000B94-20000B97uwTickPrio44InitRWPowerPro_lto.o
20000B98-20000B9Bstdout44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B9C-20000B9Fstdin44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000BA0-20000BA3stderr44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000BA4-20000BA7SystemCoreClock44InitRWPowerPro_lto.o
20000BA8-200027FF( UNUSED .=.+7256 )7 256-------
20002800-20002FFF[.bss.block.stack]2 0488NoneZI[ Linker created ]
+

UNUSED MEMORY SUMMARY

+

Detail

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeReason
080067C7-080067C71Unused memory between sections '.rodata.libc.__SEGGER_RTL_ascii_ctype_mask' and '.init_array'
08006AD6-1FFFFFFF402 625 834Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.RAM1'
2000073B-2000073B1Unused memory between sections '.bss.buttonState' and '.bss.onTimeRT'
2000073D-2000073F3Filler between sections '.bss.onTimeRT' and '.bss.onTimeGN' as align=4
NOTE: section '.bss.onTimeRT' has size 1 that is not a multiple of its alignment 4
20000741-200007433Filler between sections '.bss.onTimeGN' and '.bss.onTime' as align=4
NOTE: section '.bss.onTimeGN' has size 1 that is not a multiple of its alignment 4
20000745-200007473Filler between sections '.bss.onTime' and '.bss.offTimeRT' as align=4
NOTE: section '.bss.onTime' has size 1 that is not a multiple of its alignment 4
20000749-2000074B3Filler between sections '.bss.offTimeRT' and '.bss.offTimeGN' as align=4
NOTE: section '.bss.offTimeRT' has size 1 that is not a multiple of its alignment 4
2000074D-2000074F3Filler between sections '.bss.offTimeGN' and '.bss.offTime' as align=4
NOTE: section '.bss.offTimeGN' has size 1 that is not a multiple of its alignment 4
20000751-200007533Filler between sections '.bss.offTime' and '.bss.blinkModeRT' as align=4
NOTE: section '.bss.offTime' has size 1 that is not a multiple of its alignment 4
20000755-200007573Filler between sections '.bss.blinkModeRT' and '.bss.blinkModeGN' as align=4
NOTE: section '.bss.blinkModeRT' has size 1 that is not a multiple of its alignment 4
20000759-2000075B3Filler between sections '.bss.blinkModeGN' and '.bss.alarmMode' as align=4
NOTE: section '.bss.blinkModeGN' has size 1 that is not a multiple of its alignment 4
2000075D-2000075F3Filler between sections '.bss.alarmMode' and '.bss.OVP_SM_On.ovpInput' as align=4
NOTE: section '.bss.alarmMode' has size 1 that is not a multiple of its alignment 4
20000761-200007633Filler between sections '.bss.OVP_SM_On.ovpInput' and '.bss.LVP_SM_On.lvpInput' as align=4
NOTE: section '.bss.OVP_SM_On.ovpInput' has size 1 that is not a multiple of its alignment 4
20000765-200007673Filler between sections '.bss.LVP_SM_On.lvpInput' and '.bss.LVP_OVP_SM_On.lvpOROvpInput' as align=4
NOTE: section '.bss.LVP_SM_On.lvpInput' has size 1 that is not a multiple of its alignment 4
20000B79-20000B7B3Unused memory between sections '.bss.libc._acDownBuffer' and '.no_init'
20000B7D-20000B7F3Filler between sections '.no_init' and '.data.libc.__SEGGER_RTL_global_locale' as align=4
NOTE: section '.no_init' has size 1 that is not a multiple of its alignment 4
20000BA8-200027FF7 256Unused memory between sections '.data.SystemCoreClock' and '.bss.block.stack'
+

INITIALIZATION TABLE

+

Constructor list

+ + + + + + + + + + + +
Table
Address		Called
Address		Called
Symbol or [section] name
0x080067C80x08000605SystemCoreClockUpdate
+

Initialize by zero

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000000-20000233564modbusData
20000234-20000313224sys_data
20000314-200003BB168_SEGGER_RTT
200003BC-2000044F148huart1
20000450-200004B3100hadc1
200004B4-2000050F92hdma_usart1_tx
20000510-2000056B92hdma_usart1_rx
2000056C-200005C792hdma_adc1
200005C8-2000061376htim17
20000614-2000065F76htim16
20000660-2000067320adcData
20000674-2000068316flash_device_parameter_default
20000684-200006874voltageUout
20000688-2000068B4voltageUin
2000068C-2000068F4uwTick
20000690-200006934temp
20000694-200006974relais_temperature
20000698-2000069B4onTimeCounterSET
2000069C-2000069F4onTimeCounterRT
200006A0-200006A34onTimeCounterRESET
200006A4-200006A74onTimeCounterGN
200006A8-200006AB4onTimeCounter
200006AC-200006AF4oldTimeMSTick
200006B0-200006B34offTimeCounterRT
200006B4-200006B74offTimeCounterGN
200006B8-200006BB4offTimeCounter
200006BC-200006BF4numberOfBlinks
200006C0-200006C34msCounter
200006C4-200006C74longPressCounterButtonOn
200006C8-200006CB4longPressCounterButtonOff
200006CC-200006CF4__SEGGER_RTL_stdout_file
200006D0-200006D34__SEGGER_RTL_stdin_file
200006D4-200006D74__SEGGER_RTL_stderr_file
200006D8-200006DB4__SEGGER_RTL_locale_ptr
200006DC-200006DF4ic_overflows
200006E0-200006E34frequency
200006E4-200006E74dropLimitCounter
200006E8-200006EB4calTemperatureSensor30Value
200006EC-200006EF4blinkCounter
200006F0-200006F34autoRetryMode.170
200006F4-200006F74autoRetryMode
200006F8-200006FB4SECONDARYPROTECTION_SM_On.oldtime.175
200006FC-200006FF4SECONDARYPROTECTION_SM_On.oldtime
20000700-200007034SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176
20000704-200007074SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
20000708-2000070B4SECONDARYPROTECTION_SM_Error.retry_counter.181
2000070C-2000070F4SECONDARYPROTECTION_SM_Error.retry_counter
20000710-200007134SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182
20000714-200007174SECONDARYPROTECTION_SM_Error.oldTimeMSTick
20000718-2000071B4OVP_SM_On.ovpTimeCounter
2000071C-2000071F4OVP_SM_On.oldtime
20000720-200007234LVP_SM_On.oldtime
20000724-200007274LVP_SM_On.lvpTimeCounter
20000728-2000072B4LVP_OVP_SM_On.oldtime
2000072C-2000072F4LVP_OVP_SM_On.lvpAndOvpInputTimeCounter
20000730-200007301relaisState
20000731-200007311smState.171
20000732-200007321smState.160
20000733-200007331smState.145
20000734-200007341pauseTime
20000735-200007351smState.137
20000736-200007361smState.122
20000737-200007371smState
20000738-200007381pFlash.0
20000739-200007391mode
2000073A-2000073A1buttonState
20000000-2000073A1 851Total (66 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000073C-2000073C1onTimeRT
2000073C-2000073C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000740-200007401onTimeGN
20000740-200007401Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000744-200007441onTime
20000744-200007441Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000748-200007481offTimeRT
20000748-200007481Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000074C-2000074C1offTimeGN
2000074C-2000074C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000750-200007501offTime
20000750-200007501Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000754-200007541blinkModeRT
20000754-200007541Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000758-200007581blinkModeGN
20000758-200007581Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000075C-2000075C1alarmMode
2000075C-2000075C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000760-200007601OVP_SM_On.ovpInput
20000760-200007601Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000764-200007641LVP_SM_On.lvpInput
20000764-200007641Total (1 sections)
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+
RangeSizeSymbol or [section] name
20000768-200007681LVP_OVP_SM_On.lvpOROvpInput
20000769-20000B681 024_acUpBuffer
20000B69-20000B7816_acDownBuffer
20000768-20000B781 041Total (3 sections)
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Summary

+
RangeSizeSymbol or [section] name
20000B80-20000B9320__SEGGER_RTL_global_locale
20000B94-20000B974uwTickPrio
20000B98-20000B9B4stdout
20000B9C-20000B9F4stdin
20000BA0-20000BA34stderr
20000BA4-20000BA74SystemCoreClock
20000B80-20000BA740Total (6 sections)
+ + + + + + + + + + + + + + + + + + + + +
DescriptionSize
Initialization table180 bytes
Source image40 bytes
Destination image2 943 bytes
Saving2 723 bytes
+

LINKER-CREATED VENEERS

+

Arm-Arm range extension veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Thumb range extension veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Arm-Thumb mode switch veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Arm mode switch veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Veneer TypeSize
Thumb-Arm mode switch0
Arm-Thumb mode switch0
Thumb-Thumb range extension0
Arm-Arm range extension0
Total:0
+

SYMBOL LIST

+

Function symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
ADC1_IRQHandler0x080058132CodeWkstm32c031xx_Vectors.o
ADC_DMAConvCplt0x08005CF71002CodeLcPowerPro_lto.o
ADC_DMAError0x08005D5B202CodeLcPowerPro_lto.o
ADC_DMAHalfConvCplt0x0800577522CodeLcPowerPro_lto.o
DMA1_Channel1_IRQHandler0x080000C5164CodeGbPowerPro_lto.o
DMA1_Channel2_3_IRQHandler0x080000D5244CodeGbPowerPro_lto.o
DMAMUX1_IRQHandler0x080058112CodeWkstm32c031xx_Vectors.o
EEPROM_ReadDeviceParameter0x080017E5364CodeLcPowerPro_lto.o
EEPROM_StoreConfig0x08001809604CodeLcPowerPro_lto.o
EEPROM_Write0x0800169D2804CodeLcPowerPro_lto.o
EEPROM_WriteDefaults0x080017B5484CodeLcPowerPro_lto.o
EXTI0_1_IRQHandler0x0800580B2CodeWkstm32c031xx_Vectors.o
EXTI2_3_IRQHandler0x0800580D2CodeWkstm32c031xx_Vectors.o
EXTI4_15_IRQHandler0x0800580F2CodeWkstm32c031xx_Vectors.o
Error_Handler0x08005E4F42CodeLcPowerPro_lto.o
FLASH_IRQHandler0x080058072CodeWkstm32c031xx_Vectors.o
FLASH_WaitForLastOperation0x08000B8D804CodeLcPowerPro_lto.o
HAL_ADC_ConfigChannel0x080006C96084CodeLcPowerPro_lto.o
HAL_DMA_IRQHandler0x08000AE91644CodeLcPowerPro_lto.o
HAL_DMA_Init0x080009452244CodeLcPowerPro_lto.o
HAL_DMA_Start_IT0x08000A251964CodeLcPowerPro_lto.o
HAL_Delay0x080006B5204CodeLcPowerPro_lto.o
HAL_FLASH_Unlock0x08000BDD324CodeLcPowerPro_lto.o
HAL_GPIO_Init0x08000BFD3804CodeLcPowerPro_lto.o
HAL_InitTick0x08000655964CodeLcPowerPro_lto.o
HAL_NVIC_SystemReset0x08005D6F42CodeLcPowerPro_lto.o
HAL_RCCEx_PeriphCLKConfig0x08000E0D2684CodeLcPowerPro_lto.o
HAL_RCC_GetPCLK1Freq0x08000DCD644CodeLcPowerPro_lto.o
HAL_RCC_GetSysClockFreq0x08000D79844CodeLcPowerPro_lto.o
HAL_TIM_Base_Init0x08000F192044CodeLcPowerPro_lto.o
HAL_TIM_IC_CaptureCallback0x080005BD564CodeLcPowerPro_lto.o
HAL_UART_ErrorCallback0x080045151684CodeLcPowerPro_lto.o
HAL_UART_Init0x080010759724CodeLcPowerPro_lto.o
HAL_UART_Receive_DMA0x080015512484CodeLcPowerPro_lto.o
HardFault_Handler0x0800576F22CodeGbPowerPro_lto.o
I2C1_IRQHandler0x0800581F2CodeWkstm32c031xx_Vectors.o
JumpToBootloader0x080044B9924CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_Exec0x080045F51 6604CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_PLUS_Exec0x08004C711 1084CodeLcPowerPro_lto.o
NMI_Handler0x0800576D22CodeGbPowerPro_lto.o
PendSV_Handler0x0800577322CodeGbPowerPro_lto.o
RCC_IRQHandler0x080058092CodeWkstm32c031xx_Vectors.o
RTC_IRQHandler0x080058052CodeWkstm32c031xx_Vectors.o
Reset_Handler0x08005E6B2CodeGbSTM32C0xx_Startup.o
SEGGER_RTT_Write0x08005665564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteNoLock0x080055FD1044CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SPI1_IRQHandler0x080058212CodeWkstm32c031xx_Vectors.o
SVC_Handler0x0800577122CodeGbPowerPro_lto.o
SysTick_Handler0x080000B5164CodeGbPowerPro_lto.o
SystemCoreClockUpdate0x08000605804CodeGbPowerPro_lto.o
SystemInit0x080005F5164CodeGbPowerPro_lto.o
TIM14_IRQHandler0x0800581B2CodeWkstm32c031xx_Vectors.o
TIM16_IRQHandler0x080000ED2884CodeGbPowerPro_lto.o
TIM17_IRQHandler0x0800581D2CodeWkstm32c031xx_Vectors.o
TIM1_BRK_UP_TRG_COM_IRQHandler0x080058152CodeWkstm32c031xx_Vectors.o
TIM1_CC_IRQHandler0x080058172CodeWkstm32c031xx_Vectors.o
TIM3_IRQHandler0x080058192CodeWkstm32c031xx_Vectors.o
TIM_Base_SetConfig0x08000FE51444CodeLcPowerPro_lto.o
UARTEx_SetNbDataToProcess0x08001649844CodeLcPowerPro_lto.o
UART_DMAAbortOnError0x08005E3F162CodeLcPowerPro_lto.o
UART_DMAError0x080057791382CodeLcPowerPro_lto.o
UART_DMAReceiveCplt0x08005D731682CodeLcPowerPro_lto.o
UART_DMARxHalfCplt0x08005E1B362CodeLcPowerPro_lto.o
UART_DMATransmitCplt0x08001501804CodeLcPowerPro_lto.o
UART_DMATxHalfCplt0x0800577722CodeLcPowerPro_lto.o
UART_EndRxTransfer0x080014A1964CodeLcPowerPro_lto.o
UART_WaitOnFlagUntilTimeout0x08001441964CodeLcPowerPro_lto.o
USART1_IRQHandler0x0800020D9444CodeGbPowerPro_lto.o
USART2_IRQHandler0x080058232CodeWkstm32c031xx_Vectors.o
WWDG_IRQHandler0x080058032CodeWkstm32c031xx_Vectors.o
_DoInit0x080055A9844CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_GetAvailWriteSpace0x08005C13222CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_WriteBlocking0x080060BF882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_WriteNoCheck0x08005C29582CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__NVIC_SystemReset0x08000929284CodeLcPowerPro_lto.o
__SEGGER_RTL_X_file_bufsize0x080060BB42CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_stat0x0800557D444CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_write0x08005C09102CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_isctype0x080056B1284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_iswctype0x080056CD284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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__SEGGER_RTL_ascii_toupper0x0800613B122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towlower0x08005CE9142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towupper0x08006147122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_wctomb0x0800612B162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_current_locale0x0800569D204CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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__SEGGER_RTL_prin_flush0x08005BC3262CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
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__SEGGER_RTL_stream_write0x080060AB162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf0x080052358404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf_int_nwp0x080052358404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_copy0x08006AC3202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_ctors0x080069B1264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_done0x0800513F4CodeGbSEGGER_THUMB_Startup.o
__SEGGER_init_zero0x08006AB1182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__aeabi_d2iz0x08005F37522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_d2uiz0x08005AB9462CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_ddiv0x08005E731962CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_dmul0x080059672CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_dmul_aux0x0800592F3942CodeLcfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_f2uiz0x08005F6B362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_fmul0x080058791822CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_i2d0x08005185224CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_idiv0x08005FAB642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_idiv00x08005B3362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_lmul0x08005B05462CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_memclr0x08006117202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr40x080061172CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr80x080061172CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy0x08005C9F2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy40x08005C9F2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy80x08005C9F2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset0x080061192CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset40x080061192CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset80x080061192CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_ui2d0x08005F8F282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_ui2f0x08005AE7302CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_uidiv0x08005FEB562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_uldivmod0x080060231362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__startup_complete0x0800513F4CodeGbSEGGER_THUMB_Startup.o
_start0x08005135144CodeGbSEGGER_THUMB_Startup.o
exit0x0800514324CodeGbSEGGER_THUMB_Startup.o
fputc0x08005825342CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
fwrite0x08005847502CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
main0x0800184511 3804CodeGbPowerPro_lto.o
mbCrc160x080045BD564CodeLcPowerPro_lto.o
memcmp0x08005C63462CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
memcpy0x08005C9F142CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
memset0x0800611F2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
printf0x0800520D404CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
putchar0x08005149164CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
puts0x08005159444CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
reset_handler0x08005E6B2CodeGbSTM32C0xx_Startup.o
strlen0x08005C91142CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
vfprintf0x08005BEF262CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
vfprintf_l0x080051A11084CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
+

Function symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
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0x080000EDTIM16_IRQHandler2884CodeGbPowerPro_lto.o
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0x080005BDHAL_TIM_IC_CaptureCallback564CodeLcPowerPro_lto.o
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0x08001845main11 3804CodeGbPowerPro_lto.o
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0x08005149putchar164CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
0x08005159puts444CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
0x08005185__aeabi_i2d224CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x080051A1vfprintf_l1084CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
0x0800520Dprintf404CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
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0x0800557D__SEGGER_RTL_X_file_stat444CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x080055A9_DoInit844CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x080055FDSEGGER_RTT_WriteNoLock1044CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x08005665SEGGER_RTT_Write564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x0800569D__SEGGER_RTL_current_locale204CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080056B1__SEGGER_RTL_ascii_isctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080056CD__SEGGER_RTL_ascii_iswctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x0800576DNMI_Handler22CodeGbPowerPro_lto.o
0x0800576FHardFault_Handler22CodeGbPowerPro_lto.o
0x08005771SVC_Handler22CodeGbPowerPro_lto.o
0x08005773PendSV_Handler22CodeGbPowerPro_lto.o
0x08005775ADC_DMAHalfConvCplt22CodeLcPowerPro_lto.o
0x08005777UART_DMATxHalfCplt22CodeLcPowerPro_lto.o
0x08005779UART_DMAError1382CodeLcPowerPro_lto.o
0x08005803WWDG_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005805RTC_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005807FLASH_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005809RCC_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x0800580BEXTI0_1_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x0800580DEXTI2_3_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x0800580FEXTI4_15_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005811DMAMUX1_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005813ADC1_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005815TIM1_BRK_UP_TRG_COM_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005817TIM1_CC_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005819TIM3_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x0800581BTIM14_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x0800581DTIM17_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x0800581FI2C1_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005821SPI1_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005823USART2_IRQHandler2CodeWkstm32c031xx_Vectors.o
0x08005825fputc342CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
0x08005847fwrite502CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
0x08005879__aeabi_fmul1822CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x0800592F__aeabi_dmul_aux3942CodeLcfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005967__aeabi_dmul2CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005AB9__aeabi_d2uiz462CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005AE7__aeabi_ui2f302CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005B05__aeabi_lmul462CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005B33__aeabi_idiv062CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005B39__SEGGER_RTL_putc1382CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
0x08005BC3__SEGGER_RTL_prin_flush262CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
0x08005BDD__SEGGER_RTL_init_prin_l182CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
0x08005BEFvfprintf262CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
0x08005C09__SEGGER_RTL_X_file_write102CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x08005C13_GetAvailWriteSpace222CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x08005C29_WriteNoCheck582CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x08005C63memcmp462CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
0x08005C91strlen142CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
0x08005C9Fmemcpy142CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08005C9F__aeabi_memcpy82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08005C9F__aeabi_memcpy42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08005C9F__aeabi_memcpy2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08005CAD__SEGGER_RTL_ascii_mbtowc462CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08005CDB__SEGGER_RTL_ascii_tolower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08005CE9__SEGGER_RTL_ascii_towlower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08005CF7ADC_DMAConvCplt1002CodeLcPowerPro_lto.o
0x08005D5BADC_DMAError202CodeLcPowerPro_lto.o
0x08005D6FHAL_NVIC_SystemReset42CodeLcPowerPro_lto.o
0x08005D73UART_DMAReceiveCplt1682CodeLcPowerPro_lto.o
0x08005E1BUART_DMARxHalfCplt362CodeLcPowerPro_lto.o
0x08005E3FUART_DMAAbortOnError162CodeLcPowerPro_lto.o
0x08005E4FError_Handler42CodeLcPowerPro_lto.o
0x08005E6Breset_handler2CodeGbSTM32C0xx_Startup.o
0x08005E6BReset_Handler2CodeGbSTM32C0xx_Startup.o
0x08005E73__aeabi_ddiv1962CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005F37__aeabi_d2iz522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005F6B__aeabi_f2uiz362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005F8F__aeabi_ui2d282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005FAB__aeabi_idiv642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005FEB__aeabi_uidiv562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08006023__aeabi_uldivmod1362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x080060AB__SEGGER_RTL_stream_write162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
0x080060BB__SEGGER_RTL_X_file_bufsize42CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x080060BF_WriteBlocking882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x08006117__aeabi_memclr82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08006117__aeabi_memclr42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08006117__aeabi_memclr202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08006119__aeabi_memset82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08006119__aeabi_memset42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08006119__aeabi_memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x0800611Fmemset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x0800612B__SEGGER_RTL_ascii_wctomb162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x0800613B__SEGGER_RTL_ascii_toupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08006147__SEGGER_RTL_ascii_towupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080069B1__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
0x08006AB1__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
0x08006AC3__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
+

Function symbols by descending size

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameSizeAlignTypeBdObject File
main11 3804CodeGbPowerPro_lto.o
MODE_SECONDARYPROTECTION_Exec1 6604CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_PLUS_Exec1 1084CodeLcPowerPro_lto.o
HAL_UART_Init9724CodeLcPowerPro_lto.o
USART1_IRQHandler9444CodeGbPowerPro_lto.o
__SEGGER_RTL_vfprintf8404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf_int_nwp8404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
HAL_ADC_ConfigChannel6084CodeLcPowerPro_lto.o
__aeabi_dmul_aux3942CodeLcfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
HAL_GPIO_Init3804CodeLcPowerPro_lto.o
TIM16_IRQHandler2884CodeGbPowerPro_lto.o
EEPROM_Write2804CodeLcPowerPro_lto.o
HAL_RCCEx_PeriphCLKConfig2684CodeLcPowerPro_lto.o
HAL_UART_Receive_DMA2484CodeLcPowerPro_lto.o
HAL_DMA_Init2244CodeLcPowerPro_lto.o
HAL_TIM_Base_Init2044CodeLcPowerPro_lto.o
HAL_DMA_Start_IT1964CodeLcPowerPro_lto.o
__aeabi_ddiv1962CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_fmul1822CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
HAL_UART_ErrorCallback1684CodeLcPowerPro_lto.o
UART_DMAReceiveCplt1682CodeLcPowerPro_lto.o
HAL_DMA_IRQHandler1644CodeLcPowerPro_lto.o
TIM_Base_SetConfig1444CodeLcPowerPro_lto.o
UART_DMAError1382CodeLcPowerPro_lto.o
__SEGGER_RTL_putc1382CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__aeabi_uldivmod1362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
vfprintf_l1084CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteNoLock1044CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
ADC_DMAConvCplt1002CodeLcPowerPro_lto.o
HAL_InitTick964CodeLcPowerPro_lto.o
UART_EndRxTransfer964CodeLcPowerPro_lto.o
UART_WaitOnFlagUntilTimeout964CodeLcPowerPro_lto.o
JumpToBootloader924CodeLcPowerPro_lto.o
_WriteBlocking882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
HAL_RCC_GetSysClockFreq844CodeLcPowerPro_lto.o
UARTEx_SetNbDataToProcess844CodeLcPowerPro_lto.o
_DoInit844CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
FLASH_WaitForLastOperation804CodeLcPowerPro_lto.o
SystemCoreClockUpdate804CodeGbPowerPro_lto.o
UART_DMATransmitCplt804CodeLcPowerPro_lto.o
HAL_RCC_GetPCLK1Freq644CodeLcPowerPro_lto.o
__aeabi_idiv642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
EEPROM_StoreConfig604CodeLcPowerPro_lto.o
_WriteNoCheck582CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
HAL_TIM_IC_CaptureCallback564CodeLcPowerPro_lto.o
SEGGER_RTT_Write564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_uidiv562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
mbCrc16564CodeLcPowerPro_lto.o
__aeabi_d2iz522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
fwrite502CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
EEPROM_WriteDefaults484CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_mbtowc462CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__aeabi_d2uiz462CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_lmul462CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
memcmp462CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_stat444CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
puts444CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
printf404CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
EEPROM_ReadDeviceParameter364CodeLcPowerPro_lto.o
UART_DMARxHalfCplt362CodeLcPowerPro_lto.o
__aeabi_f2uiz362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
fputc342CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
HAL_FLASH_Unlock324CodeLcPowerPro_lto.o
__aeabi_ui2f302CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__NVIC_SystemReset284CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_isctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_iswctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__aeabi_ui2d282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_prin_flush262CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
vfprintf262CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
DMA1_Channel2_3_IRQHandler244CodeGbPowerPro_lto.o
_GetAvailWriteSpace222CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_i2d224CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
ADC_DMAError202CodeLcPowerPro_lto.o
HAL_Delay204CodeLcPowerPro_lto.o
__SEGGER_RTL_current_locale204CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__aeabi_memclr202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_init_prin_l182CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
DMA1_Channel1_IRQHandler164CodeGbPowerPro_lto.o
SysTick_Handler164CodeGbPowerPro_lto.o
SystemInit164CodeGbPowerPro_lto.o
UART_DMAAbortOnError162CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_wctomb162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stream_write162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
putchar164CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_tolower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towlower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
_start144CodeGbSEGGER_THUMB_Startup.o
memcpy142CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
strlen142CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_toupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_write102CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_idiv062CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
Error_Handler42CodeLcPowerPro_lto.o
HAL_NVIC_SystemReset42CodeLcPowerPro_lto.o
__SEGGER_RTL_X_file_bufsize42CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
ADC_DMAHalfConvCplt22CodeLcPowerPro_lto.o
HardFault_Handler22CodeGbPowerPro_lto.o
NMI_Handler22CodeGbPowerPro_lto.o
PendSV_Handler22CodeGbPowerPro_lto.o
SVC_Handler22CodeGbPowerPro_lto.o
UART_DMATxHalfCplt22CodeLcPowerPro_lto.o
exit24CodeGbSEGGER_THUMB_Startup.o
ADC1_IRQHandler2CodeWkstm32c031xx_Vectors.o
DMAMUX1_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI0_1_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI2_3_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI4_15_IRQHandler2CodeWkstm32c031xx_Vectors.o
FLASH_IRQHandler2CodeWkstm32c031xx_Vectors.o
I2C1_IRQHandler2CodeWkstm32c031xx_Vectors.o
RCC_IRQHandler2CodeWkstm32c031xx_Vectors.o
RTC_IRQHandler2CodeWkstm32c031xx_Vectors.o
Reset_Handler2CodeGbSTM32C0xx_Startup.o
SPI1_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM14_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM17_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM1_BRK_UP_TRG_COM_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM1_CC_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM3_IRQHandler2CodeWkstm32c031xx_Vectors.o
USART2_IRQHandler2CodeWkstm32c031xx_Vectors.o
WWDG_IRQHandler2CodeWkstm32c031xx_Vectors.o
__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
__aeabi_dmul2CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_memclr42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__startup_complete4CodeGbSEGGER_THUMB_Startup.o
memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
reset_handler2CodeGbSTM32C0xx_Startup.o
+

Read-write data symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter0x2000072C44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInput0x2000076814ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.oldtime0x2000072844ZeroLcPowerPro_lto.o
LVP_SM_On.lvpInput0x2000076414ZeroLcPowerPro_lto.o
LVP_SM_On.lvpTimeCounter0x2000072444ZeroLcPowerPro_lto.o
LVP_SM_On.oldtime0x2000072044ZeroLcPowerPro_lto.o
OVP_SM_On.oldtime0x2000071C44ZeroLcPowerPro_lto.o
OVP_SM_On.ovpInput0x2000076014ZeroLcPowerPro_lto.o
OVP_SM_On.ovpTimeCounter0x2000071844ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick0x2000071444ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.1820x2000071044ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter0x2000070C44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.1810x2000070844ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter0x2000070444ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1760x2000070044ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime0x200006FC44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.1750x200006F844ZeroLcPowerPro_lto.o
SystemCoreClock0x20000BA444InitLcPowerPro_lto.o
_SEGGER_RTT0x200003141684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__RAL_global_locale0x20000B80204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_global_locale0x20000B80204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_locale_ptr0x200006D844ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_file0x200006D444ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_file0x200006D044ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdout_file0x200006CC44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBuffer0x20000B6916ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acUpBuffer0x200007691 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
adcData0x20000660204ZeroLcPowerPro_lto.o
alarmMode0x2000075C14ZeroLcPowerPro_lto.o
autoRetryMode0x200006F444ZeroLcPowerPro_lto.o
autoRetryMode.1700x200006F044ZeroLcPowerPro_lto.o
blinkCounter0x200006EC44ZeroLcPowerPro_lto.o
blinkModeGN0x2000075814ZeroLcPowerPro_lto.o
blinkModeRT0x2000075414ZeroLcPowerPro_lto.o
bootLoaderMark0x20000B7C14NoneLcPowerPro_lto.o
buttonState0x2000073A1ZeroLcPowerPro_lto.o
calTemperatureSensor30Value0x200006E844ZeroLcPowerPro_lto.o
dropLimitCounter0x200006E444ZeroLcPowerPro_lto.o
flash_device_parameter_default0x20000674164ZeroLcPowerPro_lto.o
frequency0x200006E044ZeroLcPowerPro_lto.o
hadc10x200004501004ZeroLcPowerPro_lto.o
hdma_adc10x2000056C924ZeroLcPowerPro_lto.o
hdma_usart1_rx0x20000510924ZeroLcPowerPro_lto.o
hdma_usart1_tx0x200004B4924ZeroLcPowerPro_lto.o
htim160x20000614764ZeroLcPowerPro_lto.o
htim170x200005C8764ZeroLcPowerPro_lto.o
huart10x200003BC1484ZeroLcPowerPro_lto.o
ic_overflows0x200006DC44ZeroLcPowerPro_lto.o
longPressCounterButtonOff0x200006C844ZeroLcPowerPro_lto.o
longPressCounterButtonOn0x200006C444ZeroLcPowerPro_lto.o
modbusData0x200000005644ZeroLcPowerPro_lto.o
mode0x200007391ZeroLcPowerPro_lto.o
msCounter0x200006C044ZeroLcPowerPro_lto.o
numberOfBlinks0x200006BC44ZeroLcPowerPro_lto.o
offTime0x2000075014ZeroLcPowerPro_lto.o
offTimeCounter0x200006B844ZeroLcPowerPro_lto.o
offTimeCounterGN0x200006B444ZeroLcPowerPro_lto.o
offTimeCounterRT0x200006B044ZeroLcPowerPro_lto.o
offTimeGN0x2000074C14ZeroLcPowerPro_lto.o
offTimeRT0x2000074814ZeroLcPowerPro_lto.o
oldTimeMSTick0x200006AC44ZeroLcPowerPro_lto.o
onTime0x2000074414ZeroLcPowerPro_lto.o
onTimeCounter0x200006A844ZeroLcPowerPro_lto.o
onTimeCounterGN0x200006A444ZeroLcPowerPro_lto.o
onTimeCounterRESET0x200006A044ZeroLcPowerPro_lto.o
onTimeCounterRT0x2000069C44ZeroLcPowerPro_lto.o
onTimeCounterSET0x2000069844ZeroLcPowerPro_lto.o
onTimeGN0x2000074014ZeroLcPowerPro_lto.o
onTimeRT0x2000073C14ZeroLcPowerPro_lto.o
pFlash.00x2000073814ZeroLcPowerPro_lto.o
pauseTime0x2000073414ZeroLcPowerPro_lto.o
relaisState0x2000073014ZeroLcPowerPro_lto.o
relais_temperature0x2000069444ZeroLcPowerPro_lto.o
smState0x200007371ZeroLcPowerPro_lto.o
smState.1220x200007361ZeroLcPowerPro_lto.o
smState.1370x200007351ZeroLcPowerPro_lto.o
smState.1450x200007331ZeroLcPowerPro_lto.o
smState.1600x200007321ZeroLcPowerPro_lto.o
smState.1710x200007311ZeroLcPowerPro_lto.o
stderr0x20000BA044InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdin0x20000B9C44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdout0x20000B9844InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
sys_data0x200002342244ZeroLcPowerPro_lto.o
temp0x2000069044ZeroLcPowerPro_lto.o
uwTick0x2000068C44ZeroLcPowerPro_lto.o
uwTickPrio0x20000B9444InitLcPowerPro_lto.o
voltageUin0x2000068844ZeroLcPowerPro_lto.o
voltageUout0x2000068444ZeroLcPowerPro_lto.o
+

Read-write data symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
0x20000000modbusData5644ZeroLcPowerPro_lto.o
0x20000234sys_data2244ZeroLcPowerPro_lto.o
0x20000314_SEGGER_RTT1684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200003BChuart11484ZeroLcPowerPro_lto.o
0x20000450hadc11004ZeroLcPowerPro_lto.o
0x200004B4hdma_usart1_tx924ZeroLcPowerPro_lto.o
0x20000510hdma_usart1_rx924ZeroLcPowerPro_lto.o
0x2000056Chdma_adc1924ZeroLcPowerPro_lto.o
0x200005C8htim17764ZeroLcPowerPro_lto.o
0x20000614htim16764ZeroLcPowerPro_lto.o
0x20000660adcData204ZeroLcPowerPro_lto.o
0x20000674flash_device_parameter_default164ZeroLcPowerPro_lto.o
0x20000684voltageUout44ZeroLcPowerPro_lto.o
0x20000688voltageUin44ZeroLcPowerPro_lto.o
0x2000068CuwTick44ZeroLcPowerPro_lto.o
0x20000690temp44ZeroLcPowerPro_lto.o
0x20000694relais_temperature44ZeroLcPowerPro_lto.o
0x20000698onTimeCounterSET44ZeroLcPowerPro_lto.o
0x2000069ConTimeCounterRT44ZeroLcPowerPro_lto.o
0x200006A0onTimeCounterRESET44ZeroLcPowerPro_lto.o
0x200006A4onTimeCounterGN44ZeroLcPowerPro_lto.o
0x200006A8onTimeCounter44ZeroLcPowerPro_lto.o
0x200006AColdTimeMSTick44ZeroLcPowerPro_lto.o
0x200006B0offTimeCounterRT44ZeroLcPowerPro_lto.o
0x200006B4offTimeCounterGN44ZeroLcPowerPro_lto.o
0x200006B8offTimeCounter44ZeroLcPowerPro_lto.o
0x200006BCnumberOfBlinks44ZeroLcPowerPro_lto.o
0x200006C0msCounter44ZeroLcPowerPro_lto.o
0x200006C4longPressCounterButtonOn44ZeroLcPowerPro_lto.o
0x200006C8longPressCounterButtonOff44ZeroLcPowerPro_lto.o
0x200006CC__SEGGER_RTL_stdout_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200006D0__SEGGER_RTL_stdin_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200006D4__SEGGER_RTL_stderr_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200006D8__SEGGER_RTL_locale_ptr44ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x200006DCic_overflows44ZeroLcPowerPro_lto.o
0x200006E0frequency44ZeroLcPowerPro_lto.o
0x200006E4dropLimitCounter44ZeroLcPowerPro_lto.o
0x200006E8calTemperatureSensor30Value44ZeroLcPowerPro_lto.o
0x200006ECblinkCounter44ZeroLcPowerPro_lto.o
0x200006F0autoRetryMode.17044ZeroLcPowerPro_lto.o
0x200006F4autoRetryMode44ZeroLcPowerPro_lto.o
0x200006F8SECONDARYPROTECTION_SM_On.oldtime.17544ZeroLcPowerPro_lto.o
0x200006FCSECONDARYPROTECTION_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x20000700SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.17644ZeroLcPowerPro_lto.o
0x20000704SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
0x20000708SECONDARYPROTECTION_SM_Error.retry_counter.18144ZeroLcPowerPro_lto.o
0x2000070CSECONDARYPROTECTION_SM_Error.retry_counter44ZeroLcPowerPro_lto.o
0x20000710SECONDARYPROTECTION_SM_Error.oldTimeMSTick.18244ZeroLcPowerPro_lto.o
0x20000714SECONDARYPROTECTION_SM_Error.oldTimeMSTick44ZeroLcPowerPro_lto.o
0x20000718OVP_SM_On.ovpTimeCounter44ZeroLcPowerPro_lto.o
0x2000071COVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x20000720LVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x20000724LVP_SM_On.lvpTimeCounter44ZeroLcPowerPro_lto.o
0x20000728LVP_OVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x2000072CLVP_OVP_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
0x20000730relaisState14ZeroLcPowerPro_lto.o
0x20000731smState.1711ZeroLcPowerPro_lto.o
0x20000732smState.1601ZeroLcPowerPro_lto.o
0x20000733smState.1451ZeroLcPowerPro_lto.o
0x20000734pauseTime14ZeroLcPowerPro_lto.o
0x20000735smState.1371ZeroLcPowerPro_lto.o
0x20000736smState.1221ZeroLcPowerPro_lto.o
0x20000737smState1ZeroLcPowerPro_lto.o
0x20000738pFlash.014ZeroLcPowerPro_lto.o
0x20000739mode1ZeroLcPowerPro_lto.o
0x2000073AbuttonState1ZeroLcPowerPro_lto.o
0x2000073ConTimeRT14ZeroLcPowerPro_lto.o
0x20000740onTimeGN14ZeroLcPowerPro_lto.o
0x20000744onTime14ZeroLcPowerPro_lto.o
0x20000748offTimeRT14ZeroLcPowerPro_lto.o
0x2000074CoffTimeGN14ZeroLcPowerPro_lto.o
0x20000750offTime14ZeroLcPowerPro_lto.o
0x20000754blinkModeRT14ZeroLcPowerPro_lto.o
0x20000758blinkModeGN14ZeroLcPowerPro_lto.o
0x2000075CalarmMode14ZeroLcPowerPro_lto.o
0x20000760OVP_SM_On.ovpInput14ZeroLcPowerPro_lto.o
0x20000764LVP_SM_On.lvpInput14ZeroLcPowerPro_lto.o
0x20000768LVP_OVP_SM_On.lvpOROvpInput14ZeroLcPowerPro_lto.o
0x20000769_acUpBuffer1 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000B69_acDownBuffer16ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000B7CbootLoaderMark14NoneLcPowerPro_lto.o
0x20000B80__SEGGER_RTL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x20000B80__RAL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x20000B94uwTickPrio44InitLcPowerPro_lto.o
0x20000B98stdout44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000B9Cstdin44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000BA0stderr44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000BA4SystemCoreClock44InitLcPowerPro_lto.o
+

Read-write data symbols by descending size

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameSizeAlignTypeBdObject File
_acUpBuffer1 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
modbusData5644ZeroLcPowerPro_lto.o
sys_data2244ZeroLcPowerPro_lto.o
_SEGGER_RTT1684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
huart11484ZeroLcPowerPro_lto.o
hadc11004ZeroLcPowerPro_lto.o
hdma_adc1924ZeroLcPowerPro_lto.o
hdma_usart1_rx924ZeroLcPowerPro_lto.o
hdma_usart1_tx924ZeroLcPowerPro_lto.o
htim16764ZeroLcPowerPro_lto.o
htim17764ZeroLcPowerPro_lto.o
__RAL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
adcData204ZeroLcPowerPro_lto.o
_acDownBuffer16ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
flash_device_parameter_default164ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
LVP_SM_On.lvpTimeCounter44ZeroLcPowerPro_lto.o
LVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
OVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
OVP_SM_On.ovpTimeCounter44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.18244ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.18144ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.17644ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.17544ZeroLcPowerPro_lto.o
SystemCoreClock44InitLcPowerPro_lto.o
__SEGGER_RTL_locale_ptr44ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdout_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
autoRetryMode44ZeroLcPowerPro_lto.o
autoRetryMode.17044ZeroLcPowerPro_lto.o
blinkCounter44ZeroLcPowerPro_lto.o
calTemperatureSensor30Value44ZeroLcPowerPro_lto.o
dropLimitCounter44ZeroLcPowerPro_lto.o
frequency44ZeroLcPowerPro_lto.o
ic_overflows44ZeroLcPowerPro_lto.o
longPressCounterButtonOff44ZeroLcPowerPro_lto.o
longPressCounterButtonOn44ZeroLcPowerPro_lto.o
msCounter44ZeroLcPowerPro_lto.o
numberOfBlinks44ZeroLcPowerPro_lto.o
offTimeCounter44ZeroLcPowerPro_lto.o
offTimeCounterGN44ZeroLcPowerPro_lto.o
offTimeCounterRT44ZeroLcPowerPro_lto.o
oldTimeMSTick44ZeroLcPowerPro_lto.o
onTimeCounter44ZeroLcPowerPro_lto.o
onTimeCounterGN44ZeroLcPowerPro_lto.o
onTimeCounterRESET44ZeroLcPowerPro_lto.o
onTimeCounterRT44ZeroLcPowerPro_lto.o
onTimeCounterSET44ZeroLcPowerPro_lto.o
relais_temperature44ZeroLcPowerPro_lto.o
stderr44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdin44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdout44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
temp44ZeroLcPowerPro_lto.o
uwTick44ZeroLcPowerPro_lto.o
uwTickPrio44InitLcPowerPro_lto.o
voltageUin44ZeroLcPowerPro_lto.o
voltageUout44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInput14ZeroLcPowerPro_lto.o
LVP_SM_On.lvpInput14ZeroLcPowerPro_lto.o
OVP_SM_On.ovpInput14ZeroLcPowerPro_lto.o
alarmMode14ZeroLcPowerPro_lto.o
blinkModeGN14ZeroLcPowerPro_lto.o
blinkModeRT14ZeroLcPowerPro_lto.o
bootLoaderMark14NoneLcPowerPro_lto.o
buttonState1ZeroLcPowerPro_lto.o
mode1ZeroLcPowerPro_lto.o
offTime14ZeroLcPowerPro_lto.o
offTimeGN14ZeroLcPowerPro_lto.o
offTimeRT14ZeroLcPowerPro_lto.o
onTime14ZeroLcPowerPro_lto.o
onTimeGN14ZeroLcPowerPro_lto.o
onTimeRT14ZeroLcPowerPro_lto.o
pFlash.014ZeroLcPowerPro_lto.o
pauseTime14ZeroLcPowerPro_lto.o
relaisState14ZeroLcPowerPro_lto.o
smState1ZeroLcPowerPro_lto.o
smState.1221ZeroLcPowerPro_lto.o
smState.1371ZeroLcPowerPro_lto.o
smState.1451ZeroLcPowerPro_lto.o
smState.1601ZeroLcPowerPro_lto.o
smState.1711ZeroLcPowerPro_lto.o
+

Read-only data symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
AHBPrescTable0x080050C4644CnstLcPowerPro_lto.o
APBPrescTable0x08005104324CnstLcPowerPro_lto.o
UARTEx_SetNbDataToProcess.denominator0x080067D48CnstLcPowerPro_lto.o
UARTEx_SetNbDataToProcess.numerator0x080067CC8CnstLcPowerPro_lto.o
UARTPrescTable0x08005E52242CnstLcPowerPro_lto.o
_DoInit._aInitStr0x0800673F17CnstLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_ctype_map0x08006930128CnstLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_ctype_mask0x080067BA13CnstLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale0x080056E8124CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_abbrev_day_names0x0800676B29CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_abbrev_month_names0x0800678849CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_am_pm_indicator0x080063397CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_data0x08005714884CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_date_format0x080067599CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_date_time_format0x0800634015CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_day_names0x080064D358CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_month_names0x080062E287CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_c_locale_time_format0x080067629CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_codeset_ascii0x080056F4324CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_data_empty_string0x080067B91CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_data_utf8_period0x0800650F2CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_hex_lc0x0800692016CnstGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_hex_uc0x0800691016CnstGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_data__0x08006A88[40]4CnstLc[ Linker created ]
__SEGGER_init_table__0x080069D4[180]4CnstLc[ Linker created ]
+

Read-only data symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
0x080050C4AHBPrescTable644CnstLcPowerPro_lto.o
0x08005104APBPrescTable324CnstLcPowerPro_lto.o
0x080056E8__SEGGER_RTL_c_locale124CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080056F4__SEGGER_RTL_codeset_ascii324CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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+

Untyped symbols by name

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Symbol nameValueSizeAlignTypeBdObject File
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__FLASH1_segment_size__0x00007800----Gb[ Linker created ]
__FLASH1_segment_start__0x08000000----Gb[ Linker created ]
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__RAM_segment_start__0x20000000----Gb[ Linker created ]
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__ctors_end__0x080067CC----Gb[ Linker created ]
__ctors_start__0x080067C8----Gb[ Linker created ]
__stack_end__0x20003000----Gb[ Linker created ]
__thread_pointer$0x00000000----Gb[ Linker created ]
_vectors0x08000000[180]256CodeGbstm32c031xx_Vectors.o
_vectors_end0x080000B4256CodeLcstm32c031xx_Vectors.o
+

Untyped symbols by address

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ValueSymbol nameSizeAlignTypeBdObject File
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0x00003000__RAM_segment_used_size__----Gb[ Linker created ]
0x00003000__RAM_segment_size__----Gb[ Linker created ]
0x00003000__RAM1_segment_used_size__----Gb[ Linker created ]
0x00003000__RAM1_segment_size__----Gb[ Linker created ]
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0x08000000_vectors[180]256CodeGbstm32c031xx_Vectors.o
0x08000000__FLASH_segment_used_start__----Gb[ Linker created ]
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0x080000B4_vectors_end256CodeLcstm32c031xx_Vectors.o
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0x20003000__RAM_segment_used_end__----Gb[ Linker created ]
0x20003000__RAM_segment_end__----Gb[ Linker created ]
0x20003000__RAM1_segment_used_end__----Gb[ Linker created ]
0x20003000__RAM1_segment_end__----Gb[ Linker created ]
+

REGION LIST

+

Regions by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSize
FLASH08000000-080077FF30 720
FLASH108000000-080077FF30 720
RAM20000000-20002FFF12 288
RAM120000000-20002FFF12 288
+

Analysis

+FLASH: + Identical to region FLASH1 + +FLASH1: + Identical to region FLASH + +RAM: + Identical to region RAM1 + +RAM1: + Identical to region RAM +

BLOCK LIST

+

Blocks by name

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSizeOrdering
ctors080067C8-080067CB4Auto
stack20002800-20002FFF2 048Auto
vectors08000000-080000B3180Auto
+

Blocks by address

+ + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeNameOrdering
08000000-080000B3180vectorsAuto
080067C8-080067CB4ctorsAuto
20002800-20002FFF2 048stackAuto
+

STACK SIZES

+

Functions by stack size

+ + + + + + +
Function nameStackObject File
+

Functions without stack size information

+ HAL_DMA_IRQHandler + HAL_TIM_IC_CaptureCallback + HAL_UART_ErrorCallback + UART_EndRxTransfer + UART_DMAAbortOnError + HAL_RCC_GetPCLK1Freq + HAL_InitTick + HAL_Delay + ADC_DMAConvCplt + ADC_DMAHalfConvCplt + ADC_DMAError + HAL_ADC_ConfigChannel + HAL_NVIC_SystemReset + __NVIC_SystemReset + HAL_DMA_Init + HAL_DMA_Start_IT + FLASH_WaitForLastOperation + HAL_FLASH_Unlock + HAL_GPIO_Init + HAL_RCC_GetSysClockFreq + HAL_RCCEx_PeriphCLKConfig + HAL_TIM_Base_Init + TIM_Base_SetConfig + HAL_UART_Init + UART_WaitOnFlagUntilTimeout + Error_Handler + UART_DMATransmitCplt + UART_DMATxHalfCplt + UART_DMAError + HAL_UART_Receive_DMA + UART_DMARxHalfCplt + UART_DMAReceiveCplt + UARTEx_SetNbDataToProcess + EEPROM_Write + EEPROM_WriteDefaults + EEPROM_ReadDeviceParameter + EEPROM_StoreConfig + mbCrc16 + MODE_SECONDARYPROTECTION_PLUS_Exec + MODE_SECONDARYPROTECTION_Exec + JumpToBootloader + NMI_Handler + HardFault_Handler + SVC_Handler + PendSV_Handler + SysTick_Handler + DMA1_Channel1_IRQHandler + DMA1_Channel2_3_IRQHandler + TIM16_IRQHandler + USART1_IRQHandler + SystemInit + SystemCoreClockUpdate + main + _start + __SEGGER_init_done + __startup_complete + exit + WWDG_IRQHandler + RTC_IRQHandler + FLASH_IRQHandler + RCC_IRQHandler + EXTI0_1_IRQHandler + EXTI2_3_IRQHandler + EXTI4_15_IRQHandler + DMAMUX1_IRQHandler + ADC1_IRQHandler + TIM1_BRK_UP_TRG_COM_IRQHandler + TIM1_CC_IRQHandler + TIM3_IRQHandler + TIM14_IRQHandler + TIM17_IRQHandler + I2C1_IRQHandler + SPI1_IRQHandler + USART2_IRQHandler + reset_handler + Reset_Handler + putchar + fputc + fwrite + puts + __aeabi_dmul_aux + .L__aeabi_d2uiz_fast_entry + __aeabi_fmul + __aeabi_dmul + __aeabi_ddiv + __aeabi_d2iz + __aeabi_f2uiz + __aeabi_d2uiz + __aeabi_i2d + __aeabi_ui2f + __aeabi_ui2d + __aeabi_lmul + __aeabi_idiv + __aeabi_idiv0 + __aeabi_uidiv + __aeabi_uldivmod + __SEGGER_RTL_stream_write + __SEGGER_RTL_putc + __SEGGER_RTL_prin_flush + __SEGGER_RTL_init_prin_l + vfprintf + vfprintf_l + printf + __SEGGER_RTL_vfprintf_int_nwp + __SEGGER_init_zero + __SEGGER_init_copy + __SEGGER_init_ctors + __SEGGER_RTL_X_file_stat + __SEGGER_RTL_X_file_bufsize + __SEGGER_RTL_X_file_write + _DoInit + _GetAvailWriteSpace + _WriteNoCheck + _WriteBlocking + SEGGER_RTT_WriteNoLock + SEGGER_RTT_Write + memcmp + strlen + memcpy + __aeabi_memcpy + __aeabi_memcpy4 + __aeabi_memcpy8 + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset + __SEGGER_RTL_ascii_isctype + __SEGGER_RTL_ascii_toupper + __SEGGER_RTL_ascii_tolower + __SEGGER_RTL_ascii_iswctype + __SEGGER_RTL_ascii_towupper + __SEGGER_RTL_ascii_towlower + __SEGGER_RTL_current_locale + __SEGGER_RTL_ascii_mbtowc + __SEGGER_RTL_ascii_wctomb + __SEGGER_RTL_vfprintf +

UNUSED INPUTS

+

Unused object files

+No unused object files +

ABSOLUTE LISTING

+

Section .vectors from stm32c031xx_Vectors.o, size=180, align=256

+
+
_vectors:
+  0x08000000:  20003000     DC.W       20003000               ; R_ARM_ABS32
+  0x08000004:  08005E6B     DC.W       reset_handler
+  0x08000008:  0800576D     DC.W       NMI_Handler
+  0x0800000C:  0800576F     DC.W       HardFault_Handler
+  0x08000010:  00           DC.B       0x00                     ; '\0'
+  0x08000011:  00           DC.B       0x00                     ; '\0'
+  0x08000012:  00           DC.B       0x00                     ; '\0'
+  0x08000013:  00           DC.B       0x00                     ; '\0'
+  0x08000014:  00           DC.B       0x00                     ; '\0'
+  0x08000015:  00           DC.B       0x00                     ; '\0'
+  0x08000016:  00           DC.B       0x00                     ; '\0'
+  0x08000017:  00           DC.B       0x00                     ; '\0'
+  0x08000018:  00           DC.B       0x00                     ; '\0'
+  0x08000019:  00           DC.B       0x00                     ; '\0'
+  0x0800001A:  00           DC.B       0x00                     ; '\0'
+  0x0800001B:  00           DC.B       0x00                     ; '\0'
+  0x0800001C:  00           DC.B       0x00                     ; '\0'
+  0x0800001D:  00           DC.B       0x00                     ; '\0'
+  0x0800001E:  00           DC.B       0x00                     ; '\0'
+  0x0800001F:  00           DC.B       0x00                     ; '\0'
+  0x08000020:  00           DC.B       0x00                     ; '\0'
+  0x08000021:  00           DC.B       0x00                     ; '\0'
+  0x08000022:  00           DC.B       0x00                     ; '\0'
+  0x08000023:  00           DC.B       0x00                     ; '\0'
+  0x08000024:  00           DC.B       0x00                     ; '\0'
+  0x08000025:  00           DC.B       0x00                     ; '\0'
+  0x08000026:  00           DC.B       0x00                     ; '\0'
+  0x08000027:  00           DC.B       0x00                     ; '\0'
+  0x08000028:  00           DC.B       0x00                     ; '\0'
+  0x08000029:  00           DC.B       0x00                     ; '\0'
+  0x0800002A:  00           DC.B       0x00                     ; '\0'
+  0x0800002B:  00           DC.B       0x00                     ; '\0'
+  0x0800002C:  08005771     DC.W       SVC_Handler
+  0x08000030:  00           DC.B       0x00                     ; '\0'
+  0x08000031:  00           DC.B       0x00                     ; '\0'
+  0x08000032:  00           DC.B       0x00                     ; '\0'
+  0x08000033:  00           DC.B       0x00                     ; '\0'
+  0x08000034:  00           DC.B       0x00                     ; '\0'
+  0x08000035:  00           DC.B       0x00                     ; '\0'
+  0x08000036:  00           DC.B       0x00                     ; '\0'
+  0x08000037:  00           DC.B       0x00                     ; '\0'
+  0x08000038:  08005773     DC.W       PendSV_Handler
+  0x0800003C:  080000B5     DC.W       SysTick_Handler
+  0x08000040:  08005803     DC.W       WWDG_IRQHandler
+  0x08000044:  00           DC.B       0x00                     ; '\0'
+  0x08000045:  00           DC.B       0x00                     ; '\0'
+  0x08000046:  00           DC.B       0x00                     ; '\0'
+  0x08000047:  00           DC.B       0x00                     ; '\0'
+  0x08000048:  08005805     DC.W       RTC_IRQHandler
+  0x0800004C:  08005807     DC.W       FLASH_IRQHandler
+  0x08000050:  08005809     DC.W       RCC_IRQHandler
+  0x08000054:  0800580B     DC.W       EXTI0_1_IRQHandler
+  0x08000058:  0800580D     DC.W       EXTI2_3_IRQHandler
+  0x0800005C:  0800580F     DC.W       EXTI4_15_IRQHandler
+  0x08000060:  00           DC.B       0x00                     ; '\0'
+  0x08000061:  00           DC.B       0x00                     ; '\0'
+  0x08000062:  00           DC.B       0x00                     ; '\0'
+  0x08000063:  00           DC.B       0x00                     ; '\0'
+  0x08000064:  080000C5     DC.W       DMA1_Channel1_IRQHandler
+  0x08000068:  080000D5     DC.W       DMA1_Channel2_3_IRQHandler
+  0x0800006C:  08005811     DC.W       DMAMUX1_IRQHandler
+  0x08000070:  08005813     DC.W       ADC1_IRQHandler
+  0x08000074:  08005815     DC.W       TIM1_BRK_UP_TRG_COM_IRQHandler
+  0x08000078:  08005817     DC.W       TIM1_CC_IRQHandler
+  0x0800007C:  00           DC.B       0x00                     ; '\0'
+  0x0800007D:  00           DC.B       0x00                     ; '\0'
+  0x0800007E:  00           DC.B       0x00                     ; '\0'
+  0x0800007F:  00           DC.B       0x00                     ; '\0'
+  0x08000080:  08005819     DC.W       TIM3_IRQHandler
+  0x08000084:  00           DC.B       0x00                     ; '\0'
+  0x08000085:  00           DC.B       0x00                     ; '\0'
+  0x08000086:  00           DC.B       0x00                     ; '\0'
+  0x08000087:  00           DC.B       0x00                     ; '\0'
+  0x08000088:  00           DC.B       0x00                     ; '\0'
+  0x08000089:  00           DC.B       0x00                     ; '\0'
+  0x0800008A:  00           DC.B       0x00                     ; '\0'
+  0x0800008B:  00           DC.B       0x00                     ; '\0'
+  0x0800008C:  0800581B     DC.W       TIM14_IRQHandler
+  0x08000090:  00           DC.B       0x00                     ; '\0'
+  0x08000091:  00           DC.B       0x00                     ; '\0'
+  0x08000092:  00           DC.B       0x00                     ; '\0'
+  0x08000093:  00           DC.B       0x00                     ; '\0'
+  0x08000094:  080000ED     DC.W       TIM16_IRQHandler
+  0x08000098:  0800581D     DC.W       TIM17_IRQHandler
+  0x0800009C:  0800581F     DC.W       I2C1_IRQHandler
+  0x080000A0:  00           DC.B       0x00                     ; '\0'
+  0x080000A1:  00           DC.B       0x00                     ; '\0'
+  0x080000A2:  00           DC.B       0x00                     ; '\0'
+  0x080000A3:  00           DC.B       0x00                     ; '\0'
+  0x080000A4:  08005821     DC.W       SPI1_IRQHandler
+  0x080000A8:  00           DC.B       0x00                     ; '\0'
+  0x080000A9:  00           DC.B       0x00                     ; '\0'
+  0x080000AA:  00           DC.B       0x00                     ; '\0'
+  0x080000AB:  00           DC.B       0x00                     ; '\0'
+  0x080000AC:  0800020D     DC.W       USART1_IRQHandler
+  0x080000B0:  08005823     DC.W       USART2_IRQHandler
+
+

Section .text.SysTick_Handler from PowerPro_lto.o, size=16, align=4

+
+
SysTick_Handler:
+_vectors_end:
+  0x080000B4:  4802         LDR        R0, =uwTick              ; [PC, #8] [0x080000C0] =0x2000068C 
+  0x080000B6:  6801         LDR        R1, [R0]
+  0x080000B8:  1C49         ADDS       R1, R1, #1
+  0x080000BA:  6001         STR        R1, [R0]
+  0x080000BC:  4770         BX         LR
+  0x080000BE:  46C0         NOP
+  0x080000C0:  2000068C     DC.W       uwTick
+
+

Section .text.DMA1_Channel1_IRQHandler from PowerPro_lto.o, size=16, align=4

+
+
DMA1_Channel1_IRQHandler:
+  0x080000C4:  B580         PUSH       {R7, LR}
+  0x080000C6:  4802         LDR        R0, =hdma_adc1           ; [PC, #8] [0x080000D0] =0x2000056C 
+  0x080000C8:  F000 FD0E    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000CC:  BD80         POP        {R7, PC}
+  0x080000CE:  46C0         NOP
+  0x080000D0:  2000056C     DC.W       hdma_adc1
+
+

Section .text.DMA1_Channel2_3_IRQHandler from PowerPro_lto.o, size=24, align=4

+
+
DMA1_Channel2_3_IRQHandler:
+  0x080000D4:  B580         PUSH       {R7, LR}
+  0x080000D6:  4803         LDR        R0, =hdma_usart1_rx      ; [PC, #12] [0x080000E4] =0x20000510 
+  0x080000D8:  F000 FD06    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000DC:  4802         LDR        R0, =hdma_usart1_tx      ; [PC, #8] [0x080000E8] =0x200004B4 
+  0x080000DE:  F000 FD03    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000E2:  BD80         POP        {R7, PC}
+  0x080000E4:  20000510     DC.W       hdma_usart1_rx
+  0x080000E8:  200004B4     DC.W       hdma_usart1_tx
+
+

Section .text.TIM16_IRQHandler from PowerPro_lto.o, size=288, align=4

+
+
TIM16_IRQHandler:
+  0x080000EC:  B5F0         PUSH       {R4-R7, LR}
+  0x080000EE:  B081         SUB        SP, SP, #4
+  0x080000F0:  4C40         LDR        R4, =htim16              ; [PC, #0x0100] [0x080001F4] =0x20000614 
+  0x080000F2:  6820         LDR        R0, [R4]
+  0x080000F4:  68C6         LDR        R6, [R0, #12]
+  0x080000F6:  6907         LDR        R7, [R0, #16]
+  0x080000F8:  07B9         LSLS       R1, R7, #30
+  0x080000FA:  4D3F         LDR        R5, =0xFFFFFEFF          ; [PC, #252] [0x080001F8] 
+  0x080000FC:  D50E         BPL        .L2                      ; 0x0800011C
+  0x080000FE:  07B1         LSLS       R1, R6, #30
+  0x08000100:  D50C         BPL        .L2                      ; 0x0800011C
+  0x08000102:  4629         MOV        R1, R5
+  0x08000104:  31FE         ADDS       R1, #254
+  0x08000106:  6101         STR        R1, [R0, #16]
+  0x08000108:  2101         MOVS       R1, #1
+  0x0800010A:  7721         STRB       R1, [R4, #28]
+  0x0800010C:  6980         LDR        R0, [R0, #24]
+  0x0800010E:  0780         LSLS       R0, R0, #30
+  0x08000110:  D002         BEQ        .L1                      ; 0x08000118
+  0x08000112:  4620         MOV        R0, R4
+  0x08000114:  F000 FA52    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L1:
+  0x08000118:  2000         MOVS       R0, #0
+  0x0800011A:  7720         STRB       R0, [R4, #28]
+
.L2:
+  0x0800011C:  0778         LSLS       R0, R7, #29
+  0x0800011E:  D510         BPL        .L4                      ; 0x08000142
+  0x08000120:  0770         LSLS       R0, R6, #29
+  0x08000122:  D50E         BPL        .L4                      ; 0x08000142
+  0x08000124:  6820         LDR        R0, [R4]
+  0x08000126:  4629         MOV        R1, R5
+  0x08000128:  31FC         ADDS       R1, #252
+  0x0800012A:  6101         STR        R1, [R0, #16]
+  0x0800012C:  2102         MOVS       R1, #2
+  0x0800012E:  7721         STRB       R1, [R4, #28]
+  0x08000130:  6980         LDR        R0, [R0, #24]
+  0x08000132:  0580         LSLS       R0, R0, #22
+  0x08000134:  0F80         LSRS       R0, R0, #30
+  0x08000136:  D002         BEQ        .L3                      ; 0x0800013E
+  0x08000138:  4620         MOV        R0, R4
+  0x0800013A:  F000 FA3F    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L3:
+  0x0800013E:  2000         MOVS       R0, #0
+  0x08000140:  7720         STRB       R0, [R4, #28]
+
.L4:
+  0x08000142:  0738         LSLS       R0, R7, #28
+  0x08000144:  D50F         BPL        .L6                      ; 0x08000166
+  0x08000146:  0730         LSLS       R0, R6, #28
+  0x08000148:  D50D         BPL        .L6                      ; 0x08000166
+  0x0800014A:  6820         LDR        R0, [R4]
+  0x0800014C:  4629         MOV        R1, R5
+  0x0800014E:  31F8         ADDS       R1, #248
+  0x08000150:  6101         STR        R1, [R0, #16]
+  0x08000152:  2104         MOVS       R1, #4
+  0x08000154:  7721         STRB       R1, [R4, #28]
+  0x08000156:  69C0         LDR        R0, [R0, #28]
+  0x08000158:  0780         LSLS       R0, R0, #30
+  0x0800015A:  D002         BEQ        .L5                      ; 0x08000162
+  0x0800015C:  4620         MOV        R0, R4
+  0x0800015E:  F000 FA2D    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L5:
+  0x08000162:  2000         MOVS       R0, #0
+  0x08000164:  7720         STRB       R0, [R4, #28]
+
.L6:
+  0x08000166:  06F8         LSLS       R0, R7, #27
+  0x08000168:  D510         BPL        .L8                      ; 0x0800018C
+  0x0800016A:  06F0         LSLS       R0, R6, #27
+  0x0800016C:  D50E         BPL        .L8                      ; 0x0800018C
+  0x0800016E:  6820         LDR        R0, [R4]
+  0x08000170:  4629         MOV        R1, R5
+  0x08000172:  31F0         ADDS       R1, #240
+  0x08000174:  6101         STR        R1, [R0, #16]
+  0x08000176:  2108         MOVS       R1, #8
+  0x08000178:  7721         STRB       R1, [R4, #28]
+  0x0800017A:  69C0         LDR        R0, [R0, #28]
+  0x0800017C:  0580         LSLS       R0, R0, #22
+  0x0800017E:  0F80         LSRS       R0, R0, #30
+  0x08000180:  D002         BEQ        .L7                      ; 0x08000188
+  0x08000182:  4620         MOV        R0, R4
+  0x08000184:  F000 FA1A    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L7:
+  0x08000188:  2000         MOVS       R0, #0
+  0x0800018A:  7720         STRB       R0, [R4, #28]
+
.L8:
+  0x0800018C:  07F8         LSLS       R0, R7, #31
+  0x0800018E:  D010         BEQ        .L9                      ; 0x080001B2
+  0x08000190:  07F0         LSLS       R0, R6, #31
+  0x08000192:  D00E         BEQ        .L9                      ; 0x080001B2
+  0x08000194:  6820         LDR        R0, [R4]
+  0x08000196:  4629         MOV        R1, R5
+  0x08000198:  31FF         ADDS       R1, #255
+  0x0800019A:  6101         STR        R1, [R0, #16]
+  0x0800019C:  4917         LDR        R1, =0x40014400          ; [PC, #92] [0x080001FC] 
+  0x0800019E:  4288         CMP        R0, R1
+  0x080001A0:  D107         BNE        .L9                      ; 0x080001B2
+  0x080001A2:  4817         LDR        R0, =ic_overflows        ; [PC, #92] [0x08000200] =0x200006DC 
+  0x080001A4:  6801         LDR        R1, [R0]
+  0x080001A6:  1C49         ADDS       R1, R1, #1
+  0x080001A8:  6001         STR        R1, [R0]
+  0x080001AA:  D202         BCS        .L9                      ; 0x080001B2
+  0x080001AC:  4815         LDR        R0, =frequency           ; [PC, #84] [0x08000204] =0x200006E0 
+  0x080001AE:  2100         MOVS       R1, #0
+  0x080001B0:  6001         STR        R1, [R0]
+
.L9:
+  0x080001B2:  2041         MOVS       R0, #65
+  0x080001B4:  01C0         LSLS       R0, R0, #7
+  0x080001B6:  4207         TST        R7, R0
+  0x080001B8:  D004         BEQ        .L10                     ; 0x080001C4
+  0x080001BA:  0630         LSLS       R0, R6, #24
+  0x080001BC:  D502         BPL        .L10                     ; 0x080001C4
+  0x080001BE:  6820         LDR        R0, [R4]
+  0x080001C0:  4911         LDR        R1, =0xFFFFDF7F          ; [PC, #68] [0x08000208] 
+  0x080001C2:  6101         STR        R1, [R0, #16]
+
.L10:
+  0x080001C4:  05F8         LSLS       R0, R7, #23
+  0x080001C6:  D503         BPL        .L11                     ; 0x080001D0
+  0x080001C8:  0630         LSLS       R0, R6, #24
+  0x080001CA:  D501         BPL        .L11                     ; 0x080001D0
+  0x080001CC:  6820         LDR        R0, [R4]
+  0x080001CE:  6105         STR        R5, [R0, #16]
+
.L11:
+  0x080001D0:  0678         LSLS       R0, R7, #25
+  0x080001D2:  D505         BPL        .L12                     ; 0x080001E0
+  0x080001D4:  0670         LSLS       R0, R6, #25
+  0x080001D6:  D503         BPL        .L12                     ; 0x080001E0
+  0x080001D8:  6820         LDR        R0, [R4]
+  0x080001DA:  4629         MOV        R1, R5
+  0x080001DC:  31C0         ADDS       R1, #192
+  0x080001DE:  6101         STR        R1, [R0, #16]
+
.L12:
+  0x080001E0:  06B8         LSLS       R0, R7, #26
+  0x080001E2:  D504         BPL        .L13                     ; 0x080001EE
+  0x080001E4:  06B0         LSLS       R0, R6, #26
+  0x080001E6:  D502         BPL        .L13                     ; 0x080001EE
+  0x080001E8:  6820         LDR        R0, [R4]
+  0x080001EA:  35E0         ADDS       R5, #224
+  0x080001EC:  6105         STR        R5, [R0, #16]
+
.L13:
+  0x080001EE:  B001         ADD        SP, SP, #4
+  0x080001F0:  BDF0         POP        {R4-R7, PC}
+  0x080001F2:  46C0         NOP
+  0x080001F4:  20000614     DC.W       htim16
+  0x080001F8:  FFFFFEFF     DC.W       0xFFFFFEFF
+  0x080001FC:  40014400     DC.W       0x40014400
+  0x08000200:  200006DC     DC.W       ic_overflows
+  0x08000204:  200006E0     DC.W       frequency
+  0x08000208:  FFFFDF7F     DC.W       0xFFFFDF7F
+
+

Section .text.USART1_IRQHandler from PowerPro_lto.o, size=944, align=4

+
+
USART1_IRQHandler:
+  0x0800020C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800020E:  B085         SUB        SP, SP, #20
+  0x08000210:  4CE3         LDR        R4, =huart1              ; [PC, #0x038C] [0x080005A0] =0x200003BC 
+  0x08000212:  2101         MOVS       R1, #1
+  0x08000214:  6820         LDR        R0, [R4]
+  0x08000216:  9104         STR        R1, [SP, #16]
+  0x08000218:  02CE         LSLS       R6, R1, #11
+  0x0800021A:  69C3         LDR        R3, [R0, #28]
+  0x0800021C:  4631         MOV        R1, R6
+  0x0800021E:  310F         ADDS       R1, #15
+  0x08000220:  420B         TST        R3, R1
+  0x08000222:  6801         LDR        R1, [R0]
+  0x08000224:  6882         LDR        R2, [R0, #8]
+  0x08000226:  D067         BEQ        .L7                      ; 0x080002F8
+  0x08000228:  9603         STR        R6, [SP, #12]
+  0x0800022A:  4FDE         LDR        R7, =0x04000120          ; [PC, #0x0378] [0x080005A4] 
+  0x0800022C:  400F         ANDS       R7, R1
+  0x0800022E:  9D04         LDR        R5, [SP, #16]
+  0x08000230:  072E         LSLS       R6, R5, #28
+  0x08000232:  9602         STR        R6, [SP, #8]
+  0x08000234:  1C76         ADDS       R6, R6, #1
+  0x08000236:  4016         ANDS       R6, R2
+  0x08000238:  19F7         ADDS       R7, R6, R7
+  0x0800023A:  D066         BEQ        .L8                      ; 0x0800030A
+  0x0800023C:  07DF         LSLS       R7, R3, #31
+  0x0800023E:  D009         BEQ        .L1                      ; 0x08000254
+  0x08000240:  05CF         LSLS       R7, R1, #23
+  0x08000242:  D507         BPL        .L1                      ; 0x08000254
+  0x08000244:  6205         STR        R5, [R0, #32]
+  0x08000246:  2590         MOVS       R5, #144
+  0x08000248:  9501         STR        R5, [SP, #4]
+  0x0800024A:  5967         LDR        R7, [R4, R5]
+  0x0800024C:  9D04         LDR        R5, [SP, #16]
+  0x0800024E:  432F         ORRS       R7, R5
+  0x08000250:  9D01         LDR        R5, [SP, #4]
+  0x08000252:  5167         STR        R7, [R4, R5]
+
.L1:
+  0x08000254:  079F         LSLS       R7, R3, #30
+  0x08000256:  D50A         BPL        .L2                      ; 0x0800026E
+  0x08000258:  07D7         LSLS       R7, R2, #31
+  0x0800025A:  D008         BEQ        .L2                      ; 0x0800026E
+  0x0800025C:  2702         MOVS       R7, #2
+  0x0800025E:  6207         STR        R7, [R0, #32]
+  0x08000260:  2790         MOVS       R7, #144
+  0x08000262:  9701         STR        R7, [SP, #4]
+  0x08000264:  59E5         LDR        R5, [R4, R7]
+  0x08000266:  2704         MOVS       R7, #4
+  0x08000268:  432F         ORRS       R7, R5
+  0x0800026A:  9D01         LDR        R5, [SP, #4]
+  0x0800026C:  5167         STR        R7, [R4, R5]
+
.L2:
+  0x0800026E:  075F         LSLS       R7, R3, #29
+  0x08000270:  D50B         BPL        .L3                      ; 0x0800028A
+  0x08000272:  07D7         LSLS       R7, R2, #31
+  0x08000274:  D009         BEQ        .L3                      ; 0x0800028A
+  0x08000276:  2704         MOVS       R7, #4
+  0x08000278:  6207         STR        R7, [R0, #32]
+  0x0800027A:  2590         MOVS       R5, #144
+  0x0800027C:  9500         STR        R5, [SP, #0]
+  0x0800027E:  5965         LDR        R5, [R4, R5]
+  0x08000280:  9501         STR        R5, [SP, #4]
+  0x08000282:  2702         MOVS       R7, #2
+  0x08000284:  432F         ORRS       R7, R5
+  0x08000286:  9D00         LDR        R5, [SP, #0]
+  0x08000288:  5167         STR        R7, [R4, R5]
+
.L3:
+  0x0800028A:  071F         LSLS       R7, R3, #28
+  0x0800028C:  D509         BPL        .L4                      ; 0x080002A2
+  0x0800028E:  2720         MOVS       R7, #32
+  0x08000290:  400F         ANDS       R7, R1
+  0x08000292:  433E         ORRS       R6, R7
+  0x08000294:  D005         BEQ        .L4                      ; 0x080002A2
+  0x08000296:  2508         MOVS       R5, #8
+  0x08000298:  6205         STR        R5, [R0, #32]
+  0x0800029A:  2790         MOVS       R7, #144
+  0x0800029C:  59E6         LDR        R6, [R4, R7]
+  0x0800029E:  432E         ORRS       R6, R5
+  0x080002A0:  51E6         STR        R6, [R4, R7]
+
.L4:
+  0x080002A2:  9F03         LDR        R7, [SP, #12]
+  0x080002A4:  423B         TST        R3, R7
+  0x080002A6:  D007         BEQ        .L5                      ; 0x080002B8
+  0x080002A8:  014E         LSLS       R6, R1, #5
+  0x080002AA:  D505         BPL        .L5                      ; 0x080002B8
+  0x080002AC:  6207         STR        R7, [R0, #32]
+  0x080002AE:  2690         MOVS       R6, #144
+  0x080002B0:  59A5         LDR        R5, [R4, R6]
+  0x080002B2:  2720         MOVS       R7, #32
+  0x080002B4:  432F         ORRS       R7, R5
+  0x080002B6:  51A7         STR        R7, [R4, R6]
+
.L5:
+  0x080002B8:  2690         MOVS       R6, #144
+  0x080002BA:  59A7         LDR        R7, [R4, R6]
+  0x080002BC:  2F00         CMP        R7, #0
+  0x080002BE:  D065         BEQ        .L17                     ; 0x0800038C
+  0x080002C0:  069B         LSLS       R3, R3, #26
+  0x080002C2:  D50B         BPL        .L6                      ; 0x080002DC
+  0x080002C4:  2320         MOVS       R3, #32
+  0x080002C6:  4019         ANDS       R1, R3
+  0x080002C8:  9B02         LDR        R3, [SP, #8]
+  0x080002CA:  401A         ANDS       R2, R3
+  0x080002CC:  430A         ORRS       R2, R1
+  0x080002CE:  D005         BEQ        .L6                      ; 0x080002DC
+  0x080002D0:  6F61         LDR        R1, [R4, #116]
+  0x080002D2:  2900         CMP        R1, #0
+  0x080002D4:  D002         BEQ        .L6                      ; 0x080002DC
+  0x080002D6:  4620         MOV        R0, R4
+  0x080002D8:  4788         BLX        R1
+  0x080002DA:  6820         LDR        R0, [R4]
+
.L6:
+  0x080002DC:  59A1         LDR        R1, [R4, R6]
+  0x080002DE:  2228         MOVS       R2, #40
+  0x080002E0:  400A         ANDS       R2, R1
+  0x080002E2:  6880         LDR        R0, [R0, #8]
+  0x080002E4:  2740         MOVS       R7, #64
+  0x080002E6:  4038         ANDS       R0, R7
+  0x080002E8:  1880         ADDS       R0, R0, R2
+  0x080002EA:  4620         MOV        R0, R4
+  0x080002EC:  D13D         BNE        .L13                     ; 0x0800036A
+  0x080002EE:  F004 F911    BL         HAL_UART_ErrorCallback   ; 0x08004514
+  0x080002F2:  2000         MOVS       R0, #0
+  0x080002F4:  51A0         STR        R0, [R4, R6]
+  0x080002F6:  E049         B          .L17                     ; 0x0800038C
+
.L7:
+  0x080002F8:  069E         LSLS       R6, R3, #26
+  0x080002FA:  D506         BPL        .L8                      ; 0x0800030A
+  0x080002FC:  2620         MOVS       R6, #32
+  0x080002FE:  400E         ANDS       R6, R1
+  0x08000300:  9D04         LDR        R5, [SP, #16]
+  0x08000302:  072F         LSLS       R7, R5, #28
+  0x08000304:  4017         ANDS       R7, R2
+  0x08000306:  19F6         ADDS       R6, R6, R7
+  0x08000308:  D13B         BNE        .L15                     ; 0x08000382
+
.L8:
+  0x0800030A:  6EE6         LDR        R6, [R4, #108]
+  0x0800030C:  2E01         CMP        R6, #1
+  0x0800030E:  D103         BNE        .L9                      ; 0x08000318
+  0x08000310:  06DE         LSLS       R6, R3, #27
+  0x08000312:  D501         BPL        .L9                      ; 0x08000318
+  0x08000314:  06CE         LSLS       R6, R1, #27
+  0x08000316:  D43B         BMI        .L18                     ; 0x08000390
+
.L9:
+  0x08000318:  02DE         LSLS       R6, R3, #11
+  0x0800031A:  D501         BPL        .L10                     ; 0x08000320
+  0x0800031C:  0256         LSLS       R6, R2, #9
+  0x0800031E:  D420         BMI        .L12                     ; 0x08000362
+
.L10:
+  0x08000320:  0618         LSLS       R0, R3, #24
+  0x08000322:  D506         BPL        .L11                     ; 0x08000332
+  0x08000324:  2080         MOVS       R0, #128
+  0x08000326:  4008         ANDS       R0, R1
+  0x08000328:  9D04         LDR        R5, [SP, #16]
+  0x0800032A:  05EE         LSLS       R6, R5, #23
+  0x0800032C:  4032         ANDS       R2, R6
+  0x0800032E:  1880         ADDS       R0, R0, R2
+  0x08000330:  D125         BNE        .L14                     ; 0x0800037E
+
.L11:
+  0x08000332:  0658         LSLS       R0, R3, #25
+  0x08000334:  D52A         BPL        .L17                     ; 0x0800038C
+  0x08000336:  0648         LSLS       R0, R1, #25
+  0x08000338:  D528         BPL        .L17                     ; 0x0800038C
+  0x0800033A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800033E:  9904         LDR        R1, [SP, #16]
+  0x08000340:  F381 8810    MSR        PRIMASK, R1
+  0x08000344:  6821         LDR        R1, [R4]
+  0x08000346:  680A         LDR        R2, [R1]
+  0x08000348:  2340         MOVS       R3, #64
+  0x0800034A:  439A         BICS       R2, R3
+  0x0800034C:  600A         STR        R2, [R1]
+  0x0800034E:  F380 8810    MSR        PRIMASK, R0
+  0x08000352:  2088         MOVS       R0, #136
+  0x08000354:  2120         MOVS       R1, #32
+  0x08000356:  5021         STR        R1, [R4, R0]
+  0x08000358:  4897         LDR        R0, =0x20000026          ; [PC, #0x025C] [0x080005B8] 
+  0x0800035A:  2100         MOVS       R1, #0
+  0x0800035C:  7001         STRB       R1, [R0]
+  0x0800035E:  67A1         STR        R1, [R4, #120]
+  0x08000360:  E014         B          .L17                     ; 0x0800038C
+
.L12:
+  0x08000362:  9904         LDR        R1, [SP, #16]
+  0x08000364:  0509         LSLS       R1, R1, #20
+  0x08000366:  6201         STR        R1, [R0, #32]
+  0x08000368:  E010         B          .L17                     ; 0x0800038C
+
.L13:
+  0x0800036A:  F001 F899    BL         UART_EndRxTransfer       ; 0x080014A0
+  0x0800036E:  6820         LDR        R0, [R4]
+  0x08000370:  6880         LDR        R0, [R0, #8]
+  0x08000372:  0640         LSLS       R0, R0, #25
+  0x08000374:  D446         BMI        .L21                     ; 0x08000404
+  0x08000376:  4620         MOV        R0, R4
+  0x08000378:  F004 F8CC    BL         HAL_UART_ErrorCallback   ; 0x08004514
+  0x0800037C:  E006         B          .L17                     ; 0x0800038C
+
.L14:
+  0x0800037E:  6FA1         LDR        R1, [R4, #120]
+  0x08000380:  E000         B          .L16                     ; 0x08000384
+
.L15:
+  0x08000382:  6F61         LDR        R1, [R4, #116]
+
.L16:
+  0x08000384:  2900         CMP        R1, #0
+  0x08000386:  D001         BEQ        .L17                     ; 0x0800038C
+  0x08000388:  4620         MOV        R0, R4
+  0x0800038A:  4788         BLX        R1
+
.L17:
+  0x0800038C:  B005         ADD        SP, SP, #20
+  0x0800038E:  BDF0         POP        {R4-R7, PC}
+
.L18:
+  0x08000390:  2110         MOVS       R1, #16
+  0x08000392:  6201         STR        R1, [R0, #32]
+  0x08000394:  6880         LDR        R0, [R0, #8]
+  0x08000396:  0640         LSLS       R0, R0, #25
+  0x08000398:  D500         BPL        .L19                     ; 0x0800039C
+  0x0800039A:  E076         B          .L25                     ; 0x0800048A
+
.L19:
+  0x0800039C:  235E         MOVS       R3, #94
+  0x0800039E:  5AE0         LDRH       R0, [R4, R3]
+  0x080003A0:  225C         MOVS       R2, #92
+  0x080003A2:  5AA2         LDRH       R2, [R4, R2]
+  0x080003A4:  5AE3         LDRH       R3, [R4, R3]
+  0x080003A6:  2B00         CMP        R3, #0
+  0x080003A8:  D0F0         BEQ        .L17                     ; 0x0800038C
+  0x080003AA:  4282         CMP        R2, R0
+  0x080003AC:  D0EE         BEQ        .L17                     ; 0x0800038C
+  0x080003AE:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003B2:  9D04         LDR        R5, [SP, #16]
+  0x080003B4:  F385 8810    MSR        PRIMASK, R5
+  0x080003B8:  4A7C         LDR        R2, =0xFFFFFEFF          ; [PC, #0x01F0] [0x080005AC] 
+  0x080003BA:  3A20         SUBS       R2, #32
+  0x080003BC:  6823         LDR        R3, [R4]
+  0x080003BE:  681E         LDR        R6, [R3]
+  0x080003C0:  4016         ANDS       R6, R2
+  0x080003C2:  601E         STR        R6, [R3]
+  0x080003C4:  F380 8810    MSR        PRIMASK, R0
+  0x080003C8:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003CC:  F385 8810    MSR        PRIMASK, R5
+  0x080003D0:  6822         LDR        R2, [R4]
+  0x080003D2:  6893         LDR        R3, [R2, #8]
+  0x080003D4:  4E77         LDR        R6, =0xEFFFFFFE          ; [PC, #0x01DC] [0x080005B4] 
+  0x080003D6:  401E         ANDS       R6, R3
+  0x080003D8:  6096         STR        R6, [R2, #8]
+  0x080003DA:  F380 8810    MSR        PRIMASK, R0
+  0x080003DE:  208C         MOVS       R0, #140
+  0x080003E0:  2220         MOVS       R2, #32
+  0x080003E2:  5022         STR        R2, [R4, R0]
+  0x080003E4:  2000         MOVS       R0, #0
+  0x080003E6:  6760         STR        R0, [R4, #116]
+  0x080003E8:  66E0         STR        R0, [R4, #108]
+  0x080003EA:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003EE:  F385 8810    MSR        PRIMASK, R5
+  0x080003F2:  6822         LDR        R2, [R4]
+  0x080003F4:  6813         LDR        R3, [R2]
+  0x080003F6:  438B         BICS       R3, R1
+  0x080003F8:  6013         STR        R3, [R2]
+  0x080003FA:  F380 8810    MSR        PRIMASK, R0
+
.L20:
+  0x080003FE:  2002         MOVS       R0, #2
+  0x08000400:  6720         STR        R0, [R4, #112]
+  0x08000402:  E7C3         B          .L17                     ; 0x0800038C
+
.L21:
+  0x08000404:  F3EF 8010    MRS        R0, PRIMASK
+  0x08000408:  9904         LDR        R1, [SP, #16]
+  0x0800040A:  F381 8810    MSR        PRIMASK, R1
+  0x0800040E:  6821         LDR        R1, [R4]
+  0x08000410:  688A         LDR        R2, [R1, #8]
+  0x08000412:  43BA         BICS       R2, R7
+  0x08000414:  608A         STR        R2, [R1, #8]
+  0x08000416:  F380 8810    MSR        PRIMASK, R0
+  0x0800041A:  2080         MOVS       R0, #128
+  0x0800041C:  5820         LDR        R0, [R4, R0]
+  0x0800041E:  2800         CMP        R0, #0
+  0x08000420:  D100         BNE        .L22                     ; 0x08000424
+  0x08000422:  E0AC         B          .L31                     ; 0x0800057E
+
.L22:
+  0x08000424:  4601         MOV        R1, R0
+  0x08000426:  3124         ADDS       R1, #36
+  0x08000428:  9A04         LDR        R2, [SP, #16]
+  0x0800042A:  700A         STRB       R2, [R1]
+  0x0800042C:  4A5E         LDR        R2, =UART_DMAAbortOnError ; [PC, #0x0178] [0x080005A8] =0x08005E3F 
+  0x0800042E:  6382         STR        R2, [R0, #56]
+  0x08000430:  784A         LDRB       R2, [R1, #1]
+  0x08000432:  2A02         CMP        R2, #2
+  0x08000434:  D000         BEQ        .L23                     ; 0x08000438
+  0x08000436:  E0A6         B          .L32                     ; 0x08000586
+
.L23:
+  0x08000438:  6802         LDR        R2, [R0]
+  0x0800043A:  6813         LDR        R3, [R2]
+  0x0800043C:  240E         MOVS       R4, #14
+  0x0800043E:  43A3         BICS       R3, R4
+  0x08000440:  6013         STR        R3, [R2]
+  0x08000442:  6813         LDR        R3, [R2]
+  0x08000444:  9D04         LDR        R5, [SP, #16]
+  0x08000446:  43AB         BICS       R3, R5
+  0x08000448:  6013         STR        R3, [R2]
+  0x0800044A:  6C43         LDR        R3, [R0, #68]
+  0x0800044C:  681C         LDR        R4, [R3]
+  0x0800044E:  4A57         LDR        R2, =0xFFFFFEFF          ; [PC, #0x015C] [0x080005AC] 
+  0x08000450:  4014         ANDS       R4, R2
+  0x08000452:  601C         STR        R4, [R3]
+  0x08000454:  6C03         LDR        R3, [R0, #64]
+  0x08000456:  241C         MOVS       R4, #28
+  0x08000458:  401C         ANDS       R4, R3
+  0x0800045A:  462B         MOV        R3, R5
+  0x0800045C:  40A3         LSLS       R3, R4
+  0x0800045E:  4C54         LDR        R4, =0x40020004          ; [PC, #0x0150] [0x080005B0] 
+  0x08000460:  6826         LDR        R6, [R4]
+  0x08000462:  431E         ORRS       R6, R3
+  0x08000464:  6026         STR        R6, [R4]
+  0x08000466:  6C83         LDR        R3, [R0, #72]
+  0x08000468:  6CC4         LDR        R4, [R0, #76]
+  0x0800046A:  605C         STR        R4, [R3, #4]
+  0x0800046C:  6D03         LDR        R3, [R0, #80]
+  0x0800046E:  2B00         CMP        R3, #0
+  0x08000470:  D005         BEQ        .L24                     ; 0x0800047E
+  0x08000472:  681C         LDR        R4, [R3]
+  0x08000474:  4014         ANDS       R4, R2
+  0x08000476:  601C         STR        R4, [R3]
+  0x08000478:  6D42         LDR        R2, [R0, #84]
+  0x0800047A:  6D83         LDR        R3, [R0, #88]
+  0x0800047C:  6053         STR        R3, [R2, #4]
+
.L24:
+  0x0800047E:  2200         MOVS       R2, #0
+  0x08000480:  700A         STRB       R2, [R1]
+  0x08000482:  704D         STRB       R5, [R1, #1]
+  0x08000484:  F005 FCDB    BL         UART_DMAAbortOnError     ; 0x08005E3E
+  0x08000488:  E780         B          .L17                     ; 0x0800038C
+
.L25:
+  0x0800048A:  205C         MOVS       R0, #92
+  0x0800048C:  5A20         LDRH       R0, [R4, R0]
+  0x0800048E:  2680         MOVS       R6, #128
+  0x08000490:  59A2         LDR        R2, [R4, R6]
+  0x08000492:  6812         LDR        R2, [R2]
+  0x08000494:  6853         LDR        R3, [R2, #4]
+  0x08000496:  B29F         UXTH       R7, R3
+  0x08000498:  2F00         CMP        R7, #0
+  0x0800049A:  D068         BEQ        .L28                     ; 0x0800056E
+  0x0800049C:  4287         CMP        R7, R0
+  0x0800049E:  D266         BCS        .L28                     ; 0x0800056E
+  0x080004A0:  275E         MOVS       R7, #94
+  0x080004A2:  53E3         STRH       R3, [R4, R7]
+  0x080004A4:  6812         LDR        R2, [R2]
+  0x080004A6:  0692         LSLS       R2, R2, #26
+  0x080004A8:  D500         BPL        .L26                     ; 0x080004AC
+  0x080004AA:  E074         B          .L35                     ; 0x08000596
+
.L26:
+  0x080004AC:  F3EF 8310    MRS        R3, PRIMASK
+  0x080004B0:  9D04         LDR        R5, [SP, #16]
+  0x080004B2:  F385 8810    MSR        PRIMASK, R5
+  0x080004B6:  9703         STR        R7, [SP, #12]
+  0x080004B8:  6827         LDR        R7, [R4]
+  0x080004BA:  683A         LDR        R2, [R7]
+  0x080004BC:  483B         LDR        R0, =0xFFFFFEFF          ; [PC, #236] [0x080005AC] 
+  0x080004BE:  4002         ANDS       R2, R0
+  0x080004C0:  603A         STR        R2, [R7]
+  0x080004C2:  F383 8810    MSR        PRIMASK, R3
+  0x080004C6:  F3EF 8210    MRS        R2, PRIMASK
+  0x080004CA:  F385 8810    MSR        PRIMASK, R5
+  0x080004CE:  6823         LDR        R3, [R4]
+  0x080004D0:  689F         LDR        R7, [R3, #8]
+  0x080004D2:  43AF         BICS       R7, R5
+  0x080004D4:  609F         STR        R7, [R3, #8]
+  0x080004D6:  F382 8810    MSR        PRIMASK, R2
+  0x080004DA:  F3EF 8210    MRS        R2, PRIMASK
+  0x080004DE:  F385 8810    MSR        PRIMASK, R5
+  0x080004E2:  6823         LDR        R3, [R4]
+  0x080004E4:  689F         LDR        R7, [R3, #8]
+  0x080004E6:  2040         MOVS       R0, #64
+  0x080004E8:  4387         BICS       R7, R0
+  0x080004EA:  609F         STR        R7, [R3, #8]
+  0x080004EC:  F382 8810    MSR        PRIMASK, R2
+  0x080004F0:  208C         MOVS       R0, #140
+  0x080004F2:  2220         MOVS       R2, #32
+  0x080004F4:  5022         STR        R2, [R4, R0]
+  0x080004F6:  2300         MOVS       R3, #0
+  0x080004F8:  66E3         STR        R3, [R4, #108]
+  0x080004FA:  F3EF 8010    MRS        R0, PRIMASK
+  0x080004FE:  F385 8810    MSR        PRIMASK, R5
+  0x08000502:  6822         LDR        R2, [R4]
+  0x08000504:  6817         LDR        R7, [R2]
+  0x08000506:  438F         BICS       R7, R1
+  0x08000508:  6017         STR        R7, [R2]
+  0x0800050A:  9F03         LDR        R7, [SP, #12]
+  0x0800050C:  F380 8810    MSR        PRIMASK, R0
+  0x08000510:  59A6         LDR        R6, [R4, R6]
+  0x08000512:  2E00         CMP        R6, #0
+  0x08000514:  D03F         BEQ        .L35                     ; 0x08000596
+  0x08000516:  4631         MOV        R1, R6
+  0x08000518:  3124         ADDS       R1, #36
+  0x0800051A:  7848         LDRB       R0, [R1, #1]
+  0x0800051C:  2802         CMP        R0, #2
+  0x0800051E:  D137         BNE        .L33                     ; 0x08000590
+  0x08000520:  9302         STR        R3, [SP, #8]
+  0x08000522:  6830         LDR        R0, [R6]
+  0x08000524:  6802         LDR        R2, [R0]
+  0x08000526:  270E         MOVS       R7, #14
+  0x08000528:  43BA         BICS       R2, R7
+  0x0800052A:  6002         STR        R2, [R0]
+  0x0800052C:  6C72         LDR        R2, [R6, #68]
+  0x0800052E:  6817         LDR        R7, [R2]
+  0x08000530:  4B1E         LDR        R3, =0xFFFFFEFF          ; [PC, #120] [0x080005AC] 
+  0x08000532:  401F         ANDS       R7, R3
+  0x08000534:  6017         STR        R7, [R2]
+  0x08000536:  6802         LDR        R2, [R0]
+  0x08000538:  43AA         BICS       R2, R5
+  0x0800053A:  6002         STR        R2, [R0]
+  0x0800053C:  6C30         LDR        R0, [R6, #64]
+  0x0800053E:  221C         MOVS       R2, #28
+  0x08000540:  4002         ANDS       R2, R0
+  0x08000542:  4628         MOV        R0, R5
+  0x08000544:  4090         LSLS       R0, R2
+  0x08000546:  4A1A         LDR        R2, =0x40020004          ; [PC, #104] [0x080005B0] 
+  0x08000548:  6817         LDR        R7, [R2]
+  0x0800054A:  4307         ORRS       R7, R0
+  0x0800054C:  6017         STR        R7, [R2]
+  0x0800054E:  6CB0         LDR        R0, [R6, #72]
+  0x08000550:  6CF2         LDR        R2, [R6, #76]
+  0x08000552:  6042         STR        R2, [R0, #4]
+  0x08000554:  6D37         LDR        R7, [R6, #80]
+  0x08000556:  2F00         CMP        R7, #0
+  0x08000558:  D005         BEQ        .L27                     ; 0x08000566
+  0x0800055A:  6838         LDR        R0, [R7]
+  0x0800055C:  4018         ANDS       R0, R3
+  0x0800055E:  6038         STR        R0, [R7]
+  0x08000560:  6D70         LDR        R0, [R6, #84]
+  0x08000562:  6DB2         LDR        R2, [R6, #88]
+  0x08000564:  6042         STR        R2, [R0, #4]
+
.L27:
+  0x08000566:  704D         STRB       R5, [R1, #1]
+  0x08000568:  9F03         LDR        R7, [SP, #12]
+  0x0800056A:  9B02         LDR        R3, [SP, #8]
+  0x0800056C:  E012         B          .L34                     ; 0x08000594
+
.L28:
+  0x0800056E:  42B8         CMP        R0, R7
+  0x08000570:  D000         BEQ        .L29                     ; 0x08000574
+  0x08000572:  E70B         B          .L17                     ; 0x0800038C
+
.L29:
+  0x08000574:  6810         LDR        R0, [R2]
+  0x08000576:  0680         LSLS       R0, R0, #26
+  0x08000578:  D400         BMI        .L30                     ; 0x0800057C
+  0x0800057A:  E707         B          .L17                     ; 0x0800038C
+
.L30:
+  0x0800057C:  E73F         B          .L20                     ; 0x080003FE
+
.L31:
+  0x0800057E:  4808         LDR        R0, =huart1              ; [PC, #32] [0x080005A0] =0x200003BC 
+  0x08000580:  F003 FFC8    BL         HAL_UART_ErrorCallback   ; 0x08004514
+  0x08000584:  E702         B          .L17                     ; 0x0800038C
+
.L32:
+  0x08000586:  2104         MOVS       R1, #4
+  0x08000588:  63C1         STR        R1, [R0, #60]
+  0x0800058A:  F005 FC58    BL         UART_DMAAbortOnError     ; 0x08005E3E
+  0x0800058E:  E6FD         B          .L17                     ; 0x0800038C
+
.L33:
+  0x08000590:  2004         MOVS       R0, #4
+  0x08000592:  63F0         STR        R0, [R6, #60]
+
.L34:
+  0x08000594:  700B         STRB       R3, [R1]
+
.L35:
+  0x08000596:  2002         MOVS       R0, #2
+  0x08000598:  6720         STR        R0, [R4, #112]
+  0x0800059A:  5BE0         LDRH       R0, [R4, R7]
+  0x0800059C:  E6F6         B          .L17                     ; 0x0800038C
+  0x0800059E:  46C0         NOP
+  0x080005A0:  200003BC     DC.W       huart1
+  0x080005A4:  04000120     DC.W       0x04000120
+  0x080005A8:  08005E3F     DC.W       UART_DMAAbortOnError
+  0x080005AC:  FFFFFEFF     DC.W       0xFFFFFEFF
+  0x080005B0:  40020004     DC.W       0x40020004
+  0x080005B4:  EFFFFFFE     DC.W       0xEFFFFFFE
+  0x080005B8:  20000026     DC.W       20000026               ; R_ARM_ABS32
+
+

Section .text.HAL_TIM_IC_CaptureCallback from PowerPro_lto.o, size=56, align=4

+
+
HAL_TIM_IC_CaptureCallback:
+  0x080005BC:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080005BE:  4605         MOV        R5, R0
+  0x080005C0:  7F00         LDRB       R0, [R0, #28]
+  0x080005C2:  2801         CMP        R0, #1
+  0x080005C4:  D111         BNE        .L1                      ; 0x080005EA
+  0x080005C6:  6828         LDR        R0, [R5]
+  0x080005C8:  6B44         LDR        R4, [R0, #52]
+  0x080005CA:  F000 FBFF    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x080005CE:  4907         LDR        R1, =ic_overflows        ; [PC, #28] [0x080005EC] =0x200006DC 
+  0x080005D0:  2200         MOVS       R2, #0
+  0x080005D2:  600A         STR        R2, [R1]
+  0x080005D4:  6829         LDR        R1, [R5]
+  0x080005D6:  6A8B         LDR        R3, [R1, #40]
+  0x080005D8:  624A         STR        R2, [R1, #36]
+  0x080005DA:  1C59         ADDS       R1, R3, #1
+  0x080005DC:  F005 FD05    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080005E0:  4621         MOV        R1, R4
+  0x080005E2:  F005 FD02    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080005E6:  4902         LDR        R1, =frequency           ; [PC, #8] [0x080005F0] =0x200006E0 
+  0x080005E8:  6008         STR        R0, [R1]
+
.L1:
+  0x080005EA:  BDB0         POP        {R4-R5, R7, PC}
+  0x080005EC:  200006DC     DC.W       ic_overflows
+  0x080005F0:  200006E0     DC.W       frequency
+
+

Section .text.SystemInit from PowerPro_lto.o, size=16, align=4

+
+
SystemInit:
+  0x080005F4:  2001         MOVS       R0, #1
+  0x080005F6:  06C0         LSLS       R0, R0, #27
+  0x080005F8:  4901         LDR        R1, =0xE000ED08          ; [PC, #4] [0x08000600] 
+  0x080005FA:  6008         STR        R0, [R1]
+  0x080005FC:  4770         BX         LR
+  0x080005FE:  46C0         NOP
+  0x08000600:  E000ED08     DC.W       0xE000ED08
+
+

Section .text.SystemCoreClockUpdate from PowerPro_lto.o, size=80, align=4

+
+
SystemCoreClockUpdate:
+  0x08000604:  490F         LDR        R1, =0x40021000          ; [PC, #60] [0x08000644] 
+  0x08000606:  6888         LDR        R0, [R1, #8]
+  0x08000608:  0680         LSLS       R0, R0, #26
+  0x0800060A:  0F42         LSRS       R2, R0, #29
+  0x0800060C:  480E         LDR        R0, =0x02DC6C00          ; [PC, #56] [0x08000648] 
+  0x0800060E:  2A01         CMP        R2, #1
+  0x08000610:  D00D         BEQ        .L3                      ; 0x0800062E
+  0x08000612:  2A04         CMP        R2, #4
+  0x08000614:  D004         BEQ        .L1                      ; 0x08000620
+  0x08000616:  2A03         CMP        R2, #3
+  0x08000618:  D105         BNE        .L2                      ; 0x08000626
+  0x0800061A:  207D         MOVS       R0, #125
+  0x0800061C:  0200         LSLS       R0, R0, #8
+  0x0800061E:  E006         B          .L3                      ; 0x0800062E
+
.L1:
+  0x08000620:  2001         MOVS       R0, #1
+  0x08000622:  03C0         LSLS       R0, R0, #15
+  0x08000624:  E003         B          .L3                      ; 0x0800062E
+
.L2:
+  0x08000626:  680A         LDR        R2, [R1]
+  0x08000628:  0492         LSLS       R2, R2, #18
+  0x0800062A:  0F52         LSRS       R2, R2, #29
+  0x0800062C:  40D0         LSRS       R0, R2
+
.L3:
+  0x0800062E:  4A07         LDR        R2, =SystemCoreClock     ; [PC, #28] [0x0800064C] =0x20000BA4 
+  0x08000630:  6010         STR        R0, [R2]
+  0x08000632:  6889         LDR        R1, [R1, #8]
+  0x08000634:  0989         LSRS       R1, R1, #6
+  0x08000636:  233C         MOVS       R3, #60
+  0x08000638:  400B         ANDS       R3, R1
+  0x0800063A:  4905         LDR        R1, =AHBPrescTable       ; [PC, #20] [0x08000650] =0x080050C4 
+  0x0800063C:  58C9         LDR        R1, [R1, R3]
+  0x0800063E:  40C8         LSRS       R0, R1
+  0x08000640:  6010         STR        R0, [R2]
+  0x08000642:  4770         BX         LR
+  0x08000644:  40021000     DC.W       0x40021000
+  0x08000648:  02DC6C00     DC.W       0x02DC6C00
+  0x0800064C:  20000BA4     DC.W       SystemCoreClock
+  0x08000650:  080050C4     DC.W       AHBPrescTable
+
+

Section .text.HAL_InitTick from PowerPro_lto.o, size=96, align=4

+
+
HAL_InitTick:
+  0x08000654:  B5F0         PUSH       {R4-R7, LR}
+  0x08000656:  B081         SUB        SP, SP, #4
+  0x08000658:  4604         MOV        R4, R0
+  0x0800065A:  4811         LDR        R0, =SystemCoreClock     ; [PC, #68] [0x080006A0] =0x20000BA4 
+  0x0800065C:  6800         LDR        R0, [R0]
+  0x0800065E:  217D         MOVS       R1, #125
+  0x08000660:  00C9         LSLS       R1, R1, #3
+  0x08000662:  F005 FCC2    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08000666:  1E42         SUBS       R2, R0, #1
+  0x08000668:  2001         MOVS       R0, #1
+  0x0800066A:  0E11         LSRS       R1, R2, #24
+  0x0800066C:  D116         BNE        .L1                      ; 0x0800069C
+  0x0800066E:  490D         LDR        R1, =0x00FFFFFF          ; [PC, #52] [0x080006A4] 
+  0x08000670:  4E0D         LDR        R6, =0xE000E010          ; [PC, #52] [0x080006A8] 
+  0x08000672:  6072         STR        R2, [R6, #4]
+  0x08000674:  4A0D         LDR        R2, =0xE000ED20          ; [PC, #52] [0x080006AC] 
+  0x08000676:  6813         LDR        R3, [R2]
+  0x08000678:  400B         ANDS       R3, R1
+  0x0800067A:  2503         MOVS       R5, #3
+  0x0800067C:  07AD         LSLS       R5, R5, #30
+  0x0800067E:  195B         ADDS       R3, R3, R5
+  0x08000680:  6013         STR        R3, [R2]
+  0x08000682:  2300         MOVS       R3, #0
+  0x08000684:  60B3         STR        R3, [R6, #8]
+  0x08000686:  2707         MOVS       R7, #7
+  0x08000688:  6037         STR        R7, [R6]
+  0x0800068A:  2C03         CMP        R4, #3
+  0x0800068C:  D806         BHI        .L1                      ; 0x0800069C
+  0x0800068E:  6810         LDR        R0, [R2]
+  0x08000690:  4008         ANDS       R0, R1
+  0x08000692:  4328         ORRS       R0, R5
+  0x08000694:  6010         STR        R0, [R2]
+  0x08000696:  4806         LDR        R0, =uwTickPrio          ; [PC, #24] [0x080006B0] =0x20000B94 
+  0x08000698:  6004         STR        R4, [R0]
+  0x0800069A:  2000         MOVS       R0, #0
+
.L1:
+  0x0800069C:  B001         ADD        SP, SP, #4
+  0x0800069E:  BDF0         POP        {R4-R7, PC}
+  0x080006A0:  20000BA4     DC.W       SystemCoreClock
+  0x080006A4:  00FFFFFF     DC.W       0x00FFFFFF
+  0x080006A8:  E000E010     DC.W       0xE000E010
+  0x080006AC:  E000ED20     DC.W       0xE000ED20
+  0x080006B0:  20000B94     DC.W       uwTickPrio
+
+

Section .text.HAL_Delay from PowerPro_lto.o, size=20, align=4

+
+
HAL_Delay:
+  0x080006B4:  4903         LDR        R1, =uwTick              ; [PC, #12] [0x080006C4] =0x2000068C 
+  0x080006B6:  680A         LDR        R2, [R1]
+
.L1:
+  0x080006B8:  680B         LDR        R3, [R1]
+  0x080006BA:  1A9B         SUBS       R3, R3, R2
+  0x080006BC:  4283         CMP        R3, R0
+  0x080006BE:  D9FB         BLS        .L1                      ; 0x080006B8
+  0x080006C0:  4770         BX         LR
+  0x080006C2:  46C0         NOP
+  0x080006C4:  2000068C     DC.W       uwTick
+
+

Section .text.HAL_ADC_ConfigChannel from PowerPro_lto.o, size=608, align=4

+
+
HAL_ADC_ConfigChannel:
+  0x080006C8:  B5F0         PUSH       {R4-R7, LR}
+  0x080006CA:  B089         SUB        SP, SP, #36
+  0x080006CC:  2500         MOVS       R5, #0
+  0x080006CE:  9508         STR        R5, [SP, #32]
+  0x080006D0:  2654         MOVS       R6, #84
+  0x080006D2:  4F8C         LDR        R7, =hadc1               ; [PC, #0x0230] [0x08000904] =0x20000450 
+  0x080006D4:  5DB9         LDRB       R1, [R7, R6]
+  0x080006D6:  2901         CMP        R1, #1
+  0x080006D8:  D101         BNE        .L1                      ; 0x080006DE
+  0x080006DA:  2402         MOVS       R4, #2
+  0x080006DC:  E102         B          .L38                     ; 0x080008E4
+
.L1:
+  0x080006DE:  2401         MOVS       R4, #1
+  0x080006E0:  55BC         STRB       R4, [R7, R6]
+  0x080006E2:  6839         LDR        R1, [R7]
+  0x080006E4:  688A         LDR        R2, [R1, #8]
+  0x080006E6:  0752         LSLS       R2, R2, #29
+  0x080006E8:  D422         BMI        .L5                      ; 0x08000730
+  0x080006EA:  9507         STR        R5, [SP, #28]
+  0x080006EC:  693B         LDR        R3, [R7, #16]
+  0x080006EE:  6844         LDR        R4, [R0, #4]
+  0x080006F0:  2C02         CMP        R4, #2
+  0x080006F2:  4D86         LDR        R5, =0x80000004          ; [PC, #0x0218] [0x0800090C] 
+  0x080006F4:  D121         BNE        .L6                      ; 0x0800073A
+  0x080006F6:  2204         MOVS       R2, #4
+  0x080006F8:  4313         ORRS       R3, R2
+  0x080006FA:  42AB         CMP        R3, R5
+  0x080006FC:  6802         LDR        R2, [R0]
+  0x080006FE:  D106         BNE        .L2                      ; 0x0800070E
+  0x08000700:  4881         LDR        R0, =0x007FFFFF          ; [PC, #0x0204] [0x08000908] 
+  0x08000702:  43C0         MVNS       R0, R0
+  0x08000704:  43D3         MVNS       R3, R2
+  0x08000706:  4303         ORRS       R3, R0
+  0x08000708:  6A88         LDR        R0, [R1, #40]
+  0x0800070A:  4018         ANDS       R0, R3
+  0x0800070C:  6288         STR        R0, [R1, #40]
+
.L2:
+  0x0800070E:  9D07         LDR        R5, [SP, #28]
+  0x08000710:  2400         MOVS       R4, #0
+  0x08000712:  2A00         CMP        R2, #0
+  0x08000714:  D400         BMI        .L3                      ; 0x08000718
+  0x08000716:  E0E4         B          .L37                     ; 0x080008E2
+
.L3:
+  0x08000718:  487E         LDR        R0, =0x40012708          ; [PC, #0x01F8] [0x08000914] 
+  0x0800071A:  6801         LDR        R1, [R0]
+  0x0800071C:  4B7F         LDR        R3, =0xA8000400          ; [PC, #0x01FC] [0x0800091C] 
+  0x0800071E:  429A         CMP        R2, R3
+  0x08000720:  D064         BEQ        .L14                     ; 0x080007EC
+  0x08000722:  4B7D         LDR        R3, =0xA4000200          ; [PC, #0x01F4] [0x08000918] 
+  0x08000724:  429A         CMP        R2, R3
+  0x08000726:  D000         BEQ        .L4                      ; 0x0800072A
+  0x08000728:  E0DB         B          .L37                     ; 0x080008E2
+
.L4:
+  0x0800072A:  2201         MOVS       R2, #1
+  0x0800072C:  0592         LSLS       R2, R2, #22
+  0x0800072E:  E05F         B          .L15                     ; 0x080007F0
+
.L5:
+  0x08000730:  6DB8         LDR        R0, [R7, #88]
+  0x08000732:  2120         MOVS       R1, #32
+  0x08000734:  4301         ORRS       R1, R0
+  0x08000736:  65B9         STR        R1, [R7, #88]
+  0x08000738:  E0D3         B          .L37                     ; 0x080008E2
+
.L6:
+  0x0800073A:  2204         MOVS       R2, #4
+  0x0800073C:  4313         ORRS       R3, R2
+  0x0800073E:  42AB         CMP        R3, R5
+  0x08000740:  4D71         LDR        R5, =0x007FFFFF          ; [PC, #0x01C4] [0x08000908] 
+  0x08000742:  6803         LDR        R3, [R0]
+  0x08000744:  D105         BNE        .L7                      ; 0x08000752
+  0x08000746:  461A         MOV        R2, R3
+  0x08000748:  402A         ANDS       R2, R5
+  0x0800074A:  6A8C         LDR        R4, [R1, #40]
+  0x0800074C:  4314         ORRS       R4, R2
+  0x0800074E:  628C         STR        R4, [R1, #40]
+  0x08000750:  E087         B          .L33                     ; 0x08000862
+
.L7:
+  0x08000752:  9604         STR        R6, [SP, #16]
+  0x08000754:  9201         STR        R2, [SP, #4]
+  0x08000756:  4622         MOV        R2, R4
+  0x08000758:  241F         MOVS       R4, #31
+  0x0800075A:  9205         STR        R2, [SP, #20]
+  0x0800075C:  4014         ANDS       R4, R2
+  0x0800075E:  220F         MOVS       R2, #15
+  0x08000760:  9200         STR        R2, [SP, #0]
+  0x08000762:  9406         STR        R4, [SP, #24]
+  0x08000764:  40A2         LSLS       R2, R4
+  0x08000766:  6E3C         LDR        R4, [R7, #96]
+  0x08000768:  9203         STR        R2, [SP, #12]
+  0x0800076A:  4394         BICS       R4, R2
+  0x0800076C:  422B         TST        R3, R5
+  0x0800076E:  9402         STR        R4, [SP, #8]
+  0x08000770:  9E05         LDR        R6, [SP, #20]
+  0x08000772:  D045         BEQ        .L16                     ; 0x08000800
+  0x08000774:  4622         MOV        R2, R4
+  0x08000776:  07DD         LSLS       R5, R3, #31
+  0x08000778:  9D07         LDR        R5, [SP, #28]
+  0x0800077A:  D15F         BNE        .L31                     ; 0x0800083C
+  0x0800077C:  079D         LSLS       R5, R3, #30
+  0x0800077E:  D443         BMI        .L17                     ; 0x08000808
+  0x08000780:  075D         LSLS       R5, R3, #29
+  0x08000782:  D443         BMI        .L18                     ; 0x0800080C
+  0x08000784:  071D         LSLS       R5, R3, #28
+  0x08000786:  D443         BMI        .L19                     ; 0x08000810
+  0x08000788:  06DD         LSLS       R5, R3, #27
+  0x0800078A:  9D01         LDR        R5, [SP, #4]
+  0x0800078C:  D456         BMI        .L31                     ; 0x0800083C
+  0x0800078E:  069A         LSLS       R2, R3, #26
+  0x08000790:  D440         BMI        .L20                     ; 0x08000814
+  0x08000792:  065A         LSLS       R2, R3, #25
+  0x08000794:  D440         BMI        .L21                     ; 0x08000818
+  0x08000796:  061A         LSLS       R2, R3, #24
+  0x08000798:  D440         BMI        .L22                     ; 0x0800081C
+  0x0800079A:  05DA         LSLS       R2, R3, #23
+  0x0800079C:  D440         BMI        .L23                     ; 0x08000820
+  0x0800079E:  059A         LSLS       R2, R3, #22
+  0x080007A0:  D440         BMI        .L24                     ; 0x08000824
+  0x080007A2:  055A         LSLS       R2, R3, #21
+  0x080007A4:  D440         BMI        .L25                     ; 0x08000828
+  0x080007A6:  051A         LSLS       R2, R3, #20
+  0x080007A8:  D440         BMI        .L26                     ; 0x0800082C
+  0x080007AA:  04DA         LSLS       R2, R3, #19
+  0x080007AC:  D440         BMI        .L27                     ; 0x08000830
+  0x080007AE:  049A         LSLS       R2, R3, #18
+  0x080007B0:  D440         BMI        .L28                     ; 0x08000834
+  0x080007B2:  045A         LSLS       R2, R3, #17
+  0x080007B4:  D440         BMI        .L29                     ; 0x08000838
+  0x080007B6:  041A         LSLS       R2, R3, #16
+  0x080007B8:  9D00         LDR        R5, [SP, #0]
+  0x080007BA:  9A02         LDR        R2, [SP, #8]
+  0x080007BC:  D43E         BMI        .L31                     ; 0x0800083C
+  0x080007BE:  03DA         LSLS       R2, R3, #15
+  0x080007C0:  D500         BPL        .L8                      ; 0x080007C4
+  0x080007C2:  E092         B          .L39                     ; 0x080008EA
+
.L8:
+  0x080007C4:  039A         LSLS       R2, R3, #14
+  0x080007C6:  D500         BPL        .L9                      ; 0x080007CA
+  0x080007C8:  E091         B          .L40                     ; 0x080008EE
+
.L9:
+  0x080007CA:  035A         LSLS       R2, R3, #13
+  0x080007CC:  D500         BPL        .L10                     ; 0x080007D0
+  0x080007CE:  E090         B          .L41                     ; 0x080008F2
+
.L10:
+  0x080007D0:  031A         LSLS       R2, R3, #12
+  0x080007D2:  D500         BPL        .L11                     ; 0x080007D6
+  0x080007D4:  E08F         B          .L42                     ; 0x080008F6
+
.L11:
+  0x080007D6:  02DA         LSLS       R2, R3, #11
+  0x080007D8:  D500         BPL        .L12                     ; 0x080007DC
+  0x080007DA:  E08E         B          .L43                     ; 0x080008FA
+
.L12:
+  0x080007DC:  029A         LSLS       R2, R3, #10
+  0x080007DE:  D500         BPL        .L13                     ; 0x080007E2
+  0x080007E0:  E08D         B          .L44                     ; 0x080008FE
+
.L13:
+  0x080007E2:  025A         LSLS       R2, R3, #9
+  0x080007E4:  17D2         ASRS       R2, R2, #31
+  0x080007E6:  2516         MOVS       R5, #22
+  0x080007E8:  4015         ANDS       R5, R2
+  0x080007EA:  E026         B          .L30                     ; 0x0800083A
+
.L14:
+  0x080007EC:  4A46         LDR        R2, =0x007FFFFF          ; [PC, #0x0118] [0x08000908] 
+  0x080007EE:  1C52         ADDS       R2, R2, #1
+
.L15:
+  0x080007F0:  4011         ANDS       R1, R2
+  0x080007F2:  2203         MOVS       R2, #3
+  0x080007F4:  0592         LSLS       R2, R2, #22
+  0x080007F6:  6803         LDR        R3, [R0]
+  0x080007F8:  4393         BICS       R3, R2
+  0x080007FA:  1859         ADDS       R1, R3, R1
+  0x080007FC:  6001         STR        R1, [R0]
+  0x080007FE:  E070         B          .L37                     ; 0x080008E2
+
.L16:
+  0x08000800:  005A         LSLS       R2, R3, #1
+  0x08000802:  0ED5         LSRS       R5, R2, #27
+  0x08000804:  4622         MOV        R2, R4
+  0x08000806:  E019         B          .L31                     ; 0x0800083C
+
.L17:
+  0x08000808:  2501         MOVS       R5, #1
+  0x0800080A:  E017         B          .L31                     ; 0x0800083C
+
.L18:
+  0x0800080C:  2502         MOVS       R5, #2
+  0x0800080E:  E015         B          .L31                     ; 0x0800083C
+
.L19:
+  0x08000810:  2503         MOVS       R5, #3
+  0x08000812:  E013         B          .L31                     ; 0x0800083C
+
.L20:
+  0x08000814:  2505         MOVS       R5, #5
+  0x08000816:  E010         B          .L30                     ; 0x0800083A
+
.L21:
+  0x08000818:  2506         MOVS       R5, #6
+  0x0800081A:  E00E         B          .L30                     ; 0x0800083A
+
.L22:
+  0x0800081C:  2507         MOVS       R5, #7
+  0x0800081E:  E00C         B          .L30                     ; 0x0800083A
+
.L23:
+  0x08000820:  2508         MOVS       R5, #8
+  0x08000822:  E00A         B          .L30                     ; 0x0800083A
+
.L24:
+  0x08000824:  2509         MOVS       R5, #9
+  0x08000826:  E008         B          .L30                     ; 0x0800083A
+
.L25:
+  0x08000828:  250A         MOVS       R5, #10
+  0x0800082A:  E006         B          .L30                     ; 0x0800083A
+
.L26:
+  0x0800082C:  250B         MOVS       R5, #11
+  0x0800082E:  E004         B          .L30                     ; 0x0800083A
+
.L27:
+  0x08000830:  250C         MOVS       R5, #12
+  0x08000832:  E002         B          .L30                     ; 0x0800083A
+
.L28:
+  0x08000834:  250D         MOVS       R5, #13
+  0x08000836:  E000         B          .L30                     ; 0x0800083A
+
.L29:
+  0x08000838:  250E         MOVS       R5, #14
+
.L30:
+  0x0800083A:  9A02         LDR        R2, [SP, #8]
+
.L31:
+  0x0800083C:  9C06         LDR        R4, [SP, #24]
+  0x0800083E:  40A5         LSLS       R5, R4
+  0x08000840:  4315         ORRS       R5, R2
+  0x08000842:  663D         STR        R5, [R7, #96]
+  0x08000844:  08B2         LSRS       R2, R6, #2
+  0x08000846:  69FC         LDR        R4, [R7, #28]
+  0x08000848:  4294         CMP        R4, R2
+  0x0800084A:  D909         BLS        .L32                     ; 0x08000860
+  0x0800084C:  9A03         LDR        R2, [SP, #12]
+  0x0800084E:  43D2         MVNS       R2, R2
+  0x08000850:  6A8C         LDR        R4, [R1, #40]
+  0x08000852:  4014         ANDS       R4, R2
+  0x08000854:  009A         LSLS       R2, R3, #2
+  0x08000856:  0F12         LSRS       R2, R2, #28
+  0x08000858:  9D06         LDR        R5, [SP, #24]
+  0x0800085A:  40AA         LSLS       R2, R5
+  0x0800085C:  4322         ORRS       R2, R4
+  0x0800085E:  628A         STR        R2, [R1, #40]
+
.L32:
+  0x08000860:  9E04         LDR        R6, [SP, #16]
+
.L33:
+  0x08000862:  9D07         LDR        R5, [SP, #28]
+  0x08000864:  021A         LSLS       R2, R3, #8
+  0x08000866:  694C         LDR        R4, [R1, #20]
+  0x08000868:  4394         BICS       R4, R2
+  0x0800086A:  6880         LDR        R0, [R0, #8]
+  0x0800086C:  4010         ANDS       R0, R2
+  0x0800086E:  4A28         LDR        R2, =0x7FFFFF00          ; [PC, #160] [0x08000910] 
+  0x08000870:  4002         ANDS       R2, R0
+  0x08000872:  4322         ORRS       R2, R4
+  0x08000874:  614A         STR        R2, [R1, #20]
+  0x08000876:  2400         MOVS       R4, #0
+  0x08000878:  2B00         CMP        R3, #0
+  0x0800087A:  D532         BPL        .L37                     ; 0x080008E2
+  0x0800087C:  2003         MOVS       R0, #3
+  0x0800087E:  0582         LSLS       R2, R0, #22
+  0x08000880:  4824         LDR        R0, =0x40012708          ; [PC, #144] [0x08000914] 
+  0x08000882:  6805         LDR        R5, [R0]
+  0x08000884:  4629         MOV        R1, R5
+  0x08000886:  4011         ANDS       R1, R2
+  0x08000888:  4823         LDR        R0, =0xA4000200          ; [PC, #140] [0x08000918] 
+  0x0800088A:  4283         CMP        R3, R0
+  0x0800088C:  D11B         BNE        .L35                     ; 0x080008C6
+  0x0800088E:  481E         LDR        R0, =0x007FFFFF          ; [PC, #120] [0x08000908] 
+  0x08000890:  1C40         ADDS       R0, R0, #1
+  0x08000892:  4281         CMP        R1, R0
+  0x08000894:  D217         BCS        .L35                     ; 0x080008C6
+  0x08000896:  4B1F         LDR        R3, =0x40012708          ; [PC, #124] [0x08000914] 
+  0x08000898:  6818         LDR        R0, [R3]
+  0x0800089A:  4390         BICS       R0, R2
+  0x0800089C:  4301         ORRS       R1, R0
+  0x0800089E:  481A         LDR        R0, =0x007FFFFF          ; [PC, #104] [0x08000908] 
+  0x080008A0:  1840         ADDS       R0, R0, R1
+  0x080008A2:  1C40         ADDS       R0, R0, #1
+  0x080008A4:  6018         STR        R0, [R3]
+  0x080008A6:  481E         LDR        R0, =SystemCoreClock     ; [PC, #120] [0x08000920] =0x20000BA4 
+  0x080008A8:  6800         LDR        R0, [R0]
+  0x080008AA:  491E         LDR        R1, =0x00030D40          ; [PC, #120] [0x08000924] 
+  0x080008AC:  F005 FB9D    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080008B0:  210C         MOVS       R1, #12
+  0x080008B2:  4341         MULS       R1, R0, R1
+  0x080008B4:  1C48         ADDS       R0, R1, #1
+  0x080008B6:  9D07         LDR        R5, [SP, #28]
+
.L34:
+  0x080008B8:  9008         STR        R0, [SP, #32]
+  0x080008BA:  9808         LDR        R0, [SP, #32]
+  0x080008BC:  2800         CMP        R0, #0
+  0x080008BE:  D010         BEQ        .L37                     ; 0x080008E2
+  0x080008C0:  9808         LDR        R0, [SP, #32]
+  0x080008C2:  1E40         SUBS       R0, R0, #1
+  0x080008C4:  E7F8         B          .L34                     ; 0x080008B8
+
.L35:
+  0x080008C6:  4815         LDR        R0, =0xA8000400          ; [PC, #84] [0x0800091C] 
+  0x080008C8:  4283         CMP        R3, R0
+  0x080008CA:  D109         BNE        .L36                     ; 0x080008E0
+  0x080008CC:  2001         MOVS       R0, #1
+  0x080008CE:  0583         LSLS       R3, R0, #22
+  0x080008D0:  401D         ANDS       R5, R3
+  0x080008D2:  D105         BNE        .L36                     ; 0x080008E0
+  0x080008D4:  4D0F         LDR        R5, =0x40012708          ; [PC, #60] [0x08000914] 
+  0x080008D6:  6828         LDR        R0, [R5]
+  0x080008D8:  4390         BICS       R0, R2
+  0x080008DA:  4301         ORRS       R1, R0
+  0x080008DC:  4319         ORRS       R1, R3
+  0x080008DE:  6029         STR        R1, [R5]
+
.L36:
+  0x080008E0:  9D07         LDR        R5, [SP, #28]
+
.L37:
+  0x080008E2:  55BD         STRB       R5, [R7, R6]
+
.L38:
+  0x080008E4:  4620         MOV        R0, R4
+  0x080008E6:  B009         ADD        SP, SP, #36
+  0x080008E8:  BDF0         POP        {R4-R7, PC}
+
.L39:
+  0x080008EA:  2510         MOVS       R5, #16
+  0x080008EC:  E7A5         B          .L30                     ; 0x0800083A
+
.L40:
+  0x080008EE:  2511         MOVS       R5, #17
+  0x080008F0:  E7A3         B          .L30                     ; 0x0800083A
+
.L41:
+  0x080008F2:  2512         MOVS       R5, #18
+  0x080008F4:  E7A1         B          .L30                     ; 0x0800083A
+
.L42:
+  0x080008F6:  2513         MOVS       R5, #19
+  0x080008F8:  E79F         B          .L30                     ; 0x0800083A
+
.L43:
+  0x080008FA:  2514         MOVS       R5, #20
+  0x080008FC:  E79D         B          .L30                     ; 0x0800083A
+
.L44:
+  0x080008FE:  2515         MOVS       R5, #21
+  0x08000900:  E79B         B          .L30                     ; 0x0800083A
+  0x08000902:  46C0         NOP
+  0x08000904:  20000450     DC.W       hadc1
+  0x08000908:  007FFFFF     DC.W       0x007FFFFF
+  0x0800090C:  80000004     DC.W       0x80000004
+  0x08000910:  7FFFFF00     DC.W       0x7FFFFF00
+  0x08000914:  40012708     DC.W       0x40012708
+  0x08000918:  A4000200     DC.W       0xA4000200
+  0x0800091C:  A8000400     DC.W       0xA8000400
+  0x08000920:  20000BA4     DC.W       SystemCoreClock
+  0x08000924:  00030D40     DC.W       0x00030D40
+
+

Section .text.__NVIC_SystemReset from PowerPro_lto.o, size=28, align=4

+
+
__NVIC_SystemReset:
+  0x08000928:  F3BF 8F4F    DSB        SY
+  0x0800092C:  4803         LDR        R0, =0xE000ED0C          ; [PC, #12] [0x0800093C] 
+  0x0800092E:  4904         LDR        R1, =0x05FA0004          ; [PC, #16] [0x08000940] 
+  0x08000930:  6001         STR        R1, [R0]
+  0x08000932:  F3BF 8F4F    DSB        SY
+
.L1:
+  0x08000936:  BF00         NOP
+  0x08000938:  E7FD         B          .L1                      ; 0x08000936
+  0x0800093A:  46C0         NOP
+  0x0800093C:  E000ED0C     DC.W       0xE000ED0C
+  0x08000940:  05FA0004     DC.W       0x05FA0004
+
+

Section .text.HAL_DMA_Init from PowerPro_lto.o, size=224, align=4

+
+
HAL_DMA_Init:
+  0x08000944:  B5F0         PUSH       {R4-R7, LR}
+  0x08000946:  B083         SUB        SP, SP, #12
+  0x08000948:  2800         CMP        R0, #0
+  0x0800094A:  D03A         BEQ        .L1                      ; 0x080009C2
+  0x0800094C:  4604         MOV        R4, R0
+  0x0800094E:  4601         MOV        R1, R0
+  0x08000950:  3124         ADDS       R1, #36
+  0x08000952:  2002         MOVS       R0, #2
+  0x08000954:  9102         STR        R1, [SP, #8]
+  0x08000956:  7048         STRB       R0, [R1, #1]
+  0x08000958:  6827         LDR        R7, [R4]
+  0x0800095A:  6838         LDR        R0, [R7]
+  0x0800095C:  492C         LDR        R1, =0xFFFF800F          ; [PC, #176] [0x08000A10] 
+  0x0800095E:  4001         ANDS       R1, R0
+  0x08000960:  6039         STR        R1, [R7]
+  0x08000962:  4E2C         LDR        R6, =0x40020800          ; [PC, #176] [0x08000A14] 
+  0x08000964:  4630         MOV        R0, R6
+  0x08000966:  3080         ADDS       R0, #128
+  0x08000968:  64A0         STR        R0, [R4, #72]
+  0x0800096A:  482B         LDR        R0, =0xBFFDFFF8          ; [PC, #172] [0x08000A18] 
+  0x0800096C:  1838         ADDS       R0, R7, R0
+  0x0800096E:  2114         MOVS       R1, #20
+  0x08000970:  F005 FB3B    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08000974:  0080         LSLS       R0, R0, #2
+  0x08000976:  1981         ADDS       R1, R0, R6
+  0x08000978:  6420         STR        R0, [R4, #64]
+  0x0800097A:  9101         STR        R1, [SP, #4]
+  0x0800097C:  6461         STR        R1, [R4, #68]
+  0x0800097E:  20FC         MOVS       R0, #252
+  0x08000980:  4038         ANDS       R0, R7
+  0x08000982:  3808         SUBS       R0, #8
+  0x08000984:  2114         MOVS       R1, #20
+  0x08000986:  F005 FB30    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x0800098A:  211C         MOVS       R1, #28
+  0x0800098C:  4001         ANDS       R1, R0
+  0x0800098E:  2601         MOVS       R6, #1
+  0x08000990:  4630         MOV        R0, R6
+  0x08000992:  4088         LSLS       R0, R1
+  0x08000994:  64E0         STR        R0, [R4, #76]
+  0x08000996:  68E1         LDR        R1, [R4, #12]
+  0x08000998:  6922         LDR        R2, [R4, #16]
+  0x0800099A:  430A         ORRS       R2, R1
+  0x0800099C:  6961         LDR        R1, [R4, #20]
+  0x0800099E:  4311         ORRS       R1, R2
+  0x080009A0:  69A2         LDR        R2, [R4, #24]
+  0x080009A2:  430A         ORRS       R2, R1
+  0x080009A4:  69E1         LDR        R1, [R4, #28]
+  0x080009A6:  4311         ORRS       R1, R2
+  0x080009A8:  6A22         LDR        R2, [R4, #32]
+  0x080009AA:  430A         ORRS       R2, R1
+  0x080009AC:  68A1         LDR        R1, [R4, #8]
+  0x080009AE:  683B         LDR        R3, [R7]
+  0x080009B0:  4313         ORRS       R3, R2
+  0x080009B2:  430B         ORRS       R3, R1
+  0x080009B4:  603B         STR        R3, [R7]
+  0x080009B6:  03B2         LSLS       R2, R6, #14
+  0x080009B8:  4291         CMP        R1, R2
+  0x080009BA:  D104         BNE        .L2                      ; 0x080009C6
+  0x080009BC:  2100         MOVS       R1, #0
+  0x080009BE:  6061         STR        R1, [R4, #4]
+  0x080009C0:  E002         B          .L3                      ; 0x080009C8
+
.L1:
+  0x080009C2:  2001         MOVS       R0, #1
+  0x080009C4:  E021         B          .L5                      ; 0x08000A0A
+
.L2:
+  0x080009C6:  6861         LDR        R1, [R4, #4]
+
.L3:
+  0x080009C8:  B2CF         UXTB       R7, R1
+  0x080009CA:  9A01         LDR        R2, [SP, #4]
+  0x080009CC:  6017         STR        R7, [R2]
+  0x080009CE:  1E49         SUBS       R1, R1, #1
+  0x080009D0:  4A12         LDR        R2, =0x40020884          ; [PC, #72] [0x08000A1C] 
+  0x080009D2:  6010         STR        R0, [R2]
+  0x080009D4:  2000         MOVS       R0, #0
+  0x080009D6:  2903         CMP        R1, #3
+  0x080009D8:  4603         MOV        R3, R0
+  0x080009DA:  4601         MOV        R1, R0
+  0x080009DC:  4605         MOV        R5, R0
+  0x080009DE:  D80D         BHI        .L4                      ; 0x080009FC
+  0x080009E0:  1E79         SUBS       R1, R7, #1
+  0x080009E2:  008B         LSLS       R3, R1, #2
+  0x080009E4:  18D3         ADDS       R3, R2, R3
+  0x080009E6:  67DD         STR        R5, [R3, #124]
+  0x080009E8:  2501         MOVS       R5, #1
+  0x080009EA:  2603         MOVS       R6, #3
+  0x080009EC:  400E         ANDS       R6, R1
+  0x080009EE:  40B5         LSLS       R5, R6
+  0x080009F0:  2601         MOVS       R6, #1
+  0x080009F2:  490B         LDR        R1, =0x40020944          ; [PC, #44] [0x08000A20] 
+  0x080009F4:  600D         STR        R5, [R1]
+  0x080009F6:  337C         ADDS       R3, #124
+  0x080009F8:  32BC         ADDS       R2, #188
+  0x080009FA:  4611         MOV        R1, R2
+
.L4:
+  0x080009FC:  63E0         STR        R0, [R4, #60]
+  0x080009FE:  6523         STR        R3, [R4, #80]
+  0x08000A00:  6561         STR        R1, [R4, #84]
+  0x08000A02:  65A5         STR        R5, [R4, #88]
+  0x08000A04:  9902         LDR        R1, [SP, #8]
+  0x08000A06:  7008         STRB       R0, [R1]
+  0x08000A08:  704E         STRB       R6, [R1, #1]
+
.L5:
+  0x08000A0A:  B003         ADD        SP, SP, #12
+  0x08000A0C:  BDF0         POP        {R4-R7, PC}
+  0x08000A0E:  46C0         NOP
+  0x08000A10:  FFFF800F     DC.W       0xFFFF800F
+  0x08000A14:  40020800     DC.W       0x40020800
+  0x08000A18:  BFFDFFF8     DC.W       0xBFFDFFF8
+  0x08000A1C:  40020884     DC.W       0x40020884
+  0x08000A20:  40020944     DC.W       0x40020944
+
+

Section .text.HAL_DMA_Start_IT from PowerPro_lto.o, size=196, align=4

+
+
HAL_DMA_Start_IT:
+  0x08000A24:  B5F0         PUSH       {R4-R7, LR}
+  0x08000A26:  B084         SUB        SP, SP, #16
+  0x08000A28:  4604         MOV        R4, R0
+  0x08000A2A:  2024         MOVS       R0, #36
+  0x08000A2C:  5C20         LDRB       R0, [R4, R0]
+  0x08000A2E:  2801         CMP        R0, #1
+  0x08000A30:  D101         BNE        .L1                      ; 0x08000A36
+  0x08000A32:  2002         MOVS       R0, #2
+  0x08000A34:  E053         B          .L11                     ; 0x08000ADE
+
.L1:
+  0x08000A36:  4625         MOV        R5, R4
+  0x08000A38:  3524         ADDS       R5, #36
+  0x08000A3A:  7868         LDRB       R0, [R5, #1]
+  0x08000A3C:  2801         CMP        R0, #1
+  0x08000A3E:  D130         BNE        .L5                      ; 0x08000AA2
+  0x08000A40:  9300         STR        R3, [SP, #0]
+  0x08000A42:  9201         STR        R2, [SP, #4]
+  0x08000A44:  2002         MOVS       R0, #2
+  0x08000A46:  7068         STRB       R0, [R5, #1]
+  0x08000A48:  2000         MOVS       R0, #0
+  0x08000A4A:  63E0         STR        R0, [R4, #60]
+  0x08000A4C:  6826         LDR        R6, [R4]
+  0x08000A4E:  6832         LDR        R2, [R6]
+  0x08000A50:  2301         MOVS       R3, #1
+  0x08000A52:  9303         STR        R3, [SP, #12]
+  0x08000A54:  439A         BICS       R2, R3
+  0x08000A56:  6032         STR        R2, [R6]
+  0x08000A58:  6CA2         LDR        R2, [R4, #72]
+  0x08000A5A:  6CE7         LDR        R7, [R4, #76]
+  0x08000A5C:  6057         STR        R7, [R2, #4]
+  0x08000A5E:  6D22         LDR        R2, [R4, #80]
+  0x08000A60:  9202         STR        R2, [SP, #8]
+  0x08000A62:  2A00         CMP        R2, #0
+  0x08000A64:  D002         BEQ        .L2                      ; 0x08000A6C
+  0x08000A66:  6D62         LDR        R2, [R4, #84]
+  0x08000A68:  6DA7         LDR        R7, [R4, #88]
+  0x08000A6A:  6057         STR        R7, [R2, #4]
+
.L2:
+  0x08000A6C:  6C22         LDR        R2, [R4, #64]
+  0x08000A6E:  271C         MOVS       R7, #28
+  0x08000A70:  4017         ANDS       R7, R2
+  0x08000A72:  2201         MOVS       R2, #1
+  0x08000A74:  40BA         LSLS       R2, R7
+  0x08000A76:  4F1B         LDR        R7, =0x40020004          ; [PC, #108] [0x08000AE4] 
+  0x08000A78:  683B         LDR        R3, [R7]
+  0x08000A7A:  4313         ORRS       R3, R2
+  0x08000A7C:  603B         STR        R3, [R7]
+  0x08000A7E:  9A00         LDR        R2, [SP, #0]
+  0x08000A80:  6072         STR        R2, [R6, #4]
+  0x08000A82:  68A2         LDR        R2, [R4, #8]
+  0x08000A84:  2A10         CMP        R2, #16
+  0x08000A86:  9B01         LDR        R3, [SP, #4]
+  0x08000A88:  461A         MOV        R2, R3
+  0x08000A8A:  D000         BEQ        .L3                      ; 0x08000A8E
+  0x08000A8C:  460A         MOV        R2, R1
+
.L3:
+  0x08000A8E:  60B2         STR        R2, [R6, #8]
+  0x08000A90:  D000         BEQ        .L4                      ; 0x08000A94
+  0x08000A92:  4619         MOV        R1, R3
+
.L4:
+  0x08000A94:  60F1         STR        R1, [R6, #12]
+  0x08000A96:  6831         LDR        R1, [R6]
+  0x08000A98:  6B22         LDR        R2, [R4, #48]
+  0x08000A9A:  2A00         CMP        R2, #0
+  0x08000A9C:  D003         BEQ        .L6                      ; 0x08000AA6
+  0x08000A9E:  220E         MOVS       R2, #14
+  0x08000AA0:  E006         B          .L7                      ; 0x08000AB0
+
.L5:
+  0x08000AA2:  2002         MOVS       R0, #2
+  0x08000AA4:  E019         B          .L10                     ; 0x08000ADA
+
.L6:
+  0x08000AA6:  2204         MOVS       R2, #4
+  0x08000AA8:  4391         BICS       R1, R2
+  0x08000AAA:  6031         STR        R1, [R6]
+  0x08000AAC:  6832         LDR        R2, [R6]
+  0x08000AAE:  210A         MOVS       R1, #10
+
.L7:
+  0x08000AB0:  4311         ORRS       R1, R2
+  0x08000AB2:  6031         STR        R1, [R6]
+  0x08000AB4:  9903         LDR        R1, [SP, #12]
+  0x08000AB6:  0209         LSLS       R1, R1, #8
+  0x08000AB8:  6C62         LDR        R2, [R4, #68]
+  0x08000ABA:  6813         LDR        R3, [R2]
+  0x08000ABC:  03DB         LSLS       R3, R3, #15
+  0x08000ABE:  D502         BPL        .L8                      ; 0x08000AC6
+  0x08000AC0:  6813         LDR        R3, [R2]
+  0x08000AC2:  430B         ORRS       R3, R1
+  0x08000AC4:  6013         STR        R3, [R2]
+
.L8:
+  0x08000AC6:  9B02         LDR        R3, [SP, #8]
+  0x08000AC8:  2B00         CMP        R3, #0
+  0x08000ACA:  D002         BEQ        .L9                      ; 0x08000AD2
+  0x08000ACC:  681A         LDR        R2, [R3]
+  0x08000ACE:  430A         ORRS       R2, R1
+  0x08000AD0:  601A         STR        R2, [R3]
+
.L9:
+  0x08000AD2:  6831         LDR        R1, [R6]
+  0x08000AD4:  9A03         LDR        R2, [SP, #12]
+  0x08000AD6:  4311         ORRS       R1, R2
+  0x08000AD8:  6031         STR        R1, [R6]
+
.L10:
+  0x08000ADA:  2100         MOVS       R1, #0
+  0x08000ADC:  7029         STRB       R1, [R5]
+
.L11:
+  0x08000ADE:  B004         ADD        SP, SP, #16
+  0x08000AE0:  BDF0         POP        {R4-R7, PC}
+  0x08000AE2:  46C0         NOP
+  0x08000AE4:  40020004     DC.W       0x40020004
+
+

Section .text.HAL_DMA_IRQHandler from PowerPro_lto.o, size=164, align=4

+
+
HAL_DMA_IRQHandler:
+  0x08000AE8:  B5F0         PUSH       {R4-R7, LR}
+  0x08000AEA:  B081         SUB        SP, SP, #4
+  0x08000AEC:  6C01         LDR        R1, [R0, #64]
+  0x08000AEE:  241C         MOVS       R4, #28
+  0x08000AF0:  400C         ANDS       R4, R1
+  0x08000AF2:  2604         MOVS       R6, #4
+  0x08000AF4:  4633         MOV        R3, R6
+  0x08000AF6:  40A3         LSLS       R3, R4
+  0x08000AF8:  4923         LDR        R1, =0x40020004          ; [PC, #140] [0x08000B88] 
+  0x08000AFA:  1F0A         SUBS       R2, R1, #4
+  0x08000AFC:  6817         LDR        R7, [R2]
+  0x08000AFE:  6802         LDR        R2, [R0]
+  0x08000B00:  6815         LDR        R5, [R2]
+  0x08000B02:  423B         TST        R3, R7
+  0x08000B04:  D001         BEQ        .L1                      ; 0x08000B0A
+  0x08000B06:  0769         LSLS       R1, R5, #29
+  0x08000B08:  D41D         BMI        .L3                      ; 0x08000B46
+
.L1:
+  0x08000B0A:  4603         MOV        R3, R0
+  0x08000B0C:  3324         ADDS       R3, #36
+  0x08000B0E:  2602         MOVS       R6, #2
+  0x08000B10:  40A6         LSLS       R6, R4
+  0x08000B12:  423E         TST        R6, R7
+  0x08000B14:  D001         BEQ        .L2                      ; 0x08000B1A
+  0x08000B16:  07A9         LSLS       R1, R5, #30
+  0x08000B18:  D421         BMI        .L5                      ; 0x08000B5E
+
.L2:
+  0x08000B1A:  40E7         LSRS       R7, R4
+  0x08000B1C:  0739         LSLS       R1, R7, #28
+  0x08000B1E:  D531         BPL        .L8                      ; 0x08000B84
+  0x08000B20:  0729         LSLS       R1, R5, #28
+  0x08000B22:  D52F         BPL        .L8                      ; 0x08000B84
+  0x08000B24:  6811         LDR        R1, [R2]
+  0x08000B26:  250E         MOVS       R5, #14
+  0x08000B28:  43A9         BICS       R1, R5
+  0x08000B2A:  6011         STR        R1, [R2]
+  0x08000B2C:  2101         MOVS       R1, #1
+  0x08000B2E:  460A         MOV        R2, R1
+  0x08000B30:  40A2         LSLS       R2, R4
+  0x08000B32:  4D15         LDR        R5, =0x40020004          ; [PC, #84] [0x08000B88] 
+  0x08000B34:  682C         LDR        R4, [R5]
+  0x08000B36:  4314         ORRS       R4, R2
+  0x08000B38:  602C         STR        R4, [R5]
+  0x08000B3A:  63C1         STR        R1, [R0, #60]
+  0x08000B3C:  2200         MOVS       R2, #0
+  0x08000B3E:  701A         STRB       R2, [R3]
+  0x08000B40:  7059         STRB       R1, [R3, #1]
+  0x08000B42:  6B41         LDR        R1, [R0, #52]
+  0x08000B44:  E01B         B          .L7                      ; 0x08000B7E
+
.L3:
+  0x08000B46:  6811         LDR        R1, [R2]
+  0x08000B48:  0689         LSLS       R1, R1, #26
+  0x08000B4A:  D402         BMI        .L4                      ; 0x08000B52
+  0x08000B4C:  6811         LDR        R1, [R2]
+  0x08000B4E:  43B1         BICS       R1, R6
+  0x08000B50:  6011         STR        R1, [R2]
+
.L4:
+  0x08000B52:  4A0D         LDR        R2, =0x40020004          ; [PC, #52] [0x08000B88] 
+  0x08000B54:  6811         LDR        R1, [R2]
+  0x08000B56:  4319         ORRS       R1, R3
+  0x08000B58:  6011         STR        R1, [R2]
+  0x08000B5A:  6B01         LDR        R1, [R0, #48]
+  0x08000B5C:  E00F         B          .L7                      ; 0x08000B7E
+
.L5:
+  0x08000B5E:  6811         LDR        R1, [R2]
+  0x08000B60:  0689         LSLS       R1, R1, #26
+  0x08000B62:  D405         BMI        .L6                      ; 0x08000B70
+  0x08000B64:  6811         LDR        R1, [R2]
+  0x08000B66:  240A         MOVS       R4, #10
+  0x08000B68:  43A1         BICS       R1, R4
+  0x08000B6A:  6011         STR        R1, [R2]
+  0x08000B6C:  2101         MOVS       R1, #1
+  0x08000B6E:  7059         STRB       R1, [R3, #1]
+
.L6:
+  0x08000B70:  2100         MOVS       R1, #0
+  0x08000B72:  7019         STRB       R1, [R3]
+  0x08000B74:  4A04         LDR        R2, =0x40020004          ; [PC, #16] [0x08000B88] 
+  0x08000B76:  6811         LDR        R1, [R2]
+  0x08000B78:  4331         ORRS       R1, R6
+  0x08000B7A:  6011         STR        R1, [R2]
+  0x08000B7C:  6AC1         LDR        R1, [R0, #44]
+
.L7:
+  0x08000B7E:  2900         CMP        R1, #0
+  0x08000B80:  D000         BEQ        .L8                      ; 0x08000B84
+  0x08000B82:  4788         BLX        R1
+
.L8:
+  0x08000B84:  B001         ADD        SP, SP, #4
+  0x08000B86:  BDF0         POP        {R4-R7, PC}
+  0x08000B88:  40020004     DC.W       0x40020004
+
+

Section .text.FLASH_WaitForLastOperation from PowerPro_lto.o, size=80, align=4

+
+
FLASH_WaitForLastOperation:
+  0x08000B8C:  B510         PUSH       {R4, LR}
+  0x08000B8E:  207D         MOVS       R0, #125
+  0x08000B90:  00C2         LSLS       R2, R0, #3
+  0x08000B92:  480F         LDR        R0, =uwTick              ; [PC, #60] [0x08000BD0] =0x2000068C 
+  0x08000B94:  6801         LDR        R1, [R0]
+  0x08000B96:  188B         ADDS       R3, R1, R2
+  0x08000B98:  490E         LDR        R1, =0x40022010          ; [PC, #56] [0x08000BD4] 
+
.L1:
+  0x08000B9A:  680C         LDR        R4, [R1]
+  0x08000B9C:  03E4         LSLS       R4, R4, #15
+  0x08000B9E:  D504         BPL        .L3                      ; 0x08000BAA
+  0x08000BA0:  6804         LDR        R4, [R0]
+  0x08000BA2:  429C         CMP        R4, R3
+  0x08000BA4:  D3F9         BCC        .L1                      ; 0x08000B9A
+
.L2:
+  0x08000BA6:  2003         MOVS       R0, #3
+  0x08000BA8:  BD10         POP        {R4, PC}
+
.L3:
+  0x08000BAA:  680B         LDR        R3, [R1]
+  0x08000BAC:  4C0A         LDR        R4, =0x0000C3FA          ; [PC, #40] [0x08000BD8] 
+  0x08000BAE:  401C         ANDS       R4, R3
+  0x08000BB0:  600C         STR        R4, [R1]
+  0x08000BB2:  D001         BEQ        .L4                      ; 0x08000BB8
+  0x08000BB4:  2001         MOVS       R0, #1
+  0x08000BB6:  BD10         POP        {R4, PC}
+
.L4:
+  0x08000BB8:  6803         LDR        R3, [R0]
+  0x08000BBA:  189A         ADDS       R2, R3, R2
+
.L5:
+  0x08000BBC:  680B         LDR        R3, [R1]
+  0x08000BBE:  035B         LSLS       R3, R3, #13
+  0x08000BC0:  D503         BPL        .L6                      ; 0x08000BCA
+  0x08000BC2:  6803         LDR        R3, [R0]
+  0x08000BC4:  4293         CMP        R3, R2
+  0x08000BC6:  D3F9         BCC        .L5                      ; 0x08000BBC
+  0x08000BC8:  E7ED         B          .L2                      ; 0x08000BA6
+
.L6:
+  0x08000BCA:  2000         MOVS       R0, #0
+  0x08000BCC:  BD10         POP        {R4, PC}
+  0x08000BCE:  46C0         NOP
+  0x08000BD0:  2000068C     DC.W       uwTick
+  0x08000BD4:  40022010     DC.W       0x40022010
+  0x08000BD8:  0000C3FA     DC.W       0x0000C3FA
+
+

Section .text.HAL_FLASH_Unlock from PowerPro_lto.o, size=32, align=4

+
+
HAL_FLASH_Unlock:
+  0x08000BDC:  4804         LDR        R0, =0x40022008          ; [PC, #16] [0x08000BF0] 
+  0x08000BDE:  68C1         LDR        R1, [R0, #12]
+  0x08000BE0:  2900         CMP        R1, #0
+  0x08000BE2:  D504         BPL        .L1                      ; 0x08000BEE
+  0x08000BE4:  4903         LDR        R1, =0x45670123          ; [PC, #12] [0x08000BF4] 
+  0x08000BE6:  6001         STR        R1, [R0]
+  0x08000BE8:  4903         LDR        R1, =0xCDEF89AB          ; [PC, #12] [0x08000BF8] 
+  0x08000BEA:  6001         STR        R1, [R0]
+  0x08000BEC:  68C0         LDR        R0, [R0, #12]
+
.L1:
+  0x08000BEE:  4770         BX         LR
+  0x08000BF0:  40022008     DC.W       0x40022008
+  0x08000BF4:  45670123     DC.W       0x45670123
+  0x08000BF8:  CDEF89AB     DC.W       0xCDEF89AB
+
+

Section .text.HAL_GPIO_Init from PowerPro_lto.o, size=380, align=4

+
+
HAL_GPIO_Init:
+  0x08000BFC:  B5F0         PUSH       {R4-R7, LR}
+  0x08000BFE:  B08A         SUB        SP, SP, #40
+  0x08000C00:  4A59         LDR        R2, =0x50001400          ; [PC, #0x0164] [0x08000D68] 
+  0x08000C02:  9005         STR        R0, [SP, #20]
+  0x08000C04:  4290         CMP        R0, R2
+  0x08000C06:  D001         BEQ        .L1                      ; 0x08000C0C
+  0x08000C08:  2006         MOVS       R0, #6
+  0x08000C0A:  E000         B          .L2                      ; 0x08000C0E
+
.L1:
+  0x08000C0C:  2005         MOVS       R0, #5
+
.L2:
+  0x08000C0E:  220B         MOVS       R2, #11
+  0x08000C10:  0712         LSLS       R2, R2, #28
+  0x08000C12:  9B05         LDR        R3, [SP, #20]
+  0x08000C14:  189B         ADDS       R3, R3, R2
+  0x08000C16:  220A         MOVS       R2, #10
+  0x08000C18:  41D3         RORS       R3, R2
+  0x08000C1A:  9300         STR        R3, [SP, #0]
+  0x08000C1C:  2B04         CMP        R3, #4
+  0x08000C1E:  D300         BCC        .L3                      ; 0x08000C22
+  0x08000C20:  9000         STR        R0, [SP, #0]
+
.L3:
+  0x08000C22:  9805         LDR        R0, [SP, #20]
+  0x08000C24:  3020         ADDS       R0, #32
+  0x08000C26:  9001         STR        R0, [SP, #4]
+  0x08000C28:  2200         MOVS       R2, #0
+  0x08000C2A:  4617         MOV        R7, R2
+  0x08000C2C:  9207         STR        R2, [SP, #28]
+  0x08000C2E:  9208         STR        R2, [SP, #32]
+
.L4:
+  0x08000C30:  680D         LDR        R5, [R1]
+  0x08000C32:  4628         MOV        R0, R5
+  0x08000C34:  40D0         LSRS       R0, R2
+  0x08000C36:  D100         BNE        .L5                      ; 0x08000C3A
+  0x08000C38:  E093         B          .L19                     ; 0x08000D62
+
.L5:
+  0x08000C3A:  2301         MOVS       R3, #1
+  0x08000C3C:  4618         MOV        R0, R3
+  0x08000C3E:  9209         STR        R2, [SP, #36]
+  0x08000C40:  4090         LSLS       R0, R2
+  0x08000C42:  9004         STR        R0, [SP, #16]
+  0x08000C44:  4005         ANDS       R5, R0
+  0x08000C46:  D100         BNE        .L6                      ; 0x08000C4A
+  0x08000C48:  E081         B          .L18                     ; 0x08000D4E
+
.L6:
+  0x08000C4A:  684A         LDR        R2, [R1, #4]
+  0x08000C4C:  2010         MOVS       R0, #16
+  0x08000C4E:  4310         ORRS       R0, R2
+  0x08000C50:  2812         CMP        R0, #18
+  0x08000C52:  460E         MOV        R6, R1
+  0x08000C54:  9706         STR        R7, [SP, #24]
+  0x08000C56:  D116         BNE        .L7                      ; 0x08000C86
+  0x08000C58:  211C         MOVS       R1, #28
+  0x08000C5A:  9808         LDR        R0, [SP, #32]
+  0x08000C5C:  4001         ANDS       R1, R0
+  0x08000C5E:  270F         MOVS       R7, #15
+  0x08000C60:  463A         MOV        R2, R7
+  0x08000C62:  408A         LSLS       R2, R1
+  0x08000C64:  9809         LDR        R0, [SP, #36]
+  0x08000C66:  08C4         LSRS       R4, R0, #3
+  0x08000C68:  00A4         LSLS       R4, R4, #2
+  0x08000C6A:  9303         STR        R3, [SP, #12]
+  0x08000C6C:  4633         MOV        R3, R6
+  0x08000C6E:  9E01         LDR        R6, [SP, #4]
+  0x08000C70:  5930         LDR        R0, [R6, R4]
+  0x08000C72:  4390         BICS       R0, R2
+  0x08000C74:  691A         LDR        R2, [R3, #16]
+  0x08000C76:  403A         ANDS       R2, R7
+  0x08000C78:  9F06         LDR        R7, [SP, #24]
+  0x08000C7A:  408A         LSLS       R2, R1
+  0x08000C7C:  4302         ORRS       R2, R0
+  0x08000C7E:  5132         STR        R2, [R6, R4]
+  0x08000C80:  461E         MOV        R6, R3
+  0x08000C82:  9B03         LDR        R3, [SP, #12]
+  0x08000C84:  6872         LDR        R2, [R6, #4]
+
.L7:
+  0x08000C86:  2403         MOVS       R4, #3
+  0x08000C88:  4610         MOV        R0, R2
+  0x08000C8A:  4020         ANDS       R0, R4
+  0x08000C8C:  40B8         LSLS       R0, R7
+  0x08000C8E:  9402         STR        R4, [SP, #8]
+  0x08000C90:  40BC         LSLS       R4, R7
+  0x08000C92:  9905         LDR        R1, [SP, #20]
+  0x08000C94:  680F         LDR        R7, [R1]
+  0x08000C96:  43A7         BICS       R7, R4
+  0x08000C98:  4307         ORRS       R7, R0
+  0x08000C9A:  600F         STR        R7, [R1]
+  0x08000C9C:  9F06         LDR        R7, [SP, #24]
+  0x08000C9E:  43E0         MVNS       R0, R4
+  0x08000CA0:  9003         STR        R0, [SP, #12]
+  0x08000CA2:  2A12         CMP        R2, #18
+  0x08000CA4:  4631         MOV        R1, R6
+  0x08000CA6:  D815         BHI        .L9                      ; 0x08000CD4
+  0x08000CA8:  4093         LSLS       R3, R2
+  0x08000CAA:  4832         LDR        R0, =0x00060006          ; [PC, #200] [0x08000D74] 
+  0x08000CAC:  4203         TST        R3, R0
+  0x08000CAE:  D00F         BEQ        .L8                      ; 0x08000CD0
+  0x08000CB0:  9C05         LDR        R4, [SP, #20]
+  0x08000CB2:  68A0         LDR        R0, [R4, #8]
+  0x08000CB4:  9B03         LDR        R3, [SP, #12]
+  0x08000CB6:  4018         ANDS       R0, R3
+  0x08000CB8:  68CB         LDR        R3, [R1, #12]
+  0x08000CBA:  40BB         LSLS       R3, R7
+  0x08000CBC:  4303         ORRS       R3, R0
+  0x08000CBE:  60A3         STR        R3, [R4, #8]
+  0x08000CC0:  0910         LSRS       R0, R2, #4
+  0x08000CC2:  9B09         LDR        R3, [SP, #36]
+  0x08000CC4:  4098         LSLS       R0, R3
+  0x08000CC6:  6863         LDR        R3, [R4, #4]
+  0x08000CC8:  9E04         LDR        R6, [SP, #16]
+  0x08000CCA:  43B3         BICS       R3, R6
+  0x08000CCC:  4303         ORRS       R3, R0
+  0x08000CCE:  6063         STR        R3, [R4, #4]
+
.L8:
+  0x08000CD0:  2A03         CMP        R2, #3
+  0x08000CD2:  D03C         BEQ        .L18                     ; 0x08000D4E
+
.L9:
+  0x08000CD4:  9C05         LDR        R4, [SP, #20]
+  0x08000CD6:  68E0         LDR        R0, [R4, #12]
+  0x08000CD8:  9B03         LDR        R3, [SP, #12]
+  0x08000CDA:  4018         ANDS       R0, R3
+  0x08000CDC:  688B         LDR        R3, [R1, #8]
+  0x08000CDE:  40BB         LSLS       R3, R7
+  0x08000CE0:  4303         ORRS       R3, R0
+  0x08000CE2:  60E3         STR        R3, [R4, #12]
+  0x08000CE4:  00D0         LSLS       R0, R2, #3
+  0x08000CE6:  D532         BPL        .L18                     ; 0x08000D4E
+  0x08000CE8:  2018         MOVS       R0, #24
+  0x08000CEA:  9A07         LDR        R2, [SP, #28]
+  0x08000CEC:  4010         ANDS       R0, R2
+  0x08000CEE:  220F         MOVS       R2, #15
+  0x08000CF0:  4082         LSLS       R2, R0
+  0x08000CF2:  9B09         LDR        R3, [SP, #36]
+  0x08000CF4:  9C02         LDR        R4, [SP, #8]
+  0x08000CF6:  43A3         BICS       R3, R4
+  0x08000CF8:  4C1C         LDR        R4, =0x40021800          ; [PC, #112] [0x08000D6C] 
+  0x08000CFA:  18E4         ADDS       R4, R4, R3
+  0x08000CFC:  6E23         LDR        R3, [R4, #96]
+  0x08000CFE:  4393         BICS       R3, R2
+  0x08000D00:  9A00         LDR        R2, [SP, #0]
+  0x08000D02:  4082         LSLS       R2, R0
+  0x08000D04:  431A         ORRS       R2, R3
+  0x08000D06:  6622         STR        R2, [R4, #96]
+  0x08000D08:  4819         LDR        R0, =0x40021880          ; [PC, #100] [0x08000D70] 
+  0x08000D0A:  6802         LDR        R2, [R0]
+  0x08000D0C:  684B         LDR        R3, [R1, #4]
+  0x08000D0E:  03D8         LSLS       R0, R3, #15
+  0x08000D10:  D501         BPL        .L10                     ; 0x08000D16
+  0x08000D12:  432A         ORRS       R2, R5
+  0x08000D14:  E000         B          .L11                     ; 0x08000D18
+
.L10:
+  0x08000D16:  43AA         BICS       R2, R5
+
.L11:
+  0x08000D18:  4815         LDR        R0, =0x40021880          ; [PC, #84] [0x08000D70] 
+  0x08000D1A:  6002         STR        R2, [R0]
+  0x08000D1C:  6842         LDR        R2, [R0, #4]
+  0x08000D1E:  0398         LSLS       R0, R3, #14
+  0x08000D20:  D501         BPL        .L12                     ; 0x08000D26
+  0x08000D22:  432A         ORRS       R2, R5
+  0x08000D24:  E000         B          .L13                     ; 0x08000D28
+
.L12:
+  0x08000D26:  43AA         BICS       R2, R5
+
.L13:
+  0x08000D28:  4811         LDR        R0, =0x40021880          ; [PC, #68] [0x08000D70] 
+  0x08000D2A:  6042         STR        R2, [R0, #4]
+  0x08000D2C:  480F         LDR        R0, =0x40021800          ; [PC, #60] [0x08000D6C] 
+  0x08000D2E:  6802         LDR        R2, [R0]
+  0x08000D30:  02D8         LSLS       R0, R3, #11
+  0x08000D32:  D501         BPL        .L14                     ; 0x08000D38
+  0x08000D34:  432A         ORRS       R2, R5
+  0x08000D36:  E000         B          .L15                     ; 0x08000D3A
+
.L14:
+  0x08000D38:  43AA         BICS       R2, R5
+
.L15:
+  0x08000D3A:  480C         LDR        R0, =0x40021800          ; [PC, #48] [0x08000D6C] 
+  0x08000D3C:  6002         STR        R2, [R0]
+  0x08000D3E:  6842         LDR        R2, [R0, #4]
+  0x08000D40:  0298         LSLS       R0, R3, #10
+  0x08000D42:  D501         BPL        .L16                     ; 0x08000D48
+  0x08000D44:  432A         ORRS       R2, R5
+  0x08000D46:  E000         B          .L17                     ; 0x08000D4A
+
.L16:
+  0x08000D48:  43AA         BICS       R2, R5
+
.L17:
+  0x08000D4A:  4808         LDR        R0, =0x40021800          ; [PC, #32] [0x08000D6C] 
+  0x08000D4C:  6042         STR        R2, [R0, #4]
+
.L18:
+  0x08000D4E:  9808         LDR        R0, [SP, #32]
+  0x08000D50:  1D00         ADDS       R0, R0, #4
+  0x08000D52:  9008         STR        R0, [SP, #32]
+  0x08000D54:  1CBF         ADDS       R7, R7, #2
+  0x08000D56:  9807         LDR        R0, [SP, #28]
+  0x08000D58:  3008         ADDS       R0, #8
+  0x08000D5A:  9007         STR        R0, [SP, #28]
+  0x08000D5C:  9A09         LDR        R2, [SP, #36]
+  0x08000D5E:  1C52         ADDS       R2, R2, #1
+  0x08000D60:  E766         B          .L4                      ; 0x08000C30
+
.L19:
+  0x08000D62:  B00A         ADD        SP, SP, #40
+  0x08000D64:  BDF0         POP        {R4-R7, PC}
+  0x08000D66:  46C0         NOP
+  0x08000D68:  50001400     DC.W       0x50001400
+  0x08000D6C:  40021800     DC.W       0x40021800
+  0x08000D70:  40021880     DC.W       0x40021880
+  0x08000D74:  00060006     DC.W       0x00060006
+
+

Section .text.HAL_RCC_GetSysClockFreq from PowerPro_lto.o, size=84, align=4

+
+
HAL_RCC_GetSysClockFreq:
+  0x08000D78:  4811         LDR        R0, =0x40021008          ; [PC, #68] [0x08000DC0] 
+  0x08000D7A:  6801         LDR        R1, [R0]
+  0x08000D7C:  0689         LSLS       R1, R1, #26
+  0x08000D7E:  0F49         LSRS       R1, R1, #29
+  0x08000D80:  D006         BEQ        .L1                      ; 0x08000D90
+  0x08000D82:  6802         LDR        R2, [R0]
+  0x08000D84:  2138         MOVS       R1, #56
+  0x08000D86:  400A         ANDS       R2, R1
+  0x08000D88:  2A08         CMP        R2, #8
+  0x08000D8A:  D108         BNE        .L2                      ; 0x08000D9E
+  0x08000D8C:  480D         LDR        R0, =0x007A1200          ; [PC, #52] [0x08000DC4] 
+  0x08000D8E:  4770         BX         LR
+
.L1:
+  0x08000D90:  3808         SUBS       R0, #8
+  0x08000D92:  6800         LDR        R0, [R0]
+  0x08000D94:  0480         LSLS       R0, R0, #18
+  0x08000D96:  0F41         LSRS       R1, R0, #29
+  0x08000D98:  480B         LDR        R0, =0x02DC6C00          ; [PC, #44] [0x08000DC8] 
+  0x08000D9A:  40C8         LSRS       R0, R1
+  0x08000D9C:  4770         BX         LR
+
.L2:
+  0x08000D9E:  6802         LDR        R2, [R0]
+  0x08000DA0:  400A         ANDS       R2, R1
+  0x08000DA2:  2A20         CMP        R2, #32
+  0x08000DA4:  D102         BNE        .L3                      ; 0x08000DAC
+  0x08000DA6:  2001         MOVS       R0, #1
+  0x08000DA8:  03C0         LSLS       R0, R0, #15
+  0x08000DAA:  4770         BX         LR
+
.L3:
+  0x08000DAC:  6800         LDR        R0, [R0]
+  0x08000DAE:  4008         ANDS       R0, R1
+  0x08000DB0:  2818         CMP        R0, #24
+  0x08000DB2:  D001         BEQ        .L4                      ; 0x08000DB8
+  0x08000DB4:  2000         MOVS       R0, #0
+  0x08000DB6:  4770         BX         LR
+
.L4:
+  0x08000DB8:  207D         MOVS       R0, #125
+  0x08000DBA:  0200         LSLS       R0, R0, #8
+  0x08000DBC:  4770         BX         LR
+  0x08000DBE:  46C0         NOP
+  0x08000DC0:  40021008     DC.W       0x40021008
+  0x08000DC4:  007A1200     DC.W       0x007A1200
+  0x08000DC8:  02DC6C00     DC.W       0x02DC6C00
+
+

Section .text.HAL_RCC_GetPCLK1Freq from PowerPro_lto.o, size=64, align=4

+
+
HAL_RCC_GetPCLK1Freq:
+  0x08000DCC:  B580         PUSH       {R7, LR}
+  0x08000DCE:  F7FF FFD3    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+  0x08000DD2:  490A         LDR        R1, =0x40021008          ; [PC, #40] [0x08000DFC] 
+  0x08000DD4:  680A         LDR        R2, [R1]
+  0x08000DD6:  0992         LSRS       R2, R2, #6
+  0x08000DD8:  233C         MOVS       R3, #60
+  0x08000DDA:  4013         ANDS       R3, R2
+  0x08000DDC:  4A08         LDR        R2, =AHBPrescTable       ; [PC, #32] [0x08000E00] =0x080050C4 
+  0x08000DDE:  58D2         LDR        R2, [R2, R3]
+  0x08000DE0:  231F         MOVS       R3, #31
+  0x08000DE2:  401A         ANDS       R2, R3
+  0x08000DE4:  40D0         LSRS       R0, R2
+  0x08000DE6:  4A07         LDR        R2, =SystemCoreClock     ; [PC, #28] [0x08000E04] =0x20000BA4 
+  0x08000DE8:  6010         STR        R0, [R2]
+  0x08000DEA:  6809         LDR        R1, [R1]
+  0x08000DEC:  0A89         LSRS       R1, R1, #10
+  0x08000DEE:  221C         MOVS       R2, #28
+  0x08000DF0:  400A         ANDS       R2, R1
+  0x08000DF2:  4905         LDR        R1, =APBPrescTable       ; [PC, #20] [0x08000E08] =0x08005104 
+  0x08000DF4:  5889         LDR        R1, [R1, R2]
+  0x08000DF6:  4019         ANDS       R1, R3
+  0x08000DF8:  40C8         LSRS       R0, R1
+  0x08000DFA:  BD80         POP        {R7, PC}
+  0x08000DFC:  40021008     DC.W       0x40021008
+  0x08000E00:  080050C4     DC.W       AHBPrescTable
+  0x08000E04:  20000BA4     DC.W       SystemCoreClock
+  0x08000E08:  08005104     DC.W       APBPrescTable
+
+

Section .text.HAL_RCCEx_PeriphCLKConfig from PowerPro_lto.o, size=268, align=4

+
+
HAL_RCCEx_PeriphCLKConfig:
+  0x08000E0C:  B5F0         PUSH       {R4-R7, LR}
+  0x08000E0E:  B084         SUB        SP, SP, #16
+  0x08000E10:  6803         LDR        R3, [R0]
+  0x08000E12:  0659         LSLS       R1, R3, #25
+  0x08000E14:  4A3C         LDR        R2, =0x4002103C          ; [PC, #240] [0x08000F08] 
+  0x08000E16:  D401         BMI        .L1                      ; 0x08000E1C
+  0x08000E18:  2500         MOVS       R5, #0
+  0x08000E1A:  E034         B          .L6                      ; 0x08000E86
+
.L1:
+  0x08000E1C:  2601         MOVS       R6, #1
+  0x08000E1E:  0734         LSLS       R4, R6, #28
+  0x08000E20:  6811         LDR        R1, [R2]
+  0x08000E22:  4021         ANDS       R1, R4
+  0x08000E24:  9102         STR        R1, [SP, #8]
+  0x08000E26:  D106         BNE        .L2                      ; 0x08000E36
+  0x08000E28:  6811         LDR        R1, [R2]
+  0x08000E2A:  4321         ORRS       R1, R4
+  0x08000E2C:  6011         STR        R1, [R2]
+  0x08000E2E:  6811         LDR        R1, [R2]
+  0x08000E30:  4021         ANDS       R1, R4
+  0x08000E32:  9103         STR        R1, [SP, #12]
+  0x08000E34:  9903         LDR        R1, [SP, #12]
+
.L2:
+  0x08000E36:  2103         MOVS       R1, #3
+  0x08000E38:  9101         STR        R1, [SP, #4]
+  0x08000E3A:  020D         LSLS       R5, R1, #8
+  0x08000E3C:  6A17         LDR        R7, [R2, #32]
+  0x08000E3E:  402F         ANDS       R7, R5
+  0x08000E40:  6985         LDR        R5, [R0, #24]
+  0x08000E42:  4932         LDR        R1, =0xFFFFFCFF          ; [PC, #200] [0x08000F0C] 
+  0x08000E44:  D012         BEQ        .L3                      ; 0x08000E6C
+  0x08000E46:  42AF         CMP        R7, R5
+  0x08000E48:  D011         BEQ        .L4                      ; 0x08000E6E
+  0x08000E4A:  9400         STR        R4, [SP, #0]
+  0x08000E4C:  6A17         LDR        R7, [R2, #32]
+  0x08000E4E:  0436         LSLS       R6, R6, #16
+  0x08000E50:  6A14         LDR        R4, [R2, #32]
+  0x08000E52:  4334         ORRS       R4, R6
+  0x08000E54:  6214         STR        R4, [R2, #32]
+  0x08000E56:  6A14         LDR        R4, [R2, #32]
+  0x08000E58:  43B4         BICS       R4, R6
+  0x08000E5A:  6214         STR        R4, [R2, #32]
+  0x08000E5C:  463C         MOV        R4, R7
+  0x08000E5E:  400C         ANDS       R4, R1
+  0x08000E60:  6214         STR        R4, [R2, #32]
+  0x08000E62:  07FC         LSLS       R4, R7, #31
+  0x08000E64:  D13E         BNE        .L12                     ; 0x08000EE4
+  0x08000E66:  462F         MOV        R7, R5
+  0x08000E68:  9C00         LDR        R4, [SP, #0]
+  0x08000E6A:  E000         B          .L4                      ; 0x08000E6E
+
.L3:
+  0x08000E6C:  462F         MOV        R7, R5
+
.L4:
+  0x08000E6E:  460D         MOV        R5, R1
+  0x08000E70:  6A11         LDR        R1, [R2, #32]
+  0x08000E72:  4029         ANDS       R1, R5
+  0x08000E74:  4339         ORRS       R1, R7
+  0x08000E76:  6211         STR        R1, [R2, #32]
+  0x08000E78:  2500         MOVS       R5, #0
+
.L5:
+  0x08000E7A:  9902         LDR        R1, [SP, #8]
+  0x08000E7C:  2900         CMP        R1, #0
+  0x08000E7E:  D102         BNE        .L6                      ; 0x08000E86
+  0x08000E80:  6811         LDR        R1, [R2]
+  0x08000E82:  43A1         BICS       R1, R4
+  0x08000E84:  6011         STR        R1, [R2]
+
.L6:
+  0x08000E86:  07D9         LSLS       R1, R3, #31
+  0x08000E88:  D005         BEQ        .L7                      ; 0x08000E96
+  0x08000E8A:  6991         LDR        R1, [R2, #24]
+  0x08000E8C:  2403         MOVS       R4, #3
+  0x08000E8E:  43A1         BICS       R1, R4
+  0x08000E90:  6884         LDR        R4, [R0, #8]
+  0x08000E92:  430C         ORRS       R4, R1
+  0x08000E94:  6194         STR        R4, [R2, #24]
+
.L7:
+  0x08000E96:  0799         LSLS       R1, R3, #30
+  0x08000E98:  D506         BPL        .L8                      ; 0x08000EA8
+  0x08000E9A:  2103         MOVS       R1, #3
+  0x08000E9C:  0309         LSLS       R1, R1, #12
+  0x08000E9E:  6994         LDR        R4, [R2, #24]
+  0x08000EA0:  438C         BICS       R4, R1
+  0x08000EA2:  68C1         LDR        R1, [R0, #12]
+  0x08000EA4:  4321         ORRS       R1, R4
+  0x08000EA6:  6191         STR        R1, [R2, #24]
+
.L8:
+  0x08000EA8:  0699         LSLS       R1, R3, #26
+  0x08000EAA:  D506         BPL        .L9                      ; 0x08000EBA
+  0x08000EAC:  2103         MOVS       R1, #3
+  0x08000EAE:  0789         LSLS       R1, R1, #30
+  0x08000EB0:  6994         LDR        R4, [R2, #24]
+  0x08000EB2:  438C         BICS       R4, R1
+  0x08000EB4:  6941         LDR        R1, [R0, #20]
+  0x08000EB6:  4321         ORRS       R1, R4
+  0x08000EB8:  6191         STR        R1, [R2, #24]
+
.L9:
+  0x08000EBA:  0759         LSLS       R1, R3, #29
+  0x08000EBC:  D506         BPL        .L10                     ; 0x08000ECC
+  0x08000EBE:  2103         MOVS       R1, #3
+  0x08000EC0:  0389         LSLS       R1, R1, #14
+  0x08000EC2:  6994         LDR        R4, [R2, #24]
+  0x08000EC4:  438C         BICS       R4, R1
+  0x08000EC6:  6901         LDR        R1, [R0, #16]
+  0x08000EC8:  4321         ORRS       R1, R4
+  0x08000ECA:  6191         STR        R1, [R2, #24]
+
.L10:
+  0x08000ECC:  0619         LSLS       R1, R3, #24
+  0x08000ECE:  D506         BPL        .L11                     ; 0x08000EDE
+  0x08000ED0:  3A3C         SUBS       R2, #60
+  0x08000ED2:  6811         LDR        R1, [R2]
+  0x08000ED4:  23E0         MOVS       R3, #224
+  0x08000ED6:  4399         BICS       R1, R3
+  0x08000ED8:  6840         LDR        R0, [R0, #4]
+  0x08000EDA:  4308         ORRS       R0, R1
+  0x08000EDC:  6010         STR        R0, [R2]
+
.L11:
+  0x08000EDE:  4628         MOV        R0, R5
+  0x08000EE0:  B004         ADD        SP, SP, #16
+  0x08000EE2:  BDF0         POP        {R4-R7, PC}
+
.L12:
+  0x08000EE4:  4E0A         LDR        R6, =uwTick              ; [PC, #40] [0x08000F10] =0x2000068C 
+  0x08000EE6:  6837         LDR        R7, [R6]
+
.L13:
+  0x08000EE8:  6A14         LDR        R4, [R2, #32]
+  0x08000EEA:  07A4         LSLS       R4, R4, #30
+  0x08000EEC:  D407         BMI        .L14                     ; 0x08000EFE
+  0x08000EEE:  6834         LDR        R4, [R6]
+  0x08000EF0:  1BE4         SUBS       R4, R4, R7
+  0x08000EF2:  4908         LDR        R1, =0x00001388          ; [PC, #32] [0x08000F14] 
+  0x08000EF4:  428C         CMP        R4, R1
+  0x08000EF6:  D9F7         BLS        .L13                     ; 0x08000EE8
+  0x08000EF8:  9D01         LDR        R5, [SP, #4]
+  0x08000EFA:  9C00         LDR        R4, [SP, #0]
+  0x08000EFC:  E7BD         B          .L5                      ; 0x08000E7A
+
.L14:
+  0x08000EFE:  462F         MOV        R7, R5
+  0x08000F00:  9C00         LDR        R4, [SP, #0]
+  0x08000F02:  4902         LDR        R1, =0xFFFFFCFF          ; [PC, #8] [0x08000F0C] 
+  0x08000F04:  E7B3         B          .L4                      ; 0x08000E6E
+  0x08000F06:  46C0         NOP
+  0x08000F08:  4002103C     DC.W       0x4002103C
+  0x08000F0C:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08000F10:  2000068C     DC.W       uwTick
+  0x08000F14:  00001388     DC.W       0x00001388
+
+

Section .text.HAL_TIM_Base_Init from PowerPro_lto.o, size=204, align=4

+
+
HAL_TIM_Base_Init:
+  0x08000F18:  B570         PUSH       {R4-R6, LR}
+  0x08000F1A:  B086         SUB        SP, SP, #24
+  0x08000F1C:  2800         CMP        R0, #0
+  0x08000F1E:  D01A         BEQ        .L2                      ; 0x08000F56
+  0x08000F20:  4604         MOV        R4, R0
+  0x08000F22:  4605         MOV        R5, R0
+  0x08000F24:  353C         ADDS       R5, #60
+  0x08000F26:  7868         LDRB       R0, [R5, #1]
+  0x08000F28:  2800         CMP        R0, #0
+  0x08000F2A:  D017         BEQ        .L4                      ; 0x08000F5C
+
.L1:
+  0x08000F2C:  2002         MOVS       R0, #2
+  0x08000F2E:  7068         STRB       R0, [R5, #1]
+  0x08000F30:  CC01         LDM        R4!, {R0}
+  0x08000F32:  4621         MOV        R1, R4
+  0x08000F34:  F000 F856    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08000F38:  2001         MOVS       R0, #1
+  0x08000F3A:  7328         STRB       R0, [R5, #12]
+  0x08000F3C:  70A8         STRB       R0, [R5, #2]
+  0x08000F3E:  70E8         STRB       R0, [R5, #3]
+  0x08000F40:  7128         STRB       R0, [R5, #4]
+  0x08000F42:  7168         STRB       R0, [R5, #5]
+  0x08000F44:  71A8         STRB       R0, [R5, #6]
+  0x08000F46:  71E8         STRB       R0, [R5, #7]
+  0x08000F48:  7228         STRB       R0, [R5, #8]
+  0x08000F4A:  7268         STRB       R0, [R5, #9]
+  0x08000F4C:  72A8         STRB       R0, [R5, #10]
+  0x08000F4E:  72E8         STRB       R0, [R5, #11]
+  0x08000F50:  7068         STRB       R0, [R5, #1]
+  0x08000F52:  2000         MOVS       R0, #0
+  0x08000F54:  E000         B          .L3                      ; 0x08000F58
+
.L2:
+  0x08000F56:  2001         MOVS       R0, #1
+
.L3:
+  0x08000F58:  B006         ADD        SP, SP, #24
+  0x08000F5A:  BD70         POP        {R4-R6, PC}
+
.L4:
+  0x08000F5C:  7028         STRB       R0, [R5]
+  0x08000F5E:  6821         LDR        R1, [R4]
+  0x08000F60:  4A1B         LDR        R2, =0x40014800          ; [PC, #108] [0x08000FD0] 
+  0x08000F62:  4291         CMP        R1, R2
+  0x08000F64:  D029         BEQ        .L5                      ; 0x08000FBA
+  0x08000F66:  4A1B         LDR        R2, =0x40014400          ; [PC, #108] [0x08000FD4] 
+  0x08000F68:  4291         CMP        R1, R2
+  0x08000F6A:  D1DF         BNE        .L1                      ; 0x08000F2C
+  0x08000F6C:  491A         LDR        R1, =0x40021034          ; [PC, #104] [0x08000FD8] 
+  0x08000F6E:  68CA         LDR        R2, [R1, #12]
+  0x08000F70:  2601         MOVS       R6, #1
+  0x08000F72:  9603         STR        R6, [SP, #12]
+  0x08000F74:  0473         LSLS       R3, R6, #17
+  0x08000F76:  431A         ORRS       R2, R3
+  0x08000F78:  60CA         STR        R2, [R1, #12]
+  0x08000F7A:  68CA         LDR        R2, [R1, #12]
+  0x08000F7C:  401A         ANDS       R2, R3
+  0x08000F7E:  9200         STR        R2, [SP, #0]
+  0x08000F80:  9A00         LDR        R2, [SP, #0]
+  0x08000F82:  680A         LDR        R2, [R1]
+  0x08000F84:  4332         ORRS       R2, R6
+  0x08000F86:  600A         STR        R2, [R1]
+  0x08000F88:  6809         LDR        R1, [R1]
+  0x08000F8A:  4031         ANDS       R1, R6
+  0x08000F8C:  9100         STR        R1, [SP, #0]
+  0x08000F8E:  9004         STR        R0, [SP, #16]
+  0x08000F90:  2002         MOVS       R0, #2
+  0x08000F92:  9002         STR        R0, [SP, #8]
+  0x08000F94:  2040         MOVS       R0, #64
+  0x08000F96:  9001         STR        R0, [SP, #4]
+  0x08000F98:  9800         LDR        R0, [SP, #0]
+  0x08000F9A:  2005         MOVS       R0, #5
+  0x08000F9C:  9005         STR        R0, [SP, #20]
+  0x08000F9E:  0700         LSLS       R0, R0, #28
+  0x08000FA0:  A901         ADD        R1, SP, #4
+  0x08000FA2:  F7FF FE2B    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x08000FA6:  20FF         MOVS       R0, #255
+  0x08000FA8:  0200         LSLS       R0, R0, #8
+  0x08000FAA:  490C         LDR        R1, =0xE000E414          ; [PC, #48] [0x08000FDC] 
+  0x08000FAC:  680A         LDR        R2, [R1]
+  0x08000FAE:  4382         BICS       R2, R0
+  0x08000FB0:  600A         STR        R2, [R1]
+  0x08000FB2:  0570         LSLS       R0, R6, #21
+  0x08000FB4:  490A         LDR        R1, =0xE000E100          ; [PC, #40] [0x08000FE0] 
+  0x08000FB6:  6008         STR        R0, [R1]
+  0x08000FB8:  E7B8         B          .L1                      ; 0x08000F2C
+
.L5:
+  0x08000FBA:  2001         MOVS       R0, #1
+  0x08000FBC:  0480         LSLS       R0, R0, #18
+  0x08000FBE:  4906         LDR        R1, =0x40021034          ; [PC, #24] [0x08000FD8] 
+  0x08000FC0:  68CA         LDR        R2, [R1, #12]
+  0x08000FC2:  4302         ORRS       R2, R0
+  0x08000FC4:  60CA         STR        R2, [R1, #12]
+  0x08000FC6:  68C9         LDR        R1, [R1, #12]
+  0x08000FC8:  4001         ANDS       R1, R0
+  0x08000FCA:  9101         STR        R1, [SP, #4]
+  0x08000FCC:  9801         LDR        R0, [SP, #4]
+  0x08000FCE:  E7AD         B          .L1                      ; 0x08000F2C
+  0x08000FD0:  40014800     DC.W       0x40014800
+  0x08000FD4:  40014400     DC.W       0x40014400
+  0x08000FD8:  40021034     DC.W       0x40021034
+  0x08000FDC:  E000E414     DC.W       0xE000E414
+  0x08000FE0:  E000E100     DC.W       0xE000E100
+
+

Section .text.TIM_Base_SetConfig from PowerPro_lto.o, size=144, align=4

+
+
TIM_Base_SetConfig:
+  0x08000FE4:  B530         PUSH       {R4-R5, LR}
+  0x08000FE6:  6804         LDR        R4, [R0]
+  0x08000FE8:  4A1D         LDR        R2, =0x40012C00          ; [PC, #116] [0x08001060] 
+  0x08000FEA:  4290         CMP        R0, R2
+  0x08000FEC:  D004         BEQ        .L1                      ; 0x08000FF8
+  0x08000FEE:  4D1D         LDR        R5, =0x40000400          ; [PC, #116] [0x08001064] 
+  0x08000FF0:  42A8         CMP        R0, R5
+  0x08000FF2:  D006         BEQ        .L2                      ; 0x08001002
+  0x08000FF4:  4623         MOV        R3, R4
+  0x08000FF6:  E008         B          .L3                      ; 0x0800100A
+
.L1:
+  0x08000FF8:  2370         MOVS       R3, #112
+  0x08000FFA:  439C         BICS       R4, R3
+  0x08000FFC:  684B         LDR        R3, [R1, #4]
+  0x08000FFE:  4323         ORRS       R3, R4
+  0x08001000:  E00F         B          .L4                      ; 0x08001022
+
.L2:
+  0x08001002:  2370         MOVS       R3, #112
+  0x08001004:  439C         BICS       R4, R3
+  0x08001006:  684B         LDR        R3, [R1, #4]
+  0x08001008:  4323         ORRS       R3, R4
+
.L3:
+  0x0800100A:  42A8         CMP        R0, R5
+  0x0800100C:  D009         BEQ        .L4                      ; 0x08001022
+  0x0800100E:  4C16         LDR        R4, =0x40002000          ; [PC, #88] [0x08001068] 
+  0x08001010:  42A0         CMP        R0, R4
+  0x08001012:  D006         BEQ        .L4                      ; 0x08001022
+  0x08001014:  4C15         LDR        R4, =0x40014800          ; [PC, #84] [0x0800106C] 
+  0x08001016:  42A0         CMP        R0, R4
+  0x08001018:  D003         BEQ        .L4                      ; 0x08001022
+  0x0800101A:  4C15         LDR        R4, =0x40014400          ; [PC, #84] [0x08001070] 
+  0x0800101C:  42A0         CMP        R0, R4
+  0x0800101E:  461C         MOV        R4, R3
+  0x08001020:  D104         BNE        .L5                      ; 0x0800102C
+
.L4:
+  0x08001022:  2403         MOVS       R4, #3
+  0x08001024:  0224         LSLS       R4, R4, #8
+  0x08001026:  43A3         BICS       R3, R4
+  0x08001028:  68CC         LDR        R4, [R1, #12]
+  0x0800102A:  431C         ORRS       R4, R3
+
.L5:
+  0x0800102C:  4290         CMP        R0, R2
+  0x0800102E:  688A         LDR        R2, [R1, #8]
+  0x08001030:  62C2         STR        R2, [R0, #44]
+  0x08001032:  680A         LDR        R2, [R1]
+  0x08001034:  6282         STR        R2, [R0, #40]
+  0x08001036:  694A         LDR        R2, [R1, #20]
+  0x08001038:  D005         BEQ        .L6                      ; 0x08001046
+  0x0800103A:  4B0C         LDR        R3, =0x40014800          ; [PC, #48] [0x0800106C] 
+  0x0800103C:  4298         CMP        R0, R3
+  0x0800103E:  D002         BEQ        .L6                      ; 0x08001046
+  0x08001040:  4B0B         LDR        R3, =0x40014400          ; [PC, #44] [0x08001070] 
+  0x08001042:  4298         CMP        R0, R3
+  0x08001044:  D101         BNE        .L7                      ; 0x0800104A
+
.L6:
+  0x08001046:  6909         LDR        R1, [R1, #16]
+  0x08001048:  6301         STR        R1, [R0, #48]
+
.L7:
+  0x0800104A:  6801         LDR        R1, [R0]
+  0x0800104C:  2304         MOVS       R3, #4
+  0x0800104E:  430B         ORRS       R3, R1
+  0x08001050:  6003         STR        R3, [R0]
+  0x08001052:  2101         MOVS       R1, #1
+  0x08001054:  6141         STR        R1, [R0, #20]
+  0x08001056:  2180         MOVS       R1, #128
+  0x08001058:  438C         BICS       R4, R1
+  0x0800105A:  4314         ORRS       R4, R2
+  0x0800105C:  6004         STR        R4, [R0]
+  0x0800105E:  BD30         POP        {R4-R5, PC}
+  0x08001060:  40012C00     DC.W       0x40012C00
+  0x08001064:  40000400     DC.W       0x40000400
+  0x08001068:  40002000     DC.W       0x40002000
+  0x0800106C:  40014800     DC.W       0x40014800
+  0x08001070:  40014400     DC.W       0x40014400
+
+

Section .text.HAL_UART_Init from PowerPro_lto.o, size=972, align=4

+
+
HAL_UART_Init:
+  0x08001074:  B5F0         PUSH       {R4-R7, LR}
+  0x08001076:  B091         SUB        SP, SP, #68
+  0x08001078:  4EE0         LDR        R6, =huart1              ; [PC, #0x0380] [0x080013FC] =0x200003BC 
+  0x0800107A:  2488         MOVS       R4, #136
+  0x0800107C:  5930         LDR        R0, [R6, R4]
+  0x0800107E:  2800         CMP        R0, #0
+  0x08001080:  6835         LDR        R5, [R6]
+  0x08001082:  9403         STR        R4, [SP, #12]
+  0x08001084:  D168         BNE        .L4                      ; 0x08001158
+  0x08001086:  2084         MOVS       R0, #132
+  0x08001088:  2700         MOVS       R7, #0
+  0x0800108A:  5437         STRB       R7, [R6, R0]
+  0x0800108C:  A805         ADD        R0, SP, #20
+  0x0800108E:  1D00         ADDS       R0, R0, #4
+  0x08001090:  2118         MOVS       R1, #24
+  0x08001092:  F005 F840    BL         __aeabi_memclr           ; 0x08006116
+  0x08001096:  48DA         LDR        R0, =0x40013800          ; [PC, #0x0368] [0x08001400] 
+  0x08001098:  4285         CMP        R5, R0
+  0x0800109A:  D15D         BNE        .L4                      ; 0x08001158
+  0x0800109C:  2401         MOVS       R4, #1
+  0x0800109E:  9405         STR        R4, [SP, #20]
+  0x080010A0:  A805         ADD        R0, SP, #20
+  0x080010A2:  F7FF FEB3    BL         HAL_RCCEx_PeriphCLKConfig ; 0x08000E0C
+  0x080010A6:  2800         CMP        R0, #0
+  0x080010A8:  D000         BEQ        .L1                      ; 0x080010AC
+  0x080010AA:  E1A5         B          .L31                     ; 0x080013F8
+
.L1:
+  0x080010AC:  48D5         LDR        R0, =0x40021000          ; [PC, #0x0354] [0x08001404] 
+  0x080010AE:  6C01         LDR        R1, [R0, #64]
+  0x080010B0:  9410         STR        R4, [SP, #64]
+  0x080010B2:  03A2         LSLS       R2, R4, #14
+  0x080010B4:  4311         ORRS       R1, R2
+  0x080010B6:  6401         STR        R1, [R0, #64]
+  0x080010B8:  6C01         LDR        R1, [R0, #64]
+  0x080010BA:  4011         ANDS       R1, R2
+  0x080010BC:  9104         STR        R1, [SP, #16]
+  0x080010BE:  9904         LDR        R1, [SP, #16]
+  0x080010C0:  6B41         LDR        R1, [R0, #52]
+  0x080010C2:  4321         ORRS       R1, R4
+  0x080010C4:  6341         STR        R1, [R0, #52]
+  0x080010C6:  6B40         LDR        R0, [R0, #52]
+  0x080010C8:  9401         STR        R4, [SP, #4]
+  0x080010CA:  4020         ANDS       R0, R4
+  0x080010CC:  9004         STR        R0, [SP, #16]
+  0x080010CE:  970F         STR        R7, [SP, #60]
+  0x080010D0:  970E         STR        R7, [SP, #56]
+  0x080010D2:  2002         MOVS       R0, #2
+  0x080010D4:  900D         STR        R0, [SP, #52]
+  0x080010D6:  2003         MOVS       R0, #3
+  0x080010D8:  0240         LSLS       R0, R0, #9
+  0x080010DA:  900C         STR        R0, [SP, #48]
+  0x080010DC:  9804         LDR        R0, [SP, #16]
+  0x080010DE:  2005         MOVS       R0, #5
+  0x080010E0:  0700         LSLS       R0, R0, #28
+  0x080010E2:  A90C         ADD        R1, SP, #48
+  0x080010E4:  F7FF FD8A    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x080010E8:  4CC7         LDR        R4, =hdma_usart1_rx      ; [PC, #0x031C] [0x08001408] =0x20000510 
+  0x080010EA:  2180         MOVS       R1, #128
+  0x080010EC:  2032         MOVS       R0, #50
+  0x080010EE:  4DC7         LDR        R5, =0x4002001C          ; [PC, #0x031C] [0x0800140C] 
+  0x080010F0:  6025         STR        R5, [R4]
+  0x080010F2:  6060         STR        R0, [R4, #4]
+  0x080010F4:  60A7         STR        R7, [R4, #8]
+  0x080010F6:  60E7         STR        R7, [R4, #12]
+  0x080010F8:  9102         STR        R1, [SP, #8]
+  0x080010FA:  6121         STR        R1, [R4, #16]
+  0x080010FC:  6167         STR        R7, [R4, #20]
+  0x080010FE:  61A7         STR        R7, [R4, #24]
+  0x08001100:  61E7         STR        R7, [R4, #28]
+  0x08001102:  6227         STR        R7, [R4, #32]
+  0x08001104:  4620         MOV        R0, R4
+  0x08001106:  F7FF FC1D    BL         HAL_DMA_Init             ; 0x08000944
+  0x0800110A:  2800         CMP        R0, #0
+  0x0800110C:  D000         BEQ        .L2                      ; 0x08001110
+  0x0800110E:  E173         B          .L31                     ; 0x080013F8
+
.L2:
+  0x08001110:  9A02         LDR        R2, [SP, #8]
+  0x08001112:  50B4         STR        R4, [R6, R2]
+  0x08001114:  62A6         STR        R6, [R4, #40]
+  0x08001116:  4CBE         LDR        R4, =hdma_usart1_tx      ; [PC, #0x02F8] [0x08001410] =0x200004B4 
+  0x08001118:  2010         MOVS       R0, #16
+  0x0800111A:  2133         MOVS       R1, #51
+  0x0800111C:  6227         STR        R7, [R4, #32]
+  0x0800111E:  3514         ADDS       R5, #20
+  0x08001120:  6025         STR        R5, [R4]
+  0x08001122:  6061         STR        R1, [R4, #4]
+  0x08001124:  60A0         STR        R0, [R4, #8]
+  0x08001126:  60E7         STR        R7, [R4, #12]
+  0x08001128:  6122         STR        R2, [R4, #16]
+  0x0800112A:  6167         STR        R7, [R4, #20]
+  0x0800112C:  61A7         STR        R7, [R4, #24]
+  0x0800112E:  61E7         STR        R7, [R4, #28]
+  0x08001130:  4620         MOV        R0, R4
+  0x08001132:  F7FF FC07    BL         HAL_DMA_Init             ; 0x08000944
+  0x08001136:  2800         CMP        R0, #0
+  0x08001138:  D000         BEQ        .L3                      ; 0x0800113C
+  0x0800113A:  E15D         B          .L31                     ; 0x080013F8
+
.L3:
+  0x0800113C:  62A6         STR        R6, [R4, #40]
+  0x0800113E:  67F4         STR        R4, [R6, #124]
+  0x08001140:  20FF         MOVS       R0, #255
+  0x08001142:  0600         LSLS       R0, R0, #24
+  0x08001144:  49B3         LDR        R1, =0xE000E418          ; [PC, #0x02CC] [0x08001414] 
+  0x08001146:  680A         LDR        R2, [R1]
+  0x08001148:  4382         BICS       R2, R0
+  0x0800114A:  600A         STR        R2, [R1]
+  0x0800114C:  9801         LDR        R0, [SP, #4]
+  0x0800114E:  06C0         LSLS       R0, R0, #27
+  0x08001150:  49B1         LDR        R1, =0xE000E100          ; [PC, #0x02C4] [0x08001418] 
+  0x08001152:  6008         STR        R0, [R1]
+  0x08001154:  6835         LDR        R5, [R6]
+  0x08001156:  9C03         LDR        R4, [SP, #12]
+
.L4:
+  0x08001158:  2024         MOVS       R0, #36
+  0x0800115A:  5130         STR        R0, [R6, R4]
+  0x0800115C:  6828         LDR        R0, [R5]
+  0x0800115E:  2401         MOVS       R4, #1
+  0x08001160:  43A0         BICS       R0, R4
+  0x08001162:  6028         STR        R0, [R5]
+  0x08001164:  6AB0         LDR        R0, [R6, #40]
+  0x08001166:  2800         CMP        R0, #0
+  0x08001168:  D048         BEQ        .L12                     ; 0x080011FC
+  0x0800116A:  0701         LSLS       R1, R0, #28
+  0x0800116C:  D505         BPL        .L5                      ; 0x0800117A
+  0x0800116E:  03E1         LSLS       R1, R4, #15
+  0x08001170:  686A         LDR        R2, [R5, #4]
+  0x08001172:  438A         BICS       R2, R1
+  0x08001174:  6BB1         LDR        R1, [R6, #56]
+  0x08001176:  4311         ORRS       R1, R2
+  0x08001178:  6069         STR        R1, [R5, #4]
+
.L5:
+  0x0800117A:  07C1         LSLS       R1, R0, #31
+  0x0800117C:  D005         BEQ        .L6                      ; 0x0800118A
+  0x0800117E:  0461         LSLS       R1, R4, #17
+  0x08001180:  686A         LDR        R2, [R5, #4]
+  0x08001182:  438A         BICS       R2, R1
+  0x08001184:  6AF1         LDR        R1, [R6, #44]
+  0x08001186:  4311         ORRS       R1, R2
+  0x08001188:  6069         STR        R1, [R5, #4]
+
.L6:
+  0x0800118A:  0781         LSLS       R1, R0, #30
+  0x0800118C:  D505         BPL        .L7                      ; 0x0800119A
+  0x0800118E:  0421         LSLS       R1, R4, #16
+  0x08001190:  686A         LDR        R2, [R5, #4]
+  0x08001192:  438A         BICS       R2, R1
+  0x08001194:  6B31         LDR        R1, [R6, #48]
+  0x08001196:  4311         ORRS       R1, R2
+  0x08001198:  6069         STR        R1, [R5, #4]
+
.L7:
+  0x0800119A:  0741         LSLS       R1, R0, #29
+  0x0800119C:  D505         BPL        .L8                      ; 0x080011AA
+  0x0800119E:  04A1         LSLS       R1, R4, #18
+  0x080011A0:  686A         LDR        R2, [R5, #4]
+  0x080011A2:  438A         BICS       R2, R1
+  0x080011A4:  6B71         LDR        R1, [R6, #52]
+  0x080011A6:  4311         ORRS       R1, R2
+  0x080011A8:  6069         STR        R1, [R5, #4]
+
.L8:
+  0x080011AA:  06C1         LSLS       R1, R0, #27
+  0x080011AC:  D505         BPL        .L9                      ; 0x080011BA
+  0x080011AE:  0321         LSLS       R1, R4, #12
+  0x080011B0:  68AA         LDR        R2, [R5, #8]
+  0x080011B2:  438A         BICS       R2, R1
+  0x080011B4:  6BF1         LDR        R1, [R6, #60]
+  0x080011B6:  4311         ORRS       R1, R2
+  0x080011B8:  60A9         STR        R1, [R5, #8]
+
.L9:
+  0x080011BA:  0681         LSLS       R1, R0, #26
+  0x080011BC:  D505         BPL        .L10                     ; 0x080011CA
+  0x080011BE:  0361         LSLS       R1, R4, #13
+  0x080011C0:  68AA         LDR        R2, [R5, #8]
+  0x080011C2:  438A         BICS       R2, R1
+  0x080011C4:  6C31         LDR        R1, [R6, #64]
+  0x080011C6:  4311         ORRS       R1, R2
+  0x080011C8:  60A9         STR        R1, [R5, #8]
+
.L10:
+  0x080011CA:  0641         LSLS       R1, R0, #25
+  0x080011CC:  D50E         BPL        .L11                     ; 0x080011EC
+  0x080011CE:  0521         LSLS       R1, R4, #20
+  0x080011D0:  686A         LDR        R2, [R5, #4]
+  0x080011D2:  438A         BICS       R2, R1
+  0x080011D4:  6C73         LDR        R3, [R6, #68]
+  0x080011D6:  431A         ORRS       R2, R3
+  0x080011D8:  606A         STR        R2, [R5, #4]
+  0x080011DA:  428B         CMP        R3, R1
+  0x080011DC:  D106         BNE        .L11                     ; 0x080011EC
+  0x080011DE:  2103         MOVS       R1, #3
+  0x080011E0:  0549         LSLS       R1, R1, #21
+  0x080011E2:  686A         LDR        R2, [R5, #4]
+  0x080011E4:  438A         BICS       R2, R1
+  0x080011E6:  6CB1         LDR        R1, [R6, #72]
+  0x080011E8:  4311         ORRS       R1, R2
+  0x080011EA:  6069         STR        R1, [R5, #4]
+
.L11:
+  0x080011EC:  0600         LSLS       R0, R0, #24
+  0x080011EE:  D505         BPL        .L12                     ; 0x080011FC
+  0x080011F0:  04E0         LSLS       R0, R4, #19
+  0x080011F2:  6869         LDR        R1, [R5, #4]
+  0x080011F4:  4381         BICS       R1, R0
+  0x080011F6:  6CF0         LDR        R0, [R6, #76]
+  0x080011F8:  4308         ORRS       R0, R1
+  0x080011FA:  6068         STR        R0, [R5, #4]
+
.L12:
+  0x080011FC:  6828         LDR        R0, [R5]
+  0x080011FE:  4987         LDR        R1, =0xCFFF69F3          ; [PC, #0x021C] [0x0800141C] 
+  0x08001200:  4001         ANDS       R1, R0
+  0x08001202:  68B0         LDR        R0, [R6, #8]
+  0x08001204:  6932         LDR        R2, [R6, #16]
+  0x08001206:  4302         ORRS       R2, R0
+  0x08001208:  6970         LDR        R0, [R6, #20]
+  0x0800120A:  4310         ORRS       R0, R2
+  0x0800120C:  4308         ORRS       R0, R1
+  0x0800120E:  69F1         LDR        R1, [R6, #28]
+  0x08001210:  4308         ORRS       R0, R1
+  0x08001212:  6028         STR        R0, [R5]
+  0x08001214:  2003         MOVS       R0, #3
+  0x08001216:  9002         STR        R0, [SP, #8]
+  0x08001218:  0300         LSLS       R0, R0, #12
+  0x0800121A:  686A         LDR        R2, [R5, #4]
+  0x0800121C:  4382         BICS       R2, R0
+  0x0800121E:  68F0         LDR        R0, [R6, #12]
+  0x08001220:  4310         ORRS       R0, R2
+  0x08001222:  6068         STR        R0, [R5, #4]
+  0x08001224:  69B0         LDR        R0, [R6, #24]
+  0x08001226:  6A32         LDR        R2, [R6, #32]
+  0x08001228:  4302         ORRS       R2, R0
+  0x0800122A:  68A8         LDR        R0, [R5, #8]
+  0x0800122C:  4B7C         LDR        R3, =0x11FFF4FF          ; [PC, #0x01F0] [0x08001420] 
+  0x0800122E:  4003         ANDS       R3, R0
+  0x08001230:  4313         ORRS       R3, R2
+  0x08001232:  60AB         STR        R3, [R5, #8]
+  0x08001234:  6AE8         LDR        R0, [R5, #44]
+  0x08001236:  220F         MOVS       R2, #15
+  0x08001238:  4390         BICS       R0, R2
+  0x0800123A:  6A77         LDR        R7, [R6, #36]
+  0x0800123C:  4338         ORRS       R0, R7
+  0x0800123E:  62E8         STR        R0, [R5, #44]
+  0x08001240:  4878         LDR        R0, =0x40004400          ; [PC, #0x01E0] [0x08001424] 
+  0x08001242:  4285         CMP        R5, R0
+  0x08001244:  D009         BEQ        .L13                     ; 0x0800125A
+  0x08001246:  486E         LDR        R0, =0x40013800          ; [PC, #0x01B8] [0x08001400] 
+  0x08001248:  4285         CMP        R5, R0
+  0x0800124A:  D108         BNE        .L14                     ; 0x0800125E
+  0x0800124C:  486D         LDR        R0, =0x40021000          ; [PC, #0x01B4] [0x08001404] 
+  0x0800124E:  6D40         LDR        R0, [R0, #84]
+  0x08001250:  0780         LSLS       R0, R0, #30
+  0x08001252:  0F00         LSRS       R0, R0, #28
+  0x08001254:  4A74         LDR        R2, =0x08005124          ; [PC, #0x01D0] [0x08001428] 
+  0x08001256:  5812         LDR        R2, [R2, R0]
+  0x08001258:  E002         B          .L15                     ; 0x08001260
+
.L13:
+  0x0800125A:  2200         MOVS       R2, #0
+  0x0800125C:  E000         B          .L15                     ; 0x08001260
+
.L14:
+  0x0800125E:  2210         MOVS       R2, #16
+
.L15:
+  0x08001260:  03E0         LSLS       R0, R4, #15
+  0x08001262:  4281         CMP        R1, R0
+  0x08001264:  D10E         BNE        .L17                     ; 0x08001284
+  0x08001266:  2A08         CMP        R2, #8
+  0x08001268:  D900         BLS        .L16                     ; 0x0800126C
+  0x0800126A:  E08C         B          .L25                     ; 0x08001386
+
.L16:
+  0x0800126C:  447A         ADD        R2, PC
+  0x0800126E:  7912         LDRB       R2, [R2, #4]
+  0x08001270:  0052         LSLS       R2, R2, #1
+  0x08001272:  4497         ADD        PC, R2
+  0x08001274:  04           DC.B       0x04                     ; '\x04'
+  0x08001275:  88           DC.B       0x88                     ; '\x88'
+  0x08001276:  17           DC.B       0x17                     ; '\x17'
+  0x08001277:  88           DC.B       0x88                     ; '\x88'
+  0x08001278:  29           DC.B       0x29                     ; ')'
+  0x08001279:  88           DC.B       0x88                     ; '\x88'
+  0x0800127A:  88           DC.B       0x88                     ; '\x88'
+  0x0800127B:  88           DC.B       0x88                     ; '\x88'
+  0x0800127C:  2E           DC.B       0x2E                     ; '.'
+  0x0800127D:  00           DC.B       0x00                     ; '\0'
+  0x0800127E:  F7FF FDA5    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x08001282:  E023         B          .L19                     ; 0x080012CC
+
.L17:
+  0x08001284:  2A08         CMP        R2, #8
+  0x08001286:  D900         BLS        .L18                     ; 0x0800128A
+  0x08001288:  E07D         B          .L25                     ; 0x08001386
+
.L18:
+  0x0800128A:  46C0         NOP
+  0x0800128C:  447A         ADD        R2, PC
+  0x0800128E:  7912         LDRB       R2, [R2, #4]
+  0x08001290:  0052         LSLS       R2, R2, #1
+  0x08001292:  4497         ADD        PC, R2
+  0x08001294:  04           DC.B       0x04                     ; '\x04'
+  0x08001295:  78           DC.B       0x78                     ; 'x'
+  0x08001296:  10           DC.B       0x10                     ; '\x10'
+  0x08001297:  78           DC.B       0x78                     ; 'x'
+  0x08001298:  33           DC.B       0x33                     ; '3'
+  0x08001299:  78           DC.B       0x78                     ; 'x'
+  0x0800129A:  78           DC.B       0x78                     ; 'x'
+  0x0800129B:  78           DC.B       0x78                     ; 'x'
+  0x0800129C:  38           DC.B       0x38                     ; '8'
+  0x0800129D:  00           DC.B       0x00                     ; '\0'
+  0x0800129E:  F7FF FD95    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x080012A2:  E02D         B          .L21                     ; 0x08001300
+  0x080012A4:  4857         LDR        R0, =0x40021000          ; [PC, #0x015C] [0x08001404] 
+  0x080012A6:  6800         LDR        R0, [R0]
+  0x080012A8:  0600         LSLS       R0, R0, #24
+  0x080012AA:  0F40         LSRS       R0, R0, #29
+  0x080012AC:  1C41         ADDS       R1, R0, #1
+  0x080012AE:  485F         LDR        R0, =0x02DC6C00          ; [PC, #0x017C] [0x0800142C] 
+  0x080012B0:  F004 FE9B    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080012B4:  E00D         B          .L20                     ; 0x080012D2
+  0x080012B6:  4853         LDR        R0, =0x40021000          ; [PC, #0x014C] [0x08001404] 
+  0x080012B8:  6800         LDR        R0, [R0]
+  0x080012BA:  0600         LSLS       R0, R0, #24
+  0x080012BC:  0F40         LSRS       R0, R0, #29
+  0x080012BE:  1C41         ADDS       R1, R0, #1
+  0x080012C0:  485A         LDR        R0, =0x02DC6C00          ; [PC, #0x0168] [0x0800142C] 
+  0x080012C2:  F004 FE92    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080012C6:  E01E         B          .L22                     ; 0x08001306
+  0x080012C8:  F7FF FD56    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+
.L19:
+  0x080012CC:  2800         CMP        R0, #0
+  0x080012CE:  D02B         BEQ        .L24                     ; 0x08001328
+  0x080012D0:  6A77         LDR        R7, [R6, #36]
+
.L20:
+  0x080012D2:  0079         LSLS       R1, R7, #1
+  0x080012D4:  4A56         LDR        R2, =UARTPrescTable      ; [PC, #0x0158] [0x08001430] =0x08005E52 
+  0x080012D6:  5A51         LDRH       R1, [R2, R1]
+  0x080012D8:  F004 FE87    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080012DC:  0040         LSLS       R0, R0, #1
+  0x080012DE:  6871         LDR        R1, [R6, #4]
+  0x080012E0:  084A         LSRS       R2, R1, #1
+  0x080012E2:  1810         ADDS       R0, R2, R0
+  0x080012E4:  F004 FE81    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x080012E8:  4602         MOV        R2, R0
+  0x080012EA:  3A10         SUBS       R2, #16
+  0x080012EC:  4951         LDR        R1, =0x0000FFF0          ; [PC, #0x0144] [0x08001434] 
+  0x080012EE:  428A         CMP        R2, R1
+  0x080012F0:  D249         BCS        .L25                     ; 0x08001386
+  0x080012F2:  4001         ANDS       R1, R0
+  0x080012F4:  0700         LSLS       R0, R0, #28
+  0x080012F6:  0F40         LSRS       R0, R0, #29
+  0x080012F8:  4308         ORRS       R0, R1
+  0x080012FA:  E013         B          .L23                     ; 0x08001324
+  0x080012FC:  F7FF FD3C    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+
.L21:
+  0x08001300:  2800         CMP        R0, #0
+  0x08001302:  D011         BEQ        .L24                     ; 0x08001328
+  0x08001304:  6A77         LDR        R7, [R6, #36]
+
.L22:
+  0x08001306:  0079         LSLS       R1, R7, #1
+  0x08001308:  4A49         LDR        R2, =UARTPrescTable      ; [PC, #0x0124] [0x08001430] =0x08005E52 
+  0x0800130A:  5A51         LDRH       R1, [R2, R1]
+  0x0800130C:  F004 FE6D    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08001310:  6871         LDR        R1, [R6, #4]
+  0x08001312:  084A         LSRS       R2, R1, #1
+  0x08001314:  1810         ADDS       R0, R2, R0
+  0x08001316:  F004 FE68    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x0800131A:  4601         MOV        R1, R0
+  0x0800131C:  3910         SUBS       R1, #16
+  0x0800131E:  4A45         LDR        R2, =0x0000FFF0          ; [PC, #0x0114] [0x08001434] 
+  0x08001320:  4291         CMP        R1, R2
+  0x08001322:  D230         BCS        .L25                     ; 0x08001386
+
.L23:
+  0x08001324:  6831         LDR        R1, [R6]
+  0x08001326:  60C8         STR        R0, [R1, #12]
+
.L24:
+  0x08001328:  2009         MOVS       R0, #9
+  0x0800132A:  9001         STR        R0, [SP, #4]
+  0x0800132C:  02C1         LSLS       R1, R0, #11
+  0x0800132E:  6830         LDR        R0, [R6]
+  0x08001330:  6842         LDR        R2, [R0, #4]
+  0x08001332:  438A         BICS       R2, R1
+  0x08001334:  6042         STR        R2, [R0, #4]
+  0x08001336:  6881         LDR        R1, [R0, #8]
+  0x08001338:  222A         MOVS       R2, #42
+  0x0800133A:  4391         BICS       R1, R2
+  0x0800133C:  6081         STR        R1, [R0, #8]
+  0x0800133E:  6801         LDR        R1, [R0]
+  0x08001340:  4321         ORRS       R1, R4
+  0x08001342:  6001         STR        R1, [R0]
+  0x08001344:  2190         MOVS       R1, #144
+  0x08001346:  2700         MOVS       R7, #0
+  0x08001348:  5077         STR        R7, [R6, R1]
+  0x0800134A:  6777         STR        R7, [R6, #116]
+  0x0800134C:  67B7         STR        R7, [R6, #120]
+  0x0800134E:  493A         LDR        R1, =0x00010001          ; [PC, #232] [0x08001438] 
+  0x08001350:  66B1         STR        R1, [R6, #104]
+  0x08001352:  493A         LDR        R1, =uwTick              ; [PC, #232] [0x0800143C] =0x2000068C 
+  0x08001354:  680D         LDR        R5, [R1]
+  0x08001356:  6801         LDR        R1, [R0]
+  0x08001358:  0709         LSLS       R1, R1, #28
+  0x0800135A:  D51B         BPL        .L27                     ; 0x08001394
+  0x0800135C:  0560         LSLS       R0, R4, #21
+  0x0800135E:  4629         MOV        R1, R5
+  0x08001360:  F000 F86E    BL         UART_WaitOnFlagUntilTimeout ; 0x08001440
+  0x08001364:  2800         CMP        R0, #0
+  0x08001366:  D014         BEQ        .L26                     ; 0x08001392
+  0x08001368:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800136C:  F384 8810    MSR        PRIMASK, R4
+  0x08001370:  6831         LDR        R1, [R6]
+  0x08001372:  680A         LDR        R2, [R1]
+  0x08001374:  2380         MOVS       R3, #128
+  0x08001376:  439A         BICS       R2, R3
+  0x08001378:  600A         STR        R2, [R1]
+  0x0800137A:  F380 8810    MSR        PRIMASK, R0
+  0x0800137E:  2020         MOVS       R0, #32
+  0x08001380:  9C02         LDR        R4, [SP, #8]
+  0x08001382:  9A03         LDR        R2, [SP, #12]
+  0x08001384:  E032         B          .L29                     ; 0x080013EC
+
.L25:
+  0x08001386:  2000         MOVS       R0, #0
+  0x08001388:  6770         STR        R0, [R6, #116]
+  0x0800138A:  67B0         STR        R0, [R6, #120]
+  0x0800138C:  482A         LDR        R0, =0x00010001          ; [PC, #168] [0x08001438] 
+  0x0800138E:  66B0         STR        R0, [R6, #104]
+  0x08001390:  E02F         B          .L30                     ; 0x080013F2
+
.L26:
+  0x08001392:  6830         LDR        R0, [R6]
+
.L27:
+  0x08001394:  6800         LDR        R0, [R0]
+  0x08001396:  0740         LSLS       R0, R0, #29
+  0x08001398:  D51F         BPL        .L28                     ; 0x080013DA
+  0x0800139A:  05A0         LSLS       R0, R4, #22
+  0x0800139C:  4629         MOV        R1, R5
+  0x0800139E:  F000 F84F    BL         UART_WaitOnFlagUntilTimeout ; 0x08001440
+  0x080013A2:  2800         CMP        R0, #0
+  0x080013A4:  D019         BEQ        .L28                     ; 0x080013DA
+  0x080013A6:  F3EF 8010    MRS        R0, PRIMASK
+  0x080013AA:  F384 8810    MSR        PRIMASK, R4
+  0x080013AE:  9901         LDR        R1, [SP, #4]
+  0x080013B0:  0149         LSLS       R1, R1, #5
+  0x080013B2:  6832         LDR        R2, [R6]
+  0x080013B4:  6813         LDR        R3, [R2]
+  0x080013B6:  438B         BICS       R3, R1
+  0x080013B8:  6013         STR        R3, [R2]
+  0x080013BA:  F380 8810    MSR        PRIMASK, R0
+  0x080013BE:  F3EF 8010    MRS        R0, PRIMASK
+  0x080013C2:  F384 8810    MSR        PRIMASK, R4
+  0x080013C6:  6831         LDR        R1, [R6]
+  0x080013C8:  688A         LDR        R2, [R1, #8]
+  0x080013CA:  43A2         BICS       R2, R4
+  0x080013CC:  608A         STR        R2, [R1, #8]
+  0x080013CE:  F380 8810    MSR        PRIMASK, R0
+  0x080013D2:  2020         MOVS       R0, #32
+  0x080013D4:  228C         MOVS       R2, #140
+  0x080013D6:  9C02         LDR        R4, [SP, #8]
+  0x080013D8:  E008         B          .L29                     ; 0x080013EC
+
.L28:
+  0x080013DA:  2088         MOVS       R0, #136
+  0x080013DC:  2120         MOVS       R1, #32
+  0x080013DE:  5031         STR        R1, [R6, R0]
+  0x080013E0:  208C         MOVS       R0, #140
+  0x080013E2:  5031         STR        R1, [R6, R0]
+  0x080013E4:  66F7         STR        R7, [R6, #108]
+  0x080013E6:  2270         MOVS       R2, #112
+  0x080013E8:  4638         MOV        R0, R7
+  0x080013EA:  463C         MOV        R4, R7
+
.L29:
+  0x080013EC:  2184         MOVS       R1, #132
+  0x080013EE:  5477         STRB       R7, [R6, R1]
+  0x080013F0:  50B0         STR        R0, [R6, R2]
+
.L30:
+  0x080013F2:  4620         MOV        R0, R4
+  0x080013F4:  B011         ADD        SP, SP, #68
+  0x080013F6:  BDF0         POP        {R4-R7, PC}
+
.L31:
+  0x080013F8:  F004 FD29    BL         Error_Handler            ; 0x08005E4E
+  0x080013FC:  200003BC     DC.W       huart1
+  0x08001400:  40013800     DC.W       0x40013800
+  0x08001404:  40021000     DC.W       0x40021000
+  0x08001408:  20000510     DC.W       hdma_usart1_rx
+  0x0800140C:  4002001C     DC.W       0x4002001C
+  0x08001410:  200004B4     DC.W       hdma_usart1_tx
+  0x08001414:  E000E418     DC.W       0xE000E418
+  0x08001418:  E000E100     DC.W       0xE000E100
+  0x0800141C:  CFFF69F3     DC.W       0xCFFF69F3
+  0x08001420:  11FFF4FF     DC.W       0x11FFF4FF
+  0x08001424:  40004400     DC.W       0x40004400
+  0x08001428:  08005124     DC.W       08005124               ; R_ARM_ABS32
+  0x0800142C:  02DC6C00     DC.W       0x02DC6C00
+  0x08001430:  08005E52     DC.W       UARTPrescTable
+  0x08001434:  0000FFF0     DC.W       0x0000FFF0
+  0x08001438:  00010001     DC.W       0x00010001
+  0x0800143C:  2000068C     DC.W       uwTick
+
+

Section .text.UART_WaitOnFlagUntilTimeout from PowerPro_lto.o, size=96, align=4

+
+
UART_WaitOnFlagUntilTimeout:
+  0x08001440:  B570         PUSH       {R4-R6, LR}
+  0x08001442:  4D15         LDR        R5, =huart1              ; [PC, #84] [0x08001498] =0x200003BC 
+  0x08001444:  682A         LDR        R2, [R5]
+  0x08001446:  2401         MOVS       R4, #1
+  0x08001448:  02E3         LSLS       R3, R4, #11
+
.L1:
+  0x0800144A:  69D6         LDR        R6, [R2, #28]
+  0x0800144C:  4006         ANDS       R6, R0
+  0x0800144E:  4286         CMP        R6, R0
+  0x08001450:  D010         BEQ        .L2                      ; 0x08001474
+  0x08001452:  4E12         LDR        R6, =uwTick              ; [PC, #72] [0x0800149C] =0x2000068C 
+  0x08001454:  6836         LDR        R6, [R6]
+  0x08001456:  1A76         SUBS       R6, R6, R1
+  0x08001458:  0E76         LSRS       R6, R6, #25
+  0x0800145A:  D10D         BNE        .L3                      ; 0x08001478
+  0x0800145C:  6816         LDR        R6, [R2]
+  0x0800145E:  0776         LSLS       R6, R6, #29
+  0x08001460:  D5F3         BPL        .L1                      ; 0x0800144A
+  0x08001462:  69D6         LDR        R6, [R2, #28]
+  0x08001464:  0736         LSLS       R6, R6, #28
+  0x08001466:  D409         BMI        .L4                      ; 0x0800147C
+  0x08001468:  69D6         LDR        R6, [R2, #28]
+  0x0800146A:  421E         TST        R6, R3
+  0x0800146C:  D0ED         BEQ        .L1                      ; 0x0800144A
+  0x0800146E:  2403         MOVS       R4, #3
+  0x08001470:  2620         MOVS       R6, #32
+  0x08001472:  E005         B          .L5                      ; 0x08001480
+
.L2:
+  0x08001474:  2400         MOVS       R4, #0
+  0x08001476:  E00C         B          .L6                      ; 0x08001492
+
.L3:
+  0x08001478:  2403         MOVS       R4, #3
+  0x0800147A:  E00A         B          .L6                      ; 0x08001492
+
.L4:
+  0x0800147C:  2308         MOVS       R3, #8
+  0x0800147E:  461E         MOV        R6, R3
+
.L5:
+  0x08001480:  6213         STR        R3, [R2, #32]
+  0x08001482:  4628         MOV        R0, R5
+  0x08001484:  F000 F80C    BL         UART_EndRxTransfer       ; 0x080014A0
+  0x08001488:  2084         MOVS       R0, #132
+  0x0800148A:  2100         MOVS       R1, #0
+  0x0800148C:  5429         STRB       R1, [R5, R0]
+  0x0800148E:  2090         MOVS       R0, #144
+  0x08001490:  502E         STR        R6, [R5, R0]
+
.L6:
+  0x08001492:  4620         MOV        R0, R4
+  0x08001494:  BD70         POP        {R4-R6, PC}
+  0x08001496:  46C0         NOP
+  0x08001498:  200003BC     DC.W       huart1
+  0x0800149C:  2000068C     DC.W       uwTick
+
+

Section .text.UART_EndRxTransfer from PowerPro_lto.o, size=96, align=4

+
+
UART_EndRxTransfer:
+  0x080014A0:  B530         PUSH       {R4-R5, LR}
+  0x080014A2:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014A6:  2101         MOVS       R1, #1
+  0x080014A8:  F381 8810    MSR        PRIMASK, R1
+  0x080014AC:  2309         MOVS       R3, #9
+  0x080014AE:  015B         LSLS       R3, R3, #5
+  0x080014B0:  6804         LDR        R4, [R0]
+  0x080014B2:  6825         LDR        R5, [R4]
+  0x080014B4:  439D         BICS       R5, R3
+  0x080014B6:  6025         STR        R5, [R4]
+  0x080014B8:  F382 8810    MSR        PRIMASK, R2
+  0x080014BC:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014C0:  F381 8810    MSR        PRIMASK, R1
+  0x080014C4:  6803         LDR        R3, [R0]
+  0x080014C6:  689C         LDR        R4, [R3, #8]
+  0x080014C8:  4D0C         LDR        R5, =0xEFFFFFFE          ; [PC, #48] [0x080014FC] 
+  0x080014CA:  4025         ANDS       R5, R4
+  0x080014CC:  609D         STR        R5, [R3, #8]
+  0x080014CE:  F382 8810    MSR        PRIMASK, R2
+  0x080014D2:  6EC2         LDR        R2, [R0, #108]
+  0x080014D4:  2A01         CMP        R2, #1
+  0x080014D6:  D10A         BNE        .L1                      ; 0x080014EE
+  0x080014D8:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014DC:  F381 8810    MSR        PRIMASK, R1
+  0x080014E0:  6801         LDR        R1, [R0]
+  0x080014E2:  680B         LDR        R3, [R1]
+  0x080014E4:  2410         MOVS       R4, #16
+  0x080014E6:  43A3         BICS       R3, R4
+  0x080014E8:  600B         STR        R3, [R1]
+  0x080014EA:  F382 8810    MSR        PRIMASK, R2
+
.L1:
+  0x080014EE:  218C         MOVS       R1, #140
+  0x080014F0:  2220         MOVS       R2, #32
+  0x080014F2:  5042         STR        R2, [R0, R1]
+  0x080014F4:  2100         MOVS       R1, #0
+  0x080014F6:  6741         STR        R1, [R0, #116]
+  0x080014F8:  66C1         STR        R1, [R0, #108]
+  0x080014FA:  BD30         POP        {R4-R5, PC}
+  0x080014FC:  EFFFFFFE     DC.W       0xEFFFFFFE
+
+

Section .text.UART_DMATransmitCplt from PowerPro_lto.o, size=80, align=4

+
+
UART_DMATransmitCplt:
+  0x08001500:  B530         PUSH       {R4-R5, LR}
+  0x08001502:  6A81         LDR        R1, [R0, #40]
+  0x08001504:  6800         LDR        R0, [R0]
+  0x08001506:  6800         LDR        R0, [R0]
+  0x08001508:  0680         LSLS       R0, R0, #26
+  0x0800150A:  D41A         BMI        .L1                      ; 0x08001542
+  0x0800150C:  2056         MOVS       R0, #86
+  0x0800150E:  2200         MOVS       R2, #0
+  0x08001510:  520A         STRH       R2, [R1, R0]
+  0x08001512:  F3EF 8010    MRS        R0, PRIMASK
+  0x08001516:  2201         MOVS       R2, #1
+  0x08001518:  F382 8810    MSR        PRIMASK, R2
+  0x0800151C:  680B         LDR        R3, [R1]
+  0x0800151E:  689C         LDR        R4, [R3, #8]
+  0x08001520:  2580         MOVS       R5, #128
+  0x08001522:  43AC         BICS       R4, R5
+  0x08001524:  609C         STR        R4, [R3, #8]
+  0x08001526:  F380 8810    MSR        PRIMASK, R0
+  0x0800152A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800152E:  F382 8810    MSR        PRIMASK, R2
+  0x08001532:  6809         LDR        R1, [R1]
+  0x08001534:  680A         LDR        R2, [R1]
+  0x08001536:  2340         MOVS       R3, #64
+  0x08001538:  4313         ORRS       R3, R2
+  0x0800153A:  600B         STR        R3, [R1]
+  0x0800153C:  F380 8810    MSR        PRIMASK, R0
+  0x08001540:  BD30         POP        {R4-R5, PC}
+
.L1:
+  0x08001542:  4802         LDR        R0, =0x20000026          ; [PC, #8] [0x0800154C] 
+  0x08001544:  2100         MOVS       R1, #0
+  0x08001546:  7001         STRB       R1, [R0]
+  0x08001548:  BD30         POP        {R4-R5, PC}
+  0x0800154A:  46C0         NOP
+  0x0800154C:  20000026     DC.W       20000026               ; R_ARM_ABS32
+
+

Section .text.HAL_UART_Receive_DMA from PowerPro_lto.o, size=248, align=4

+
+
HAL_UART_Receive_DMA:
+  0x08001550:  B5F0         PUSH       {R4-R7, LR}
+  0x08001552:  B083         SUB        SP, SP, #12
+  0x08001554:  4604         MOV        R4, R0
+  0x08001556:  4607         MOV        R7, R0
+  0x08001558:  3780         ADDS       R7, #128
+  0x0800155A:  68F8         LDR        R0, [R7, #12]
+  0x0800155C:  2820         CMP        R0, #32
+  0x0800155E:  D142         BNE        .L3                      ; 0x080015E6
+  0x08001560:  000A         MOVS       R2, R1
+  0x08001562:  D042         BEQ        .L4                      ; 0x080015EA
+  0x08001564:  2301         MOVS       R3, #1
+  0x08001566:  0318         LSLS       R0, R3, #12
+  0x08001568:  68A1         LDR        R1, [R4, #8]
+  0x0800156A:  4281         CMP        R1, R0
+  0x0800156C:  D104         BNE        .L1                      ; 0x08001578
+  0x0800156E:  6920         LDR        R0, [R4, #16]
+  0x08001570:  2800         CMP        R0, #0
+  0x08001572:  D101         BNE        .L1                      ; 0x08001578
+  0x08001574:  07D0         LSLS       R0, R2, #31
+  0x08001576:  D138         BNE        .L4                      ; 0x080015EA
+
.L1:
+  0x08001578:  4620         MOV        R0, R4
+  0x0800157A:  305C         ADDS       R0, #92
+  0x0800157C:  2500         MOVS       R5, #0
+  0x0800157E:  66E5         STR        R5, [R4, #108]
+  0x08001580:  6821         LDR        R1, [R4]
+  0x08001582:  6849         LDR        R1, [R1, #4]
+  0x08001584:  0209         LSLS       R1, R1, #8
+  0x08001586:  9302         STR        R3, [SP, #8]
+  0x08001588:  D50D         BPL        .L2                      ; 0x080015A6
+  0x0800158A:  F3EF 8110    MRS        R1, PRIMASK
+  0x0800158E:  9101         STR        R1, [SP, #4]
+  0x08001590:  F383 8810    MSR        PRIMASK, R3
+  0x08001594:  069B         LSLS       R3, R3, #26
+  0x08001596:  6826         LDR        R6, [R4]
+  0x08001598:  6831         LDR        R1, [R6]
+  0x0800159A:  4319         ORRS       R1, R3
+  0x0800159C:  9B02         LDR        R3, [SP, #8]
+  0x0800159E:  6031         STR        R1, [R6]
+  0x080015A0:  9901         LDR        R1, [SP, #4]
+  0x080015A2:  F381 8810    MSR        PRIMASK, R1
+
.L2:
+  0x080015A6:  613D         STR        R5, [R7, #16]
+  0x080015A8:  65A2         STR        R2, [R4, #88]
+  0x080015AA:  021E         LSLS       R6, R3, #8
+  0x080015AC:  8006         STRH       R6, [R0]
+  0x080015AE:  2022         MOVS       R0, #34
+  0x080015B0:  60F8         STR        R0, [R7, #12]
+  0x080015B2:  6838         LDR        R0, [R7]
+  0x080015B4:  2800         CMP        R0, #0
+  0x080015B6:  D01A         BEQ        .L5                      ; 0x080015EE
+  0x080015B8:  4B21         LDR        R3, =UART_DMARxHalfCplt  ; [PC, #132] [0x08001640] =0x08005E1B 
+  0x080015BA:  4631         MOV        R1, R6
+  0x080015BC:  4E21         LDR        R6, =UART_DMAReceiveCplt ; [PC, #132] [0x08001644] =0x08005D73 
+  0x080015BE:  62C6         STR        R6, [R0, #44]
+  0x080015C0:  460E         MOV        R6, R1
+  0x080015C2:  6303         STR        R3, [R0, #48]
+  0x080015C4:  491D         LDR        R1, =UART_DMAError       ; [PC, #116] [0x0800163C] =0x08005779 
+  0x080015C6:  6341         STR        R1, [R0, #52]
+  0x080015C8:  6385         STR        R5, [R0, #56]
+  0x080015CA:  6821         LDR        R1, [R4]
+  0x080015CC:  3124         ADDS       R1, #36
+  0x080015CE:  4633         MOV        R3, R6
+  0x080015D0:  F7FF FA28    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080015D4:  9902         LDR        R1, [SP, #8]
+  0x080015D6:  2800         CMP        R0, #0
+  0x080015D8:  D009         BEQ        .L5                      ; 0x080015EE
+  0x080015DA:  2010         MOVS       R0, #16
+  0x080015DC:  6138         STR        R0, [R7, #16]
+  0x080015DE:  2020         MOVS       R0, #32
+  0x080015E0:  60F8         STR        R0, [R7, #12]
+  0x080015E2:  460D         MOV        R5, R1
+  0x080015E4:  E027         B          .L7                      ; 0x08001636
+
.L3:
+  0x080015E6:  2502         MOVS       R5, #2
+  0x080015E8:  E025         B          .L7                      ; 0x08001636
+
.L4:
+  0x080015EA:  2501         MOVS       R5, #1
+  0x080015EC:  E023         B          .L7                      ; 0x08001636
+
.L5:
+  0x080015EE:  6920         LDR        R0, [R4, #16]
+  0x080015F0:  2800         CMP        R0, #0
+  0x080015F2:  D00A         BEQ        .L6                      ; 0x0800160A
+  0x080015F4:  F3EF 8010    MRS        R0, PRIMASK
+  0x080015F8:  2101         MOVS       R1, #1
+  0x080015FA:  F381 8810    MSR        PRIMASK, R1
+  0x080015FE:  6821         LDR        R1, [R4]
+  0x08001600:  680A         LDR        R2, [R1]
+  0x08001602:  4332         ORRS       R2, R6
+  0x08001604:  600A         STR        R2, [R1]
+  0x08001606:  F380 8810    MSR        PRIMASK, R0
+
.L6:
+  0x0800160A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800160E:  2101         MOVS       R1, #1
+  0x08001610:  F381 8810    MSR        PRIMASK, R1
+  0x08001614:  6822         LDR        R2, [R4]
+  0x08001616:  6893         LDR        R3, [R2, #8]
+  0x08001618:  430B         ORRS       R3, R1
+  0x0800161A:  6093         STR        R3, [R2, #8]
+  0x0800161C:  F380 8810    MSR        PRIMASK, R0
+  0x08001620:  F3EF 8010    MRS        R0, PRIMASK
+  0x08001624:  F381 8810    MSR        PRIMASK, R1
+  0x08001628:  6821         LDR        R1, [R4]
+  0x0800162A:  688A         LDR        R2, [R1, #8]
+  0x0800162C:  2340         MOVS       R3, #64
+  0x0800162E:  4313         ORRS       R3, R2
+  0x08001630:  608B         STR        R3, [R1, #8]
+  0x08001632:  F380 8810    MSR        PRIMASK, R0
+
.L7:
+  0x08001636:  4628         MOV        R0, R5
+  0x08001638:  B003         ADD        SP, SP, #12
+  0x0800163A:  BDF0         POP        {R4-R7, PC}
+  0x0800163C:  08005779     DC.W       UART_DMAError
+  0x08001640:  08005E1B     DC.W       UART_DMARxHalfCplt
+  0x08001644:  08005D73     DC.W       UART_DMAReceiveCplt
+
+

Section .text.UARTEx_SetNbDataToProcess from PowerPro_lto.o, size=84, align=4

+
+
UARTEx_SetNbDataToProcess:
+  0x08001648:  B5F0         PUSH       {R4-R7, LR}
+  0x0800164A:  B081         SUB        SP, SP, #4
+  0x0800164C:  4D10         LDR        R5, =huart1              ; [PC, #64] [0x08001690] =0x200003BC 
+  0x0800164E:  6E68         LDR        R0, [R5, #100]
+  0x08001650:  2800         CMP        R0, #0
+  0x08001652:  D015         BEQ        .L1                      ; 0x08001680
+  0x08001654:  6828         LDR        R0, [R5]
+  0x08001656:  6881         LDR        R1, [R0, #8]
+  0x08001658:  9100         STR        R1, [SP, #0]
+  0x0800165A:  6880         LDR        R0, [R0, #8]
+  0x0800165C:  0F40         LSRS       R0, R0, #29
+  0x0800165E:  4F0D         LDR        R7, =UARTEx_SetNbDataToProcess.denominator ; [PC, #52] [0x08001694] =0x080067D4 
+  0x08001660:  5C39         LDRB       R1, [R7, R0]
+  0x08001662:  4E0D         LDR        R6, =UARTEx_SetNbDataToProcess.numerator ; [PC, #52] [0x08001698] =0x080067CC 
+  0x08001664:  5C30         LDRB       R0, [R6, R0]
+  0x08001666:  00C0         LSLS       R0, R0, #3
+  0x08001668:  F004 FCBF    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x0800166C:  4604         MOV        R4, R0
+  0x0800166E:  9800         LDR        R0, [SP, #0]
+  0x08001670:  0100         LSLS       R0, R0, #4
+  0x08001672:  0F40         LSRS       R0, R0, #29
+  0x08001674:  5C39         LDRB       R1, [R7, R0]
+  0x08001676:  5C30         LDRB       R0, [R6, R0]
+  0x08001678:  00C0         LSLS       R0, R0, #3
+  0x0800167A:  F004 FCB6    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x0800167E:  E001         B          .L2                      ; 0x08001684
+
.L1:
+  0x08001680:  2401         MOVS       R4, #1
+  0x08001682:  4620         MOV        R0, R4
+
.L2:
+  0x08001684:  2168         MOVS       R1, #104
+  0x08001686:  5268         STRH       R0, [R5, R1]
+  0x08001688:  206A         MOVS       R0, #106
+  0x0800168A:  522C         STRH       R4, [R5, R0]
+  0x0800168C:  B001         ADD        SP, SP, #4
+  0x0800168E:  BDF0         POP        {R4-R7, PC}
+  0x08001690:  200003BC     DC.W       huart1
+  0x08001694:  080067D4     DC.W       UARTEx_SetNbDataToProcess.denominator
+  0x08001698:  080067CC     DC.W       UARTEx_SetNbDataToProcess.numerator
+
+

Section .text.EEPROM_Write from PowerPro_lto.o, size=280, align=4

+
+
EEPROM_Write:
+  0x0800169C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800169E:  B08B         SUB        SP, SP, #44
+  0x080016A0:  493F         LDR        R1, =0x08007800          ; [PC, #252] [0x080017A0] 
+  0x080016A2:  2210         MOVS       R2, #16
+  0x080016A4:  9009         STR        R0, [SP, #36]
+  0x080016A6:  F004 FADC    BL         memcmp                   ; 0x08005C62
+  0x080016AA:  2800         CMP        R0, #0
+  0x080016AC:  D029         BEQ        .L4                      ; 0x08001702
+  0x080016AE:  F7FF FA95    BL         HAL_FLASH_Unlock         ; 0x08000BDC
+  0x080016B2:  4F3C         LDR        R7, =pFlash.0            ; [PC, #240] [0x080017A4] =0x20000738 
+  0x080016B4:  7838         LDRB       R0, [R7]
+  0x080016B6:  2800         CMP        R0, #0
+  0x080016B8:  4E3B         LDR        R6, =0x40022014          ; [PC, #236] [0x080017A8] 
+  0x080016BA:  D11C         BNE        .L3                      ; 0x080016F6
+  0x080016BC:  2501         MOVS       R5, #1
+  0x080016BE:  703D         STRB       R5, [R7]
+  0x080016C0:  F7FF FA64    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x080016C4:  2800         CMP        R0, #0
+  0x080016C6:  D114         BNE        .L2                      ; 0x080016F2
+  0x080016C8:  200F         MOVS       R0, #15
+  0x080016CA:  43C0         MVNS       R0, R0
+  0x080016CC:  4604         MOV        R4, R0
+
.L1:
+  0x080016CE:  6831         LDR        R1, [R6]
+  0x080016D0:  3408         ADDS       R4, #8
+  0x080016D2:  D018         BEQ        .L5                      ; 0x08001706
+  0x080016D4:  4A35         LDR        R2, =0xFFFEFF85          ; [PC, #212] [0x080017AC] 
+  0x080016D6:  4011         ANDS       R1, R2
+  0x080016D8:  1840         ADDS       R0, R0, R1
+  0x080016DA:  4935         LDR        R1, =0x0001008A          ; [PC, #212] [0x080017B0] 
+  0x080016DC:  1840         ADDS       R0, R0, R1
+  0x080016DE:  6030         STR        R0, [R6]
+  0x080016E0:  F7FF FA54    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x080016E4:  2800         CMP        R0, #0
+  0x080016E6:  4620         MOV        R0, R4
+  0x080016E8:  D0F1         BEQ        .L1                      ; 0x080016CE
+  0x080016EA:  6830         LDR        R0, [R6]
+  0x080016EC:  2102         MOVS       R1, #2
+  0x080016EE:  4388         BICS       R0, R1
+  0x080016F0:  6030         STR        R0, [R6]
+
.L2:
+  0x080016F2:  2000         MOVS       R0, #0
+  0x080016F4:  7038         STRB       R0, [R7]
+
.L3:
+  0x080016F6:  2001         MOVS       R0, #1
+  0x080016F8:  07C0         LSLS       R0, R0, #31
+  0x080016FA:  6831         LDR        R1, [R6]
+  0x080016FC:  4301         ORRS       R1, R0
+  0x080016FE:  6031         STR        R1, [R6]
+  0x08001700:  6830         LDR        R0, [R6]
+
.L4:
+  0x08001702:  B00B         ADD        SP, SP, #44
+  0x08001704:  BDF0         POP        {R4-R7, PC}
+
.L5:
+  0x08001706:  2002         MOVS       R0, #2
+  0x08001708:  4381         BICS       R1, R0
+  0x0800170A:  6031         STR        R1, [R6]
+  0x0800170C:  2200         MOVS       R2, #0
+  0x0800170E:  703A         STRB       R2, [R7]
+  0x08001710:  4823         LDR        R0, =0x08007800          ; [PC, #140] [0x080017A0] 
+  0x08001712:  1D00         ADDS       R0, R0, #4
+
.L6:
+  0x08001714:  900A         STR        R0, [SP, #40]
+  0x08001716:  2A0F         CMP        R2, #15
+  0x08001718:  D8ED         BHI        .L3                      ; 0x080016F6
+  0x0800171A:  703D         STRB       R5, [R7]
+  0x0800171C:  9909         LDR        R1, [SP, #36]
+  0x0800171E:  1888         ADDS       R0, R1, R2
+  0x08001720:  7903         LDRB       R3, [R0, #4]
+  0x08001722:  9304         STR        R3, [SP, #16]
+  0x08001724:  462C         MOV        R4, R5
+  0x08001726:  7945         LDRB       R5, [R0, #5]
+  0x08001728:  7983         LDRB       R3, [R0, #6]
+  0x0800172A:  9302         STR        R3, [SP, #8]
+  0x0800172C:  79C3         LDRB       R3, [R0, #7]
+  0x0800172E:  9301         STR        R3, [SP, #4]
+  0x08001730:  9208         STR        R2, [SP, #32]
+  0x08001732:  5C89         LDRB       R1, [R1, R2]
+  0x08001734:  9107         STR        R1, [SP, #28]
+  0x08001736:  7841         LDRB       R1, [R0, #1]
+  0x08001738:  9103         STR        R1, [SP, #12]
+  0x0800173A:  7881         LDRB       R1, [R0, #2]
+  0x0800173C:  9106         STR        R1, [SP, #24]
+  0x0800173E:  78C0         LDRB       R0, [R0, #3]
+  0x08001740:  9005         STR        R0, [SP, #20]
+  0x08001742:  F7FF FA23    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x08001746:  2800         CMP        R0, #0
+  0x08001748:  D1D3         BNE        .L2                      ; 0x080016F2
+  0x0800174A:  0228         LSLS       R0, R5, #8
+  0x0800174C:  9904         LDR        R1, [SP, #16]
+  0x0800174E:  1840         ADDS       R0, R0, R1
+  0x08001750:  9902         LDR        R1, [SP, #8]
+  0x08001752:  0409         LSLS       R1, R1, #16
+  0x08001754:  9A01         LDR        R2, [SP, #4]
+  0x08001756:  0612         LSLS       R2, R2, #24
+  0x08001758:  1851         ADDS       R1, R2, R1
+  0x0800175A:  1808         ADDS       R0, R1, R0
+  0x0800175C:  9903         LDR        R1, [SP, #12]
+  0x0800175E:  0209         LSLS       R1, R1, #8
+  0x08001760:  9A07         LDR        R2, [SP, #28]
+  0x08001762:  1889         ADDS       R1, R1, R2
+  0x08001764:  9A06         LDR        R2, [SP, #24]
+  0x08001766:  0412         LSLS       R2, R2, #16
+  0x08001768:  9B05         LDR        R3, [SP, #20]
+  0x0800176A:  061B         LSLS       R3, R3, #24
+  0x0800176C:  189A         ADDS       R2, R3, R2
+  0x0800176E:  1851         ADDS       R1, R2, R1
+  0x08001770:  6832         LDR        R2, [R6]
+  0x08001772:  4322         ORRS       R2, R4
+  0x08001774:  6032         STR        R2, [R6]
+  0x08001776:  9B0A         LDR        R3, [SP, #40]
+  0x08001778:  1F1A         SUBS       R2, R3, #4
+  0x0800177A:  6011         STR        R1, [R2]
+  0x0800177C:  F3BF 8F6F    ISB        SY
+  0x08001780:  6018         STR        R0, [R3]
+  0x08001782:  F7FF FA03    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x08001786:  6831         LDR        R1, [R6]
+  0x08001788:  43A1         BICS       R1, R4
+  0x0800178A:  6031         STR        R1, [R6]
+  0x0800178C:  2100         MOVS       R1, #0
+  0x0800178E:  7039         STRB       R1, [R7]
+  0x08001790:  2800         CMP        R0, #0
+  0x08001792:  9A08         LDR        R2, [SP, #32]
+  0x08001794:  D1AF         BNE        .L3                      ; 0x080016F6
+  0x08001796:  4625         MOV        R5, R4
+  0x08001798:  980A         LDR        R0, [SP, #40]
+  0x0800179A:  3008         ADDS       R0, #8
+  0x0800179C:  3208         ADDS       R2, #8
+  0x0800179E:  E7B9         B          .L6                      ; 0x08001714
+  0x080017A0:  08007800     DC.W       0x08007800
+  0x080017A4:  20000738     DC.W       pFlash.0
+  0x080017A8:  40022014     DC.W       0x40022014
+  0x080017AC:  FFFEFF85     DC.W       0xFFFEFF85
+  0x080017B0:  0001008A     DC.W       0x0001008A
+
+

Section .text.EEPROM_WriteDefaults from PowerPro_lto.o, size=48, align=4

+
+
EEPROM_WriteDefaults:
+  0x080017B4:  B580         PUSH       {R7, LR}
+  0x080017B6:  480A         LDR        R0, =flash_device_parameter_default ; [PC, #40] [0x080017E0] =0x20000674 
+  0x080017B8:  2100         MOVS       R1, #0
+  0x080017BA:  73C1         STRB       R1, [R0, #15]
+  0x080017BC:  2202         MOVS       R2, #2
+  0x080017BE:  7382         STRB       R2, [R0, #14]
+  0x080017C0:  7341         STRB       R1, [R0, #13]
+  0x080017C2:  2201         MOVS       R2, #1
+  0x080017C4:  7302         STRB       R2, [R0, #12]
+  0x080017C6:  72C1         STRB       R1, [R0, #11]
+  0x080017C8:  7282         STRB       R2, [R0, #10]
+  0x080017CA:  7241         STRB       R1, [R0, #9]
+  0x080017CC:  7201         STRB       R1, [R0, #8]
+  0x080017CE:  71C1         STRB       R1, [R0, #7]
+  0x080017D0:  7181         STRB       R1, [R0, #6]
+  0x080017D2:  224B         MOVS       R2, #75
+  0x080017D4:  7142         STRB       R2, [R0, #5]
+  0x080017D6:  7101         STRB       R1, [R0, #4]
+  0x080017D8:  F7FF FF60    BL         EEPROM_Write             ; 0x0800169C
+  0x080017DC:  BD80         POP        {R7, PC}
+  0x080017DE:  46C0         NOP
+  0x080017E0:  20000674     DC.W       flash_device_parameter_default
+
+

Section .text.EEPROM_ReadDeviceParameter from PowerPro_lto.o, size=36, align=4

+
+
EEPROM_ReadDeviceParameter:
+  0x080017E4:  B530         PUSH       {R4-R5, LR}
+  0x080017E6:  4806         LDR        R0, =0x08007800          ; [PC, #24] [0x08001800] 
+  0x080017E8:  8981         LDRH       R1, [R0, #12]
+  0x080017EA:  8942         LDRH       R2, [R0, #10]
+  0x080017EC:  8903         LDRH       R3, [R0, #8]
+  0x080017EE:  6804         LDR        R4, [R0]
+  0x080017F0:  6840         LDR        R0, [R0, #4]
+  0x080017F2:  4D04         LDR        R5, =sys_data            ; [PC, #16] [0x08001804] =0x20000234 
+  0x080017F4:  606C         STR        R4, [R5, #4]
+  0x080017F6:  6128         STR        R0, [R5, #16]
+  0x080017F8:  82AB         STRH       R3, [R5, #20]
+  0x080017FA:  82EA         STRH       R2, [R5, #22]
+  0x080017FC:  8329         STRH       R1, [R5, #24]
+  0x080017FE:  BD30         POP        {R4-R5, PC}
+  0x08001800:  08007800     DC.W       0x08007800
+  0x08001804:  20000234     DC.W       sys_data
+
+

Section .text.EEPROM_StoreConfig from PowerPro_lto.o, size=60, align=4

+
+
EEPROM_StoreConfig:
+  0x08001808:  B5F0         PUSH       {R4-R7, LR}
+  0x0800180A:  B085         SUB        SP, SP, #20
+  0x0800180C:  490B         LDR        R1, =0x08007800          ; [PC, #44] [0x0800183C] 
+  0x0800180E:  AA01         ADD        R2, SP, #4
+  0x08001810:  4613         MOV        R3, R2
+  0x08001812:  C9F0         LDM        R1!, {R4-R7}
+  0x08001814:  C3F0         STM        R3!, {R4-R7}
+  0x08001816:  2800         CMP        R0, #0
+  0x08001818:  4809         LDR        R0, =sys_data            ; [PC, #36] [0x08001840] =0x20000234 
+  0x0800181A:  6901         LDR        R1, [R0, #16]
+  0x0800181C:  8A83         LDRH       R3, [R0, #20]
+  0x0800181E:  8113         STRH       R3, [R2, #8]
+  0x08001820:  8AC3         LDRH       R3, [R0, #22]
+  0x08001822:  8153         STRH       R3, [R2, #10]
+  0x08001824:  8B03         LDRH       R3, [R0, #24]
+  0x08001826:  8193         STRH       R3, [R2, #12]
+  0x08001828:  9102         STR        R1, [SP, #8]
+  0x0800182A:  D001         BEQ        .L1                      ; 0x08001830
+  0x0800182C:  6840         LDR        R0, [R0, #4]
+  0x0800182E:  9001         STR        R0, [SP, #4]
+
.L1:
+  0x08001830:  A801         ADD        R0, SP, #4
+  0x08001832:  F7FF FF33    BL         EEPROM_Write             ; 0x0800169C
+  0x08001836:  B005         ADD        SP, SP, #20
+  0x08001838:  BDF0         POP        {R4-R7, PC}
+  0x0800183A:  46C0         NOP
+  0x0800183C:  08007800     DC.W       0x08007800
+  0x08001840:  20000234     DC.W       sys_data
+
+

Section .text.main from PowerPro_lto.o, size=11380, align=4

+
+
main:
+  0x08001844:  B500         PUSH       {LR}
+  0x08001846:  B0B5         SUB        SP, SP, #212
+  0x08001848:  49F7         LDR        R1, =bootLoaderMark      ; [PC, #0x03DC] [0x08001C28] =0x20000B7C 
+  0x0800184A:  7808         LDRB       R0, [R1]
+  0x0800184C:  2801         CMP        R0, #1
+  0x0800184E:  D101         BNE        .L1                      ; 0x08001854
+  0x08001850:  F002 FDF6    BL         .L289                    ; 0x08004440
+
.L1:
+  0x08001854:  4EF5         LDR        R6, =0x40022000          ; [PC, #0x03D4] [0x08001C2C] 
+  0x08001856:  6A30         LDR        R0, [R6, #32]
+  0x08001858:  01C0         LSLS       R0, R0, #7
+  0x0800185A:  D51F         BPL        .L3                      ; 0x0800189C
+  0x0800185C:  48F4         LDR        R0, =0x08006152          ; [PC, #0x03D0] [0x08001C30] 
+  0x0800185E:  F003 FC7B    BL         puts                     ; 0x08005158
+  0x08001862:  F7FF F9BB    BL         HAL_FLASH_Unlock         ; 0x08000BDC
+  0x08001866:  F7FF F991    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x0800186A:  6970         LDR        R0, [R6, #20]
+  0x0800186C:  0040         LSLS       R0, R0, #1
+  0x0800186E:  D504         BPL        .L2                      ; 0x0800187A
+  0x08001870:  48F0         LDR        R0, =0x08192A3B          ; [PC, #0x03C0] [0x08001C34] 
+  0x08001872:  60F0         STR        R0, [R6, #12]
+  0x08001874:  48F0         LDR        R0, =0x4C5D6E7F          ; [PC, #0x03C0] [0x08001C38] 
+  0x08001876:  60F0         STR        R0, [R6, #12]
+  0x08001878:  6970         LDR        R0, [R6, #20]
+
.L2:
+  0x0800187A:  4CF0         LDR        R4, =FLASH_WaitForLastOperation ; [PC, #0x03C0] [0x08001C3C] =0x08000B8D 
+  0x0800187C:  47A0         BLX        R4
+  0x0800187E:  2501         MOVS       R5, #1
+  0x08001880:  0628         LSLS       R0, R5, #24
+  0x08001882:  6A31         LDR        R1, [R6, #32]
+  0x08001884:  4381         BICS       R1, R0
+  0x08001886:  6231         STR        R1, [R6, #32]
+  0x08001888:  47A0         BLX        R4
+  0x0800188A:  0468         LSLS       R0, R5, #17
+  0x0800188C:  6971         LDR        R1, [R6, #20]
+  0x0800188E:  4301         ORRS       R1, R0
+  0x08001890:  6171         STR        R1, [R6, #20]
+  0x08001892:  47A0         BLX        R4
+  0x08001894:  06E8         LSLS       R0, R5, #27
+  0x08001896:  6971         LDR        R1, [R6, #20]
+  0x08001898:  4301         ORRS       R1, R0
+  0x0800189A:  6171         STR        R1, [R6, #20]
+
.L3:
+  0x0800189C:  2003         MOVS       R0, #3
+  0x0800189E:  9014         STR        R0, [SP, #80]
+  0x080018A0:  F7FE FED8    BL         HAL_InitTick             ; 0x08000654
+  0x080018A4:  2800         CMP        R0, #0
+  0x080018A6:  4CE6         LDR        R4, =0x40021000          ; [PC, #0x0398] [0x08001C40] 
+  0x080018A8:  D10F         BNE        .L4                      ; 0x080018CA
+  0x080018AA:  6C20         LDR        R0, [R4, #64]
+  0x080018AC:  2101         MOVS       R1, #1
+  0x080018AE:  4308         ORRS       R0, R1
+  0x080018B0:  6420         STR        R0, [R4, #64]
+  0x080018B2:  6C20         LDR        R0, [R4, #64]
+  0x080018B4:  4008         ANDS       R0, R1
+  0x080018B6:  9029         STR        R0, [SP, #164]
+  0x080018B8:  9829         LDR        R0, [SP, #164]
+  0x080018BA:  0708         LSLS       R0, R1, #28
+  0x080018BC:  6BE1         LDR        R1, [R4, #60]
+  0x080018BE:  4301         ORRS       R1, R0
+  0x080018C0:  63E1         STR        R1, [R4, #60]
+  0x080018C2:  6BE1         LDR        R1, [R4, #60]
+  0x080018C4:  4001         ANDS       R1, R0
+  0x080018C6:  9129         STR        R1, [SP, #164]
+  0x080018C8:  9829         LDR        R0, [SP, #164]
+
.L4:
+  0x080018CA:  6830         LDR        R0, [R6]
+  0x080018CC:  2107         MOVS       R1, #7
+  0x080018CE:  9123         STR        R1, [SP, #140]
+  0x080018D0:  4388         BICS       R0, R1
+  0x080018D2:  6030         STR        R0, [R6]
+  0x080018D4:  2501         MOVS       R5, #1
+  0x080018D6:  032B         LSLS       R3, R5, #12
+  0x080018D8:  68A0         LDR        R0, [R4, #8]
+  0x080018DA:  0680         LSLS       R0, R0, #26
+  0x080018DC:  0F40         LSRS       R0, R0, #29
+  0x080018DE:  4FD9         LDR        R7, =0x000003C7          ; [PC, #0x0364] [0x08001C44] 
+  0x080018E0:  48D9         LDR        R0, =0xFFFFC7FF          ; [PC, #0x0364] [0x08001C48] 
+  0x080018E2:  9313         STR        R3, [SP, #76]
+  0x080018E4:  D013         BEQ        .L6                      ; 0x0800190E
+  0x080018E6:  6821         LDR        R1, [R4]
+  0x080018E8:  4001         ANDS       R1, R0
+  0x080018EA:  4319         ORRS       R1, R3
+  0x080018EC:  6021         STR        R1, [R4]
+  0x080018EE:  0228         LSLS       R0, R5, #8
+  0x080018F0:  6821         LDR        R1, [R4]
+  0x080018F2:  4301         ORRS       R1, R0
+  0x080018F4:  6021         STR        R1, [R4]
+  0x080018F6:  48D5         LDR        R0, =uwTick              ; [PC, #0x0354] [0x08001C4C] =0x2000068C 
+  0x080018F8:  6801         LDR        R1, [R0]
+
.L5:
+  0x080018FA:  463A         MOV        R2, R7
+  0x080018FC:  3239         ADDS       R2, #57
+  0x080018FE:  6823         LDR        R3, [R4]
+  0x08001900:  4213         TST        R3, R2
+  0x08001902:  D11E         BNE        .L9                      ; 0x08001942
+  0x08001904:  6802         LDR        R2, [R0]
+  0x08001906:  1A52         SUBS       R2, R2, R1
+  0x08001908:  2A02         CMP        R2, #2
+  0x0800190A:  D9F6         BLS        .L5                      ; 0x080018FA
+  0x0800190C:  E017         B          .L7                      ; 0x0800193E
+
.L6:
+  0x0800190E:  217F         MOVS       R1, #127
+  0x08001910:  0209         LSLS       R1, R1, #8
+  0x08001912:  6862         LDR        R2, [R4, #4]
+  0x08001914:  438A         BICS       R2, R1
+  0x08001916:  03A9         LSLS       R1, R5, #14
+  0x08001918:  1851         ADDS       R1, R2, R1
+  0x0800191A:  6061         STR        R1, [R4, #4]
+  0x0800191C:  6821         LDR        R1, [R4]
+  0x0800191E:  4001         ANDS       R1, R0
+  0x08001920:  4319         ORRS       R1, R3
+  0x08001922:  6021         STR        R1, [R4]
+  0x08001924:  6820         LDR        R0, [R4]
+  0x08001926:  0480         LSLS       R0, R0, #18
+  0x08001928:  0F40         LSRS       R0, R0, #29
+  0x0800192A:  49C9         LDR        R1, =0x02DC6C00          ; [PC, #0x0324] [0x08001C50] 
+  0x0800192C:  40C1         LSRS       R1, R0
+  0x0800192E:  48C9         LDR        R0, =SystemCoreClock     ; [PC, #0x0324] [0x08001C54] =0x20000BA4 
+  0x08001930:  6001         STR        R1, [R0]
+  0x08001932:  48C9         LDR        R0, =uwTickPrio          ; [PC, #0x0324] [0x08001C58] =0x20000B94 
+  0x08001934:  6800         LDR        R0, [R0]
+  0x08001936:  F7FE FE8D    BL         HAL_InitTick             ; 0x08000654
+  0x0800193A:  2800         CMP        R0, #0
+  0x0800193C:  D008         BEQ        .L10                     ; 0x08001950
+
.L7:
+  0x0800193E:  B672         CPSID      i
+
.L8:
+  0x08001940:  E7FE         B          .L8                      ; 0x08001940
+
.L9:
+  0x08001942:  207F         MOVS       R0, #127
+  0x08001944:  0200         LSLS       R0, R0, #8
+  0x08001946:  6861         LDR        R1, [R4, #4]
+  0x08001948:  4381         BICS       R1, R0
+  0x0800194A:  03A8         LSLS       R0, R5, #14
+  0x0800194C:  1808         ADDS       R0, R1, R0
+  0x0800194E:  6060         STR        R0, [R4, #4]
+
.L10:
+  0x08001950:  6830         LDR        R0, [R6]
+  0x08001952:  207B         MOVS       R0, #123
+  0x08001954:  0200         LSLS       R0, R0, #8
+  0x08001956:  68A1         LDR        R1, [R4, #8]
+  0x08001958:  4381         BICS       R1, R0
+  0x0800195A:  200B         MOVS       R0, #11
+  0x0800195C:  901D         STR        R0, [SP, #116]
+  0x0800195E:  0200         LSLS       R0, R0, #8
+  0x08001960:  1808         ADDS       R0, R1, R0
+  0x08001962:  60A0         STR        R0, [R4, #8]
+  0x08001964:  48BD         LDR        R0, =0xFFFFF0FE          ; [PC, #0x02F4] [0x08001C5C] 
+  0x08001966:  1C40         ADDS       R0, R0, #1
+  0x08001968:  68A1         LDR        R1, [R4, #8]
+  0x0800196A:  4001         ANDS       R1, R0
+  0x0800196C:  60A1         STR        R1, [R4, #8]
+  0x0800196E:  463B         MOV        R3, R7
+  0x08001970:  3339         ADDS       R3, #57
+  0x08001972:  6820         LDR        R0, [R4]
+  0x08001974:  4218         TST        R0, R3
+  0x08001976:  D03C         BEQ        .L15                     ; 0x080019F2
+  0x08001978:  68A0         LDR        R0, [R4, #8]
+  0x0800197A:  9923         LDR        R1, [SP, #140]
+  0x0800197C:  4388         BICS       R0, R1
+  0x0800197E:  60A0         STR        R0, [R4, #8]
+  0x08001980:  48B2         LDR        R0, =uwTick              ; [PC, #0x02C8] [0x08001C4C] =0x2000068C 
+  0x08001982:  6800         LDR        R0, [R0]
+
.L11:
+  0x08001984:  68A1         LDR        R1, [R4, #8]
+  0x08001986:  0689         LSLS       R1, R1, #26
+  0x08001988:  0F49         LSRS       R1, R1, #29
+  0x0800198A:  D006         BEQ        .L12                     ; 0x0800199A
+  0x0800198C:  49AF         LDR        R1, =uwTick              ; [PC, #0x02BC] [0x08001C4C] =0x2000068C 
+  0x0800198E:  6809         LDR        R1, [R1]
+  0x08001990:  1A09         SUBS       R1, R1, R0
+  0x08001992:  4AB3         LDR        R2, =0x00001388          ; [PC, #0x02CC] [0x08001C60] 
+  0x08001994:  4291         CMP        R1, R2
+  0x08001996:  D9F5         BLS        .L11                     ; 0x08001984
+  0x08001998:  E02B         B          .L15                     ; 0x080019F2
+
.L12:
+  0x0800199A:  6830         LDR        R0, [R6]
+  0x0800199C:  0740         LSLS       R0, R0, #29
+  0x0800199E:  D00F         BEQ        .L14                     ; 0x080019C0
+  0x080019A0:  6830         LDR        R0, [R6]
+  0x080019A2:  9923         LDR        R1, [SP, #140]
+  0x080019A4:  4388         BICS       R0, R1
+  0x080019A6:  6030         STR        R0, [R6]
+  0x080019A8:  48A8         LDR        R0, =uwTick              ; [PC, #0x02A0] [0x08001C4C] =0x2000068C 
+  0x080019AA:  6800         LDR        R0, [R0]
+
.L13:
+  0x080019AC:  6831         LDR        R1, [R6]
+  0x080019AE:  0749         LSLS       R1, R1, #29
+  0x080019B0:  D006         BEQ        .L14                     ; 0x080019C0
+  0x080019B2:  49A6         LDR        R1, =uwTick              ; [PC, #0x0298] [0x08001C4C] =0x2000068C 
+  0x080019B4:  6809         LDR        R1, [R1]
+  0x080019B6:  1A09         SUBS       R1, R1, R0
+  0x080019B8:  4AA9         LDR        R2, =0x00001388          ; [PC, #0x02A4] [0x08001C60] 
+  0x080019BA:  4291         CMP        R1, R2
+  0x080019BC:  D9F6         BLS        .L13                     ; 0x080019AC
+  0x080019BE:  E018         B          .L15                     ; 0x080019F2
+
.L14:
+  0x080019C0:  9823         LDR        R0, [SP, #140]
+  0x080019C2:  0300         LSLS       R0, R0, #12
+  0x080019C4:  68A1         LDR        R1, [R4, #8]
+  0x080019C6:  4381         BICS       R1, R0
+  0x080019C8:  60A1         STR        R1, [R4, #8]
+  0x080019CA:  9321         STR        R3, [SP, #132]
+  0x080019CC:  F7FF F9D4    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+  0x080019D0:  68A1         LDR        R1, [R4, #8]
+  0x080019D2:  0989         LSRS       R1, R1, #6
+  0x080019D4:  263C         MOVS       R6, #60
+  0x080019D6:  4031         ANDS       R1, R6
+  0x080019D8:  4AA2         LDR        R2, =AHBPrescTable       ; [PC, #0x0288] [0x08001C64] =0x080050C4 
+  0x080019DA:  5851         LDR        R1, [R2, R1]
+  0x080019DC:  221F         MOVS       R2, #31
+  0x080019DE:  400A         ANDS       R2, R1
+  0x080019E0:  40D0         LSRS       R0, R2
+  0x080019E2:  499C         LDR        R1, =SystemCoreClock     ; [PC, #0x0270] [0x08001C54] =0x20000BA4 
+  0x080019E4:  6008         STR        R0, [R1]
+  0x080019E6:  489C         LDR        R0, =uwTickPrio          ; [PC, #0x0270] [0x08001C58] =0x20000B94 
+  0x080019E8:  6800         LDR        R0, [R0]
+  0x080019EA:  F7FE FE33    BL         HAL_InitTick             ; 0x08000654
+  0x080019EE:  2800         CMP        R0, #0
+  0x080019F0:  D001         BEQ        .L17                     ; 0x080019F6
+
.L15:
+  0x080019F2:  B672         CPSID      i
+
.L16:
+  0x080019F4:  E7FE         B          .L16                     ; 0x080019F4
+
.L17:
+  0x080019F6:  223C         MOVS       R2, #60
+  0x080019F8:  2600         MOVS       R6, #0
+  0x080019FA:  962D         STR        R6, [SP, #180]
+  0x080019FC:  962C         STR        R6, [SP, #176]
+  0x080019FE:  6B60         LDR        R0, [R4, #52]
+  0x08001A00:  2102         MOVS       R1, #2
+  0x08001A02:  4308         ORRS       R0, R1
+  0x08001A04:  6360         STR        R0, [R4, #52]
+  0x08001A06:  6B60         LDR        R0, [R4, #52]
+  0x08001A08:  910F         STR        R1, [SP, #60]
+  0x08001A0A:  4008         ANDS       R0, R1
+  0x08001A0C:  9030         STR        R0, [SP, #192]
+  0x08001A0E:  9830         LDR        R0, [SP, #192]
+  0x08001A10:  6B60         LDR        R0, [R4, #52]
+  0x08001A12:  2104         MOVS       R1, #4
+  0x08001A14:  4308         ORRS       R0, R1
+  0x08001A16:  6360         STR        R0, [R4, #52]
+  0x08001A18:  6B60         LDR        R0, [R4, #52]
+  0x08001A1A:  910E         STR        R1, [SP, #56]
+  0x08001A1C:  4008         ANDS       R0, R1
+  0x08001A1E:  9030         STR        R0, [SP, #192]
+  0x08001A20:  9830         LDR        R0, [SP, #192]
+  0x08001A22:  6B60         LDR        R0, [R4, #52]
+  0x08001A24:  4328         ORRS       R0, R5
+  0x08001A26:  6360         STR        R0, [R4, #52]
+  0x08001A28:  6B60         LDR        R0, [R4, #52]
+  0x08001A2A:  4028         ANDS       R0, R5
+  0x08001A2C:  9030         STR        R0, [SP, #192]
+  0x08001A2E:  9830         LDR        R0, [SP, #192]
+  0x08001A30:  9914         LDR        R1, [SP, #80]
+  0x08001A32:  038B         LSLS       R3, R1, #14
+  0x08001A34:  931E         STR        R3, [SP, #120]
+  0x08001A36:  498C         LDR        R1, =0x50000818          ; [PC, #0x0230] [0x08001C68] 
+  0x08001A38:  610B         STR        R3, [R1, #16]
+  0x08001A3A:  0229         LSLS       R1, R5, #8
+  0x08001A3C:  9110         STR        R1, [SP, #64]
+  0x08001A3E:  4B8B         LDR        R3, =0x50000010          ; [PC, #0x022C] [0x08001C6C] 
+  0x08001A40:  6199         STR        R1, [R3, #24]
+  0x08001A42:  498B         LDR        R1, =0x50000410          ; [PC, #0x022C] [0x08001C70] 
+  0x08001A44:  2338         MOVS       R3, #56
+  0x08001A46:  9320         STR        R3, [SP, #128]
+  0x08001A48:  618B         STR        R3, [R1, #24]
+  0x08001A4A:  952B         STR        R5, [SP, #172]
+  0x08001A4C:  962A         STR        R6, [SP, #168]
+  0x08001A4E:  9729         STR        R7, [SP, #164]
+  0x08001A50:  3910         SUBS       R1, #16
+  0x08001A52:  4608         MOV        R0, R1
+  0x08001A54:  911F         STR        R1, [SP, #124]
+  0x08001A56:  921C         STR        R2, [SP, #112]
+  0x08001A58:  A929         ADD        R1, SP, #164
+  0x08001A5A:  9122         STR        R1, [SP, #136]
+  0x08001A5C:  4F85         LDR        R7, =HAL_GPIO_Init       ; [PC, #0x0214] [0x08001C74] =0x08000BFD 
+  0x08001A5E:  47B8         BLX        R7
+  0x08001A60:  962C         STR        R6, [SP, #176]
+  0x08001A62:  962B         STR        R6, [SP, #172]
+  0x08001A64:  952A         STR        R5, [SP, #168]
+  0x08001A66:  981E         LDR        R0, [SP, #120]
+  0x08001A68:  9029         STR        R0, [SP, #164]
+  0x08001A6A:  487F         LDR        R0, =0x50000818          ; [PC, #0x01FC] [0x08001C68] 
+  0x08001A6C:  3818         SUBS       R0, #24
+  0x08001A6E:  901E         STR        R0, [SP, #120]
+  0x08001A70:  9922         LDR        R1, [SP, #136]
+  0x08001A72:  47B8         BLX        R7
+  0x08001A74:  952B         STR        R5, [SP, #172]
+  0x08001A76:  962A         STR        R6, [SP, #168]
+  0x08001A78:  9814         LDR        R0, [SP, #80]
+  0x08001A7A:  9029         STR        R0, [SP, #164]
+  0x08001A7C:  4F7B         LDR        R7, =0x50000010          ; [PC, #0x01EC] [0x08001C6C] 
+  0x08001A7E:  3F10         SUBS       R7, #16
+  0x08001A80:  4638         MOV        R0, R7
+  0x08001A82:  9922         LDR        R1, [SP, #136]
+  0x08001A84:  4A7B         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01EC] [0x08001C74] =0x08000BFD 
+  0x08001A86:  4790         BLX        R2
+  0x08001A88:  962C         STR        R6, [SP, #176]
+  0x08001A8A:  962B         STR        R6, [SP, #172]
+  0x08001A8C:  952A         STR        R5, [SP, #168]
+  0x08001A8E:  9810         LDR        R0, [SP, #64]
+  0x08001A90:  9029         STR        R0, [SP, #164]
+  0x08001A92:  4638         MOV        R0, R7
+  0x08001A94:  9922         LDR        R1, [SP, #136]
+  0x08001A96:  4A77         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01DC] [0x08001C74] =0x08000BFD 
+  0x08001A98:  4790         BLX        R2
+  0x08001A9A:  962B         STR        R6, [SP, #172]
+  0x08001A9C:  962A         STR        R6, [SP, #168]
+  0x08001A9E:  2040         MOVS       R0, #64
+  0x08001AA0:  9007         STR        R0, [SP, #28]
+  0x08001AA2:  9029         STR        R0, [SP, #164]
+  0x08001AA4:  981E         LDR        R0, [SP, #120]
+  0x08001AA6:  9922         LDR        R1, [SP, #136]
+  0x08001AA8:  4A72         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01C8] [0x08001C74] =0x08000BFD 
+  0x08001AAA:  4790         BLX        R2
+  0x08001AAC:  962B         STR        R6, [SP, #172]
+  0x08001AAE:  962A         STR        R6, [SP, #168]
+  0x08001AB0:  2009         MOVS       R0, #9
+  0x08001AB2:  0300         LSLS       R0, R0, #12
+  0x08001AB4:  9029         STR        R0, [SP, #164]
+  0x08001AB6:  9709         STR        R7, [SP, #36]
+  0x08001AB8:  4638         MOV        R0, R7
+  0x08001ABA:  9F22         LDR        R7, [SP, #136]
+  0x08001ABC:  4639         MOV        R1, R7
+  0x08001ABE:  4A6D         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01B4] [0x08001C74] =0x08000BFD 
+  0x08001AC0:  4790         BLX        R2
+  0x08001AC2:  962C         STR        R6, [SP, #176]
+  0x08001AC4:  962B         STR        R6, [SP, #172]
+  0x08001AC6:  952A         STR        R5, [SP, #168]
+  0x08001AC8:  9820         LDR        R0, [SP, #128]
+  0x08001ACA:  9029         STR        R0, [SP, #164]
+  0x08001ACC:  981F         LDR        R0, [SP, #124]
+  0x08001ACE:  4639         MOV        R1, R7
+  0x08001AD0:  4A68         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01A0] [0x08001C74] =0x08000BFD 
+  0x08001AD2:  4790         BLX        R2
+  0x08001AD4:  6BA0         LDR        R0, [R4, #56]
+  0x08001AD6:  4328         ORRS       R0, R5
+  0x08001AD8:  63A0         STR        R0, [R4, #56]
+  0x08001ADA:  6BA0         LDR        R0, [R4, #56]
+  0x08001ADC:  4028         ANDS       R0, R5
+  0x08001ADE:  9029         STR        R0, [SP, #164]
+  0x08001AE0:  9829         LDR        R0, [SP, #164]
+  0x08001AE2:  23FF         MOVS       R3, #255
+  0x08001AE4:  0218         LSLS       R0, R3, #8
+  0x08001AE6:  4964         LDR        R1, =0xE000E408          ; [PC, #0x0190] [0x08001C78] 
+  0x08001AE8:  680A         LDR        R2, [R1]
+  0x08001AEA:  4382         BICS       R2, R0
+  0x08001AEC:  600A         STR        R2, [R1]
+  0x08001AEE:  0268         LSLS       R0, R5, #9
+  0x08001AF0:  4A62         LDR        R2, =0xE000E100          ; [PC, #0x0188] [0x08001C7C] 
+  0x08001AF2:  6010         STR        R0, [R2]
+  0x08001AF4:  9312         STR        R3, [SP, #72]
+  0x08001AF6:  0418         LSLS       R0, R3, #16
+  0x08001AF8:  680B         LDR        R3, [R1]
+  0x08001AFA:  4383         BICS       R3, R0
+  0x08001AFC:  600B         STR        R3, [R1]
+  0x08001AFE:  9821         LDR        R0, [SP, #132]
+  0x08001B00:  6010         STR        R0, [R2]
+  0x08001B02:  4B5F         LDR        R3, =hadc1               ; [PC, #0x017C] [0x08001C80] =0x20000450 
+  0x08001B04:  981C         LDR        R0, [SP, #112]
+  0x08001B06:  541D         STRB       R5, [R3, R0]
+  0x08001B08:  202C         MOVS       R0, #44
+  0x08001B0A:  9008         STR        R0, [SP, #32]
+  0x08001B0C:  541D         STRB       R5, [R3, R0]
+  0x08001B0E:  2120         MOVS       R1, #32
+  0x08001B10:  545E         STRB       R6, [R3, R1]
+  0x08001B12:  2080         MOVS       R0, #128
+  0x08001B14:  221C         MOVS       R2, #28
+  0x08001B16:  9204         STR        R2, [SP, #16]
+  0x08001B18:  641A         STR        R2, [R3, #64]
+  0x08001B1A:  900A         STR        R0, [SP, #40]
+  0x08001B1C:  6458         STR        R0, [R3, #68]
+  0x08001B1E:  649E         STR        R6, [R3, #72]
+  0x08001B20:  64DE         STR        R6, [R3, #76]
+  0x08001B22:  631E         STR        R6, [R3, #48]
+  0x08001B24:  9823         LDR        R0, [SP, #140]
+  0x08001B26:  6358         STR        R0, [R3, #52]
+  0x08001B28:  625E         STR        R6, [R3, #36]
+  0x08001B2A:  629E         STR        R6, [R3, #40]
+  0x08001B2C:  61DD         STR        R5, [R3, #28]
+  0x08001B2E:  769D         STRB       R5, [R3, #26]
+  0x08001B30:  831E         STRH       R6, [R3, #24]
+  0x08001B32:  2208         MOVS       R2, #8
+  0x08001B34:  4853         LDR        R0, =0x7FFFFFE8          ; [PC, #0x014C] [0x08001C84] 
+  0x08001B36:  3018         ADDS       R0, #24
+  0x08001B38:  4F53         LDR        R7, =0x40012400          ; [PC, #0x014C] [0x08001C88] 
+  0x08001B3A:  601F         STR        R7, [R3]
+  0x08001B3C:  6058         STR        R0, [R3, #4]
+  0x08001B3E:  609E         STR        R6, [R3, #8]
+  0x08001B40:  60DE         STR        R6, [R3, #12]
+  0x08001B42:  6118         STR        R0, [R3, #16]
+  0x08001B44:  921A         STR        R2, [SP, #104]
+  0x08001B46:  615A         STR        R2, [R3, #20]
+  0x08001B48:  9626         STR        R6, [SP, #152]
+  0x08001B4A:  9625         STR        R6, [SP, #148]
+  0x08001B4C:  9624         STR        R6, [SP, #144]
+  0x08001B4E:  9622         STR        R6, [SP, #136]
+  0x08001B50:  9627         STR        R6, [SP, #156]
+  0x08001B52:  461E         MOV        R6, R3
+  0x08001B54:  463B         MOV        R3, R7
+  0x08001B56:  6DB0         LDR        R0, [R6, #88]
+  0x08001B58:  2800         CMP        R0, #0
+  0x08001B5A:  9120         STR        R1, [SP, #128]
+  0x08001B5C:  D14A         BNE        .L20                     ; 0x08001BF4
+  0x08001B5E:  9034         STR        R0, [SP, #208]
+  0x08001B60:  901F         STR        R0, [SP, #124]
+  0x08001B62:  9033         STR        R0, [SP, #204]
+  0x08001B64:  A829         ADD        R0, SP, #164
+  0x08001B66:  901E         STR        R0, [SP, #120]
+  0x08001B68:  1D00         ADDS       R0, R0, #4
+  0x08001B6A:  2720         MOVS       R7, #32
+  0x08001B6C:  2118         MOVS       R1, #24
+  0x08001B6E:  F004 FAD2    BL         __aeabi_memclr           ; 0x08006116
+  0x08001B72:  9729         STR        R7, [SP, #164]
+  0x08001B74:  981E         LDR        R0, [SP, #120]
+  0x08001B76:  F7FF F949    BL         HAL_RCCEx_PeriphCLKConfig ; 0x08000E0C
+  0x08001B7A:  2800         CMP        R0, #0
+  0x08001B7C:  D000         BEQ        .L18                     ; 0x08001B80
+  0x08001B7E:  E2E0         B          .L61                     ; 0x08002142
+
.L18:
+  0x08001B80:  2201         MOVS       R2, #1
+  0x08001B82:  0510         LSLS       R0, R2, #20
+  0x08001B84:  6C21         LDR        R1, [R4, #64]
+  0x08001B86:  4301         ORRS       R1, R0
+  0x08001B88:  6421         STR        R1, [R4, #64]
+  0x08001B8A:  6C21         LDR        R1, [R4, #64]
+  0x08001B8C:  4001         ANDS       R1, R0
+  0x08001B8E:  9128         STR        R1, [SP, #160]
+  0x08001B90:  9828         LDR        R0, [SP, #160]
+  0x08001B92:  6B60         LDR        R0, [R4, #52]
+  0x08001B94:  921E         STR        R2, [SP, #120]
+  0x08001B96:  4310         ORRS       R0, R2
+  0x08001B98:  6360         STR        R0, [R4, #52]
+  0x08001B9A:  6B60         LDR        R0, [R4, #52]
+  0x08001B9C:  4010         ANDS       R0, R2
+  0x08001B9E:  9028         STR        R0, [SP, #160]
+  0x08001BA0:  9F1F         LDR        R7, [SP, #124]
+  0x08001BA2:  9732         STR        R7, [SP, #200]
+  0x08001BA4:  2003         MOVS       R0, #3
+  0x08001BA6:  9031         STR        R0, [SP, #196]
+  0x08001BA8:  981C         LDR        R0, [SP, #112]
+  0x08001BAA:  9030         STR        R0, [SP, #192]
+  0x08001BAC:  9828         LDR        R0, [SP, #160]
+  0x08001BAE:  A930         ADD        R1, SP, #192
+  0x08001BB0:  9809         LDR        R0, [SP, #36]
+  0x08001BB2:  F7FF F823    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x08001BB6:  981E         LDR        R0, [SP, #120]
+  0x08001BB8:  02C0         LSLS       R0, R0, #11
+  0x08001BBA:  4A34         LDR        R2, =hdma_adc1           ; [PC, #208] [0x08001C8C] =0x2000056C 
+  0x08001BBC:  6217         STR        R7, [R2, #32]
+  0x08001BBE:  4934         LDR        R1, =0x40020008          ; [PC, #208] [0x08001C90] 
+  0x08001BC0:  6011         STR        R1, [R2]
+  0x08001BC2:  2105         MOVS       R1, #5
+  0x08001BC4:  6051         STR        R1, [R2, #4]
+  0x08001BC6:  6097         STR        R7, [R2, #8]
+  0x08001BC8:  60D7         STR        R7, [R2, #12]
+  0x08001BCA:  4617         MOV        R7, R2
+  0x08001BCC:  990A         LDR        R1, [SP, #40]
+  0x08001BCE:  6111         STR        R1, [R2, #16]
+  0x08001BD0:  9910         LDR        R1, [SP, #64]
+  0x08001BD2:  6151         STR        R1, [R2, #20]
+  0x08001BD4:  6190         STR        R0, [R2, #24]
+  0x08001BD6:  9820         LDR        R0, [SP, #128]
+  0x08001BD8:  61D0         STR        R0, [R2, #28]
+  0x08001BDA:  4610         MOV        R0, R2
+  0x08001BDC:  F7FE FEB2    BL         HAL_DMA_Init             ; 0x08000944
+  0x08001BE0:  2800         CMP        R0, #0
+  0x08001BE2:  D000         BEQ        .L19                     ; 0x08001BE6
+  0x08001BE4:  E2AD         B          .L61                     ; 0x08002142
+
.L19:
+  0x08001BE6:  2054         MOVS       R0, #84
+  0x08001BE8:  991F         LDR        R1, [SP, #124]
+  0x08001BEA:  5431         STRB       R1, [R6, R0]
+  0x08001BEC:  62BE         STR        R6, [R7, #40]
+  0x08001BEE:  6537         STR        R7, [R6, #80]
+  0x08001BF0:  65F1         STR        R1, [R6, #92]
+  0x08001BF2:  6833         LDR        R3, [R6]
+
.L20:
+  0x08001BF4:  0728         LSLS       R0, R5, #28
+  0x08001BF6:  901F         STR        R0, [SP, #124]
+  0x08001BF8:  6898         LDR        R0, [R3, #8]
+  0x08001BFA:  00C0         LSLS       R0, R0, #3
+  0x08001BFC:  4A15         LDR        R2, =SystemCoreClock     ; [PC, #84] [0x08001C54] =0x20000BA4 
+  0x08001BFE:  931E         STR        R3, [SP, #120]
+  0x08001C00:  D44C         BMI        .L22                     ; 0x08001C9C
+  0x08001C02:  6898         LDR        R0, [R3, #8]
+  0x08001C04:  4923         LDR        R1, =0x6FFFFFE8          ; [PC, #140] [0x08001C94] 
+  0x08001C06:  4001         ANDS       R1, R0
+  0x08001C08:  981F         LDR        R0, [SP, #124]
+  0x08001C0A:  4301         ORRS       R1, R0
+  0x08001C0C:  6099         STR        R1, [R3, #8]
+  0x08001C0E:  6810         LDR        R0, [R2]
+  0x08001C10:  4921         LDR        R1, =0x00030D40          ; [PC, #132] [0x08001C98] 
+  0x08001C12:  F004 F9EA    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08001C16:  9B1E         LDR        R3, [SP, #120]
+  0x08001C18:  0040         LSLS       R0, R0, #1
+
.L21:
+  0x08001C1A:  9027         STR        R0, [SP, #156]
+  0x08001C1C:  9827         LDR        R0, [SP, #156]
+  0x08001C1E:  2800         CMP        R0, #0
+  0x08001C20:  D03C         BEQ        .L22                     ; 0x08001C9C
+  0x08001C22:  9827         LDR        R0, [SP, #156]
+  0x08001C24:  1E40         SUBS       R0, R0, #1
+  0x08001C26:  E7F8         B          .L21                     ; 0x08001C1A
+  0x08001C28:  20000B7C     DC.W       bootLoaderMark
+  0x08001C2C:  40022000     DC.W       0x40022000
+  0x08001C30:  08006152     DC.W       08006152               ; R_ARM_ABS32
+  0x08001C34:  08192A3B     DC.W       0x08192A3B
+  0x08001C38:  4C5D6E7F     DC.W       0x4C5D6E7F
+  0x08001C3C:  08000B8D     DC.W       FLASH_WaitForLastOperation
+  0x08001C40:  40021000     DC.W       0x40021000
+  0x08001C44:  000003C7     DC.W       0x000003C7
+  0x08001C48:  FFFFC7FF     DC.W       0xFFFFC7FF
+  0x08001C4C:  2000068C     DC.W       uwTick
+  0x08001C50:  02DC6C00     DC.W       0x02DC6C00
+  0x08001C54:  20000BA4     DC.W       SystemCoreClock
+  0x08001C58:  20000B94     DC.W       uwTickPrio
+  0x08001C5C:  FFFFF0FE     DC.W       0xFFFFF0FE
+  0x08001C60:  00001388     DC.W       0x00001388
+  0x08001C64:  080050C4     DC.W       AHBPrescTable
+  0x08001C68:  50000818     DC.W       0x50000818
+  0x08001C6C:  50000010     DC.W       0x50000010
+  0x08001C70:  50000410     DC.W       0x50000410
+  0x08001C74:  08000BFD     DC.W       HAL_GPIO_Init
+  0x08001C78:  E000E408     DC.W       0xE000E408
+  0x08001C7C:  E000E100     DC.W       0xE000E100
+  0x08001C80:  20000450     DC.W       hadc1
+  0x08001C84:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08001C88:  40012400     DC.W       0x40012400
+  0x08001C8C:  2000056C     DC.W       hdma_adc1
+  0x08001C90:  40020008     DC.W       0x40020008
+  0x08001C94:  6FFFFFE8     DC.W       0x6FFFFFE8
+  0x08001C98:  00030D40     DC.W       0x00030D40
+
.L22:
+  0x08001C9C:  689F         LDR        R7, [R3, #8]
+  0x08001C9E:  981F         LDR        R0, [SP, #124]
+  0x08001CA0:  4007         ANDS       R7, R0
+  0x08001CA2:  D107         BNE        .L23                     ; 0x08001CB4
+  0x08001CA4:  6DB0         LDR        R0, [R6, #88]
+  0x08001CA6:  2110         MOVS       R1, #16
+  0x08001CA8:  4301         ORRS       R1, R0
+  0x08001CAA:  65B1         STR        R1, [R6, #88]
+  0x08001CAC:  6DF0         LDR        R0, [R6, #92]
+  0x08001CAE:  2101         MOVS       R1, #1
+  0x08001CB0:  4301         ORRS       R1, R0
+  0x08001CB2:  65F1         STR        R1, [R6, #92]
+
.L23:
+  0x08001CB4:  6898         LDR        R0, [R3, #8]
+  0x08001CB6:  990E         LDR        R1, [SP, #56]
+  0x08001CB8:  4008         ANDS       R0, R1
+  0x08001CBA:  6DB2         LDR        R2, [R6, #88]
+  0x08001CBC:  2110         MOVS       R1, #16
+  0x08001CBE:  400A         ANDS       R2, R1
+  0x08001CC0:  1810         ADDS       R0, R2, R0
+  0x08001CC2:  6DB0         LDR        R0, [R6, #88]
+  0x08001CC4:  D001         BEQ        .L24                     ; 0x08001CCA
+  0x08001CC6:  F002 FBC3    BL         .L291                    ; 0x08004450
+
.L24:
+  0x08001CCA:  49CF         LDR        R1, =0xFFFFFEFD          ; [PC, #0x033C] [0x08002008] 
+  0x08001CCC:  4008         ANDS       R0, R1
+  0x08001CCE:  1C80         ADDS       R0, R0, #2
+  0x08001CD0:  65B0         STR        R0, [R6, #88]
+  0x08001CD2:  6930         LDR        R0, [R6, #16]
+  0x08001CD4:  901B         STR        R0, [SP, #108]
+  0x08001CD6:  6898         LDR        R0, [R3, #8]
+  0x08001CD8:  07C0         LSLS       R0, R0, #31
+  0x08001CDA:  D175         BNE        .L33                     ; 0x08001DC8
+  0x08001CDC:  6B30         LDR        R0, [R6, #48]
+  0x08001CDE:  2800         CMP        R0, #0
+  0x08001CE0:  9B13         LDR        R3, [SP, #76]
+  0x08001CE2:  D100         BNE        .L25                     ; 0x08001CE6
+  0x08001CE4:  2300         MOVS       R3, #0
+
.L25:
+  0x08001CE6:  2001         MOVS       R0, #1
+  0x08001CE8:  991B         LDR        R1, [SP, #108]
+  0x08001CEA:  2900         CMP        R1, #0
+  0x08001CEC:  9718         STR        R7, [SP, #96]
+  0x08001CEE:  9019         STR        R0, [SP, #100]
+  0x08001CF0:  DA03         BGE        .L26                     ; 0x08001CFA
+  0x08001CF2:  48C6         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0318] [0x0800200C] 
+  0x08001CF4:  3017         ADDS       R0, #23
+  0x08001CF6:  4008         ANDS       R0, R1
+  0x08001CF8:  E000         B          .L27                     ; 0x08001CFC
+
.L26:
+  0x08001CFA:  0540         LSLS       R0, R0, #21
+
.L27:
+  0x08001CFC:  68B2         LDR        R2, [R6, #8]
+  0x08001CFE:  4302         ORRS       R2, R0
+  0x08001D00:  7E30         LDRB       R0, [R6, #24]
+  0x08001D02:  0380         LSLS       R0, R0, #14
+  0x08001D04:  4310         ORRS       R0, R2
+  0x08001D06:  7E72         LDRB       R2, [R6, #25]
+  0x08001D08:  03D2         LSLS       R2, R2, #15
+  0x08001D0A:  4302         ORRS       R2, R0
+  0x08001D0C:  7EB0         LDRB       R0, [R6, #26]
+  0x08001D0E:  0347         LSLS       R7, R0, #13
+  0x08001D10:  4317         ORRS       R7, R2
+  0x08001D12:  68F2         LDR        R2, [R6, #12]
+  0x08001D14:  433A         ORRS       R2, R7
+  0x08001D16:  431A         ORRS       R2, R3
+  0x08001D18:  9908         LDR        R1, [SP, #32]
+  0x08001D1A:  5C73         LDRB       R3, [R6, R1]
+  0x08001D1C:  005B         LSLS       R3, R3, #1
+  0x08001D1E:  4313         ORRS       R3, R2
+  0x08001D20:  9920         LDR        R1, [SP, #128]
+  0x08001D22:  5C72         LDRB       R2, [R6, R1]
+  0x08001D24:  2A01         CMP        R2, #1
+  0x08001D26:  D10C         BNE        .L29                     ; 0x08001D42
+  0x08001D28:  2800         CMP        R0, #0
+  0x08001D2A:  D007         BEQ        .L28                     ; 0x08001D3C
+  0x08001D2C:  6DB0         LDR        R0, [R6, #88]
+  0x08001D2E:  4308         ORRS       R0, R1
+  0x08001D30:  65B0         STR        R0, [R6, #88]
+  0x08001D32:  6DF0         LDR        R0, [R6, #92]
+  0x08001D34:  9919         LDR        R1, [SP, #100]
+  0x08001D36:  4308         ORRS       R0, R1
+  0x08001D38:  65F0         STR        R0, [R6, #92]
+  0x08001D3A:  E002         B          .L29                     ; 0x08001D42
+
.L28:
+  0x08001D3C:  48B4         LDR        R0, =0x0000FFFF          ; [PC, #0x02D0] [0x08002010] 
+  0x08001D3E:  1C40         ADDS       R0, R0, #1
+  0x08001D40:  4303         ORRS       R3, R0
+
.L29:
+  0x08001D42:  6A70         LDR        R0, [R6, #36]
+  0x08001D44:  6AB2         LDR        R2, [R6, #40]
+  0x08001D46:  991E         LDR        R1, [SP, #120]
+  0x08001D48:  68C9         LDR        R1, [R1, #12]
+  0x08001D4A:  4FB2         LDR        R7, =0xFFDE0201          ; [PC, #0x02C8] [0x08002014] 
+  0x08001D4C:  400F         ANDS       R7, R1
+  0x08001D4E:  2800         CMP        R0, #0
+  0x08001D50:  D003         BEQ        .L30                     ; 0x08001D5A
+  0x08001D52:  9910         LDR        R1, [SP, #64]
+  0x08001D54:  31C0         ADDS       R1, #192
+  0x08001D56:  4008         ANDS       R0, R1
+  0x08001D58:  4310         ORRS       R0, R2
+
.L30:
+  0x08001D5A:  4318         ORRS       R0, R3
+  0x08001D5C:  4338         ORRS       R0, R7
+  0x08001D5E:  991E         LDR        R1, [SP, #120]
+  0x08001D60:  60C8         STR        R0, [R1, #12]
+  0x08001D62:  2003         MOVS       R0, #3
+  0x08001D64:  0780         LSLS       R0, R0, #30
+  0x08001D66:  6873         LDR        R3, [R6, #4]
+  0x08001D68:  9317         STR        R3, [SP, #92]
+  0x08001D6A:  9016         STR        R0, [SP, #88]
+  0x08001D6C:  4003         ANDS       R3, R0
+  0x08001D6E:  991C         LDR        R1, [SP, #112]
+  0x08001D70:  5C71         LDRB       R1, [R6, R1]
+  0x08001D72:  2901         CMP        R1, #1
+  0x08001D74:  6CF2         LDR        R2, [R6, #76]
+  0x08001D76:  9819         LDR        R0, [SP, #100]
+  0x08001D78:  D109         BNE        .L31                     ; 0x08001D8E
+  0x08001D7A:  6C31         LDR        R1, [R6, #64]
+  0x08001D7C:  6C77         LDR        R7, [R6, #68]
+  0x08001D7E:  430F         ORRS       R7, R1
+  0x08001D80:  6CB1         LDR        R1, [R6, #72]
+  0x08001D82:  4339         ORRS       R1, R7
+  0x08001D84:  4319         ORRS       R1, R3
+  0x08001D86:  4311         ORRS       R1, R2
+  0x08001D88:  4301         ORRS       R1, R0
+  0x08001D8A:  460B         MOV        R3, R1
+  0x08001D8C:  E000         B          .L32                     ; 0x08001D90
+
.L31:
+  0x08001D8E:  4313         ORRS       R3, R2
+
.L32:
+  0x08001D90:  9F1E         LDR        R7, [SP, #120]
+  0x08001D92:  6939         LDR        R1, [R7, #16]
+  0x08001D94:  4AA0         LDR        R2, =0x1FFFFC02          ; [PC, #0x0280] [0x08002018] 
+  0x08001D96:  400A         ANDS       R2, R1
+  0x08001D98:  431A         ORRS       R2, R3
+  0x08001D9A:  463B         MOV        R3, R7
+  0x08001D9C:  613A         STR        R2, [R7, #16]
+  0x08001D9E:  07C1         LSLS       R1, R0, #31
+  0x08001DA0:  9A17         LDR        R2, [SP, #92]
+  0x08001DA2:  428A         CMP        R2, R1
+  0x08001DA4:  9F18         LDR        R7, [SP, #96]
+  0x08001DA6:  D00F         BEQ        .L33                     ; 0x08001DC8
+  0x08001DA8:  9916         LDR        R1, [SP, #88]
+  0x08001DAA:  428A         CMP        R2, R1
+  0x08001DAC:  D00C         BEQ        .L33                     ; 0x08001DC8
+  0x08001DAE:  0781         LSLS       R1, R0, #30
+  0x08001DB0:  428A         CMP        R2, R1
+  0x08001DB2:  D009         BEQ        .L33                     ; 0x08001DC8
+  0x08001DB4:  210F         MOVS       R1, #15
+  0x08001DB6:  0489         LSLS       R1, R1, #18
+  0x08001DB8:  400A         ANDS       R2, R1
+  0x08001DBA:  4610         MOV        R0, R2
+  0x08001DBC:  4A97         LDR        R2, =0x40012708          ; [PC, #0x025C] [0x0800201C] 
+  0x08001DBE:  6813         LDR        R3, [R2]
+  0x08001DC0:  438B         BICS       R3, R1
+  0x08001DC2:  1818         ADDS       R0, R3, R0
+  0x08001DC4:  9B1E         LDR        R3, [SP, #120]
+  0x08001DC6:  6010         STR        R0, [R2]
+
.L33:
+  0x08001DC8:  6958         LDR        R0, [R3, #20]
+  0x08001DCA:  9923         LDR        R1, [SP, #140]
+  0x08001DCC:  4388         BICS       R0, R1
+  0x08001DCE:  6B72         LDR        R2, [R6, #52]
+  0x08001DD0:  4310         ORRS       R0, R2
+  0x08001DD2:  6158         STR        R0, [R3, #20]
+  0x08001DD4:  6958         LDR        R0, [R3, #20]
+  0x08001DD6:  2170         MOVS       R1, #112
+  0x08001DD8:  4388         BICS       R0, R1
+  0x08001DDA:  6BB1         LDR        R1, [R6, #56]
+  0x08001DDC:  0109         LSLS       R1, R1, #4
+  0x08001DDE:  4301         ORRS       R1, R0
+  0x08001DE0:  6159         STR        R1, [R3, #20]
+  0x08001DE2:  0568         LSLS       R0, R5, #21
+  0x08001DE4:  991B         LDR        R1, [SP, #108]
+  0x08001DE6:  4281         CMP        R1, R0
+  0x08001DE8:  D007         BEQ        .L34                     ; 0x08001DFA
+  0x08001DEA:  2900         CMP        R1, #0
+  0x08001DEC:  D111         BNE        .L35                     ; 0x08001E12
+  0x08001DEE:  4886         LDR        R0, =0xFFFFFEFD          ; [PC, #0x0218] [0x08002008] 
+  0x08001DF0:  30F3         ADDS       R0, #243
+  0x08001DF2:  6A99         LDR        R1, [R3, #40]
+  0x08001DF4:  4301         ORRS       R1, R0
+  0x08001DF6:  6299         STR        R1, [R3, #40]
+  0x08001DF8:  E00B         B          .L35                     ; 0x08001E12
+
.L34:
+  0x08001DFA:  6A98         LDR        R0, [R3, #40]
+  0x08001DFC:  69F0         LDR        R0, [R6, #28]
+  0x08001DFE:  0080         LSLS       R0, R0, #2
+  0x08001E00:  301C         ADDS       R0, #28
+  0x08001E02:  9904         LDR        R1, [SP, #16]
+  0x08001E04:  4008         ANDS       R0, R1
+  0x08001E06:  4980         LDR        R1, =0xFFFFFEFD          ; [PC, #0x0200] [0x08002008] 
+  0x08001E08:  31F3         ADDS       R1, #243
+  0x08001E0A:  4081         LSLS       R1, R0
+  0x08001E0C:  6E30         LDR        R0, [R6, #96]
+  0x08001E0E:  4308         ORRS       R0, R1
+  0x08001E10:  6298         STR        R0, [R3, #40]
+
.L35:
+  0x08001E12:  6958         LDR        R0, [R3, #20]
+  0x08001E14:  9923         LDR        R1, [SP, #140]
+  0x08001E16:  4008         ANDS       R0, R1
+  0x08001E18:  4290         CMP        R0, R2
+  0x08001E1A:  D001         BEQ        .L36                     ; 0x08001E20
+  0x08001E1C:  F002 FB1A    BL         .L292                    ; 0x08004454
+
.L36:
+  0x08001E20:  9822         LDR        R0, [SP, #136]
+  0x08001E22:  65F0         STR        R0, [R6, #92]
+  0x08001E24:  6DB0         LDR        R0, [R6, #88]
+  0x08001E26:  2501         MOVS       R5, #1
+  0x08001E28:  4328         ORRS       R0, R5
+  0x08001E2A:  990F         LDR        R1, [SP, #60]
+  0x08001E2C:  4388         BICS       R0, R1
+  0x08001E2E:  65B0         STR        R0, [R6, #88]
+  0x08001E30:  2F00         CMP        R7, #0
+  0x08001E32:  D100         BNE        .L37                     ; 0x08001E36
+  0x08001E34:  E185         B          .L61                     ; 0x08002142
+
.L37:
+  0x08001E36:  9525         STR        R5, [SP, #148]
+  0x08001E38:  06E8         LSLS       R0, R5, #27
+  0x08001E3A:  1D00         ADDS       R0, R0, #4
+  0x08001E3C:  9024         STR        R0, [SP, #144]
+  0x08001E3E:  A824         ADD        R0, SP, #144
+  0x08001E40:  F7FE FC42    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E44:  2800         CMP        R0, #0
+  0x08001E46:  D000         BEQ        .L38                     ; 0x08001E4A
+  0x08001E48:  E17B         B          .L61                     ; 0x08002142
+
.L38:
+  0x08001E4A:  4875         LDR        R0, =0x0C000008          ; [PC, #0x01D4] [0x08002020] 
+  0x08001E4C:  9024         STR        R0, [SP, #144]
+  0x08001E4E:  A824         ADD        R0, SP, #144
+  0x08001E50:  F7FE FC3A    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E54:  2800         CMP        R0, #0
+  0x08001E56:  D000         BEQ        .L39                     ; 0x08001E5A
+  0x08001E58:  E173         B          .L61                     ; 0x08002142
+
.L39:
+  0x08001E5A:  981F         LDR        R0, [SP, #124]
+  0x08001E5C:  3010         ADDS       R0, #16
+  0x08001E5E:  9024         STR        R0, [SP, #144]
+  0x08001E60:  A824         ADD        R0, SP, #144
+  0x08001E62:  F7FE FC31    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E66:  2800         CMP        R0, #0
+  0x08001E68:  D000         BEQ        .L40                     ; 0x08001E6C
+  0x08001E6A:  E16A         B          .L61                     ; 0x08002142
+
.L40:
+  0x08001E6C:  486D         LDR        R0, =0x14000020          ; [PC, #0x01B4] [0x08002024] 
+  0x08001E6E:  9024         STR        R0, [SP, #144]
+  0x08001E70:  A824         ADD        R0, SP, #144
+  0x08001E72:  F7FE FC29    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E76:  2800         CMP        R0, #0
+  0x08001E78:  D000         BEQ        .L41                     ; 0x08001E7C
+  0x08001E7A:  E162         B          .L61                     ; 0x08002142
+
.L41:
+  0x08001E7C:  486A         LDR        R0, =0xA4000200          ; [PC, #0x01A8] [0x08002028] 
+  0x08001E7E:  9024         STR        R0, [SP, #144]
+  0x08001E80:  A824         ADD        R0, SP, #144
+  0x08001E82:  F7FE FC21    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E86:  2800         CMP        R0, #0
+  0x08001E88:  D000         BEQ        .L42                     ; 0x08001E8C
+  0x08001E8A:  E15A         B          .L61                     ; 0x08002142
+
.L42:
+  0x08001E8C:  4F67         LDR        R7, =htim16              ; [PC, #0x019C] [0x0800202C] =0x20000614 
+  0x08001E8E:  2077         MOVS       R0, #119
+  0x08001E90:  4967         LDR        R1, =0x40014400          ; [PC, #0x019C] [0x08002030] 
+  0x08001E92:  6039         STR        R1, [R7]
+  0x08001E94:  6078         STR        R0, [R7, #4]
+  0x08001E96:  9922         LDR        R1, [SP, #136]
+  0x08001E98:  60B9         STR        R1, [R7, #8]
+  0x08001E9A:  485D         LDR        R0, =0x0000FFFF          ; [PC, #0x0174] [0x08002010] 
+  0x08001E9C:  60F8         STR        R0, [R7, #12]
+  0x08001E9E:  6139         STR        R1, [R7, #16]
+  0x08001EA0:  6179         STR        R1, [R7, #20]
+  0x08001EA2:  980A         LDR        R0, [SP, #40]
+  0x08001EA4:  61B8         STR        R0, [R7, #24]
+  0x08001EA6:  4638         MOV        R0, R7
+  0x08001EA8:  F7FF F836    BL         HAL_TIM_Base_Init        ; 0x08000F18
+  0x08001EAC:  2800         CMP        R0, #0
+  0x08001EAE:  D000         BEQ        .L43                     ; 0x08001EB2
+  0x08001EB0:  E147         B          .L61                     ; 0x08002142
+
.L43:
+  0x08001EB2:  263D         MOVS       R6, #61
+  0x08001EB4:  5DB8         LDRB       R0, [R7, R6]
+  0x08001EB6:  2800         CMP        R0, #0
+  0x08001EB8:  D101         BNE        .L44                     ; 0x08001EBE
+  0x08001EBA:  991C         LDR        R1, [SP, #112]
+  0x08001EBC:  5478         STRB       R0, [R7, R1]
+
.L44:
+  0x08001EBE:  980F         LDR        R0, [SP, #60]
+  0x08001EC0:  55B8         STRB       R0, [R7, R6]
+  0x08001EC2:  4639         MOV        R1, R7
+  0x08001EC4:  C901         LDM        R1!, {R0}
+  0x08001EC6:  F7FF F88D    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08001ECA:  2048         MOVS       R0, #72
+  0x08001ECC:  901F         STR        R0, [SP, #124]
+  0x08001ECE:  543D         STRB       R5, [R7, R0]
+  0x08001ED0:  203E         MOVS       R0, #62
+  0x08001ED2:  901B         STR        R0, [SP, #108]
+  0x08001ED4:  543D         STRB       R5, [R7, R0]
+  0x08001ED6:  203F         MOVS       R0, #63
+  0x08001ED8:  901E         STR        R0, [SP, #120]
+  0x08001EDA:  543D         STRB       R5, [R7, R0]
+  0x08001EDC:  9807         LDR        R0, [SP, #28]
+  0x08001EDE:  543D         STRB       R5, [R7, R0]
+  0x08001EE0:  2041         MOVS       R0, #65
+  0x08001EE2:  9019         STR        R0, [SP, #100]
+  0x08001EE4:  543D         STRB       R5, [R7, R0]
+  0x08001EE6:  2042         MOVS       R0, #66
+  0x08001EE8:  9016         STR        R0, [SP, #88]
+  0x08001EEA:  543D         STRB       R5, [R7, R0]
+  0x08001EEC:  2043         MOVS       R0, #67
+  0x08001EEE:  9015         STR        R0, [SP, #84]
+  0x08001EF0:  543D         STRB       R5, [R7, R0]
+  0x08001EF2:  2044         MOVS       R0, #68
+  0x08001EF4:  9011         STR        R0, [SP, #68]
+  0x08001EF6:  543D         STRB       R5, [R7, R0]
+  0x08001EF8:  2045         MOVS       R0, #69
+  0x08001EFA:  9018         STR        R0, [SP, #96]
+  0x08001EFC:  543D         STRB       R5, [R7, R0]
+  0x08001EFE:  2046         MOVS       R0, #70
+  0x08001F00:  900C         STR        R0, [SP, #48]
+  0x08001F02:  543D         STRB       R5, [R7, R0]
+  0x08001F04:  2047         MOVS       R0, #71
+  0x08001F06:  900B         STR        R0, [SP, #44]
+  0x08001F08:  543D         STRB       R5, [R7, R0]
+  0x08001F0A:  55BD         STRB       R5, [R7, R6]
+  0x08001F0C:  981C         LDR        R0, [SP, #112]
+  0x08001F0E:  5C38         LDRB       R0, [R7, R0]
+  0x08001F10:  2801         CMP        R0, #1
+  0x08001F12:  D100         BNE        .L45                     ; 0x08001F16
+  0x08001F14:  E115         B          .L61                     ; 0x08002142
+
.L45:
+  0x08001F16:  6838         LDR        R0, [R7]
+  0x08001F18:  6A01         LDR        R1, [R0, #32]
+  0x08001F1A:  6A02         LDR        R2, [R0, #32]
+  0x08001F1C:  43AA         BICS       R2, R5
+  0x08001F1E:  6202         STR        R2, [R0, #32]
+  0x08001F20:  6982         LDR        R2, [R0, #24]
+  0x08001F22:  4B44         LDR        R3, =0x40012C00          ; [PC, #0x0110] [0x08002034] 
+  0x08001F24:  4298         CMP        R0, R3
+  0x08001F26:  9605         STR        R6, [SP, #20]
+  0x08001F28:  D002         BEQ        .L46                     ; 0x08001F30
+  0x08001F2A:  4B43         LDR        R3, =0x40000400          ; [PC, #0x010C] [0x08002038] 
+  0x08001F2C:  4298         CMP        R0, R3
+  0x08001F2E:  D101         BNE        .L47                     ; 0x08001F34
+
.L46:
+  0x08001F30:  2303         MOVS       R3, #3
+  0x08001F32:  439A         BICS       R2, R3
+
.L47:
+  0x08001F34:  9B1C         LDR        R3, [SP, #112]
+  0x08001F36:  9E22         LDR        R6, [SP, #136]
+  0x08001F38:  54FE         STRB       R6, [R7, R3]
+  0x08001F3A:  432A         ORRS       R2, R5
+  0x08001F3C:  23F0         MOVS       R3, #240
+  0x08001F3E:  439A         BICS       R2, R3
+  0x08001F40:  6182         STR        R2, [R0, #24]
+  0x08001F42:  9A0F         LDR        R2, [SP, #60]
+  0x08001F44:  4311         ORRS       R1, R2
+  0x08001F46:  9A1A         LDR        R2, [SP, #104]
+  0x08001F48:  4391         BICS       R1, R2
+  0x08001F4A:  6201         STR        R1, [R0, #32]
+  0x08001F4C:  6981         LDR        R1, [R0, #24]
+  0x08001F4E:  220C         MOVS       R2, #12
+  0x08001F50:  920D         STR        R2, [SP, #52]
+  0x08001F52:  4391         BICS       R1, R2
+  0x08001F54:  6181         STR        R1, [R0, #24]
+  0x08001F56:  4F39         LDR        R7, =htim17              ; [PC, #228] [0x0800203C] =0x200005C8 
+  0x08001F58:  4A39         LDR        R2, =0x40014800          ; [PC, #228] [0x08002040] 
+  0x08001F5A:  9910         LDR        R1, [SP, #64]
+  0x08001F5C:  31DF         ADDS       R1, #223
+  0x08001F5E:  C744         STM        R7!, {R2, R6}
+  0x08001F60:  603E         STR        R6, [R7]
+  0x08001F62:  6079         STR        R1, [R7, #4]
+  0x08001F64:  60BE         STR        R6, [R7, #8]
+  0x08001F66:  60FE         STR        R6, [R7, #12]
+  0x08001F68:  990A         LDR        R1, [SP, #40]
+  0x08001F6A:  6139         STR        R1, [R7, #16]
+  0x08001F6C:  6981         LDR        R1, [R0, #24]
+  0x08001F6E:  6181         STR        R1, [R0, #24]
+  0x08001F70:  3F08         SUBS       R7, #8
+  0x08001F72:  4638         MOV        R0, R7
+  0x08001F74:  F7FE FFD0    BL         HAL_TIM_Base_Init        ; 0x08000F18
+  0x08001F78:  2800         CMP        R0, #0
+  0x08001F7A:  D000         BEQ        .L48                     ; 0x08001F7E
+  0x08001F7C:  E0E1         B          .L61                     ; 0x08002142
+
.L48:
+  0x08001F7E:  9E05         LDR        R6, [SP, #20]
+  0x08001F80:  5DB8         LDRB       R0, [R7, R6]
+  0x08001F82:  2800         CMP        R0, #0
+  0x08001F84:  463A         MOV        R2, R7
+  0x08001F86:  D101         BNE        .L49                     ; 0x08001F8C
+  0x08001F88:  991C         LDR        R1, [SP, #112]
+  0x08001F8A:  5450         STRB       R0, [R2, R1]
+
.L49:
+  0x08001F8C:  9F0F         LDR        R7, [SP, #60]
+  0x08001F8E:  5597         STRB       R7, [R2, R6]
+  0x08001F90:  4611         MOV        R1, R2
+  0x08001F92:  C901         LDM        R1!, {R0}
+  0x08001F94:  F7FF F826    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08001F98:  4928         LDR        R1, =htim17              ; [PC, #160] [0x0800203C] =0x200005C8 
+  0x08001F9A:  981F         LDR        R0, [SP, #124]
+  0x08001F9C:  540D         STRB       R5, [R1, R0]
+  0x08001F9E:  981B         LDR        R0, [SP, #108]
+  0x08001FA0:  540D         STRB       R5, [R1, R0]
+  0x08001FA2:  981E         LDR        R0, [SP, #120]
+  0x08001FA4:  540D         STRB       R5, [R1, R0]
+  0x08001FA6:  9807         LDR        R0, [SP, #28]
+  0x08001FA8:  540D         STRB       R5, [R1, R0]
+  0x08001FAA:  9819         LDR        R0, [SP, #100]
+  0x08001FAC:  540D         STRB       R5, [R1, R0]
+  0x08001FAE:  9816         LDR        R0, [SP, #88]
+  0x08001FB0:  540D         STRB       R5, [R1, R0]
+  0x08001FB2:  9815         LDR        R0, [SP, #84]
+  0x08001FB4:  540D         STRB       R5, [R1, R0]
+  0x08001FB6:  9811         LDR        R0, [SP, #68]
+  0x08001FB8:  540D         STRB       R5, [R1, R0]
+  0x08001FBA:  9818         LDR        R0, [SP, #96]
+  0x08001FBC:  540D         STRB       R5, [R1, R0]
+  0x08001FBE:  980C         LDR        R0, [SP, #48]
+  0x08001FC0:  540D         STRB       R5, [R1, R0]
+  0x08001FC2:  980B         LDR        R0, [SP, #44]
+  0x08001FC4:  540D         STRB       R5, [R1, R0]
+  0x08001FC6:  558D         STRB       R5, [R1, R6]
+  0x08001FC8:  981C         LDR        R0, [SP, #112]
+  0x08001FCA:  5C08         LDRB       R0, [R1, R0]
+  0x08001FCC:  2801         CMP        R0, #1
+  0x08001FCE:  D100         BNE        .L50                     ; 0x08001FD2
+  0x08001FD0:  E0B7         B          .L61                     ; 0x08002142
+
.L50:
+  0x08001FD2:  6808         LDR        R0, [R1]
+  0x08001FD4:  6A01         LDR        R1, [R0, #32]
+  0x08001FD6:  6A02         LDR        R2, [R0, #32]
+  0x08001FD8:  43AA         BICS       R2, R5
+  0x08001FDA:  6202         STR        R2, [R0, #32]
+  0x08001FDC:  4339         ORRS       R1, R7
+  0x08001FDE:  6846         LDR        R6, [R0, #4]
+  0x08001FE0:  6982         LDR        R2, [R0, #24]
+  0x08001FE2:  921F         STR        R2, [SP, #124]
+  0x08001FE4:  4B13         LDR        R3, =0x40012C00          ; [PC, #76] [0x08002034] 
+  0x08001FE6:  4298         CMP        R0, R3
+  0x08001FE8:  D02C         BEQ        .L53                     ; 0x08002044
+  0x08001FEA:  4B15         LDR        R3, =0x40014800          ; [PC, #84] [0x08002040] 
+  0x08001FEC:  4298         CMP        R0, R3
+  0x08001FEE:  D002         BEQ        .L51                     ; 0x08001FF6
+  0x08001FF0:  4B0F         LDR        R3, =0x40014400          ; [PC, #60] [0x08002030] 
+  0x08001FF2:  4298         CMP        R0, R3
+  0x08001FF4:  D101         BNE        .L52                     ; 0x08001FFA
+
.L51:
+  0x08001FF6:  9F0D         LDR        R7, [SP, #52]
+  0x08001FF8:  43B9         BICS       R1, R7
+
.L52:
+  0x08001FFA:  4B11         LDR        R3, =0x40014800          ; [PC, #68] [0x08002040] 
+  0x08001FFC:  4298         CMP        R0, R3
+  0x08001FFE:  D023         BEQ        .L54                     ; 0x08002048
+  0x08002000:  4B0B         LDR        R3, =0x40014400          ; [PC, #44] [0x08002030] 
+  0x08002002:  4298         CMP        R0, R3
+  0x08002004:  D020         BEQ        .L54                     ; 0x08002048
+  0x08002006:  E021         B          .L55                     ; 0x0800204C
+  0x08002008:  FFFFFEFD     DC.W       0xFFFFFEFD
+  0x0800200C:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08002010:  0000FFFF     DC.W       0x0000FFFF
+  0x08002014:  FFDE0201     DC.W       0xFFDE0201
+  0x08002018:  1FFFFC02     DC.W       0x1FFFFC02
+  0x0800201C:  40012708     DC.W       0x40012708
+  0x08002020:  0C000008     DC.W       0x0C000008
+  0x08002024:  14000020     DC.W       0x14000020
+  0x08002028:  A4000200     DC.W       0xA4000200
+  0x0800202C:  20000614     DC.W       htim16
+  0x08002030:  40014400     DC.W       0x40014400
+  0x08002034:  40012C00     DC.W       0x40012C00
+  0x08002038:  40000400     DC.W       0x40000400
+  0x0800203C:  200005C8     DC.W       htim17
+  0x08002040:  40014800     DC.W       0x40014800
+
.L53:
+  0x08002044:  9F0D         LDR        R7, [SP, #52]
+  0x08002046:  43B9         BICS       R1, R7
+
.L54:
+  0x08002048:  4BBB         LDR        R3, =0xFFFFFCFF          ; [PC, #0x02EC] [0x08002338] 
+  0x0800204A:  401E         ANDS       R6, R3
+
.L55:
+  0x0800204C:  4632         MOV        R2, R6
+  0x0800204E:  9F1C         LDR        R7, [SP, #112]
+  0x08002050:  4BBA         LDR        R3, =htim17              ; [PC, #0x02E8] [0x0800233C] =0x200005C8 
+  0x08002052:  9E22         LDR        R6, [SP, #136]
+  0x08002054:  55DE         STRB       R6, [R3, R7]
+  0x08002056:  6042         STR        R2, [R0, #4]
+  0x08002058:  4BB9         LDR        R3, =0xFFFEFF8C          ; [PC, #0x02E4] [0x08002340] 
+  0x0800205A:  9A1F         LDR        R2, [SP, #124]
+  0x0800205C:  401A         ANDS       R2, R3
+  0x0800205E:  3260         ADDS       R2, #96
+  0x08002060:  6182         STR        R2, [R0, #24]
+  0x08002062:  6346         STR        R6, [R0, #52]
+  0x08002064:  6201         STR        R1, [R0, #32]
+  0x08002066:  6981         LDR        R1, [R0, #24]
+  0x08002068:  9A1A         LDR        R2, [SP, #104]
+  0x0800206A:  4311         ORRS       R1, R2
+  0x0800206C:  6181         STR        R1, [R0, #24]
+  0x0800206E:  6981         LDR        R1, [R0, #24]
+  0x08002070:  9A0E         LDR        R2, [SP, #56]
+  0x08002072:  4391         BICS       R1, R2
+  0x08002074:  6181         STR        R1, [R0, #24]
+  0x08002076:  6981         LDR        R1, [R0, #24]
+  0x08002078:  6181         STR        R1, [R0, #24]
+  0x0800207A:  036F         LSLS       R7, R5, #13
+  0x0800207C:  6447         STR        R7, [R0, #68]
+  0x0800207E:  49B1         LDR        R1, =0x40014800          ; [PC, #0x02C4] [0x08002344] 
+  0x08002080:  4288         CMP        R0, R1
+  0x08002082:  4EB1         LDR        R6, =0x000003C7          ; [PC, #0x02C4] [0x08002348] 
+  0x08002084:  D142         BNE        .L59                     ; 0x0800210C
+  0x08002086:  6B60         LDR        R0, [R4, #52]
+  0x08002088:  2601         MOVS       R6, #1
+  0x0800208A:  4330         ORRS       R0, R6
+  0x0800208C:  6360         STR        R0, [R4, #52]
+  0x0800208E:  6B60         LDR        R0, [R4, #52]
+  0x08002090:  4030         ANDS       R0, R6
+  0x08002092:  9030         STR        R0, [SP, #192]
+  0x08002094:  2005         MOVS       R0, #5
+  0x08002096:  902D         STR        R0, [SP, #180]
+  0x08002098:  2000         MOVS       R0, #0
+  0x0800209A:  902C         STR        R0, [SP, #176]
+  0x0800209C:  902B         STR        R0, [SP, #172]
+  0x0800209E:  2402         MOVS       R4, #2
+  0x080020A0:  942A         STR        R4, [SP, #168]
+  0x080020A2:  980A         LDR        R0, [SP, #40]
+  0x080020A4:  9029         STR        R0, [SP, #164]
+  0x080020A6:  9830         LDR        R0, [SP, #192]
+  0x080020A8:  A929         ADD        R1, SP, #164
+  0x080020AA:  9809         LDR        R0, [SP, #36]
+  0x080020AC:  F7FE FDA6    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x080020B0:  49A2         LDR        R1, =htim17              ; [PC, #0x0288] [0x0800233C] =0x200005C8 
+  0x080020B2:  9A1B         LDR        R2, [SP, #108]
+  0x080020B4:  5C88         LDRB       R0, [R1, R2]
+  0x080020B6:  2801         CMP        R0, #1
+  0x080020B8:  D143         BNE        .L61                     ; 0x08002142
+  0x080020BA:  548C         STRB       R4, [R1, R2]
+  0x080020BC:  6808         LDR        R0, [R1]
+  0x080020BE:  6A01         LDR        R1, [R0, #32]
+  0x080020C0:  43B1         BICS       R1, R6
+  0x080020C2:  6201         STR        R1, [R0, #32]
+  0x080020C4:  6A01         LDR        R1, [R0, #32]
+  0x080020C6:  4331         ORRS       R1, R6
+  0x080020C8:  6201         STR        R1, [R0, #32]
+  0x080020CA:  49A0         LDR        R1, =0x40000400          ; [PC, #0x0280] [0x0800234C] 
+  0x080020CC:  4288         CMP        R0, R1
+  0x080020CE:  4633         MOV        R3, R6
+  0x080020D0:  4E9D         LDR        R6, =0x000003C7          ; [PC, #0x0274] [0x08002348] 
+  0x080020D2:  D00F         BEQ        .L57                     ; 0x080020F4
+  0x080020D4:  499E         LDR        R1, =0x40012C00          ; [PC, #0x0278] [0x08002350] 
+  0x080020D6:  4288         CMP        R0, R1
+  0x080020D8:  D005         BEQ        .L56                     ; 0x080020E6
+  0x080020DA:  499A         LDR        R1, =0x40014800          ; [PC, #0x0268] [0x08002344] 
+  0x080020DC:  4288         CMP        R0, R1
+  0x080020DE:  D002         BEQ        .L56                     ; 0x080020E6
+  0x080020E0:  499C         LDR        R1, =0x40014400          ; [PC, #0x0270] [0x08002354] 
+  0x080020E2:  4288         CMP        R0, R1
+  0x080020E4:  D10F         BNE        .L58                     ; 0x08002106
+
.L56:
+  0x080020E6:  03D9         LSLS       R1, R3, #15
+  0x080020E8:  6C42         LDR        R2, [R0, #68]
+  0x080020EA:  430A         ORRS       R2, R1
+  0x080020EC:  6442         STR        R2, [R0, #68]
+  0x080020EE:  4998         LDR        R1, =0x40012C00          ; [PC, #0x0260] [0x08002350] 
+  0x080020F0:  4288         CMP        R0, R1
+  0x080020F2:  D108         BNE        .L58                     ; 0x08002106
+
.L57:
+  0x080020F4:  4A98         LDR        R2, =0x0000FFFF          ; [PC, #0x0260] [0x08002358] 
+  0x080020F6:  3208         ADDS       R2, #8
+  0x080020F8:  6881         LDR        R1, [R0, #8]
+  0x080020FA:  4011         ANDS       R1, R2
+  0x080020FC:  2906         CMP        R1, #6
+  0x080020FE:  D005         BEQ        .L59                     ; 0x0800210C
+  0x08002100:  041A         LSLS       R2, R3, #16
+  0x08002102:  4291         CMP        R1, R2
+  0x08002104:  D002         BEQ        .L59                     ; 0x0800210C
+
.L58:
+  0x08002106:  6801         LDR        R1, [R0]
+  0x08002108:  4319         ORRS       R1, R3
+  0x0800210A:  6001         STR        R1, [R0]
+
.L59:
+  0x0800210C:  4993         LDR        R1, =0x40003000          ; [PC, #0x024C] [0x0800235C] 
+  0x0800210E:  4894         LDR        R0, =0x0000CCCC          ; [PC, #0x0250] [0x08002360] 
+  0x08002110:  6008         STR        R0, [R1]
+  0x08002112:  4894         LDR        R0, =0x00005555          ; [PC, #0x0250] [0x08002364] 
+  0x08002114:  6008         STR        R0, [R1]
+  0x08002116:  9814         LDR        R0, [SP, #80]
+  0x08002118:  6048         STR        R0, [R1, #4]
+  0x0800211A:  4630         MOV        R0, R6
+  0x0800211C:  3021         ADDS       R0, #33
+  0x0800211E:  900B         STR        R0, [SP, #44]
+  0x08002120:  6088         STR        R0, [R1, #8]
+  0x08002122:  4891         LDR        R0, =uwTick              ; [PC, #0x0244] [0x08002368] =0x2000068C 
+  0x08002124:  6800         LDR        R0, [R0]
+  0x08002126:  9A13         LDR        R2, [SP, #76]
+
.L60:
+  0x08002128:  68C9         LDR        R1, [R1, #12]
+  0x0800212A:  0749         LSLS       R1, R1, #29
+  0x0800212C:  D00B         BEQ        .L62                     ; 0x08002146
+  0x0800212E:  498E         LDR        R1, =uwTick              ; [PC, #0x0238] [0x08002368] =0x2000068C 
+  0x08002130:  6809         LDR        R1, [R1]
+  0x08002132:  1A09         SUBS       R1, R1, R0
+  0x08002134:  2932         CMP        R1, #50
+  0x08002136:  4989         LDR        R1, =0x40003000          ; [PC, #0x0224] [0x0800235C] 
+  0x08002138:  D3F6         BCC        .L60                     ; 0x08002128
+  0x0800213A:  68C9         LDR        R1, [R1, #12]
+  0x0800213C:  0749         LSLS       R1, R1, #29
+  0x0800213E:  4987         LDR        R1, =0x40003000          ; [PC, #0x021C] [0x0800235C] 
+  0x08002140:  D0F2         BEQ        .L60                     ; 0x08002128
+
.L61:
+  0x08002142:  F003 FE84    BL         Error_Handler            ; 0x08005E4E
+
.L62:
+  0x08002146:  4985         LDR        R1, =0x40003000          ; [PC, #0x0214] [0x0800235C] 
+  0x08002148:  6908         LDR        R0, [R1, #16]
+  0x0800214A:  9B0B         LDR        R3, [SP, #44]
+  0x0800214C:  4298         CMP        R0, R3
+  0x0800214E:  D102         BNE        .L63                     ; 0x08002156
+  0x08002150:  4886         LDR        R0, =0x0000AAAA          ; [PC, #0x0218] [0x0800236C] 
+  0x08002152:  6008         STR        R0, [R1]
+  0x08002154:  E000         B          .L64                     ; 0x08002158
+
.L63:
+  0x08002156:  610B         STR        R3, [R1, #16]
+
.L64:
+  0x08002158:  9921         LDR        R1, [SP, #132]
+  0x0800215A:  4C85         LDR        R4, =huart1              ; [PC, #0x0214] [0x08002370] =0x200003BC 
+  0x0800215C:  4885         LDR        R0, =0x40013800          ; [PC, #0x0214] [0x08002374] 
+  0x0800215E:  6020         STR        R0, [R4]
+  0x08002160:  204B         MOVS       R0, #75
+  0x08002162:  9006         STR        R0, [SP, #24]
+  0x08002164:  0206         LSLS       R6, R0, #8
+  0x08002166:  6066         STR        R6, [R4, #4]
+  0x08002168:  60A2         STR        R2, [R4, #8]
+  0x0800216A:  9822         LDR        R0, [SP, #136]
+  0x0800216C:  60E0         STR        R0, [R4, #12]
+  0x0800216E:  6121         STR        R1, [R4, #16]
+  0x08002170:  980D         LDR        R0, [SP, #52]
+  0x08002172:  6160         STR        R0, [R4, #20]
+  0x08002174:  4620         MOV        R0, R4
+  0x08002176:  3018         ADDS       R0, #24
+  0x08002178:  2114         MOVS       R1, #20
+  0x0800217A:  F003 FFCC    BL         __aeabi_memclr           ; 0x08006116
+  0x0800217E:  F7FE FF79    BL         HAL_UART_Init            ; 0x08001074
+  0x08002182:  2800         CMP        R0, #0
+  0x08002184:  D1DD         BNE        .L61                     ; 0x08002142
+  0x08002186:  9619         STR        R6, [SP, #100]
+  0x08002188:  9715         STR        R7, [SP, #84]
+  0x0800218A:  2184         MOVS       R1, #132
+  0x0800218C:  5C60         LDRB       R0, [R4, R1]
+  0x0800218E:  2801         CMP        R0, #1
+  0x08002190:  D0D7         BEQ        .L61                     ; 0x08002142
+  0x08002192:  2788         MOVS       R7, #136
+  0x08002194:  2624         MOVS       R6, #36
+  0x08002196:  51E6         STR        R6, [R4, R7]
+  0x08002198:  5465         STRB       R5, [R4, R1]
+  0x0800219A:  6820         LDR        R0, [R4]
+  0x0800219C:  6804         LDR        R4, [R0]
+  0x0800219E:  43EA         MVNS       R2, R5
+  0x080021A0:  921E         STR        R2, [SP, #120]
+  0x080021A2:  911F         STR        R1, [SP, #124]
+  0x080021A4:  6801         LDR        R1, [R0]
+  0x080021A6:  4011         ANDS       R1, R2
+  0x080021A8:  6001         STR        R1, [R0]
+  0x080021AA:  9923         LDR        R1, [SP, #140]
+  0x080021AC:  0749         LSLS       R1, R1, #29
+  0x080021AE:  6882         LDR        R2, [R0, #8]
+  0x080021B0:  438A         BICS       R2, R1
+  0x080021B2:  6082         STR        R2, [R0, #8]
+  0x080021B4:  F7FF FA48    BL         UARTEx_SetNbDataToProcess ; 0x08001648
+  0x080021B8:  486D         LDR        R0, =huart1              ; [PC, #0x01B4] [0x08002370] =0x200003BC 
+  0x080021BA:  6800         LDR        R0, [R0]
+  0x080021BC:  6004         STR        R4, [R0]
+  0x080021BE:  9C20         LDR        R4, [SP, #128]
+  0x080021C0:  496B         LDR        R1, =huart1              ; [PC, #0x01AC] [0x08002370] =0x200003BC 
+  0x080021C2:  51CC         STR        R4, [R1, R7]
+  0x080021C4:  51CE         STR        R6, [R1, R7]
+  0x080021C6:  9A1F         LDR        R2, [SP, #124]
+  0x080021C8:  548D         STRB       R5, [R1, R2]
+  0x080021CA:  6801         LDR        R1, [R0]
+  0x080021CC:  9116         STR        R1, [SP, #88]
+  0x080021CE:  6801         LDR        R1, [R0]
+  0x080021D0:  9A1E         LDR        R2, [SP, #120]
+  0x080021D2:  4011         ANDS       R1, R2
+  0x080021D4:  6001         STR        R1, [R0]
+  0x080021D6:  9923         LDR        R1, [SP, #140]
+  0x080021D8:  0649         LSLS       R1, R1, #25
+  0x080021DA:  6882         LDR        R2, [R0, #8]
+  0x080021DC:  438A         BICS       R2, R1
+  0x080021DE:  6082         STR        R2, [R0, #8]
+  0x080021E0:  F7FF FA32    BL         UARTEx_SetNbDataToProcess ; 0x08001648
+  0x080021E4:  4862         LDR        R0, =huart1              ; [PC, #0x0188] [0x08002370] =0x200003BC 
+  0x080021E6:  6800         LDR        R0, [R0]
+  0x080021E8:  9916         LDR        R1, [SP, #88]
+  0x080021EA:  6001         STR        R1, [R0]
+  0x080021EC:  4960         LDR        R1, =huart1              ; [PC, #0x0180] [0x08002370] =0x200003BC 
+  0x080021EE:  51CC         STR        R4, [R1, R7]
+  0x080021F0:  9616         STR        R6, [SP, #88]
+  0x080021F2:  51CE         STR        R6, [R1, R7]
+  0x080021F4:  9E22         LDR        R6, [SP, #136]
+  0x080021F6:  9A1F         LDR        R2, [SP, #124]
+  0x080021F8:  548E         STRB       R6, [R1, R2]
+  0x080021FA:  6801         LDR        R1, [R0]
+  0x080021FC:  6802         LDR        R2, [R0]
+  0x080021FE:  9B1E         LDR        R3, [SP, #120]
+  0x08002200:  401A         ANDS       R2, R3
+  0x08002202:  4B5B         LDR        R3, =huart1              ; [PC, #0x016C] [0x08002370] =0x200003BC 
+  0x08002204:  6002         STR        R2, [R0]
+  0x08002206:  076A         LSLS       R2, R5, #29
+  0x08002208:  4391         BICS       R1, R2
+  0x0800220A:  6001         STR        R1, [R0]
+  0x0800220C:  970C         STR        R7, [SP, #48]
+  0x0800220E:  51DC         STR        R4, [R3, R7]
+  0x08002210:  665E         STR        R6, [R3, #100]
+  0x08002212:  4859         LDR        R0, =0x0800780E          ; [PC, #0x0164] [0x08002378] 
+  0x08002214:  8800         LDRH       R0, [R0]
+  0x08002216:  2802         CMP        R0, #2
+  0x08002218:  D003         BEQ        .L65                     ; 0x08002222
+  0x0800221A:  28FF         CMP        R0, #255
+  0x0800221C:  D105         BNE        .L66                     ; 0x0800222A
+  0x0800221E:  4857         LDR        R0, =0x08006373          ; [PC, #0x015C] [0x0800237C] 
+  0x08002220:  E004         B          .L67                     ; 0x0800222C
+
.L65:
+  0x08002222:  4857         LDR        R0, =0x08006361          ; [PC, #0x015C] [0x08002380] 
+  0x08002224:  F002 FF98    BL         puts                     ; 0x08005158
+  0x08002228:  E004         B          .L68                     ; 0x08002234
+
.L66:
+  0x0800222A:  4856         LDR        R0, =0x08006165          ; [PC, #0x0158] [0x08002384] 
+
.L67:
+  0x0800222C:  F002 FF94    BL         puts                     ; 0x08005158
+  0x08002230:  F7FF FAC0    BL         EEPROM_WriteDefaults     ; 0x080017B4
+
.L68:
+  0x08002234:  9C13         LDR        R4, [SP, #76]
+  0x08002236:  F7FF FAD5    BL         EEPROM_ReadDeviceParameter ; 0x080017E4
+  0x0800223A:  9806         LDR        R0, [SP, #24]
+  0x0800223C:  00C0         LSLS       R0, R0, #3
+  0x0800223E:  4F52         LDR        R7, =sys_data            ; [PC, #0x0148] [0x08002388] =0x20000234 
+  0x08002240:  8038         STRH       R0, [R7]
+  0x08002242:  813D         STRH       R5, [R7, #8]
+  0x08002244:  817E         STRH       R6, [R7, #10]
+  0x08002246:  81BE         STRH       R6, [R7, #12]
+  0x08002248:  4850         LDR        R0, =0x080067F8          ; [PC, #0x0140] [0x0800238C] 
+  0x0800224A:  F002 FF85    BL         puts                     ; 0x08005158
+  0x0800224E:  693A         LDR        R2, [R7, #16]
+  0x08002250:  8AB9         LDRH       R1, [R7, #20]
+  0x08002252:  8AF8         LDRH       R0, [R7, #22]
+  0x08002254:  2800         CMP        R0, #0
+  0x08002256:  D001         BEQ        .L69                     ; 0x0800225C
+  0x08002258:  2803         CMP        R0, #3
+  0x0800225A:  D300         BCC        .L70                     ; 0x0800225E
+
.L69:
+  0x0800225C:  2001         MOVS       R0, #1
+
.L70:
+  0x0800225E:  2900         CMP        R1, #0
+  0x08002260:  4F43         LDR        R7, =huart1              ; [PC, #0x010C] [0x08002370] =0x200003BC 
+  0x08002262:  9B21         LDR        R3, [SP, #132]
+  0x08002264:  D001         BEQ        .L71                     ; 0x0800226A
+  0x08002266:  2901         CMP        R1, #1
+  0x08002268:  D102         BNE        .L72                     ; 0x08002270
+
.L71:
+  0x0800226A:  4606         MOV        R6, R0
+  0x0800226C:  360A         ADDS       R6, #10
+  0x0800226E:  E001         B          .L73                     ; 0x08002274
+
.L72:
+  0x08002270:  4606         MOV        R6, R0
+  0x08002272:  3609         ADDS       R6, #9
+
.L73:
+  0x08002274:  9623         STR        R6, [SP, #140]
+  0x08002276:  4616         MOV        R6, R2
+  0x08002278:  607A         STR        R2, [R7, #4]
+  0x0800227A:  4A45         LDR        R2, =modbusData          ; [PC, #0x0114] [0x08002390] =0x20000000 
+  0x0800227C:  6017         STR        R7, [R2]
+  0x0800227E:  2900         CMP        R1, #0
+  0x08002280:  4622         MOV        R2, R4
+  0x08002282:  D006         BEQ        .L75                     ; 0x08002292
+  0x08002284:  2901         CMP        R1, #1
+  0x08002286:  D102         BNE        .L74                     ; 0x0800228E
+  0x08002288:  9914         LDR        R1, [SP, #80]
+  0x0800228A:  024B         LSLS       R3, R1, #9
+  0x0800228C:  E001         B          .L75                     ; 0x08002292
+
.L74:
+  0x0800228E:  9A22         LDR        R2, [SP, #136]
+  0x08002290:  4613         MOV        R3, R2
+
.L75:
+  0x08002292:  60BA         STR        R2, [R7, #8]
+  0x08002294:  613B         STR        R3, [R7, #16]
+  0x08002296:  2801         CMP        R0, #1
+  0x08002298:  D001         BEQ        .L76                     ; 0x0800229E
+  0x0800229A:  9815         LDR        R0, [SP, #84]
+  0x0800229C:  9022         STR        R0, [SP, #136]
+
.L76:
+  0x0800229E:  9822         LDR        R0, [SP, #136]
+  0x080022A0:  60F8         STR        R0, [R7, #12]
+  0x080022A2:  F7FE FEE7    BL         HAL_UART_Init            ; 0x08001074
+  0x080022A6:  2800         CMP        R0, #0
+  0x080022A8:  D001         BEQ        .L77                     ; 0x080022AE
+  0x080022AA:  F002 F8E0    BL         .L294                    ; 0x0800446E
+
.L77:
+  0x080022AE:  980C         LDR        R0, [SP, #48]
+  0x080022B0:  5838         LDR        R0, [R7, R0]
+  0x080022B2:  2820         CMP        R0, #32
+  0x080022B4:  991F         LDR        R1, [SP, #124]
+  0x080022B6:  4632         MOV        R2, R6
+  0x080022B8:  D110         BNE        .L78                     ; 0x080022DC
+  0x080022BA:  5C78         LDRB       R0, [R7, R1]
+  0x080022BC:  2801         CMP        R0, #1
+  0x080022BE:  D00D         BEQ        .L78                     ; 0x080022DC
+  0x080022C0:  9B0C         LDR        R3, [SP, #48]
+  0x080022C2:  9816         LDR        R0, [SP, #88]
+  0x080022C4:  50F8         STR        R0, [R7, R3]
+  0x080022C6:  2000         MOVS       R0, #0
+  0x080022C8:  5478         STRB       R0, [R7, R1]
+  0x080022CA:  2001         MOVS       R0, #1
+  0x080022CC:  05C0         LSLS       R0, R0, #23
+  0x080022CE:  6839         LDR        R1, [R7]
+  0x080022D0:  684A         LDR        R2, [R1, #4]
+  0x080022D2:  4302         ORRS       R2, R0
+  0x080022D4:  604A         STR        R2, [R1, #4]
+  0x080022D6:  4632         MOV        R2, R6
+  0x080022D8:  9820         LDR        R0, [SP, #128]
+  0x080022DA:  50F8         STR        R0, [R7, R3]
+
.L78:
+  0x080022DC:  9819         LDR        R0, [SP, #100]
+  0x080022DE:  1C40         ADDS       R0, R0, #1
+  0x080022E0:  4282         CMP        R2, R0
+  0x080022E2:  D209         BCS        .L79                     ; 0x080022F8
+  0x080022E4:  9823         LDR        R0, [SP, #140]
+  0x080022E6:  F003 FE52    BL         __aeabi_ui2d             ; 0x08005F8E
+  0x080022EA:  2200         MOVS       R2, #0
+  0x080022EC:  4B29         LDR        R3, =0x400C0000          ; [PC, #164] [0x08002394] 
+  0x080022EE:  F003 FB3A    BL         __aeabi_dmul             ; 0x08005966
+  0x080022F2:  F003 FBE1    BL         __aeabi_d2uiz            ; 0x08005AB8
+  0x080022F6:  E007         B          .L80                     ; 0x08002308
+
.L79:
+  0x080022F8:  9814         LDR        R0, [SP, #80]
+  0x080022FA:  0240         LSLS       R0, R0, #9
+  0x080022FC:  30D6         ADDS       R0, #214
+  0x080022FE:  4350         MULS       R0, R2, R0
+  0x08002300:  4925         LDR        R1, =0x000F4240          ; [PC, #148] [0x08002398] 
+  0x08002302:  F003 FE72    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08002306:  1C40         ADDS       R0, R0, #1
+
.L80:
+  0x08002308:  4924         LDR        R1, =0xFEFFFFFF          ; [PC, #144] [0x0800239C] 
+  0x0800230A:  1C49         ADDS       R1, R1, #1
+  0x0800230C:  683A         LDR        R2, [R7]
+  0x0800230E:  6953         LDR        R3, [R2, #20]
+  0x08002310:  400B         ANDS       R3, R1
+  0x08002312:  4303         ORRS       R3, R0
+  0x08002314:  6153         STR        R3, [R2, #20]
+  0x08002316:  06A8         LSLS       R0, R5, #26
+  0x08002318:  6811         LDR        R1, [R2]
+  0x0800231A:  4301         ORRS       R1, R0
+  0x0800231C:  6011         STR        R1, [R2]
+  0x0800231E:  4C1C         LDR        R4, =modbusData          ; [PC, #112] [0x08002390] =0x20000000 
+  0x08002320:  6820         LDR        R0, [R4]
+  0x08002322:  4627         MOV        R7, R4
+  0x08002324:  3727         ADDS       R7, #39
+  0x08002326:  4639         MOV        R1, R7
+  0x08002328:  F7FF F912    BL         HAL_UART_Receive_DMA     ; 0x08001550
+  0x0800232C:  2800         CMP        R0, #0
+  0x0800232E:  D039         BEQ        .L82                     ; 0x080023A4
+  0x08002330:  481B         LDR        R0, =0x080063A1          ; [PC, #108] [0x080023A0] 
+  0x08002332:  F002 FF6B    BL         printf                   ; 0x0800520C
+
.L81:
+  0x08002336:  E7FE         B          .L81                     ; 0x08002336
+  0x08002338:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x0800233C:  200005C8     DC.W       htim17
+  0x08002340:  FFFEFF8C     DC.W       0xFFFEFF8C
+  0x08002344:  40014800     DC.W       0x40014800
+  0x08002348:  000003C7     DC.W       0x000003C7
+  0x0800234C:  40000400     DC.W       0x40000400
+  0x08002350:  40012C00     DC.W       0x40012C00
+  0x08002354:  40014400     DC.W       0x40014400
+  0x08002358:  0000FFFF     DC.W       0x0000FFFF
+  0x0800235C:  40003000     DC.W       0x40003000
+  0x08002360:  0000CCCC     DC.W       0x0000CCCC
+  0x08002364:  00005555     DC.W       0x00005555
+  0x08002368:  2000068C     DC.W       uwTick
+  0x0800236C:  0000AAAA     DC.W       0x0000AAAA
+  0x08002370:  200003BC     DC.W       huart1
+  0x08002374:  40013800     DC.W       0x40013800
+  0x08002378:  0800780E     DC.W       0x0800780E
+  0x0800237C:  08006373     DC.W       08006373               ; R_ARM_ABS32
+  0x08002380:  08006361     DC.W       08006361               ; R_ARM_ABS32
+  0x08002384:  08006165     DC.W       08006165               ; R_ARM_ABS32
+  0x08002388:  20000234     DC.W       sys_data
+  0x0800238C:  080067F8     DC.W       080067F8               ; R_ARM_ABS32
+  0x08002390:  20000000     DC.W       modbusData
+  0x08002394:  400C0000     DC.W       0x400C0000
+  0x08002398:  000F4240     DC.W       0x000F4240
+  0x0800239C:  FEFFFFFF     DC.W       0xFEFFFFFF
+  0x080023A0:  080063A1     DC.W       080063A1               ; R_ARM_ABS32
+
.L82:
+  0x080023A4:  9716         STR        R7, [SP, #88]
+  0x080023A6:  2026         MOVS       R0, #38
+  0x080023A8:  2100         MOVS       R1, #0
+  0x080023AA:  9022         STR        R0, [SP, #136]
+  0x080023AC:  5421         STRB       R1, [R4, R0]
+  0x080023AE:  61E1         STR        R1, [R4, #28]
+  0x080023B0:  84A1         STRH       R1, [R4, #36]
+  0x080023B2:  8421         STRH       R1, [R4, #32]
+  0x080023B4:  9123         STR        R1, [SP, #140]
+  0x080023B6:  4620         MOV        R0, R4
+  0x080023B8:  301C         ADDS       R0, #28
+  0x080023BA:  7181         STRB       R1, [R0, #6]
+  0x080023BC:  4EFD         LDR        R6, =0x50000410          ; [PC, #0x03F4] [0x080027B4] 
+  0x080023BE:  9820         LDR        R0, [SP, #128]
+  0x080023C0:  60B0         STR        R0, [R6, #8]
+  0x080023C2:  03EF         LSLS       R7, R5, #15
+  0x080023C4:  48FC         LDR        R0, =0x50000818          ; [PC, #0x03F0] [0x080027B8] 
+  0x080023C6:  6007         STR        R7, [R0]
+  0x080023C8:  03AC         LSLS       R4, R5, #14
+  0x080023CA:  6004         STR        R4, [R0]
+  0x080023CC:  9810         LDR        R0, [SP, #64]
+  0x080023CE:  30F4         ADDS       R0, #244
+  0x080023D0:  9009         STR        R0, [SP, #36]
+  0x080023D2:  F7FE F96F    BL         HAL_Delay                ; 0x080006B4
+  0x080023D6:  9820         LDR        R0, [SP, #128]
+  0x080023D8:  61B0         STR        R0, [R6, #24]
+  0x080023DA:  971E         STR        R7, [SP, #120]
+  0x080023DC:  48F6         LDR        R0, =0x50000818          ; [PC, #0x03D8] [0x080027B8] 
+  0x080023DE:  6107         STR        R7, [R0, #16]
+  0x080023E0:  941F         STR        R4, [SP, #124]
+  0x080023E2:  6104         STR        R4, [R0, #16]
+  0x080023E4:  48F5         LDR        R0, =0x50000010          ; [PC, #0x03D4] [0x080027BC] 
+  0x080023E6:  9910         LDR        R1, [SP, #64]
+  0x080023E8:  6081         STR        R1, [R0, #8]
+  0x080023EA:  9F1A         LDR        R7, [SP, #104]
+  0x080023EC:  61B7         STR        R7, [R6, #24]
+  0x080023EE:  2410         MOVS       R4, #16
+  0x080023F0:  60B4         STR        R4, [R6, #8]
+  0x080023F2:  2032         MOVS       R0, #50
+  0x080023F4:  9015         STR        R0, [SP, #84]
+  0x080023F6:  F7FE F95D    BL         HAL_Delay                ; 0x080006B4
+  0x080023FA:  9419         STR        R4, [SP, #100]
+  0x080023FC:  61B4         STR        R4, [R6, #24]
+  0x080023FE:  6830         LDR        R0, [R6]
+  0x08002400:  6831         LDR        R1, [R6]
+  0x08002402:  6832         LDR        R2, [R6]
+  0x08002404:  0992         LSRS       R2, R2, #6
+  0x08002406:  9B0E         LDR        R3, [SP, #56]
+  0x08002408:  401A         ANDS       R2, R3
+  0x0800240A:  0989         LSRS       R1, R1, #6
+  0x0800240C:  9B0F         LDR        R3, [SP, #60]
+  0x0800240E:  4019         ANDS       R1, R3
+  0x08002410:  0640         LSLS       R0, R0, #25
+  0x08002412:  0FC0         LSRS       R0, R0, #31
+  0x08002414:  1808         ADDS       R0, R1, R0
+  0x08002416:  1880         ADDS       R0, R0, R2
+  0x08002418:  6831         LDR        R1, [R6]
+  0x0800241A:  0989         LSRS       R1, R1, #6
+  0x0800241C:  4039         ANDS       R1, R7
+  0x0800241E:  1841         ADDS       R1, R0, R1
+  0x08002420:  270F         MOVS       R7, #15
+  0x08002422:  4079         EORS       R1, R7
+  0x08002424:  4CE6         LDR        R4, =mode                ; [PC, #0x0398] [0x080027C0] =0x20000739 
+  0x08002426:  7021         STRB       R1, [R4]
+  0x08002428:  48E6         LDR        R0, =0x08006736          ; [PC, #0x0398] [0x080027C4] 
+  0x0800242A:  F002 FEEF    BL         printf                   ; 0x0800520C
+  0x0800242E:  7820         LDRB       R0, [R4]
+  0x08002430:  49E5         LDR        R1, =sys_data            ; [PC, #0x0394] [0x080027C8] =0x20000234 
+  0x08002432:  8508         STRH       R0, [R1, #40]
+  0x08002434:  48E5         LDR        R0, =0x1FFF7568          ; [PC, #0x0394] [0x080027CC] 
+  0x08002436:  8800         LDRH       R0, [R0]
+  0x08002438:  F003 FB55    BL         __aeabi_ui2f             ; 0x08005AE6
+  0x0800243C:  2173         MOVS       R1, #115
+  0x0800243E:  05C9         LSLS       R1, R1, #23
+  0x08002440:  F003 FA1A    BL         __aeabi_fmul             ; 0x08005878
+  0x08002444:  49E2         LDR        R1, =0x453B8000          ; [PC, #0x0388] [0x080027D0] 
+  0x08002446:  F003 FA17    BL         __aeabi_fmul             ; 0x08005878
+  0x0800244A:  F003 FD8E    BL         __aeabi_f2uiz            ; 0x08005F6A
+  0x0800244E:  49E1         LDR        R1, =calTemperatureSensor30Value ; [PC, #0x0384] [0x080027D4] =0x200006E8 
+  0x08002450:  6008         STR        R0, [R1]
+  0x08002452:  9823         LDR        R0, [SP, #140]
+  0x08002454:  9029         STR        R0, [SP, #164]
+  0x08002456:  4EE0         LDR        R6, =hadc1               ; [PC, #0x0380] [0x080027D8] =0x20000450 
+  0x08002458:  2254         MOVS       R2, #84
+  0x0800245A:  5CB0         LDRB       R0, [R6, R2]
+  0x0800245C:  2801         CMP        R0, #1
+  0x0800245E:  6834         LDR        R4, [R6]
+  0x08002460:  4628         MOV        R0, R5
+  0x08002462:  9221         STR        R2, [SP, #132]
+  0x08002464:  D069         BEQ        .L94                     ; 0x0800253A
+  0x08002466:  9703         STR        R7, [SP, #12]
+  0x08002468:  2701         MOVS       R7, #1
+  0x0800246A:  54B7         STRB       R7, [R6, R2]
+  0x0800246C:  68A1         LDR        R1, [R4, #8]
+  0x0800246E:  68A2         LDR        R2, [R4, #8]
+  0x08002470:  07D2         LSLS       R2, R2, #31
+  0x08002472:  D01F         BEQ        .L85                     ; 0x080024B4
+  0x08002474:  980F         LDR        R0, [SP, #60]
+  0x08002476:  4001         ANDS       R1, R0
+  0x08002478:  D11C         BNE        .L85                     ; 0x080024B4
+  0x0800247A:  68A1         LDR        R1, [R4, #8]
+  0x0800247C:  2205         MOVS       R2, #5
+  0x0800247E:  400A         ANDS       R2, R1
+  0x08002480:  2A01         CMP        R2, #1
+  0x08002482:  D110         BNE        .L84                     ; 0x080024A6
+  0x08002484:  68A1         LDR        R1, [R4, #8]
+  0x08002486:  48D5         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0354] [0x080027DC] 
+  0x08002488:  4001         ANDS       R1, R0
+  0x0800248A:  980F         LDR        R0, [SP, #60]
+  0x0800248C:  4301         ORRS       R1, R0
+  0x0800248E:  60A1         STR        R1, [R4, #8]
+  0x08002490:  9814         LDR        R0, [SP, #80]
+  0x08002492:  6020         STR        R0, [R4]
+  0x08002494:  48D2         LDR        R0, =uwTick              ; [PC, #0x0348] [0x080027E0] =0x2000068C 
+  0x08002496:  6801         LDR        R1, [R0]
+
.L83:
+  0x08002498:  68A2         LDR        R2, [R4, #8]
+  0x0800249A:  07D2         LSLS       R2, R2, #31
+  0x0800249C:  D00A         BEQ        .L85                     ; 0x080024B4
+  0x0800249E:  6802         LDR        R2, [R0]
+  0x080024A0:  1A52         SUBS       R2, R2, R1
+  0x080024A2:  2A03         CMP        R2, #3
+  0x080024A4:  D3F8         BCC        .L83                     ; 0x08002498
+
.L84:
+  0x080024A6:  6DB1         LDR        R1, [R6, #88]
+  0x080024A8:  9819         LDR        R0, [SP, #100]
+  0x080024AA:  4301         ORRS       R1, R0
+  0x080024AC:  65B1         STR        R1, [R6, #88]
+  0x080024AE:  6DF1         LDR        R1, [R6, #92]
+  0x080024B0:  4339         ORRS       R1, R7
+  0x080024B2:  65F1         STR        R1, [R6, #92]
+
.L85:
+  0x080024B4:  68A1         LDR        R1, [R4, #8]
+  0x080024B6:  07C9         LSLS       R1, R1, #31
+  0x080024B8:  6DB1         LDR        R1, [R6, #88]
+  0x080024BA:  D12E         BNE        .L90                     ; 0x0800251A
+  0x080024BC:  9702         STR        R7, [SP, #8]
+  0x080024BE:  48C9         LDR        R0, =0xFFFFFEFD          ; [PC, #0x0324] [0x080027E4] 
+  0x080024C0:  4001         ANDS       R1, R0
+  0x080024C2:  980F         LDR        R0, [SP, #60]
+  0x080024C4:  4301         ORRS       R1, R0
+  0x080024C6:  65B1         STR        R1, [R6, #88]
+  0x080024C8:  68E1         LDR        R1, [R4, #12]
+  0x080024CA:  68E2         LDR        R2, [R4, #12]
+  0x080024CC:  4BC6         LDR        R3, =0xFFFF7FFC          ; [PC, #0x0318] [0x080027E8] 
+  0x080024CE:  4013         ANDS       R3, R2
+  0x080024D0:  60E3         STR        R3, [R4, #12]
+  0x080024D2:  981E         LDR        R0, [SP, #120]
+  0x080024D4:  1CC0         ADDS       R0, R0, #3
+  0x080024D6:  4008         ANDS       R0, R1
+  0x080024D8:  9001         STR        R0, [SP, #4]
+  0x080024DA:  4622         MOV        R2, R4
+  0x080024DC:  32B4         ADDS       R2, #180
+  0x080024DE:  2300         MOVS       R3, #0
+  0x080024E0:  461F         MOV        R7, R3
+
.L86:
+  0x080024E2:  2F08         CMP        R7, #8
+  0x080024E4:  68A1         LDR        R1, [R4, #8]
+  0x080024E6:  48BD         LDR        R0, =0x7FFFFFE8          ; [PC, #0x02F4] [0x080027DC] 
+  0x080024E8:  D101         BNE        .L87                     ; 0x080024EE
+  0x080024EA:  F001 FF5E    BL         .L284                    ; 0x080043AA
+
.L87:
+  0x080024EE:  4001         ANDS       R1, R0
+  0x080024F0:  1841         ADDS       R1, R0, R1
+  0x080024F2:  3118         ADDS       R1, #24
+  0x080024F4:  60A1         STR        R1, [R4, #8]
+
.L88:
+  0x080024F6:  68A1         LDR        R1, [R4, #8]
+  0x080024F8:  2900         CMP        R1, #0
+  0x080024FA:  D507         BPL        .L89                     ; 0x0800250C
+  0x080024FC:  9929         LDR        R1, [SP, #164]
+  0x080024FE:  1C49         ADDS       R1, R1, #1
+  0x08002500:  9129         STR        R1, [SP, #164]
+  0x08002502:  9929         LDR        R1, [SP, #164]
+  0x08002504:  0AC9         LSRS       R1, R1, #11
+  0x08002506:  2957         CMP        R1, #87
+  0x08002508:  D3F5         BCC        .L88                     ; 0x080024F6
+  0x0800250A:  E00C         B          .L92                     ; 0x08002526
+
.L89:
+  0x0800250C:  6811         LDR        R1, [R2]
+  0x0800250E:  207F         MOVS       R0, #127
+  0x08002510:  4008         ANDS       R0, R1
+  0x08002512:  1818         ADDS       R0, R3, R0
+  0x08002514:  1C43         ADDS       R3, R0, #1
+  0x08002516:  1C7F         ADDS       R7, R7, #1
+  0x08002518:  E7E3         B          .L86                     ; 0x080024E2
+
.L90:
+  0x0800251A:  9819         LDR        R0, [SP, #100]
+  0x0800251C:  4301         ORRS       R1, R0
+
.L91:
+  0x0800251E:  9A21         LDR        R2, [SP, #132]
+  0x08002520:  9823         LDR        R0, [SP, #140]
+  0x08002522:  54B0         STRB       R0, [R6, R2]
+  0x08002524:  E008         B          .L93                     ; 0x08002538
+
.L92:
+  0x08002526:  2000         MOVS       R0, #0
+  0x08002528:  9B21         LDR        R3, [SP, #132]
+  0x0800252A:  54F0         STRB       R0, [R6, R3]
+  0x0800252C:  6DB1         LDR        R1, [R6, #88]
+  0x0800252E:  9A19         LDR        R2, [SP, #100]
+  0x08002530:  4311         ORRS       R1, R2
+  0x08002532:  9A0F         LDR        R2, [SP, #60]
+  0x08002534:  4391         BICS       R1, R2
+  0x08002536:  461A         MOV        R2, R3
+
.L93:
+  0x08002538:  65B1         STR        R1, [R6, #88]
+
.L94:
+  0x0800253A:  68A1         LDR        R1, [R4, #8]
+  0x0800253C:  0749         LSLS       R1, R1, #29
+  0x0800253E:  4FAB         LDR        R7, =modbusData          ; [PC, #0x02AC] [0x080027EC] =0x20000000 
+  0x08002540:  D45C         BMI        .L101                    ; 0x080025FC
+  0x08002542:  2800         CMP        R0, #0
+  0x08002544:  D15A         BNE        .L101                    ; 0x080025FC
+  0x08002546:  2001         MOVS       R0, #1
+  0x08002548:  9023         STR        R0, [SP, #140]
+  0x0800254A:  54B0         STRB       R0, [R6, R2]
+  0x0800254C:  68E0         LDR        R0, [R4, #12]
+  0x0800254E:  07C0         LSLS       R0, R0, #31
+  0x08002550:  D10C         BNE        .L96                     ; 0x0800256C
+  0x08002552:  68A0         LDR        R0, [R4, #8]
+  0x08002554:  07C0         LSLS       R0, R0, #31
+  0x08002556:  D005         BEQ        .L95                     ; 0x08002564
+  0x08002558:  68A0         LDR        R0, [R4, #8]
+  0x0800255A:  49A0         LDR        R1, =0x7FFFFFE8          ; [PC, #0x0280] [0x080027DC] 
+  0x0800255C:  4008         ANDS       R0, R1
+  0x0800255E:  990F         LDR        R1, [SP, #60]
+  0x08002560:  4308         ORRS       R0, R1
+  0x08002562:  60A0         STR        R0, [R4, #8]
+
.L95:
+  0x08002564:  68E0         LDR        R0, [R4, #12]
+  0x08002566:  9923         LDR        R1, [SP, #140]
+  0x08002568:  4308         ORRS       R0, R1
+  0x0800256A:  60E0         STR        R0, [R4, #12]
+
.L96:
+  0x0800256C:  2000         MOVS       R0, #0
+  0x0800256E:  9003         STR        R0, [SP, #12]
+  0x08002570:  9029         STR        R0, [SP, #164]
+  0x08002572:  68A0         LDR        R0, [R4, #8]
+  0x08002574:  07C0         LSLS       R0, R0, #31
+  0x08002576:  D11E         BNE        .L100                    ; 0x080025B6
+  0x08002578:  4898         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0260] [0x080027DC] 
+  0x0800257A:  302F         ADDS       R0, #47
+  0x0800257C:  68A1         LDR        R1, [R4, #8]
+  0x0800257E:  4201         TST        R1, R0
+  0x08002580:  D008         BEQ        .L98                     ; 0x08002594
+
.L97:
+  0x08002582:  6DB0         LDR        R0, [R6, #88]
+  0x08002584:  9919         LDR        R1, [SP, #100]
+  0x08002586:  4308         ORRS       R0, R1
+  0x08002588:  65B0         STR        R0, [R6, #88]
+  0x0800258A:  6DF0         LDR        R0, [R6, #92]
+  0x0800258C:  9923         LDR        R1, [SP, #140]
+  0x0800258E:  4308         ORRS       R0, R1
+  0x08002590:  65F0         STR        R0, [R6, #92]
+  0x08002592:  E033         B          .L101                    ; 0x080025FC
+
.L98:
+  0x08002594:  68A0         LDR        R0, [R4, #8]
+  0x08002596:  4991         LDR        R1, =0x7FFFFFE8          ; [PC, #0x0244] [0x080027DC] 
+  0x08002598:  4008         ANDS       R0, R1
+  0x0800259A:  9923         LDR        R1, [SP, #140]
+  0x0800259C:  4308         ORRS       R0, R1
+  0x0800259E:  60A0         STR        R0, [R4, #8]
+  0x080025A0:  4893         LDR        R0, =0x40012708          ; [PC, #0x024C] [0x080027F0] 
+  0x080025A2:  6800         LDR        R0, [R0]
+  0x080025A4:  0200         LSLS       R0, R0, #8
+  0x080025A6:  D501         BPL        .L99                     ; 0x080025AC
+  0x080025A8:  F001 FED7    BL         .L277                    ; 0x0800435A
+
.L99:
+  0x080025AC:  7E70         LDRB       R0, [R6, #25]
+  0x080025AE:  2801         CMP        R0, #1
+  0x080025B0:  D001         BEQ        .L100                    ; 0x080025B6
+  0x080025B2:  F001 FEE2    BL         .L280                    ; 0x0800437A
+
.L100:
+  0x080025B6:  9B03         LDR        R3, [SP, #12]
+  0x080025B8:  54B3         STRB       R3, [R6, R2]
+  0x080025BA:  6DB0         LDR        R0, [R6, #88]
+  0x080025BC:  498D         LDR        R1, =0xFFFFF0FE          ; [PC, #0x0234] [0x080027F4] 
+  0x080025BE:  4008         ANDS       R0, R1
+  0x080025C0:  9910         LDR        R1, [SP, #64]
+  0x080025C2:  4308         ORRS       R0, R1
+  0x080025C4:  65B0         STR        R0, [R6, #88]
+  0x080025C6:  65F3         STR        R3, [R6, #92]
+  0x080025C8:  9804         LDR        R0, [SP, #16]
+  0x080025CA:  6020         STR        R0, [R4]
+  0x080025CC:  6D30         LDR        R0, [R6, #80]
+  0x080025CE:  498A         LDR        R1, =ADC_DMAError        ; [PC, #0x0228] [0x080027F8] =0x08005D5B 
+  0x080025D0:  4A8A         LDR        R2, =ADC_DMAHalfConvCplt ; [PC, #0x0228] [0x080027FC] =0x08005775 
+  0x080025D2:  4B8B         LDR        R3, =ADC_DMAConvCplt     ; [PC, #0x022C] [0x08002800] =0x08005CF7 
+  0x080025D4:  62C3         STR        R3, [R0, #44]
+  0x080025D6:  6302         STR        R2, [R0, #48]
+  0x080025D8:  6341         STR        R1, [R0, #52]
+  0x080025DA:  6861         LDR        R1, [R4, #4]
+  0x080025DC:  9A19         LDR        R2, [SP, #100]
+  0x080025DE:  4311         ORRS       R1, R2
+  0x080025E0:  6061         STR        R1, [R4, #4]
+  0x080025E2:  3440         ADDS       R4, #64
+  0x080025E4:  4A87         LDR        R2, =adcData             ; [PC, #0x021C] [0x08002804] =0x20000660 
+  0x080025E6:  2305         MOVS       R3, #5
+  0x080025E8:  4621         MOV        R1, R4
+  0x080025EA:  F7FE FA1B    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080025EE:  6830         LDR        R0, [R6]
+  0x080025F0:  6881         LDR        R1, [R0, #8]
+  0x080025F2:  4A7A         LDR        R2, =0x7FFFFFE8          ; [PC, #0x01E8] [0x080027DC] 
+  0x080025F4:  4011         ANDS       R1, R2
+  0x080025F6:  9A0E         LDR        R2, [SP, #56]
+  0x080025F8:  4311         ORRS       R1, R2
+  0x080025FA:  6081         STR        R1, [R0, #8]
+
.L101:
+  0x080025FC:  4B82         LDR        R3, =htim16              ; [PC, #0x0208] [0x08002808] =0x20000614 
+  0x080025FE:  6818         LDR        R0, [R3]
+  0x08002600:  2200         MOVS       R2, #0
+  0x08002602:  6242         STR        R2, [R0, #36]
+  0x08002604:  4981         LDR        R1, =ic_overflows        ; [PC, #0x0204] [0x0800280C] =0x200006DC 
+  0x08002606:  9223         STR        R2, [SP, #140]
+  0x08002608:  600A         STR        R2, [R1]
+  0x0800260A:  9C05         LDR        R4, [SP, #20]
+  0x0800260C:  5D19         LDRB       R1, [R3, R4]
+  0x0800260E:  2901         CMP        R1, #1
+  0x08002610:  D117         BNE        .L104                    ; 0x08002642
+  0x08002612:  2102         MOVS       R1, #2
+  0x08002614:  5519         STRB       R1, [R3, R4]
+  0x08002616:  68C2         LDR        R2, [R0, #12]
+  0x08002618:  2101         MOVS       R1, #1
+  0x0800261A:  430A         ORRS       R2, R1
+  0x0800261C:  60C2         STR        R2, [R0, #12]
+  0x0800261E:  4A7C         LDR        R2, =0x40012C00          ; [PC, #0x01F0] [0x08002810] 
+  0x08002620:  4290         CMP        R0, R2
+  0x08002622:  D002         BEQ        .L102                    ; 0x0800262A
+  0x08002624:  4A7B         LDR        R2, =0x40000400          ; [PC, #0x01EC] [0x08002814] 
+  0x08002626:  4290         CMP        R0, R2
+  0x08002628:  D108         BNE        .L103                    ; 0x0800263C
+
.L102:
+  0x0800262A:  4B7B         LDR        R3, =0x0000FFFF          ; [PC, #0x01EC] [0x08002818] 
+  0x0800262C:  3308         ADDS       R3, #8
+  0x0800262E:  6882         LDR        R2, [R0, #8]
+  0x08002630:  401A         ANDS       R2, R3
+  0x08002632:  2A06         CMP        R2, #6
+  0x08002634:  D005         BEQ        .L104                    ; 0x08002642
+  0x08002636:  040B         LSLS       R3, R1, #16
+  0x08002638:  429A         CMP        R2, R3
+  0x0800263A:  D002         BEQ        .L104                    ; 0x08002642
+
.L103:
+  0x0800263C:  6802         LDR        R2, [R0]
+  0x0800263E:  430A         ORRS       R2, R1
+  0x08002640:  6002         STR        R2, [R0]
+
.L104:
+  0x08002642:  4A71         LDR        R2, =htim16              ; [PC, #0x01C4] [0x08002808] =0x20000614 
+  0x08002644:  9B1B         LDR        R3, [SP, #108]
+  0x08002646:  5CD1         LDRB       R1, [R2, R3]
+  0x08002648:  2901         CMP        R1, #1
+  0x0800264A:  9911         LDR        R1, [SP, #68]
+  0x0800264C:  5C51         LDRB       R1, [R2, R1]
+  0x0800264E:  D121         BNE        .L107                    ; 0x08002694
+  0x08002650:  2901         CMP        R1, #1
+  0x08002652:  D11F         BNE        .L107                    ; 0x08002694
+  0x08002654:  2102         MOVS       R1, #2
+  0x08002656:  54D1         STRB       R1, [R2, R3]
+  0x08002658:  9B11         LDR        R3, [SP, #68]
+  0x0800265A:  54D1         STRB       R1, [R2, R3]
+  0x0800265C:  68C2         LDR        R2, [R0, #12]
+  0x0800265E:  430A         ORRS       R2, R1
+  0x08002660:  60C2         STR        R2, [R0, #12]
+  0x08002662:  6A02         LDR        R2, [R0, #32]
+  0x08002664:  2101         MOVS       R1, #1
+  0x08002666:  438A         BICS       R2, R1
+  0x08002668:  6202         STR        R2, [R0, #32]
+  0x0800266A:  6A02         LDR        R2, [R0, #32]
+  0x0800266C:  430A         ORRS       R2, R1
+  0x0800266E:  6202         STR        R2, [R0, #32]
+  0x08002670:  4A67         LDR        R2, =0x40012C00          ; [PC, #0x019C] [0x08002810] 
+  0x08002672:  4290         CMP        R0, R2
+  0x08002674:  D002         BEQ        .L105                    ; 0x0800267C
+  0x08002676:  4A67         LDR        R2, =0x40000400          ; [PC, #0x019C] [0x08002814] 
+  0x08002678:  4290         CMP        R0, R2
+  0x0800267A:  D108         BNE        .L106                    ; 0x0800268E
+
.L105:
+  0x0800267C:  4B66         LDR        R3, =0x0000FFFF          ; [PC, #0x0198] [0x08002818] 
+  0x0800267E:  3308         ADDS       R3, #8
+  0x08002680:  6882         LDR        R2, [R0, #8]
+  0x08002682:  401A         ANDS       R2, R3
+  0x08002684:  2A06         CMP        R2, #6
+  0x08002686:  D005         BEQ        .L107                    ; 0x08002694
+  0x08002688:  040B         LSLS       R3, R1, #16
+  0x0800268A:  429A         CMP        R2, R3
+  0x0800268C:  D002         BEQ        .L107                    ; 0x08002694
+
.L106:
+  0x0800268E:  6802         LDR        R2, [R0]
+  0x08002690:  430A         ORRS       R2, R1
+  0x08002692:  6002         STR        R2, [R0]
+
.L107:
+  0x08002694:  9517         STR        R5, [SP, #92]
+
.L108:
+  0x08002696:  4861         LDR        R0, =0x40003000          ; [PC, #0x0184] [0x0800281C] 
+  0x08002698:  4961         LDR        R1, =0x0000AAAA          ; [PC, #0x0184] [0x08002820] 
+  0x0800269A:  6001         STR        R1, [R0]
+  0x0800269C:  7D38         LDRB       R0, [R7, #20]
+  0x0800269E:  2801         CMP        R0, #1
+  0x080026A0:  D10F         BNE        .L110                    ; 0x080026C2
+  0x080026A2:  9818         LDR        R0, [SP, #96]
+  0x080026A4:  00C0         LSLS       R0, R0, #3
+  0x080026A6:  463E         MOV        R6, R7
+  0x080026A8:  9021         STR        R0, [SP, #132]
+  0x080026AA:  583F         LDR        R7, [R7, R0]
+  0x080026AC:  2F05         CMP        R7, #5
+  0x080026AE:  D223         BCS        .L113                    ; 0x080026F8
+
.L109:
+  0x080026B0:  2000         MOVS       R0, #0
+  0x080026B2:  9921         LDR        R1, [SP, #132]
+  0x080026B4:  5070         STR        R0, [R6, R1]
+  0x080026B6:  7530         STRB       R0, [R6, #20]
+  0x080026B8:  208C         MOVS       R0, #140
+  0x080026BA:  2122         MOVS       R1, #34
+  0x080026BC:  4A59         LDR        R2, =huart1              ; [PC, #0x0164] [0x08002824] =0x200003BC 
+  0x080026BE:  5011         STR        R1, [R2, R0]
+  0x080026C0:  4637         MOV        R7, R6
+
.L110:
+  0x080026C2:  4847         LDR        R0, =uwTick              ; [PC, #0x011C] [0x080027E0] =0x2000068C 
+  0x080026C4:  6800         LDR        R0, [R0]
+  0x080026C6:  4958         LDR        R1, =oldTimeMSTick       ; [PC, #0x0160] [0x08002828] =0x200006AC 
+  0x080026C8:  6809         LDR        R1, [R1]
+  0x080026CA:  4281         CMP        R1, R0
+  0x080026CC:  D102         BNE        .L111                    ; 0x080026D4
+  0x080026CE:  4857         LDR        R0, =msCounter           ; [PC, #0x015C] [0x0800282C] =0x200006C0 
+  0x080026D0:  6800         LDR        R0, [R0]
+  0x080026D2:  E1B2         B          .L151                    ; 0x08002A3A
+
.L111:
+  0x080026D4:  4837         LDR        R0, =0x50000410          ; [PC, #220] [0x080027B4] 
+  0x080026D6:  6800         LDR        R0, [R0]
+  0x080026D8:  07C0         LSLS       R0, R0, #31
+  0x080026DA:  4C55         LDR        R4, =longPressCounterButtonOn ; [PC, #0x0154] [0x08002830] =0x200006C4 
+  0x080026DC:  6820         LDR        R0, [R4]
+  0x080026DE:  D001         BEQ        .L112                    ; 0x080026E4
+  0x080026E0:  1C40         ADDS       R0, R0, #1
+  0x080026E2:  6020         STR        R0, [R4]
+
.L112:
+  0x080026E4:  4953         LDR        R1, =0x00001388          ; [PC, #0x014C] [0x08002834] 
+  0x080026E6:  4288         CMP        R0, R1
+  0x080026E8:  D947         BLS        .L120                    ; 0x0800277A
+  0x080026EA:  4853         LDR        R0, =buttonState         ; [PC, #0x014C] [0x08002838] =0x2000073A 
+  0x080026EC:  7800         LDRB       R0, [R0]
+  0x080026EE:  2802         CMP        R0, #2
+  0x080026F0:  D053         BEQ        .L122                    ; 0x0800279A
+  0x080026F2:  4852         LDR        R0, =0x080067DC          ; [PC, #0x0148] [0x0800283C] 
+  0x080026F4:  9E0F         LDR        R6, [SP, #60]
+  0x080026F6:  E04C         B          .L121                    ; 0x08002792
+
.L113:
+  0x080026F8:  2027         MOVS       R0, #39
+  0x080026FA:  5C30         LDRB       R0, [R6, R0]
+  0x080026FC:  901B         STR        R0, [SP, #108]
+  0x080026FE:  1EBC         SUBS       R4, R7, #2
+  0x08002700:  9816         LDR        R0, [SP, #88]
+  0x08002702:  4621         MOV        R1, R4
+  0x08002704:  F001 FF5A    BL         mbCrc16                  ; 0x080045BC
+  0x08002708:  1C79         ADDS       R1, R7, #1
+  0x0800270A:  D0D1         BEQ        .L109                    ; 0x080026B0
+  0x0800270C:  9916         LDR        R1, [SP, #88]
+  0x0800270E:  5D09         LDRB       R1, [R1, R4]
+  0x08002710:  19F2         ADDS       R2, R6, R7
+  0x08002712:  9B22         LDR        R3, [SP, #136]
+  0x08002714:  5CD2         LDRB       R2, [R2, R3]
+  0x08002716:  0212         LSLS       R2, R2, #8
+  0x08002718:  1851         ADDS       R1, R2, R1
+  0x0800271A:  4281         CMP        R1, R0
+  0x0800271C:  D1C8         BNE        .L109                    ; 0x080026B0
+  0x0800271E:  981B         LDR        R0, [SP, #108]
+  0x08002720:  2800         CMP        R0, #0
+  0x08002722:  D004         BEQ        .L114                    ; 0x0800272E
+  0x08002724:  4828         LDR        R0, =sys_data            ; [PC, #160] [0x080027C8] =0x20000234 
+  0x08002726:  8B00         LDRH       R0, [R0, #24]
+  0x08002728:  991B         LDR        R1, [SP, #108]
+  0x0800272A:  4288         CMP        R0, R1
+  0x0800272C:  D1C0         BNE        .L109                    ; 0x080026B0
+
.L114:
+  0x0800272E:  9812         LDR        R0, [SP, #72]
+  0x08002730:  3028         ADDS       R0, #40
+  0x08002732:  9B1B         LDR        R3, [SP, #108]
+  0x08002734:  5433         STRB       R3, [R6, R0]
+  0x08002736:  218B         MOVS       R1, #139
+  0x08002738:  008A         LSLS       R2, R1, #2
+  0x0800273A:  9211         STR        R2, [SP, #68]
+  0x0800273C:  2100         MOVS       R1, #0
+  0x0800273E:  50B1         STR        R1, [R6, R2]
+  0x08002740:  2228         MOVS       R2, #40
+  0x08002742:  5CB2         LDRB       R2, [R6, R2]
+  0x08002744:  2A10         CMP        R2, #16
+  0x08002746:  D101         BNE        .L115                    ; 0x0800274C
+  0x08002748:  F001 F9F8    BL         .L216                    ; 0x08003B3C
+
.L115:
+  0x0800274C:  2A06         CMP        R2, #6
+  0x0800274E:  D101         BNE        .L116                    ; 0x08002754
+  0x08002750:  F001 F9E9    BL         .L215                    ; 0x08003B26
+
.L116:
+  0x08002754:  2A03         CMP        R2, #3
+  0x08002756:  4F25         LDR        R7, =modbusData          ; [PC, #148] [0x080027EC] =0x20000000 
+  0x08002758:  D001         BEQ        .L117                    ; 0x0800275E
+  0x0800275A:  F001 F9FA    BL         .L218                    ; 0x08003B52
+
.L117:
+  0x0800275E:  4A1A         LDR        R2, =sys_data            ; [PC, #104] [0x080027C8] =0x20000234 
+  0x08002760:  8B12         LDRH       R2, [R2, #24]
+  0x08002762:  2B00         CMP        R3, #0
+  0x08002764:  D101         BNE        .L118                    ; 0x0800276A
+  0x08002766:  F001 FA1E    BL         .L224                    ; 0x08003BA6
+
.L118:
+  0x0800276A:  429A         CMP        R2, R3
+  0x0800276C:  D101         BNE        .L119                    ; 0x08002772
+  0x0800276E:  F001 FA1A    BL         .L224                    ; 0x08003BA6
+
.L119:
+  0x08002772:  2386         MOVS       R3, #134
+  0x08002774:  9A1D         LDR        R2, [SP, #116]
+  0x08002776:  F001 FA34    BL         .L226                    ; 0x08003BE2
+
.L120:
+  0x0800277A:  280B         CMP        R0, #11
+  0x0800277C:  D30D         BCC        .L122                    ; 0x0800279A
+  0x0800277E:  482E         LDR        R0, =buttonState         ; [PC, #184] [0x08002838] =0x2000073A 
+  0x08002780:  7800         LDRB       R0, [R0]
+  0x08002782:  490C         LDR        R1, =0x50000410          ; [PC, #48] [0x080027B4] 
+  0x08002784:  6809         LDR        R1, [R1]
+  0x08002786:  07C9         LSLS       R1, R1, #31
+  0x08002788:  D107         BNE        .L122                    ; 0x0800279A
+  0x0800278A:  2801         CMP        R0, #1
+  0x0800278C:  D005         BEQ        .L122                    ; 0x0800279A
+  0x0800278E:  2601         MOVS       R6, #1
+  0x08002790:  48F0         LDR        R0, =0x0800634F          ; [PC, #0x03C0] [0x08002B54] 
+
.L121:
+  0x08002792:  F002 FCE1    BL         puts                     ; 0x08005158
+  0x08002796:  4828         LDR        R0, =buttonState         ; [PC, #160] [0x08002838] =0x2000073A 
+  0x08002798:  7006         STRB       R6, [R0]
+
.L122:
+  0x0800279A:  4806         LDR        R0, =0x50000410          ; [PC, #24] [0x080027B4] 
+  0x0800279C:  6800         LDR        R0, [R0]
+  0x0800279E:  07C0         LSLS       R0, R0, #31
+  0x080027A0:  D100         BNE        .L123                    ; 0x080027A4
+  0x080027A2:  6020         STR        R0, [R4]
+
.L123:
+  0x080027A4:  4803         LDR        R0, =0x50000410          ; [PC, #12] [0x080027B4] 
+  0x080027A6:  6800         LDR        R0, [R0]
+  0x080027A8:  0780         LSLS       R0, R0, #30
+  0x080027AA:  48EB         LDR        R0, =longPressCounterButtonOff ; [PC, #0x03AC] [0x08002B58] =0x200006C8 
+  0x080027AC:  D448         BMI        .L124                    ; 0x08002840
+  0x080027AE:  2100         MOVS       R1, #0
+  0x080027B0:  6001         STR        R1, [R0]
+  0x080027B2:  E053         B          .L125                    ; 0x0800285C
+  0x080027B4:  50000410     DC.W       0x50000410
+  0x080027B8:  50000818     DC.W       0x50000818
+  0x080027BC:  50000010     DC.W       0x50000010
+  0x080027C0:  20000739     DC.W       mode
+  0x080027C4:  08006736     DC.W       08006736               ; R_ARM_ABS32
+  0x080027C8:  20000234     DC.W       sys_data
+  0x080027CC:  1FFF7568     DC.W       0x1FFF7568
+  0x080027D0:  453B8000     DC.W       0x453B8000
+  0x080027D4:  200006E8     DC.W       calTemperatureSensor30Value
+  0x080027D8:  20000450     DC.W       hadc1
+  0x080027DC:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x080027E0:  2000068C     DC.W       uwTick
+  0x080027E4:  FFFFFEFD     DC.W       0xFFFFFEFD
+  0x080027E8:  FFFF7FFC     DC.W       0xFFFF7FFC
+  0x080027EC:  20000000     DC.W       modbusData
+  0x080027F0:  40012708     DC.W       0x40012708
+  0x080027F4:  FFFFF0FE     DC.W       0xFFFFF0FE
+  0x080027F8:  08005D5B     DC.W       ADC_DMAError
+  0x080027FC:  08005775     DC.W       ADC_DMAHalfConvCplt
+  0x08002800:  08005CF7     DC.W       ADC_DMAConvCplt
+  0x08002804:  20000660     DC.W       adcData
+  0x08002808:  20000614     DC.W       htim16
+  0x0800280C:  200006DC     DC.W       ic_overflows
+  0x08002810:  40012C00     DC.W       0x40012C00
+  0x08002814:  40000400     DC.W       0x40000400
+  0x08002818:  0000FFFF     DC.W       0x0000FFFF
+  0x0800281C:  40003000     DC.W       0x40003000
+  0x08002820:  0000AAAA     DC.W       0x0000AAAA
+  0x08002824:  200003BC     DC.W       huart1
+  0x08002828:  200006AC     DC.W       oldTimeMSTick
+  0x0800282C:  200006C0     DC.W       msCounter
+  0x08002830:  200006C4     DC.W       longPressCounterButtonOn
+  0x08002834:  00001388     DC.W       0x00001388
+  0x08002838:  2000073A     DC.W       buttonState
+  0x0800283C:  080067DC     DC.W       080067DC               ; R_ARM_ABS32
+
.L124:
+  0x08002840:  6801         LDR        R1, [R0]
+  0x08002842:  1C49         ADDS       R1, R1, #1
+  0x08002844:  6001         STR        R1, [R0]
+  0x08002846:  290B         CMP        R1, #11
+  0x08002848:  D308         BCC        .L125                    ; 0x0800285C
+  0x0800284A:  4CE3         LDR        R4, =buttonState         ; [PC, #0x038C] [0x08002BD8] =0x2000073A 
+  0x0800284C:  7820         LDRB       R0, [R4]
+  0x0800284E:  2800         CMP        R0, #0
+  0x08002850:  D004         BEQ        .L125                    ; 0x0800285C
+  0x08002852:  48E2         LDR        R0, =0x08006511          ; [PC, #0x0388] [0x08002BDC] 
+  0x08002854:  F002 FC80    BL         puts                     ; 0x08005158
+  0x08002858:  2000         MOVS       R0, #0
+  0x0800285A:  7020         STRB       R0, [R4]
+
.L125:
+  0x0800285C:  48E0         LDR        R0, =onTimeCounter       ; [PC, #0x0380] [0x08002BE0] =0x200006A8 
+  0x0800285E:  6801         LDR        R1, [R0]
+  0x08002860:  2900         CMP        R1, #0
+  0x08002862:  D012         BEQ        .L127                    ; 0x0800288A
+  0x08002864:  1E49         SUBS       R1, R1, #1
+  0x08002866:  6001         STR        R1, [R0]
+  0x08002868:  D10F         BNE        .L127                    ; 0x0800288A
+  0x0800286A:  49DE         LDR        R1, =0x50000410          ; [PC, #0x0378] [0x08002BE4] 
+  0x0800286C:  9A20         LDR        R2, [SP, #128]
+  0x0800286E:  618A         STR        R2, [R1, #24]
+  0x08002870:  49DD         LDR        R1, =alarmMode           ; [PC, #0x0374] [0x08002BE8] =0x2000075C 
+  0x08002872:  7809         LDRB       R1, [R1]
+  0x08002874:  2901         CMP        R1, #1
+  0x08002876:  D108         BNE        .L127                    ; 0x0800288A
+  0x08002878:  49DC         LDR        R1, =offTime             ; [PC, #0x0370] [0x08002BEC] =0x20000750 
+  0x0800287A:  780A         LDRB       R2, [R1]
+  0x0800287C:  2A00         CMP        R2, #0
+  0x0800287E:  49F5         LDR        R1, =0x00001388          ; [PC, #0x03D4] [0x08002C54] 
+  0x08002880:  D100         BNE        .L126                    ; 0x08002884
+  0x08002882:  2100         MOVS       R1, #0
+
.L126:
+  0x08002884:  4AF4         LDR        R2, =offTimeCounter      ; [PC, #0x03D0] [0x08002C58] =0x200006B8 
+  0x08002886:  6011         STR        R1, [R2]
+  0x08002888:  E001         B          .L128                    ; 0x0800288E
+
.L127:
+  0x0800288A:  49F3         LDR        R1, =offTimeCounter      ; [PC, #0x03CC] [0x08002C58] =0x200006B8 
+  0x0800288C:  6809         LDR        R1, [R1]
+
.L128:
+  0x0800288E:  2900         CMP        R1, #0
+  0x08002890:  D00C         BEQ        .L130                    ; 0x080028AC
+  0x08002892:  1E49         SUBS       R1, R1, #1
+  0x08002894:  4AF0         LDR        R2, =offTimeCounter      ; [PC, #0x03C0] [0x08002C58] =0x200006B8 
+  0x08002896:  6011         STR        R1, [R2]
+  0x08002898:  D108         BNE        .L130                    ; 0x080028AC
+  0x0800289A:  49F2         LDR        R1, =0x50000410          ; [PC, #0x03C8] [0x08002C64] 
+  0x0800289C:  9A20         LDR        R2, [SP, #128]
+  0x0800289E:  608A         STR        R2, [R1, #8]
+  0x080028A0:  49F2         LDR        R1, =onTime              ; [PC, #0x03C8] [0x08002C6C] =0x20000744 
+  0x080028A2:  7809         LDRB       R1, [R1]
+  0x080028A4:  2900         CMP        R1, #0
+  0x080028A6:  D000         BEQ        .L129                    ; 0x080028AA
+  0x080028A8:  21C8         MOVS       R1, #200
+
.L129:
+  0x080028AA:  6001         STR        R1, [R0]
+
.L130:
+  0x080028AC:  4CF0         LDR        R4, =adcData             ; [PC, #0x03C0] [0x08002C70] =0x20000660 
+  0x080028AE:  6820         LDR        R0, [R4]
+  0x080028B0:  49F0         LDR        R1, =0x00000CE4          ; [PC, #0x03C0] [0x08002C74] 
+  0x080028B2:  4348         MULS       R0, R1, R0
+  0x080028B4:  49F0         LDR        R1, =0x00010063          ; [PC, #0x03C0] [0x08002C78] 
+  0x080028B6:  F003 FB78    BL         __aeabi_idiv             ; 0x08005FAA
+  0x080028BA:  49F0         LDR        R1, =0xFFFFFCFF          ; [PC, #0x03C0] [0x08002C7C] 
+  0x080028BC:  1808         ADDS       R0, R1, R0
+  0x080028BE:  30A9         ADDS       R0, #169
+  0x080028C0:  210A         MOVS       R1, #10
+  0x080028C2:  F003 FB72    BL         __aeabi_idiv             ; 0x08005FAA
+  0x080028C6:  49EE         LDR        R1, =relais_temperature  ; [PC, #0x03B8] [0x08002C80] =0x20000694 
+  0x080028C8:  6008         STR        R0, [R1]
+  0x080028CA:  48EE         LDR        R0, =onTimeCounterSET    ; [PC, #0x03B8] [0x08002C84] =0x20000698 
+  0x080028CC:  6801         LDR        R1, [R0]
+  0x080028CE:  2900         CMP        R1, #0
+  0x080028D0:  D005         BEQ        .L131                    ; 0x080028DE
+  0x080028D2:  1E49         SUBS       R1, R1, #1
+  0x080028D4:  6001         STR        R1, [R0]
+  0x080028D6:  D102         BNE        .L131                    ; 0x080028DE
+  0x080028D8:  48E2         LDR        R0, =0x50000410          ; [PC, #0x0388] [0x08002C64] 
+  0x080028DA:  991A         LDR        R1, [SP, #104]
+  0x080028DC:  6181         STR        R1, [R0, #24]
+
.L131:
+  0x080028DE:  48EA         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03A8] [0x08002C88] =0x200006A0 
+  0x080028E0:  6801         LDR        R1, [R0]
+  0x080028E2:  2900         CMP        R1, #0
+  0x080028E4:  D005         BEQ        .L132                    ; 0x080028F2
+  0x080028E6:  1E49         SUBS       R1, R1, #1
+  0x080028E8:  6001         STR        R1, [R0]
+  0x080028EA:  D102         BNE        .L132                    ; 0x080028F2
+  0x080028EC:  48DD         LDR        R0, =0x50000410          ; [PC, #0x0374] [0x08002C64] 
+  0x080028EE:  9919         LDR        R1, [SP, #100]
+  0x080028F0:  6181         STR        R1, [R0, #24]
+
.L132:
+  0x080028F2:  48E6         LDR        R0, =onTimeCounterGN     ; [PC, #0x0398] [0x08002C8C] =0x200006A4 
+  0x080028F4:  6801         LDR        R1, [R0]
+  0x080028F6:  2900         CMP        R1, #0
+  0x080028F8:  D012         BEQ        .L134                    ; 0x08002920
+  0x080028FA:  1E49         SUBS       R1, R1, #1
+  0x080028FC:  6001         STR        R1, [R0]
+  0x080028FE:  D10F         BNE        .L134                    ; 0x08002920
+  0x08002900:  49E3         LDR        R1, =0x50000818          ; [PC, #0x038C] [0x08002C90] 
+  0x08002902:  9A1F         LDR        R2, [SP, #124]
+  0x08002904:  610A         STR        R2, [R1, #16]
+  0x08002906:  49E3         LDR        R1, =blinkModeGN         ; [PC, #0x038C] [0x08002C94] =0x20000758 
+  0x08002908:  7809         LDRB       R1, [R1]
+  0x0800290A:  2901         CMP        R1, #1
+  0x0800290C:  D108         BNE        .L134                    ; 0x08002920
+  0x0800290E:  49E2         LDR        R1, =offTimeGN           ; [PC, #0x0388] [0x08002C98] =0x2000074C 
+  0x08002910:  780A         LDRB       R2, [R1]
+  0x08002912:  2A00         CMP        R2, #0
+  0x08002914:  990B         LDR        R1, [SP, #44]
+  0x08002916:  D100         BNE        .L133                    ; 0x0800291A
+  0x08002918:  2100         MOVS       R1, #0
+
.L133:
+  0x0800291A:  4AE0         LDR        R2, =offTimeCounterGN    ; [PC, #0x0380] [0x08002C9C] =0x200006B4 
+  0x0800291C:  6011         STR        R1, [R2]
+  0x0800291E:  E001         B          .L135                    ; 0x08002924
+
.L134:
+  0x08002920:  49DE         LDR        R1, =offTimeCounterGN    ; [PC, #0x0378] [0x08002C9C] =0x200006B4 
+  0x08002922:  6809         LDR        R1, [R1]
+
.L135:
+  0x08002924:  2900         CMP        R1, #0
+  0x08002926:  D00C         BEQ        .L137                    ; 0x08002942
+  0x08002928:  1E49         SUBS       R1, R1, #1
+  0x0800292A:  4AF3         LDR        R2, =offTimeCounterGN    ; [PC, #0x03CC] [0x08002CF8] =0x200006B4 
+  0x0800292C:  6011         STR        R1, [R2]
+  0x0800292E:  D108         BNE        .L137                    ; 0x08002942
+  0x08002930:  49D7         LDR        R1, =0x50000818          ; [PC, #0x035C] [0x08002C90] 
+  0x08002932:  9A1F         LDR        R2, [SP, #124]
+  0x08002934:  600A         STR        R2, [R1]
+  0x08002936:  49F1         LDR        R1, =onTimeGN            ; [PC, #0x03C4] [0x08002CFC] =0x20000740 
+  0x08002938:  7809         LDRB       R1, [R1]
+  0x0800293A:  2900         CMP        R1, #0
+  0x0800293C:  D000         BEQ        .L136                    ; 0x08002940
+  0x0800293E:  21C8         MOVS       R1, #200
+
.L136:
+  0x08002940:  6001         STR        R1, [R0]
+
.L137:
+  0x08002942:  48EF         LDR        R0, =onTimeCounterRT     ; [PC, #0x03BC] [0x08002D00] =0x2000069C 
+  0x08002944:  6801         LDR        R1, [R0]
+  0x08002946:  2900         CMP        R1, #0
+  0x08002948:  D002         BEQ        .L138                    ; 0x08002950
+  0x0800294A:  1E49         SUBS       R1, R1, #1
+  0x0800294C:  6001         STR        R1, [R0]
+  0x0800294E:  D006         BEQ        .L140                    ; 0x0800295E
+
.L138:
+  0x08002950:  49F0         LDR        R1, =blinkCounter        ; [PC, #0x03C0] [0x08002D14] =0x200006EC 
+  0x08002952:  6809         LDR        R1, [R1]
+
.L139:
+  0x08002954:  2900         CMP        R1, #0
+  0x08002956:  D018         BEQ        .L143                    ; 0x0800298A
+  0x08002958:  49EF         LDR        R1, =offTimeCounterRT    ; [PC, #0x03BC] [0x08002D18] =0x200006B0 
+  0x0800295A:  6809         LDR        R1, [R1]
+  0x0800295C:  E021         B          .L145                    ; 0x080029A2
+
.L140:
+  0x0800295E:  49EB         LDR        R1, =0x50000818          ; [PC, #0x03AC] [0x08002D0C] 
+  0x08002960:  9A1E         LDR        R2, [SP, #120]
+  0x08002962:  610A         STR        R2, [R1, #16]
+  0x08002964:  49ED         LDR        R1, =blinkModeRT         ; [PC, #0x03B4] [0x08002D1C] =0x20000754 
+  0x08002966:  7809         LDRB       R1, [R1]
+  0x08002968:  2901         CMP        R1, #1
+  0x0800296A:  D107         BNE        .L142                    ; 0x0800297C
+  0x0800296C:  49EC         LDR        R1, =offTimeRT           ; [PC, #0x03B0] [0x08002D20] =0x20000748 
+  0x0800296E:  7809         LDRB       R1, [R1]
+  0x08002970:  2900         CMP        R1, #0
+  0x08002972:  D001         BEQ        .L141                    ; 0x08002978
+  0x08002974:  49EB         LDR        R1, =0x000003C7          ; [PC, #0x03AC] [0x08002D24] 
+  0x08002976:  3121         ADDS       R1, #33
+
.L141:
+  0x08002978:  4AE7         LDR        R2, =offTimeCounterRT    ; [PC, #0x039C] [0x08002D18] =0x200006B0 
+  0x0800297A:  6011         STR        R1, [R2]
+
.L142:
+  0x0800297C:  4AE5         LDR        R2, =blinkCounter        ; [PC, #0x0394] [0x08002D14] =0x200006EC 
+  0x0800297E:  6811         LDR        R1, [R2]
+  0x08002980:  2900         CMP        R1, #0
+  0x08002982:  D002         BEQ        .L143                    ; 0x0800298A
+  0x08002984:  1E49         SUBS       R1, R1, #1
+  0x08002986:  6011         STR        R1, [R2]
+  0x08002988:  E7E4         B          .L139                    ; 0x08002954
+
.L143:
+  0x0800298A:  49E7         LDR        R1, =numberOfBlinks      ; [PC, #0x039C] [0x08002D28] =0x200006BC 
+  0x0800298C:  6809         LDR        R1, [R1]
+  0x0800298E:  4AE1         LDR        R2, =blinkCounter        ; [PC, #0x0384] [0x08002D14] =0x200006EC 
+  0x08002990:  6011         STR        R1, [R2]
+  0x08002992:  49E6         LDR        R1, =pauseTime           ; [PC, #0x0398] [0x08002D2C] =0x20000734 
+  0x08002994:  780A         LDRB       R2, [R1]
+  0x08002996:  2A00         CMP        R2, #0
+  0x08002998:  49B3         LDR        R1, =0x00001388          ; [PC, #0x02CC] [0x08002C68] 
+  0x0800299A:  D100         BNE        .L144                    ; 0x0800299E
+  0x0800299C:  2100         MOVS       R1, #0
+
.L144:
+  0x0800299E:  4ADE         LDR        R2, =offTimeCounterRT    ; [PC, #0x0378] [0x08002D18] =0x200006B0 
+  0x080029A0:  6011         STR        R1, [R2]
+
.L145:
+  0x080029A2:  2900         CMP        R1, #0
+  0x080029A4:  D00C         BEQ        .L147                    ; 0x080029C0
+  0x080029A6:  1E49         SUBS       R1, R1, #1
+  0x080029A8:  4ADB         LDR        R2, =offTimeCounterRT    ; [PC, #0x036C] [0x08002D18] =0x200006B0 
+  0x080029AA:  6011         STR        R1, [R2]
+  0x080029AC:  D108         BNE        .L147                    ; 0x080029C0
+  0x080029AE:  49D7         LDR        R1, =0x50000818          ; [PC, #0x035C] [0x08002D0C] 
+  0x080029B0:  9A1E         LDR        R2, [SP, #120]
+  0x080029B2:  600A         STR        R2, [R1]
+  0x080029B4:  49DE         LDR        R1, =onTimeRT            ; [PC, #0x0378] [0x08002D30] =0x2000073C 
+  0x080029B6:  7809         LDRB       R1, [R1]
+  0x080029B8:  2900         CMP        R1, #0
+  0x080029BA:  D000         BEQ        .L146                    ; 0x080029BE
+  0x080029BC:  21C8         MOVS       R1, #200
+
.L146:
+  0x080029BE:  6001         STR        R1, [R0]
+
.L147:
+  0x080029C0:  6860         LDR        R0, [R4, #4]
+  0x080029C2:  4DAC         LDR        R5, =0x00000CE4          ; [PC, #0x02B0] [0x08002C74] 
+  0x080029C4:  4368         MULS       R0, R5, R0
+  0x080029C6:  4EAC         LDR        R6, =0x00010063          ; [PC, #0x02B0] [0x08002C78] 
+  0x080029C8:  4631         MOV        R1, R6
+  0x080029CA:  F003 FAEE    BL         __aeabi_idiv             ; 0x08005FAA
+  0x080029CE:  4621         MOV        R1, R4
+  0x080029D0:  4604         MOV        R4, R0
+  0x080029D2:  9F1D         LDR        R7, [SP, #116]
+  0x080029D4:  437C         MULS       R4, R7, R4
+  0x080029D6:  48D7         LDR        R0, =voltageUin          ; [PC, #0x035C] [0x08002D34] =0x20000688 
+  0x080029D8:  6004         STR        R4, [R0]
+  0x080029DA:  6888         LDR        R0, [R1, #8]
+  0x080029DC:  4368         MULS       R0, R5, R0
+  0x080029DE:  4631         MOV        R1, R6
+  0x080029E0:  F003 FAE3    BL         __aeabi_idiv             ; 0x08005FAA
+  0x080029E4:  4602         MOV        R2, R0
+  0x080029E6:  48D4         LDR        R0, =voltageUout         ; [PC, #0x0350] [0x08002D38] =0x20000684 
+  0x080029E8:  437A         MULS       R2, R7, R2
+  0x080029EA:  6002         STR        R2, [R0]
+  0x080029EC:  49D3         LDR        R1, =relaisState         ; [PC, #0x034C] [0x08002D3C] =0x20000730 
+  0x080029EE:  48D4         LDR        R0, =dropLimitCounter    ; [PC, #0x0350] [0x08002D40] =0x200006E4 
+  0x080029F0:  7809         LDRB       R1, [R1]
+  0x080029F2:  2901         CMP        R1, #1
+  0x080029F4:  6801         LDR        R1, [R0]
+  0x080029F6:  D112         BNE        .L149                    ; 0x08002A1E
+  0x080029F8:  1AA3         SUBS       R3, R4, R2
+  0x080029FA:  17DE         ASRS       R6, R3, #31
+  0x080029FC:  4073         EORS       R3, R6
+  0x080029FE:  1B9B         SUBS       R3, R3, R6
+  0x08002A00:  2B5B         CMP        R3, #91
+  0x08002A02:  D30C         BCC        .L149                    ; 0x08002A1E
+  0x08002A04:  4EC7         LDR        R6, =0x000003C7          ; [PC, #0x031C] [0x08002D24] 
+  0x08002A06:  3621         ADDS       R6, #33
+  0x08002A08:  42B1         CMP        R1, R6
+  0x08002A0A:  4FCE         LDR        R7, =modbusData          ; [PC, #0x0338] [0x08002D44] =0x20000000 
+  0x08002A0C:  9D17         LDR        R5, [SP, #92]
+  0x08002A0E:  D201         BCS        .L148                    ; 0x08002A14
+  0x08002A10:  1C49         ADDS       R1, R1, #1
+  0x08002A12:  6001         STR        R1, [R0]
+
.L148:
+  0x08002A14:  48CC         LDR        R0, =0x080062BF          ; [PC, #0x0330] [0x08002D48] 
+  0x08002A16:  4621         MOV        R1, R4
+  0x08002A18:  F002 FBF8    BL         printf                   ; 0x0800520C
+  0x08002A1C:  E005         B          .L150                    ; 0x08002A2A
+
.L149:
+  0x08002A1E:  2900         CMP        R1, #0
+  0x08002A20:  4FC8         LDR        R7, =modbusData          ; [PC, #0x0320] [0x08002D44] =0x20000000 
+  0x08002A22:  9D17         LDR        R5, [SP, #92]
+  0x08002A24:  D001         BEQ        .L150                    ; 0x08002A2A
+  0x08002A26:  1E49         SUBS       R1, R1, #1
+  0x08002A28:  6001         STR        R1, [R0]
+
.L150:
+  0x08002A2A:  48C8         LDR        R0, =uwTick              ; [PC, #0x0320] [0x08002D4C] =0x2000068C 
+  0x08002A2C:  6800         LDR        R0, [R0]
+  0x08002A2E:  49C8         LDR        R1, =oldTimeMSTick       ; [PC, #0x0320] [0x08002D50] =0x200006AC 
+  0x08002A30:  6008         STR        R0, [R1]
+  0x08002A32:  49C8         LDR        R1, =msCounter           ; [PC, #0x0320] [0x08002D54] =0x200006C0 
+  0x08002A34:  6808         LDR        R0, [R1]
+  0x08002A36:  1C40         ADDS       R0, R0, #1
+  0x08002A38:  6008         STR        R0, [R1]
+
.L151:
+  0x08002A3A:  49BA         LDR        R1, =0x000003C7          ; [PC, #0x02E8] [0x08002D24] 
+  0x08002A3C:  311F         ADDS       R1, #31
+  0x08002A3E:  4288         CMP        R0, R1
+  0x08002A40:  DD6F         BLE        .L156                    ; 0x08002B22
+  0x08002A42:  488B         LDR        R0, =adcData             ; [PC, #0x022C] [0x08002C70] =0x20000660 
+  0x08002A44:  6900         LDR        R0, [R0, #16]
+  0x08002A46:  498B         LDR        R1, =0x00000CE4          ; [PC, #0x022C] [0x08002C74] 
+  0x08002A48:  4348         MULS       R0, R1, R0
+  0x08002A4A:  0C00         LSRS       R0, R0, #16
+  0x08002A4C:  49C2         LDR        R1, =calTemperatureSensor30Value ; [PC, #0x0308] [0x08002D58] =0x200006E8 
+  0x08002A4E:  6809         LDR        R1, [R1]
+  0x08002A50:  1A40         SUBS       R0, R0, R1
+  0x08002A52:  F002 FB97    BL         __aeabi_i2d              ; 0x08005184
+  0x08002A56:  4AC1         LDR        R2, =0xA3D70A3D          ; [PC, #0x0304] [0x08002D5C] 
+  0x08002A58:  4BC1         LDR        R3, =0x40043D70          ; [PC, #0x0304] [0x08002D60] 
+  0x08002A5A:  F003 FA0A    BL         __aeabi_ddiv             ; 0x08005E72
+  0x08002A5E:  F003 FA6A    BL         __aeabi_d2iz             ; 0x08005F36
+  0x08002A62:  4604         MOV        R4, R0
+  0x08002A64:  3419         ADDS       R4, #25
+  0x08002A66:  22C8         MOVS       R2, #200
+  0x08002A68:  48BE         LDR        R0, =sys_data            ; [PC, #0x02F8] [0x08002D64] =0x20000234 
+  0x08002A6A:  5284         STRH       R4, [R0, R2]
+  0x08002A6C:  9823         LDR        R0, [SP, #140]
+  0x08002A6E:  1C40         ADDS       R0, R0, #1
+  0x08002A70:  2164         MOVS       R1, #100
+  0x08002A72:  2864         CMP        R0, #100
+  0x08002A74:  D300         BCC        .L152                    ; 0x08002A78
+  0x08002A76:  4608         MOV        R0, R1
+
.L152:
+  0x08002A78:  4BBA         LDR        R3, =sys_data            ; [PC, #0x02E8] [0x08002D64] =0x20000234 
+  0x08002A7A:  5E9B         LDRSH      R3, [R3, R2]
+  0x08002A7C:  2B32         CMP        R3, #50
+  0x08002A7E:  DC00         BGT        .L153                    ; 0x08002A82
+  0x08002A80:  9823         LDR        R0, [SP, #140]
+
.L153:
+  0x08002A82:  1E46         SUBS       R6, R0, #1
+  0x08002A84:  4603         MOV        R3, R0
+  0x08002A86:  41B3         SBCS       R3, R6
+  0x08002A88:  4EB6         LDR        R6, =sys_data            ; [PC, #0x02D8] [0x08002D64] =0x20000234 
+  0x08002A8A:  5EB2         LDRSH      R2, [R6, R2]
+  0x08002A8C:  2601         MOVS       R6, #1
+  0x08002A8E:  2700         MOVS       R7, #0
+  0x08002A90:  2A32         CMP        R2, #50
+  0x08002A92:  4632         MOV        R2, R6
+  0x08002A94:  DB00         BLT        .L154                    ; 0x08002A98
+  0x08002A96:  463A         MOV        R2, R7
+
.L154:
+  0x08002A98:  9721         STR        R7, [SP, #132]
+  0x08002A9A:  401A         ANDS       R2, R3
+  0x08002A9C:  1A82         SUBS       R2, R0, R2
+  0x08002A9E:  2A64         CMP        R2, #100
+  0x08002AA0:  9223         STR        R2, [SP, #140]
+  0x08002AA2:  D300         BCC        .L155                    ; 0x08002AA6
+  0x08002AA4:  460A         MOV        R2, R1
+
.L155:
+  0x08002AA6:  48B0         LDR        R0, =htim17              ; [PC, #0x02C0] [0x08002D68] =0x200005C8 
+  0x08002AA8:  6807         LDR        R7, [R0]
+  0x08002AAA:  6AF8         LDR        R0, [R7, #44]
+  0x08002AAC:  1C40         ADDS       R0, R0, #1
+  0x08002AAE:  4350         MULS       R0, R2, R0
+  0x08002AB0:  F003 FA9B    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08002AB4:  6378         STR        R0, [R7, #52]
+  0x08002AB6:  489F         LDR        R0, =voltageUin          ; [PC, #0x027C] [0x08002D34] =0x20000688 
+  0x08002AB8:  6800         LDR        R0, [R0]
+  0x08002ABA:  21CC         MOVS       R1, #204
+  0x08002ABC:  4BA9         LDR        R3, =sys_data            ; [PC, #0x02A4] [0x08002D64] =0x20000234 
+  0x08002ABE:  5258         STRH       R0, [R3, R1]
+  0x08002AC0:  489D         LDR        R0, =voltageUout         ; [PC, #0x0274] [0x08002D38] =0x20000684 
+  0x08002AC2:  6800         LDR        R0, [R0]
+  0x08002AC4:  22CE         MOVS       R2, #206
+  0x08002AC6:  5298         STRH       R0, [R3, R2]
+  0x08002AC8:  5A58         LDRH       R0, [R3, R1]
+  0x08002ACA:  5A99         LDRH       R1, [R3, R2]
+  0x08002ACC:  1A40         SUBS       R0, R0, R1
+  0x08002ACE:  21D0         MOVS       R1, #208
+  0x08002AD0:  5258         STRH       R0, [R3, R1]
+  0x08002AD2:  48A6         LDR        R0, =frequency           ; [PC, #0x0298] [0x08002D6C] =0x200006E0 
+  0x08002AD4:  8800         LDRH       R0, [R0]
+  0x08002AD6:  0840         LSRS       R0, R0, #1
+  0x08002AD8:  991C         LDR        R1, [SP, #112]
+  0x08002ADA:  4348         MULS       R0, R1, R0
+  0x08002ADC:  21D4         MOVS       R1, #212
+  0x08002ADE:  5258         STRH       R0, [R3, R1]
+  0x08002AE0:  20D2         MOVS       R0, #210
+  0x08002AE2:  9923         LDR        R1, [SP, #140]
+  0x08002AE4:  5219         STRH       R1, [R3, R0]
+  0x08002AE6:  489B         LDR        R0, =msCounter           ; [PC, #0x026C] [0x08002D54] =0x200006C0 
+  0x08002AE8:  9921         LDR        R1, [SP, #132]
+  0x08002AEA:  6001         STR        R1, [R0]
+  0x08002AEC:  48A0         LDR        R0, =temp                ; [PC, #0x0280] [0x08002D70] =0x20000690 
+  0x08002AEE:  6004         STR        R4, [R0]
+  0x08002AF0:  4AA0         LDR        R2, =0x50000010          ; [PC, #0x0280] [0x08002D74] 
+  0x08002AF2:  6810         LDR        R0, [R2]
+  0x08002AF4:  4030         ANDS       R0, R6
+  0x08002AF6:  21D8         MOVS       R1, #216
+  0x08002AF8:  5258         STRH       R0, [R3, R1]
+  0x08002AFA:  6810         LDR        R0, [R2]
+  0x08002AFC:  0780         LSLS       R0, R0, #30
+  0x08002AFE:  0FC0         LSRS       R0, R0, #31
+  0x08002B00:  21D6         MOVS       R1, #214
+  0x08002B02:  5258         STRH       R0, [R3, R1]
+  0x08002B04:  4857         LDR        R0, =0x50000410          ; [PC, #0x015C] [0x08002C64] 
+  0x08002B06:  6800         LDR        R0, [R0]
+  0x08002B08:  0880         LSRS       R0, R0, #2
+  0x08002B0A:  4386         BICS       R6, R0
+  0x08002B0C:  20DA         MOVS       R0, #218
+  0x08002B0E:  521E         STRH       R6, [R3, R0]
+  0x08002B10:  488A         LDR        R0, =relaisState         ; [PC, #0x0228] [0x08002D3C] =0x20000730 
+  0x08002B12:  7800         LDRB       R0, [R0]
+  0x08002B14:  21DC         MOVS       R1, #220
+  0x08002B16:  5258         STRH       R0, [R3, R1]
+  0x08002B18:  4859         LDR        R0, =relais_temperature  ; [PC, #0x0164] [0x08002C80] =0x20000694 
+  0x08002B1A:  6800         LDR        R0, [R0]
+  0x08002B1C:  21CA         MOVS       R1, #202
+  0x08002B1E:  5258         STRH       R0, [R3, R1]
+  0x08002B20:  4F88         LDR        R7, =modbusData          ; [PC, #0x0220] [0x08002D44] =0x20000000 
+
.L156:
+  0x08002B22:  4895         LDR        R0, =mode                ; [PC, #0x0254] [0x08002D78] =0x20000739 
+  0x08002B24:  7800         LDRB       R0, [R0]
+  0x08002B26:  2807         CMP        R0, #7
+  0x08002B28:  D900         BLS        .L157                    ; 0x08002B2C
+  0x08002B2A:  E15D         B          .L166                    ; 0x08002DE8
+
.L157:
+  0x08002B2C:  4478         ADD        R0, PC
+  0x08002B2E:  7900         LDRB       R0, [R0, #4]
+  0x08002B30:  0040         LSLS       R0, R0, #1
+  0x08002B32:  4487         ADD        PC, R0
+  0x08002B34:  03           DC.B       0x03                     ; '\x03'
+  0x08002B35:  80           DC.B       0x80                     ; '\x80'
+  0x08002B36:  3C           DC.B       0x3C                     ; '<'
+  0x08002B37:  41           DC.B       0x41                     ; 'A'
+  0x08002B38:  37           DC.B       0x37                     ; '7'
+  0x08002B39:  85           DC.B       0x85                     ; '\x85'
+  0x08002B3A:  D9           DC.B       0xD9                     ; '\xD9'
+  0x08002B3B:  46           DC.B       0x46                     ; 'F'
+  0x08002B3C:  4C8F         LDR        R4, =smState.137         ; [PC, #0x023C] [0x08002D7C] =0x20000735 
+  0x08002B3E:  7820         LDRB       R0, [R4]
+  0x08002B40:  0040         LSLS       R0, R0, #1
+  0x08002B42:  46C0         NOP
+  0x08002B44:  4478         ADD        R0, PC
+  0x08002B46:  8880         LDRH       R0, [R0, #4]
+  0x08002B48:  0040         LSLS       R0, R0, #1
+  0x08002B4A:  4487         ADD        PC, R0
+  0x08002B4C:  07           DC.B       0x07                     ; '\x07'
+  0x08002B4D:  00           DC.B       0x00                     ; '\0'
+  0x08002B4E:  A4           DC.B       0xA4                     ; '\xA4'
+  0x08002B4F:  03           DC.B       0x03                     ; '\x03'
+  0x08002B50:  7E           DC.B       0x7E                     ; '~'
+  0x08002B51:  01           DC.B       0x01                     ; '\x01'
+  0x08002B52:  C0           DC.B       0xC0                     ; '\xC0'
+  0x08002B53:  01           DC.B       0x01                     ; '\x01'
+  0x08002B54:  0800634F     DC.W       0800634F               ; R_ARM_ABS32
+  0x08002B58:  200006C8     DC.W       longPressCounterButtonOff
+  0x08002B5C:  4841         LDR        R0, =0x50000410          ; [PC, #0x0104] [0x08002C64] 
+  0x08002B5E:  6801         LDR        R1, [R0]
+  0x08002B60:  4A3B         LDR        R2, =buttonState         ; [PC, #236] [0x08002C50] =0x2000073A 
+  0x08002B62:  7810         LDRB       R0, [R2]
+  0x08002B64:  2801         CMP        R0, #1
+  0x08002B66:  D001         BEQ        .L158                    ; 0x08002B6C
+  0x08002B68:  F001 F970    BL         .L237                    ; 0x08003E4C
+
.L158:
+  0x08002B6C:  0748         LSLS       R0, R1, #29
+  0x08002B6E:  D501         BPL        .L159                    ; 0x08002B74
+  0x08002B70:  F001 F949    BL         .L235                    ; 0x08003E06
+
.L159:
+  0x08002B74:  483B         LDR        R0, =0x50000410          ; [PC, #236] [0x08002C64] 
+  0x08002B76:  9920         LDR        R1, [SP, #128]
+  0x08002B78:  6081         STR        R1, [R0, #8]
+  0x08002B7A:  2000         MOVS       R0, #0
+  0x08002B7C:  7010         STRB       R0, [R2]
+  0x08002B7E:  486C         LDR        R0, =onTimeRT            ; [PC, #0x01B0] [0x08002D30] =0x2000073C 
+  0x08002B80:  7005         STRB       R5, [R0]
+  0x08002B82:  4867         LDR        R0, =offTimeRT           ; [PC, #0x019C] [0x08002D20] =0x20000748 
+  0x08002B84:  7005         STRB       R5, [R0]
+  0x08002B86:  4865         LDR        R0, =blinkModeRT         ; [PC, #0x0194] [0x08002D1C] =0x20000754 
+  0x08002B88:  7005         STRB       R5, [R0]
+  0x08002B8A:  4867         LDR        R0, =numberOfBlinks      ; [PC, #0x019C] [0x08002D28] =0x200006BC 
+  0x08002B8C:  2703         MOVS       R7, #3
+  0x08002B8E:  6007         STR        R7, [R0]
+  0x08002B90:  4860         LDR        R0, =blinkCounter        ; [PC, #0x0180] [0x08002D14] =0x200006EC 
+  0x08002B92:  6007         STR        R7, [R0]
+  0x08002B94:  9A10         LDR        R2, [SP, #64]
+  0x08002B96:  32F4         ADDS       R2, #244
+  0x08002B98:  4879         LDR        R0, =0x08006874          ; [PC, #0x01E4] [0x08002D80] 
+  0x08002B9A:  495D         LDR        R1, =onTimeCounterRT     ; [PC, #0x0174] [0x08002D10] =0x2000069C 
+  0x08002B9C:  4B63         LDR        R3, =pauseTime           ; [PC, #0x018C] [0x08002D2C] =0x20000734 
+  0x08002B9E:  9E1E         LDR        R6, [SP, #120]
+  0x08002BA0:  F001 F947    BL         .L236                    ; 0x08003E32
+  0x08002BA4:  2001         MOVS       R0, #1
+  0x08002BA6:  F002 F863    BL         MODE_SECONDARYPROTECTION_PLUS_Exec ; 0x08004C70
+  0x08002BAA:  F001 FA8F    BL         .L254                    ; 0x080040CC
+  0x08002BAE:  2000         MOVS       R0, #0
+  0x08002BB0:  F002 F85E    BL         MODE_SECONDARYPROTECTION_PLUS_Exec ; 0x08004C70
+  0x08002BB4:  F001 FA8A    BL         .L254                    ; 0x080040CC
+  0x08002BB8:  2001         MOVS       R0, #1
+  0x08002BBA:  F001 FD1B    BL         MODE_SECONDARYPROTECTION_Exec ; 0x080045F4
+  0x08002BBE:  F001 FA85    BL         .L254                    ; 0x080040CC
+  0x08002BC2:  4C70         LDR        R4, =smState.145         ; [PC, #0x01C0] [0x08002D84] =0x20000733 
+  0x08002BC4:  7820         LDRB       R0, [R4]
+  0x08002BC6:  0040         LSLS       R0, R0, #1
+  0x08002BC8:  4478         ADD        R0, PC
+  0x08002BCA:  8880         LDRH       R0, [R0, #4]
+  0x08002BCC:  0040         LSLS       R0, R0, #1
+  0x08002BCE:  4487         ADD        PC, R0
+  0x08002BD0:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08002BD1:  00           DC.B       0x00                     ; '\0'
+  0x08002BD2:  1F           DC.B       0x1F                     ; '\x1F'
+  0x08002BD3:  02           DC.B       0x02                     ; '\x02'
+  0x08002BD4:  10           DC.B       0x10                     ; '\x10'
+  0x08002BD5:  01           DC.B       0x01                     ; '\x01'
+  0x08002BD6:  68           DC.B       0x68                     ; 'h'
+  0x08002BD7:  01           DC.B       0x01                     ; '\x01'
+  0x08002BD8:  2000073A     DC.W       buttonState
+  0x08002BDC:  08006511     DC.W       08006511               ; R_ARM_ABS32
+  0x08002BE0:  200006A8     DC.W       onTimeCounter
+  0x08002BE4:  50000410     DC.W       0x50000410
+  0x08002BE8:  2000075C     DC.W       alarmMode
+  0x08002BEC:  20000750     DC.W       offTime
+  0x08002BF0:  481C         LDR        R0, =0x50000410          ; [PC, #112] [0x08002C64] 
+  0x08002BF2:  6801         LDR        R1, [R0]
+  0x08002BF4:  4A16         LDR        R2, =buttonState         ; [PC, #88] [0x08002C50] =0x2000073A 
+  0x08002BF6:  7810         LDRB       R0, [R2]
+  0x08002BF8:  2801         CMP        R0, #1
+  0x08002BFA:  D001         BEQ        .L160                    ; 0x08002C00
+  0x08002BFC:  F001 F8CF    BL         .L232                    ; 0x08003D9E
+
.L160:
+  0x08002C00:  0748         LSLS       R0, R1, #29
+  0x08002C02:  D501         BPL        .L161                    ; 0x08002C08
+  0x08002C04:  F001 F8A8    BL         .L230                    ; 0x08003D58
+
.L161:
+  0x08002C08:  4816         LDR        R0, =0x50000410          ; [PC, #88] [0x08002C64] 
+  0x08002C0A:  9920         LDR        R1, [SP, #128]
+  0x08002C0C:  6081         STR        R1, [R0, #8]
+  0x08002C0E:  2000         MOVS       R0, #0
+  0x08002C10:  7010         STRB       R0, [R2]
+  0x08002C12:  4847         LDR        R0, =onTimeRT            ; [PC, #0x011C] [0x08002D30] =0x2000073C 
+  0x08002C14:  7005         STRB       R5, [R0]
+  0x08002C16:  4842         LDR        R0, =offTimeRT           ; [PC, #0x0108] [0x08002D20] =0x20000748 
+  0x08002C18:  7005         STRB       R5, [R0]
+  0x08002C1A:  4840         LDR        R0, =blinkModeRT         ; [PC, #0x0100] [0x08002D1C] =0x20000754 
+  0x08002C1C:  7005         STRB       R5, [R0]
+  0x08002C1E:  4842         LDR        R0, =numberOfBlinks      ; [PC, #0x0108] [0x08002D28] =0x200006BC 
+  0x08002C20:  9F14         LDR        R7, [SP, #80]
+  0x08002C22:  6007         STR        R7, [R0]
+  0x08002C24:  483B         LDR        R0, =blinkCounter        ; [PC, #236] [0x08002D14] =0x200006EC 
+  0x08002C26:  6007         STR        R7, [R0]
+  0x08002C28:  4857         LDR        R0, =0x08006667          ; [PC, #0x015C] [0x08002D88] 
+  0x08002C2A:  4939         LDR        R1, =onTimeCounterRT     ; [PC, #228] [0x08002D10] =0x2000069C 
+  0x08002C2C:  4B3F         LDR        R3, =pauseTime           ; [PC, #252] [0x08002D2C] =0x20000734 
+  0x08002C2E:  9A09         LDR        R2, [SP, #36]
+  0x08002C30:  9E1E         LDR        R6, [SP, #120]
+  0x08002C32:  F001 F8A7    BL         .L231                    ; 0x08003D84
+  0x08002C36:  2000         MOVS       R0, #0
+  0x08002C38:  F001 FCDC    BL         MODE_SECONDARYPROTECTION_Exec ; 0x080045F4
+  0x08002C3C:  F001 FA46    BL         .L254                    ; 0x080040CC
+  0x08002C40:  4C52         LDR        R4, =smState.122         ; [PC, #0x0148] [0x08002D8C] =0x20000736 
+  0x08002C42:  7820         LDRB       R0, [R4]
+  0x08002C44:  A105         ADR        R1, 0x08002C5C
+  0x08002C46:  0040         LSLS       R0, R0, #1
+  0x08002C48:  5A08         LDRH       R0, [R1, R0]
+  0x08002C4A:  0040         LSLS       R0, R0, #1
+  0x08002C4C:  4487         ADD        PC, R0
+  0x08002C4E:  46C0         NOP
+  0x08002C50:  2000073A     DC.W       buttonState
+  0x08002C54:  00001388     DC.W       0x00001388
+  0x08002C58:  200006B8     DC.W       offTimeCounter
+  0x08002C5C:  28           DC.B       0x28                     ; '('
+  0x08002C5D:  00           DC.B       0x00                     ; '\0'
+  0x08002C5E:  BD           DC.B       0xBD                     ; '\xBD'
+  0x08002C5F:  04           DC.B       0x04                     ; '\x04'
+  0x08002C60:  F7           DC.B       0xF7                     ; '\xF7'
+  0x08002C61:  02           DC.B       0x02                     ; '\x02'
+  0x08002C62:  40           DC.B       0x40                     ; '@'
+  0x08002C63:  04           DC.B       0x04                     ; '\x04'
+  0x08002C64:  50000410     DC.W       0x50000410
+  0x08002C68:  00001388     DC.W       0x00001388
+  0x08002C6C:  20000744     DC.W       onTime
+  0x08002C70:  20000660     DC.W       adcData
+  0x08002C74:  00000CE4     DC.W       0x00000CE4
+  0x08002C78:  00010063     DC.W       0x00010063
+  0x08002C7C:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08002C80:  20000694     DC.W       relais_temperature
+  0x08002C84:  20000698     DC.W       onTimeCounterSET
+  0x08002C88:  200006A0     DC.W       onTimeCounterRESET
+  0x08002C8C:  200006A4     DC.W       onTimeCounterGN
+  0x08002C90:  50000818     DC.W       0x50000818
+  0x08002C94:  20000758     DC.W       blinkModeGN
+  0x08002C98:  2000074C     DC.W       offTimeGN
+  0x08002C9C:  200006B4     DC.W       offTimeCounterGN
+  0x08002CA0:  483B         LDR        R0, =0x50000410          ; [PC, #236] [0x08002D90] 
+  0x08002CA2:  6801         LDR        R1, [R0]
+  0x08002CA4:  4A3B         LDR        R2, =buttonState         ; [PC, #236] [0x08002D94] =0x2000073A 
+  0x08002CA6:  7810         LDRB       R0, [R2]
+  0x08002CA8:  2801         CMP        R0, #1
+  0x08002CAA:  D001         BEQ        .L162                    ; 0x08002CB0
+  0x08002CAC:  F001 F981    BL         .L245                    ; 0x08003FB2
+
.L162:
+  0x08002CB0:  0748         LSLS       R0, R1, #29
+  0x08002CB2:  D501         BPL        .L163                    ; 0x08002CB8
+  0x08002CB4:  F001 F95A    BL         .L243                    ; 0x08003F6C
+
.L163:
+  0x08002CB8:  4835         LDR        R0, =0x50000410          ; [PC, #212] [0x08002D90] 
+  0x08002CBA:  9920         LDR        R1, [SP, #128]
+  0x08002CBC:  6081         STR        R1, [R0, #8]
+  0x08002CBE:  2000         MOVS       R0, #0
+  0x08002CC0:  7010         STRB       R0, [R2]
+  0x08002CC2:  481B         LDR        R0, =onTimeRT            ; [PC, #108] [0x08002D30] =0x2000073C 
+  0x08002CC4:  7005         STRB       R5, [R0]
+  0x08002CC6:  4816         LDR        R0, =offTimeRT           ; [PC, #88] [0x08002D20] =0x20000748 
+  0x08002CC8:  7005         STRB       R5, [R0]
+  0x08002CCA:  4814         LDR        R0, =blinkModeRT         ; [PC, #80] [0x08002D1C] =0x20000754 
+  0x08002CCC:  7005         STRB       R5, [R0]
+  0x08002CCE:  4816         LDR        R0, =numberOfBlinks      ; [PC, #88] [0x08002D28] =0x200006BC 
+  0x08002CD0:  2703         MOVS       R7, #3
+  0x08002CD2:  6007         STR        R7, [R0]
+  0x08002CD4:  480F         LDR        R0, =blinkCounter        ; [PC, #60] [0x08002D14] =0x200006EC 
+  0x08002CD6:  6007         STR        R7, [R0]
+  0x08002CD8:  9A10         LDR        R2, [SP, #64]
+  0x08002CDA:  32F4         ADDS       R2, #244
+  0x08002CDC:  482E         LDR        R0, =0x080065E3          ; [PC, #184] [0x08002D98] 
+  0x08002CDE:  490C         LDR        R1, =onTimeCounterRT     ; [PC, #48] [0x08002D10] =0x2000069C 
+  0x08002CE0:  4B12         LDR        R3, =pauseTime           ; [PC, #72] [0x08002D2C] =0x20000734 
+  0x08002CE2:  9E1E         LDR        R6, [SP, #120]
+  0x08002CE4:  F001 F958    BL         .L244                    ; 0x08003F98
+  0x08002CE8:  4C2C         LDR        R4, =smState             ; [PC, #176] [0x08002D9C] =0x20000737 
+  0x08002CEA:  7820         LDRB       R0, [R4]
+  0x08002CEC:  A105         ADR        R1, 0x08002D04
+  0x08002CEE:  0040         LSLS       R0, R0, #1
+  0x08002CF0:  5A08         LDRH       R0, [R1, R0]
+  0x08002CF2:  0040         LSLS       R0, R0, #1
+  0x08002CF4:  4487         ADD        PC, R0
+  0x08002CF6:  46C0         NOP
+  0x08002CF8:  200006B4     DC.W       offTimeCounterGN
+  0x08002CFC:  20000740     DC.W       onTimeGN
+  0x08002D00:  2000069C     DC.W       onTimeCounterRT
+  0x08002D04:  54           DC.B       0x54                     ; 'T'
+  0x08002D05:  00           DC.B       0x00                     ; '\0'
+  0x08002D06:  EA           DC.B       0xEA                     ; '\xEA'
+  0x08002D07:  05           DC.B       0x05                     ; '\x05'
+  0x08002D08:  BC           DC.B       0xBC                     ; '\xBC'
+  0x08002D09:  03           DC.B       0x03                     ; '\x03'
+  0x08002D0A:  52           DC.B       0x52                     ; 'R'
+  0x08002D0B:  04           DC.B       0x04                     ; '\x04'
+  0x08002D0C:  50000818     DC.W       0x50000818
+  0x08002D10:  2000069C     DC.W       onTimeCounterRT
+  0x08002D14:  200006EC     DC.W       blinkCounter
+  0x08002D18:  200006B0     DC.W       offTimeCounterRT
+  0x08002D1C:  20000754     DC.W       blinkModeRT
+  0x08002D20:  20000748     DC.W       offTimeRT
+  0x08002D24:  000003C7     DC.W       0x000003C7
+  0x08002D28:  200006BC     DC.W       numberOfBlinks
+  0x08002D2C:  20000734     DC.W       pauseTime
+  0x08002D30:  2000073C     DC.W       onTimeRT
+  0x08002D34:  20000688     DC.W       voltageUin
+  0x08002D38:  20000684     DC.W       voltageUout
+  0x08002D3C:  20000730     DC.W       relaisState
+  0x08002D40:  200006E4     DC.W       dropLimitCounter
+  0x08002D44:  20000000     DC.W       modbusData
+  0x08002D48:  080062BF     DC.W       080062BF               ; R_ARM_ABS32
+  0x08002D4C:  2000068C     DC.W       uwTick
+  0x08002D50:  200006AC     DC.W       oldTimeMSTick
+  0x08002D54:  200006C0     DC.W       msCounter
+  0x08002D58:  200006E8     DC.W       calTemperatureSensor30Value
+  0x08002D5C:  A3D70A3D     DC.W       0xA3D70A3D
+  0x08002D60:  40043D70     DC.W       0x40043D70
+  0x08002D64:  20000234     DC.W       sys_data
+  0x08002D68:  200005C8     DC.W       htim17
+  0x08002D6C:  200006E0     DC.W       frequency
+  0x08002D70:  20000690     DC.W       temp
+  0x08002D74:  50000010     DC.W       0x50000010
+  0x08002D78:  20000739     DC.W       mode
+  0x08002D7C:  20000735     DC.W       smState.137
+  0x08002D80:  08006874     DC.W       08006874               ; R_ARM_ABS32
+  0x08002D84:  20000733     DC.W       smState.145
+  0x08002D88:  08006667     DC.W       08006667               ; R_ARM_ABS32
+  0x08002D8C:  20000736     DC.W       smState.122
+  0x08002D90:  50000410     DC.W       0x50000410
+  0x08002D94:  2000073A     DC.W       buttonState
+  0x08002D98:  080065E3     DC.W       080065E3               ; R_ARM_ABS32
+  0x08002D9C:  20000737     DC.W       smState
+  0x08002DA0:  487E         LDR        R0, =0x50000410          ; [PC, #0x01F8] [0x08002F9C] 
+  0x08002DA2:  6801         LDR        R1, [R0]
+  0x08002DA4:  4A7E         LDR        R2, =buttonState         ; [PC, #0x01F8] [0x08002FA0] =0x2000073A 
+  0x08002DA6:  7810         LDRB       R0, [R2]
+  0x08002DA8:  2801         CMP        R0, #1
+  0x08002DAA:  D001         BEQ        .L164                    ; 0x08002DB0
+  0x08002DAC:  F001 F958    BL         .L250                    ; 0x08004060
+
.L164:
+  0x08002DB0:  0748         LSLS       R0, R1, #29
+  0x08002DB2:  D501         BPL        .L165                    ; 0x08002DB8
+  0x08002DB4:  F001 F931    BL         .L248                    ; 0x0800401A
+
.L165:
+  0x08002DB8:  4878         LDR        R0, =0x50000410          ; [PC, #0x01E0] [0x08002F9C] 
+  0x08002DBA:  9920         LDR        R1, [SP, #128]
+  0x08002DBC:  6081         STR        R1, [R0, #8]
+  0x08002DBE:  2000         MOVS       R0, #0
+  0x08002DC0:  7010         STRB       R0, [R2]
+  0x08002DC2:  4878         LDR        R0, =onTimeRT            ; [PC, #0x01E0] [0x08002FA4] =0x2000073C 
+  0x08002DC4:  7005         STRB       R5, [R0]
+  0x08002DC6:  4878         LDR        R0, =offTimeRT           ; [PC, #0x01E0] [0x08002FA8] =0x20000748 
+  0x08002DC8:  7005         STRB       R5, [R0]
+  0x08002DCA:  4878         LDR        R0, =blinkModeRT         ; [PC, #0x01E0] [0x08002FAC] =0x20000754 
+  0x08002DCC:  7005         STRB       R5, [R0]
+  0x08002DCE:  4878         LDR        R0, =numberOfBlinks      ; [PC, #0x01E0] [0x08002FB0] =0x200006BC 
+  0x08002DD0:  2703         MOVS       R7, #3
+  0x08002DD2:  6007         STR        R7, [R0]
+  0x08002DD4:  4877         LDR        R0, =blinkCounter        ; [PC, #0x01DC] [0x08002FB4] =0x200006EC 
+  0x08002DD6:  6007         STR        R7, [R0]
+  0x08002DD8:  9A10         LDR        R2, [SP, #64]
+  0x08002DDA:  32F4         ADDS       R2, #244
+  0x08002DDC:  4876         LDR        R0, =0x0800657F          ; [PC, #0x01D8] [0x08002FB8] 
+  0x08002DDE:  4977         LDR        R1, =onTimeCounterRT     ; [PC, #0x01DC] [0x08002FBC] =0x2000069C 
+  0x08002DE0:  4B77         LDR        R3, =pauseTime           ; [PC, #0x01DC] [0x08002FC0] =0x20000734 
+  0x08002DE2:  9E1E         LDR        R6, [SP, #120]
+  0x08002DE4:  F001 F92F    BL         .L249                    ; 0x08004046
+
.L166:
+  0x08002DE8:  4876         LDR        R0, =0x08006522          ; [PC, #0x01D8] [0x08002FC4] 
+  0x08002DEA:  F002 F9B5    BL         puts                     ; 0x08005158
+  0x08002DEE:  F001 F96D    BL         .L254                    ; 0x080040CC
+  0x08002DF2:  486B         LDR        R0, =buttonState         ; [PC, #0x01AC] [0x08002FA0] =0x2000073A 
+  0x08002DF4:  7800         LDRB       R0, [R0]
+  0x08002DF6:  2800         CMP        R0, #0
+  0x08002DF8:  D001         BEQ        .L167                    ; 0x08002DFE
+  0x08002DFA:  F001 F967    BL         .L254                    ; 0x080040CC
+
.L167:
+  0x08002DFE:  4967         LDR        R1, =0x50000410          ; [PC, #0x019C] [0x08002F9C] 
+  0x08002E00:  981A         LDR        R0, [SP, #104]
+  0x08002E02:  6188         STR        R0, [R1, #24]
+  0x08002E04:  9819         LDR        R0, [SP, #100]
+  0x08002E06:  6088         STR        R0, [R1, #8]
+  0x08002E08:  486F         LDR        R0, =relaisState         ; [PC, #0x01BC] [0x08002FC8] =0x20000730 
+  0x08002E0A:  2600         MOVS       R6, #0
+  0x08002E0C:  7006         STRB       R6, [R0]
+  0x08002E0E:  486F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01BC] [0x08002FCC] =0x200006A0 
+  0x08002E10:  9A15         LDR        R2, [SP, #84]
+  0x08002E12:  6002         STR        R2, [R0]
+  0x08002E14:  9820         LDR        R0, [SP, #128]
+  0x08002E16:  6188         STR        R0, [R1, #24]
+  0x08002E18:  486D         LDR        R0, =offTimeCounter      ; [PC, #0x01B4] [0x08002FD0] =0x200006B8 
+  0x08002E1A:  6006         STR        R6, [R0]
+  0x08002E1C:  486D         LDR        R0, =alarmMode           ; [PC, #0x01B4] [0x08002FD4] =0x2000075C 
+  0x08002E1E:  7006         STRB       R6, [R0]
+  0x08002E20:  486D         LDR        R0, =onTimeCounter       ; [PC, #0x01B4] [0x08002FD8] =0x200006A8 
+  0x08002E22:  6006         STR        R6, [R0]
+  0x08002E24:  496D         LDR        R1, =0x50000818          ; [PC, #0x01B4] [0x08002FDC] 
+  0x08002E26:  981F         LDR        R0, [SP, #124]
+  0x08002E28:  6108         STR        R0, [R1, #16]
+  0x08002E2A:  486D         LDR        R0, =offTimeCounterGN    ; [PC, #0x01B4] [0x08002FE0] =0x200006B4 
+  0x08002E2C:  6006         STR        R6, [R0]
+  0x08002E2E:  486D         LDR        R0, =blinkModeGN         ; [PC, #0x01B4] [0x08002FE4] =0x20000758 
+  0x08002E30:  7006         STRB       R6, [R0]
+  0x08002E32:  486D         LDR        R0, =onTimeCounterGN     ; [PC, #0x01B4] [0x08002FE8] =0x200006A4 
+  0x08002E34:  6006         STR        R6, [R0]
+  0x08002E36:  981E         LDR        R0, [SP, #120]
+  0x08002E38:  6108         STR        R0, [R1, #16]
+  0x08002E3A:  486C         LDR        R0, =offTimeCounterRT    ; [PC, #0x01B0] [0x08002FEC] =0x200006B0 
+  0x08002E3C:  6006         STR        R6, [R0]
+  0x08002E3E:  485B         LDR        R0, =blinkModeRT         ; [PC, #0x016C] [0x08002FAC] =0x20000754 
+  0x08002E40:  7006         STRB       R6, [R0]
+  0x08002E42:  485E         LDR        R0, =onTimeCounterRT     ; [PC, #0x0178] [0x08002FBC] =0x2000069C 
+  0x08002E44:  6006         STR        R6, [R0]
+  0x08002E46:  486A         LDR        R0, =0x0800625E          ; [PC, #0x01A8] [0x08002FF0] 
+  0x08002E48:  E33D         B          .L189                    ; 0x080034C6
+  0x08002E4A:  4855         LDR        R0, =buttonState         ; [PC, #0x0154] [0x08002FA0] =0x2000073A 
+  0x08002E4C:  7800         LDRB       R0, [R0]
+  0x08002E4E:  2800         CMP        R0, #0
+  0x08002E50:  D001         BEQ        .L168                    ; 0x08002E56
+  0x08002E52:  F001 F93B    BL         .L254                    ; 0x080040CC
+
.L168:
+  0x08002E56:  4951         LDR        R1, =0x50000410          ; [PC, #0x0144] [0x08002F9C] 
+  0x08002E58:  981A         LDR        R0, [SP, #104]
+  0x08002E5A:  6188         STR        R0, [R1, #24]
+  0x08002E5C:  9819         LDR        R0, [SP, #100]
+  0x08002E5E:  6088         STR        R0, [R1, #8]
+  0x08002E60:  4859         LDR        R0, =relaisState         ; [PC, #0x0164] [0x08002FC8] =0x20000730 
+  0x08002E62:  2600         MOVS       R6, #0
+  0x08002E64:  7006         STRB       R6, [R0]
+  0x08002E66:  4859         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0164] [0x08002FCC] =0x200006A0 
+  0x08002E68:  9A15         LDR        R2, [SP, #84]
+  0x08002E6A:  6002         STR        R2, [R0]
+  0x08002E6C:  9820         LDR        R0, [SP, #128]
+  0x08002E6E:  6188         STR        R0, [R1, #24]
+  0x08002E70:  4857         LDR        R0, =offTimeCounter      ; [PC, #0x015C] [0x08002FD0] =0x200006B8 
+  0x08002E72:  6006         STR        R6, [R0]
+  0x08002E74:  4857         LDR        R0, =alarmMode           ; [PC, #0x015C] [0x08002FD4] =0x2000075C 
+  0x08002E76:  7006         STRB       R6, [R0]
+  0x08002E78:  4857         LDR        R0, =onTimeCounter       ; [PC, #0x015C] [0x08002FD8] =0x200006A8 
+  0x08002E7A:  6006         STR        R6, [R0]
+  0x08002E7C:  4957         LDR        R1, =0x50000818          ; [PC, #0x015C] [0x08002FDC] 
+  0x08002E7E:  981F         LDR        R0, [SP, #124]
+  0x08002E80:  6108         STR        R0, [R1, #16]
+  0x08002E82:  4857         LDR        R0, =offTimeCounterGN    ; [PC, #0x015C] [0x08002FE0] =0x200006B4 
+  0x08002E84:  6006         STR        R6, [R0]
+  0x08002E86:  4857         LDR        R0, =blinkModeGN         ; [PC, #0x015C] [0x08002FE4] =0x20000758 
+  0x08002E88:  7006         STRB       R6, [R0]
+  0x08002E8A:  4857         LDR        R0, =onTimeCounterGN     ; [PC, #0x015C] [0x08002FE8] =0x200006A4 
+  0x08002E8C:  6006         STR        R6, [R0]
+  0x08002E8E:  981E         LDR        R0, [SP, #120]
+  0x08002E90:  6108         STR        R0, [R1, #16]
+  0x08002E92:  4856         LDR        R0, =offTimeCounterRT    ; [PC, #0x0158] [0x08002FEC] =0x200006B0 
+  0x08002E94:  6006         STR        R6, [R0]
+  0x08002E96:  4845         LDR        R0, =blinkModeRT         ; [PC, #0x0114] [0x08002FAC] =0x20000754 
+  0x08002E98:  7006         STRB       R6, [R0]
+  0x08002E9A:  4848         LDR        R0, =onTimeCounterRT     ; [PC, #0x0120] [0x08002FBC] =0x2000069C 
+  0x08002E9C:  6006         STR        R6, [R0]
+  0x08002E9E:  4855         LDR        R0, =0x08006441          ; [PC, #0x0154] [0x08002FF4] 
+  0x08002EA0:  E311         B          .L189                    ; 0x080034C6
+  0x08002EA2:  483E         LDR        R0, =0x50000410          ; [PC, #248] [0x08002F9C] 
+  0x08002EA4:  6801         LDR        R1, [R0]
+  0x08002EA6:  4E3E         LDR        R6, =buttonState         ; [PC, #248] [0x08002FA0] =0x2000073A 
+  0x08002EA8:  7830         LDRB       R0, [R6]
+  0x08002EAA:  2801         CMP        R0, #1
+  0x08002EAC:  D001         BEQ        .L169                    ; 0x08002EB2
+  0x08002EAE:  F000 FEC8    BL         .L228                    ; 0x08003C42
+
.L169:
+  0x08002EB2:  0748         LSLS       R0, R1, #29
+  0x08002EB4:  D501         BPL        .L170                    ; 0x08002EBA
+  0x08002EB6:  F000 FE9C    BL         .L227                    ; 0x08003BF2
+
.L170:
+  0x08002EBA:  4838         LDR        R0, =0x50000410          ; [PC, #224] [0x08002F9C] 
+  0x08002EBC:  9920         LDR        R1, [SP, #128]
+  0x08002EBE:  6081         STR        R1, [R0, #8]
+  0x08002EC0:  2000         MOVS       R0, #0
+  0x08002EC2:  7030         STRB       R0, [R6]
+  0x08002EC4:  4844         LDR        R0, =onTimeCounter       ; [PC, #0x0110] [0x08002FD8] =0x200006A8 
+  0x08002EC6:  9909         LDR        R1, [SP, #36]
+  0x08002EC8:  6001         STR        R1, [R0]
+  0x08002ECA:  F001 F8FF    BL         .L254                    ; 0x080040CC
+  0x08002ECE:  4833         LDR        R0, =0x50000410          ; [PC, #204] [0x08002F9C] 
+  0x08002ED0:  6801         LDR        R1, [R0]
+  0x08002ED2:  4E33         LDR        R6, =buttonState         ; [PC, #204] [0x08002FA0] =0x2000073A 
+  0x08002ED4:  7830         LDRB       R0, [R6]
+  0x08002ED6:  2801         CMP        R0, #1
+  0x08002ED8:  D12A         BNE        .L172                    ; 0x08002F30
+  0x08002EDA:  0748         LSLS       R0, R1, #29
+  0x08002EDC:  D400         BMI        .L171                    ; 0x08002EE0
+  0x08002EDE:  E369         B          .L193                    ; 0x080035B4
+
.L171:
+  0x08002EE0:  492E         LDR        R1, =0x50000410          ; [PC, #184] [0x08002F9C] 
+  0x08002EE2:  9819         LDR        R0, [SP, #100]
+  0x08002EE4:  6188         STR        R0, [R1, #24]
+  0x08002EE6:  981A         LDR        R0, [SP, #104]
+  0x08002EE8:  6088         STR        R0, [R1, #8]
+  0x08002EEA:  4837         LDR        R0, =relaisState         ; [PC, #220] [0x08002FC8] =0x20000730 
+  0x08002EEC:  7005         STRB       R5, [R0]
+  0x08002EEE:  4842         LDR        R0, =onTimeCounterSET    ; [PC, #0x0108] [0x08002FF8] =0x20000698 
+  0x08002EF0:  9A15         LDR        R2, [SP, #84]
+  0x08002EF2:  6002         STR        R2, [R0]
+  0x08002EF4:  9820         LDR        R0, [SP, #128]
+  0x08002EF6:  6088         STR        R0, [R1, #8]
+  0x08002EF8:  4840         LDR        R0, =onTimeGN            ; [PC, #0x0100] [0x08002FFC] =0x20000740 
+  0x08002EFA:  7005         STRB       R5, [R0]
+  0x08002EFC:  4836         LDR        R0, =onTimeCounter       ; [PC, #216] [0x08002FD8] =0x200006A8 
+  0x08002EFE:  21C8         MOVS       R1, #200
+  0x08002F00:  6001         STR        R1, [R0]
+  0x08002F02:  483F         LDR        R0, =offTimeGN           ; [PC, #252] [0x08003000] =0x2000074C 
+  0x08002F04:  7005         STRB       R5, [R0]
+  0x08002F06:  4837         LDR        R0, =blinkModeGN         ; [PC, #220] [0x08002FE4] =0x20000758 
+  0x08002F08:  7005         STRB       R5, [R0]
+  0x08002F0A:  4A34         LDR        R2, =0x50000818          ; [PC, #208] [0x08002FDC] 
+  0x08002F0C:  981F         LDR        R0, [SP, #124]
+  0x08002F0E:  6010         STR        R0, [R2]
+  0x08002F10:  4835         LDR        R0, =onTimeCounterGN     ; [PC, #212] [0x08002FE8] =0x200006A4 
+  0x08002F12:  6001         STR        R1, [R0]
+  0x08002F14:  981E         LDR        R0, [SP, #120]
+  0x08002F16:  6110         STR        R0, [R2, #16]
+  0x08002F18:  4834         LDR        R0, =offTimeCounterRT    ; [PC, #208] [0x08002FEC] =0x200006B0 
+  0x08002F1A:  2100         MOVS       R1, #0
+  0x08002F1C:  6001         STR        R1, [R0]
+  0x08002F1E:  4823         LDR        R0, =blinkModeRT         ; [PC, #140] [0x08002FAC] =0x20000754 
+  0x08002F20:  7001         STRB       R1, [R0]
+  0x08002F22:  4826         LDR        R0, =onTimeCounterRT     ; [PC, #152] [0x08002FBC] =0x2000069C 
+  0x08002F24:  6001         STR        R1, [R0]
+  0x08002F26:  4837         LDR        R0, =0x0800664E          ; [PC, #220] [0x08003004] 
+  0x08002F28:  F002 F916    BL         puts                     ; 0x08005158
+  0x08002F2C:  7025         STRB       R5, [R4]
+  0x08002F2E:  7830         LDRB       R0, [R6]
+
.L172:
+  0x08002F30:  2802         CMP        R0, #2
+  0x08002F32:  D001         BEQ        .L173                    ; 0x08002F38
+  0x08002F34:  F001 F8CA    BL         .L254                    ; 0x080040CC
+
.L173:
+  0x08002F38:  4918         LDR        R1, =0x50000410          ; [PC, #96] [0x08002F9C] 
+  0x08002F3A:  9819         LDR        R0, [SP, #100]
+  0x08002F3C:  6188         STR        R0, [R1, #24]
+  0x08002F3E:  981A         LDR        R0, [SP, #104]
+  0x08002F40:  6088         STR        R0, [R1, #8]
+  0x08002F42:  4821         LDR        R0, =relaisState         ; [PC, #132] [0x08002FC8] =0x20000730 
+  0x08002F44:  7005         STRB       R5, [R0]
+  0x08002F46:  482C         LDR        R0, =onTimeCounterSET    ; [PC, #176] [0x08002FF8] =0x20000698 
+  0x08002F48:  9A15         LDR        R2, [SP, #84]
+  0x08002F4A:  6002         STR        R2, [R0]
+  0x08002F4C:  482E         LDR        R0, =onTime              ; [PC, #184] [0x08003008] =0x20000744 
+  0x08002F4E:  7005         STRB       R5, [R0]
+  0x08002F50:  482E         LDR        R0, =offTime             ; [PC, #184] [0x0800300C] =0x20000750 
+  0x08002F52:  7005         STRB       R5, [R0]
+  0x08002F54:  481F         LDR        R0, =alarmMode           ; [PC, #124] [0x08002FD4] =0x2000075C 
+  0x08002F56:  7005         STRB       R5, [R0]
+  0x08002F58:  9820         LDR        R0, [SP, #128]
+  0x08002F5A:  6088         STR        R0, [R1, #8]
+  0x08002F5C:  491E         LDR        R1, =onTimeCounter       ; [PC, #120] [0x08002FD8] =0x200006A8 
+  0x08002F5E:  20C8         MOVS       R0, #200
+  0x08002F60:  6008         STR        R0, [R1]
+  0x08002F62:  4B1E         LDR        R3, =0x50000818          ; [PC, #120] [0x08002FDC] 
+  0x08002F64:  991F         LDR        R1, [SP, #124]
+  0x08002F66:  6019         STR        R1, [R3]
+  0x08002F68:  491F         LDR        R1, =onTimeCounterGN     ; [PC, #124] [0x08002FE8] =0x200006A4 
+  0x08002F6A:  2200         MOVS       R2, #0
+  0x08002F6C:  600A         STR        R2, [R1]
+  0x08002F6E:  491D         LDR        R1, =blinkModeGN         ; [PC, #116] [0x08002FE4] =0x20000758 
+  0x08002F70:  700A         STRB       R2, [R1]
+  0x08002F72:  491B         LDR        R1, =offTimeCounterGN    ; [PC, #108] [0x08002FE0] =0x200006B4 
+  0x08002F74:  600A         STR        R2, [R1]
+  0x08002F76:  9E1E         LDR        R6, [SP, #120]
+  0x08002F78:  611E         STR        R6, [R3, #16]
+  0x08002F7A:  490A         LDR        R1, =onTimeRT            ; [PC, #40] [0x08002FA4] =0x2000073C 
+  0x08002F7C:  700D         STRB       R5, [R1]
+  0x08002F7E:  491B         LDR        R1, =offTimeCounterRT    ; [PC, #108] [0x08002FEC] =0x200006B0 
+  0x08002F80:  600A         STR        R2, [R1]
+  0x08002F82:  4909         LDR        R1, =offTimeRT           ; [PC, #36] [0x08002FA8] =0x20000748 
+  0x08002F84:  700D         STRB       R5, [R1]
+  0x08002F86:  4909         LDR        R1, =blinkModeRT         ; [PC, #36] [0x08002FAC] =0x20000754 
+  0x08002F88:  700D         STRB       R5, [R1]
+  0x08002F8A:  4909         LDR        R1, =numberOfBlinks      ; [PC, #36] [0x08002FB0] =0x200006BC 
+  0x08002F8C:  600D         STR        R5, [R1]
+  0x08002F8E:  4909         LDR        R1, =blinkCounter        ; [PC, #36] [0x08002FB4] =0x200006EC 
+  0x08002F90:  600D         STR        R5, [R1]
+  0x08002F92:  490B         LDR        R1, =pauseTime           ; [PC, #44] [0x08002FC0] =0x20000734 
+  0x08002F94:  700D         STRB       R5, [R1]
+  0x08002F96:  601E         STR        R6, [R3]
+  0x08002F98:  F000 FF88    BL         .L239                    ; 0x08003EAC
+  0x08002F9C:  50000410     DC.W       0x50000410
+  0x08002FA0:  2000073A     DC.W       buttonState
+  0x08002FA4:  2000073C     DC.W       onTimeRT
+  0x08002FA8:  20000748     DC.W       offTimeRT
+  0x08002FAC:  20000754     DC.W       blinkModeRT
+  0x08002FB0:  200006BC     DC.W       numberOfBlinks
+  0x08002FB4:  200006EC     DC.W       blinkCounter
+  0x08002FB8:  0800657F     DC.W       0800657F               ; R_ARM_ABS32
+  0x08002FBC:  2000069C     DC.W       onTimeCounterRT
+  0x08002FC0:  20000734     DC.W       pauseTime
+  0x08002FC4:  08006522     DC.W       08006522               ; R_ARM_ABS32
+  0x08002FC8:  20000730     DC.W       relaisState
+  0x08002FCC:  200006A0     DC.W       onTimeCounterRESET
+  0x08002FD0:  200006B8     DC.W       offTimeCounter
+  0x08002FD4:  2000075C     DC.W       alarmMode
+  0x08002FD8:  200006A8     DC.W       onTimeCounter
+  0x08002FDC:  50000818     DC.W       0x50000818
+  0x08002FE0:  200006B4     DC.W       offTimeCounterGN
+  0x08002FE4:  20000758     DC.W       blinkModeGN
+  0x08002FE8:  200006A4     DC.W       onTimeCounterGN
+  0x08002FEC:  200006B0     DC.W       offTimeCounterRT
+  0x08002FF0:  0800625E     DC.W       0800625E               ; R_ARM_ABS32
+  0x08002FF4:  08006441     DC.W       08006441               ; R_ARM_ABS32
+  0x08002FF8:  20000698     DC.W       onTimeCounterSET
+  0x08002FFC:  20000740     DC.W       onTimeGN
+  0x08003000:  2000074C     DC.W       offTimeGN
+  0x08003004:  0800664E     DC.W       0800664E               ; R_ARM_ABS32
+  0x08003008:  20000744     DC.W       onTime
+  0x0800300C:  20000750     DC.W       offTime
+  0x08003010:  48EE         LDR        R0, =0x50000410          ; [PC, #0x03B8] [0x080033CC] 
+  0x08003012:  6800         LDR        R0, [R0]
+  0x08003014:  49EE         LDR        R1, =0x50000010          ; [PC, #0x03B8] [0x080033D0] 
+  0x08003016:  6809         LDR        R1, [R1]
+  0x08003018:  0789         LSLS       R1, R1, #30
+  0x0800301A:  D403         BMI        .L174                    ; 0x08003024
+  0x0800301C:  49EC         LDR        R1, =0x50000010          ; [PC, #0x03B0] [0x080033D0] 
+  0x0800301E:  6809         LDR        R1, [R1]
+  0x08003020:  0789         LSLS       R1, R1, #30
+  0x08003022:  D517         BPL        .L177                    ; 0x08003054
+
.L174:
+  0x08003024:  49EB         LDR        R1, =OVP_SM_On.oldtime   ; [PC, #0x03AC] [0x080033D4] =0x2000071C 
+  0x08003026:  680A         LDR        R2, [R1]
+  0x08003028:  4BEB         LDR        R3, =uwTick              ; [PC, #0x03AC] [0x080033D8] =0x2000068C 
+  0x0800302A:  681B         LDR        R3, [R3]
+  0x0800302C:  4293         CMP        R3, R2
+  0x0800302E:  D011         BEQ        .L177                    ; 0x08003054
+  0x08003030:  4AEA         LDR        R2, =OVP_SM_On.ovpTimeCounter ; [PC, #0x03A8] [0x080033DC] =0x20000718 
+  0x08003032:  6813         LDR        R3, [R2]
+  0x08003034:  4EEA         LDR        R6, =0x00001388          ; [PC, #0x03A8] [0x080033E0] 
+  0x08003036:  42B3         CMP        R3, R6
+  0x08003038:  DA05         BGE        .L175                    ; 0x08003046
+  0x0800303A:  1C5E         ADDS       R6, R3, #1
+  0x0800303C:  6016         STR        R6, [R2]
+  0x0800303E:  4EE8         LDR        R6, =0x00001388          ; [PC, #0x03A0] [0x080033E0] 
+  0x08003040:  1E76         SUBS       R6, R6, #1
+  0x08003042:  42B3         CMP        R3, R6
+  0x08003044:  D103         BNE        .L176                    ; 0x0800304E
+
.L175:
+  0x08003046:  2300         MOVS       R3, #0
+  0x08003048:  6013         STR        R3, [R2]
+  0x0800304A:  4AE6         LDR        R2, =OVP_SM_On.ovpInput  ; [PC, #0x0398] [0x080033E4] =0x20000760 
+  0x0800304C:  7015         STRB       R5, [R2]
+
.L176:
+  0x0800304E:  4AE2         LDR        R2, =uwTick              ; [PC, #0x0388] [0x080033D8] =0x2000068C 
+  0x08003050:  6812         LDR        R2, [R2]
+  0x08003052:  600A         STR        R2, [R1]
+
.L177:
+  0x08003054:  49DE         LDR        R1, =0x50000010          ; [PC, #0x0378] [0x080033D0] 
+  0x08003056:  6809         LDR        R1, [R1]
+  0x08003058:  0789         LSLS       R1, R1, #30
+  0x0800305A:  D404         BMI        .L178                    ; 0x08003066
+  0x0800305C:  49DF         LDR        R1, =OVP_SM_On.ovpTimeCounter ; [PC, #0x037C] [0x080033DC] =0x20000718 
+  0x0800305E:  2200         MOVS       R2, #0
+  0x08003060:  600A         STR        R2, [R1]
+  0x08003062:  49E0         LDR        R1, =OVP_SM_On.ovpInput  ; [PC, #0x0380] [0x080033E4] =0x20000760 
+  0x08003064:  700A         STRB       R2, [R1]
+
.L178:
+  0x08003066:  990E         LDR        R1, [SP, #56]
+  0x08003068:  4008         ANDS       R0, R1
+  0x0800306A:  D133         BNE        .L179                    ; 0x080030D4
+  0x0800306C:  4AD7         LDR        R2, =0x50000410          ; [PC, #0x035C] [0x080033CC] 
+  0x0800306E:  981A         LDR        R0, [SP, #104]
+  0x08003070:  6190         STR        R0, [R2, #24]
+  0x08003072:  9819         LDR        R0, [SP, #100]
+  0x08003074:  6090         STR        R0, [R2, #8]
+  0x08003076:  49DC         LDR        R1, =relaisState         ; [PC, #0x0370] [0x080033E8] =0x20000730 
+  0x08003078:  2000         MOVS       R0, #0
+  0x0800307A:  7008         STRB       R0, [R1]
+  0x0800307C:  49DB         LDR        R1, =onTimeCounterRESET  ; [PC, #0x036C] [0x080033EC] =0x200006A0 
+  0x0800307E:  9B15         LDR        R3, [SP, #84]
+  0x08003080:  600B         STR        R3, [R1]
+  0x08003082:  9920         LDR        R1, [SP, #128]
+  0x08003084:  6091         STR        R1, [R2, #8]
+  0x08003086:  49DA         LDR        R1, =onTimeCounter       ; [PC, #0x0368] [0x080033F0] =0x200006A8 
+  0x08003088:  9A09         LDR        R2, [SP, #36]
+  0x0800308A:  600A         STR        R2, [R1]
+  0x0800308C:  4AD9         LDR        R2, =0x50000818          ; [PC, #0x0364] [0x080033F4] 
+  0x0800308E:  991F         LDR        R1, [SP, #124]
+  0x08003090:  6111         STR        R1, [R2, #16]
+  0x08003092:  49D9         LDR        R1, =offTimeCounterGN    ; [PC, #0x0364] [0x080033F8] =0x200006B4 
+  0x08003094:  6008         STR        R0, [R1]
+  0x08003096:  49D9         LDR        R1, =blinkModeGN         ; [PC, #0x0364] [0x080033FC] =0x20000758 
+  0x08003098:  7008         STRB       R0, [R1]
+  0x0800309A:  49D9         LDR        R1, =onTimeCounterGN     ; [PC, #0x0364] [0x08003400] =0x200006A4 
+  0x0800309C:  6008         STR        R0, [R1]
+  0x0800309E:  49D9         LDR        R1, =onTimeRT            ; [PC, #0x0364] [0x08003404] =0x2000073C 
+  0x080030A0:  700D         STRB       R5, [R1]
+  0x080030A2:  49D9         LDR        R1, =offTimeRT           ; [PC, #0x0364] [0x08003408] =0x20000748 
+  0x080030A4:  700D         STRB       R5, [R1]
+  0x080030A6:  49D9         LDR        R1, =blinkModeRT         ; [PC, #0x0364] [0x0800340C] =0x20000754 
+  0x080030A8:  700D         STRB       R5, [R1]
+  0x080030AA:  49D9         LDR        R1, =numberOfBlinks      ; [PC, #0x0364] [0x08003410] =0x200006BC 
+  0x080030AC:  9E14         LDR        R6, [SP, #80]
+  0x080030AE:  600E         STR        R6, [R1]
+  0x080030B0:  49D8         LDR        R1, =blinkCounter        ; [PC, #0x0360] [0x08003414] =0x200006EC 
+  0x080030B2:  600E         STR        R6, [R1]
+  0x080030B4:  49D8         LDR        R1, =pauseTime           ; [PC, #0x0360] [0x08003418] =0x20000734 
+  0x080030B6:  700D         STRB       R5, [R1]
+  0x080030B8:  991E         LDR        R1, [SP, #120]
+  0x080030BA:  6011         STR        R1, [R2]
+  0x080030BC:  49D7         LDR        R1, =buttonState         ; [PC, #0x035C] [0x0800341C] =0x2000073A 
+  0x080030BE:  7008         STRB       R0, [R1]
+  0x080030C0:  48D7         LDR        R0, =onTimeCounterRT     ; [PC, #0x035C] [0x08003420] =0x2000069C 
+  0x080030C2:  21C8         MOVS       R1, #200
+  0x080030C4:  6001         STR        R1, [R0]
+  0x080030C6:  48D7         LDR        R0, =0x080068F4          ; [PC, #0x035C] [0x08003424] 
+  0x080030C8:  F002 F846    BL         puts                     ; 0x08005158
+  0x080030CC:  48D6         LDR        R0, =0x08006694          ; [PC, #0x0358] [0x08003428] 
+  0x080030CE:  F002 F843    BL         puts                     ; 0x08005158
+  0x080030D2:  7026         STRB       R6, [R4]
+
.L179:
+  0x080030D4:  48D5         LDR        R0, =temp                ; [PC, #0x0354] [0x0800342C] =0x20000690 
+  0x080030D6:  6800         LDR        R0, [R0]
+  0x080030D8:  2851         CMP        R0, #81
+  0x080030DA:  DB31         BLT        .L180                    ; 0x08003140
+  0x080030DC:  4ABB         LDR        R2, =0x50000410          ; [PC, #0x02EC] [0x080033CC] 
+  0x080030DE:  981A         LDR        R0, [SP, #104]
+  0x080030E0:  6190         STR        R0, [R2, #24]
+  0x080030E2:  9819         LDR        R0, [SP, #100]
+  0x080030E4:  6090         STR        R0, [R2, #8]
+  0x080030E6:  49C0         LDR        R1, =relaisState         ; [PC, #0x0300] [0x080033E8] =0x20000730 
+  0x080030E8:  2000         MOVS       R0, #0
+  0x080030EA:  7008         STRB       R0, [R1]
+  0x080030EC:  49BF         LDR        R1, =onTimeCounterRESET  ; [PC, #0x02FC] [0x080033EC] =0x200006A0 
+  0x080030EE:  9B15         LDR        R3, [SP, #84]
+  0x080030F0:  600B         STR        R3, [R1]
+  0x080030F2:  9920         LDR        R1, [SP, #128]
+  0x080030F4:  6091         STR        R1, [R2, #8]
+  0x080030F6:  49BE         LDR        R1, =onTimeCounter       ; [PC, #0x02F8] [0x080033F0] =0x200006A8 
+  0x080030F8:  9A09         LDR        R2, [SP, #36]
+  0x080030FA:  600A         STR        R2, [R1]
+  0x080030FC:  4BBD         LDR        R3, =0x50000818          ; [PC, #0x02F4] [0x080033F4] 
+  0x080030FE:  991F         LDR        R1, [SP, #124]
+  0x08003100:  6119         STR        R1, [R3, #16]
+  0x08003102:  49BD         LDR        R1, =offTimeCounterGN    ; [PC, #0x02F4] [0x080033F8] =0x200006B4 
+  0x08003104:  6008         STR        R0, [R1]
+  0x08003106:  49BD         LDR        R1, =blinkModeGN         ; [PC, #0x02F4] [0x080033FC] =0x20000758 
+  0x08003108:  7008         STRB       R0, [R1]
+  0x0800310A:  49BD         LDR        R1, =onTimeCounterGN     ; [PC, #0x02F4] [0x08003400] =0x200006A4 
+  0x0800310C:  6008         STR        R0, [R1]
+  0x0800310E:  49BD         LDR        R1, =onTimeRT            ; [PC, #0x02F4] [0x08003404] =0x2000073C 
+  0x08003110:  700D         STRB       R5, [R1]
+  0x08003112:  49BD         LDR        R1, =offTimeRT           ; [PC, #0x02F4] [0x08003408] =0x20000748 
+  0x08003114:  700D         STRB       R5, [R1]
+  0x08003116:  49BD         LDR        R1, =blinkModeRT         ; [PC, #0x02F4] [0x0800340C] =0x20000754 
+  0x08003118:  700D         STRB       R5, [R1]
+  0x0800311A:  49BD         LDR        R1, =numberOfBlinks      ; [PC, #0x02F4] [0x08003410] =0x200006BC 
+  0x0800311C:  2205         MOVS       R2, #5
+  0x0800311E:  600A         STR        R2, [R1]
+  0x08003120:  49BC         LDR        R1, =blinkCounter        ; [PC, #0x02F0] [0x08003414] =0x200006EC 
+  0x08003122:  600A         STR        R2, [R1]
+  0x08003124:  49BC         LDR        R1, =pauseTime           ; [PC, #0x02F0] [0x08003418] =0x20000734 
+  0x08003126:  700D         STRB       R5, [R1]
+  0x08003128:  991E         LDR        R1, [SP, #120]
+  0x0800312A:  6019         STR        R1, [R3]
+  0x0800312C:  49BB         LDR        R1, =buttonState         ; [PC, #0x02EC] [0x0800341C] =0x2000073A 
+  0x0800312E:  7008         STRB       R0, [R1]
+  0x08003130:  48BB         LDR        R0, =onTimeCounterRT     ; [PC, #0x02EC] [0x08003420] =0x2000069C 
+  0x08003132:  21C8         MOVS       R1, #200
+  0x08003134:  6001         STR        R1, [R0]
+  0x08003136:  48BE         LDR        R0, =0x08006294          ; [PC, #0x02F8] [0x08003430] 
+  0x08003138:  F002 F80E    BL         puts                     ; 0x08005158
+  0x0800313C:  9814         LDR        R0, [SP, #80]
+  0x0800313E:  7020         STRB       R0, [R4]
+
.L180:
+  0x08003140:  4EA8         LDR        R6, =OVP_SM_On.ovpInput  ; [PC, #0x02A0] [0x080033E4] =0x20000760 
+  0x08003142:  4BA9         LDR        R3, =relaisState         ; [PC, #0x02A4] [0x080033E8] =0x20000730 
+  0x08003144:  7830         LDRB       R0, [R6]
+  0x08003146:  2801         CMP        R0, #1
+  0x08003148:  7818         LDRB       R0, [R3]
+  0x0800314A:  D124         BNE        .L181                    ; 0x08003196
+  0x0800314C:  2800         CMP        R0, #0
+  0x0800314E:  D049         BEQ        .L182                    ; 0x080031E4
+  0x08003150:  4A9E         LDR        R2, =0x50000410          ; [PC, #0x0278] [0x080033CC] 
+  0x08003152:  981A         LDR        R0, [SP, #104]
+  0x08003154:  6190         STR        R0, [R2, #24]
+  0x08003156:  9819         LDR        R0, [SP, #100]
+  0x08003158:  6090         STR        R0, [R2, #8]
+  0x0800315A:  2000         MOVS       R0, #0
+  0x0800315C:  7018         STRB       R0, [R3]
+  0x0800315E:  49A3         LDR        R1, =onTimeCounterRESET  ; [PC, #0x028C] [0x080033EC] =0x200006A0 
+  0x08003160:  9B15         LDR        R3, [SP, #84]
+  0x08003162:  600B         STR        R3, [R1]
+  0x08003164:  9920         LDR        R1, [SP, #128]
+  0x08003166:  6091         STR        R1, [R2, #8]
+  0x08003168:  49A1         LDR        R1, =onTimeCounter       ; [PC, #0x0284] [0x080033F0] =0x200006A8 
+  0x0800316A:  9A09         LDR        R2, [SP, #36]
+  0x0800316C:  600A         STR        R2, [R1]
+  0x0800316E:  49A1         LDR        R1, =0x50000818          ; [PC, #0x0284] [0x080033F4] 
+  0x08003170:  9A1F         LDR        R2, [SP, #124]
+  0x08003172:  610A         STR        R2, [R1, #16]
+  0x08003174:  49A0         LDR        R1, =offTimeCounterGN    ; [PC, #0x0280] [0x080033F8] =0x200006B4 
+  0x08003176:  6008         STR        R0, [R1]
+  0x08003178:  49A0         LDR        R1, =blinkModeGN         ; [PC, #0x0280] [0x080033FC] =0x20000758 
+  0x0800317A:  7008         STRB       R0, [R1]
+  0x0800317C:  49A0         LDR        R1, =onTimeCounterGN     ; [PC, #0x0280] [0x08003400] =0x200006A4 
+  0x0800317E:  6008         STR        R0, [R1]
+  0x08003180:  48AC         LDR        R0, =0x080066A9          ; [PC, #0x02B0] [0x08003434] 
+  0x08003182:  F001 FFE9    BL         puts                     ; 0x08005158
+  0x08003186:  48AC         LDR        R0, =0x0800623B          ; [PC, #0x02B0] [0x08003438] 
+  0x08003188:  F001 FFE6    BL         puts                     ; 0x08005158
+  0x0800318C:  4B96         LDR        R3, =relaisState         ; [PC, #0x0258] [0x080033E8] =0x20000730 
+  0x0800318E:  7830         LDRB       R0, [R6]
+  0x08003190:  2800         CMP        R0, #0
+  0x08003192:  D127         BNE        .L182                    ; 0x080031E4
+  0x08003194:  7818         LDRB       R0, [R3]
+
.L181:
+  0x08003196:  2800         CMP        R0, #0
+  0x08003198:  D124         BNE        .L182                    ; 0x080031E4
+  0x0800319A:  498C         LDR        R1, =0x50000410          ; [PC, #0x0230] [0x080033CC] 
+  0x0800319C:  9819         LDR        R0, [SP, #100]
+  0x0800319E:  6188         STR        R0, [R1, #24]
+  0x080031A0:  981A         LDR        R0, [SP, #104]
+  0x080031A2:  6088         STR        R0, [R1, #8]
+  0x080031A4:  701D         STRB       R5, [R3]
+  0x080031A6:  48A5         LDR        R0, =onTimeCounterSET    ; [PC, #0x0294] [0x0800343C] =0x20000698 
+  0x080031A8:  9A15         LDR        R2, [SP, #84]
+  0x080031AA:  6002         STR        R2, [R0]
+  0x080031AC:  9820         LDR        R0, [SP, #128]
+  0x080031AE:  6088         STR        R0, [R1, #8]
+  0x080031B0:  488F         LDR        R0, =onTimeCounter       ; [PC, #0x023C] [0x080033F0] =0x200006A8 
+  0x080031B2:  21C8         MOVS       R1, #200
+  0x080031B4:  6001         STR        R1, [R0]
+  0x080031B6:  4B8F         LDR        R3, =0x50000818          ; [PC, #0x023C] [0x080033F4] 
+  0x080031B8:  9E1F         LDR        R6, [SP, #124]
+  0x080031BA:  611E         STR        R6, [R3, #16]
+  0x080031BC:  48A0         LDR        R0, =onTimeGN            ; [PC, #0x0280] [0x08003440] =0x20000740 
+  0x080031BE:  7005         STRB       R5, [R0]
+  0x080031C0:  488D         LDR        R0, =offTimeCounterGN    ; [PC, #0x0234] [0x080033F8] =0x200006B4 
+  0x080031C2:  2200         MOVS       R2, #0
+  0x080031C4:  6002         STR        R2, [R0]
+  0x080031C6:  489F         LDR        R0, =offTimeGN           ; [PC, #0x027C] [0x08003444] =0x2000074C 
+  0x080031C8:  7005         STRB       R5, [R0]
+  0x080031CA:  488C         LDR        R0, =blinkModeGN         ; [PC, #0x0230] [0x080033FC] =0x20000758 
+  0x080031CC:  7005         STRB       R5, [R0]
+  0x080031CE:  601E         STR        R6, [R3]
+  0x080031D0:  4E84         LDR        R6, =OVP_SM_On.ovpInput  ; [PC, #0x0210] [0x080033E4] =0x20000760 
+  0x080031D2:  488B         LDR        R0, =onTimeCounterGN     ; [PC, #0x022C] [0x08003400] =0x200006A4 
+  0x080031D4:  6001         STR        R1, [R0]
+  0x080031D6:  489C         LDR        R0, =0x080068B0          ; [PC, #0x0270] [0x08003448] 
+  0x080031D8:  F001 FFBE    BL         puts                     ; 0x08005158
+  0x080031DC:  489B         LDR        R0, =0x08006479          ; [PC, #0x026C] [0x0800344C] 
+  0x080031DE:  F001 FFBB    BL         puts                     ; 0x08005158
+  0x080031E2:  4B81         LDR        R3, =relaisState         ; [PC, #0x0204] [0x080033E8] =0x20000730 
+
.L182:
+  0x080031E4:  488D         LDR        R0, =buttonState         ; [PC, #0x0234] [0x0800341C] =0x2000073A 
+  0x080031E6:  7800         LDRB       R0, [R0]
+  0x080031E8:  2800         CMP        R0, #0
+  0x080031EA:  D001         BEQ        .L183                    ; 0x080031F0
+  0x080031EC:  F000 FF6E    BL         .L254                    ; 0x080040CC
+
.L183:
+  0x080031F0:  4976         LDR        R1, =0x50000410          ; [PC, #0x01D8] [0x080033CC] 
+  0x080031F2:  981A         LDR        R0, [SP, #104]
+  0x080031F4:  6188         STR        R0, [R1, #24]
+  0x080031F6:  9819         LDR        R0, [SP, #100]
+  0x080031F8:  6088         STR        R0, [R1, #8]
+  0x080031FA:  2700         MOVS       R7, #0
+  0x080031FC:  701F         STRB       R7, [R3]
+  0x080031FE:  487B         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01EC] [0x080033EC] =0x200006A0 
+  0x08003200:  9A15         LDR        R2, [SP, #84]
+  0x08003202:  6002         STR        R2, [R0]
+  0x08003204:  9820         LDR        R0, [SP, #128]
+  0x08003206:  6088         STR        R0, [R1, #8]
+  0x08003208:  4879         LDR        R0, =onTimeCounter       ; [PC, #0x01E4] [0x080033F0] =0x200006A8 
+  0x0800320A:  21C8         MOVS       R1, #200
+  0x0800320C:  6001         STR        R1, [R0]
+  0x0800320E:  4979         LDR        R1, =0x50000818          ; [PC, #0x01E4] [0x080033F4] 
+  0x08003210:  981F         LDR        R0, [SP, #124]
+  0x08003212:  6108         STR        R0, [R1, #16]
+  0x08003214:  4878         LDR        R0, =offTimeCounterGN    ; [PC, #0x01E0] [0x080033F8] =0x200006B4 
+  0x08003216:  6007         STR        R7, [R0]
+  0x08003218:  4878         LDR        R0, =blinkModeGN         ; [PC, #0x01E0] [0x080033FC] =0x20000758 
+  0x0800321A:  7007         STRB       R7, [R0]
+  0x0800321C:  4878         LDR        R0, =onTimeCounterGN     ; [PC, #0x01E0] [0x08003400] =0x200006A4 
+  0x0800321E:  6007         STR        R7, [R0]
+  0x08003220:  981E         LDR        R0, [SP, #120]
+  0x08003222:  6108         STR        R0, [R1, #16]
+  0x08003224:  488A         LDR        R0, =offTimeCounterRT    ; [PC, #0x0228] [0x08003450] =0x200006B0 
+  0x08003226:  6007         STR        R7, [R0]
+  0x08003228:  4878         LDR        R0, =blinkModeRT         ; [PC, #0x01E0] [0x0800340C] =0x20000754 
+  0x0800322A:  7007         STRB       R7, [R0]
+  0x0800322C:  487C         LDR        R0, =onTimeCounterRT     ; [PC, #0x01F0] [0x08003420] =0x2000069C 
+  0x0800322E:  6007         STR        R7, [R0]
+  0x08003230:  4888         LDR        R0, =0x0800625E          ; [PC, #0x0220] [0x08003454] 
+  0x08003232:  F001 FF91    BL         puts                     ; 0x08005158
+  0x08003236:  7027         STRB       R7, [R4]
+  0x08003238:  4868         LDR        R0, =OVP_SM_On.ovpTimeCounter ; [PC, #0x01A0] [0x080033DC] =0x20000718 
+  0x0800323A:  F000 FC70    BL         .L214                    ; 0x08003B1E
+  0x0800323E:  4877         LDR        R0, =buttonState         ; [PC, #0x01DC] [0x0800341C] =0x2000073A 
+  0x08003240:  7800         LDRB       R0, [R0]
+  0x08003242:  2800         CMP        R0, #0
+  0x08003244:  D001         BEQ        .L184                    ; 0x0800324A
+  0x08003246:  F000 FF41    BL         .L254                    ; 0x080040CC
+
.L184:
+  0x0800324A:  4960         LDR        R1, =0x50000410          ; [PC, #0x0180] [0x080033CC] 
+  0x0800324C:  981A         LDR        R0, [SP, #104]
+  0x0800324E:  6188         STR        R0, [R1, #24]
+  0x08003250:  9819         LDR        R0, [SP, #100]
+  0x08003252:  6088         STR        R0, [R1, #8]
+  0x08003254:  4864         LDR        R0, =relaisState         ; [PC, #0x0190] [0x080033E8] =0x20000730 
+  0x08003256:  2600         MOVS       R6, #0
+  0x08003258:  7006         STRB       R6, [R0]
+  0x0800325A:  4864         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0190] [0x080033EC] =0x200006A0 
+  0x0800325C:  9A15         LDR        R2, [SP, #84]
+  0x0800325E:  6002         STR        R2, [R0]
+  0x08003260:  9820         LDR        R0, [SP, #128]
+  0x08003262:  6188         STR        R0, [R1, #24]
+  0x08003264:  487C         LDR        R0, =offTimeCounter      ; [PC, #0x01F0] [0x08003458] =0x200006B8 
+  0x08003266:  6006         STR        R6, [R0]
+  0x08003268:  487C         LDR        R0, =alarmMode           ; [PC, #0x01F0] [0x0800345C] =0x2000075C 
+  0x0800326A:  7006         STRB       R6, [R0]
+  0x0800326C:  4860         LDR        R0, =onTimeCounter       ; [PC, #0x0180] [0x080033F0] =0x200006A8 
+  0x0800326E:  6006         STR        R6, [R0]
+  0x08003270:  4960         LDR        R1, =0x50000818          ; [PC, #0x0180] [0x080033F4] 
+  0x08003272:  981F         LDR        R0, [SP, #124]
+  0x08003274:  6108         STR        R0, [R1, #16]
+  0x08003276:  4860         LDR        R0, =offTimeCounterGN    ; [PC, #0x0180] [0x080033F8] =0x200006B4 
+  0x08003278:  6006         STR        R6, [R0]
+  0x0800327A:  4860         LDR        R0, =blinkModeGN         ; [PC, #0x0180] [0x080033FC] =0x20000758 
+  0x0800327C:  7006         STRB       R6, [R0]
+  0x0800327E:  4860         LDR        R0, =onTimeCounterGN     ; [PC, #0x0180] [0x08003400] =0x200006A4 
+  0x08003280:  6006         STR        R6, [R0]
+  0x08003282:  981E         LDR        R0, [SP, #120]
+  0x08003284:  6108         STR        R0, [R1, #16]
+  0x08003286:  4872         LDR        R0, =offTimeCounterRT    ; [PC, #0x01C8] [0x08003450] =0x200006B0 
+  0x08003288:  6006         STR        R6, [R0]
+  0x0800328A:  4860         LDR        R0, =blinkModeRT         ; [PC, #0x0180] [0x0800340C] =0x20000754 
+  0x0800328C:  7006         STRB       R6, [R0]
+  0x0800328E:  4864         LDR        R0, =onTimeCounterRT     ; [PC, #0x0190] [0x08003420] =0x2000069C 
+  0x08003290:  6006         STR        R6, [R0]
+  0x08003292:  4873         LDR        R0, =0x08006224          ; [PC, #0x01CC] [0x08003460] 
+  0x08003294:  E117         B          .L189                    ; 0x080034C6
+  0x08003296:  484D         LDR        R0, =0x50000410          ; [PC, #0x0134] [0x080033CC] 
+  0x08003298:  6807         LDR        R7, [R0]
+  0x0800329A:  4860         LDR        R0, =buttonState         ; [PC, #0x0180] [0x0800341C] =0x2000073A 
+  0x0800329C:  7800         LDRB       R0, [R0]
+  0x0800329E:  2800         CMP        R0, #0
+  0x080032A0:  D124         BNE        .L185                    ; 0x080032EC
+  0x080032A2:  494A         LDR        R1, =0x50000410          ; [PC, #0x0128] [0x080033CC] 
+  0x080032A4:  981A         LDR        R0, [SP, #104]
+  0x080032A6:  6188         STR        R0, [R1, #24]
+  0x080032A8:  9819         LDR        R0, [SP, #100]
+  0x080032AA:  6088         STR        R0, [R1, #8]
+  0x080032AC:  484E         LDR        R0, =relaisState         ; [PC, #0x0138] [0x080033E8] =0x20000730 
+  0x080032AE:  2600         MOVS       R6, #0
+  0x080032B0:  7006         STRB       R6, [R0]
+  0x080032B2:  484E         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0138] [0x080033EC] =0x200006A0 
+  0x080032B4:  9A15         LDR        R2, [SP, #84]
+  0x080032B6:  6002         STR        R2, [R0]
+  0x080032B8:  9820         LDR        R0, [SP, #128]
+  0x080032BA:  6088         STR        R0, [R1, #8]
+  0x080032BC:  484C         LDR        R0, =onTimeCounter       ; [PC, #0x0130] [0x080033F0] =0x200006A8 
+  0x080032BE:  21C8         MOVS       R1, #200
+  0x080032C0:  6001         STR        R1, [R0]
+  0x080032C2:  494C         LDR        R1, =0x50000818          ; [PC, #0x0130] [0x080033F4] 
+  0x080032C4:  981F         LDR        R0, [SP, #124]
+  0x080032C6:  6108         STR        R0, [R1, #16]
+  0x080032C8:  484B         LDR        R0, =offTimeCounterGN    ; [PC, #0x012C] [0x080033F8] =0x200006B4 
+  0x080032CA:  6006         STR        R6, [R0]
+  0x080032CC:  484B         LDR        R0, =blinkModeGN         ; [PC, #0x012C] [0x080033FC] =0x20000758 
+  0x080032CE:  7006         STRB       R6, [R0]
+  0x080032D0:  484B         LDR        R0, =onTimeCounterGN     ; [PC, #0x012C] [0x08003400] =0x200006A4 
+  0x080032D2:  6006         STR        R6, [R0]
+  0x080032D4:  981E         LDR        R0, [SP, #120]
+  0x080032D6:  6108         STR        R0, [R1, #16]
+  0x080032D8:  485D         LDR        R0, =offTimeCounterRT    ; [PC, #0x0174] [0x08003450] =0x200006B0 
+  0x080032DA:  6006         STR        R6, [R0]
+  0x080032DC:  484B         LDR        R0, =blinkModeRT         ; [PC, #0x012C] [0x0800340C] =0x20000754 
+  0x080032DE:  7006         STRB       R6, [R0]
+  0x080032E0:  484F         LDR        R0, =onTimeCounterRT     ; [PC, #0x013C] [0x08003420] =0x2000069C 
+  0x080032E2:  6006         STR        R6, [R0]
+  0x080032E4:  485F         LDR        R0, =0x08006441          ; [PC, #0x017C] [0x08003464] 
+  0x080032E6:  F001 FF37    BL         puts                     ; 0x08005158
+  0x080032EA:  7026         STRB       R6, [R4]
+
.L185:
+  0x080032EC:  980E         LDR        R0, [SP, #56]
+  0x080032EE:  4007         ANDS       R7, R0
+  0x080032F0:  D130         BNE        .L186                    ; 0x08003354
+  0x080032F2:  4A36         LDR        R2, =0x50000410          ; [PC, #216] [0x080033CC] 
+  0x080032F4:  981A         LDR        R0, [SP, #104]
+  0x080032F6:  6190         STR        R0, [R2, #24]
+  0x080032F8:  9819         LDR        R0, [SP, #100]
+  0x080032FA:  6090         STR        R0, [R2, #8]
+  0x080032FC:  493A         LDR        R1, =relaisState         ; [PC, #232] [0x080033E8] =0x20000730 
+  0x080032FE:  700F         STRB       R7, [R1]
+  0x08003300:  493A         LDR        R1, =onTimeCounterRESET  ; [PC, #232] [0x080033EC] =0x200006A0 
+  0x08003302:  9B15         LDR        R3, [SP, #84]
+  0x08003304:  600B         STR        R3, [R1]
+  0x08003306:  9920         LDR        R1, [SP, #128]
+  0x08003308:  6091         STR        R1, [R2, #8]
+  0x0800330A:  9910         LDR        R1, [SP, #64]
+  0x0800330C:  31F4         ADDS       R1, #244
+  0x0800330E:  4A38         LDR        R2, =onTimeCounter       ; [PC, #224] [0x080033F0] =0x200006A8 
+  0x08003310:  6011         STR        R1, [R2]
+  0x08003312:  4A38         LDR        R2, =0x50000818          ; [PC, #224] [0x080033F4] 
+  0x08003314:  991F         LDR        R1, [SP, #124]
+  0x08003316:  6111         STR        R1, [R2, #16]
+  0x08003318:  4937         LDR        R1, =offTimeCounterGN    ; [PC, #220] [0x080033F8] =0x200006B4 
+  0x0800331A:  600F         STR        R7, [R1]
+  0x0800331C:  4937         LDR        R1, =blinkModeGN         ; [PC, #220] [0x080033FC] =0x20000758 
+  0x0800331E:  700F         STRB       R7, [R1]
+  0x08003320:  4937         LDR        R1, =onTimeCounterGN     ; [PC, #220] [0x08003400] =0x200006A4 
+  0x08003322:  600F         STR        R7, [R1]
+  0x08003324:  4937         LDR        R1, =onTimeRT            ; [PC, #220] [0x08003404] =0x2000073C 
+  0x08003326:  700D         STRB       R5, [R1]
+  0x08003328:  4937         LDR        R1, =offTimeRT           ; [PC, #220] [0x08003408] =0x20000748 
+  0x0800332A:  700D         STRB       R5, [R1]
+  0x0800332C:  4937         LDR        R1, =blinkModeRT         ; [PC, #220] [0x0800340C] =0x20000754 
+  0x0800332E:  700D         STRB       R5, [R1]
+  0x08003330:  4937         LDR        R1, =numberOfBlinks      ; [PC, #220] [0x08003410] =0x200006BC 
+  0x08003332:  2603         MOVS       R6, #3
+  0x08003334:  600E         STR        R6, [R1]
+  0x08003336:  4937         LDR        R1, =blinkCounter        ; [PC, #220] [0x08003414] =0x200006EC 
+  0x08003338:  600E         STR        R6, [R1]
+  0x0800333A:  4937         LDR        R1, =pauseTime           ; [PC, #220] [0x08003418] =0x20000734 
+  0x0800333C:  700D         STRB       R5, [R1]
+  0x0800333E:  991E         LDR        R1, [SP, #120]
+  0x08003340:  6011         STR        R1, [R2]
+  0x08003342:  4936         LDR        R1, =buttonState         ; [PC, #216] [0x0800341C] =0x2000073A 
+  0x08003344:  700F         STRB       R7, [R1]
+  0x08003346:  4836         LDR        R0, =onTimeCounterRT     ; [PC, #216] [0x08003420] =0x2000069C 
+  0x08003348:  21C8         MOVS       R1, #200
+  0x0800334A:  6001         STR        R1, [R0]
+  0x0800334C:  4846         LDR        R0, =0x08006874          ; [PC, #0x0118] [0x08003468] 
+  0x0800334E:  F001 FF03    BL         puts                     ; 0x08005158
+  0x08003352:  7026         STRB       R6, [R4]
+
.L186:
+  0x08003354:  4835         LDR        R0, =temp                ; [PC, #212] [0x0800342C] =0x20000690 
+  0x08003356:  6800         LDR        R0, [R0]
+  0x08003358:  2851         CMP        R0, #81
+  0x0800335A:  4F44         LDR        R7, =modbusData          ; [PC, #0x0110] [0x0800346C] =0x20000000 
+  0x0800335C:  DA01         BGE        .L187                    ; 0x08003362
+  0x0800335E:  F000 FEB5    BL         .L254                    ; 0x080040CC
+
.L187:
+  0x08003362:  4A1A         LDR        R2, =0x50000410          ; [PC, #104] [0x080033CC] 
+  0x08003364:  981A         LDR        R0, [SP, #104]
+  0x08003366:  6190         STR        R0, [R2, #24]
+  0x08003368:  9819         LDR        R0, [SP, #100]
+  0x0800336A:  6090         STR        R0, [R2, #8]
+  0x0800336C:  491E         LDR        R1, =relaisState         ; [PC, #120] [0x080033E8] =0x20000730 
+  0x0800336E:  2000         MOVS       R0, #0
+  0x08003370:  7008         STRB       R0, [R1]
+  0x08003372:  491E         LDR        R1, =onTimeCounterRESET  ; [PC, #120] [0x080033EC] =0x200006A0 
+  0x08003374:  9B15         LDR        R3, [SP, #84]
+  0x08003376:  600B         STR        R3, [R1]
+  0x08003378:  9920         LDR        R1, [SP, #128]
+  0x0800337A:  6091         STR        R1, [R2, #8]
+  0x0800337C:  9910         LDR        R1, [SP, #64]
+  0x0800337E:  31F4         ADDS       R1, #244
+  0x08003380:  4A1B         LDR        R2, =onTimeCounter       ; [PC, #108] [0x080033F0] =0x200006A8 
+  0x08003382:  6011         STR        R1, [R2]
+  0x08003384:  4B1B         LDR        R3, =0x50000818          ; [PC, #108] [0x080033F4] 
+  0x08003386:  991F         LDR        R1, [SP, #124]
+  0x08003388:  6119         STR        R1, [R3, #16]
+  0x0800338A:  491B         LDR        R1, =offTimeCounterGN    ; [PC, #108] [0x080033F8] =0x200006B4 
+  0x0800338C:  6008         STR        R0, [R1]
+  0x0800338E:  491B         LDR        R1, =blinkModeGN         ; [PC, #108] [0x080033FC] =0x20000758 
+  0x08003390:  7008         STRB       R0, [R1]
+  0x08003392:  491B         LDR        R1, =onTimeCounterGN     ; [PC, #108] [0x08003400] =0x200006A4 
+  0x08003394:  6008         STR        R0, [R1]
+  0x08003396:  491B         LDR        R1, =onTimeRT            ; [PC, #108] [0x08003404] =0x2000073C 
+  0x08003398:  700D         STRB       R5, [R1]
+  0x0800339A:  491B         LDR        R1, =offTimeRT           ; [PC, #108] [0x08003408] =0x20000748 
+  0x0800339C:  700D         STRB       R5, [R1]
+  0x0800339E:  491B         LDR        R1, =blinkModeRT         ; [PC, #108] [0x0800340C] =0x20000754 
+  0x080033A0:  700D         STRB       R5, [R1]
+  0x080033A2:  491B         LDR        R1, =numberOfBlinks      ; [PC, #108] [0x08003410] =0x200006BC 
+  0x080033A4:  2205         MOVS       R2, #5
+  0x080033A6:  600A         STR        R2, [R1]
+  0x080033A8:  491A         LDR        R1, =blinkCounter        ; [PC, #104] [0x08003414] =0x200006EC 
+  0x080033AA:  600A         STR        R2, [R1]
+  0x080033AC:  491A         LDR        R1, =pauseTime           ; [PC, #104] [0x08003418] =0x20000734 
+  0x080033AE:  700D         STRB       R5, [R1]
+  0x080033B0:  991E         LDR        R1, [SP, #120]
+  0x080033B2:  6019         STR        R1, [R3]
+  0x080033B4:  4919         LDR        R1, =buttonState         ; [PC, #100] [0x0800341C] =0x2000073A 
+  0x080033B6:  7008         STRB       R0, [R1]
+  0x080033B8:  4819         LDR        R0, =onTimeCounterRT     ; [PC, #100] [0x08003420] =0x2000069C 
+  0x080033BA:  21C8         MOVS       R1, #200
+  0x080033BC:  6001         STR        R1, [R0]
+  0x080033BE:  481C         LDR        R0, =0x08006294          ; [PC, #112] [0x08003430] 
+  0x080033C0:  F001 FECA    BL         puts                     ; 0x08005158
+  0x080033C4:  2003         MOVS       R0, #3
+  0x080033C6:  F000 FE80    BL         .L253                    ; 0x080040CA
+  0x080033CA:  46C0         NOP
+  0x080033CC:  50000410     DC.W       0x50000410
+  0x080033D0:  50000010     DC.W       0x50000010
+  0x080033D4:  2000071C     DC.W       OVP_SM_On.oldtime
+  0x080033D8:  2000068C     DC.W       uwTick
+  0x080033DC:  20000718     DC.W       OVP_SM_On.ovpTimeCounter
+  0x080033E0:  00001388     DC.W       0x00001388
+  0x080033E4:  20000760     DC.W       OVP_SM_On.ovpInput
+  0x080033E8:  20000730     DC.W       relaisState
+  0x080033EC:  200006A0     DC.W       onTimeCounterRESET
+  0x080033F0:  200006A8     DC.W       onTimeCounter
+  0x080033F4:  50000818     DC.W       0x50000818
+  0x080033F8:  200006B4     DC.W       offTimeCounterGN
+  0x080033FC:  20000758     DC.W       blinkModeGN
+  0x08003400:  200006A4     DC.W       onTimeCounterGN
+  0x08003404:  2000073C     DC.W       onTimeRT
+  0x08003408:  20000748     DC.W       offTimeRT
+  0x0800340C:  20000754     DC.W       blinkModeRT
+  0x08003410:  200006BC     DC.W       numberOfBlinks
+  0x08003414:  200006EC     DC.W       blinkCounter
+  0x08003418:  20000734     DC.W       pauseTime
+  0x0800341C:  2000073A     DC.W       buttonState
+  0x08003420:  2000069C     DC.W       onTimeCounterRT
+  0x08003424:  080068F4     DC.W       080068F4               ; R_ARM_ABS32
+  0x08003428:  08006694     DC.W       08006694               ; R_ARM_ABS32
+  0x0800342C:  20000690     DC.W       temp
+  0x08003430:  08006294     DC.W       08006294               ; R_ARM_ABS32
+  0x08003434:  080066A9     DC.W       080066A9               ; R_ARM_ABS32
+  0x08003438:  0800623B     DC.W       0800623B               ; R_ARM_ABS32
+  0x0800343C:  20000698     DC.W       onTimeCounterSET
+  0x08003440:  20000740     DC.W       onTimeGN
+  0x08003444:  2000074C     DC.W       offTimeGN
+  0x08003448:  080068B0     DC.W       080068B0               ; R_ARM_ABS32
+  0x0800344C:  08006479     DC.W       08006479               ; R_ARM_ABS32
+  0x08003450:  200006B0     DC.W       offTimeCounterRT
+  0x08003454:  0800625E     DC.W       0800625E               ; R_ARM_ABS32
+  0x08003458:  200006B8     DC.W       offTimeCounter
+  0x0800345C:  2000075C     DC.W       alarmMode
+  0x08003460:  08006224     DC.W       08006224               ; R_ARM_ABS32
+  0x08003464:  08006441     DC.W       08006441               ; R_ARM_ABS32
+  0x08003468:  08006874     DC.W       08006874               ; R_ARM_ABS32
+  0x0800346C:  20000000     DC.W       modbusData
+  0x08003470:  48ED         LDR        R0, =buttonState         ; [PC, #0x03B4] [0x08003828] =0x2000073A 
+  0x08003472:  7800         LDRB       R0, [R0]
+  0x08003474:  2800         CMP        R0, #0
+  0x08003476:  D001         BEQ        .L188                    ; 0x0800347C
+  0x08003478:  F000 FE28    BL         .L254                    ; 0x080040CC
+
.L188:
+  0x0800347C:  49EB         LDR        R1, =0x50000410          ; [PC, #0x03AC] [0x0800382C] 
+  0x0800347E:  981A         LDR        R0, [SP, #104]
+  0x08003480:  6188         STR        R0, [R1, #24]
+  0x08003482:  9819         LDR        R0, [SP, #100]
+  0x08003484:  6088         STR        R0, [R1, #8]
+  0x08003486:  48EA         LDR        R0, =relaisState         ; [PC, #0x03A8] [0x08003830] =0x20000730 
+  0x08003488:  2600         MOVS       R6, #0
+  0x0800348A:  7006         STRB       R6, [R0]
+  0x0800348C:  48E9         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03A4] [0x08003834] =0x200006A0 
+  0x0800348E:  9A15         LDR        R2, [SP, #84]
+  0x08003490:  6002         STR        R2, [R0]
+  0x08003492:  9820         LDR        R0, [SP, #128]
+  0x08003494:  6188         STR        R0, [R1, #24]
+  0x08003496:  48E8         LDR        R0, =offTimeCounter      ; [PC, #0x03A0] [0x08003838] =0x200006B8 
+  0x08003498:  6006         STR        R6, [R0]
+  0x0800349A:  48E8         LDR        R0, =alarmMode           ; [PC, #0x03A0] [0x0800383C] =0x2000075C 
+  0x0800349C:  7006         STRB       R6, [R0]
+  0x0800349E:  48E8         LDR        R0, =onTimeCounter       ; [PC, #0x03A0] [0x08003840] =0x200006A8 
+  0x080034A0:  6006         STR        R6, [R0]
+  0x080034A2:  49E8         LDR        R1, =0x50000818          ; [PC, #0x03A0] [0x08003844] 
+  0x080034A4:  981F         LDR        R0, [SP, #124]
+  0x080034A6:  6108         STR        R0, [R1, #16]
+  0x080034A8:  48E7         LDR        R0, =offTimeCounterGN    ; [PC, #0x039C] [0x08003848] =0x200006B4 
+  0x080034AA:  6006         STR        R6, [R0]
+  0x080034AC:  48E7         LDR        R0, =blinkModeGN         ; [PC, #0x039C] [0x0800384C] =0x20000758 
+  0x080034AE:  7006         STRB       R6, [R0]
+  0x080034B0:  48E7         LDR        R0, =onTimeCounterGN     ; [PC, #0x039C] [0x08003850] =0x200006A4 
+  0x080034B2:  6006         STR        R6, [R0]
+  0x080034B4:  981E         LDR        R0, [SP, #120]
+  0x080034B6:  6108         STR        R0, [R1, #16]
+  0x080034B8:  48E6         LDR        R0, =offTimeCounterRT    ; [PC, #0x0398] [0x08003854] =0x200006B0 
+  0x080034BA:  6006         STR        R6, [R0]
+  0x080034BC:  48E6         LDR        R0, =blinkModeRT         ; [PC, #0x0398] [0x08003858] =0x20000754 
+  0x080034BE:  7006         STRB       R6, [R0]
+  0x080034C0:  48E6         LDR        R0, =onTimeCounterRT     ; [PC, #0x0398] [0x0800385C] =0x2000069C 
+  0x080034C2:  6006         STR        R6, [R0]
+  0x080034C4:  48E6         LDR        R0, =0x080061EA          ; [PC, #0x0398] [0x08003860] 
+
.L189:
+  0x080034C6:  F001 FE47    BL         puts                     ; 0x08005158
+  0x080034CA:  7026         STRB       R6, [R4]
+  0x080034CC:  F000 FDFE    BL         .L254                    ; 0x080040CC
+  0x080034D0:  48D6         LDR        R0, =0x50000410          ; [PC, #0x0358] [0x0800382C] 
+  0x080034D2:  6801         LDR        R1, [R0]
+  0x080034D4:  4ED4         LDR        R6, =buttonState         ; [PC, #0x0350] [0x08003828] =0x2000073A 
+  0x080034D6:  7830         LDRB       R0, [R6]
+  0x080034D8:  2801         CMP        R0, #1
+  0x080034DA:  D129         BNE        .L190                    ; 0x08003530
+  0x080034DC:  0748         LSLS       R0, R1, #29
+  0x080034DE:  D569         BPL        .L193                    ; 0x080035B4
+  0x080034E0:  49D2         LDR        R1, =0x50000410          ; [PC, #0x0348] [0x0800382C] 
+  0x080034E2:  9819         LDR        R0, [SP, #100]
+  0x080034E4:  6188         STR        R0, [R1, #24]
+  0x080034E6:  981A         LDR        R0, [SP, #104]
+  0x080034E8:  6088         STR        R0, [R1, #8]
+  0x080034EA:  48D1         LDR        R0, =relaisState         ; [PC, #0x0344] [0x08003830] =0x20000730 
+  0x080034EC:  7005         STRB       R5, [R0]
+  0x080034EE:  48DD         LDR        R0, =onTimeCounterSET    ; [PC, #0x0374] [0x08003864] =0x20000698 
+  0x080034F0:  9A15         LDR        R2, [SP, #84]
+  0x080034F2:  6002         STR        R2, [R0]
+  0x080034F4:  9820         LDR        R0, [SP, #128]
+  0x080034F6:  6088         STR        R0, [R1, #8]
+  0x080034F8:  48DB         LDR        R0, =onTimeGN            ; [PC, #0x036C] [0x08003868] =0x20000740 
+  0x080034FA:  7005         STRB       R5, [R0]
+  0x080034FC:  48D0         LDR        R0, =onTimeCounter       ; [PC, #0x0340] [0x08003840] =0x200006A8 
+  0x080034FE:  21C8         MOVS       R1, #200
+  0x08003500:  6001         STR        R1, [R0]
+  0x08003502:  48DA         LDR        R0, =offTimeGN           ; [PC, #0x0368] [0x0800386C] =0x2000074C 
+  0x08003504:  7005         STRB       R5, [R0]
+  0x08003506:  48D1         LDR        R0, =blinkModeGN         ; [PC, #0x0344] [0x0800384C] =0x20000758 
+  0x08003508:  7005         STRB       R5, [R0]
+  0x0800350A:  4ACE         LDR        R2, =0x50000818          ; [PC, #0x0338] [0x08003844] 
+  0x0800350C:  981F         LDR        R0, [SP, #124]
+  0x0800350E:  6010         STR        R0, [R2]
+  0x08003510:  48CF         LDR        R0, =onTimeCounterGN     ; [PC, #0x033C] [0x08003850] =0x200006A4 
+  0x08003512:  6001         STR        R1, [R0]
+  0x08003514:  981E         LDR        R0, [SP, #120]
+  0x08003516:  6110         STR        R0, [R2, #16]
+  0x08003518:  48CE         LDR        R0, =offTimeCounterRT    ; [PC, #0x0338] [0x08003854] =0x200006B0 
+  0x0800351A:  2100         MOVS       R1, #0
+  0x0800351C:  6001         STR        R1, [R0]
+  0x0800351E:  48CE         LDR        R0, =blinkModeRT         ; [PC, #0x0338] [0x08003858] =0x20000754 
+  0x08003520:  7001         STRB       R1, [R0]
+  0x08003522:  48CE         LDR        R0, =onTimeCounterRT     ; [PC, #0x0338] [0x0800385C] =0x2000069C 
+  0x08003524:  6001         STR        R1, [R0]
+  0x08003526:  48D2         LDR        R0, =0x0800642B          ; [PC, #0x0348] [0x08003870] 
+  0x08003528:  F001 FE16    BL         puts                     ; 0x08005158
+  0x0800352C:  7025         STRB       R5, [R4]
+  0x0800352E:  7830         LDRB       R0, [R6]
+
.L190:
+  0x08003530:  2802         CMP        R0, #2
+  0x08003532:  D001         BEQ        .L191                    ; 0x08003538
+  0x08003534:  F000 FDCA    BL         .L254                    ; 0x080040CC
+
.L191:
+  0x08003538:  49BC         LDR        R1, =0x50000410          ; [PC, #0x02F0] [0x0800382C] 
+  0x0800353A:  9819         LDR        R0, [SP, #100]
+  0x0800353C:  6188         STR        R0, [R1, #24]
+  0x0800353E:  981A         LDR        R0, [SP, #104]
+  0x08003540:  6088         STR        R0, [R1, #8]
+  0x08003542:  48BB         LDR        R0, =relaisState         ; [PC, #0x02EC] [0x08003830] =0x20000730 
+  0x08003544:  7005         STRB       R5, [R0]
+  0x08003546:  48C7         LDR        R0, =onTimeCounterSET    ; [PC, #0x031C] [0x08003864] =0x20000698 
+  0x08003548:  9A15         LDR        R2, [SP, #84]
+  0x0800354A:  6002         STR        R2, [R0]
+  0x0800354C:  48C9         LDR        R0, =onTime              ; [PC, #0x0324] [0x08003874] =0x20000744 
+  0x0800354E:  7005         STRB       R5, [R0]
+  0x08003550:  48C9         LDR        R0, =offTime             ; [PC, #0x0324] [0x08003878] =0x20000750 
+  0x08003552:  7005         STRB       R5, [R0]
+  0x08003554:  48B9         LDR        R0, =alarmMode           ; [PC, #0x02E4] [0x0800383C] =0x2000075C 
+  0x08003556:  7005         STRB       R5, [R0]
+  0x08003558:  9820         LDR        R0, [SP, #128]
+  0x0800355A:  6088         STR        R0, [R1, #8]
+  0x0800355C:  49B8         LDR        R1, =onTimeCounter       ; [PC, #0x02E0] [0x08003840] =0x200006A8 
+  0x0800355E:  20C8         MOVS       R0, #200
+  0x08003560:  6008         STR        R0, [R1]
+  0x08003562:  4BB8         LDR        R3, =0x50000818          ; [PC, #0x02E0] [0x08003844] 
+  0x08003564:  991F         LDR        R1, [SP, #124]
+  0x08003566:  6019         STR        R1, [R3]
+  0x08003568:  49B9         LDR        R1, =onTimeCounterGN     ; [PC, #0x02E4] [0x08003850] =0x200006A4 
+  0x0800356A:  2200         MOVS       R2, #0
+  0x0800356C:  600A         STR        R2, [R1]
+  0x0800356E:  49B7         LDR        R1, =blinkModeGN         ; [PC, #0x02DC] [0x0800384C] =0x20000758 
+  0x08003570:  700A         STRB       R2, [R1]
+  0x08003572:  49B5         LDR        R1, =offTimeCounterGN    ; [PC, #0x02D4] [0x08003848] =0x200006B4 
+  0x08003574:  600A         STR        R2, [R1]
+  0x08003576:  9E1E         LDR        R6, [SP, #120]
+  0x08003578:  611E         STR        R6, [R3, #16]
+  0x0800357A:  49C0         LDR        R1, =onTimeRT            ; [PC, #0x0300] [0x0800387C] =0x2000073C 
+  0x0800357C:  700D         STRB       R5, [R1]
+  0x0800357E:  49B5         LDR        R1, =offTimeCounterRT    ; [PC, #0x02D4] [0x08003854] =0x200006B0 
+  0x08003580:  600A         STR        R2, [R1]
+  0x08003582:  49BF         LDR        R1, =offTimeRT           ; [PC, #0x02FC] [0x08003880] =0x20000748 
+  0x08003584:  700D         STRB       R5, [R1]
+  0x08003586:  49B4         LDR        R1, =blinkModeRT         ; [PC, #0x02D0] [0x08003858] =0x20000754 
+  0x08003588:  700D         STRB       R5, [R1]
+  0x0800358A:  49BE         LDR        R1, =numberOfBlinks      ; [PC, #0x02F8] [0x08003884] =0x200006BC 
+  0x0800358C:  600D         STR        R5, [R1]
+  0x0800358E:  49BE         LDR        R1, =blinkCounter        ; [PC, #0x02F8] [0x08003888] =0x200006EC 
+  0x08003590:  600D         STR        R5, [R1]
+  0x08003592:  49BE         LDR        R1, =pauseTime           ; [PC, #0x02F8] [0x0800388C] =0x20000734 
+  0x08003594:  700D         STRB       R5, [R1]
+  0x08003596:  601E         STR        R6, [R3]
+  0x08003598:  F000 FD3B    BL         .L247                    ; 0x08004012
+  0x0800359C:  48A3         LDR        R0, =0x50000410          ; [PC, #0x028C] [0x0800382C] 
+  0x0800359E:  6801         LDR        R1, [R0]
+  0x080035A0:  4EA1         LDR        R6, =buttonState         ; [PC, #0x0284] [0x08003828] =0x2000073A 
+  0x080035A2:  7830         LDRB       R0, [R6]
+  0x080035A4:  2801         CMP        R0, #1
+  0x080035A6:  D001         BEQ        .L192                    ; 0x080035AC
+  0x080035A8:  F000 FCAC    BL         .L241                    ; 0x08003F04
+
.L192:
+  0x080035AC:  0748         LSLS       R0, R1, #29
+  0x080035AE:  D501         BPL        .L193                    ; 0x080035B4
+  0x080035B0:  F000 FC80    BL         .L240                    ; 0x08003EB4
+
.L193:
+  0x080035B4:  489D         LDR        R0, =0x50000410          ; [PC, #0x0274] [0x0800382C] 
+  0x080035B6:  9920         LDR        R1, [SP, #128]
+  0x080035B8:  6081         STR        R1, [R0, #8]
+  0x080035BA:  2000         MOVS       R0, #0
+  0x080035BC:  7030         STRB       R0, [R6]
+  0x080035BE:  9810         LDR        R0, [SP, #64]
+  0x080035C0:  30F4         ADDS       R0, #244
+  0x080035C2:  499F         LDR        R1, =onTimeCounter       ; [PC, #0x027C] [0x08003840] =0x200006A8 
+  0x080035C4:  6008         STR        R0, [R1]
+  0x080035C6:  F000 FD81    BL         .L254                    ; 0x080040CC
+  0x080035CA:  4898         LDR        R0, =0x50000410          ; [PC, #0x0260] [0x0800382C] 
+  0x080035CC:  6800         LDR        R0, [R0]
+  0x080035CE:  49B0         LDR        R1, =0x50000010          ; [PC, #0x02C0] [0x08003890] 
+  0x080035D0:  6809         LDR        R1, [R1]
+  0x080035D2:  07C9         LSLS       R1, R1, #31
+  0x080035D4:  D103         BNE        .L194                    ; 0x080035DE
+  0x080035D6:  49AE         LDR        R1, =0x50000010          ; [PC, #0x02B8] [0x08003890] 
+  0x080035D8:  6809         LDR        R1, [R1]
+  0x080035DA:  0789         LSLS       R1, R1, #30
+  0x080035DC:  D517         BPL        .L197                    ; 0x0800360E
+
.L194:
+  0x080035DE:  49AD         LDR        R1, =LVP_OVP_SM_On.oldtime ; [PC, #0x02B4] [0x08003894] =0x20000728 
+  0x080035E0:  680A         LDR        R2, [R1]
+  0x080035E2:  4BAD         LDR        R3, =uwTick              ; [PC, #0x02B4] [0x08003898] =0x2000068C 
+  0x080035E4:  681B         LDR        R3, [R3]
+  0x080035E6:  4293         CMP        R3, R2
+  0x080035E8:  D011         BEQ        .L197                    ; 0x0800360E
+  0x080035EA:  4AAC         LDR        R2, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x02B0] [0x0800389C] =0x2000072C 
+  0x080035EC:  6813         LDR        R3, [R2]
+  0x080035EE:  4EAC         LDR        R6, =0x00001388          ; [PC, #0x02B0] [0x080038A0] 
+  0x080035F0:  42B3         CMP        R3, R6
+  0x080035F2:  DA05         BGE        .L195                    ; 0x08003600
+  0x080035F4:  1C5E         ADDS       R6, R3, #1
+  0x080035F6:  6016         STR        R6, [R2]
+  0x080035F8:  4EA9         LDR        R6, =0x00001388          ; [PC, #0x02A4] [0x080038A0] 
+  0x080035FA:  1E76         SUBS       R6, R6, #1
+  0x080035FC:  42B3         CMP        R3, R6
+  0x080035FE:  D103         BNE        .L196                    ; 0x08003608
+
.L195:
+  0x08003600:  2300         MOVS       R3, #0
+  0x08003602:  6013         STR        R3, [R2]
+  0x08003604:  4AA7         LDR        R2, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x029C] [0x080038A4] =0x20000768 
+  0x08003606:  7015         STRB       R5, [R2]
+
.L196:
+  0x08003608:  4AA3         LDR        R2, =uwTick              ; [PC, #0x028C] [0x08003898] =0x2000068C 
+  0x0800360A:  6812         LDR        R2, [R2]
+  0x0800360C:  600A         STR        R2, [R1]
+
.L197:
+  0x0800360E:  49A0         LDR        R1, =0x50000010          ; [PC, #0x0280] [0x08003890] 
+  0x08003610:  6809         LDR        R1, [R1]
+  0x08003612:  07C9         LSLS       R1, R1, #31
+  0x08003614:  D108         BNE        .L198                    ; 0x08003628
+  0x08003616:  499E         LDR        R1, =0x50000010          ; [PC, #0x0278] [0x08003890] 
+  0x08003618:  6809         LDR        R1, [R1]
+  0x0800361A:  0789         LSLS       R1, R1, #30
+  0x0800361C:  D404         BMI        .L198                    ; 0x08003628
+  0x0800361E:  499F         LDR        R1, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x027C] [0x0800389C] =0x2000072C 
+  0x08003620:  2200         MOVS       R2, #0
+  0x08003622:  600A         STR        R2, [R1]
+  0x08003624:  499F         LDR        R1, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x027C] [0x080038A4] =0x20000768 
+  0x08003626:  700A         STRB       R2, [R1]
+
.L198:
+  0x08003628:  990E         LDR        R1, [SP, #56]
+  0x0800362A:  4008         ANDS       R0, R1
+  0x0800362C:  D134         BNE        .L199                    ; 0x08003698
+  0x0800362E:  4A7F         LDR        R2, =0x50000410          ; [PC, #0x01FC] [0x0800382C] 
+  0x08003630:  981A         LDR        R0, [SP, #104]
+  0x08003632:  6190         STR        R0, [R2, #24]
+  0x08003634:  9819         LDR        R0, [SP, #100]
+  0x08003636:  6090         STR        R0, [R2, #8]
+  0x08003638:  497D         LDR        R1, =relaisState         ; [PC, #0x01F4] [0x08003830] =0x20000730 
+  0x0800363A:  2000         MOVS       R0, #0
+  0x0800363C:  7008         STRB       R0, [R1]
+  0x0800363E:  497D         LDR        R1, =onTimeCounterRESET  ; [PC, #0x01F4] [0x08003834] =0x200006A0 
+  0x08003640:  9B15         LDR        R3, [SP, #84]
+  0x08003642:  600B         STR        R3, [R1]
+  0x08003644:  9920         LDR        R1, [SP, #128]
+  0x08003646:  6091         STR        R1, [R2, #8]
+  0x08003648:  9910         LDR        R1, [SP, #64]
+  0x0800364A:  31F4         ADDS       R1, #244
+  0x0800364C:  4A7C         LDR        R2, =onTimeCounter       ; [PC, #0x01F0] [0x08003840] =0x200006A8 
+  0x0800364E:  6011         STR        R1, [R2]
+  0x08003650:  4A7C         LDR        R2, =0x50000818          ; [PC, #0x01F0] [0x08003844] 
+  0x08003652:  991F         LDR        R1, [SP, #124]
+  0x08003654:  6111         STR        R1, [R2, #16]
+  0x08003656:  497C         LDR        R1, =offTimeCounterGN    ; [PC, #0x01F0] [0x08003848] =0x200006B4 
+  0x08003658:  6008         STR        R0, [R1]
+  0x0800365A:  497C         LDR        R1, =blinkModeGN         ; [PC, #0x01F0] [0x0800384C] =0x20000758 
+  0x0800365C:  7008         STRB       R0, [R1]
+  0x0800365E:  497C         LDR        R1, =onTimeCounterGN     ; [PC, #0x01F0] [0x08003850] =0x200006A4 
+  0x08003660:  6008         STR        R0, [R1]
+  0x08003662:  4986         LDR        R1, =onTimeRT            ; [PC, #0x0218] [0x0800387C] =0x2000073C 
+  0x08003664:  700D         STRB       R5, [R1]
+  0x08003666:  4986         LDR        R1, =offTimeRT           ; [PC, #0x0218] [0x08003880] =0x20000748 
+  0x08003668:  700D         STRB       R5, [R1]
+  0x0800366A:  497B         LDR        R1, =blinkModeRT         ; [PC, #0x01EC] [0x08003858] =0x20000754 
+  0x0800366C:  700D         STRB       R5, [R1]
+  0x0800366E:  4985         LDR        R1, =numberOfBlinks      ; [PC, #0x0214] [0x08003884] =0x200006BC 
+  0x08003670:  2603         MOVS       R6, #3
+  0x08003672:  600E         STR        R6, [R1]
+  0x08003674:  4984         LDR        R1, =blinkCounter        ; [PC, #0x0210] [0x08003888] =0x200006EC 
+  0x08003676:  600E         STR        R6, [R1]
+  0x08003678:  4984         LDR        R1, =pauseTime           ; [PC, #0x0210] [0x0800388C] =0x20000734 
+  0x0800367A:  700D         STRB       R5, [R1]
+  0x0800367C:  991E         LDR        R1, [SP, #120]
+  0x0800367E:  6011         STR        R1, [R2]
+  0x08003680:  4969         LDR        R1, =buttonState         ; [PC, #0x01A4] [0x08003828] =0x2000073A 
+  0x08003682:  7008         STRB       R0, [R1]
+  0x08003684:  4875         LDR        R0, =onTimeCounterRT     ; [PC, #0x01D4] [0x0800385C] =0x2000069C 
+  0x08003686:  21C8         MOVS       R1, #200
+  0x08003688:  6001         STR        R1, [R0]
+  0x0800368A:  4887         LDR        R0, =0x080068F4          ; [PC, #0x021C] [0x080038A8] 
+  0x0800368C:  F001 FD64    BL         puts                     ; 0x08005158
+  0x08003690:  4886         LDR        R0, =0x08006618          ; [PC, #0x0218] [0x080038AC] 
+  0x08003692:  F001 FD61    BL         puts                     ; 0x08005158
+  0x08003696:  7026         STRB       R6, [R4]
+
.L199:
+  0x08003698:  4885         LDR        R0, =temp                ; [PC, #0x0214] [0x080038B0] =0x20000690 
+  0x0800369A:  6800         LDR        R0, [R0]
+  0x0800369C:  2851         CMP        R0, #81
+  0x0800369E:  DB32         BLT        .L200                    ; 0x08003706
+  0x080036A0:  4A62         LDR        R2, =0x50000410          ; [PC, #0x0188] [0x0800382C] 
+  0x080036A2:  981A         LDR        R0, [SP, #104]
+  0x080036A4:  6190         STR        R0, [R2, #24]
+  0x080036A6:  9819         LDR        R0, [SP, #100]
+  0x080036A8:  6090         STR        R0, [R2, #8]
+  0x080036AA:  4961         LDR        R1, =relaisState         ; [PC, #0x0184] [0x08003830] =0x20000730 
+  0x080036AC:  2000         MOVS       R0, #0
+  0x080036AE:  7008         STRB       R0, [R1]
+  0x080036B0:  4960         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0180] [0x08003834] =0x200006A0 
+  0x080036B2:  9B15         LDR        R3, [SP, #84]
+  0x080036B4:  600B         STR        R3, [R1]
+  0x080036B6:  9920         LDR        R1, [SP, #128]
+  0x080036B8:  6091         STR        R1, [R2, #8]
+  0x080036BA:  9910         LDR        R1, [SP, #64]
+  0x080036BC:  31F4         ADDS       R1, #244
+  0x080036BE:  4A60         LDR        R2, =onTimeCounter       ; [PC, #0x0180] [0x08003840] =0x200006A8 
+  0x080036C0:  6011         STR        R1, [R2]
+  0x080036C2:  4B60         LDR        R3, =0x50000818          ; [PC, #0x0180] [0x08003844] 
+  0x080036C4:  991F         LDR        R1, [SP, #124]
+  0x080036C6:  6119         STR        R1, [R3, #16]
+  0x080036C8:  495F         LDR        R1, =offTimeCounterGN    ; [PC, #0x017C] [0x08003848] =0x200006B4 
+  0x080036CA:  6008         STR        R0, [R1]
+  0x080036CC:  495F         LDR        R1, =blinkModeGN         ; [PC, #0x017C] [0x0800384C] =0x20000758 
+  0x080036CE:  7008         STRB       R0, [R1]
+  0x080036D0:  495F         LDR        R1, =onTimeCounterGN     ; [PC, #0x017C] [0x08003850] =0x200006A4 
+  0x080036D2:  6008         STR        R0, [R1]
+  0x080036D4:  4969         LDR        R1, =onTimeRT            ; [PC, #0x01A4] [0x0800387C] =0x2000073C 
+  0x080036D6:  700D         STRB       R5, [R1]
+  0x080036D8:  4969         LDR        R1, =offTimeRT           ; [PC, #0x01A4] [0x08003880] =0x20000748 
+  0x080036DA:  700D         STRB       R5, [R1]
+  0x080036DC:  495E         LDR        R1, =blinkModeRT         ; [PC, #0x0178] [0x08003858] =0x20000754 
+  0x080036DE:  700D         STRB       R5, [R1]
+  0x080036E0:  4968         LDR        R1, =numberOfBlinks      ; [PC, #0x01A0] [0x08003884] =0x200006BC 
+  0x080036E2:  2205         MOVS       R2, #5
+  0x080036E4:  600A         STR        R2, [R1]
+  0x080036E6:  4968         LDR        R1, =blinkCounter        ; [PC, #0x01A0] [0x08003888] =0x200006EC 
+  0x080036E8:  600A         STR        R2, [R1]
+  0x080036EA:  4968         LDR        R1, =pauseTime           ; [PC, #0x01A0] [0x0800388C] =0x20000734 
+  0x080036EC:  700D         STRB       R5, [R1]
+  0x080036EE:  991E         LDR        R1, [SP, #120]
+  0x080036F0:  6019         STR        R1, [R3]
+  0x080036F2:  494D         LDR        R1, =buttonState         ; [PC, #0x0134] [0x08003828] =0x2000073A 
+  0x080036F4:  7008         STRB       R0, [R1]
+  0x080036F6:  4859         LDR        R0, =onTimeCounterRT     ; [PC, #0x0164] [0x0800385C] =0x2000069C 
+  0x080036F8:  21C8         MOVS       R1, #200
+  0x080036FA:  6001         STR        R1, [R0]
+  0x080036FC:  486D         LDR        R0, =0x08006294          ; [PC, #0x01B4] [0x080038B4] 
+  0x080036FE:  F001 FD2B    BL         puts                     ; 0x08005158
+  0x08003702:  2003         MOVS       R0, #3
+  0x08003704:  7020         STRB       R0, [R4]
+
.L200:
+  0x08003706:  4E67         LDR        R6, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x019C] [0x080038A4] =0x20000768 
+  0x08003708:  4B49         LDR        R3, =relaisState         ; [PC, #0x0124] [0x08003830] =0x20000730 
+  0x0800370A:  7830         LDRB       R0, [R6]
+  0x0800370C:  2801         CMP        R0, #1
+  0x0800370E:  7818         LDRB       R0, [R3]
+  0x08003710:  D137         BNE        .L201                    ; 0x08003782
+  0x08003712:  2800         CMP        R0, #0
+  0x08003714:  D05C         BEQ        .L202                    ; 0x080037D0
+  0x08003716:  4A45         LDR        R2, =0x50000410          ; [PC, #0x0114] [0x0800382C] 
+  0x08003718:  981A         LDR        R0, [SP, #104]
+  0x0800371A:  6190         STR        R0, [R2, #24]
+  0x0800371C:  9819         LDR        R0, [SP, #100]
+  0x0800371E:  6090         STR        R0, [R2, #8]
+  0x08003720:  2000         MOVS       R0, #0
+  0x08003722:  7018         STRB       R0, [R3]
+  0x08003724:  4943         LDR        R1, =onTimeCounterRESET  ; [PC, #0x010C] [0x08003834] =0x200006A0 
+  0x08003726:  9B15         LDR        R3, [SP, #84]
+  0x08003728:  600B         STR        R3, [R1]
+  0x0800372A:  9920         LDR        R1, [SP, #128]
+  0x0800372C:  6091         STR        R1, [R2, #8]
+  0x0800372E:  9910         LDR        R1, [SP, #64]
+  0x08003730:  31F4         ADDS       R1, #244
+  0x08003732:  4A43         LDR        R2, =onTimeCounter       ; [PC, #0x010C] [0x08003840] =0x200006A8 
+  0x08003734:  6011         STR        R1, [R2]
+  0x08003736:  4A43         LDR        R2, =0x50000818          ; [PC, #0x010C] [0x08003844] 
+  0x08003738:  991F         LDR        R1, [SP, #124]
+  0x0800373A:  6111         STR        R1, [R2, #16]
+  0x0800373C:  4942         LDR        R1, =offTimeCounterGN    ; [PC, #0x0108] [0x08003848] =0x200006B4 
+  0x0800373E:  6008         STR        R0, [R1]
+  0x08003740:  4942         LDR        R1, =blinkModeGN         ; [PC, #0x0108] [0x0800384C] =0x20000758 
+  0x08003742:  7008         STRB       R0, [R1]
+  0x08003744:  4942         LDR        R1, =onTimeCounterGN     ; [PC, #0x0108] [0x08003850] =0x200006A4 
+  0x08003746:  6008         STR        R0, [R1]
+  0x08003748:  484C         LDR        R0, =onTimeRT            ; [PC, #0x0130] [0x0800387C] =0x2000073C 
+  0x0800374A:  7005         STRB       R5, [R0]
+  0x0800374C:  484C         LDR        R0, =offTimeRT           ; [PC, #0x0130] [0x08003880] =0x20000748 
+  0x0800374E:  7005         STRB       R5, [R0]
+  0x08003750:  4841         LDR        R0, =blinkModeRT         ; [PC, #0x0104] [0x08003858] =0x20000754 
+  0x08003752:  7005         STRB       R5, [R0]
+  0x08003754:  484B         LDR        R0, =numberOfBlinks      ; [PC, #0x012C] [0x08003884] =0x200006BC 
+  0x08003756:  2102         MOVS       R1, #2
+  0x08003758:  6001         STR        R1, [R0]
+  0x0800375A:  484B         LDR        R0, =blinkCounter        ; [PC, #0x012C] [0x08003888] =0x200006EC 
+  0x0800375C:  6001         STR        R1, [R0]
+  0x0800375E:  484B         LDR        R0, =pauseTime           ; [PC, #0x012C] [0x0800388C] =0x20000734 
+  0x08003760:  7005         STRB       R5, [R0]
+  0x08003762:  981E         LDR        R0, [SP, #120]
+  0x08003764:  6010         STR        R0, [R2]
+  0x08003766:  483D         LDR        R0, =onTimeCounterRT     ; [PC, #244] [0x0800385C] =0x2000069C 
+  0x08003768:  21C8         MOVS       R1, #200
+  0x0800376A:  6001         STR        R1, [R0]
+  0x0800376C:  4852         LDR        R0, =0x08006854          ; [PC, #0x0148] [0x080038B8] 
+  0x0800376E:  F001 FCF3    BL         puts                     ; 0x08005158
+  0x08003772:  4852         LDR        R0, =0x080061FD          ; [PC, #0x0148] [0x080038BC] 
+  0x08003774:  F001 FCF0    BL         puts                     ; 0x08005158
+  0x08003778:  4B2D         LDR        R3, =relaisState         ; [PC, #180] [0x08003830] =0x20000730 
+  0x0800377A:  7830         LDRB       R0, [R6]
+  0x0800377C:  2800         CMP        R0, #0
+  0x0800377E:  D127         BNE        .L202                    ; 0x080037D0
+  0x08003780:  7818         LDRB       R0, [R3]
+
.L201:
+  0x08003782:  2800         CMP        R0, #0
+  0x08003784:  D124         BNE        .L202                    ; 0x080037D0
+  0x08003786:  4929         LDR        R1, =0x50000410          ; [PC, #164] [0x0800382C] 
+  0x08003788:  9819         LDR        R0, [SP, #100]
+  0x0800378A:  6188         STR        R0, [R1, #24]
+  0x0800378C:  981A         LDR        R0, [SP, #104]
+  0x0800378E:  6088         STR        R0, [R1, #8]
+  0x08003790:  701D         STRB       R5, [R3]
+  0x08003792:  4834         LDR        R0, =onTimeCounterSET    ; [PC, #208] [0x08003864] =0x20000698 
+  0x08003794:  9A15         LDR        R2, [SP, #84]
+  0x08003796:  6002         STR        R2, [R0]
+  0x08003798:  9820         LDR        R0, [SP, #128]
+  0x0800379A:  6088         STR        R0, [R1, #8]
+  0x0800379C:  4828         LDR        R0, =onTimeCounter       ; [PC, #160] [0x08003840] =0x200006A8 
+  0x0800379E:  21C8         MOVS       R1, #200
+  0x080037A0:  6001         STR        R1, [R0]
+  0x080037A2:  4B28         LDR        R3, =0x50000818          ; [PC, #160] [0x08003844] 
+  0x080037A4:  9E1F         LDR        R6, [SP, #124]
+  0x080037A6:  611E         STR        R6, [R3, #16]
+  0x080037A8:  482F         LDR        R0, =onTimeGN            ; [PC, #188] [0x08003868] =0x20000740 
+  0x080037AA:  7005         STRB       R5, [R0]
+  0x080037AC:  4826         LDR        R0, =offTimeCounterGN    ; [PC, #152] [0x08003848] =0x200006B4 
+  0x080037AE:  2200         MOVS       R2, #0
+  0x080037B0:  6002         STR        R2, [R0]
+  0x080037B2:  482E         LDR        R0, =offTimeGN           ; [PC, #184] [0x0800386C] =0x2000074C 
+  0x080037B4:  7005         STRB       R5, [R0]
+  0x080037B6:  4825         LDR        R0, =blinkModeGN         ; [PC, #148] [0x0800384C] =0x20000758 
+  0x080037B8:  7005         STRB       R5, [R0]
+  0x080037BA:  601E         STR        R6, [R3]
+  0x080037BC:  4E39         LDR        R6, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #228] [0x080038A4] =0x20000768 
+  0x080037BE:  4824         LDR        R0, =onTimeCounterGN     ; [PC, #144] [0x08003850] =0x200006A4 
+  0x080037C0:  6001         STR        R1, [R0]
+  0x080037C2:  483F         LDR        R0, =0x08006864          ; [PC, #252] [0x080038C0] 
+  0x080037C4:  F001 FCC8    BL         puts                     ; 0x08005158
+  0x080037C8:  483E         LDR        R0, =0x08006405          ; [PC, #248] [0x080038C4] 
+  0x080037CA:  F001 FCC5    BL         puts                     ; 0x08005158
+  0x080037CE:  4B18         LDR        R3, =relaisState         ; [PC, #96] [0x08003830] =0x20000730 
+
.L202:
+  0x080037D0:  4815         LDR        R0, =buttonState         ; [PC, #84] [0x08003828] =0x2000073A 
+  0x080037D2:  7800         LDRB       R0, [R0]
+  0x080037D4:  2800         CMP        R0, #0
+  0x080037D6:  D001         BEQ        .L203                    ; 0x080037DC
+  0x080037D8:  F000 FC78    BL         .L254                    ; 0x080040CC
+
.L203:
+  0x080037DC:  4913         LDR        R1, =0x50000410          ; [PC, #76] [0x0800382C] 
+  0x080037DE:  981A         LDR        R0, [SP, #104]
+  0x080037E0:  6188         STR        R0, [R1, #24]
+  0x080037E2:  9819         LDR        R0, [SP, #100]
+  0x080037E4:  6088         STR        R0, [R1, #8]
+  0x080037E6:  2700         MOVS       R7, #0
+  0x080037E8:  701F         STRB       R7, [R3]
+  0x080037EA:  4812         LDR        R0, =onTimeCounterRESET  ; [PC, #72] [0x08003834] =0x200006A0 
+  0x080037EC:  9A15         LDR        R2, [SP, #84]
+  0x080037EE:  6002         STR        R2, [R0]
+  0x080037F0:  9820         LDR        R0, [SP, #128]
+  0x080037F2:  6088         STR        R0, [R1, #8]
+  0x080037F4:  4812         LDR        R0, =onTimeCounter       ; [PC, #72] [0x08003840] =0x200006A8 
+  0x080037F6:  21C8         MOVS       R1, #200
+  0x080037F8:  6001         STR        R1, [R0]
+  0x080037FA:  4912         LDR        R1, =0x50000818          ; [PC, #72] [0x08003844] 
+  0x080037FC:  981F         LDR        R0, [SP, #124]
+  0x080037FE:  6108         STR        R0, [R1, #16]
+  0x08003800:  4811         LDR        R0, =offTimeCounterGN    ; [PC, #68] [0x08003848] =0x200006B4 
+  0x08003802:  6007         STR        R7, [R0]
+  0x08003804:  4811         LDR        R0, =blinkModeGN         ; [PC, #68] [0x0800384C] =0x20000758 
+  0x08003806:  7007         STRB       R7, [R0]
+  0x08003808:  4811         LDR        R0, =onTimeCounterGN     ; [PC, #68] [0x08003850] =0x200006A4 
+  0x0800380A:  6007         STR        R7, [R0]
+  0x0800380C:  981E         LDR        R0, [SP, #120]
+  0x0800380E:  6108         STR        R0, [R1, #16]
+  0x08003810:  4810         LDR        R0, =offTimeCounterRT    ; [PC, #64] [0x08003854] =0x200006B0 
+  0x08003812:  6007         STR        R7, [R0]
+  0x08003814:  4810         LDR        R0, =blinkModeRT         ; [PC, #64] [0x08003858] =0x20000754 
+  0x08003816:  7007         STRB       R7, [R0]
+  0x08003818:  4810         LDR        R0, =onTimeCounterRT     ; [PC, #64] [0x0800385C] =0x2000069C 
+  0x0800381A:  6007         STR        R7, [R0]
+  0x0800381C:  482A         LDR        R0, =0x08006224          ; [PC, #168] [0x080038C8] 
+  0x0800381E:  F001 FC9B    BL         puts                     ; 0x08005158
+  0x08003822:  7027         STRB       R7, [R4]
+  0x08003824:  481D         LDR        R0, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #116] [0x0800389C] =0x2000072C 
+  0x08003826:  E17A         B          .L214                    ; 0x08003B1E
+  0x08003828:  2000073A     DC.W       buttonState
+  0x0800382C:  50000410     DC.W       0x50000410
+  0x08003830:  20000730     DC.W       relaisState
+  0x08003834:  200006A0     DC.W       onTimeCounterRESET
+  0x08003838:  200006B8     DC.W       offTimeCounter
+  0x0800383C:  2000075C     DC.W       alarmMode
+  0x08003840:  200006A8     DC.W       onTimeCounter
+  0x08003844:  50000818     DC.W       0x50000818
+  0x08003848:  200006B4     DC.W       offTimeCounterGN
+  0x0800384C:  20000758     DC.W       blinkModeGN
+  0x08003850:  200006A4     DC.W       onTimeCounterGN
+  0x08003854:  200006B0     DC.W       offTimeCounterRT
+  0x08003858:  20000754     DC.W       blinkModeRT
+  0x0800385C:  2000069C     DC.W       onTimeCounterRT
+  0x08003860:  080061EA     DC.W       080061EA               ; R_ARM_ABS32
+  0x08003864:  20000698     DC.W       onTimeCounterSET
+  0x08003868:  20000740     DC.W       onTimeGN
+  0x0800386C:  2000074C     DC.W       offTimeGN
+  0x08003870:  0800642B     DC.W       0800642B               ; R_ARM_ABS32
+  0x08003874:  20000744     DC.W       onTime
+  0x08003878:  20000750     DC.W       offTime
+  0x0800387C:  2000073C     DC.W       onTimeRT
+  0x08003880:  20000748     DC.W       offTimeRT
+  0x08003884:  200006BC     DC.W       numberOfBlinks
+  0x08003888:  200006EC     DC.W       blinkCounter
+  0x0800388C:  20000734     DC.W       pauseTime
+  0x08003890:  50000010     DC.W       0x50000010
+  0x08003894:  20000728     DC.W       LVP_OVP_SM_On.oldtime
+  0x08003898:  2000068C     DC.W       uwTick
+  0x0800389C:  2000072C     DC.W       LVP_OVP_SM_On.lvpAndOvpInputTimeCounter
+  0x080038A0:  00001388     DC.W       0x00001388
+  0x080038A4:  20000768     DC.W       LVP_OVP_SM_On.lvpOROvpInput
+  0x080038A8:  080068F4     DC.W       080068F4               ; R_ARM_ABS32
+  0x080038AC:  08006618     DC.W       08006618               ; R_ARM_ABS32
+  0x080038B0:  20000690     DC.W       temp
+  0x080038B4:  08006294     DC.W       08006294               ; R_ARM_ABS32
+  0x080038B8:  08006854     DC.W       08006854               ; R_ARM_ABS32
+  0x080038BC:  080061FD     DC.W       080061FD               ; R_ARM_ABS32
+  0x080038C0:  08006864     DC.W       08006864               ; R_ARM_ABS32
+  0x080038C4:  08006405     DC.W       08006405               ; R_ARM_ABS32
+  0x080038C8:  08006224     DC.W       08006224               ; R_ARM_ABS32
+  0x080038CC:  48F7         LDR        R0, =0x50000410          ; [PC, #0x03DC] [0x08003CAC] 
+  0x080038CE:  6800         LDR        R0, [R0]
+  0x080038D0:  49F7         LDR        R1, =0x50000010          ; [PC, #0x03DC] [0x08003CB0] 
+  0x080038D2:  6809         LDR        R1, [R1]
+  0x080038D4:  07C9         LSLS       R1, R1, #31
+  0x080038D6:  D103         BNE        .L204                    ; 0x080038E0
+  0x080038D8:  49F5         LDR        R1, =0x50000010          ; [PC, #0x03D4] [0x08003CB0] 
+  0x080038DA:  6809         LDR        R1, [R1]
+  0x080038DC:  0789         LSLS       R1, R1, #30
+  0x080038DE:  D517         BPL        .L207                    ; 0x08003910
+
.L204:
+  0x080038E0:  49F4         LDR        R1, =LVP_SM_On.oldtime   ; [PC, #0x03D0] [0x08003CB4] =0x20000720 
+  0x080038E2:  680A         LDR        R2, [R1]
+  0x080038E4:  4BF4         LDR        R3, =uwTick              ; [PC, #0x03D0] [0x08003CB8] =0x2000068C 
+  0x080038E6:  681B         LDR        R3, [R3]
+  0x080038E8:  4293         CMP        R3, R2
+  0x080038EA:  D011         BEQ        .L207                    ; 0x08003910
+  0x080038EC:  4AF3         LDR        R2, =LVP_SM_On.lvpTimeCounter ; [PC, #0x03CC] [0x08003CBC] =0x20000724 
+  0x080038EE:  6813         LDR        R3, [R2]
+  0x080038F0:  4EF3         LDR        R6, =0x00001388          ; [PC, #0x03CC] [0x08003CC0] 
+  0x080038F2:  42B3         CMP        R3, R6
+  0x080038F4:  DA05         BGE        .L205                    ; 0x08003902
+  0x080038F6:  1C5E         ADDS       R6, R3, #1
+  0x080038F8:  6016         STR        R6, [R2]
+  0x080038FA:  4EF1         LDR        R6, =0x00001388          ; [PC, #0x03C4] [0x08003CC0] 
+  0x080038FC:  1E76         SUBS       R6, R6, #1
+  0x080038FE:  42B3         CMP        R3, R6
+  0x08003900:  D103         BNE        .L206                    ; 0x0800390A
+
.L205:
+  0x08003902:  2300         MOVS       R3, #0
+  0x08003904:  6013         STR        R3, [R2]
+  0x08003906:  4AEF         LDR        R2, =LVP_SM_On.lvpInput  ; [PC, #0x03BC] [0x08003CC4] =0x20000764 
+  0x08003908:  7015         STRB       R5, [R2]
+
.L206:
+  0x0800390A:  4AEB         LDR        R2, =uwTick              ; [PC, #0x03AC] [0x08003CB8] =0x2000068C 
+  0x0800390C:  6812         LDR        R2, [R2]
+  0x0800390E:  600A         STR        R2, [R1]
+
.L207:
+  0x08003910:  49E7         LDR        R1, =0x50000010          ; [PC, #0x039C] [0x08003CB0] 
+  0x08003912:  6809         LDR        R1, [R1]
+  0x08003914:  07C9         LSLS       R1, R1, #31
+  0x08003916:  D104         BNE        .L208                    ; 0x08003922
+  0x08003918:  49E8         LDR        R1, =LVP_SM_On.lvpTimeCounter ; [PC, #0x03A0] [0x08003CBC] =0x20000724 
+  0x0800391A:  2200         MOVS       R2, #0
+  0x0800391C:  600A         STR        R2, [R1]
+  0x0800391E:  49E9         LDR        R1, =LVP_SM_On.lvpInput  ; [PC, #0x03A4] [0x08003CC4] =0x20000764 
+  0x08003920:  700A         STRB       R2, [R1]
+
.L208:
+  0x08003922:  990E         LDR        R1, [SP, #56]
+  0x08003924:  4008         ANDS       R0, R1
+  0x08003926:  D134         BNE        .L209                    ; 0x08003992
+  0x08003928:  4AE0         LDR        R2, =0x50000410          ; [PC, #0x0380] [0x08003CAC] 
+  0x0800392A:  981A         LDR        R0, [SP, #104]
+  0x0800392C:  6190         STR        R0, [R2, #24]
+  0x0800392E:  9819         LDR        R0, [SP, #100]
+  0x08003930:  6090         STR        R0, [R2, #8]
+  0x08003932:  49E5         LDR        R1, =relaisState         ; [PC, #0x0394] [0x08003CC8] =0x20000730 
+  0x08003934:  2000         MOVS       R0, #0
+  0x08003936:  7008         STRB       R0, [R1]
+  0x08003938:  49E4         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0390] [0x08003CCC] =0x200006A0 
+  0x0800393A:  9B15         LDR        R3, [SP, #84]
+  0x0800393C:  600B         STR        R3, [R1]
+  0x0800393E:  9920         LDR        R1, [SP, #128]
+  0x08003940:  6091         STR        R1, [R2, #8]
+  0x08003942:  9910         LDR        R1, [SP, #64]
+  0x08003944:  31F4         ADDS       R1, #244
+  0x08003946:  4AE2         LDR        R2, =onTimeCounter       ; [PC, #0x0388] [0x08003CD0] =0x200006A8 
+  0x08003948:  6011         STR        R1, [R2]
+  0x0800394A:  4AE2         LDR        R2, =0x50000818          ; [PC, #0x0388] [0x08003CD4] 
+  0x0800394C:  991F         LDR        R1, [SP, #124]
+  0x0800394E:  6111         STR        R1, [R2, #16]
+  0x08003950:  49E1         LDR        R1, =offTimeCounterGN    ; [PC, #0x0384] [0x08003CD8] =0x200006B4 
+  0x08003952:  6008         STR        R0, [R1]
+  0x08003954:  49E1         LDR        R1, =blinkModeGN         ; [PC, #0x0384] [0x08003CDC] =0x20000758 
+  0x08003956:  7008         STRB       R0, [R1]
+  0x08003958:  49E1         LDR        R1, =onTimeCounterGN     ; [PC, #0x0384] [0x08003CE0] =0x200006A4 
+  0x0800395A:  6008         STR        R0, [R1]
+  0x0800395C:  49E1         LDR        R1, =onTimeRT            ; [PC, #0x0384] [0x08003CE4] =0x2000073C 
+  0x0800395E:  700D         STRB       R5, [R1]
+  0x08003960:  49E1         LDR        R1, =offTimeRT           ; [PC, #0x0384] [0x08003CE8] =0x20000748 
+  0x08003962:  700D         STRB       R5, [R1]
+  0x08003964:  49E1         LDR        R1, =blinkModeRT         ; [PC, #0x0384] [0x08003CEC] =0x20000754 
+  0x08003966:  700D         STRB       R5, [R1]
+  0x08003968:  49E1         LDR        R1, =numberOfBlinks      ; [PC, #0x0384] [0x08003CF0] =0x200006BC 
+  0x0800396A:  2603         MOVS       R6, #3
+  0x0800396C:  600E         STR        R6, [R1]
+  0x0800396E:  49E1         LDR        R1, =blinkCounter        ; [PC, #0x0384] [0x08003CF4] =0x200006EC 
+  0x08003970:  600E         STR        R6, [R1]
+  0x08003972:  49E1         LDR        R1, =pauseTime           ; [PC, #0x0384] [0x08003CF8] =0x20000734 
+  0x08003974:  700D         STRB       R5, [R1]
+  0x08003976:  991E         LDR        R1, [SP, #120]
+  0x08003978:  6011         STR        R1, [R2]
+  0x0800397A:  49E0         LDR        R1, =buttonState         ; [PC, #0x0380] [0x08003CFC] =0x2000073A 
+  0x0800397C:  7008         STRB       R0, [R1]
+  0x0800397E:  48E0         LDR        R0, =onTimeCounterRT     ; [PC, #0x0380] [0x08003D00] =0x2000069C 
+  0x08003980:  21C8         MOVS       R1, #200
+  0x08003982:  6001         STR        R1, [R0]
+  0x08003984:  48DF         LDR        R0, =0x080068F4          ; [PC, #0x037C] [0x08003D04] 
+  0x08003986:  F001 FBE7    BL         puts                     ; 0x08005158
+  0x0800398A:  48DF         LDR        R0, =0x080065AC          ; [PC, #0x037C] [0x08003D08] 
+  0x0800398C:  F001 FBE4    BL         puts                     ; 0x08005158
+  0x08003990:  7026         STRB       R6, [R4]
+
.L209:
+  0x08003992:  48DE         LDR        R0, =temp                ; [PC, #0x0378] [0x08003D0C] =0x20000690 
+  0x08003994:  6800         LDR        R0, [R0]
+  0x08003996:  2851         CMP        R0, #81
+  0x08003998:  DB32         BLT        .L210                    ; 0x08003A00
+  0x0800399A:  4AC4         LDR        R2, =0x50000410          ; [PC, #0x0310] [0x08003CAC] 
+  0x0800399C:  981A         LDR        R0, [SP, #104]
+  0x0800399E:  6190         STR        R0, [R2, #24]
+  0x080039A0:  9819         LDR        R0, [SP, #100]
+  0x080039A2:  6090         STR        R0, [R2, #8]
+  0x080039A4:  49C8         LDR        R1, =relaisState         ; [PC, #0x0320] [0x08003CC8] =0x20000730 
+  0x080039A6:  2000         MOVS       R0, #0
+  0x080039A8:  7008         STRB       R0, [R1]
+  0x080039AA:  49C8         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0320] [0x08003CCC] =0x200006A0 
+  0x080039AC:  9B15         LDR        R3, [SP, #84]
+  0x080039AE:  600B         STR        R3, [R1]
+  0x080039B0:  9920         LDR        R1, [SP, #128]
+  0x080039B2:  6091         STR        R1, [R2, #8]
+  0x080039B4:  9910         LDR        R1, [SP, #64]
+  0x080039B6:  31F4         ADDS       R1, #244
+  0x080039B8:  4AC5         LDR        R2, =onTimeCounter       ; [PC, #0x0314] [0x08003CD0] =0x200006A8 
+  0x080039BA:  6011         STR        R1, [R2]
+  0x080039BC:  4BC5         LDR        R3, =0x50000818          ; [PC, #0x0314] [0x08003CD4] 
+  0x080039BE:  991F         LDR        R1, [SP, #124]
+  0x080039C0:  6119         STR        R1, [R3, #16]
+  0x080039C2:  49C5         LDR        R1, =offTimeCounterGN    ; [PC, #0x0314] [0x08003CD8] =0x200006B4 
+  0x080039C4:  6008         STR        R0, [R1]
+  0x080039C6:  49C5         LDR        R1, =blinkModeGN         ; [PC, #0x0314] [0x08003CDC] =0x20000758 
+  0x080039C8:  7008         STRB       R0, [R1]
+  0x080039CA:  49C5         LDR        R1, =onTimeCounterGN     ; [PC, #0x0314] [0x08003CE0] =0x200006A4 
+  0x080039CC:  6008         STR        R0, [R1]
+  0x080039CE:  49C5         LDR        R1, =onTimeRT            ; [PC, #0x0314] [0x08003CE4] =0x2000073C 
+  0x080039D0:  700D         STRB       R5, [R1]
+  0x080039D2:  49C5         LDR        R1, =offTimeRT           ; [PC, #0x0314] [0x08003CE8] =0x20000748 
+  0x080039D4:  700D         STRB       R5, [R1]
+  0x080039D6:  49C5         LDR        R1, =blinkModeRT         ; [PC, #0x0314] [0x08003CEC] =0x20000754 
+  0x080039D8:  700D         STRB       R5, [R1]
+  0x080039DA:  49C5         LDR        R1, =numberOfBlinks      ; [PC, #0x0314] [0x08003CF0] =0x200006BC 
+  0x080039DC:  2205         MOVS       R2, #5
+  0x080039DE:  600A         STR        R2, [R1]
+  0x080039E0:  49C4         LDR        R1, =blinkCounter        ; [PC, #0x0310] [0x08003CF4] =0x200006EC 
+  0x080039E2:  600A         STR        R2, [R1]
+  0x080039E4:  49C4         LDR        R1, =pauseTime           ; [PC, #0x0310] [0x08003CF8] =0x20000734 
+  0x080039E6:  700D         STRB       R5, [R1]
+  0x080039E8:  991E         LDR        R1, [SP, #120]
+  0x080039EA:  6019         STR        R1, [R3]
+  0x080039EC:  49C3         LDR        R1, =buttonState         ; [PC, #0x030C] [0x08003CFC] =0x2000073A 
+  0x080039EE:  7008         STRB       R0, [R1]
+  0x080039F0:  48C3         LDR        R0, =onTimeCounterRT     ; [PC, #0x030C] [0x08003D00] =0x2000069C 
+  0x080039F2:  21C8         MOVS       R1, #200
+  0x080039F4:  6001         STR        R1, [R0]
+  0x080039F6:  48C6         LDR        R0, =0x08006294          ; [PC, #0x0318] [0x08003D10] 
+  0x080039F8:  F001 FBAE    BL         puts                     ; 0x08005158
+  0x080039FC:  2003         MOVS       R0, #3
+  0x080039FE:  7020         STRB       R0, [R4]
+
.L210:
+  0x08003A00:  4EB0         LDR        R6, =LVP_SM_On.lvpInput  ; [PC, #0x02C0] [0x08003CC4] =0x20000764 
+  0x08003A02:  4BB1         LDR        R3, =relaisState         ; [PC, #0x02C4] [0x08003CC8] =0x20000730 
+  0x08003A04:  7830         LDRB       R0, [R6]
+  0x08003A06:  2801         CMP        R0, #1
+  0x08003A08:  7818         LDRB       R0, [R3]
+  0x08003A0A:  D137         BNE        .L211                    ; 0x08003A7C
+  0x08003A0C:  2800         CMP        R0, #0
+  0x08003A0E:  D05C         BEQ        .L212                    ; 0x08003ACA
+  0x08003A10:  4AA6         LDR        R2, =0x50000410          ; [PC, #0x0298] [0x08003CAC] 
+  0x08003A12:  981A         LDR        R0, [SP, #104]
+  0x08003A14:  6190         STR        R0, [R2, #24]
+  0x08003A16:  9819         LDR        R0, [SP, #100]
+  0x08003A18:  6090         STR        R0, [R2, #8]
+  0x08003A1A:  2000         MOVS       R0, #0
+  0x08003A1C:  7018         STRB       R0, [R3]
+  0x08003A1E:  49AB         LDR        R1, =onTimeCounterRESET  ; [PC, #0x02AC] [0x08003CCC] =0x200006A0 
+  0x08003A20:  9B15         LDR        R3, [SP, #84]
+  0x08003A22:  600B         STR        R3, [R1]
+  0x08003A24:  9920         LDR        R1, [SP, #128]
+  0x08003A26:  6091         STR        R1, [R2, #8]
+  0x08003A28:  9910         LDR        R1, [SP, #64]
+  0x08003A2A:  31F4         ADDS       R1, #244
+  0x08003A2C:  4AA8         LDR        R2, =onTimeCounter       ; [PC, #0x02A0] [0x08003CD0] =0x200006A8 
+  0x08003A2E:  6011         STR        R1, [R2]
+  0x08003A30:  4AA8         LDR        R2, =0x50000818          ; [PC, #0x02A0] [0x08003CD4] 
+  0x08003A32:  991F         LDR        R1, [SP, #124]
+  0x08003A34:  6111         STR        R1, [R2, #16]
+  0x08003A36:  49A8         LDR        R1, =offTimeCounterGN    ; [PC, #0x02A0] [0x08003CD8] =0x200006B4 
+  0x08003A38:  6008         STR        R0, [R1]
+  0x08003A3A:  49A8         LDR        R1, =blinkModeGN         ; [PC, #0x02A0] [0x08003CDC] =0x20000758 
+  0x08003A3C:  7008         STRB       R0, [R1]
+  0x08003A3E:  49A8         LDR        R1, =onTimeCounterGN     ; [PC, #0x02A0] [0x08003CE0] =0x200006A4 
+  0x08003A40:  6008         STR        R0, [R1]
+  0x08003A42:  48A8         LDR        R0, =onTimeRT            ; [PC, #0x02A0] [0x08003CE4] =0x2000073C 
+  0x08003A44:  7005         STRB       R5, [R0]
+  0x08003A46:  48A8         LDR        R0, =offTimeRT           ; [PC, #0x02A0] [0x08003CE8] =0x20000748 
+  0x08003A48:  7005         STRB       R5, [R0]
+  0x08003A4A:  48A8         LDR        R0, =blinkModeRT         ; [PC, #0x02A0] [0x08003CEC] =0x20000754 
+  0x08003A4C:  7005         STRB       R5, [R0]
+  0x08003A4E:  48A8         LDR        R0, =numberOfBlinks      ; [PC, #0x02A0] [0x08003CF0] =0x200006BC 
+  0x08003A50:  2102         MOVS       R1, #2
+  0x08003A52:  6001         STR        R1, [R0]
+  0x08003A54:  48A7         LDR        R0, =blinkCounter        ; [PC, #0x029C] [0x08003CF4] =0x200006EC 
+  0x08003A56:  6001         STR        R1, [R0]
+  0x08003A58:  48A7         LDR        R0, =pauseTime           ; [PC, #0x029C] [0x08003CF8] =0x20000734 
+  0x08003A5A:  7005         STRB       R5, [R0]
+  0x08003A5C:  981E         LDR        R0, [SP, #120]
+  0x08003A5E:  6010         STR        R0, [R2]
+  0x08003A60:  48A7         LDR        R0, =onTimeCounterRT     ; [PC, #0x029C] [0x08003D00] =0x2000069C 
+  0x08003A62:  21C8         MOVS       R1, #200
+  0x08003A64:  6001         STR        R1, [R0]
+  0x08003A66:  48AB         LDR        R0, =0x080065C1          ; [PC, #0x02AC] [0x08003D14] 
+  0x08003A68:  F001 FB76    BL         puts                     ; 0x08005158
+  0x08003A6C:  48AA         LDR        R0, =0x080061C7          ; [PC, #0x02A8] [0x08003D18] 
+  0x08003A6E:  F001 FB73    BL         puts                     ; 0x08005158
+  0x08003A72:  4B95         LDR        R3, =relaisState         ; [PC, #0x0254] [0x08003CC8] =0x20000730 
+  0x08003A74:  7830         LDRB       R0, [R6]
+  0x08003A76:  2800         CMP        R0, #0
+  0x08003A78:  D127         BNE        .L212                    ; 0x08003ACA
+  0x08003A7A:  7818         LDRB       R0, [R3]
+
.L211:
+  0x08003A7C:  2800         CMP        R0, #0
+  0x08003A7E:  D124         BNE        .L212                    ; 0x08003ACA
+  0x08003A80:  498A         LDR        R1, =0x50000410          ; [PC, #0x0228] [0x08003CAC] 
+  0x08003A82:  9819         LDR        R0, [SP, #100]
+  0x08003A84:  6188         STR        R0, [R1, #24]
+  0x08003A86:  981A         LDR        R0, [SP, #104]
+  0x08003A88:  6088         STR        R0, [R1, #8]
+  0x08003A8A:  701D         STRB       R5, [R3]
+  0x08003A8C:  48A3         LDR        R0, =onTimeCounterSET    ; [PC, #0x028C] [0x08003D1C] =0x20000698 
+  0x08003A8E:  9A15         LDR        R2, [SP, #84]
+  0x08003A90:  6002         STR        R2, [R0]
+  0x08003A92:  9820         LDR        R0, [SP, #128]
+  0x08003A94:  6088         STR        R0, [R1, #8]
+  0x08003A96:  488E         LDR        R0, =onTimeCounter       ; [PC, #0x0238] [0x08003CD0] =0x200006A8 
+  0x08003A98:  21C8         MOVS       R1, #200
+  0x08003A9A:  6001         STR        R1, [R0]
+  0x08003A9C:  4B8D         LDR        R3, =0x50000818          ; [PC, #0x0234] [0x08003CD4] 
+  0x08003A9E:  9E1F         LDR        R6, [SP, #124]
+  0x08003AA0:  611E         STR        R6, [R3, #16]
+  0x08003AA2:  489F         LDR        R0, =onTimeGN            ; [PC, #0x027C] [0x08003D20] =0x20000740 
+  0x08003AA4:  7005         STRB       R5, [R0]
+  0x08003AA6:  488C         LDR        R0, =offTimeCounterGN    ; [PC, #0x0230] [0x08003CD8] =0x200006B4 
+  0x08003AA8:  2200         MOVS       R2, #0
+  0x08003AAA:  6002         STR        R2, [R0]
+  0x08003AAC:  489D         LDR        R0, =offTimeGN           ; [PC, #0x0274] [0x08003D24] =0x2000074C 
+  0x08003AAE:  7005         STRB       R5, [R0]
+  0x08003AB0:  488A         LDR        R0, =blinkModeGN         ; [PC, #0x0228] [0x08003CDC] =0x20000758 
+  0x08003AB2:  7005         STRB       R5, [R0]
+  0x08003AB4:  601E         STR        R6, [R3]
+  0x08003AB6:  4E83         LDR        R6, =LVP_SM_On.lvpInput  ; [PC, #0x020C] [0x08003CC4] =0x20000764 
+  0x08003AB8:  4889         LDR        R0, =onTimeCounterGN     ; [PC, #0x0224] [0x08003CE0] =0x200006A4 
+  0x08003ABA:  6001         STR        R1, [R0]
+  0x08003ABC:  489A         LDR        R0, =0x0800684C          ; [PC, #0x0268] [0x08003D28] 
+  0x08003ABE:  F001 FB4B    BL         puts                     ; 0x08005158
+  0x08003AC2:  489A         LDR        R0, =0x08006405          ; [PC, #0x0268] [0x08003D2C] 
+  0x08003AC4:  F001 FB48    BL         puts                     ; 0x08005158
+  0x08003AC8:  4B7F         LDR        R3, =relaisState         ; [PC, #0x01FC] [0x08003CC8] =0x20000730 
+
.L212:
+  0x08003ACA:  488C         LDR        R0, =buttonState         ; [PC, #0x0230] [0x08003CFC] =0x2000073A 
+  0x08003ACC:  7800         LDRB       R0, [R0]
+  0x08003ACE:  2800         CMP        R0, #0
+  0x08003AD0:  D000         BEQ        .L213                    ; 0x08003AD4
+  0x08003AD2:  E2FB         B          .L254                    ; 0x080040CC
+
.L213:
+  0x08003AD4:  4975         LDR        R1, =0x50000410          ; [PC, #0x01D4] [0x08003CAC] 
+  0x08003AD6:  981A         LDR        R0, [SP, #104]
+  0x08003AD8:  6188         STR        R0, [R1, #24]
+  0x08003ADA:  9819         LDR        R0, [SP, #100]
+  0x08003ADC:  6088         STR        R0, [R1, #8]
+  0x08003ADE:  2700         MOVS       R7, #0
+  0x08003AE0:  701F         STRB       R7, [R3]
+  0x08003AE2:  487A         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01E8] [0x08003CCC] =0x200006A0 
+  0x08003AE4:  9A15         LDR        R2, [SP, #84]
+  0x08003AE6:  6002         STR        R2, [R0]
+  0x08003AE8:  9820         LDR        R0, [SP, #128]
+  0x08003AEA:  6088         STR        R0, [R1, #8]
+  0x08003AEC:  4878         LDR        R0, =onTimeCounter       ; [PC, #0x01E0] [0x08003CD0] =0x200006A8 
+  0x08003AEE:  21C8         MOVS       R1, #200
+  0x08003AF0:  6001         STR        R1, [R0]
+  0x08003AF2:  4978         LDR        R1, =0x50000818          ; [PC, #0x01E0] [0x08003CD4] 
+  0x08003AF4:  981F         LDR        R0, [SP, #124]
+  0x08003AF6:  6108         STR        R0, [R1, #16]
+  0x08003AF8:  4877         LDR        R0, =offTimeCounterGN    ; [PC, #0x01DC] [0x08003CD8] =0x200006B4 
+  0x08003AFA:  6007         STR        R7, [R0]
+  0x08003AFC:  4877         LDR        R0, =blinkModeGN         ; [PC, #0x01DC] [0x08003CDC] =0x20000758 
+  0x08003AFE:  7007         STRB       R7, [R0]
+  0x08003B00:  4877         LDR        R0, =onTimeCounterGN     ; [PC, #0x01DC] [0x08003CE0] =0x200006A4 
+  0x08003B02:  6007         STR        R7, [R0]
+  0x08003B04:  981E         LDR        R0, [SP, #120]
+  0x08003B06:  6108         STR        R0, [R1, #16]
+  0x08003B08:  4889         LDR        R0, =offTimeCounterRT    ; [PC, #0x0224] [0x08003D30] =0x200006B0 
+  0x08003B0A:  6007         STR        R7, [R0]
+  0x08003B0C:  4877         LDR        R0, =blinkModeRT         ; [PC, #0x01DC] [0x08003CEC] =0x20000754 
+  0x08003B0E:  7007         STRB       R7, [R0]
+  0x08003B10:  487B         LDR        R0, =onTimeCounterRT     ; [PC, #0x01EC] [0x08003D00] =0x2000069C 
+  0x08003B12:  6007         STR        R7, [R0]
+  0x08003B14:  4887         LDR        R0, =0x080061EA          ; [PC, #0x021C] [0x08003D34] 
+  0x08003B16:  F001 FB1F    BL         puts                     ; 0x08005158
+  0x08003B1A:  7027         STRB       R7, [R4]
+  0x08003B1C:  4867         LDR        R0, =LVP_SM_On.lvpTimeCounter ; [PC, #0x019C] [0x08003CBC] =0x20000724 
+
.L214:
+  0x08003B1E:  6007         STR        R7, [R0]
+  0x08003B20:  7037         STRB       R7, [R6]
+  0x08003B22:  4F85         LDR        R7, =modbusData          ; [PC, #0x0214] [0x08003D38] =0x20000000 
+  0x08003B24:  E2D2         B          .L254                    ; 0x080040CC
+
.L215:
+  0x08003B26:  4985         LDR        R1, =sys_data            ; [PC, #0x0214] [0x08003D3C] =0x20000234 
+  0x08003B28:  8B09         LDRH       R1, [R1, #24]
+  0x08003B2A:  2B00         CMP        R3, #0
+  0x08003B2C:  4F82         LDR        R7, =modbusData          ; [PC, #0x0208] [0x08003D38] =0x20000000 
+  0x08003B2E:  D01B         BEQ        .L219                    ; 0x08003B68
+  0x08003B30:  4299         CMP        R1, R3
+  0x08003B32:  D019         BEQ        .L219                    ; 0x08003B68
+  0x08003B34:  2125         MOVS       R1, #37
+  0x08003B36:  00C9         LSLS       R1, R1, #3
+  0x08003B38:  4A81         LDR        R2, =0x00000B86          ; [PC, #0x0204] [0x08003D40] 
+  0x08003B3A:  E031         B          .L223                    ; 0x08003BA0
+
.L216:
+  0x08003B3C:  497F         LDR        R1, =sys_data            ; [PC, #0x01FC] [0x08003D3C] =0x20000234 
+  0x08003B3E:  8B09         LDRH       R1, [R1, #24]
+  0x08003B40:  2B00         CMP        R3, #0
+  0x08003B42:  D01E         BEQ        .L221                    ; 0x08003B82
+  0x08003B44:  4299         CMP        R1, R3
+  0x08003B46:  D01C         BEQ        .L221                    ; 0x08003B82
+  0x08003B48:  2125         MOVS       R1, #37
+  0x08003B4A:  00C9         LSLS       R1, R1, #3
+  0x08003B4C:  4A7C         LDR        R2, =0x00000B86          ; [PC, #0x01F0] [0x08003D40] 
+
.L217:
+  0x08003B4E:  4F7A         LDR        R7, =modbusData          ; [PC, #0x01E8] [0x08003D38] =0x20000000 
+  0x08003B50:  E026         B          .L223                    ; 0x08003BA0
+
.L218:
+  0x08003B52:  9912         LDR        R1, [SP, #72]
+  0x08003B54:  312A         ADDS       R1, #42
+  0x08003B56:  2301         MOVS       R3, #1
+  0x08003B58:  547B         STRB       R3, [R7, R1]
+  0x08003B5A:  990A         LDR        R1, [SP, #40]
+  0x08003B5C:  404A         EORS       R2, R1
+  0x08003B5E:  2125         MOVS       R1, #37
+  0x08003B60:  00C9         LSLS       R1, R1, #3
+  0x08003B62:  547A         STRB       R2, [R7, R1]
+  0x08003B64:  2603         MOVS       R6, #3
+  0x08003B66:  E3A0         B          .L271                    ; 0x080042AA
+
.L219:
+  0x08003B68:  212A         MOVS       R1, #42
+  0x08003B6A:  5C7A         LDRB       R2, [R7, R1]
+  0x08003B6C:  2129         MOVS       R1, #41
+  0x08003B6E:  5C79         LDRB       R1, [R7, R1]
+  0x08003B70:  0209         LSLS       R1, R1, #8
+  0x08003B72:  1889         ADDS       R1, R1, R2
+  0x08003B74:  2970         CMP        R1, #112
+  0x08003B76:  D200         BCS        .L220                    ; 0x08003B7A
+  0x08003B78:  E31D         B          .L262                    ; 0x080041B6
+
.L220:
+  0x08003B7A:  2125         MOVS       R1, #37
+  0x08003B7C:  00C9         LSLS       R1, R1, #3
+  0x08003B7E:  4A71         LDR        R2, =0x00000286          ; [PC, #0x01C4] [0x08003D44] 
+  0x08003B80:  E00E         B          .L223                    ; 0x08003BA0
+
.L221:
+  0x08003B82:  9908         LDR        R1, [SP, #32]
+  0x08003B84:  4F6C         LDR        R7, =modbusData          ; [PC, #0x01B0] [0x08003D38] =0x20000000 
+  0x08003B86:  5C79         LDRB       R1, [R7, R1]
+  0x08003B88:  222B         MOVS       R2, #43
+  0x08003B8A:  5CBA         LDRB       R2, [R7, R2]
+  0x08003B8C:  0212         LSLS       R2, R2, #8
+  0x08003B8E:  1856         ADDS       R6, R2, R1
+  0x08003B90:  D002         BEQ        .L222                    ; 0x08003B98
+  0x08003B92:  2E7C         CMP        R6, #124
+  0x08003B94:  D200         BCS        .L222                    ; 0x08003B98
+  0x08003B96:  E325         B          .L263                    ; 0x080041E4
+
.L222:
+  0x08003B98:  2125         MOVS       R1, #37
+  0x08003B9A:  00C9         LSLS       R1, R1, #3
+  0x08003B9C:  2239         MOVS       R2, #57
+  0x08003B9E:  0112         LSLS       R2, R2, #4
+
.L223:
+  0x08003BA0:  527A         STRH       R2, [R7, R1]
+  0x08003BA2:  2603         MOVS       R6, #3
+  0x08003BA4:  E381         B          .L271                    ; 0x080042AA
+
.L224:
+  0x08003BA6:  9A08         LDR        R2, [SP, #32]
+  0x08003BA8:  5CBE         LDRB       R6, [R7, R2]
+  0x08003BAA:  222B         MOVS       R2, #43
+  0x08003BAC:  5CBA         LDRB       R2, [R7, R2]
+  0x08003BAE:  0212         LSLS       R2, R2, #8
+  0x08003BB0:  1994         ADDS       R4, R2, R6
+  0x08003BB2:  2203         MOVS       R2, #3
+  0x08003BB4:  2383         MOVS       R3, #131
+  0x08003BB6:  2C00         CMP        R4, #0
+  0x08003BB8:  D013         BEQ        .L226                    ; 0x08003BE2
+  0x08003BBA:  2C7D         CMP        R4, #125
+  0x08003BBC:  D811         BHI        .L226                    ; 0x08003BE2
+  0x08003BBE:  9605         STR        R6, [SP, #20]
+  0x08003BC0:  222A         MOVS       R2, #42
+  0x08003BC2:  5CBE         LDRB       R6, [R7, R2]
+  0x08003BC4:  2229         MOVS       R2, #41
+  0x08003BC6:  5CBA         LDRB       R2, [R7, R2]
+  0x08003BC8:  9203         STR        R2, [SP, #12]
+  0x08003BCA:  0212         LSLS       R2, R2, #8
+  0x08003BCC:  9604         STR        R6, [SP, #16]
+  0x08003BCE:  1992         ADDS       R2, R2, R6
+  0x08003BD0:  18A4         ADDS       R4, R4, R2
+  0x08003BD2:  941B         STR        R4, [SP, #108]
+  0x08003BD4:  3C71         SUBS       R4, #113
+  0x08003BD6:  266F         MOVS       R6, #111
+  0x08003BD8:  43F6         MVNS       R6, R6
+  0x08003BDA:  42B4         CMP        R4, R6
+  0x08003BDC:  D300         BCC        .L225                    ; 0x08003BE0
+  0x08003BDE:  E341         B          .L267                    ; 0x08004264
+
.L225:
+  0x08003BE0:  2202         MOVS       R2, #2
+
.L226:
+  0x08003BE2:  9912         LDR        R1, [SP, #72]
+  0x08003BE4:  312A         ADDS       R1, #42
+  0x08003BE6:  547A         STRB       R2, [R7, R1]
+  0x08003BE8:  2125         MOVS       R1, #37
+  0x08003BEA:  00C9         LSLS       R1, R1, #3
+  0x08003BEC:  547B         STRB       R3, [R7, R1]
+  0x08003BEE:  2603         MOVS       R6, #3
+  0x08003BF0:  E35B         B          .L271                    ; 0x080042AA
+
.L227:
+  0x08003BF2:  492E         LDR        R1, =0x50000410          ; [PC, #184] [0x08003CAC] 
+  0x08003BF4:  9819         LDR        R0, [SP, #100]
+  0x08003BF6:  6188         STR        R0, [R1, #24]
+  0x08003BF8:  981A         LDR        R0, [SP, #104]
+  0x08003BFA:  6088         STR        R0, [R1, #8]
+  0x08003BFC:  4832         LDR        R0, =relaisState         ; [PC, #200] [0x08003CC8] =0x20000730 
+  0x08003BFE:  7005         STRB       R5, [R0]
+  0x08003C00:  4846         LDR        R0, =onTimeCounterSET    ; [PC, #0x0118] [0x08003D1C] =0x20000698 
+  0x08003C02:  9A15         LDR        R2, [SP, #84]
+  0x08003C04:  6002         STR        R2, [R0]
+  0x08003C06:  9820         LDR        R0, [SP, #128]
+  0x08003C08:  6088         STR        R0, [R1, #8]
+  0x08003C0A:  4845         LDR        R0, =onTimeGN            ; [PC, #0x0114] [0x08003D20] =0x20000740 
+  0x08003C0C:  7005         STRB       R5, [R0]
+  0x08003C0E:  4830         LDR        R0, =onTimeCounter       ; [PC, #192] [0x08003CD0] =0x200006A8 
+  0x08003C10:  21C8         MOVS       R1, #200
+  0x08003C12:  6001         STR        R1, [R0]
+  0x08003C14:  4843         LDR        R0, =offTimeGN           ; [PC, #0x010C] [0x08003D24] =0x2000074C 
+  0x08003C16:  7005         STRB       R5, [R0]
+  0x08003C18:  4830         LDR        R0, =blinkModeGN         ; [PC, #192] [0x08003CDC] =0x20000758 
+  0x08003C1A:  7005         STRB       R5, [R0]
+  0x08003C1C:  4A2D         LDR        R2, =0x50000818          ; [PC, #180] [0x08003CD4] 
+  0x08003C1E:  981F         LDR        R0, [SP, #124]
+  0x08003C20:  6010         STR        R0, [R2]
+  0x08003C22:  482F         LDR        R0, =onTimeCounterGN     ; [PC, #188] [0x08003CE0] =0x200006A4 
+  0x08003C24:  6001         STR        R1, [R0]
+  0x08003C26:  981E         LDR        R0, [SP, #120]
+  0x08003C28:  6110         STR        R0, [R2, #16]
+  0x08003C2A:  4841         LDR        R0, =offTimeCounterRT    ; [PC, #0x0104] [0x08003D30] =0x200006B0 
+  0x08003C2C:  2100         MOVS       R1, #0
+  0x08003C2E:  6001         STR        R1, [R0]
+  0x08003C30:  482E         LDR        R0, =blinkModeRT         ; [PC, #184] [0x08003CEC] =0x20000754 
+  0x08003C32:  7001         STRB       R1, [R0]
+  0x08003C34:  4832         LDR        R0, =onTimeCounterRT     ; [PC, #200] [0x08003D00] =0x2000069C 
+  0x08003C36:  6001         STR        R1, [R0]
+  0x08003C38:  4843         LDR        R0, =0x0800649F          ; [PC, #0x010C] [0x08003D48] 
+  0x08003C3A:  F001 FA8D    BL         puts                     ; 0x08005158
+  0x08003C3E:  7025         STRB       R5, [R4]
+  0x08003C40:  7830         LDRB       R0, [R6]
+
.L228:
+  0x08003C42:  2802         CMP        R0, #2
+  0x08003C44:  D000         BEQ        .L229                    ; 0x08003C48
+  0x08003C46:  E241         B          .L254                    ; 0x080040CC
+
.L229:
+  0x08003C48:  4918         LDR        R1, =0x50000410          ; [PC, #96] [0x08003CAC] 
+  0x08003C4A:  9819         LDR        R0, [SP, #100]
+  0x08003C4C:  6188         STR        R0, [R1, #24]
+  0x08003C4E:  981A         LDR        R0, [SP, #104]
+  0x08003C50:  6088         STR        R0, [R1, #8]
+  0x08003C52:  481D         LDR        R0, =relaisState         ; [PC, #116] [0x08003CC8] =0x20000730 
+  0x08003C54:  7005         STRB       R5, [R0]
+  0x08003C56:  4831         LDR        R0, =onTimeCounterSET    ; [PC, #196] [0x08003D1C] =0x20000698 
+  0x08003C58:  9A15         LDR        R2, [SP, #84]
+  0x08003C5A:  6002         STR        R2, [R0]
+  0x08003C5C:  483B         LDR        R0, =onTime              ; [PC, #236] [0x08003D4C] =0x20000744 
+  0x08003C5E:  7005         STRB       R5, [R0]
+  0x08003C60:  483B         LDR        R0, =offTime             ; [PC, #236] [0x08003D50] =0x20000750 
+  0x08003C62:  7005         STRB       R5, [R0]
+  0x08003C64:  483B         LDR        R0, =alarmMode           ; [PC, #236] [0x08003D54] =0x2000075C 
+  0x08003C66:  7005         STRB       R5, [R0]
+  0x08003C68:  9820         LDR        R0, [SP, #128]
+  0x08003C6A:  6088         STR        R0, [R1, #8]
+  0x08003C6C:  4918         LDR        R1, =onTimeCounter       ; [PC, #96] [0x08003CD0] =0x200006A8 
+  0x08003C6E:  20C8         MOVS       R0, #200
+  0x08003C70:  6008         STR        R0, [R1]
+  0x08003C72:  4B18         LDR        R3, =0x50000818          ; [PC, #96] [0x08003CD4] 
+  0x08003C74:  991F         LDR        R1, [SP, #124]
+  0x08003C76:  6019         STR        R1, [R3]
+  0x08003C78:  4919         LDR        R1, =onTimeCounterGN     ; [PC, #100] [0x08003CE0] =0x200006A4 
+  0x08003C7A:  2200         MOVS       R2, #0
+  0x08003C7C:  600A         STR        R2, [R1]
+  0x08003C7E:  4917         LDR        R1, =blinkModeGN         ; [PC, #92] [0x08003CDC] =0x20000758 
+  0x08003C80:  700A         STRB       R2, [R1]
+  0x08003C82:  4915         LDR        R1, =offTimeCounterGN    ; [PC, #84] [0x08003CD8] =0x200006B4 
+  0x08003C84:  600A         STR        R2, [R1]
+  0x08003C86:  9E1E         LDR        R6, [SP, #120]
+  0x08003C88:  611E         STR        R6, [R3, #16]
+  0x08003C8A:  4916         LDR        R1, =onTimeRT            ; [PC, #88] [0x08003CE4] =0x2000073C 
+  0x08003C8C:  700D         STRB       R5, [R1]
+  0x08003C8E:  4928         LDR        R1, =offTimeCounterRT    ; [PC, #160] [0x08003D30] =0x200006B0 
+  0x08003C90:  600A         STR        R2, [R1]
+  0x08003C92:  4915         LDR        R1, =offTimeRT           ; [PC, #84] [0x08003CE8] =0x20000748 
+  0x08003C94:  700D         STRB       R5, [R1]
+  0x08003C96:  4915         LDR        R1, =blinkModeRT         ; [PC, #84] [0x08003CEC] =0x20000754 
+  0x08003C98:  700D         STRB       R5, [R1]
+  0x08003C9A:  4915         LDR        R1, =numberOfBlinks      ; [PC, #84] [0x08003CF0] =0x200006BC 
+  0x08003C9C:  600D         STR        R5, [R1]
+  0x08003C9E:  4915         LDR        R1, =blinkCounter        ; [PC, #84] [0x08003CF4] =0x200006EC 
+  0x08003CA0:  600D         STR        R5, [R1]
+  0x08003CA2:  4915         LDR        R1, =pauseTime           ; [PC, #84] [0x08003CF8] =0x20000734 
+  0x08003CA4:  700D         STRB       R5, [R1]
+  0x08003CA6:  601E         STR        R6, [R3]
+  0x08003CA8:  E0A9         B          .L234                    ; 0x08003DFE
+  0x08003CAA:  46C0         NOP
+  0x08003CAC:  50000410     DC.W       0x50000410
+  0x08003CB0:  50000010     DC.W       0x50000010
+  0x08003CB4:  20000720     DC.W       LVP_SM_On.oldtime
+  0x08003CB8:  2000068C     DC.W       uwTick
+  0x08003CBC:  20000724     DC.W       LVP_SM_On.lvpTimeCounter
+  0x08003CC0:  00001388     DC.W       0x00001388
+  0x08003CC4:  20000764     DC.W       LVP_SM_On.lvpInput
+  0x08003CC8:  20000730     DC.W       relaisState
+  0x08003CCC:  200006A0     DC.W       onTimeCounterRESET
+  0x08003CD0:  200006A8     DC.W       onTimeCounter
+  0x08003CD4:  50000818     DC.W       0x50000818
+  0x08003CD8:  200006B4     DC.W       offTimeCounterGN
+  0x08003CDC:  20000758     DC.W       blinkModeGN
+  0x08003CE0:  200006A4     DC.W       onTimeCounterGN
+  0x08003CE4:  2000073C     DC.W       onTimeRT
+  0x08003CE8:  20000748     DC.W       offTimeRT
+  0x08003CEC:  20000754     DC.W       blinkModeRT
+  0x08003CF0:  200006BC     DC.W       numberOfBlinks
+  0x08003CF4:  200006EC     DC.W       blinkCounter
+  0x08003CF8:  20000734     DC.W       pauseTime
+  0x08003CFC:  2000073A     DC.W       buttonState
+  0x08003D00:  2000069C     DC.W       onTimeCounterRT
+  0x08003D04:  080068F4     DC.W       080068F4               ; R_ARM_ABS32
+  0x08003D08:  080065AC     DC.W       080065AC               ; R_ARM_ABS32
+  0x08003D0C:  20000690     DC.W       temp
+  0x08003D10:  08006294     DC.W       08006294               ; R_ARM_ABS32
+  0x08003D14:  080065C1     DC.W       080065C1               ; R_ARM_ABS32
+  0x08003D18:  080061C7     DC.W       080061C7               ; R_ARM_ABS32
+  0x08003D1C:  20000698     DC.W       onTimeCounterSET
+  0x08003D20:  20000740     DC.W       onTimeGN
+  0x08003D24:  2000074C     DC.W       offTimeGN
+  0x08003D28:  0800684C     DC.W       0800684C               ; R_ARM_ABS32
+  0x08003D2C:  08006405     DC.W       08006405               ; R_ARM_ABS32
+  0x08003D30:  200006B0     DC.W       offTimeCounterRT
+  0x08003D34:  080061EA     DC.W       080061EA               ; R_ARM_ABS32
+  0x08003D38:  20000000     DC.W       modbusData
+  0x08003D3C:  20000234     DC.W       sys_data
+  0x08003D40:  00000B86     DC.W       0x00000B86
+  0x08003D44:  00000286     DC.W       0x00000286
+  0x08003D48:  0800649F     DC.W       0800649F               ; R_ARM_ABS32
+  0x08003D4C:  20000744     DC.W       onTime
+  0x08003D50:  20000750     DC.W       offTime
+  0x08003D54:  2000075C     DC.W       alarmMode
+
.L230:
+  0x08003D58:  49EA         LDR        R1, =0x50000410          ; [PC, #0x03A8] [0x08004104] 
+  0x08003D5A:  9819         LDR        R0, [SP, #100]
+  0x08003D5C:  6188         STR        R0, [R1, #24]
+  0x08003D5E:  981A         LDR        R0, [SP, #104]
+  0x08003D60:  6088         STR        R0, [R1, #8]
+  0x08003D62:  48E9         LDR        R0, =relaisState         ; [PC, #0x03A4] [0x08004108] =0x20000730 
+  0x08003D64:  7005         STRB       R5, [R0]
+  0x08003D66:  48E9         LDR        R0, =onTimeCounterSET    ; [PC, #0x03A4] [0x0800410C] =0x20000698 
+  0x08003D68:  9A15         LDR        R2, [SP, #84]
+  0x08003D6A:  6002         STR        R2, [R0]
+  0x08003D6C:  9820         LDR        R0, [SP, #128]
+  0x08003D6E:  6088         STR        R0, [R1, #8]
+  0x08003D70:  48E7         LDR        R0, =offTimeGN           ; [PC, #0x039C] [0x08004110] =0x2000074C 
+  0x08003D72:  7005         STRB       R5, [R0]
+  0x08003D74:  48E7         LDR        R0, =onTimeGN            ; [PC, #0x039C] [0x08004114] =0x20000740 
+  0x08003D76:  7005         STRB       R5, [R0]
+  0x08003D78:  48E7         LDR        R0, =0x0800645B          ; [PC, #0x039C] [0x08004118] 
+  0x08003D7A:  49E8         LDR        R1, =onTimeCounterGN     ; [PC, #0x03A0] [0x0800411C] =0x200006A4 
+  0x08003D7C:  4BE8         LDR        R3, =blinkModeGN         ; [PC, #0x03A0] [0x08004120] =0x20000758 
+  0x08003D7E:  22C8         MOVS       R2, #200
+  0x08003D80:  9E1F         LDR        R6, [SP, #124]
+  0x08003D82:  462F         MOV        R7, R5
+
.L231:
+  0x08003D84:  701D         STRB       R5, [R3]
+  0x08003D86:  4BE7         LDR        R3, =onTimeCounter       ; [PC, #0x039C] [0x08004124] =0x200006A8 
+  0x08003D88:  601A         STR        R2, [R3]
+  0x08003D8A:  4AE7         LDR        R2, =0x50000818          ; [PC, #0x039C] [0x08004128] 
+  0x08003D8C:  6016         STR        R6, [R2]
+  0x08003D8E:  22C8         MOVS       R2, #200
+  0x08003D90:  600A         STR        R2, [R1]
+  0x08003D92:  F001 F9E1    BL         puts                     ; 0x08005158
+  0x08003D96:  7027         STRB       R7, [R4]
+  0x08003D98:  48E4         LDR        R0, =buttonState         ; [PC, #0x0390] [0x0800412C] =0x2000073A 
+  0x08003D9A:  7800         LDRB       R0, [R0]
+  0x08003D9C:  4FE4         LDR        R7, =modbusData          ; [PC, #0x0390] [0x08004130] =0x20000000 
+
.L232:
+  0x08003D9E:  2802         CMP        R0, #2
+  0x08003DA0:  D000         BEQ        .L233                    ; 0x08003DA4
+  0x08003DA2:  E193         B          .L254                    ; 0x080040CC
+
.L233:
+  0x08003DA4:  49D7         LDR        R1, =0x50000410          ; [PC, #0x035C] [0x08004104] 
+  0x08003DA6:  9819         LDR        R0, [SP, #100]
+  0x08003DA8:  6188         STR        R0, [R1, #24]
+  0x08003DAA:  981A         LDR        R0, [SP, #104]
+  0x08003DAC:  6088         STR        R0, [R1, #8]
+  0x08003DAE:  48D6         LDR        R0, =relaisState         ; [PC, #0x0358] [0x08004108] =0x20000730 
+  0x08003DB0:  7005         STRB       R5, [R0]
+  0x08003DB2:  48D6         LDR        R0, =onTimeCounterSET    ; [PC, #0x0358] [0x0800410C] =0x20000698 
+  0x08003DB4:  9A15         LDR        R2, [SP, #84]
+  0x08003DB6:  6002         STR        R2, [R0]
+  0x08003DB8:  48DE         LDR        R0, =onTime              ; [PC, #0x0378] [0x08004134] =0x20000744 
+  0x08003DBA:  7005         STRB       R5, [R0]
+  0x08003DBC:  48DE         LDR        R0, =offTime             ; [PC, #0x0378] [0x08004138] =0x20000750 
+  0x08003DBE:  7005         STRB       R5, [R0]
+  0x08003DC0:  48DE         LDR        R0, =alarmMode           ; [PC, #0x0378] [0x0800413C] =0x2000075C 
+  0x08003DC2:  7005         STRB       R5, [R0]
+  0x08003DC4:  9820         LDR        R0, [SP, #128]
+  0x08003DC6:  6088         STR        R0, [R1, #8]
+  0x08003DC8:  49D6         LDR        R1, =onTimeCounter       ; [PC, #0x0358] [0x08004124] =0x200006A8 
+  0x08003DCA:  20C8         MOVS       R0, #200
+  0x08003DCC:  6008         STR        R0, [R1]
+  0x08003DCE:  4BD6         LDR        R3, =0x50000818          ; [PC, #0x0358] [0x08004128] 
+  0x08003DD0:  991F         LDR        R1, [SP, #124]
+  0x08003DD2:  6019         STR        R1, [R3]
+  0x08003DD4:  49D1         LDR        R1, =onTimeCounterGN     ; [PC, #0x0344] [0x0800411C] =0x200006A4 
+  0x08003DD6:  2200         MOVS       R2, #0
+  0x08003DD8:  600A         STR        R2, [R1]
+  0x08003DDA:  49D1         LDR        R1, =blinkModeGN         ; [PC, #0x0344] [0x08004120] =0x20000758 
+  0x08003DDC:  700A         STRB       R2, [R1]
+  0x08003DDE:  49D8         LDR        R1, =offTimeCounterGN    ; [PC, #0x0360] [0x08004140] =0x200006B4 
+  0x08003DE0:  600A         STR        R2, [R1]
+  0x08003DE2:  49D8         LDR        R1, =onTimeRT            ; [PC, #0x0360] [0x08004144] =0x2000073C 
+  0x08003DE4:  700D         STRB       R5, [R1]
+  0x08003DE6:  49D8         LDR        R1, =offTimeRT           ; [PC, #0x0360] [0x08004148] =0x20000748 
+  0x08003DE8:  700D         STRB       R5, [R1]
+  0x08003DEA:  49D8         LDR        R1, =blinkModeRT         ; [PC, #0x0360] [0x0800414C] =0x20000754 
+  0x08003DEC:  700D         STRB       R5, [R1]
+  0x08003DEE:  49D8         LDR        R1, =numberOfBlinks      ; [PC, #0x0360] [0x08004150] =0x200006BC 
+  0x08003DF0:  600D         STR        R5, [R1]
+  0x08003DF2:  49D8         LDR        R1, =blinkCounter        ; [PC, #0x0360] [0x08004154] =0x200006EC 
+  0x08003DF4:  600D         STR        R5, [R1]
+  0x08003DF6:  49D8         LDR        R1, =pauseTime           ; [PC, #0x0360] [0x08004158] =0x20000734 
+  0x08003DF8:  700D         STRB       R5, [R1]
+  0x08003DFA:  991E         LDR        R1, [SP, #120]
+  0x08003DFC:  6019         STR        R1, [R3]
+
.L234:
+  0x08003DFE:  49D7         LDR        R1, =onTimeCounterRT     ; [PC, #0x035C] [0x0800415C] =0x2000069C 
+  0x08003E00:  6008         STR        R0, [R1]
+  0x08003E02:  48D7         LDR        R0, =0x080066B2          ; [PC, #0x035C] [0x08004160] 
+  0x08003E04:  E15E         B          .L252                    ; 0x080040C4
+
.L235:
+  0x08003E06:  49BF         LDR        R1, =0x50000410          ; [PC, #0x02FC] [0x08004104] 
+  0x08003E08:  9819         LDR        R0, [SP, #100]
+  0x08003E0A:  6188         STR        R0, [R1, #24]
+  0x08003E0C:  981A         LDR        R0, [SP, #104]
+  0x08003E0E:  6088         STR        R0, [R1, #8]
+  0x08003E10:  48BD         LDR        R0, =relaisState         ; [PC, #0x02F4] [0x08004108] =0x20000730 
+  0x08003E12:  7005         STRB       R5, [R0]
+  0x08003E14:  48BD         LDR        R0, =onTimeCounterSET    ; [PC, #0x02F4] [0x0800410C] =0x20000698 
+  0x08003E16:  9A15         LDR        R2, [SP, #84]
+  0x08003E18:  6002         STR        R2, [R0]
+  0x08003E1A:  9820         LDR        R0, [SP, #128]
+  0x08003E1C:  6088         STR        R0, [R1, #8]
+  0x08003E1E:  48BC         LDR        R0, =offTimeGN           ; [PC, #0x02F0] [0x08004110] =0x2000074C 
+  0x08003E20:  7005         STRB       R5, [R0]
+  0x08003E22:  48BC         LDR        R0, =onTimeGN            ; [PC, #0x02F0] [0x08004114] =0x20000740 
+  0x08003E24:  7005         STRB       R5, [R0]
+  0x08003E26:  48CF         LDR        R0, =0x0800664E          ; [PC, #0x033C] [0x08004164] 
+  0x08003E28:  49BC         LDR        R1, =onTimeCounterGN     ; [PC, #0x02F0] [0x0800411C] =0x200006A4 
+  0x08003E2A:  4BBD         LDR        R3, =blinkModeGN         ; [PC, #0x02F4] [0x08004120] =0x20000758 
+  0x08003E2C:  22C8         MOVS       R2, #200
+  0x08003E2E:  9E1F         LDR        R6, [SP, #124]
+  0x08003E30:  462F         MOV        R7, R5
+
.L236:
+  0x08003E32:  701D         STRB       R5, [R3]
+  0x08003E34:  4BBB         LDR        R3, =onTimeCounter       ; [PC, #0x02EC] [0x08004124] =0x200006A8 
+  0x08003E36:  601A         STR        R2, [R3]
+  0x08003E38:  4ABB         LDR        R2, =0x50000818          ; [PC, #0x02EC] [0x08004128] 
+  0x08003E3A:  6016         STR        R6, [R2]
+  0x08003E3C:  22C8         MOVS       R2, #200
+  0x08003E3E:  600A         STR        R2, [R1]
+  0x08003E40:  F001 F98A    BL         puts                     ; 0x08005158
+  0x08003E44:  7027         STRB       R7, [R4]
+  0x08003E46:  48B9         LDR        R0, =buttonState         ; [PC, #0x02E4] [0x0800412C] =0x2000073A 
+  0x08003E48:  7800         LDRB       R0, [R0]
+  0x08003E4A:  4FB9         LDR        R7, =modbusData          ; [PC, #0x02E4] [0x08004130] =0x20000000 
+
.L237:
+  0x08003E4C:  2802         CMP        R0, #2
+  0x08003E4E:  D000         BEQ        .L238                    ; 0x08003E52
+  0x08003E50:  E13C         B          .L254                    ; 0x080040CC
+
.L238:
+  0x08003E52:  49AC         LDR        R1, =0x50000410          ; [PC, #0x02B0] [0x08004104] 
+  0x08003E54:  9819         LDR        R0, [SP, #100]
+  0x08003E56:  6188         STR        R0, [R1, #24]
+  0x08003E58:  981A         LDR        R0, [SP, #104]
+  0x08003E5A:  6088         STR        R0, [R1, #8]
+  0x08003E5C:  48AA         LDR        R0, =relaisState         ; [PC, #0x02A8] [0x08004108] =0x20000730 
+  0x08003E5E:  7005         STRB       R5, [R0]
+  0x08003E60:  48AA         LDR        R0, =onTimeCounterSET    ; [PC, #0x02A8] [0x0800410C] =0x20000698 
+  0x08003E62:  9A15         LDR        R2, [SP, #84]
+  0x08003E64:  6002         STR        R2, [R0]
+  0x08003E66:  48B3         LDR        R0, =onTime              ; [PC, #0x02CC] [0x08004134] =0x20000744 
+  0x08003E68:  7005         STRB       R5, [R0]
+  0x08003E6A:  48B3         LDR        R0, =offTime             ; [PC, #0x02CC] [0x08004138] =0x20000750 
+  0x08003E6C:  7005         STRB       R5, [R0]
+  0x08003E6E:  48B3         LDR        R0, =alarmMode           ; [PC, #0x02CC] [0x0800413C] =0x2000075C 
+  0x08003E70:  7005         STRB       R5, [R0]
+  0x08003E72:  9820         LDR        R0, [SP, #128]
+  0x08003E74:  6088         STR        R0, [R1, #8]
+  0x08003E76:  49AB         LDR        R1, =onTimeCounter       ; [PC, #0x02AC] [0x08004124] =0x200006A8 
+  0x08003E78:  20C8         MOVS       R0, #200
+  0x08003E7A:  6008         STR        R0, [R1]
+  0x08003E7C:  4BAA         LDR        R3, =0x50000818          ; [PC, #0x02A8] [0x08004128] 
+  0x08003E7E:  991F         LDR        R1, [SP, #124]
+  0x08003E80:  6019         STR        R1, [R3]
+  0x08003E82:  49A6         LDR        R1, =onTimeCounterGN     ; [PC, #0x0298] [0x0800411C] =0x200006A4 
+  0x08003E84:  2200         MOVS       R2, #0
+  0x08003E86:  600A         STR        R2, [R1]
+  0x08003E88:  49A5         LDR        R1, =blinkModeGN         ; [PC, #0x0294] [0x08004120] =0x20000758 
+  0x08003E8A:  700A         STRB       R2, [R1]
+  0x08003E8C:  49AC         LDR        R1, =offTimeCounterGN    ; [PC, #0x02B0] [0x08004140] =0x200006B4 
+  0x08003E8E:  600A         STR        R2, [R1]
+  0x08003E90:  49AC         LDR        R1, =onTimeRT            ; [PC, #0x02B0] [0x08004144] =0x2000073C 
+  0x08003E92:  700D         STRB       R5, [R1]
+  0x08003E94:  49AC         LDR        R1, =offTimeRT           ; [PC, #0x02B0] [0x08004148] =0x20000748 
+  0x08003E96:  700D         STRB       R5, [R1]
+  0x08003E98:  49AC         LDR        R1, =blinkModeRT         ; [PC, #0x02B0] [0x0800414C] =0x20000754 
+  0x08003E9A:  700D         STRB       R5, [R1]
+  0x08003E9C:  49AC         LDR        R1, =numberOfBlinks      ; [PC, #0x02B0] [0x08004150] =0x200006BC 
+  0x08003E9E:  600D         STR        R5, [R1]
+  0x08003EA0:  49AC         LDR        R1, =blinkCounter        ; [PC, #0x02B0] [0x08004154] =0x200006EC 
+  0x08003EA2:  600D         STR        R5, [R1]
+  0x08003EA4:  49AC         LDR        R1, =pauseTime           ; [PC, #0x02B0] [0x08004158] =0x20000734 
+  0x08003EA6:  700D         STRB       R5, [R1]
+  0x08003EA8:  991E         LDR        R1, [SP, #120]
+  0x08003EAA:  6019         STR        R1, [R3]
+
.L239:
+  0x08003EAC:  49AB         LDR        R1, =onTimeCounterRT     ; [PC, #0x02AC] [0x0800415C] =0x2000069C 
+  0x08003EAE:  6008         STR        R0, [R1]
+  0x08003EB0:  48AD         LDR        R0, =0x08006890          ; [PC, #0x02B4] [0x08004168] 
+  0x08003EB2:  E107         B          .L252                    ; 0x080040C4
+
.L240:
+  0x08003EB4:  4993         LDR        R1, =0x50000410          ; [PC, #0x024C] [0x08004104] 
+  0x08003EB6:  9819         LDR        R0, [SP, #100]
+  0x08003EB8:  6188         STR        R0, [R1, #24]
+  0x08003EBA:  981A         LDR        R0, [SP, #104]
+  0x08003EBC:  6088         STR        R0, [R1, #8]
+  0x08003EBE:  4892         LDR        R0, =relaisState         ; [PC, #0x0248] [0x08004108] =0x20000730 
+  0x08003EC0:  7005         STRB       R5, [R0]
+  0x08003EC2:  4892         LDR        R0, =onTimeCounterSET    ; [PC, #0x0248] [0x0800410C] =0x20000698 
+  0x08003EC4:  9A15         LDR        R2, [SP, #84]
+  0x08003EC6:  6002         STR        R2, [R0]
+  0x08003EC8:  9820         LDR        R0, [SP, #128]
+  0x08003ECA:  6088         STR        R0, [R1, #8]
+  0x08003ECC:  4891         LDR        R0, =onTimeGN            ; [PC, #0x0244] [0x08004114] =0x20000740 
+  0x08003ECE:  7005         STRB       R5, [R0]
+  0x08003ED0:  4894         LDR        R0, =onTimeCounter       ; [PC, #0x0250] [0x08004124] =0x200006A8 
+  0x08003ED2:  21C8         MOVS       R1, #200
+  0x08003ED4:  6001         STR        R1, [R0]
+  0x08003ED6:  488E         LDR        R0, =offTimeGN           ; [PC, #0x0238] [0x08004110] =0x2000074C 
+  0x08003ED8:  7005         STRB       R5, [R0]
+  0x08003EDA:  4891         LDR        R0, =blinkModeGN         ; [PC, #0x0244] [0x08004120] =0x20000758 
+  0x08003EDC:  7005         STRB       R5, [R0]
+  0x08003EDE:  4A92         LDR        R2, =0x50000818          ; [PC, #0x0248] [0x08004128] 
+  0x08003EE0:  981F         LDR        R0, [SP, #124]
+  0x08003EE2:  6010         STR        R0, [R2]
+  0x08003EE4:  488D         LDR        R0, =onTimeCounterGN     ; [PC, #0x0234] [0x0800411C] =0x200006A4 
+  0x08003EE6:  6001         STR        R1, [R0]
+  0x08003EE8:  981E         LDR        R0, [SP, #120]
+  0x08003EEA:  6110         STR        R0, [R2, #16]
+  0x08003EEC:  489F         LDR        R0, =offTimeCounterRT    ; [PC, #0x027C] [0x0800416C] =0x200006B0 
+  0x08003EEE:  2100         MOVS       R1, #0
+  0x08003EF0:  6001         STR        R1, [R0]
+  0x08003EF2:  4896         LDR        R0, =blinkModeRT         ; [PC, #0x0258] [0x0800414C] =0x20000754 
+  0x08003EF4:  7001         STRB       R1, [R0]
+  0x08003EF6:  4899         LDR        R0, =onTimeCounterRT     ; [PC, #0x0264] [0x0800415C] =0x2000069C 
+  0x08003EF8:  6001         STR        R1, [R0]
+  0x08003EFA:  489D         LDR        R0, =0x080063CD          ; [PC, #0x0274] [0x08004170] 
+  0x08003EFC:  F001 F92C    BL         puts                     ; 0x08005158
+  0x08003F00:  7025         STRB       R5, [R4]
+  0x08003F02:  7830         LDRB       R0, [R6]
+
.L241:
+  0x08003F04:  2802         CMP        R0, #2
+  0x08003F06:  D000         BEQ        .L242                    ; 0x08003F0A
+  0x08003F08:  E0E0         B          .L254                    ; 0x080040CC
+
.L242:
+  0x08003F0A:  497E         LDR        R1, =0x50000410          ; [PC, #0x01F8] [0x08004104] 
+  0x08003F0C:  9819         LDR        R0, [SP, #100]
+  0x08003F0E:  6188         STR        R0, [R1, #24]
+  0x08003F10:  981A         LDR        R0, [SP, #104]
+  0x08003F12:  6088         STR        R0, [R1, #8]
+  0x08003F14:  487C         LDR        R0, =relaisState         ; [PC, #0x01F0] [0x08004108] =0x20000730 
+  0x08003F16:  7005         STRB       R5, [R0]
+  0x08003F18:  487C         LDR        R0, =onTimeCounterSET    ; [PC, #0x01F0] [0x0800410C] =0x20000698 
+  0x08003F1A:  9A15         LDR        R2, [SP, #84]
+  0x08003F1C:  6002         STR        R2, [R0]
+  0x08003F1E:  4885         LDR        R0, =onTime              ; [PC, #0x0214] [0x08004134] =0x20000744 
+  0x08003F20:  7005         STRB       R5, [R0]
+  0x08003F22:  4885         LDR        R0, =offTime             ; [PC, #0x0214] [0x08004138] =0x20000750 
+  0x08003F24:  7005         STRB       R5, [R0]
+  0x08003F26:  4885         LDR        R0, =alarmMode           ; [PC, #0x0214] [0x0800413C] =0x2000075C 
+  0x08003F28:  7005         STRB       R5, [R0]
+  0x08003F2A:  9820         LDR        R0, [SP, #128]
+  0x08003F2C:  6088         STR        R0, [R1, #8]
+  0x08003F2E:  497D         LDR        R1, =onTimeCounter       ; [PC, #0x01F4] [0x08004124] =0x200006A8 
+  0x08003F30:  20C8         MOVS       R0, #200
+  0x08003F32:  6008         STR        R0, [R1]
+  0x08003F34:  4B7C         LDR        R3, =0x50000818          ; [PC, #0x01F0] [0x08004128] 
+  0x08003F36:  991F         LDR        R1, [SP, #124]
+  0x08003F38:  6019         STR        R1, [R3]
+  0x08003F3A:  4978         LDR        R1, =onTimeCounterGN     ; [PC, #0x01E0] [0x0800411C] =0x200006A4 
+  0x08003F3C:  2200         MOVS       R2, #0
+  0x08003F3E:  600A         STR        R2, [R1]
+  0x08003F40:  4977         LDR        R1, =blinkModeGN         ; [PC, #0x01DC] [0x08004120] =0x20000758 
+  0x08003F42:  700A         STRB       R2, [R1]
+  0x08003F44:  497E         LDR        R1, =offTimeCounterGN    ; [PC, #0x01F8] [0x08004140] =0x200006B4 
+  0x08003F46:  600A         STR        R2, [R1]
+  0x08003F48:  9E1E         LDR        R6, [SP, #120]
+  0x08003F4A:  611E         STR        R6, [R3, #16]
+  0x08003F4C:  497D         LDR        R1, =onTimeRT            ; [PC, #0x01F4] [0x08004144] =0x2000073C 
+  0x08003F4E:  700D         STRB       R5, [R1]
+  0x08003F50:  4986         LDR        R1, =offTimeCounterRT    ; [PC, #0x0218] [0x0800416C] =0x200006B0 
+  0x08003F52:  600A         STR        R2, [R1]
+  0x08003F54:  497C         LDR        R1, =offTimeRT           ; [PC, #0x01F0] [0x08004148] =0x20000748 
+  0x08003F56:  700D         STRB       R5, [R1]
+  0x08003F58:  497C         LDR        R1, =blinkModeRT         ; [PC, #0x01F0] [0x0800414C] =0x20000754 
+  0x08003F5A:  700D         STRB       R5, [R1]
+  0x08003F5C:  497C         LDR        R1, =numberOfBlinks      ; [PC, #0x01F0] [0x08004150] =0x200006BC 
+  0x08003F5E:  600D         STR        R5, [R1]
+  0x08003F60:  497C         LDR        R1, =blinkCounter        ; [PC, #0x01F0] [0x08004154] =0x200006EC 
+  0x08003F62:  600D         STR        R5, [R1]
+  0x08003F64:  497C         LDR        R1, =pauseTime           ; [PC, #0x01F0] [0x08004158] =0x20000734 
+  0x08003F66:  700D         STRB       R5, [R1]
+  0x08003F68:  601E         STR        R6, [R3]
+  0x08003F6A:  E0A8         B          .L251                    ; 0x080040BE
+
.L243:
+  0x08003F6C:  4965         LDR        R1, =0x50000410          ; [PC, #0x0194] [0x08004104] 
+  0x08003F6E:  9819         LDR        R0, [SP, #100]
+  0x08003F70:  6188         STR        R0, [R1, #24]
+  0x08003F72:  981A         LDR        R0, [SP, #104]
+  0x08003F74:  6088         STR        R0, [R1, #8]
+  0x08003F76:  4864         LDR        R0, =relaisState         ; [PC, #0x0190] [0x08004108] =0x20000730 
+  0x08003F78:  7005         STRB       R5, [R0]
+  0x08003F7A:  4864         LDR        R0, =onTimeCounterSET    ; [PC, #0x0190] [0x0800410C] =0x20000698 
+  0x08003F7C:  9A15         LDR        R2, [SP, #84]
+  0x08003F7E:  6002         STR        R2, [R0]
+  0x08003F80:  9820         LDR        R0, [SP, #128]
+  0x08003F82:  6088         STR        R0, [R1, #8]
+  0x08003F84:  4862         LDR        R0, =offTimeGN           ; [PC, #0x0188] [0x08004110] =0x2000074C 
+  0x08003F86:  7005         STRB       R5, [R0]
+  0x08003F88:  4862         LDR        R0, =onTimeGN            ; [PC, #0x0188] [0x08004114] =0x20000740 
+  0x08003F8A:  7005         STRB       R5, [R0]
+  0x08003F8C:  4879         LDR        R0, =0x080063DF          ; [PC, #0x01E4] [0x08004174] 
+  0x08003F8E:  4963         LDR        R1, =onTimeCounterGN     ; [PC, #0x018C] [0x0800411C] =0x200006A4 
+  0x08003F90:  4B63         LDR        R3, =blinkModeGN         ; [PC, #0x018C] [0x08004120] =0x20000758 
+  0x08003F92:  22C8         MOVS       R2, #200
+  0x08003F94:  9E1F         LDR        R6, [SP, #124]
+  0x08003F96:  462F         MOV        R7, R5
+
.L244:
+  0x08003F98:  701D         STRB       R5, [R3]
+  0x08003F9A:  4B62         LDR        R3, =onTimeCounter       ; [PC, #0x0188] [0x08004124] =0x200006A8 
+  0x08003F9C:  601A         STR        R2, [R3]
+  0x08003F9E:  4A62         LDR        R2, =0x50000818          ; [PC, #0x0188] [0x08004128] 
+  0x08003FA0:  6016         STR        R6, [R2]
+  0x08003FA2:  22C8         MOVS       R2, #200
+  0x08003FA4:  600A         STR        R2, [R1]
+  0x08003FA6:  F001 F8D7    BL         puts                     ; 0x08005158
+  0x08003FAA:  7027         STRB       R7, [R4]
+  0x08003FAC:  485F         LDR        R0, =buttonState         ; [PC, #0x017C] [0x0800412C] =0x2000073A 
+  0x08003FAE:  7800         LDRB       R0, [R0]
+  0x08003FB0:  4F5F         LDR        R7, =modbusData          ; [PC, #0x017C] [0x08004130] =0x20000000 
+
.L245:
+  0x08003FB2:  2802         CMP        R0, #2
+  0x08003FB4:  D000         BEQ        .L246                    ; 0x08003FB8
+  0x08003FB6:  E089         B          .L254                    ; 0x080040CC
+
.L246:
+  0x08003FB8:  4952         LDR        R1, =0x50000410          ; [PC, #0x0148] [0x08004104] 
+  0x08003FBA:  9819         LDR        R0, [SP, #100]
+  0x08003FBC:  6188         STR        R0, [R1, #24]
+  0x08003FBE:  981A         LDR        R0, [SP, #104]
+  0x08003FC0:  6088         STR        R0, [R1, #8]
+  0x08003FC2:  4851         LDR        R0, =relaisState         ; [PC, #0x0144] [0x08004108] =0x20000730 
+  0x08003FC4:  7005         STRB       R5, [R0]
+  0x08003FC6:  4851         LDR        R0, =onTimeCounterSET    ; [PC, #0x0144] [0x0800410C] =0x20000698 
+  0x08003FC8:  9A15         LDR        R2, [SP, #84]
+  0x08003FCA:  6002         STR        R2, [R0]
+  0x08003FCC:  4859         LDR        R0, =onTime              ; [PC, #0x0164] [0x08004134] =0x20000744 
+  0x08003FCE:  7005         STRB       R5, [R0]
+  0x08003FD0:  4859         LDR        R0, =offTime             ; [PC, #0x0164] [0x08004138] =0x20000750 
+  0x08003FD2:  7005         STRB       R5, [R0]
+  0x08003FD4:  4859         LDR        R0, =alarmMode           ; [PC, #0x0164] [0x0800413C] =0x2000075C 
+  0x08003FD6:  7005         STRB       R5, [R0]
+  0x08003FD8:  9820         LDR        R0, [SP, #128]
+  0x08003FDA:  6088         STR        R0, [R1, #8]
+  0x08003FDC:  4951         LDR        R1, =onTimeCounter       ; [PC, #0x0144] [0x08004124] =0x200006A8 
+  0x08003FDE:  20C8         MOVS       R0, #200
+  0x08003FE0:  6008         STR        R0, [R1]
+  0x08003FE2:  4B51         LDR        R3, =0x50000818          ; [PC, #0x0144] [0x08004128] 
+  0x08003FE4:  991F         LDR        R1, [SP, #124]
+  0x08003FE6:  6019         STR        R1, [R3]
+  0x08003FE8:  494C         LDR        R1, =onTimeCounterGN     ; [PC, #0x0130] [0x0800411C] =0x200006A4 
+  0x08003FEA:  2200         MOVS       R2, #0
+  0x08003FEC:  600A         STR        R2, [R1]
+  0x08003FEE:  494C         LDR        R1, =blinkModeGN         ; [PC, #0x0130] [0x08004120] =0x20000758 
+  0x08003FF0:  700A         STRB       R2, [R1]
+  0x08003FF2:  4953         LDR        R1, =offTimeCounterGN    ; [PC, #0x014C] [0x08004140] =0x200006B4 
+  0x08003FF4:  600A         STR        R2, [R1]
+  0x08003FF6:  4953         LDR        R1, =onTimeRT            ; [PC, #0x014C] [0x08004144] =0x2000073C 
+  0x08003FF8:  700D         STRB       R5, [R1]
+  0x08003FFA:  4953         LDR        R1, =offTimeRT           ; [PC, #0x014C] [0x08004148] =0x20000748 
+  0x08003FFC:  700D         STRB       R5, [R1]
+  0x08003FFE:  4953         LDR        R1, =blinkModeRT         ; [PC, #0x014C] [0x0800414C] =0x20000754 
+  0x08004000:  700D         STRB       R5, [R1]
+  0x08004002:  4953         LDR        R1, =numberOfBlinks      ; [PC, #0x014C] [0x08004150] =0x200006BC 
+  0x08004004:  600D         STR        R5, [R1]
+  0x08004006:  4953         LDR        R1, =blinkCounter        ; [PC, #0x014C] [0x08004154] =0x200006EC 
+  0x08004008:  600D         STR        R5, [R1]
+  0x0800400A:  4953         LDR        R1, =pauseTime           ; [PC, #0x014C] [0x08004158] =0x20000734 
+  0x0800400C:  700D         STRB       R5, [R1]
+  0x0800400E:  991E         LDR        R1, [SP, #120]
+  0x08004010:  6019         STR        R1, [R3]
+
.L247:
+  0x08004012:  4952         LDR        R1, =onTimeCounterRT     ; [PC, #0x0148] [0x0800415C] =0x2000069C 
+  0x08004014:  6008         STR        R0, [R1]
+  0x08004016:  4858         LDR        R0, =0x08006631          ; [PC, #0x0160] [0x08004178] 
+  0x08004018:  E054         B          .L252                    ; 0x080040C4
+
.L248:
+  0x0800401A:  493A         LDR        R1, =0x50000410          ; [PC, #232] [0x08004104] 
+  0x0800401C:  9819         LDR        R0, [SP, #100]
+  0x0800401E:  6188         STR        R0, [R1, #24]
+  0x08004020:  981A         LDR        R0, [SP, #104]
+  0x08004022:  6088         STR        R0, [R1, #8]
+  0x08004024:  4838         LDR        R0, =relaisState         ; [PC, #224] [0x08004108] =0x20000730 
+  0x08004026:  7005         STRB       R5, [R0]
+  0x08004028:  4838         LDR        R0, =onTimeCounterSET    ; [PC, #224] [0x0800410C] =0x20000698 
+  0x0800402A:  9A15         LDR        R2, [SP, #84]
+  0x0800402C:  6002         STR        R2, [R0]
+  0x0800402E:  9820         LDR        R0, [SP, #128]
+  0x08004030:  6088         STR        R0, [R1, #8]
+  0x08004032:  4837         LDR        R0, =offTimeGN           ; [PC, #220] [0x08004110] =0x2000074C 
+  0x08004034:  7005         STRB       R5, [R0]
+  0x08004036:  4837         LDR        R0, =onTimeGN            ; [PC, #220] [0x08004114] =0x20000740 
+  0x08004038:  7005         STRB       R5, [R0]
+  0x0800403A:  4850         LDR        R0, =0x080063AF          ; [PC, #0x0140] [0x0800417C] 
+  0x0800403C:  4937         LDR        R1, =onTimeCounterGN     ; [PC, #220] [0x0800411C] =0x200006A4 
+  0x0800403E:  4B38         LDR        R3, =blinkModeGN         ; [PC, #224] [0x08004120] =0x20000758 
+  0x08004040:  22C8         MOVS       R2, #200
+  0x08004042:  9E1F         LDR        R6, [SP, #124]
+  0x08004044:  462F         MOV        R7, R5
+
.L249:
+  0x08004046:  701D         STRB       R5, [R3]
+  0x08004048:  4B36         LDR        R3, =onTimeCounter       ; [PC, #216] [0x08004124] =0x200006A8 
+  0x0800404A:  601A         STR        R2, [R3]
+  0x0800404C:  4A36         LDR        R2, =0x50000818          ; [PC, #216] [0x08004128] 
+  0x0800404E:  6016         STR        R6, [R2]
+  0x08004050:  22C8         MOVS       R2, #200
+  0x08004052:  600A         STR        R2, [R1]
+  0x08004054:  F001 F880    BL         puts                     ; 0x08005158
+  0x08004058:  7027         STRB       R7, [R4]
+  0x0800405A:  4834         LDR        R0, =buttonState         ; [PC, #208] [0x0800412C] =0x2000073A 
+  0x0800405C:  7800         LDRB       R0, [R0]
+  0x0800405E:  4F34         LDR        R7, =modbusData          ; [PC, #208] [0x08004130] =0x20000000 
+
.L250:
+  0x08004060:  2802         CMP        R0, #2
+  0x08004062:  D133         BNE        .L254                    ; 0x080040CC
+  0x08004064:  4927         LDR        R1, =0x50000410          ; [PC, #156] [0x08004104] 
+  0x08004066:  9819         LDR        R0, [SP, #100]
+  0x08004068:  6188         STR        R0, [R1, #24]
+  0x0800406A:  981A         LDR        R0, [SP, #104]
+  0x0800406C:  6088         STR        R0, [R1, #8]
+  0x0800406E:  4826         LDR        R0, =relaisState         ; [PC, #152] [0x08004108] =0x20000730 
+  0x08004070:  7005         STRB       R5, [R0]
+  0x08004072:  4826         LDR        R0, =onTimeCounterSET    ; [PC, #152] [0x0800410C] =0x20000698 
+  0x08004074:  9A15         LDR        R2, [SP, #84]
+  0x08004076:  6002         STR        R2, [R0]
+  0x08004078:  482E         LDR        R0, =onTime              ; [PC, #184] [0x08004134] =0x20000744 
+  0x0800407A:  7005         STRB       R5, [R0]
+  0x0800407C:  482E         LDR        R0, =offTime             ; [PC, #184] [0x08004138] =0x20000750 
+  0x0800407E:  7005         STRB       R5, [R0]
+  0x08004080:  482E         LDR        R0, =alarmMode           ; [PC, #184] [0x0800413C] =0x2000075C 
+  0x08004082:  7005         STRB       R5, [R0]
+  0x08004084:  9820         LDR        R0, [SP, #128]
+  0x08004086:  6088         STR        R0, [R1, #8]
+  0x08004088:  4926         LDR        R1, =onTimeCounter       ; [PC, #152] [0x08004124] =0x200006A8 
+  0x0800408A:  20C8         MOVS       R0, #200
+  0x0800408C:  6008         STR        R0, [R1]
+  0x0800408E:  4B26         LDR        R3, =0x50000818          ; [PC, #152] [0x08004128] 
+  0x08004090:  991F         LDR        R1, [SP, #124]
+  0x08004092:  6019         STR        R1, [R3]
+  0x08004094:  4921         LDR        R1, =onTimeCounterGN     ; [PC, #132] [0x0800411C] =0x200006A4 
+  0x08004096:  2200         MOVS       R2, #0
+  0x08004098:  600A         STR        R2, [R1]
+  0x0800409A:  4921         LDR        R1, =blinkModeGN         ; [PC, #132] [0x08004120] =0x20000758 
+  0x0800409C:  700A         STRB       R2, [R1]
+  0x0800409E:  4928         LDR        R1, =offTimeCounterGN    ; [PC, #160] [0x08004140] =0x200006B4 
+  0x080040A0:  600A         STR        R2, [R1]
+  0x080040A2:  4928         LDR        R1, =onTimeRT            ; [PC, #160] [0x08004144] =0x2000073C 
+  0x080040A4:  700D         STRB       R5, [R1]
+  0x080040A6:  4928         LDR        R1, =offTimeRT           ; [PC, #160] [0x08004148] =0x20000748 
+  0x080040A8:  700D         STRB       R5, [R1]
+  0x080040AA:  4928         LDR        R1, =blinkModeRT         ; [PC, #160] [0x0800414C] =0x20000754 
+  0x080040AC:  700D         STRB       R5, [R1]
+  0x080040AE:  4928         LDR        R1, =numberOfBlinks      ; [PC, #160] [0x08004150] =0x200006BC 
+  0x080040B0:  600D         STR        R5, [R1]
+  0x080040B2:  4928         LDR        R1, =blinkCounter        ; [PC, #160] [0x08004154] =0x200006EC 
+  0x080040B4:  600D         STR        R5, [R1]
+  0x080040B6:  4928         LDR        R1, =pauseTime           ; [PC, #160] [0x08004158] =0x20000734 
+  0x080040B8:  700D         STRB       R5, [R1]
+  0x080040BA:  991E         LDR        R1, [SP, #120]
+  0x080040BC:  6019         STR        R1, [R3]
+
.L251:
+  0x080040BE:  4927         LDR        R1, =onTimeCounterRT     ; [PC, #156] [0x0800415C] =0x2000069C 
+  0x080040C0:  6008         STR        R0, [R1]
+  0x080040C2:  48F9         LDR        R0, =0x080065CA          ; [PC, #0x03E4] [0x080044A8] 
+
.L252:
+  0x080040C4:  F001 F848    BL         puts                     ; 0x08005158
+  0x080040C8:  2002         MOVS       R0, #2
+
.L253:
+  0x080040CA:  7020         STRB       R0, [R4]
+
.L254:
+  0x080040CC:  9822         LDR        R0, [SP, #136]
+  0x080040CE:  5C38         LDRB       R0, [R7, R0]
+  0x080040D0:  49EF         LDR        R1, =sys_data            ; [PC, #0x03BC] [0x08004490] =0x20000234 
+  0x080040D2:  8B49         LDRH       R1, [R1, #26]
+  0x080040D4:  2900         CMP        R1, #0
+  0x080040D6:  D101         BNE        .L255                    ; 0x080040DC
+  0x080040D8:  F7FE FADD    BL         .L108                    ; 0x08002696
+
.L255:
+  0x080040DC:  2800         CMP        R0, #0
+  0x080040DE:  D001         BEQ        .L256                    ; 0x080040E4
+  0x080040E0:  F7FE FAD9    BL         .L108                    ; 0x08002696
+
.L256:
+  0x080040E4:  48EA         LDR        R0, =sys_data            ; [PC, #0x03A8] [0x08004490] =0x20000234 
+  0x080040E6:  8B40         LDRH       R0, [R0, #26]
+  0x080040E8:  1E41         SUBS       R1, R0, #1
+  0x080040EA:  2905         CMP        R1, #5
+  0x080040EC:  D84B         BHI        .L257                    ; 0x08004186
+  0x080040EE:  0049         LSLS       R1, R1, #1
+  0x080040F0:  4479         ADD        R1, PC
+  0x080040F2:  8889         LDRH       R1, [R1, #4]
+  0x080040F4:  0049         LSLS       R1, R1, #1
+  0x080040F6:  448F         ADD        PC, R1
+  0x080040F8:  51           DC.B       0x51                     ; 'Q'
+  0x080040F9:  00           DC.B       0x00                     ; '\0'
+  0x080040FA:  43           DC.B       0x43                     ; 'C'
+  0x080040FB:  00           DC.B       0x00                     ; '\0'
+  0x080040FC:  43           DC.B       0x43                     ; 'C'
+  0x080040FD:  00           DC.B       0x00                     ; '\0'
+  0x080040FE:  53           DC.B       0x53                     ; 'S'
+  0x080040FF:  00           DC.B       0x00                     ; '\0'
+  0x08004100:  4D           DC.B       0x4D                     ; 'M'
+  0x08004101:  00           DC.B       0x00                     ; '\0'
+  0x08004102:  2F           DC.B       0x2F                     ; '/'
+  0x08004103:  01           DC.B       0x01                     ; '\x01'
+  0x08004104:  50000410     DC.W       0x50000410
+  0x08004108:  20000730     DC.W       relaisState
+  0x0800410C:  20000698     DC.W       onTimeCounterSET
+  0x08004110:  2000074C     DC.W       offTimeGN
+  0x08004114:  20000740     DC.W       onTimeGN
+  0x08004118:  0800645B     DC.W       0800645B               ; R_ARM_ABS32
+  0x0800411C:  200006A4     DC.W       onTimeCounterGN
+  0x08004120:  20000758     DC.W       blinkModeGN
+  0x08004124:  200006A8     DC.W       onTimeCounter
+  0x08004128:  50000818     DC.W       0x50000818
+  0x0800412C:  2000073A     DC.W       buttonState
+  0x08004130:  20000000     DC.W       modbusData
+  0x08004134:  20000744     DC.W       onTime
+  0x08004138:  20000750     DC.W       offTime
+  0x0800413C:  2000075C     DC.W       alarmMode
+  0x08004140:  200006B4     DC.W       offTimeCounterGN
+  0x08004144:  2000073C     DC.W       onTimeRT
+  0x08004148:  20000748     DC.W       offTimeRT
+  0x0800414C:  20000754     DC.W       blinkModeRT
+  0x08004150:  200006BC     DC.W       numberOfBlinks
+  0x08004154:  200006EC     DC.W       blinkCounter
+  0x08004158:  20000734     DC.W       pauseTime
+  0x0800415C:  2000069C     DC.W       onTimeCounterRT
+  0x08004160:  080066B2     DC.W       080066B2               ; R_ARM_ABS32
+  0x08004164:  0800664E     DC.W       0800664E               ; R_ARM_ABS32
+  0x08004168:  08006890     DC.W       08006890               ; R_ARM_ABS32
+  0x0800416C:  200006B0     DC.W       offTimeCounterRT
+  0x08004170:  080063CD     DC.W       080063CD               ; R_ARM_ABS32
+  0x08004174:  080063DF     DC.W       080063DF               ; R_ARM_ABS32
+  0x08004178:  08006631     DC.W       08006631               ; R_ARM_ABS32
+  0x0800417C:  080063AF     DC.W       080063AF               ; R_ARM_ABS32
+  0x08004180:  F7FD FB18    BL         EEPROM_WriteDefaults     ; 0x080017B4
+  0x08004184:  E012         B          .L261                    ; 0x080041AC
+
.L257:
+  0x08004186:  49C9         LDR        R1, =0x000004D2          ; [PC, #0x0324] [0x080044AC] 
+  0x08004188:  4288         CMP        R0, R1
+  0x0800418A:  D00C         BEQ        .L259                    ; 0x080041A6
+  0x0800418C:  49C8         LDR        R1, =0x00001552          ; [PC, #0x0320] [0x080044B0] 
+  0x0800418E:  4288         CMP        R0, R1
+  0x08004190:  D100         BNE        .L258                    ; 0x08004194
+  0x08004192:  E159         B          .L290                    ; 0x08004448
+
.L258:
+  0x08004194:  48C7         LDR        R0, =0x0800680C          ; [PC, #0x031C] [0x080044B4] 
+  0x08004196:  F000 FFDF    BL         puts                     ; 0x08005158
+  0x0800419A:  E007         B          .L261                    ; 0x080041AC
+  0x0800419C:  2000         MOVS       R0, #0
+  0x0800419E:  E003         B          .L260                    ; 0x080041A8
+  0x080041A0:  F7FD FB20    BL         EEPROM_ReadDeviceParameter ; 0x080017E4
+  0x080041A4:  E002         B          .L261                    ; 0x080041AC
+
.L259:
+  0x080041A6:  4628         MOV        R0, R5
+
.L260:
+  0x080041A8:  F7FD FB2E    BL         EEPROM_StoreConfig       ; 0x08001808
+
.L261:
+  0x080041AC:  2000         MOVS       R0, #0
+  0x080041AE:  49B8         LDR        R1, =sys_data            ; [PC, #0x02E0] [0x08004490] =0x20000234 
+  0x080041B0:  8348         STRH       R0, [R1, #26]
+  0x080041B2:  F7FE FA70    BL         .L108                    ; 0x08002696
+
.L262:
+  0x080041B6:  9B08         LDR        R3, [SP, #32]
+  0x080041B8:  5CFB         LDRB       R3, [R7, R3]
+  0x080041BA:  9C06         LDR        R4, [SP, #24]
+  0x080041BC:  00A4         LSLS       R4, R4, #2
+  0x080041BE:  553B         STRB       R3, [R7, R4]
+  0x080041C0:  242B         MOVS       R4, #43
+  0x080041C2:  5D3C         LDRB       R4, [R7, R4]
+  0x080041C4:  9E12         LDR        R6, [SP, #72]
+  0x080041C6:  362C         ADDS       R6, #44
+  0x080041C8:  55BC         STRB       R4, [R7, R6]
+  0x080041CA:  2695         MOVS       R6, #149
+  0x080041CC:  0076         LSLS       R6, R6, #1
+  0x080041CE:  55BA         STRB       R2, [R7, R6]
+  0x080041D0:  2225         MOVS       R2, #37
+  0x080041D2:  00D2         LSLS       R2, R2, #3
+  0x080041D4:  2606         MOVS       R6, #6
+  0x080041D6:  52BE         STRH       R6, [R7, R2]
+  0x080041D8:  0049         LSLS       R1, R1, #1
+  0x080041DA:  4FAD         LDR        R7, =sys_data            ; [PC, #0x02B4] [0x08004490] =0x20000234 
+  0x080041DC:  187A         ADDS       R2, R7, R1
+  0x080041DE:  7054         STRB       R4, [R2, #1]
+  0x080041E0:  547B         STRB       R3, [R7, R1]
+  0x080041E2:  E061         B          .L270                    ; 0x080042A8
+
.L263:
+  0x080041E4:  911B         STR        R1, [SP, #108]
+  0x080041E6:  222A         MOVS       R2, #42
+  0x080041E8:  5CBA         LDRB       R2, [R7, R2]
+  0x080041EA:  2129         MOVS       R1, #41
+  0x080041EC:  9105         STR        R1, [SP, #20]
+  0x080041EE:  5C79         LDRB       R1, [R7, R1]
+  0x080041F0:  020C         LSLS       R4, R1, #8
+  0x080041F2:  18A4         ADDS       R4, R4, R2
+  0x080041F4:  1936         ADDS       R6, R6, R4
+  0x080041F6:  4637         MOV        R7, R6
+  0x080041F8:  3F71         SUBS       R7, #113
+  0x080041FA:  236F         MOVS       R3, #111
+  0x080041FC:  43DB         MVNS       R3, R3
+  0x080041FE:  429F         CMP        R7, R3
+  0x08004200:  D204         BCS        .L264                    ; 0x0800420C
+  0x08004202:  2125         MOVS       R1, #37
+  0x08004204:  00C9         LSLS       R1, R1, #3
+  0x08004206:  9A05         LDR        R2, [SP, #20]
+  0x08004208:  0112         LSLS       R2, R2, #4
+  0x0800420A:  E4A0         B          .L217                    ; 0x08003B4E
+
.L264:
+  0x0800420C:  9204         STR        R2, [SP, #16]
+  0x0800420E:  0052         LSLS       R2, R2, #1
+  0x08004210:  9105         STR        R1, [SP, #20]
+  0x08004212:  024B         LSLS       R3, R1, #9
+  0x08004214:  189A         ADDS       R2, R3, R2
+  0x08004216:  4B9E         LDR        R3, =sys_data            ; [PC, #0x0278] [0x08004490] =0x20000234 
+  0x08004218:  189F         ADDS       R7, R3, R2
+  0x0800421A:  4A9E         LDR        R2, =modbusData          ; [PC, #0x0278] [0x08004494] =0x20000000 
+  0x0800421C:  322F         ADDS       R2, #47
+  0x0800421E:  991B         LDR        R1, [SP, #108]
+
.L265:
+  0x08004220:  42B4         CMP        R4, R6
+  0x08004222:  D208         BCS        .L266                    ; 0x08004236
+  0x08004224:  1E53         SUBS       R3, R2, #1
+  0x08004226:  781B         LDRB       R3, [R3]
+  0x08004228:  707B         STRB       R3, [R7, #1]
+  0x0800422A:  7813         LDRB       R3, [R2]
+  0x0800422C:  703B         STRB       R3, [R7]
+  0x0800422E:  1C92         ADDS       R2, R2, #2
+  0x08004230:  1CBF         ADDS       R7, R7, #2
+  0x08004232:  1C64         ADDS       R4, R4, #1
+  0x08004234:  E7F4         B          .L265                    ; 0x08004220
+
.L266:
+  0x08004236:  9A06         LDR        R2, [SP, #24]
+  0x08004238:  0092         LSLS       R2, R2, #2
+  0x0800423A:  4F96         LDR        R7, =modbusData          ; [PC, #0x0258] [0x08004494] =0x20000000 
+  0x0800423C:  54B9         STRB       R1, [R7, R2]
+  0x0800423E:  9B12         LDR        R3, [SP, #72]
+  0x08004240:  4619         MOV        R1, R3
+  0x08004242:  312C         ADDS       R1, #44
+  0x08004244:  2200         MOVS       R2, #0
+  0x08004246:  547A         STRB       R2, [R7, R1]
+  0x08004248:  2195         MOVS       R1, #149
+  0x0800424A:  0049         LSLS       R1, R1, #1
+  0x0800424C:  9A04         LDR        R2, [SP, #16]
+  0x0800424E:  547A         STRB       R2, [R7, R1]
+  0x08004250:  4619         MOV        R1, R3
+  0x08004252:  312A         ADDS       R1, #42
+  0x08004254:  9A05         LDR        R2, [SP, #20]
+  0x08004256:  547A         STRB       R2, [R7, R1]
+  0x08004258:  2125         MOVS       R1, #37
+  0x0800425A:  00C9         LSLS       R1, R1, #3
+  0x0800425C:  9A19         LDR        R2, [SP, #100]
+  0x0800425E:  547A         STRB       R2, [R7, R1]
+  0x08004260:  2606         MOVS       R6, #6
+  0x08004262:  E022         B          .L271                    ; 0x080042AA
+
.L267:
+  0x08004264:  9B12         LDR        R3, [SP, #72]
+  0x08004266:  332A         ADDS       R3, #42
+  0x08004268:  9C05         LDR        R4, [SP, #20]
+  0x0800426A:  0064         LSLS       R4, R4, #1
+  0x0800426C:  54FC         STRB       R4, [R7, R3]
+  0x0800426E:  2325         MOVS       R3, #37
+  0x08004270:  00DB         LSLS       R3, R3, #3
+  0x08004272:  2403         MOVS       R4, #3
+  0x08004274:  54FC         STRB       R4, [R7, R3]
+  0x08004276:  9B04         LDR        R3, [SP, #16]
+  0x08004278:  005B         LSLS       R3, R3, #1
+  0x0800427A:  9C03         LDR        R4, [SP, #12]
+  0x0800427C:  0264         LSLS       R4, R4, #9
+  0x0800427E:  18E3         ADDS       R3, R4, R3
+  0x08004280:  4C83         LDR        R4, =sys_data            ; [PC, #0x020C] [0x08004490] =0x20000234 
+  0x08004282:  18E3         ADDS       R3, R4, R3
+
.L268:
+  0x08004284:  9C1B         LDR        R4, [SP, #108]
+  0x08004286:  42A2         CMP        R2, R4
+  0x08004288:  D20D         BCS        .L269                    ; 0x080042A6
+  0x0800428A:  4C82         LDR        R4, =modbusData          ; [PC, #0x0208] [0x08004494] =0x20000000 
+  0x0800428C:  1864         ADDS       R4, R4, R1
+  0x0800428E:  185E         ADDS       R6, R3, R1
+  0x08004290:  7876         LDRB       R6, [R6, #1]
+  0x08004292:  2795         MOVS       R7, #149
+  0x08004294:  007F         LSLS       R7, R7, #1
+  0x08004296:  55E6         STRB       R6, [R4, R7]
+  0x08004298:  5C5E         LDRB       R6, [R3, R1]
+  0x0800429A:  9F12         LDR        R7, [SP, #72]
+  0x0800429C:  372C         ADDS       R7, #44
+  0x0800429E:  55E6         STRB       R6, [R4, R7]
+  0x080042A0:  1C89         ADDS       R1, R1, #2
+  0x080042A2:  1C52         ADDS       R2, R2, #1
+  0x080042A4:  E7EE         B          .L268                    ; 0x08004284
+
.L269:
+  0x080042A6:  1CCE         ADDS       R6, R1, #3
+
.L270:
+  0x080042A8:  4F7A         LDR        R7, =modbusData          ; [PC, #0x01E8] [0x08004494] =0x20000000 
+
.L271:
+  0x080042AA:  183C         ADDS       R4, R7, R0
+  0x080042AC:  4620         MOV        R0, R4
+  0x080042AE:  4631         MOV        R1, R6
+  0x080042B0:  F000 F984    BL         mbCrc16                  ; 0x080045BC
+  0x080042B4:  55A0         STRB       R0, [R4, R6]
+  0x080042B6:  990D         LDR        R1, [SP, #52]
+  0x080042B8:  9A22         LDR        R2, [SP, #136]
+  0x080042BA:  54B9         STRB       R1, [R7, R2]
+  0x080042BC:  19A1         ADDS       R1, R4, R6
+  0x080042BE:  0A00         LSRS       R0, R0, #8
+  0x080042C0:  7048         STRB       R0, [R1, #1]
+  0x080042C2:  1CB0         ADDS       R0, R6, #2
+  0x080042C4:  9911         LDR        R1, [SP, #68]
+  0x080042C6:  5078         STR        R0, [R7, R1]
+  0x080042C8:  683E         LDR        R6, [R7]
+  0x080042CA:  990C         LDR        R1, [SP, #48]
+  0x080042CC:  5871         LDR        R1, [R6, R1]
+  0x080042CE:  2920         CMP        R1, #32
+  0x080042D0:  D13C         BNE        .L275                    ; 0x0800434C
+  0x080042D2:  B283         UXTH       R3, R0
+  0x080042D4:  2B00         CMP        R3, #0
+  0x080042D6:  D039         BEQ        .L275                    ; 0x0800434C
+  0x080042D8:  68B1         LDR        R1, [R6, #8]
+  0x080042DA:  9A13         LDR        R2, [SP, #76]
+  0x080042DC:  4291         CMP        R1, R2
+  0x080042DE:  D102         BNE        .L272                    ; 0x080042E6
+  0x080042E0:  6931         LDR        R1, [R6, #16]
+  0x080042E2:  2900         CMP        R1, #0
+  0x080042E4:  D032         BEQ        .L275                    ; 0x0800434C
+
.L272:
+  0x080042E6:  4632         MOV        R2, R6
+  0x080042E8:  3254         ADDS       R2, #84
+  0x080042EA:  4637         MOV        R7, R6
+  0x080042EC:  3788         ADDS       R7, #136
+  0x080042EE:  8050         STRH       R0, [R2, #2]
+  0x080042F0:  2100         MOVS       R1, #0
+  0x080042F2:  60B9         STR        R1, [R7, #8]
+  0x080042F4:  8010         STRH       R0, [R2]
+  0x080042F6:  6534         STR        R4, [R6, #80]
+  0x080042F8:  2021         MOVS       R0, #33
+  0x080042FA:  6038         STR        R0, [R7]
+  0x080042FC:  6FF0         LDR        R0, [R6, #124]
+  0x080042FE:  2800         CMP        R0, #0
+  0x08004300:  D014         BEQ        .L273                    ; 0x0800432C
+  0x08004302:  931B         STR        R3, [SP, #108]
+  0x08004304:  4B66         LDR        R3, =UART_DMATxHalfCplt  ; [PC, #0x0198] [0x080044A0] =0x08005777 
+  0x08004306:  4A67         LDR        R2, =UART_DMATransmitCplt ; [PC, #0x019C] [0x080044A4] =0x08001501 
+  0x08004308:  62C2         STR        R2, [R0, #44]
+  0x0800430A:  6303         STR        R3, [R0, #48]
+  0x0800430C:  4A63         LDR        R2, =UART_DMAError       ; [PC, #0x018C] [0x0800449C] =0x08005779 
+  0x0800430E:  6342         STR        R2, [R0, #52]
+  0x08004310:  6381         STR        R1, [R0, #56]
+  0x08004312:  6832         LDR        R2, [R6]
+  0x08004314:  3228         ADDS       R2, #40
+  0x08004316:  4621         MOV        R1, R4
+  0x08004318:  9B1B         LDR        R3, [SP, #108]
+  0x0800431A:  F7FC FB83    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x0800431E:  2800         CMP        R0, #0
+  0x08004320:  D004         BEQ        .L273                    ; 0x0800432C
+  0x08004322:  9819         LDR        R0, [SP, #100]
+  0x08004324:  60B8         STR        R0, [R7, #8]
+  0x08004326:  9820         LDR        R0, [SP, #128]
+  0x08004328:  6038         STR        R0, [R7]
+  0x0800432A:  E00E         B          .L274                    ; 0x0800434A
+
.L273:
+  0x0800432C:  6830         LDR        R0, [R6]
+  0x0800432E:  9907         LDR        R1, [SP, #28]
+  0x08004330:  6201         STR        R1, [R0, #32]
+  0x08004332:  F3EF 8010    MRS        R0, PRIMASK
+  0x08004336:  2101         MOVS       R1, #1
+  0x08004338:  F381 8810    MSR        PRIMASK, R1
+  0x0800433C:  6831         LDR        R1, [R6]
+  0x0800433E:  688A         LDR        R2, [R1, #8]
+  0x08004340:  9B0A         LDR        R3, [SP, #40]
+  0x08004342:  431A         ORRS       R2, R3
+  0x08004344:  608A         STR        R2, [R1, #8]
+  0x08004346:  F380 8810    MSR        PRIMASK, R0
+
.L274:
+  0x0800434A:  4F52         LDR        R7, =modbusData          ; [PC, #0x0148] [0x08004494] =0x20000000 
+
.L275:
+  0x0800434C:  2000         MOVS       R0, #0
+  0x0800434E:  9921         LDR        R1, [SP, #132]
+  0x08004350:  5078         STR        R0, [R7, R1]
+  0x08004352:  7538         STRB       R0, [R7, #20]
+  0x08004354:  F7FE F9B5    BL         .L110                    ; 0x080026C2
+
.L276:
+  0x08004358:  E7FE         B          .L276                    ; 0x08004358
+
.L277:
+  0x0800435A:  4849         LDR        R0, =SystemCoreClock     ; [PC, #0x0124] [0x08004480] =0x20000BA4 
+  0x0800435C:  6800         LDR        R0, [R0]
+  0x0800435E:  494A         LDR        R1, =0x00030D40          ; [PC, #0x0128] [0x08004488] 
+  0x08004360:  F001 FE43    BL         __aeabi_uidiv            ; 0x08005FEA
+  0x08004364:  9A21         LDR        R2, [SP, #132]
+  0x08004366:  1C40         ADDS       R0, R0, #1
+
.L278:
+  0x08004368:  9029         STR        R0, [SP, #164]
+  0x0800436A:  9829         LDR        R0, [SP, #164]
+  0x0800436C:  2800         CMP        R0, #0
+  0x0800436E:  D101         BNE        .L279                    ; 0x08004374
+  0x08004370:  F7FE F91C    BL         .L99                     ; 0x080025AC
+
.L279:
+  0x08004374:  9829         LDR        R0, [SP, #164]
+  0x08004376:  1E40         SUBS       R0, R0, #1
+  0x08004378:  E7F6         B          .L278                    ; 0x08004368
+
.L280:
+  0x0800437A:  4840         LDR        R0, =uwTick              ; [PC, #0x0100] [0x0800447C] =0x2000068C 
+  0x0800437C:  6800         LDR        R0, [R0]
+
.L281:
+  0x0800437E:  6821         LDR        R1, [R4]
+  0x08004380:  07C9         LSLS       R1, R1, #31
+  0x08004382:  D001         BEQ        .L282                    ; 0x08004388
+  0x08004384:  F7FE F917    BL         .L100                    ; 0x080025B6
+
.L282:
+  0x08004388:  68A1         LDR        R1, [R4, #8]
+  0x0800438A:  07C9         LSLS       R1, R1, #31
+  0x0800438C:  D106         BNE        .L283                    ; 0x0800439C
+  0x0800438E:  68A1         LDR        R1, [R4, #8]
+  0x08004390:  4A3C         LDR        R2, =0x7FFFFFE8          ; [PC, #240] [0x08004484] 
+  0x08004392:  4011         ANDS       R1, R2
+  0x08004394:  9A21         LDR        R2, [SP, #132]
+  0x08004396:  9B23         LDR        R3, [SP, #140]
+  0x08004398:  4319         ORRS       R1, R3
+  0x0800439A:  60A1         STR        R1, [R4, #8]
+
.L283:
+  0x0800439C:  4937         LDR        R1, =uwTick              ; [PC, #220] [0x0800447C] =0x2000068C 
+  0x0800439E:  6809         LDR        R1, [R1]
+  0x080043A0:  1A09         SUBS       R1, R1, R0
+  0x080043A2:  2903         CMP        R1, #3
+  0x080043A4:  D3EB         BCC        .L281                    ; 0x0800437E
+  0x080043A6:  F7FE F8EC    BL         .L97                     ; 0x08002582
+
.L284:
+  0x080043AA:  4001         ANDS       R1, R0
+  0x080043AC:  9F02         LDR        R7, [SP, #8]
+  0x080043AE:  4339         ORRS       R1, R7
+  0x080043B0:  60A1         STR        R1, [R4, #8]
+  0x080043B2:  1D18         ADDS       R0, R3, #4
+  0x080043B4:  08C3         LSRS       R3, R0, #3
+  0x080043B6:  6920         LDR        R0, [R4, #16]
+  0x080043B8:  0F80         LSRS       R0, R0, #30
+  0x080043BA:  D114         BNE        .L286                    ; 0x080043E6
+  0x080043BC:  9803         LDR        R0, [SP, #12]
+  0x080043BE:  0480         LSLS       R0, R0, #18
+  0x080043C0:  4932         LDR        R1, =0x40012708          ; [PC, #200] [0x0800448C] 
+  0x080043C2:  6809         LDR        R1, [R1]
+  0x080043C4:  4001         ANDS       R1, R0
+  0x080043C6:  0C89         LSRS       R1, R1, #18
+  0x080043C8:  2907         CMP        R1, #7
+  0x080043CA:  D30C         BCC        .L286                    ; 0x080043E6
+  0x080043CC:  1EC8         SUBS       R0, R1, #3
+  0x080043CE:  4639         MOV        R1, R7
+  0x080043D0:  4081         LSLS       R1, R0
+  0x080043D2:  9130         STR        R1, [SP, #192]
+  0x080043D4:  9830         LDR        R0, [SP, #192]
+  0x080043D6:  0841         LSRS       R1, R0, #1
+
.L285:
+  0x080043D8:  9130         STR        R1, [SP, #192]
+  0x080043DA:  9830         LDR        R0, [SP, #192]
+  0x080043DC:  2800         CMP        R0, #0
+  0x080043DE:  D002         BEQ        .L286                    ; 0x080043E6
+  0x080043E0:  9830         LDR        R0, [SP, #192]
+  0x080043E2:  1E41         SUBS       R1, R0, #1
+  0x080043E4:  E7F8         B          .L285                    ; 0x080043D8
+
.L286:
+  0x080043E6:  6810         LDR        R0, [R2]
+  0x080043E8:  217F         MOVS       R1, #127
+  0x080043EA:  4388         BICS       R0, R1
+  0x080043EC:  4318         ORRS       R0, R3
+  0x080043EE:  6010         STR        R0, [R2]
+  0x080043F0:  68A0         LDR        R0, [R4, #8]
+  0x080043F2:  4924         LDR        R1, =0x7FFFFFE8          ; [PC, #144] [0x08004484] 
+  0x080043F4:  4008         ANDS       R0, R1
+  0x080043F6:  990F         LDR        R1, [SP, #60]
+  0x080043F8:  4308         ORRS       R0, R1
+  0x080043FA:  60A0         STR        R0, [R4, #8]
+  0x080043FC:  481F         LDR        R0, =uwTick              ; [PC, #124] [0x0800447C] =0x2000068C 
+  0x080043FE:  6802         LDR        R2, [R0]
+
.L287:
+  0x08004400:  68A0         LDR        R0, [R4, #8]
+  0x08004402:  07C0         LSLS       R0, R0, #31
+  0x08004404:  D012         BEQ        .L288                    ; 0x0800442C
+  0x08004406:  481D         LDR        R0, =uwTick              ; [PC, #116] [0x0800447C] =0x2000068C 
+  0x08004408:  6800         LDR        R0, [R0]
+  0x0800440A:  1A80         SUBS       R0, R0, R2
+  0x0800440C:  2803         CMP        R0, #3
+  0x0800440E:  D3F7         BCC        .L287                    ; 0x08004400
+  0x08004410:  68A0         LDR        R0, [R4, #8]
+  0x08004412:  07C0         LSLS       R0, R0, #31
+  0x08004414:  D0F4         BEQ        .L287                    ; 0x08004400
+  0x08004416:  6DB0         LDR        R0, [R6, #88]
+  0x08004418:  9919         LDR        R1, [SP, #100]
+  0x0800441A:  4308         ORRS       R0, R1
+  0x0800441C:  65B0         STR        R0, [R6, #88]
+  0x0800441E:  6DF0         LDR        R0, [R6, #92]
+  0x08004420:  4338         ORRS       R0, R7
+  0x08004422:  65F0         STR        R0, [R6, #92]
+  0x08004424:  4628         MOV        R0, R5
+  0x08004426:  9A21         LDR        R2, [SP, #132]
+  0x08004428:  F7FE F887    BL         .L94                     ; 0x0800253A
+
.L288:
+  0x0800442C:  68E0         LDR        R0, [R4, #12]
+  0x0800442E:  9901         LDR        R1, [SP, #4]
+  0x08004430:  4308         ORRS       R0, R1
+  0x08004432:  60E0         STR        R0, [R4, #12]
+  0x08004434:  6DB1         LDR        R1, [R6, #88]
+  0x08004436:  4339         ORRS       R1, R7
+  0x08004438:  980F         LDR        R0, [SP, #60]
+  0x0800443A:  4381         BICS       R1, R0
+  0x0800443C:  F7FE F86F    BL         .L91                     ; 0x0800251E
+
.L289:
+  0x08004440:  2000         MOVS       R0, #0
+  0x08004442:  7008         STRB       R0, [R1]
+  0x08004444:  F000 F838    BL         JumpToBootloader         ; 0x080044B8
+
.L290:
+  0x08004448:  480B         LDR        R0, =bootLoaderMark      ; [PC, #44] [0x08004478] =0x20000B7C 
+  0x0800444A:  7005         STRB       R5, [R0]
+  0x0800444C:  F001 FC8F    BL         HAL_NVIC_SystemReset     ; 0x08005D6E
+
.L291:
+  0x08004450:  3658         ADDS       R6, #88
+  0x08004452:  E008         B          .L293                    ; 0x08004466
+
.L292:
+  0x08004454:  6DB0         LDR        R0, [R6, #88]
+  0x08004456:  2110         MOVS       R1, #16
+  0x08004458:  4301         ORRS       R1, R0
+  0x0800445A:  980F         LDR        R0, [SP, #60]
+  0x0800445C:  4381         BICS       R1, R0
+  0x0800445E:  65B1         STR        R1, [R6, #88]
+  0x08004460:  6DF0         LDR        R0, [R6, #92]
+  0x08004462:  365C         ADDS       R6, #92
+  0x08004464:  4629         MOV        R1, R5
+
.L293:
+  0x08004466:  4301         ORRS       R1, R0
+  0x08004468:  6031         STR        R1, [R6]
+  0x0800446A:  F7FD FE6A    BL         .L61                     ; 0x08002142
+
.L294:
+  0x0800446E:  480A         LDR        R0, =0x0800656E          ; [PC, #40] [0x08004498] 
+  0x08004470:  F000 FE72    BL         puts                     ; 0x08005158
+  0x08004474:  F001 FCEB    BL         Error_Handler            ; 0x08005E4E
+  0x08004478:  20000B7C     DC.W       bootLoaderMark
+  0x0800447C:  2000068C     DC.W       uwTick
+  0x08004480:  20000BA4     DC.W       SystemCoreClock
+  0x08004484:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08004488:  00030D40     DC.W       0x00030D40
+  0x0800448C:  40012708     DC.W       0x40012708
+  0x08004490:  20000234     DC.W       sys_data
+  0x08004494:  20000000     DC.W       modbusData
+  0x08004498:  0800656E     DC.W       0800656E               ; R_ARM_ABS32
+  0x0800449C:  08005779     DC.W       UART_DMAError
+  0x080044A0:  08005777     DC.W       UART_DMATxHalfCplt
+  0x080044A4:  08001501     DC.W       UART_DMATransmitCplt
+  0x080044A8:  080065CA     DC.W       080065CA               ; R_ARM_ABS32
+  0x080044AC:  000004D2     DC.W       0x000004D2
+  0x080044B0:  00001552     DC.W       0x00001552
+  0x080044B4:  0800680C     DC.W       0800680C               ; R_ARM_ABS32
+
+

Section .text.JumpToBootloader from PowerPro_lto.o, size=92, align=4

+
+
JumpToBootloader:
+  0x080044B8:  B082         SUB        SP, SP, #8
+  0x080044BA:  B672         CPSID      i
+  0x080044BC:  2000         MOVS       R0, #0
+  0x080044BE:  43C0         MVNS       R0, R0
+  0x080044C0:  490E         LDR        R1, =0xE000E180          ; [PC, #56] [0x080044FC] 
+  0x080044C2:  6008         STR        R0, [R1]
+  0x080044C4:  490E         LDR        R1, =0xE000E280          ; [PC, #56] [0x08004500] 
+  0x080044C6:  6008         STR        R0, [R1]
+  0x080044C8:  480E         LDR        R0, =0x1FFF0000          ; [PC, #56] [0x08004504] 
+  0x080044CA:  6801         LDR        R1, [R0]
+  0x080044CC:  6840         LDR        R0, [R0, #4]
+  0x080044CE:  F381 8808    MSR        MSP, R1
+  0x080044D2:  490D         LDR        R1, =0x40021040          ; [PC, #52] [0x08004508] 
+  0x080044D4:  680A         LDR        R2, [R1]
+  0x080044D6:  2301         MOVS       R3, #1
+  0x080044D8:  431A         ORRS       R2, R3
+  0x080044DA:  600A         STR        R2, [R1]
+  0x080044DC:  6809         LDR        R1, [R1]
+  0x080044DE:  4019         ANDS       R1, R3
+  0x080044E0:  9101         STR        R1, [SP, #4]
+  0x080044E2:  9901         LDR        R1, [SP, #4]
+  0x080044E4:  4909         LDR        R1, =0x40010000          ; [PC, #36] [0x0800450C] 
+  0x080044E6:  680A         LDR        R2, [R1]
+  0x080044E8:  431A         ORRS       R2, R3
+  0x080044EA:  2302         MOVS       R3, #2
+  0x080044EC:  439A         BICS       R2, R3
+  0x080044EE:  600A         STR        R2, [R1]
+  0x080044F0:  B662         CPSIE      i
+  0x080044F2:  4780         BLX        R0
+
.L1:
+  0x080044F4:  4806         LDR        R0, =0x0800653B          ; [PC, #24] [0x08004510] 
+  0x080044F6:  F000 FE2F    BL         puts                     ; 0x08005158
+  0x080044FA:  E7FB         B          .L1                      ; 0x080044F4
+  0x080044FC:  E000E180     DC.W       0xE000E180
+  0x08004500:  E000E280     DC.W       0xE000E280
+  0x08004504:  1FFF0000     DC.W       0x1FFF0000
+  0x08004508:  40021040     DC.W       0x40021040
+  0x0800450C:  40010000     DC.W       0x40010000
+  0x08004510:  0800653B     DC.W       0800653B               ; R_ARM_ABS32
+
+

Section .text.HAL_UART_ErrorCallback from PowerPro_lto.o, size=168, align=4

+
+
HAL_UART_ErrorCallback:
+  0x08004514:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x08004516:  4604         MOV        R4, R0
+  0x08004518:  4820         LDR        R0, =modbusData          ; [PC, #128] [0x0800459C] =0x20000000 
+  0x0800451A:  2101         MOVS       R1, #1
+  0x0800451C:  7501         STRB       R1, [R0, #20]
+  0x0800451E:  4920         LDR        R1, =0x00000231          ; [PC, #128] [0x080045A0] 
+  0x08004520:  2200         MOVS       R2, #0
+  0x08004522:  5442         STRB       R2, [R0, R1]
+  0x08004524:  215C         MOVS       R1, #92
+  0x08004526:  5A61         LDRH       R1, [R4, R1]
+  0x08004528:  2280         MOVS       R2, #128
+  0x0800452A:  58A2         LDR        R2, [R4, R2]
+  0x0800452C:  6812         LDR        R2, [R2]
+  0x0800452E:  6852         LDR        R2, [R2, #4]
+  0x08004530:  1A89         SUBS       R1, R1, R2
+  0x08004532:  2245         MOVS       R2, #69
+  0x08004534:  00D2         LSLS       R2, R2, #3
+  0x08004536:  5081         STR        R1, [R0, R2]
+  0x08004538:  4625         MOV        R5, R4
+  0x0800453A:  3580         ADDS       R5, #128
+  0x0800453C:  6928         LDR        R0, [R5, #16]
+  0x0800453E:  6928         LDR        R0, [R5, #16]
+  0x08004540:  2804         CMP        R0, #4
+  0x08004542:  D102         BNE        .L1                      ; 0x0800454A
+  0x08004544:  4817         LDR        R0, =0x0800681C          ; [PC, #92] [0x080045A4] 
+  0x08004546:  F000 FE61    BL         printf                   ; 0x0800520C
+
.L1:
+  0x0800454A:  6928         LDR        R0, [R5, #16]
+  0x0800454C:  2801         CMP        R0, #1
+  0x0800454E:  D102         BNE        .L2                      ; 0x08004556
+  0x08004550:  4815         LDR        R0, =0x0800682C          ; [PC, #84] [0x080045A8] 
+  0x08004552:  F000 FE5B    BL         printf                   ; 0x0800520C
+
.L2:
+  0x08004556:  6928         LDR        R0, [R5, #16]
+  0x08004558:  2802         CMP        R0, #2
+  0x0800455A:  D102         BNE        .L3                      ; 0x08004562
+  0x0800455C:  4813         LDR        R0, =0x0800683C          ; [PC, #76] [0x080045AC] 
+  0x0800455E:  F000 FE55    BL         printf                   ; 0x0800520C
+
.L3:
+  0x08004562:  6928         LDR        R0, [R5, #16]
+  0x08004564:  2810         CMP        R0, #16
+  0x08004566:  D102         BNE        .L4                      ; 0x0800456E
+  0x08004568:  4811         LDR        R0, =0x0800654C          ; [PC, #68] [0x080045B0] 
+  0x0800456A:  F000 FE4F    BL         printf                   ; 0x0800520C
+
.L4:
+  0x0800456E:  6928         LDR        R0, [R5, #16]
+  0x08004570:  2810         CMP        R0, #16
+  0x08004572:  D102         BNE        .L5                      ; 0x0800457A
+  0x08004574:  480E         LDR        R0, =0x0800654C          ; [PC, #56] [0x080045B0] 
+  0x08004576:  F000 FE49    BL         printf                   ; 0x0800520C
+
.L5:
+  0x0800457A:  6928         LDR        R0, [R5, #16]
+  0x0800457C:  2808         CMP        R0, #8
+  0x0800457E:  D102         BNE        .L6                      ; 0x08004586
+  0x08004580:  480C         LDR        R0, =0x0800655D          ; [PC, #48] [0x080045B4] 
+  0x08004582:  F000 FE43    BL         printf                   ; 0x0800520C
+
.L6:
+  0x08004586:  6DA1         LDR        R1, [R4, #88]
+  0x08004588:  4620         MOV        R0, R4
+  0x0800458A:  F7FC FFE1    BL         HAL_UART_Receive_DMA     ; 0x08001550
+  0x0800458E:  2800         CMP        R0, #0
+  0x08004590:  D002         BEQ        .L7                      ; 0x08004598
+  0x08004592:  4809         LDR        R0, =0x080061A0          ; [PC, #36] [0x080045B8] 
+  0x08004594:  F000 FE3A    BL         printf                   ; 0x0800520C
+
.L7:
+  0x08004598:  BDB0         POP        {R4-R5, R7, PC}
+  0x0800459A:  46C0         NOP
+  0x0800459C:  20000000     DC.W       modbusData
+  0x080045A0:  00000231     DC.W       0x00000231
+  0x080045A4:  0800681C     DC.W       0800681C               ; R_ARM_ABS32
+  0x080045A8:  0800682C     DC.W       0800682C               ; R_ARM_ABS32
+  0x080045AC:  0800683C     DC.W       0800683C               ; R_ARM_ABS32
+  0x080045B0:  0800654C     DC.W       0800654C               ; R_ARM_ABS32
+  0x080045B4:  0800655D     DC.W       0800655D               ; R_ARM_ABS32
+  0x080045B8:  080061A0     DC.W       080061A0               ; R_ARM_ABS32
+
+

Section .text.mbCrc16 from PowerPro_lto.o, size=56, align=4

+
+
mbCrc16:
+  0x080045BC:  B530         PUSH       {R4-R5, LR}
+  0x080045BE:  2200         MOVS       R2, #0
+  0x080045C0:  4B0A         LDR        R3, =0x0000FFFF          ; [PC, #40] [0x080045EC] 
+
.L1:
+  0x080045C2:  428A         CMP        R2, R1
+  0x080045C4:  D00F         BEQ        .L5                      ; 0x080045E6
+  0x080045C6:  5C84         LDRB       R4, [R0, R2]
+  0x080045C8:  4063         EORS       R3, R4
+  0x080045CA:  2407         MOVS       R4, #7
+  0x080045CC:  43E4         MVNS       R4, R4
+
.L2:
+  0x080045CE:  2C00         CMP        R4, #0
+  0x080045D0:  D007         BEQ        .L4                      ; 0x080045E2
+  0x080045D2:  085D         LSRS       R5, R3, #1
+  0x080045D4:  07DB         LSLS       R3, R3, #31
+  0x080045D6:  D001         BEQ        .L3                      ; 0x080045DC
+  0x080045D8:  4B05         LDR        R3, =0x0000A001          ; [PC, #20] [0x080045F0] 
+  0x080045DA:  405D         EORS       R5, R3
+
.L3:
+  0x080045DC:  462B         MOV        R3, R5
+  0x080045DE:  1C64         ADDS       R4, R4, #1
+  0x080045E0:  E7F5         B          .L2                      ; 0x080045CE
+
.L4:
+  0x080045E2:  1C52         ADDS       R2, R2, #1
+  0x080045E4:  E7ED         B          .L1                      ; 0x080045C2
+
.L5:
+  0x080045E6:  B298         UXTH       R0, R3
+  0x080045E8:  BD30         POP        {R4-R5, PC}
+  0x080045EA:  46C0         NOP
+  0x080045EC:  0000FFFF     DC.W       0x0000FFFF
+  0x080045F0:  0000A001     DC.W       0x0000A001
+
+

Section .text.MODE_SECONDARYPROTECTION_Exec from PowerPro_lto.o, size=1660, align=4

+
+
MODE_SECONDARYPROTECTION_Exec:
+  0x080045F4:  B5F0         PUSH       {R4-R7, LR}
+  0x080045F6:  B085         SUB        SP, SP, #20
+  0x080045F8:  4F07         LDR        R7, =autoRetryMode       ; [PC, #28] [0x08004618] =0x200006F4 
+  0x080045FA:  6038         STR        R0, [R7]
+  0x080045FC:  4D07         LDR        R5, =0x50000418          ; [PC, #28] [0x0800461C] 
+  0x080045FE:  4628         MOV        R0, R5
+  0x08004600:  3808         SUBS       R0, #8
+  0x08004602:  6800         LDR        R0, [R0]
+  0x08004604:  0740         LSLS       R0, R0, #29
+  0x08004606:  0FC0         LSRS       R0, R0, #31
+  0x08004608:  4C05         LDR        R4, =smState.160         ; [PC, #20] [0x08004620] =0x20000732 
+  0x0800460A:  7821         LDRB       R1, [R4]
+  0x0800460C:  4479         ADD        R1, PC
+  0x0800460E:  7909         LDRB       R1, [R1, #4]
+  0x08004610:  0049         LSLS       R1, R1, #1
+  0x08004612:  448F         ADD        PC, R1
+  0x08004614:  07           DC.B       0x07                     ; '\x07'
+  0x08004615:  A2           DC.B       0xA2                     ; '\xA2'
+  0x08004616:  2C           DC.B       0x2C                     ; ','
+  0x08004617:  91           DC.B       0x91                     ; '\x91'
+  0x08004618:  200006F4     DC.W       autoRetryMode
+  0x0800461C:  50000418     DC.W       0x50000418
+  0x08004620:  20000732     DC.W       smState.160
+  0x08004624:  49DA         LDR        R1, =0x50000010          ; [PC, #0x0368] [0x08004990] 
+  0x08004626:  680A         LDR        R2, [R1]
+  0x08004628:  07D2         LSLS       R2, R2, #31
+  0x0800462A:  D000         BEQ        .L1                      ; 0x0800462E
+  0x0800462C:  6809         LDR        R1, [R1]
+
.L1:
+  0x0800462E:  4AD9         LDR        R2, =buttonState         ; [PC, #0x0364] [0x08004994] =0x2000073A 
+  0x08004630:  7811         LDRB       R1, [R2]
+  0x08004632:  2901         CMP        R1, #1
+  0x08004634:  D000         BEQ        .L2                      ; 0x08004638
+  0x08004636:  E27C         B          .L23                     ; 0x08004B32
+
.L2:
+  0x08004638:  2800         CMP        R0, #0
+  0x0800463A:  D000         BEQ        .L3                      ; 0x0800463E
+  0x0800463C:  E258         B          .L21                     ; 0x08004AF0
+
.L3:
+  0x0800463E:  2020         MOVS       R0, #32
+  0x08004640:  6028         STR        R0, [R5]
+  0x08004642:  2000         MOVS       R0, #0
+  0x08004644:  7010         STRB       R0, [R2]
+  0x08004646:  207D         MOVS       R0, #125
+  0x08004648:  0080         LSLS       R0, R0, #2
+  0x0800464A:  4AD3         LDR        R2, =onTimeCounter       ; [PC, #0x034C] [0x08004998] =0x200006A8 
+  0x0800464C:  6010         STR        R0, [R2]
+  0x0800464E:  48D3         LDR        R0, =onTimeRT            ; [PC, #0x034C] [0x0800499C] =0x2000073C 
+  0x08004650:  7001         STRB       R1, [R0]
+  0x08004652:  48D3         LDR        R0, =offTimeRT           ; [PC, #0x034C] [0x080049A0] =0x20000748 
+  0x08004654:  7001         STRB       R1, [R0]
+  0x08004656:  48D3         LDR        R0, =blinkModeRT         ; [PC, #0x034C] [0x080049A4] =0x20000754 
+  0x08004658:  7001         STRB       R1, [R0]
+  0x0800465A:  48D3         LDR        R0, =numberOfBlinks      ; [PC, #0x034C] [0x080049A8] =0x200006BC 
+  0x0800465C:  2703         MOVS       R7, #3
+  0x0800465E:  6007         STR        R7, [R0]
+  0x08004660:  48D2         LDR        R0, =blinkCounter        ; [PC, #0x0348] [0x080049AC] =0x200006EC 
+  0x08004662:  6007         STR        R7, [R0]
+  0x08004664:  03CA         LSLS       R2, R1, #15
+  0x08004666:  48D2         LDR        R0, =0x08006711          ; [PC, #0x0348] [0x080049B0] 
+  0x08004668:  4BD2         LDR        R3, =onTimeCounterRT     ; [PC, #0x0348] [0x080049B4] =0x2000069C 
+  0x0800466A:  4ED3         LDR        R6, =pauseTime           ; [PC, #0x034C] [0x080049B8] =0x20000734 
+  0x0800466C:  E257         B          .L22                     ; 0x08004B1E
+  0x0800466E:  2800         CMP        R0, #0
+  0x08004670:  D134         BNE        .L4                      ; 0x080046DC
+  0x08004672:  2008         MOVS       R0, #8
+  0x08004674:  6128         STR        R0, [R5, #16]
+  0x08004676:  2010         MOVS       R0, #16
+  0x08004678:  6028         STR        R0, [R5]
+  0x0800467A:  49D0         LDR        R1, =relaisState         ; [PC, #0x0340] [0x080049BC] =0x20000730 
+  0x0800467C:  2000         MOVS       R0, #0
+  0x0800467E:  7008         STRB       R0, [R1]
+  0x08004680:  49CF         LDR        R1, =onTimeCounterRESET  ; [PC, #0x033C] [0x080049C0] =0x200006A0 
+  0x08004682:  2232         MOVS       R2, #50
+  0x08004684:  600A         STR        R2, [R1]
+  0x08004686:  2120         MOVS       R1, #32
+  0x08004688:  6029         STR        R1, [R5]
+  0x0800468A:  217D         MOVS       R1, #125
+  0x0800468C:  0089         LSLS       R1, R1, #2
+  0x0800468E:  4AC2         LDR        R2, =onTimeCounter       ; [PC, #0x0308] [0x08004998] =0x200006A8 
+  0x08004690:  6011         STR        R1, [R2]
+  0x08004692:  2101         MOVS       R1, #1
+  0x08004694:  038B         LSLS       R3, R1, #14
+  0x08004696:  4ACB         LDR        R2, =0x50000818          ; [PC, #0x032C] [0x080049C4] 
+  0x08004698:  6113         STR        R3, [R2, #16]
+  0x0800469A:  4BCB         LDR        R3, =offTimeCounterGN    ; [PC, #0x032C] [0x080049C8] =0x200006B4 
+  0x0800469C:  6018         STR        R0, [R3]
+  0x0800469E:  4BCB         LDR        R3, =blinkModeGN         ; [PC, #0x032C] [0x080049CC] =0x20000758 
+  0x080046A0:  7018         STRB       R0, [R3]
+  0x080046A2:  4BCB         LDR        R3, =onTimeCounterGN     ; [PC, #0x032C] [0x080049D0] =0x200006A4 
+  0x080046A4:  6018         STR        R0, [R3]
+  0x080046A6:  4BBD         LDR        R3, =onTimeRT            ; [PC, #0x02F4] [0x0800499C] =0x2000073C 
+  0x080046A8:  7019         STRB       R1, [R3]
+  0x080046AA:  4BBD         LDR        R3, =offTimeRT           ; [PC, #0x02F4] [0x080049A0] =0x20000748 
+  0x080046AC:  7019         STRB       R1, [R3]
+  0x080046AE:  4BBD         LDR        R3, =blinkModeRT         ; [PC, #0x02F4] [0x080049A4] =0x20000754 
+  0x080046B0:  7019         STRB       R1, [R3]
+  0x080046B2:  4BBD         LDR        R3, =numberOfBlinks      ; [PC, #0x02F4] [0x080049A8] =0x200006BC 
+  0x080046B4:  2603         MOVS       R6, #3
+  0x080046B6:  601E         STR        R6, [R3]
+  0x080046B8:  4BBC         LDR        R3, =blinkCounter        ; [PC, #0x02F0] [0x080049AC] =0x200006EC 
+  0x080046BA:  601E         STR        R6, [R3]
+  0x080046BC:  4BBE         LDR        R3, =pauseTime           ; [PC, #0x02F8] [0x080049B8] =0x20000734 
+  0x080046BE:  7019         STRB       R1, [R3]
+  0x080046C0:  03C9         LSLS       R1, R1, #15
+  0x080046C2:  6011         STR        R1, [R2]
+  0x080046C4:  49B3         LDR        R1, =buttonState         ; [PC, #0x02CC] [0x08004994] =0x2000073A 
+  0x080046C6:  7008         STRB       R0, [R1]
+  0x080046C8:  48BA         LDR        R0, =onTimeCounterRT     ; [PC, #0x02E8] [0x080049B4] =0x2000069C 
+  0x080046CA:  21C8         MOVS       R1, #200
+  0x080046CC:  6001         STR        R1, [R0]
+  0x080046CE:  48C1         LDR        R0, =0x080068F4          ; [PC, #0x0304] [0x080049D4] 
+  0x080046D0:  F000 FD42    BL         puts                     ; 0x08005158
+  0x080046D4:  48B6         LDR        R0, =0x08006711          ; [PC, #0x02D8] [0x080049B0] 
+  0x080046D6:  F000 FD3F    BL         puts                     ; 0x08005158
+  0x080046DA:  7026         STRB       R6, [R4]
+
.L4:
+  0x080046DC:  48AD         LDR        R0, =buttonState         ; [PC, #0x02B4] [0x08004994] =0x2000073A 
+  0x080046DE:  7800         LDRB       R0, [R0]
+  0x080046E0:  2800         CMP        R0, #0
+  0x080046E2:  D000         BEQ        .L5                      ; 0x080046E6
+  0x080046E4:  E25B         B          .L25                     ; 0x08004B9E
+
.L5:
+  0x080046E6:  2008         MOVS       R0, #8
+  0x080046E8:  6128         STR        R0, [R5, #16]
+  0x080046EA:  2010         MOVS       R0, #16
+  0x080046EC:  6028         STR        R0, [R5]
+  0x080046EE:  48B3         LDR        R0, =relaisState         ; [PC, #0x02CC] [0x080049BC] =0x20000730 
+  0x080046F0:  2600         MOVS       R6, #0
+  0x080046F2:  7006         STRB       R6, [R0]
+  0x080046F4:  48B2         LDR        R0, =onTimeCounterRESET  ; [PC, #0x02C8] [0x080049C0] =0x200006A0 
+  0x080046F6:  2132         MOVS       R1, #50
+  0x080046F8:  6001         STR        R1, [R0]
+  0x080046FA:  2020         MOVS       R0, #32
+  0x080046FC:  6128         STR        R0, [R5, #16]
+  0x080046FE:  48B6         LDR        R0, =offTimeCounter      ; [PC, #0x02D8] [0x080049D8] =0x200006B8 
+  0x08004700:  6006         STR        R6, [R0]
+  0x08004702:  48B6         LDR        R0, =alarmMode           ; [PC, #0x02D8] [0x080049DC] =0x2000075C 
+  0x08004704:  7006         STRB       R6, [R0]
+  0x08004706:  48A4         LDR        R0, =onTimeCounter       ; [PC, #0x0290] [0x08004998] =0x200006A8 
+  0x08004708:  6006         STR        R6, [R0]
+  0x0800470A:  2001         MOVS       R0, #1
+  0x0800470C:  0381         LSLS       R1, R0, #14
+  0x0800470E:  4AAD         LDR        R2, =0x50000818          ; [PC, #0x02B4] [0x080049C4] 
+  0x08004710:  6111         STR        R1, [R2, #16]
+  0x08004712:  49AD         LDR        R1, =offTimeCounterGN    ; [PC, #0x02B4] [0x080049C8] =0x200006B4 
+  0x08004714:  600E         STR        R6, [R1]
+  0x08004716:  49AD         LDR        R1, =blinkModeGN         ; [PC, #0x02B4] [0x080049CC] =0x20000758 
+  0x08004718:  700E         STRB       R6, [R1]
+  0x0800471A:  49AD         LDR        R1, =onTimeCounterGN     ; [PC, #0x02B4] [0x080049D0] =0x200006A4 
+  0x0800471C:  600E         STR        R6, [R1]
+  0x0800471E:  03C0         LSLS       R0, R0, #15
+  0x08004720:  6110         STR        R0, [R2, #16]
+  0x08004722:  48AF         LDR        R0, =offTimeCounterRT    ; [PC, #0x02BC] [0x080049E0] =0x200006B0 
+  0x08004724:  6006         STR        R6, [R0]
+  0x08004726:  489F         LDR        R0, =blinkModeRT         ; [PC, #0x027C] [0x080049A4] =0x20000754 
+  0x08004728:  7006         STRB       R6, [R0]
+  0x0800472A:  48A2         LDR        R0, =onTimeCounterRT     ; [PC, #0x0288] [0x080049B4] =0x2000069C 
+  0x0800472C:  6006         STR        R6, [R0]
+  0x0800472E:  48AD         LDR        R0, =0x08006271          ; [PC, #0x02B4] [0x080049E4] 
+  0x08004730:  F000 FD12    BL         puts                     ; 0x08005158
+  0x08004734:  7026         STRB       R6, [R4]
+  0x08004736:  E232         B          .L25                     ; 0x08004B9E
+  0x08004738:  4E96         LDR        R6, =buttonState         ; [PC, #0x0258] [0x08004994] =0x2000073A 
+  0x0800473A:  7831         LDRB       R1, [R6]
+  0x0800473C:  2901         CMP        R1, #1
+  0x0800473E:  D000         BEQ        .L6                      ; 0x08004742
+  0x08004740:  E181         B          .L17                     ; 0x08004A46
+
.L6:
+  0x08004742:  2800         CMP        R0, #0
+  0x08004744:  D000         BEQ        .L7                      ; 0x08004748
+  0x08004746:  E155         B          .L16                     ; 0x080049F4
+
.L7:
+  0x08004748:  2020         MOVS       R0, #32
+  0x0800474A:  6028         STR        R0, [R5]
+  0x0800474C:  2000         MOVS       R0, #0
+  0x0800474E:  7030         STRB       R0, [R6]
+  0x08004750:  207D         MOVS       R0, #125
+  0x08004752:  0080         LSLS       R0, R0, #2
+  0x08004754:  4990         LDR        R1, =onTimeCounter       ; [PC, #0x0240] [0x08004998] =0x200006A8 
+  0x08004756:  6008         STR        R0, [R1]
+  0x08004758:  E1AF         B          .L18                     ; 0x08004ABA
+  0x0800475A:  217D         MOVS       R1, #125
+  0x0800475C:  008B         LSLS       R3, R1, #2
+  0x0800475E:  2701         MOVS       R7, #1
+  0x08004760:  03BA         LSLS       R2, R7, #14
+  0x08004762:  03FE         LSLS       R6, R7, #15
+  0x08004764:  9604         STR        R6, [SP, #16]
+  0x08004766:  2800         CMP        R0, #0
+  0x08004768:  4E96         LDR        R6, =0x50000818          ; [PC, #0x0258] [0x080049C4] 
+  0x0800476A:  D12F         BNE        .L8                      ; 0x080047CC
+  0x0800476C:  2008         MOVS       R0, #8
+  0x0800476E:  6128         STR        R0, [R5, #16]
+  0x08004770:  2010         MOVS       R0, #16
+  0x08004772:  6028         STR        R0, [R5]
+  0x08004774:  4991         LDR        R1, =relaisState         ; [PC, #0x0244] [0x080049BC] =0x20000730 
+  0x08004776:  2000         MOVS       R0, #0
+  0x08004778:  7008         STRB       R0, [R1]
+  0x0800477A:  4991         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0244] [0x080049C0] =0x200006A0 
+  0x0800477C:  4614         MOV        R4, R2
+  0x0800477E:  2232         MOVS       R2, #50
+  0x08004780:  600A         STR        R2, [R1]
+  0x08004782:  2120         MOVS       R1, #32
+  0x08004784:  6029         STR        R1, [R5]
+  0x08004786:  4984         LDR        R1, =onTimeCounter       ; [PC, #0x0210] [0x08004998] =0x200006A8 
+  0x08004788:  600B         STR        R3, [R1]
+  0x0800478A:  6134         STR        R4, [R6, #16]
+  0x0800478C:  4C96         LDR        R4, =smState.160         ; [PC, #0x0258] [0x080049E8] =0x20000732 
+  0x0800478E:  498E         LDR        R1, =offTimeCounterGN    ; [PC, #0x0238] [0x080049C8] =0x200006B4 
+  0x08004790:  6008         STR        R0, [R1]
+  0x08004792:  498E         LDR        R1, =blinkModeGN         ; [PC, #0x0238] [0x080049CC] =0x20000758 
+  0x08004794:  7008         STRB       R0, [R1]
+  0x08004796:  498E         LDR        R1, =onTimeCounterGN     ; [PC, #0x0238] [0x080049D0] =0x200006A4 
+  0x08004798:  6008         STR        R0, [R1]
+  0x0800479A:  4980         LDR        R1, =onTimeRT            ; [PC, #0x0200] [0x0800499C] =0x2000073C 
+  0x0800479C:  700F         STRB       R7, [R1]
+  0x0800479E:  4980         LDR        R1, =offTimeRT           ; [PC, #0x0200] [0x080049A0] =0x20000748 
+  0x080047A0:  700F         STRB       R7, [R1]
+  0x080047A2:  4980         LDR        R1, =blinkModeRT         ; [PC, #0x0200] [0x080049A4] =0x20000754 
+  0x080047A4:  700F         STRB       R7, [R1]
+  0x080047A6:  4980         LDR        R1, =numberOfBlinks      ; [PC, #0x0200] [0x080049A8] =0x200006BC 
+  0x080047A8:  2203         MOVS       R2, #3
+  0x080047AA:  600A         STR        R2, [R1]
+  0x080047AC:  497F         LDR        R1, =blinkCounter        ; [PC, #0x01FC] [0x080049AC] =0x200006EC 
+  0x080047AE:  600A         STR        R2, [R1]
+  0x080047B0:  4981         LDR        R1, =pauseTime           ; [PC, #0x0204] [0x080049B8] =0x20000734 
+  0x080047B2:  700F         STRB       R7, [R1]
+  0x080047B4:  9904         LDR        R1, [SP, #16]
+  0x080047B6:  6031         STR        R1, [R6]
+  0x080047B8:  4976         LDR        R1, =buttonState         ; [PC, #0x01D8] [0x08004994] =0x2000073A 
+  0x080047BA:  7008         STRB       R0, [R1]
+  0x080047BC:  487D         LDR        R0, =onTimeCounterRT     ; [PC, #0x01F4] [0x080049B4] =0x2000069C 
+  0x080047BE:  21C8         MOVS       R1, #200
+  0x080047C0:  6001         STR        R1, [R0]
+  0x080047C2:  4884         LDR        R0, =0x080068F4          ; [PC, #0x0210] [0x080049D4] 
+  0x080047C4:  F000 FCC8    BL         puts                     ; 0x08005158
+  0x080047C8:  4879         LDR        R0, =0x08006711          ; [PC, #0x01E4] [0x080049B0] 
+  0x080047CA:  E0DC         B          .L15                     ; 0x08004986
+
.L8:
+  0x080047CC:  9100         STR        R1, [SP, #0]
+  0x080047CE:  9302         STR        R3, [SP, #8]
+  0x080047D0:  486F         LDR        R0, =0x50000010          ; [PC, #0x01BC] [0x08004990] 
+  0x080047D2:  6801         LDR        R1, [R0]
+  0x080047D4:  07C9         LSLS       R1, R1, #31
+  0x080047D6:  9203         STR        R2, [SP, #12]
+  0x080047D8:  9B04         LDR        R3, [SP, #16]
+  0x080047DA:  D003         BEQ        .L9                      ; 0x080047E4
+  0x080047DC:  6800         LDR        R0, [R0]
+  0x080047DE:  0780         LSLS       R0, R0, #30
+  0x080047E0:  D500         BPL        .L9                      ; 0x080047E4
+  0x080047E2:  E1DE         B          .L26                     ; 0x08004BA2
+
.L9:
+  0x080047E4:  4881         LDR        R0, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x0204] [0x080049EC] =0x20000704 
+  0x080047E6:  2100         MOVS       R1, #0
+  0x080047E8:  6001         STR        R1, [R0]
+
.L10:
+  0x080047EA:  9101         STR        R1, [SP, #4]
+  0x080047EC:  48FB         LDR        R0, =buttonState         ; [PC, #0x03EC] [0x08004BDC] =0x2000073A 
+  0x080047EE:  7800         LDRB       R0, [R0]
+  0x080047F0:  2800         CMP        R0, #0
+  0x080047F2:  D125         BNE        .L11                     ; 0x08004840
+  0x080047F4:  2008         MOVS       R0, #8
+  0x080047F6:  6128         STR        R0, [R5, #16]
+  0x080047F8:  2010         MOVS       R0, #16
+  0x080047FA:  6028         STR        R0, [R5]
+  0x080047FC:  48F8         LDR        R0, =relaisState         ; [PC, #0x03E0] [0x08004BE0] =0x20000730 
+  0x080047FE:  2600         MOVS       R6, #0
+  0x08004800:  7006         STRB       R6, [R0]
+  0x08004802:  486F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01BC] [0x080049C0] =0x200006A0 
+  0x08004804:  2132         MOVS       R1, #50
+  0x08004806:  6001         STR        R1, [R0]
+  0x08004808:  2020         MOVS       R0, #32
+  0x0800480A:  6028         STR        R0, [R5]
+  0x0800480C:  48F7         LDR        R0, =onTimeCounter       ; [PC, #0x03DC] [0x08004BEC] =0x200006A8 
+  0x0800480E:  21C8         MOVS       R1, #200
+  0x08004810:  6001         STR        R1, [R0]
+  0x08004812:  48F9         LDR        R0, =0x50000818          ; [PC, #0x03E4] [0x08004BF8] 
+  0x08004814:  6102         STR        R2, [R0, #16]
+  0x08004816:  486C         LDR        R0, =offTimeCounterGN    ; [PC, #0x01B0] [0x080049C8] =0x200006B4 
+  0x08004818:  6006         STR        R6, [R0]
+  0x0800481A:  48F6         LDR        R0, =blinkModeGN         ; [PC, #0x03D8] [0x08004BF4] =0x20000758 
+  0x0800481C:  7006         STRB       R6, [R0]
+  0x0800481E:  48F7         LDR        R0, =onTimeCounterGN     ; [PC, #0x03DC] [0x08004BFC] =0x200006A4 
+  0x08004820:  6006         STR        R6, [R0]
+  0x08004822:  48F5         LDR        R0, =0x50000818          ; [PC, #0x03D4] [0x08004BF8] 
+  0x08004824:  6103         STR        R3, [R0, #16]
+  0x08004826:  48F6         LDR        R0, =offTimeCounterRT    ; [PC, #0x03D8] [0x08004C00] =0x200006B0 
+  0x08004828:  6006         STR        R6, [R0]
+  0x0800482A:  48F6         LDR        R0, =blinkModeRT         ; [PC, #0x03D8] [0x08004C04] =0x20000754 
+  0x0800482C:  7006         STRB       R6, [R0]
+  0x0800482E:  48F6         LDR        R0, =onTimeCounterRT     ; [PC, #0x03D8] [0x08004C08] =0x2000069C 
+  0x08004830:  6006         STR        R6, [R0]
+  0x08004832:  486C         LDR        R0, =0x08006271          ; [PC, #0x01B0] [0x080049E4] 
+  0x08004834:  F000 FC90    BL         puts                     ; 0x08005158
+  0x08004838:  9A03         LDR        R2, [SP, #12]
+  0x0800483A:  9B04         LDR        R3, [SP, #16]
+  0x0800483C:  7026         STRB       R6, [R4]
+  0x0800483E:  4EEE         LDR        R6, =0x50000818          ; [PC, #0x03B8] [0x08004BF8] 
+
.L11:
+  0x08004840:  9800         LDR        R0, [SP, #0]
+  0x08004842:  00C0         LSLS       R0, R0, #3
+  0x08004844:  496A         LDR        R1, =dropLimitCounter    ; [PC, #0x01A8] [0x080049F0] =0x200006E4 
+  0x08004846:  6809         LDR        R1, [R1]
+  0x08004848:  4281         CMP        R1, R0
+  0x0800484A:  D136         BNE        .L12                     ; 0x080048BA
+  0x0800484C:  2008         MOVS       R0, #8
+  0x0800484E:  6128         STR        R0, [R5, #16]
+  0x08004850:  2010         MOVS       R0, #16
+  0x08004852:  6028         STR        R0, [R5]
+  0x08004854:  48E2         LDR        R0, =relaisState         ; [PC, #0x0388] [0x08004BE0] =0x20000730 
+  0x08004856:  2600         MOVS       R6, #0
+  0x08004858:  7006         STRB       R6, [R0]
+  0x0800485A:  48FB         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03EC] [0x08004C48] =0x200006A0 
+  0x0800485C:  2132         MOVS       R1, #50
+  0x0800485E:  6001         STR        R1, [R0]
+  0x08004860:  2020         MOVS       R0, #32
+  0x08004862:  6028         STR        R0, [R5]
+  0x08004864:  48E1         LDR        R0, =onTimeCounter       ; [PC, #0x0384] [0x08004BEC] =0x200006A8 
+  0x08004866:  9902         LDR        R1, [SP, #8]
+  0x08004868:  6001         STR        R1, [R0]
+  0x0800486A:  48E3         LDR        R0, =0x50000818          ; [PC, #0x038C] [0x08004BF8] 
+  0x0800486C:  6102         STR        R2, [R0, #16]
+  0x0800486E:  48EB         LDR        R0, =offTimeCounterGN    ; [PC, #0x03AC] [0x08004C1C] =0x200006B4 
+  0x08004870:  6006         STR        R6, [R0]
+  0x08004872:  48E0         LDR        R0, =blinkModeGN         ; [PC, #0x0380] [0x08004BF4] =0x20000758 
+  0x08004874:  7006         STRB       R6, [R0]
+  0x08004876:  48E1         LDR        R0, =onTimeCounterGN     ; [PC, #0x0384] [0x08004BFC] =0x200006A4 
+  0x08004878:  6006         STR        R6, [R0]
+  0x0800487A:  48E9         LDR        R0, =onTimeRT            ; [PC, #0x03A4] [0x08004C20] =0x2000073C 
+  0x0800487C:  7007         STRB       R7, [R0]
+  0x0800487E:  48E9         LDR        R0, =offTimeRT           ; [PC, #0x03A4] [0x08004C24] =0x20000748 
+  0x08004880:  7007         STRB       R7, [R0]
+  0x08004882:  48E0         LDR        R0, =blinkModeRT         ; [PC, #0x0380] [0x08004C04] =0x20000754 
+  0x08004884:  7007         STRB       R7, [R0]
+  0x08004886:  48E8         LDR        R0, =numberOfBlinks      ; [PC, #0x03A0] [0x08004C28] =0x200006BC 
+  0x08004888:  2104         MOVS       R1, #4
+  0x0800488A:  6001         STR        R1, [R0]
+  0x0800488C:  48E7         LDR        R0, =blinkCounter        ; [PC, #0x039C] [0x08004C2C] =0x200006EC 
+  0x0800488E:  6001         STR        R1, [R0]
+  0x08004890:  48E7         LDR        R0, =pauseTime           ; [PC, #0x039C] [0x08004C30] =0x20000734 
+  0x08004892:  7007         STRB       R7, [R0]
+  0x08004894:  48D8         LDR        R0, =0x50000818          ; [PC, #0x0360] [0x08004BF8] 
+  0x08004896:  6003         STR        R3, [R0]
+  0x08004898:  48D0         LDR        R0, =buttonState         ; [PC, #0x0340] [0x08004BDC] =0x2000073A 
+  0x0800489A:  7006         STRB       R6, [R0]
+  0x0800489C:  48DA         LDR        R0, =onTimeCounterRT     ; [PC, #0x0368] [0x08004C08] =0x2000069C 
+  0x0800489E:  21C8         MOVS       R1, #200
+  0x080048A0:  6001         STR        R1, [R0]
+  0x080048A2:  48EF         LDR        R0, =0x080066F4          ; [PC, #0x03BC] [0x08004C60] 
+  0x080048A4:  F000 FC58    BL         puts                     ; 0x08005158
+  0x080048A8:  48E8         LDR        R0, =0x08006711          ; [PC, #0x03A0] [0x08004C4C] 
+  0x080048AA:  F000 FC55    BL         puts                     ; 0x08005158
+  0x080048AE:  9B04         LDR        R3, [SP, #16]
+  0x080048B0:  2003         MOVS       R0, #3
+  0x080048B2:  7020         STRB       R0, [R4]
+  0x080048B4:  48E9         LDR        R0, =dropLimitCounter    ; [PC, #0x03A4] [0x08004C5C] =0x200006E4 
+  0x080048B6:  6006         STR        R6, [R0]
+  0x080048B8:  4ECF         LDR        R6, =0x50000818          ; [PC, #0x033C] [0x08004BF8] 
+
.L12:
+  0x080048BA:  9801         LDR        R0, [SP, #4]
+  0x080048BC:  2800         CMP        R0, #0
+  0x080048BE:  D032         BEQ        .L13                     ; 0x08004926
+  0x080048C0:  2008         MOVS       R0, #8
+  0x080048C2:  6128         STR        R0, [R5, #16]
+  0x080048C4:  2010         MOVS       R0, #16
+  0x080048C6:  6028         STR        R0, [R5]
+  0x080048C8:  49C5         LDR        R1, =relaisState         ; [PC, #0x0314] [0x08004BE0] =0x20000730 
+  0x080048CA:  2000         MOVS       R0, #0
+  0x080048CC:  7008         STRB       R0, [R1]
+  0x080048CE:  49DE         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0378] [0x08004C48] =0x200006A0 
+  0x080048D0:  2232         MOVS       R2, #50
+  0x080048D2:  600A         STR        R2, [R1]
+  0x080048D4:  2120         MOVS       R1, #32
+  0x080048D6:  6029         STR        R1, [R5]
+  0x080048D8:  49C4         LDR        R1, =onTimeCounter       ; [PC, #0x0310] [0x08004BEC] =0x200006A8 
+  0x080048DA:  9A02         LDR        R2, [SP, #8]
+  0x080048DC:  600A         STR        R2, [R1]
+  0x080048DE:  9903         LDR        R1, [SP, #12]
+  0x080048E0:  6131         STR        R1, [R6, #16]
+  0x080048E2:  49CE         LDR        R1, =offTimeCounterGN    ; [PC, #0x0338] [0x08004C1C] =0x200006B4 
+  0x080048E4:  6008         STR        R0, [R1]
+  0x080048E6:  49C3         LDR        R1, =blinkModeGN         ; [PC, #0x030C] [0x08004BF4] =0x20000758 
+  0x080048E8:  7008         STRB       R0, [R1]
+  0x080048EA:  49C4         LDR        R1, =onTimeCounterGN     ; [PC, #0x0310] [0x08004BFC] =0x200006A4 
+  0x080048EC:  6008         STR        R0, [R1]
+  0x080048EE:  49CC         LDR        R1, =onTimeRT            ; [PC, #0x0330] [0x08004C20] =0x2000073C 
+  0x080048F0:  700F         STRB       R7, [R1]
+  0x080048F2:  49CC         LDR        R1, =offTimeRT           ; [PC, #0x0330] [0x08004C24] =0x20000748 
+  0x080048F4:  700F         STRB       R7, [R1]
+  0x080048F6:  49C3         LDR        R1, =blinkModeRT         ; [PC, #0x030C] [0x08004C04] =0x20000754 
+  0x080048F8:  700F         STRB       R7, [R1]
+  0x080048FA:  49CB         LDR        R1, =numberOfBlinks      ; [PC, #0x032C] [0x08004C28] =0x200006BC 
+  0x080048FC:  2202         MOVS       R2, #2
+  0x080048FE:  600A         STR        R2, [R1]
+  0x08004900:  49CA         LDR        R1, =blinkCounter        ; [PC, #0x0328] [0x08004C2C] =0x200006EC 
+  0x08004902:  600A         STR        R2, [R1]
+  0x08004904:  49CA         LDR        R1, =pauseTime           ; [PC, #0x0328] [0x08004C30] =0x20000734 
+  0x08004906:  700F         STRB       R7, [R1]
+  0x08004908:  6033         STR        R3, [R6]
+  0x0800490A:  49B4         LDR        R1, =buttonState         ; [PC, #0x02D0] [0x08004BDC] =0x2000073A 
+  0x0800490C:  7008         STRB       R0, [R1]
+  0x0800490E:  48BE         LDR        R0, =onTimeCounterRT     ; [PC, #0x02F8] [0x08004C08] =0x2000069C 
+  0x08004910:  21C8         MOVS       R1, #200
+  0x08004912:  6001         STR        R1, [R0]
+  0x08004914:  48D3         LDR        R0, =0x080068B8          ; [PC, #0x034C] [0x08004C64] 
+  0x08004916:  F000 FC1F    BL         puts                     ; 0x08005158
+  0x0800491A:  48CC         LDR        R0, =0x08006711          ; [PC, #0x0330] [0x08004C4C] 
+  0x0800491C:  F000 FC1C    BL         puts                     ; 0x08005158
+  0x08004920:  9B04         LDR        R3, [SP, #16]
+  0x08004922:  2003         MOVS       R0, #3
+  0x08004924:  7020         STRB       R0, [R4]
+
.L13:
+  0x08004926:  48D0         LDR        R0, =temp                ; [PC, #0x0340] [0x08004C68] =0x20000690 
+  0x08004928:  6800         LDR        R0, [R0]
+  0x0800492A:  2851         CMP        R0, #81
+  0x0800492C:  DA00         BGE        .L14                     ; 0x08004930
+  0x0800492E:  E136         B          .L25                     ; 0x08004B9E
+
.L14:
+  0x08004930:  2008         MOVS       R0, #8
+  0x08004932:  6128         STR        R0, [R5, #16]
+  0x08004934:  2010         MOVS       R0, #16
+  0x08004936:  6028         STR        R0, [R5]
+  0x08004938:  49A9         LDR        R1, =relaisState         ; [PC, #0x02A4] [0x08004BE0] =0x20000730 
+  0x0800493A:  2000         MOVS       R0, #0
+  0x0800493C:  7008         STRB       R0, [R1]
+  0x0800493E:  49C2         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0308] [0x08004C48] =0x200006A0 
+  0x08004940:  2232         MOVS       R2, #50
+  0x08004942:  600A         STR        R2, [R1]
+  0x08004944:  2120         MOVS       R1, #32
+  0x08004946:  6029         STR        R1, [R5]
+  0x08004948:  49A8         LDR        R1, =onTimeCounter       ; [PC, #0x02A0] [0x08004BEC] =0x200006A8 
+  0x0800494A:  9A02         LDR        R2, [SP, #8]
+  0x0800494C:  600A         STR        R2, [R1]
+  0x0800494E:  9903         LDR        R1, [SP, #12]
+  0x08004950:  6131         STR        R1, [R6, #16]
+  0x08004952:  49B2         LDR        R1, =offTimeCounterGN    ; [PC, #0x02C8] [0x08004C1C] =0x200006B4 
+  0x08004954:  6008         STR        R0, [R1]
+  0x08004956:  49A7         LDR        R1, =blinkModeGN         ; [PC, #0x029C] [0x08004BF4] =0x20000758 
+  0x08004958:  7008         STRB       R0, [R1]
+  0x0800495A:  49A8         LDR        R1, =onTimeCounterGN     ; [PC, #0x02A0] [0x08004BFC] =0x200006A4 
+  0x0800495C:  6008         STR        R0, [R1]
+  0x0800495E:  49B0         LDR        R1, =onTimeRT            ; [PC, #0x02C0] [0x08004C20] =0x2000073C 
+  0x08004960:  700F         STRB       R7, [R1]
+  0x08004962:  49B0         LDR        R1, =offTimeRT           ; [PC, #0x02C0] [0x08004C24] =0x20000748 
+  0x08004964:  700F         STRB       R7, [R1]
+  0x08004966:  49A7         LDR        R1, =blinkModeRT         ; [PC, #0x029C] [0x08004C04] =0x20000754 
+  0x08004968:  700F         STRB       R7, [R1]
+  0x0800496A:  49AF         LDR        R1, =numberOfBlinks      ; [PC, #0x02BC] [0x08004C28] =0x200006BC 
+  0x0800496C:  2205         MOVS       R2, #5
+  0x0800496E:  600A         STR        R2, [R1]
+  0x08004970:  49AE         LDR        R1, =blinkCounter        ; [PC, #0x02B8] [0x08004C2C] =0x200006EC 
+  0x08004972:  600A         STR        R2, [R1]
+  0x08004974:  49AE         LDR        R1, =pauseTime           ; [PC, #0x02B8] [0x08004C30] =0x20000734 
+  0x08004976:  700F         STRB       R7, [R1]
+  0x08004978:  6033         STR        R3, [R6]
+  0x0800497A:  4998         LDR        R1, =buttonState         ; [PC, #0x0260] [0x08004BDC] =0x2000073A 
+  0x0800497C:  7008         STRB       R0, [R1]
+  0x0800497E:  48A2         LDR        R0, =onTimeCounterRT     ; [PC, #0x0288] [0x08004C08] =0x2000069C 
+  0x08004980:  21C8         MOVS       R1, #200
+  0x08004982:  6001         STR        R1, [R0]
+  0x08004984:  48B9         LDR        R0, =0x08006294          ; [PC, #0x02E4] [0x08004C6C] 
+
.L15:
+  0x08004986:  F000 FBE7    BL         puts                     ; 0x08005158
+  0x0800498A:  2003         MOVS       R0, #3
+  0x0800498C:  E106         B          .L24                     ; 0x08004B9C
+  0x0800498E:  46C0         NOP
+  0x08004990:  50000010     DC.W       0x50000010
+  0x08004994:  2000073A     DC.W       buttonState
+  0x08004998:  200006A8     DC.W       onTimeCounter
+  0x0800499C:  2000073C     DC.W       onTimeRT
+  0x080049A0:  20000748     DC.W       offTimeRT
+  0x080049A4:  20000754     DC.W       blinkModeRT
+  0x080049A8:  200006BC     DC.W       numberOfBlinks
+  0x080049AC:  200006EC     DC.W       blinkCounter
+  0x080049B0:  08006711     DC.W       08006711               ; R_ARM_ABS32
+  0x080049B4:  2000069C     DC.W       onTimeCounterRT
+  0x080049B8:  20000734     DC.W       pauseTime
+  0x080049BC:  20000730     DC.W       relaisState
+  0x080049C0:  200006A0     DC.W       onTimeCounterRESET
+  0x080049C4:  50000818     DC.W       0x50000818
+  0x080049C8:  200006B4     DC.W       offTimeCounterGN
+  0x080049CC:  20000758     DC.W       blinkModeGN
+  0x080049D0:  200006A4     DC.W       onTimeCounterGN
+  0x080049D4:  080068F4     DC.W       080068F4               ; R_ARM_ABS32
+  0x080049D8:  200006B8     DC.W       offTimeCounter
+  0x080049DC:  2000075C     DC.W       alarmMode
+  0x080049E0:  200006B0     DC.W       offTimeCounterRT
+  0x080049E4:  08006271     DC.W       08006271               ; R_ARM_ABS32
+  0x080049E8:  20000732     DC.W       smState.160
+  0x080049EC:  20000704     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
+  0x080049F0:  200006E4     DC.W       dropLimitCounter
+
.L16:
+  0x080049F4:  2010         MOVS       R0, #16
+  0x080049F6:  6128         STR        R0, [R5, #16]
+  0x080049F8:  2008         MOVS       R0, #8
+  0x080049FA:  6028         STR        R0, [R5]
+  0x080049FC:  4878         LDR        R0, =relaisState         ; [PC, #0x01E0] [0x08004BE0] =0x20000730 
+  0x080049FE:  2601         MOVS       R6, #1
+  0x08004A00:  7006         STRB       R6, [R0]
+  0x08004A02:  4878         LDR        R0, =onTimeCounterSET    ; [PC, #0x01E0] [0x08004BE4] =0x20000698 
+  0x08004A04:  2132         MOVS       R1, #50
+  0x08004A06:  6001         STR        R1, [R0]
+  0x08004A08:  2020         MOVS       R0, #32
+  0x08004A0A:  6028         STR        R0, [R5]
+  0x08004A0C:  4876         LDR        R0, =onTimeGN            ; [PC, #0x01D8] [0x08004BE8] =0x20000740 
+  0x08004A0E:  7006         STRB       R6, [R0]
+  0x08004A10:  4876         LDR        R0, =onTimeCounter       ; [PC, #0x01D8] [0x08004BEC] =0x200006A8 
+  0x08004A12:  21C8         MOVS       R1, #200
+  0x08004A14:  6001         STR        R1, [R0]
+  0x08004A16:  4876         LDR        R0, =offTimeGN           ; [PC, #0x01D8] [0x08004BF0] =0x2000074C 
+  0x08004A18:  7006         STRB       R6, [R0]
+  0x08004A1A:  4876         LDR        R0, =blinkModeGN         ; [PC, #0x01D8] [0x08004BF4] =0x20000758 
+  0x08004A1C:  7006         STRB       R6, [R0]
+  0x08004A1E:  03B0         LSLS       R0, R6, #14
+  0x08004A20:  4A75         LDR        R2, =0x50000818          ; [PC, #0x01D4] [0x08004BF8] 
+  0x08004A22:  6010         STR        R0, [R2]
+  0x08004A24:  4875         LDR        R0, =onTimeCounterGN     ; [PC, #0x01D4] [0x08004BFC] =0x200006A4 
+  0x08004A26:  6001         STR        R1, [R0]
+  0x08004A28:  03F0         LSLS       R0, R6, #15
+  0x08004A2A:  6110         STR        R0, [R2, #16]
+  0x08004A2C:  4874         LDR        R0, =offTimeCounterRT    ; [PC, #0x01D0] [0x08004C00] =0x200006B0 
+  0x08004A2E:  2100         MOVS       R1, #0
+  0x08004A30:  6001         STR        R1, [R0]
+  0x08004A32:  4874         LDR        R0, =blinkModeRT         ; [PC, #0x01D0] [0x08004C04] =0x20000754 
+  0x08004A34:  7001         STRB       R1, [R0]
+  0x08004A36:  4874         LDR        R0, =onTimeCounterRT     ; [PC, #0x01D0] [0x08004C08] =0x2000069C 
+  0x08004A38:  6001         STR        R1, [R0]
+  0x08004A3A:  4874         LDR        R0, =0x080064B1          ; [PC, #0x01D0] [0x08004C0C] 
+  0x08004A3C:  F000 FB8C    BL         puts                     ; 0x08005158
+  0x08004A40:  7026         STRB       R6, [R4]
+  0x08004A42:  4E66         LDR        R6, =buttonState         ; [PC, #0x0198] [0x08004BDC] =0x2000073A 
+  0x08004A44:  7831         LDRB       R1, [R6]
+
.L17:
+  0x08004A46:  2902         CMP        R1, #2
+  0x08004A48:  D137         BNE        .L18                     ; 0x08004ABA
+  0x08004A4A:  2010         MOVS       R0, #16
+  0x08004A4C:  6128         STR        R0, [R5, #16]
+  0x08004A4E:  2008         MOVS       R0, #8
+  0x08004A50:  6028         STR        R0, [R5]
+  0x08004A52:  4963         LDR        R1, =relaisState         ; [PC, #0x018C] [0x08004BE0] =0x20000730 
+  0x08004A54:  2001         MOVS       R0, #1
+  0x08004A56:  7008         STRB       R0, [R1]
+  0x08004A58:  4962         LDR        R1, =onTimeCounterSET    ; [PC, #0x0188] [0x08004BE4] =0x20000698 
+  0x08004A5A:  2232         MOVS       R2, #50
+  0x08004A5C:  600A         STR        R2, [R1]
+  0x08004A5E:  496C         LDR        R1, =onTime              ; [PC, #0x01B0] [0x08004C10] =0x20000744 
+  0x08004A60:  7008         STRB       R0, [R1]
+  0x08004A62:  496C         LDR        R1, =offTime             ; [PC, #0x01B0] [0x08004C14] =0x20000750 
+  0x08004A64:  7008         STRB       R0, [R1]
+  0x08004A66:  496C         LDR        R1, =alarmMode           ; [PC, #0x01B0] [0x08004C18] =0x2000075C 
+  0x08004A68:  7008         STRB       R0, [R1]
+  0x08004A6A:  2120         MOVS       R1, #32
+  0x08004A6C:  6029         STR        R1, [R5]
+  0x08004A6E:  4A5F         LDR        R2, =onTimeCounter       ; [PC, #0x017C] [0x08004BEC] =0x200006A8 
+  0x08004A70:  21C8         MOVS       R1, #200
+  0x08004A72:  6011         STR        R1, [R2]
+  0x08004A74:  0383         LSLS       R3, R0, #14
+  0x08004A76:  4A60         LDR        R2, =0x50000818          ; [PC, #0x0180] [0x08004BF8] 
+  0x08004A78:  6013         STR        R3, [R2]
+  0x08004A7A:  4B60         LDR        R3, =onTimeCounterGN     ; [PC, #0x0180] [0x08004BFC] =0x200006A4 
+  0x08004A7C:  2500         MOVS       R5, #0
+  0x08004A7E:  601D         STR        R5, [R3]
+  0x08004A80:  4B5C         LDR        R3, =blinkModeGN         ; [PC, #0x0170] [0x08004BF4] =0x20000758 
+  0x08004A82:  701D         STRB       R5, [R3]
+  0x08004A84:  4B65         LDR        R3, =offTimeCounterGN    ; [PC, #0x0194] [0x08004C1C] =0x200006B4 
+  0x08004A86:  601D         STR        R5, [R3]
+  0x08004A88:  03C3         LSLS       R3, R0, #15
+  0x08004A8A:  6113         STR        R3, [R2, #16]
+  0x08004A8C:  4E64         LDR        R6, =onTimeRT            ; [PC, #0x0190] [0x08004C20] =0x2000073C 
+  0x08004A8E:  7030         STRB       R0, [R6]
+  0x08004A90:  4E5B         LDR        R6, =offTimeCounterRT    ; [PC, #0x016C] [0x08004C00] =0x200006B0 
+  0x08004A92:  6035         STR        R5, [R6]
+  0x08004A94:  4E51         LDR        R6, =buttonState         ; [PC, #0x0144] [0x08004BDC] =0x2000073A 
+  0x08004A96:  4D63         LDR        R5, =offTimeRT           ; [PC, #0x018C] [0x08004C24] =0x20000748 
+  0x08004A98:  7028         STRB       R0, [R5]
+  0x08004A9A:  4D5A         LDR        R5, =blinkModeRT         ; [PC, #0x0168] [0x08004C04] =0x20000754 
+  0x08004A9C:  7028         STRB       R0, [R5]
+  0x08004A9E:  4D62         LDR        R5, =numberOfBlinks      ; [PC, #0x0188] [0x08004C28] =0x200006BC 
+  0x08004AA0:  6028         STR        R0, [R5]
+  0x08004AA2:  4D62         LDR        R5, =blinkCounter        ; [PC, #0x0188] [0x08004C2C] =0x200006EC 
+  0x08004AA4:  6028         STR        R0, [R5]
+  0x08004AA6:  4D62         LDR        R5, =pauseTime           ; [PC, #0x0188] [0x08004C30] =0x20000734 
+  0x08004AA8:  7028         STRB       R0, [R5]
+  0x08004AAA:  6013         STR        R3, [R2]
+  0x08004AAC:  4856         LDR        R0, =onTimeCounterRT     ; [PC, #0x0158] [0x08004C08] =0x2000069C 
+  0x08004AAE:  6001         STR        R1, [R0]
+  0x08004AB0:  4860         LDR        R0, =0x080066CB          ; [PC, #0x0180] [0x08004C34] 
+  0x08004AB2:  F000 FB51    BL         puts                     ; 0x08005158
+  0x08004AB6:  2002         MOVS       R0, #2
+  0x08004AB8:  7020         STRB       R0, [R4]
+
.L18:
+  0x08004ABA:  6838         LDR        R0, [R7]
+  0x08004ABC:  2801         CMP        R0, #1
+  0x08004ABE:  D16E         BNE        .L25                     ; 0x08004B9E
+  0x08004AC0:  485D         LDR        R0, =uwTick              ; [PC, #0x0174] [0x08004C38] =0x2000068C 
+  0x08004AC2:  6802         LDR        R2, [R0]
+  0x08004AC4:  495D         LDR        R1, =SECONDARYPROTECTION_SM_Error.oldTimeMSTick ; [PC, #0x0174] [0x08004C3C] =0x20000714 
+  0x08004AC6:  680B         LDR        R3, [R1]
+  0x08004AC8:  4293         CMP        R3, R2
+  0x08004ACA:  D102         BNE        .L19                     ; 0x08004AD2
+  0x08004ACC:  485C         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0170] [0x08004C40] =0x2000070C 
+  0x08004ACE:  6800         LDR        R0, [R0]
+  0x08004AD0:  E005         B          .L20                     ; 0x08004ADE
+
.L19:
+  0x08004AD2:  6800         LDR        R0, [R0]
+  0x08004AD4:  6008         STR        R0, [R1]
+  0x08004AD6:  495A         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0168] [0x08004C40] =0x2000070C 
+  0x08004AD8:  6808         LDR        R0, [R1]
+  0x08004ADA:  1C40         ADDS       R0, R0, #1
+  0x08004ADC:  6008         STR        R0, [R1]
+
.L20:
+  0x08004ADE:  4959         LDR        R1, =0x0036EE81          ; [PC, #0x0164] [0x08004C44] 
+  0x08004AE0:  4288         CMP        R0, R1
+  0x08004AE2:  D35C         BCC        .L25                     ; 0x08004B9E
+  0x08004AE4:  4856         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0158] [0x08004C40] =0x2000070C 
+  0x08004AE6:  2100         MOVS       R1, #0
+  0x08004AE8:  6001         STR        R1, [R0]
+  0x08004AEA:  2001         MOVS       R0, #1
+  0x08004AEC:  7030         STRB       R0, [R6]
+  0x08004AEE:  E056         B          .L25                     ; 0x08004B9E
+
.L21:
+  0x08004AF0:  2010         MOVS       R0, #16
+  0x08004AF2:  6128         STR        R0, [R5, #16]
+  0x08004AF4:  2008         MOVS       R0, #8
+  0x08004AF6:  6028         STR        R0, [R5]
+  0x08004AF8:  4839         LDR        R0, =relaisState         ; [PC, #228] [0x08004BE0] =0x20000730 
+  0x08004AFA:  7001         STRB       R1, [R0]
+  0x08004AFC:  4839         LDR        R0, =onTimeCounterSET    ; [PC, #228] [0x08004BE4] =0x20000698 
+  0x08004AFE:  2232         MOVS       R2, #50
+  0x08004B00:  6002         STR        R2, [R0]
+  0x08004B02:  2020         MOVS       R0, #32
+  0x08004B04:  6028         STR        R0, [R5]
+  0x08004B06:  4838         LDR        R0, =onTimeGN            ; [PC, #224] [0x08004BE8] =0x20000740 
+  0x08004B08:  7001         STRB       R1, [R0]
+  0x08004B0A:  4838         LDR        R0, =onTimeCounter       ; [PC, #224] [0x08004BEC] =0x200006A8 
+  0x08004B0C:  22C8         MOVS       R2, #200
+  0x08004B0E:  6002         STR        R2, [R0]
+  0x08004B10:  4837         LDR        R0, =offTimeGN           ; [PC, #220] [0x08004BF0] =0x2000074C 
+  0x08004B12:  7001         STRB       R1, [R0]
+  0x08004B14:  038A         LSLS       R2, R1, #14
+  0x08004B16:  483D         LDR        R0, =0x080064B1          ; [PC, #244] [0x08004C0C] 
+  0x08004B18:  4B38         LDR        R3, =onTimeCounterGN     ; [PC, #224] [0x08004BFC] =0x200006A4 
+  0x08004B1A:  4E36         LDR        R6, =blinkModeGN         ; [PC, #216] [0x08004BF4] =0x20000758 
+  0x08004B1C:  460F         MOV        R7, R1
+
.L22:
+  0x08004B1E:  7031         STRB       R1, [R6]
+  0x08004B20:  4935         LDR        R1, =0x50000818          ; [PC, #212] [0x08004BF8] 
+  0x08004B22:  600A         STR        R2, [R1]
+  0x08004B24:  21C8         MOVS       R1, #200
+  0x08004B26:  6019         STR        R1, [R3]
+  0x08004B28:  F000 FB16    BL         puts                     ; 0x08005158
+  0x08004B2C:  7027         STRB       R7, [R4]
+  0x08004B2E:  482B         LDR        R0, =buttonState         ; [PC, #172] [0x08004BDC] =0x2000073A 
+  0x08004B30:  7801         LDRB       R1, [R0]
+
.L23:
+  0x08004B32:  2902         CMP        R1, #2
+  0x08004B34:  D133         BNE        .L25                     ; 0x08004B9E
+  0x08004B36:  2010         MOVS       R0, #16
+  0x08004B38:  6128         STR        R0, [R5, #16]
+  0x08004B3A:  2008         MOVS       R0, #8
+  0x08004B3C:  6028         STR        R0, [R5]
+  0x08004B3E:  4928         LDR        R1, =relaisState         ; [PC, #160] [0x08004BE0] =0x20000730 
+  0x08004B40:  2001         MOVS       R0, #1
+  0x08004B42:  7008         STRB       R0, [R1]
+  0x08004B44:  4927         LDR        R1, =onTimeCounterSET    ; [PC, #156] [0x08004BE4] =0x20000698 
+  0x08004B46:  2232         MOVS       R2, #50
+  0x08004B48:  600A         STR        R2, [R1]
+  0x08004B4A:  4931         LDR        R1, =onTime              ; [PC, #196] [0x08004C10] =0x20000744 
+  0x08004B4C:  7008         STRB       R0, [R1]
+  0x08004B4E:  4931         LDR        R1, =offTime             ; [PC, #196] [0x08004C14] =0x20000750 
+  0x08004B50:  7008         STRB       R0, [R1]
+  0x08004B52:  4931         LDR        R1, =alarmMode           ; [PC, #196] [0x08004C18] =0x2000075C 
+  0x08004B54:  7008         STRB       R0, [R1]
+  0x08004B56:  2120         MOVS       R1, #32
+  0x08004B58:  6029         STR        R1, [R5]
+  0x08004B5A:  4A24         LDR        R2, =onTimeCounter       ; [PC, #144] [0x08004BEC] =0x200006A8 
+  0x08004B5C:  21C8         MOVS       R1, #200
+  0x08004B5E:  6011         STR        R1, [R2]
+  0x08004B60:  0383         LSLS       R3, R0, #14
+  0x08004B62:  4A25         LDR        R2, =0x50000818          ; [PC, #148] [0x08004BF8] 
+  0x08004B64:  6013         STR        R3, [R2]
+  0x08004B66:  4B25         LDR        R3, =onTimeCounterGN     ; [PC, #148] [0x08004BFC] =0x200006A4 
+  0x08004B68:  2500         MOVS       R5, #0
+  0x08004B6A:  601D         STR        R5, [R3]
+  0x08004B6C:  4B21         LDR        R3, =blinkModeGN         ; [PC, #132] [0x08004BF4] =0x20000758 
+  0x08004B6E:  701D         STRB       R5, [R3]
+  0x08004B70:  4B2A         LDR        R3, =offTimeCounterGN    ; [PC, #168] [0x08004C1C] =0x200006B4 
+  0x08004B72:  601D         STR        R5, [R3]
+  0x08004B74:  4B2A         LDR        R3, =onTimeRT            ; [PC, #168] [0x08004C20] =0x2000073C 
+  0x08004B76:  7018         STRB       R0, [R3]
+  0x08004B78:  4B2A         LDR        R3, =offTimeRT           ; [PC, #168] [0x08004C24] =0x20000748 
+  0x08004B7A:  7018         STRB       R0, [R3]
+  0x08004B7C:  4B21         LDR        R3, =blinkModeRT         ; [PC, #132] [0x08004C04] =0x20000754 
+  0x08004B7E:  7018         STRB       R0, [R3]
+  0x08004B80:  4B29         LDR        R3, =numberOfBlinks      ; [PC, #164] [0x08004C28] =0x200006BC 
+  0x08004B82:  6018         STR        R0, [R3]
+  0x08004B84:  4B29         LDR        R3, =blinkCounter        ; [PC, #164] [0x08004C2C] =0x200006EC 
+  0x08004B86:  6018         STR        R0, [R3]
+  0x08004B88:  4B29         LDR        R3, =pauseTime           ; [PC, #164] [0x08004C30] =0x20000734 
+  0x08004B8A:  7018         STRB       R0, [R3]
+  0x08004B8C:  03C0         LSLS       R0, R0, #15
+  0x08004B8E:  6010         STR        R0, [R2]
+  0x08004B90:  481D         LDR        R0, =onTimeCounterRT     ; [PC, #116] [0x08004C08] =0x2000069C 
+  0x08004B92:  6001         STR        R1, [R0]
+  0x08004B94:  4827         LDR        R0, =0x080066CB          ; [PC, #156] [0x08004C34] 
+  0x08004B96:  F000 FADF    BL         puts                     ; 0x08005158
+  0x08004B9A:  2002         MOVS       R0, #2
+
.L24:
+  0x08004B9C:  7020         STRB       R0, [R4]
+
.L25:
+  0x08004B9E:  B005         ADD        SP, SP, #20
+  0x08004BA0:  BDF0         POP        {R4-R7, PC}
+
.L26:
+  0x08004BA2:  482B         LDR        R0, =SECONDARYPROTECTION_SM_On.oldtime ; [PC, #172] [0x08004C50] =0x200006FC 
+  0x08004BA4:  6802         LDR        R2, [R0]
+  0x08004BA6:  4924         LDR        R1, =uwTick              ; [PC, #144] [0x08004C38] =0x2000068C 
+  0x08004BA8:  680B         LDR        R3, [R1]
+  0x08004BAA:  4293         CMP        R3, R2
+  0x08004BAC:  D103         BNE        .L27                     ; 0x08004BB6
+  0x08004BAE:  2100         MOVS       R1, #0
+  0x08004BB0:  9B04         LDR        R3, [SP, #16]
+  0x08004BB2:  9A03         LDR        R2, [SP, #12]
+  0x08004BB4:  E619         B          .L10                     ; 0x080047EA
+
.L27:
+  0x08004BB6:  6809         LDR        R1, [R1]
+  0x08004BB8:  6001         STR        R1, [R0]
+  0x08004BBA:  4926         LDR        R1, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter ; [PC, #152] [0x08004C54] =0x20000704 
+  0x08004BBC:  680B         LDR        R3, [R1]
+  0x08004BBE:  1C5A         ADDS       R2, R3, #1
+  0x08004BC0:  2000         MOVS       R0, #0
+  0x08004BC2:  4E25         LDR        R6, =0x0000752F          ; [PC, #148] [0x08004C58] 
+  0x08004BC4:  42B3         CMP        R3, R6
+  0x08004BC6:  4603         MOV        R3, R0
+  0x08004BC8:  DC00         BGT        .L28                     ; 0x08004BCC
+  0x08004BCA:  4613         MOV        R3, R2
+
.L28:
+  0x08004BCC:  600B         STR        R3, [R1]
+  0x08004BCE:  4639         MOV        R1, R7
+  0x08004BD0:  DC00         BGT        .L29                     ; 0x08004BD4
+  0x08004BD2:  2100         MOVS       R1, #0
+
.L29:
+  0x08004BD4:  9B04         LDR        R3, [SP, #16]
+  0x08004BD6:  4E08         LDR        R6, =0x50000818          ; [PC, #32] [0x08004BF8] 
+  0x08004BD8:  9A03         LDR        R2, [SP, #12]
+  0x08004BDA:  E606         B          .L10                     ; 0x080047EA
+  0x08004BDC:  2000073A     DC.W       buttonState
+  0x08004BE0:  20000730     DC.W       relaisState
+  0x08004BE4:  20000698     DC.W       onTimeCounterSET
+  0x08004BE8:  20000740     DC.W       onTimeGN
+  0x08004BEC:  200006A8     DC.W       onTimeCounter
+  0x08004BF0:  2000074C     DC.W       offTimeGN
+  0x08004BF4:  20000758     DC.W       blinkModeGN
+  0x08004BF8:  50000818     DC.W       0x50000818
+  0x08004BFC:  200006A4     DC.W       onTimeCounterGN
+  0x08004C00:  200006B0     DC.W       offTimeCounterRT
+  0x08004C04:  20000754     DC.W       blinkModeRT
+  0x08004C08:  2000069C     DC.W       onTimeCounterRT
+  0x08004C0C:  080064B1     DC.W       080064B1               ; R_ARM_ABS32
+  0x08004C10:  20000744     DC.W       onTime
+  0x08004C14:  20000750     DC.W       offTime
+  0x08004C18:  2000075C     DC.W       alarmMode
+  0x08004C1C:  200006B4     DC.W       offTimeCounterGN
+  0x08004C20:  2000073C     DC.W       onTimeRT
+  0x08004C24:  20000748     DC.W       offTimeRT
+  0x08004C28:  200006BC     DC.W       numberOfBlinks
+  0x08004C2C:  200006EC     DC.W       blinkCounter
+  0x08004C30:  20000734     DC.W       pauseTime
+  0x08004C34:  080066CB     DC.W       080066CB               ; R_ARM_ABS32
+  0x08004C38:  2000068C     DC.W       uwTick
+  0x08004C3C:  20000714     DC.W       SECONDARYPROTECTION_SM_Error.oldTimeMSTick
+  0x08004C40:  2000070C     DC.W       SECONDARYPROTECTION_SM_Error.retry_counter
+  0x08004C44:  0036EE81     DC.W       0x0036EE81
+  0x08004C48:  200006A0     DC.W       onTimeCounterRESET
+  0x08004C4C:  08006711     DC.W       08006711               ; R_ARM_ABS32
+  0x08004C50:  200006FC     DC.W       SECONDARYPROTECTION_SM_On.oldtime
+  0x08004C54:  20000704     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
+  0x08004C58:  0000752F     DC.W       0x0000752F
+  0x08004C5C:  200006E4     DC.W       dropLimitCounter
+  0x08004C60:  080066F4     DC.W       080066F4               ; R_ARM_ABS32
+  0x08004C64:  080068B8     DC.W       080068B8               ; R_ARM_ABS32
+  0x08004C68:  20000690     DC.W       temp
+  0x08004C6C:  08006294     DC.W       08006294               ; R_ARM_ABS32
+
+

Section .text.MODE_SECONDARYPROTECTION_PLUS_Exec from PowerPro_lto.o, size=1108, align=4

+
+
MODE_SECONDARYPROTECTION_PLUS_Exec:
+  0x08004C70:  B5F0         PUSH       {R4-R7, LR}
+  0x08004C72:  B085         SUB        SP, SP, #20
+  0x08004C74:  4EEC         LDR        R6, =autoRetryMode.170   ; [PC, #0x03B0] [0x08005028] =0x200006F0 
+  0x08004C76:  6030         STR        R0, [R6]
+  0x08004C78:  4DEC         LDR        R5, =0x50000418          ; [PC, #0x03B0] [0x0800502C] 
+  0x08004C7A:  4628         MOV        R0, R5
+  0x08004C7C:  3808         SUBS       R0, #8
+  0x08004C7E:  6800         LDR        R0, [R0]
+  0x08004C80:  0740         LSLS       R0, R0, #29
+  0x08004C82:  0FC0         LSRS       R0, R0, #31
+  0x08004C84:  4BEA         LDR        R3, =smState.171         ; [PC, #0x03A8] [0x08005030] =0x20000731 
+  0x08004C86:  7819         LDRB       R1, [R3]
+  0x08004C88:  2902         CMP        R1, #2
+  0x08004C8A:  D038         BEQ        .L1                      ; 0x08004CFE
+  0x08004C8C:  2901         CMP        R1, #1
+  0x08004C8E:  D145         BNE        .L2                      ; 0x08004D1C
+  0x08004C90:  217D         MOVS       R1, #125
+  0x08004C92:  008A         LSLS       R2, R1, #2
+  0x08004C94:  2701         MOVS       R7, #1
+  0x08004C96:  03BC         LSLS       R4, R7, #14
+  0x08004C98:  03FB         LSLS       R3, R7, #15
+  0x08004C9A:  2800         CMP        R0, #0
+  0x08004C9C:  4EED         LDR        R6, =0x50000818          ; [PC, #0x03B4] [0x08005054] 
+  0x08004C9E:  D162         BNE        .L5                      ; 0x08004D66
+  0x08004CA0:  2008         MOVS       R0, #8
+  0x08004CA2:  6128         STR        R0, [R5, #16]
+  0x08004CA4:  2010         MOVS       R0, #16
+  0x08004CA6:  6028         STR        R0, [R5]
+  0x08004CA8:  49E4         LDR        R1, =relaisState         ; [PC, #0x0390] [0x0800503C] =0x20000730 
+  0x08004CAA:  2000         MOVS       R0, #0
+  0x08004CAC:  7008         STRB       R0, [R1]
+  0x08004CAE:  49F6         LDR        R1, =onTimeCounterRESET  ; [PC, #0x03D8] [0x08005088] =0x200006A0 
+  0x08004CB0:  4616         MOV        R6, R2
+  0x08004CB2:  2232         MOVS       R2, #50
+  0x08004CB4:  600A         STR        R2, [R1]
+  0x08004CB6:  2120         MOVS       R1, #32
+  0x08004CB8:  6029         STR        R1, [R5]
+  0x08004CBA:  49E3         LDR        R1, =onTimeCounter       ; [PC, #0x038C] [0x08005048] =0x200006A8 
+  0x08004CBC:  600E         STR        R6, [R1]
+  0x08004CBE:  4DE5         LDR        R5, =0x50000818          ; [PC, #0x0394] [0x08005054] 
+  0x08004CC0:  612C         STR        R4, [R5, #16]
+  0x08004CC2:  49F2         LDR        R1, =offTimeCounterGN    ; [PC, #0x03C8] [0x0800508C] =0x200006B4 
+  0x08004CC4:  6008         STR        R0, [R1]
+  0x08004CC6:  49E2         LDR        R1, =blinkModeGN         ; [PC, #0x0388] [0x08005050] =0x20000758 
+  0x08004CC8:  7008         STRB       R0, [R1]
+  0x08004CCA:  49E3         LDR        R1, =onTimeCounterGN     ; [PC, #0x038C] [0x08005058] =0x200006A4 
+  0x08004CCC:  6008         STR        R0, [R1]
+  0x08004CCE:  49F2         LDR        R1, =onTimeRT            ; [PC, #0x03C8] [0x08005098] =0x2000073C 
+  0x08004CD0:  700F         STRB       R7, [R1]
+  0x08004CD2:  49F2         LDR        R1, =offTimeRT           ; [PC, #0x03C8] [0x0800509C] =0x20000748 
+  0x08004CD4:  700F         STRB       R7, [R1]
+  0x08004CD6:  49E2         LDR        R1, =blinkModeRT         ; [PC, #0x0388] [0x08005060] =0x20000754 
+  0x08004CD8:  700F         STRB       R7, [R1]
+  0x08004CDA:  49F1         LDR        R1, =numberOfBlinks      ; [PC, #0x03C4] [0x080050A0] =0x200006BC 
+  0x08004CDC:  2203         MOVS       R2, #3
+  0x08004CDE:  600A         STR        R2, [R1]
+  0x08004CE0:  49F0         LDR        R1, =blinkCounter        ; [PC, #0x03C0] [0x080050A4] =0x200006EC 
+  0x08004CE2:  600A         STR        R2, [R1]
+  0x08004CE4:  49F0         LDR        R1, =pauseTime           ; [PC, #0x03C0] [0x080050A8] =0x20000734 
+  0x08004CE6:  700F         STRB       R7, [R1]
+  0x08004CE8:  602B         STR        R3, [R5]
+  0x08004CEA:  49D2         LDR        R1, =buttonState         ; [PC, #0x0348] [0x08005034] =0x2000073A 
+  0x08004CEC:  7008         STRB       R0, [R1]
+  0x08004CEE:  48DD         LDR        R0, =onTimeCounterRT     ; [PC, #0x0374] [0x08005064] =0x2000069C 
+  0x08004CF0:  21C8         MOVS       R1, #200
+  0x08004CF2:  6001         STR        R1, [R0]
+  0x08004CF4:  48F2         LDR        R0, =0x080068F4          ; [PC, #0x03C8] [0x080050C0] 
+  0x08004CF6:  F000 FA2F    BL         puts                     ; 0x08005158
+  0x08004CFA:  48ED         LDR        R0, =0x08006711          ; [PC, #0x03B4] [0x080050B0] 
+  0x08004CFC:  E18C         B          .L23                     ; 0x08005018
+
.L1:
+  0x08004CFE:  4CCD         LDR        R4, =buttonState         ; [PC, #0x0334] [0x08005034] =0x2000073A 
+  0x08004D00:  7821         LDRB       R1, [R4]
+  0x08004D02:  2901         CMP        R1, #1
+  0x08004D04:  D168         BNE        .L8                      ; 0x08004DD8
+  0x08004D06:  2800         CMP        R0, #0
+  0x08004D08:  D13C         BNE        .L7                      ; 0x08004D84
+  0x08004D0A:  2020         MOVS       R0, #32
+  0x08004D0C:  6028         STR        R0, [R5]
+  0x08004D0E:  2000         MOVS       R0, #0
+  0x08004D10:  7020         STRB       R0, [R4]
+  0x08004D12:  207D         MOVS       R0, #125
+  0x08004D14:  0080         LSLS       R0, R0, #2
+  0x08004D16:  49CC         LDR        R1, =onTimeCounter       ; [PC, #0x0330] [0x08005048] =0x200006A8 
+  0x08004D18:  6008         STR        R0, [R1]
+  0x08004D1A:  E05D         B          .L8                      ; 0x08004DD8
+
.L2:
+  0x08004D1C:  49D6         LDR        R1, =0x50000010          ; [PC, #0x0358] [0x08005078] 
+  0x08004D1E:  680A         LDR        R2, [R1]
+  0x08004D20:  07D2         LSLS       R2, R2, #31
+  0x08004D22:  D000         BEQ        .L3                      ; 0x08004D26
+  0x08004D24:  6809         LDR        R1, [R1]
+
.L3:
+  0x08004D26:  4AC3         LDR        R2, =buttonState         ; [PC, #0x030C] [0x08005034] =0x2000073A 
+  0x08004D28:  7811         LDRB       R1, [R2]
+  0x08004D2A:  2901         CMP        R1, #1
+  0x08004D2C:  D000         BEQ        .L4                      ; 0x08004D30
+  0x08004D2E:  E178         B          .L24                     ; 0x08005022
+
.L4:
+  0x08004D30:  2800         CMP        R0, #0
+  0x08004D32:  D16E         BNE        .L13                     ; 0x08004E12
+  0x08004D34:  2020         MOVS       R0, #32
+  0x08004D36:  6028         STR        R0, [R5]
+  0x08004D38:  2000         MOVS       R0, #0
+  0x08004D3A:  7010         STRB       R0, [R2]
+  0x08004D3C:  207D         MOVS       R0, #125
+  0x08004D3E:  0080         LSLS       R0, R0, #2
+  0x08004D40:  4AC1         LDR        R2, =onTimeCounter       ; [PC, #0x0304] [0x08005048] =0x200006A8 
+  0x08004D42:  6010         STR        R0, [R2]
+  0x08004D44:  48D4         LDR        R0, =onTimeRT            ; [PC, #0x0350] [0x08005098] =0x2000073C 
+  0x08004D46:  7001         STRB       R1, [R0]
+  0x08004D48:  48D4         LDR        R0, =offTimeRT           ; [PC, #0x0350] [0x0800509C] =0x20000748 
+  0x08004D4A:  7001         STRB       R1, [R0]
+  0x08004D4C:  48C4         LDR        R0, =blinkModeRT         ; [PC, #0x0310] [0x08005060] =0x20000754 
+  0x08004D4E:  7001         STRB       R1, [R0]
+  0x08004D50:  48D3         LDR        R0, =numberOfBlinks      ; [PC, #0x034C] [0x080050A0] =0x200006BC 
+  0x08004D52:  2203         MOVS       R2, #3
+  0x08004D54:  6002         STR        R2, [R0]
+  0x08004D56:  48D3         LDR        R0, =blinkCounter        ; [PC, #0x034C] [0x080050A4] =0x200006EC 
+  0x08004D58:  6002         STR        R2, [R0]
+  0x08004D5A:  03CA         LSLS       R2, R1, #15
+  0x08004D5C:  2402         MOVS       R4, #2
+  0x08004D5E:  48D4         LDR        R0, =0x08006711          ; [PC, #0x0350] [0x080050B0] 
+  0x08004D60:  4BC0         LDR        R3, =onTimeCounterRT     ; [PC, #0x0300] [0x08005064] =0x2000069C 
+  0x08004D62:  4DD1         LDR        R5, =pauseTime           ; [PC, #0x0344] [0x080050A8] =0x20000734 
+  0x08004D64:  E06C         B          .L14                     ; 0x08004E40
+
.L5:
+  0x08004D66:  9101         STR        R1, [SP, #4]
+  0x08004D68:  48C3         LDR        R0, =0x50000010          ; [PC, #0x030C] [0x08005078] 
+  0x08004D6A:  6801         LDR        R1, [R0]
+  0x08004D6C:  07C9         LSLS       R1, R1, #31
+  0x08004D6E:  9303         STR        R3, [SP, #12]
+  0x08004D70:  9404         STR        R4, [SP, #16]
+  0x08004D72:  9202         STR        R2, [SP, #8]
+  0x08004D74:  D002         BEQ        .L6                      ; 0x08004D7C
+  0x08004D76:  6800         LDR        R0, [R0]
+  0x08004D78:  0780         LSLS       R0, R0, #30
+  0x08004D7A:  D46B         BMI        .L15                     ; 0x08004E54
+
.L6:
+  0x08004D7C:  48C0         LDR        R0, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 ; [PC, #0x0300] [0x08005080] =0x20000700 
+  0x08004D7E:  2400         MOVS       R4, #0
+  0x08004D80:  6004         STR        R4, [R0]
+  0x08004D82:  E07E         B          .L19                     ; 0x08004E82
+
.L7:
+  0x08004D84:  49AC         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x02B0] [0x08005038] =0x20000708 
+  0x08004D86:  2000         MOVS       R0, #0
+  0x08004D88:  6008         STR        R0, [R1]
+  0x08004D8A:  2110         MOVS       R1, #16
+  0x08004D8C:  6129         STR        R1, [R5, #16]
+  0x08004D8E:  2108         MOVS       R1, #8
+  0x08004D90:  6029         STR        R1, [R5]
+  0x08004D92:  49AA         LDR        R1, =relaisState         ; [PC, #0x02A8] [0x0800503C] =0x20000730 
+  0x08004D94:  2701         MOVS       R7, #1
+  0x08004D96:  700F         STRB       R7, [R1]
+  0x08004D98:  49A9         LDR        R1, =onTimeCounterSET    ; [PC, #0x02A4] [0x08005040] =0x20000698 
+  0x08004D9A:  2232         MOVS       R2, #50
+  0x08004D9C:  600A         STR        R2, [R1]
+  0x08004D9E:  2120         MOVS       R1, #32
+  0x08004DA0:  6029         STR        R1, [R5]
+  0x08004DA2:  49A8         LDR        R1, =onTimeGN            ; [PC, #0x02A0] [0x08005044] =0x20000740 
+  0x08004DA4:  700F         STRB       R7, [R1]
+  0x08004DA6:  49A8         LDR        R1, =onTimeCounter       ; [PC, #0x02A0] [0x08005048] =0x200006A8 
+  0x08004DA8:  22C8         MOVS       R2, #200
+  0x08004DAA:  600A         STR        R2, [R1]
+  0x08004DAC:  49A7         LDR        R1, =offTimeGN           ; [PC, #0x029C] [0x0800504C] =0x2000074C 
+  0x08004DAE:  700F         STRB       R7, [R1]
+  0x08004DB0:  49A7         LDR        R1, =blinkModeGN         ; [PC, #0x029C] [0x08005050] =0x20000758 
+  0x08004DB2:  700F         STRB       R7, [R1]
+  0x08004DB4:  03B9         LSLS       R1, R7, #14
+  0x08004DB6:  461D         MOV        R5, R3
+  0x08004DB8:  4BA6         LDR        R3, =0x50000818          ; [PC, #0x0298] [0x08005054] 
+  0x08004DBA:  6019         STR        R1, [R3]
+  0x08004DBC:  49A6         LDR        R1, =onTimeCounterGN     ; [PC, #0x0298] [0x08005058] =0x200006A4 
+  0x08004DBE:  600A         STR        R2, [R1]
+  0x08004DC0:  03F9         LSLS       R1, R7, #15
+  0x08004DC2:  6119         STR        R1, [R3, #16]
+  0x08004DC4:  49A5         LDR        R1, =offTimeCounterRT    ; [PC, #0x0294] [0x0800505C] =0x200006B0 
+  0x08004DC6:  6008         STR        R0, [R1]
+  0x08004DC8:  49A5         LDR        R1, =blinkModeRT         ; [PC, #0x0294] [0x08005060] =0x20000754 
+  0x08004DCA:  7008         STRB       R0, [R1]
+  0x08004DCC:  49A5         LDR        R1, =onTimeCounterRT     ; [PC, #0x0294] [0x08005064] =0x2000069C 
+  0x08004DCE:  6008         STR        R0, [R1]
+  0x08004DD0:  48A5         LDR        R0, =0x080064B1          ; [PC, #0x0294] [0x08005068] 
+  0x08004DD2:  F000 F9C1    BL         puts                     ; 0x08005158
+  0x08004DD6:  702F         STRB       R7, [R5]
+
.L8:
+  0x08004DD8:  6830         LDR        R0, [R6]
+  0x08004DDA:  2801         CMP        R0, #1
+  0x08004DDC:  D000         BEQ        .L9                      ; 0x08004DE0
+  0x08004DDE:  E120         B          .L24                     ; 0x08005022
+
.L9:
+  0x08004DE0:  48A2         LDR        R0, =uwTick              ; [PC, #0x0288] [0x0800506C] =0x2000068C 
+  0x08004DE2:  6802         LDR        R2, [R0]
+  0x08004DE4:  49A2         LDR        R1, =SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182 ; [PC, #0x0288] [0x08005070] =0x20000710 
+  0x08004DE6:  680B         LDR        R3, [R1]
+  0x08004DE8:  4293         CMP        R3, R2
+  0x08004DEA:  D102         BNE        .L10                     ; 0x08004DF2
+  0x08004DEC:  4892         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0248] [0x08005038] =0x20000708 
+  0x08004DEE:  6800         LDR        R0, [R0]
+  0x08004DF0:  E005         B          .L11                     ; 0x08004DFE
+
.L10:
+  0x08004DF2:  6800         LDR        R0, [R0]
+  0x08004DF4:  6008         STR        R0, [R1]
+  0x08004DF6:  4990         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0240] [0x08005038] =0x20000708 
+  0x08004DF8:  6808         LDR        R0, [R1]
+  0x08004DFA:  1C40         ADDS       R0, R0, #1
+  0x08004DFC:  6008         STR        R0, [R1]
+
.L11:
+  0x08004DFE:  499D         LDR        R1, =0x0036EE81          ; [PC, #0x0274] [0x08005074] 
+  0x08004E00:  4288         CMP        R0, R1
+  0x08004E02:  D200         BCS        .L12                     ; 0x08004E06
+  0x08004E04:  E10D         B          .L24                     ; 0x08005022
+
.L12:
+  0x08004E06:  488C         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0230] [0x08005038] =0x20000708 
+  0x08004E08:  2100         MOVS       R1, #0
+  0x08004E0A:  6001         STR        R1, [R0]
+  0x08004E0C:  2001         MOVS       R0, #1
+  0x08004E0E:  7020         STRB       R0, [R4]
+  0x08004E10:  E107         B          .L24                     ; 0x08005022
+
.L13:
+  0x08004E12:  2010         MOVS       R0, #16
+  0x08004E14:  6128         STR        R0, [R5, #16]
+  0x08004E16:  2008         MOVS       R0, #8
+  0x08004E18:  6028         STR        R0, [R5]
+  0x08004E1A:  4888         LDR        R0, =relaisState         ; [PC, #0x0220] [0x0800503C] =0x20000730 
+  0x08004E1C:  7001         STRB       R1, [R0]
+  0x08004E1E:  4888         LDR        R0, =onTimeCounterSET    ; [PC, #0x0220] [0x08005040] =0x20000698 
+  0x08004E20:  2232         MOVS       R2, #50
+  0x08004E22:  6002         STR        R2, [R0]
+  0x08004E24:  2020         MOVS       R0, #32
+  0x08004E26:  6028         STR        R0, [R5]
+  0x08004E28:  4886         LDR        R0, =onTimeGN            ; [PC, #0x0218] [0x08005044] =0x20000740 
+  0x08004E2A:  7001         STRB       R1, [R0]
+  0x08004E2C:  4886         LDR        R0, =onTimeCounter       ; [PC, #0x0218] [0x08005048] =0x200006A8 
+  0x08004E2E:  22C8         MOVS       R2, #200
+  0x08004E30:  6002         STR        R2, [R0]
+  0x08004E32:  4886         LDR        R0, =offTimeGN           ; [PC, #0x0218] [0x0800504C] =0x2000074C 
+  0x08004E34:  7001         STRB       R1, [R0]
+  0x08004E36:  038A         LSLS       R2, R1, #14
+  0x08004E38:  488B         LDR        R0, =0x080064B1          ; [PC, #0x022C] [0x08005068] 
+  0x08004E3A:  4B87         LDR        R3, =onTimeCounterGN     ; [PC, #0x021C] [0x08005058] =0x200006A4 
+  0x08004E3C:  4D84         LDR        R5, =blinkModeGN         ; [PC, #0x0210] [0x08005050] =0x20000758 
+  0x08004E3E:  460C         MOV        R4, R1
+
.L14:
+  0x08004E40:  7029         STRB       R1, [R5]
+  0x08004E42:  4984         LDR        R1, =0x50000818          ; [PC, #0x0210] [0x08005054] 
+  0x08004E44:  600A         STR        R2, [R1]
+  0x08004E46:  21C8         MOVS       R1, #200
+  0x08004E48:  6019         STR        R1, [R3]
+  0x08004E4A:  F000 F985    BL         puts                     ; 0x08005158
+  0x08004E4E:  4878         LDR        R0, =smState.171         ; [PC, #0x01E0] [0x08005030] =0x20000731 
+  0x08004E50:  7004         STRB       R4, [R0]
+  0x08004E52:  E0E6         B          .L24                     ; 0x08005022
+
.L15:
+  0x08004E54:  4889         LDR        R0, =SECONDARYPROTECTION_SM_On.oldtime.175 ; [PC, #0x0224] [0x0800507C] =0x200006F8 
+  0x08004E56:  6802         LDR        R2, [R0]
+  0x08004E58:  4984         LDR        R1, =uwTick              ; [PC, #0x0210] [0x0800506C] =0x2000068C 
+  0x08004E5A:  680B         LDR        R3, [R1]
+  0x08004E5C:  4293         CMP        R3, R2
+  0x08004E5E:  D00D         BEQ        .L17                     ; 0x08004E7C
+  0x08004E60:  6809         LDR        R1, [R1]
+  0x08004E62:  6001         STR        R1, [R0]
+  0x08004E64:  4986         LDR        R1, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 ; [PC, #0x0218] [0x08005080] =0x20000700 
+  0x08004E66:  680B         LDR        R3, [R1]
+  0x08004E68:  1C5A         ADDS       R2, R3, #1
+  0x08004E6A:  2000         MOVS       R0, #0
+  0x08004E6C:  4C85         LDR        R4, =0x0000752F          ; [PC, #0x0214] [0x08005084] 
+  0x08004E6E:  42A3         CMP        R3, R4
+  0x08004E70:  4603         MOV        R3, R0
+  0x08004E72:  DC00         BGT        .L16                     ; 0x08004E76
+  0x08004E74:  4613         MOV        R3, R2
+
.L16:
+  0x08004E76:  600B         STR        R3, [R1]
+  0x08004E78:  463C         MOV        R4, R7
+  0x08004E7A:  DC00         BGT        .L18                     ; 0x08004E7E
+
.L17:
+  0x08004E7C:  2400         MOVS       R4, #0
+
.L18:
+  0x08004E7E:  9B03         LDR        R3, [SP, #12]
+  0x08004E80:  9A02         LDR        R2, [SP, #8]
+
.L19:
+  0x08004E82:  9901         LDR        R1, [SP, #4]
+  0x08004E84:  486B         LDR        R0, =buttonState         ; [PC, #0x01AC] [0x08005034] =0x2000073A 
+  0x08004E86:  7800         LDRB       R0, [R0]
+  0x08004E88:  2800         CMP        R0, #0
+  0x08004E8A:  9400         STR        R4, [SP, #0]
+  0x08004E8C:  D125         BNE        .L20                     ; 0x08004EDA
+  0x08004E8E:  2008         MOVS       R0, #8
+  0x08004E90:  6128         STR        R0, [R5, #16]
+  0x08004E92:  2010         MOVS       R0, #16
+  0x08004E94:  6028         STR        R0, [R5]
+  0x08004E96:  4869         LDR        R0, =relaisState         ; [PC, #0x01A4] [0x0800503C] =0x20000730 
+  0x08004E98:  2400         MOVS       R4, #0
+  0x08004E9A:  7004         STRB       R4, [R0]
+  0x08004E9C:  487A         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01E8] [0x08005088] =0x200006A0 
+  0x08004E9E:  2132         MOVS       R1, #50
+  0x08004EA0:  6001         STR        R1, [R0]
+  0x08004EA2:  2020         MOVS       R0, #32
+  0x08004EA4:  6028         STR        R0, [R5]
+  0x08004EA6:  4868         LDR        R0, =onTimeCounter       ; [PC, #0x01A0] [0x08005048] =0x200006A8 
+  0x08004EA8:  21C8         MOVS       R1, #200
+  0x08004EAA:  6001         STR        R1, [R0]
+  0x08004EAC:  9804         LDR        R0, [SP, #16]
+  0x08004EAE:  6130         STR        R0, [R6, #16]
+  0x08004EB0:  4876         LDR        R0, =offTimeCounterGN    ; [PC, #0x01D8] [0x0800508C] =0x200006B4 
+  0x08004EB2:  6004         STR        R4, [R0]
+  0x08004EB4:  4866         LDR        R0, =blinkModeGN         ; [PC, #0x0198] [0x08005050] =0x20000758 
+  0x08004EB6:  7004         STRB       R4, [R0]
+  0x08004EB8:  4867         LDR        R0, =onTimeCounterGN     ; [PC, #0x019C] [0x08005058] =0x200006A4 
+  0x08004EBA:  6004         STR        R4, [R0]
+  0x08004EBC:  6133         STR        R3, [R6, #16]
+  0x08004EBE:  4867         LDR        R0, =offTimeCounterRT    ; [PC, #0x019C] [0x0800505C] =0x200006B0 
+  0x08004EC0:  6004         STR        R4, [R0]
+  0x08004EC2:  4867         LDR        R0, =blinkModeRT         ; [PC, #0x019C] [0x08005060] =0x20000754 
+  0x08004EC4:  7004         STRB       R4, [R0]
+  0x08004EC6:  4867         LDR        R0, =onTimeCounterRT     ; [PC, #0x019C] [0x08005064] =0x2000069C 
+  0x08004EC8:  6004         STR        R4, [R0]
+  0x08004ECA:  4871         LDR        R0, =0x08006271          ; [PC, #0x01C4] [0x08005090] 
+  0x08004ECC:  F000 F944    BL         puts                     ; 0x08005158
+  0x08004ED0:  A901         ADD        R1, SP, #4
+  0x08004ED2:  C90E         LDM        R1, {R1-R3}
+  0x08004ED4:  4856         LDR        R0, =smState.171         ; [PC, #0x0158] [0x08005030] =0x20000731 
+  0x08004ED6:  7004         STRB       R4, [R0]
+  0x08004ED8:  9C00         LDR        R4, [SP, #0]
+
.L20:
+  0x08004EDA:  00C8         LSLS       R0, R1, #3
+  0x08004EDC:  496D         LDR        R1, =dropLimitCounter    ; [PC, #0x01B4] [0x08005094] =0x200006E4 
+  0x08004EDE:  6809         LDR        R1, [R1]
+  0x08004EE0:  4281         CMP        R1, R0
+  0x08004EE2:  D135         BNE        .L21                     ; 0x08004F50
+  0x08004EE4:  2008         MOVS       R0, #8
+  0x08004EE6:  6128         STR        R0, [R5, #16]
+  0x08004EE8:  2010         MOVS       R0, #16
+  0x08004EEA:  6028         STR        R0, [R5]
+  0x08004EEC:  4853         LDR        R0, =relaisState         ; [PC, #0x014C] [0x0800503C] =0x20000730 
+  0x08004EEE:  2400         MOVS       R4, #0
+  0x08004EF0:  7004         STRB       R4, [R0]
+  0x08004EF2:  4865         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0194] [0x08005088] =0x200006A0 
+  0x08004EF4:  2132         MOVS       R1, #50
+  0x08004EF6:  6001         STR        R1, [R0]
+  0x08004EF8:  2020         MOVS       R0, #32
+  0x08004EFA:  6028         STR        R0, [R5]
+  0x08004EFC:  4852         LDR        R0, =onTimeCounter       ; [PC, #0x0148] [0x08005048] =0x200006A8 
+  0x08004EFE:  6002         STR        R2, [R0]
+  0x08004F00:  9804         LDR        R0, [SP, #16]
+  0x08004F02:  6130         STR        R0, [R6, #16]
+  0x08004F04:  4861         LDR        R0, =offTimeCounterGN    ; [PC, #0x0184] [0x0800508C] =0x200006B4 
+  0x08004F06:  6004         STR        R4, [R0]
+  0x08004F08:  4851         LDR        R0, =blinkModeGN         ; [PC, #0x0144] [0x08005050] =0x20000758 
+  0x08004F0A:  7004         STRB       R4, [R0]
+  0x08004F0C:  4852         LDR        R0, =onTimeCounterGN     ; [PC, #0x0148] [0x08005058] =0x200006A4 
+  0x08004F0E:  6004         STR        R4, [R0]
+  0x08004F10:  4861         LDR        R0, =onTimeRT            ; [PC, #0x0184] [0x08005098] =0x2000073C 
+  0x08004F12:  7007         STRB       R7, [R0]
+  0x08004F14:  4861         LDR        R0, =offTimeRT           ; [PC, #0x0184] [0x0800509C] =0x20000748 
+  0x08004F16:  7007         STRB       R7, [R0]
+  0x08004F18:  4851         LDR        R0, =blinkModeRT         ; [PC, #0x0144] [0x08005060] =0x20000754 
+  0x08004F1A:  7007         STRB       R7, [R0]
+  0x08004F1C:  4860         LDR        R0, =numberOfBlinks      ; [PC, #0x0180] [0x080050A0] =0x200006BC 
+  0x08004F1E:  2104         MOVS       R1, #4
+  0x08004F20:  6001         STR        R1, [R0]
+  0x08004F22:  4860         LDR        R0, =blinkCounter        ; [PC, #0x0180] [0x080050A4] =0x200006EC 
+  0x08004F24:  6001         STR        R1, [R0]
+  0x08004F26:  4860         LDR        R0, =pauseTime           ; [PC, #0x0180] [0x080050A8] =0x20000734 
+  0x08004F28:  7007         STRB       R7, [R0]
+  0x08004F2A:  6033         STR        R3, [R6]
+  0x08004F2C:  4841         LDR        R0, =buttonState         ; [PC, #0x0104] [0x08005034] =0x2000073A 
+  0x08004F2E:  7004         STRB       R4, [R0]
+  0x08004F30:  484C         LDR        R0, =onTimeCounterRT     ; [PC, #0x0130] [0x08005064] =0x2000069C 
+  0x08004F32:  21C8         MOVS       R1, #200
+  0x08004F34:  6001         STR        R1, [R0]
+  0x08004F36:  485D         LDR        R0, =0x080066F4          ; [PC, #0x0174] [0x080050AC] 
+  0x08004F38:  F000 F90E    BL         puts                     ; 0x08005158
+  0x08004F3C:  485C         LDR        R0, =0x08006711          ; [PC, #0x0170] [0x080050B0] 
+  0x08004F3E:  F000 F90B    BL         puts                     ; 0x08005158
+  0x08004F42:  9B03         LDR        R3, [SP, #12]
+  0x08004F44:  2002         MOVS       R0, #2
+  0x08004F46:  493A         LDR        R1, =smState.171         ; [PC, #232] [0x08005030] =0x20000731 
+  0x08004F48:  7008         STRB       R0, [R1]
+  0x08004F4A:  4852         LDR        R0, =dropLimitCounter    ; [PC, #0x0148] [0x08005094] =0x200006E4 
+  0x08004F4C:  6004         STR        R4, [R0]
+  0x08004F4E:  9C00         LDR        R4, [SP, #0]
+
.L21:
+  0x08004F50:  2C00         CMP        R4, #0
+  0x08004F52:  D032         BEQ        .L22                     ; 0x08004FBA
+  0x08004F54:  2008         MOVS       R0, #8
+  0x08004F56:  6128         STR        R0, [R5, #16]
+  0x08004F58:  2010         MOVS       R0, #16
+  0x08004F5A:  6028         STR        R0, [R5]
+  0x08004F5C:  4937         LDR        R1, =relaisState         ; [PC, #220] [0x0800503C] =0x20000730 
+  0x08004F5E:  2000         MOVS       R0, #0
+  0x08004F60:  7008         STRB       R0, [R1]
+  0x08004F62:  4949         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0124] [0x08005088] =0x200006A0 
+  0x08004F64:  2232         MOVS       R2, #50
+  0x08004F66:  600A         STR        R2, [R1]
+  0x08004F68:  2120         MOVS       R1, #32
+  0x08004F6A:  6029         STR        R1, [R5]
+  0x08004F6C:  4936         LDR        R1, =onTimeCounter       ; [PC, #216] [0x08005048] =0x200006A8 
+  0x08004F6E:  9A02         LDR        R2, [SP, #8]
+  0x08004F70:  600A         STR        R2, [R1]
+  0x08004F72:  9904         LDR        R1, [SP, #16]
+  0x08004F74:  6131         STR        R1, [R6, #16]
+  0x08004F76:  4945         LDR        R1, =offTimeCounterGN    ; [PC, #0x0114] [0x0800508C] =0x200006B4 
+  0x08004F78:  6008         STR        R0, [R1]
+  0x08004F7A:  4935         LDR        R1, =blinkModeGN         ; [PC, #212] [0x08005050] =0x20000758 
+  0x08004F7C:  7008         STRB       R0, [R1]
+  0x08004F7E:  4936         LDR        R1, =onTimeCounterGN     ; [PC, #216] [0x08005058] =0x200006A4 
+  0x08004F80:  6008         STR        R0, [R1]
+  0x08004F82:  4945         LDR        R1, =onTimeRT            ; [PC, #0x0114] [0x08005098] =0x2000073C 
+  0x08004F84:  700F         STRB       R7, [R1]
+  0x08004F86:  4945         LDR        R1, =offTimeRT           ; [PC, #0x0114] [0x0800509C] =0x20000748 
+  0x08004F88:  700F         STRB       R7, [R1]
+  0x08004F8A:  4935         LDR        R1, =blinkModeRT         ; [PC, #212] [0x08005060] =0x20000754 
+  0x08004F8C:  700F         STRB       R7, [R1]
+  0x08004F8E:  4944         LDR        R1, =numberOfBlinks      ; [PC, #0x0110] [0x080050A0] =0x200006BC 
+  0x08004F90:  2402         MOVS       R4, #2
+  0x08004F92:  600C         STR        R4, [R1]
+  0x08004F94:  4943         LDR        R1, =blinkCounter        ; [PC, #0x010C] [0x080050A4] =0x200006EC 
+  0x08004F96:  600C         STR        R4, [R1]
+  0x08004F98:  4943         LDR        R1, =pauseTime           ; [PC, #0x010C] [0x080050A8] =0x20000734 
+  0x08004F9A:  700F         STRB       R7, [R1]
+  0x08004F9C:  6033         STR        R3, [R6]
+  0x08004F9E:  4925         LDR        R1, =buttonState         ; [PC, #148] [0x08005034] =0x2000073A 
+  0x08004FA0:  7008         STRB       R0, [R1]
+  0x08004FA2:  4830         LDR        R0, =onTimeCounterRT     ; [PC, #192] [0x08005064] =0x2000069C 
+  0x08004FA4:  21C8         MOVS       R1, #200
+  0x08004FA6:  6001         STR        R1, [R0]
+  0x08004FA8:  4842         LDR        R0, =0x080068B8          ; [PC, #0x0108] [0x080050B4] 
+  0x08004FAA:  F000 F8D5    BL         puts                     ; 0x08005158
+  0x08004FAE:  4840         LDR        R0, =0x08006711          ; [PC, #0x0100] [0x080050B0] 
+  0x08004FB0:  F000 F8D2    BL         puts                     ; 0x08005158
+  0x08004FB4:  9B03         LDR        R3, [SP, #12]
+  0x08004FB6:  481E         LDR        R0, =smState.171         ; [PC, #120] [0x08005030] =0x20000731 
+  0x08004FB8:  7004         STRB       R4, [R0]
+
.L22:
+  0x08004FBA:  483F         LDR        R0, =temp                ; [PC, #252] [0x080050B8] =0x20000690 
+  0x08004FBC:  6800         LDR        R0, [R0]
+  0x08004FBE:  2851         CMP        R0, #81
+  0x08004FC0:  9C04         LDR        R4, [SP, #16]
+  0x08004FC2:  DB2E         BLT        .L24                     ; 0x08005022
+  0x08004FC4:  2008         MOVS       R0, #8
+  0x08004FC6:  6128         STR        R0, [R5, #16]
+  0x08004FC8:  2010         MOVS       R0, #16
+  0x08004FCA:  6028         STR        R0, [R5]
+  0x08004FCC:  491B         LDR        R1, =relaisState         ; [PC, #108] [0x0800503C] =0x20000730 
+  0x08004FCE:  2000         MOVS       R0, #0
+  0x08004FD0:  7008         STRB       R0, [R1]
+  0x08004FD2:  492D         LDR        R1, =onTimeCounterRESET  ; [PC, #180] [0x08005088] =0x200006A0 
+  0x08004FD4:  2232         MOVS       R2, #50
+  0x08004FD6:  600A         STR        R2, [R1]
+  0x08004FD8:  2120         MOVS       R1, #32
+  0x08004FDA:  6029         STR        R1, [R5]
+  0x08004FDC:  491A         LDR        R1, =onTimeCounter       ; [PC, #104] [0x08005048] =0x200006A8 
+  0x08004FDE:  9A02         LDR        R2, [SP, #8]
+  0x08004FE0:  600A         STR        R2, [R1]
+  0x08004FE2:  6134         STR        R4, [R6, #16]
+  0x08004FE4:  4929         LDR        R1, =offTimeCounterGN    ; [PC, #164] [0x0800508C] =0x200006B4 
+  0x08004FE6:  6008         STR        R0, [R1]
+  0x08004FE8:  4919         LDR        R1, =blinkModeGN         ; [PC, #100] [0x08005050] =0x20000758 
+  0x08004FEA:  7008         STRB       R0, [R1]
+  0x08004FEC:  491A         LDR        R1, =onTimeCounterGN     ; [PC, #104] [0x08005058] =0x200006A4 
+  0x08004FEE:  6008         STR        R0, [R1]
+  0x08004FF0:  4929         LDR        R1, =onTimeRT            ; [PC, #164] [0x08005098] =0x2000073C 
+  0x08004FF2:  700F         STRB       R7, [R1]
+  0x08004FF4:  4929         LDR        R1, =offTimeRT           ; [PC, #164] [0x0800509C] =0x20000748 
+  0x08004FF6:  700F         STRB       R7, [R1]
+  0x08004FF8:  4919         LDR        R1, =blinkModeRT         ; [PC, #100] [0x08005060] =0x20000754 
+  0x08004FFA:  700F         STRB       R7, [R1]
+  0x08004FFC:  4928         LDR        R1, =numberOfBlinks      ; [PC, #160] [0x080050A0] =0x200006BC 
+  0x08004FFE:  2205         MOVS       R2, #5
+  0x08005000:  600A         STR        R2, [R1]
+  0x08005002:  4928         LDR        R1, =blinkCounter        ; [PC, #160] [0x080050A4] =0x200006EC 
+  0x08005004:  600A         STR        R2, [R1]
+  0x08005006:  4928         LDR        R1, =pauseTime           ; [PC, #160] [0x080050A8] =0x20000734 
+  0x08005008:  700F         STRB       R7, [R1]
+  0x0800500A:  6033         STR        R3, [R6]
+  0x0800500C:  4909         LDR        R1, =buttonState         ; [PC, #36] [0x08005034] =0x2000073A 
+  0x0800500E:  7008         STRB       R0, [R1]
+  0x08005010:  4814         LDR        R0, =onTimeCounterRT     ; [PC, #80] [0x08005064] =0x2000069C 
+  0x08005012:  21C8         MOVS       R1, #200
+  0x08005014:  6001         STR        R1, [R0]
+  0x08005016:  4829         LDR        R0, =0x08006294          ; [PC, #164] [0x080050BC] 
+
.L23:
+  0x08005018:  F000 F89E    BL         puts                     ; 0x08005158
+  0x0800501C:  2002         MOVS       R0, #2
+  0x0800501E:  4904         LDR        R1, =smState.171         ; [PC, #16] [0x08005030] =0x20000731 
+  0x08005020:  7008         STRB       R0, [R1]
+
.L24:
+  0x08005022:  B005         ADD        SP, SP, #20
+  0x08005024:  BDF0         POP        {R4-R7, PC}
+  0x08005026:  46C0         NOP
+  0x08005028:  200006F0     DC.W       autoRetryMode.170
+  0x0800502C:  50000418     DC.W       0x50000418
+  0x08005030:  20000731     DC.W       smState.171
+  0x08005034:  2000073A     DC.W       buttonState
+  0x08005038:  20000708     DC.W       SECONDARYPROTECTION_SM_Error.retry_counter.181
+  0x0800503C:  20000730     DC.W       relaisState
+  0x08005040:  20000698     DC.W       onTimeCounterSET
+  0x08005044:  20000740     DC.W       onTimeGN
+  0x08005048:  200006A8     DC.W       onTimeCounter
+  0x0800504C:  2000074C     DC.W       offTimeGN
+  0x08005050:  20000758     DC.W       blinkModeGN
+  0x08005054:  50000818     DC.W       0x50000818
+  0x08005058:  200006A4     DC.W       onTimeCounterGN
+  0x0800505C:  200006B0     DC.W       offTimeCounterRT
+  0x08005060:  20000754     DC.W       blinkModeRT
+  0x08005064:  2000069C     DC.W       onTimeCounterRT
+  0x08005068:  080064B1     DC.W       080064B1               ; R_ARM_ABS32
+  0x0800506C:  2000068C     DC.W       uwTick
+  0x08005070:  20000710     DC.W       SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182
+  0x08005074:  0036EE81     DC.W       0x0036EE81
+  0x08005078:  50000010     DC.W       0x50000010
+  0x0800507C:  200006F8     DC.W       SECONDARYPROTECTION_SM_On.oldtime.175
+  0x08005080:  20000700     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176
+  0x08005084:  0000752F     DC.W       0x0000752F
+  0x08005088:  200006A0     DC.W       onTimeCounterRESET
+  0x0800508C:  200006B4     DC.W       offTimeCounterGN
+  0x08005090:  08006271     DC.W       08006271               ; R_ARM_ABS32
+  0x08005094:  200006E4     DC.W       dropLimitCounter
+  0x08005098:  2000073C     DC.W       onTimeRT
+  0x0800509C:  20000748     DC.W       offTimeRT
+  0x080050A0:  200006BC     DC.W       numberOfBlinks
+  0x080050A4:  200006EC     DC.W       blinkCounter
+  0x080050A8:  20000734     DC.W       pauseTime
+  0x080050AC:  080066F4     DC.W       080066F4               ; R_ARM_ABS32
+  0x080050B0:  08006711     DC.W       08006711               ; R_ARM_ABS32
+  0x080050B4:  080068B8     DC.W       080068B8               ; R_ARM_ABS32
+  0x080050B8:  20000690     DC.W       temp
+  0x080050BC:  08006294     DC.W       08006294               ; R_ARM_ABS32
+  0x080050C0:  080068F4     DC.W       080068F4               ; R_ARM_ABS32
+
+

Section .rodata.AHBPrescTable from PowerPro_lto.o, size=64, align=4

+
+
AHBPrescTable:
+  0x080050C4:  00           DC.B       0x00                     ; '\0'
+  0x080050C5:  00           DC.B       0x00                     ; '\0'
+  0x080050C6:  00           DC.B       0x00                     ; '\0'
+  0x080050C7:  00           DC.B       0x00                     ; '\0'
+  0x080050C8:  00           DC.B       0x00                     ; '\0'
+  0x080050C9:  00           DC.B       0x00                     ; '\0'
+  0x080050CA:  00           DC.B       0x00                     ; '\0'
+  0x080050CB:  00           DC.B       0x00                     ; '\0'
+  0x080050CC:  00           DC.B       0x00                     ; '\0'
+  0x080050CD:  00           DC.B       0x00                     ; '\0'
+  0x080050CE:  00           DC.B       0x00                     ; '\0'
+  0x080050CF:  00           DC.B       0x00                     ; '\0'
+  0x080050D0:  00           DC.B       0x00                     ; '\0'
+  0x080050D1:  00           DC.B       0x00                     ; '\0'
+  0x080050D2:  00           DC.B       0x00                     ; '\0'
+  0x080050D3:  00           DC.B       0x00                     ; '\0'
+  0x080050D4:  00           DC.B       0x00                     ; '\0'
+  0x080050D5:  00           DC.B       0x00                     ; '\0'
+  0x080050D6:  00           DC.B       0x00                     ; '\0'
+  0x080050D7:  00           DC.B       0x00                     ; '\0'
+  0x080050D8:  00           DC.B       0x00                     ; '\0'
+  0x080050D9:  00           DC.B       0x00                     ; '\0'
+  0x080050DA:  00           DC.B       0x00                     ; '\0'
+  0x080050DB:  00           DC.B       0x00                     ; '\0'
+  0x080050DC:  00           DC.B       0x00                     ; '\0'
+  0x080050DD:  00           DC.B       0x00                     ; '\0'
+  0x080050DE:  00           DC.B       0x00                     ; '\0'
+  0x080050DF:  00           DC.B       0x00                     ; '\0'
+  0x080050E0:  00           DC.B       0x00                     ; '\0'
+  0x080050E1:  00           DC.B       0x00                     ; '\0'
+  0x080050E2:  00           DC.B       0x00                     ; '\0'
+  0x080050E3:  00           DC.B       0x00                     ; '\0'
+  0x080050E4:  01           DC.B       0x01                     ; '\x01'
+  0x080050E5:  00           DC.B       0x00                     ; '\0'
+  0x080050E6:  00           DC.B       0x00                     ; '\0'
+  0x080050E7:  00           DC.B       0x00                     ; '\0'
+  0x080050E8:  02           DC.B       0x02                     ; '\x02'
+  0x080050E9:  00           DC.B       0x00                     ; '\0'
+  0x080050EA:  00           DC.B       0x00                     ; '\0'
+  0x080050EB:  00           DC.B       0x00                     ; '\0'
+  0x080050EC:  03           DC.B       0x03                     ; '\x03'
+  0x080050ED:  00           DC.B       0x00                     ; '\0'
+  0x080050EE:  00           DC.B       0x00                     ; '\0'
+  0x080050EF:  00           DC.B       0x00                     ; '\0'
+  0x080050F0:  04           DC.B       0x04                     ; '\x04'
+  0x080050F1:  00           DC.B       0x00                     ; '\0'
+  0x080050F2:  00           DC.B       0x00                     ; '\0'
+  0x080050F3:  00           DC.B       0x00                     ; '\0'
+  0x080050F4:  06           DC.B       0x06                     ; '\x06'
+  0x080050F5:  00           DC.B       0x00                     ; '\0'
+  0x080050F6:  00           DC.B       0x00                     ; '\0'
+  0x080050F7:  00           DC.B       0x00                     ; '\0'
+  0x080050F8:  07           DC.B       0x07                     ; '\x07'
+  0x080050F9:  00           DC.B       0x00                     ; '\0'
+  0x080050FA:  00           DC.B       0x00                     ; '\0'
+  0x080050FB:  00           DC.B       0x00                     ; '\0'
+  0x080050FC:  08           DC.B       0x08                     ; '\b'
+  0x080050FD:  00           DC.B       0x00                     ; '\0'
+  0x080050FE:  00           DC.B       0x00                     ; '\0'
+  0x080050FF:  00           DC.B       0x00                     ; '\0'
+  0x08005100:  09           DC.B       0x09                     ; '\t'
+  0x08005101:  00           DC.B       0x00                     ; '\0'
+  0x08005102:  00           DC.B       0x00                     ; '\0'
+  0x08005103:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.APBPrescTable from PowerPro_lto.o, size=32, align=4

+
+
APBPrescTable:
+  0x08005104:  00           DC.B       0x00                     ; '\0'
+  0x08005105:  00           DC.B       0x00                     ; '\0'
+  0x08005106:  00           DC.B       0x00                     ; '\0'
+  0x08005107:  00           DC.B       0x00                     ; '\0'
+  0x08005108:  00           DC.B       0x00                     ; '\0'
+  0x08005109:  00           DC.B       0x00                     ; '\0'
+  0x0800510A:  00           DC.B       0x00                     ; '\0'
+  0x0800510B:  00           DC.B       0x00                     ; '\0'
+  0x0800510C:  00           DC.B       0x00                     ; '\0'
+  0x0800510D:  00           DC.B       0x00                     ; '\0'
+  0x0800510E:  00           DC.B       0x00                     ; '\0'
+  0x0800510F:  00           DC.B       0x00                     ; '\0'
+  0x08005110:  00           DC.B       0x00                     ; '\0'
+  0x08005111:  00           DC.B       0x00                     ; '\0'
+  0x08005112:  00           DC.B       0x00                     ; '\0'
+  0x08005113:  00           DC.B       0x00                     ; '\0'
+  0x08005114:  01           DC.B       0x01                     ; '\x01'
+  0x08005115:  00           DC.B       0x00                     ; '\0'
+  0x08005116:  00           DC.B       0x00                     ; '\0'
+  0x08005117:  00           DC.B       0x00                     ; '\0'
+  0x08005118:  02           DC.B       0x02                     ; '\x02'
+  0x08005119:  00           DC.B       0x00                     ; '\0'
+  0x0800511A:  00           DC.B       0x00                     ; '\0'
+  0x0800511B:  00           DC.B       0x00                     ; '\0'
+  0x0800511C:  03           DC.B       0x03                     ; '\x03'
+  0x0800511D:  00           DC.B       0x00                     ; '\0'
+  0x0800511E:  00           DC.B       0x00                     ; '\0'
+  0x0800511F:  00           DC.B       0x00                     ; '\0'
+  0x08005120:  04           DC.B       0x04                     ; '\x04'
+  0x08005121:  00           DC.B       0x00                     ; '\0'
+  0x08005122:  00           DC.B       0x00                     ; '\0'
+  0x08005123:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lswitch.table.UART_SetConfig from PowerPro_lto.o, size=16, align=4

+
+  0x08005124:  00           DC.B       0x00                     ; '\0'
+  0x08005125:  00           DC.B       0x00                     ; '\0'
+  0x08005126:  00           DC.B       0x00                     ; '\0'
+  0x08005127:  00           DC.B       0x00                     ; '\0'
+  0x08005128:  04           DC.B       0x04                     ; '\x04'
+  0x08005129:  00           DC.B       0x00                     ; '\0'
+  0x0800512A:  00           DC.B       0x00                     ; '\0'
+  0x0800512B:  00           DC.B       0x00                     ; '\0'
+  0x0800512C:  02           DC.B       0x02                     ; '\x02'
+  0x0800512D:  00           DC.B       0x00                     ; '\0'
+  0x0800512E:  00           DC.B       0x00                     ; '\0'
+  0x0800512F:  00           DC.B       0x00                     ; '\0'
+  0x08005130:  08           DC.B       0x08                     ; '\b'
+  0x08005131:  00           DC.B       0x00                     ; '\0'
+  0x08005132:  00           DC.B       0x00                     ; '\0'
+  0x08005133:  00           DC.B       0x00                     ; '\0'
+
+

Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

+
+
_start:
+  0x08005134:  4C03         LDR        R4, =0x080069D4          ; [PC, #12] [0x08005144] 
+
.L1:
+  0x08005136:  6820         LDR        R0, [R4]
+  0x08005138:  3404         ADDS       R4, #4
+  0x0800513A:  4780         BLX        R0
+  0x0800513C:  E7FB         B          .L1                      ; 0x08005136
+
__SEGGER_init_done:
+__startup_complete:
+  0x0800513E:  F7FC FB81    BL         main                     ; 0x08001844
+
exit:
+  0x08005142:  E7FE         B          exit                     ; 0x08005142
+  0x08005144:  080069D4     DC.W       080069D4               ; R_ARM_ABS32
+
+

Section .text.libc.putchar from fileops.o (libc_v6m_t_le_eabi_small.a), size=16, align=4

+
+
putchar:
+  0x08005148:  B580         PUSH       {R7, LR}
+  0x0800514A:  4902         LDR        R1, =stdout              ; [PC, #8] [0x08005154] =0x20000B98 
+  0x0800514C:  6809         LDR        R1, [R1]
+  0x0800514E:  F000 FB69    BL         fputc                    ; 0x08005824
+  0x08005152:  BD80         POP        {R7, PC}
+  0x08005154:  20000B98     DC.W       stdout
+
+

Section .text.libc.puts from fileops.o (libc_v6m_t_le_eabi_small.a), size=44, align=4

+
+
puts:
+  0x08005158:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x0800515A:  4604         MOV        R4, R0
+  0x0800515C:  4808         LDR        R0, =stdout              ; [PC, #32] [0x08005180] =0x20000B98 
+  0x0800515E:  6805         LDR        R5, [R0]
+  0x08005160:  4620         MOV        R0, R4
+  0x08005162:  F000 FD95    BL         strlen                   ; 0x08005C90
+  0x08005166:  4602         MOV        R2, R0
+  0x08005168:  4628         MOV        R0, R5
+  0x0800516A:  4621         MOV        R1, R4
+  0x0800516C:  F000 FD4C    BL         __SEGGER_RTL_X_file_write ; 0x08005C08
+  0x08005170:  1C40         ADDS       R0, R0, #1
+  0x08005172:  D003         BEQ        .L1                      ; 0x0800517C
+  0x08005174:  200A         MOVS       R0, #10
+  0x08005176:  F7FF FFE7    BL         putchar                  ; 0x08005148
+  0x0800517A:  BDB0         POP        {R4-R5, R7, PC}
+
.L1:
+  0x0800517C:  43C0         MVNS       R0, R0
+  0x0800517E:  BDB0         POP        {R4-R5, R7, PC}
+  0x08005180:  20000B98     DC.W       stdout
+
+

Section .text.libc.__aeabi_i2d from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__aeabi_i2d:
+  0x08005184:  4B05         LDR        R3, =__aeabi_ui2d        ; [PC, #20] [0x0800519C] =0x08005F8F 
+  0x08005186:  4200         TST        R0, R0
+  0x08005188:  D506         BPL        .L1                      ; 0x08005198
+  0x0800518A:  4240         RSBS       R0, R0, #0
+  0x0800518C:  B500         PUSH       {LR}
+  0x0800518E:  4798         BLX        R3
+  0x08005190:  BC08         POP        {R3}
+  0x08005192:  2201         MOVS       R2, #1
+  0x08005194:  07D2         LSLS       R2, R2, #31
+  0x08005196:  4311         ORRS       R1, R2
+
.L1:
+  0x08005198:  4718         BX         R3
+  0x0800519A:  0000         NOP
+  0x0800519C:  08005F8F     DC.W       __aeabi_ui2d
+
+

Section .text.libc.vfprintf_l from prinops.o (libc_v6m_t_le_eabi_small.a), size=108, align=4

+
+
vfprintf_l:
+  0x080051A0:  B5F0         PUSH       {R4-R7, LR}
+  0x080051A2:  AF03         ADD        R7, SP, #12
+  0x080051A4:  B091         SUB        SP, SP, #68
+  0x080051A6:  466E         MOV        R6, SP
+  0x080051A8:  1DF5         ADDS       R5, R6, #7
+  0x080051AA:  3519         ADDS       R5, #25
+  0x080051AC:  61B3         STR        R3, [R6, #24]
+  0x080051AE:  6172         STR        R2, [R6, #20]
+  0x080051B0:  6071         STR        R1, [R6, #4]
+  0x080051B2:  60F0         STR        R0, [R6, #12]
+  0x080051B4:  F000 FF81    BL         __SEGGER_RTL_X_file_bufsize ; 0x080060BA
+  0x080051B8:  60B0         STR        R0, [R6, #8]
+  0x080051BA:  1DC2         ADDS       R2, R0, #7
+  0x080051BC:  2107         MOVS       R1, #7
+  0x080051BE:  438A         BICS       R2, R1
+  0x080051C0:  4669         MOV        R1, SP
+  0x080051C2:  6131         STR        R1, [R6, #16]
+  0x080051C4:  4669         MOV        R1, SP
+  0x080051C6:  1A88         SUBS       R0, R1, R2
+  0x080051C8:  6030         STR        R0, [R6]
+  0x080051CA:  4685         MOV        SP, R0
+  0x080051CC:  1DF4         ADDS       R4, R6, #7
+  0x080051CE:  3415         ADDS       R4, #21
+  0x080051D0:  4620         MOV        R0, R4
+  0x080051D2:  6871         LDR        R1, [R6, #4]
+  0x080051D4:  F000 FD02    BL         __SEGGER_RTL_init_prin_l ; 0x08005BDC
+  0x080051D8:  480A         LDR        R0, =__SEGGER_RTL_stream_write ; [PC, #40] [0x08005204] =0x080060AB 
+  0x080051DA:  63F0         STR        R0, [R6, #60]
+  0x080051DC:  480A         LDR        R0, =0x7FFFFFFF          ; [PC, #40] [0x08005208] 
+  0x080051DE:  6028         STR        R0, [R5]
+  0x080051E0:  68F0         LDR        R0, [R6, #12]
+  0x080051E2:  6228         STR        R0, [R5, #32]
+  0x080051E4:  68B0         LDR        R0, [R6, #8]
+  0x080051E6:  6168         STR        R0, [R5, #20]
+  0x080051E8:  6830         LDR        R0, [R6]
+  0x080051EA:  60E8         STR        R0, [R5, #12]
+  0x080051EC:  4620         MOV        R0, R4
+  0x080051EE:  6971         LDR        R1, [R6, #20]
+  0x080051F0:  69B2         LDR        R2, [R6, #24]
+  0x080051F2:  F000 F81F    BL         __SEGGER_RTL_vfprintf_int_nwp ; 0x08005234
+  0x080051F6:  6931         LDR        R1, [R6, #16]
+  0x080051F8:  468D         MOV        SP, R1
+  0x080051FA:  1FFE         SUBS       R6, R7, #7
+  0x080051FC:  3E05         SUBS       R6, #5
+  0x080051FE:  46B5         MOV        SP, R6
+  0x08005200:  BDF0         POP        {R4-R7, PC}
+  0x08005202:  46C0         NOP
+  0x08005204:  080060AB     DC.W       __SEGGER_RTL_stream_write
+  0x08005208:  7FFFFFFF     DC.W       0x7FFFFFFF
+
+

Section .text.libc.printf from prinops.o (libc_v6m_t_le_eabi_small.a), size=40, align=4

+
+
printf:
+  0x0800520C:  B083         SUB        SP, SP, #12
+  0x0800520E:  B510         PUSH       {R4, LR}
+  0x08005210:  B081         SUB        SP, SP, #4
+  0x08005212:  4604         MOV        R4, R0
+  0x08005214:  A803         ADD        R0, SP, #12
+  0x08005216:  C00E         STM        R0!, {R1-R3}
+  0x08005218:  4805         LDR        R0, =stdout              ; [PC, #20] [0x08005230] =0x20000B98 
+  0x0800521A:  6800         LDR        R0, [R0]
+  0x0800521C:  AA03         ADD        R2, SP, #12
+  0x0800521E:  9200         STR        R2, [SP, #0]
+  0x08005220:  4621         MOV        R1, R4
+  0x08005222:  F000 FCE4    BL         vfprintf                 ; 0x08005BEE
+  0x08005226:  B001         ADD        SP, SP, #4
+  0x08005228:  BC10         POP        {R4}
+  0x0800522A:  BC02         POP        {R1}
+  0x0800522C:  B003         ADD        SP, SP, #12
+  0x0800522E:  4708         BX         R1
+  0x08005230:  20000B98     DC.W       stdout
+
+

Section .text.libc.__SEGGER_RTL_vfprintf_int_nwp from __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a), size=840, align=4

+
+
__SEGGER_RTL_vfprintf_int_nwp:
+__SEGGER_RTL_vfprintf:
+  0x08005234:  B5F0         PUSH       {R4-R7, LR}
+  0x08005236:  B093         SUB        SP, SP, #76
+  0x08005238:  9208         STR        R2, [SP, #32]
+  0x0800523A:  9109         STR        R1, [SP, #36]
+  0x0800523C:  4605         MOV        R5, R0
+  0x0800523E:  2000         MOVS       R0, #0
+  0x08005240:  9006         STR        R0, [SP, #24]
+  0x08005242:  6028         STR        R0, [R5]
+  0x08005244:  2001         MOVS       R0, #1
+  0x08005246:  0341         LSLS       R1, R0, #13
+  0x08005248:  9102         STR        R1, [SP, #8]
+  0x0800524A:  0381         LSLS       R1, R0, #14
+  0x0800524C:  9105         STR        R1, [SP, #20]
+  0x0800524E:  9001         STR        R0, [SP, #4]
+  0x08005250:  03C0         LSLS       R0, R0, #15
+  0x08005252:  9003         STR        R0, [SP, #12]
+  0x08005254:  9504         STR        R5, [SP, #16]
+
.L1:
+  0x08005256:  9809         LDR        R0, [SP, #36]
+  0x08005258:  1C44         ADDS       R4, R0, #1
+  0x0800525A:  7801         LDRB       R1, [R0]
+  0x0800525C:  2925         CMP        R1, #37
+  0x0800525E:  D007         BEQ        .L3                      ; 0x08005270
+  0x08005260:  2900         CMP        R1, #0
+  0x08005262:  D100         BNE        .L2                      ; 0x08005266
+  0x08005264:  E16E         B          .L63                     ; 0x08005544
+
.L2:
+  0x08005266:  4628         MOV        R0, R5
+  0x08005268:  F000 FC66    BL         __SEGGER_RTL_putc        ; 0x08005B38
+  0x0800526C:  9409         STR        R4, [SP, #36]
+  0x0800526E:  E7F2         B          .L1                      ; 0x08005256
+
.L3:
+  0x08005270:  9F06         LDR        R7, [SP, #24]
+
.L4:
+  0x08005272:  1C61         ADDS       R1, R4, #1
+  0x08005274:  7820         LDRB       R0, [R4]
+  0x08005276:  285E         CMP        R0, #94
+  0x08005278:  460C         MOV        R4, R1
+  0x0800527A:  D0FA         BEQ        .L4                      ; 0x08005272
+  0x0800527C:  287A         CMP        R0, #122
+  0x0800527E:  D01A         BEQ        .L10                     ; 0x080052B6
+  0x08005280:  2823         CMP        R0, #35
+  0x08005282:  D013         BEQ        .L7                      ; 0x080052AC
+  0x08005284:  2827         CMP        R0, #39
+  0x08005286:  D00D         BEQ        .L5                      ; 0x080052A4
+  0x08005288:  282B         CMP        R0, #43
+  0x0800528A:  D00D         BEQ        .L6                      ; 0x080052A8
+  0x0800528C:  2868         CMP        R0, #104
+  0x0800528E:  D015         BEQ        .L12                     ; 0x080052BC
+  0x08005290:  286A         CMP        R0, #106
+  0x08005292:  D00E         BEQ        .L9                      ; 0x080052B2
+  0x08005294:  286C         CMP        R0, #108
+  0x08005296:  D016         BEQ        .L13                     ; 0x080052C6
+  0x08005298:  2874         CMP        R0, #116
+  0x0800529A:  D00C         BEQ        .L10                     ; 0x080052B6
+  0x0800529C:  2820         CMP        R0, #32
+  0x0800529E:  D119         BNE        .L15                     ; 0x080052D4
+  0x080052A0:  2040         MOVS       R0, #64
+  0x080052A2:  E004         B          .L8                      ; 0x080052AE
+
.L5:
+  0x080052A4:  9803         LDR        R0, [SP, #12]
+  0x080052A6:  E002         B          .L8                      ; 0x080052AE
+
.L6:
+  0x080052A8:  2020         MOVS       R0, #32
+  0x080052AA:  E000         B          .L8                      ; 0x080052AE
+
.L7:
+  0x080052AC:  2080         MOVS       R0, #128
+
.L8:
+  0x080052AE:  4307         ORRS       R7, R0
+  0x080052B0:  E7DF         B          .L4                      ; 0x08005272
+
.L9:
+  0x080052B2:  2002         MOVS       R0, #2
+  0x080052B4:  4307         ORRS       R7, R0
+
.L10:
+  0x080052B6:  7808         LDRB       R0, [R1]
+
.L11:
+  0x080052B8:  1C49         ADDS       R1, R1, #1
+  0x080052BA:  E00B         B          .L15                     ; 0x080052D4
+
.L12:
+  0x080052BC:  7808         LDRB       R0, [R1]
+  0x080052BE:  2868         CMP        R0, #104
+  0x080052C0:  D15A         BNE        .L23                     ; 0x08005378
+  0x080052C2:  2008         MOVS       R0, #8
+  0x080052C4:  E003         B          .L14                     ; 0x080052CE
+
.L13:
+  0x080052C6:  7808         LDRB       R0, [R1]
+  0x080052C8:  286C         CMP        R0, #108
+  0x080052CA:  D1F5         BNE        .L11                     ; 0x080052B8
+  0x080052CC:  2002         MOVS       R0, #2
+
.L14:
+  0x080052CE:  4307         ORRS       R7, R0
+  0x080052D0:  7848         LDRB       R0, [R1, #1]
+  0x080052D2:  1C89         ADDS       R1, R1, #2
+
.L15:
+  0x080052D4:  9109         STR        R1, [SP, #36]
+
.L16:
+  0x080052D6:  4601         MOV        R1, R0
+  0x080052D8:  3963         SUBS       R1, #99
+  0x080052DA:  2300         MOVS       R3, #0
+  0x080052DC:  2915         CMP        R1, #21
+  0x080052DE:  D812         BHI        .L17                     ; 0x08005306
+  0x080052E0:  4479         ADD        R1, PC
+  0x080052E2:  7909         LDRB       R1, [R1, #4]
+  0x080052E4:  0049         LSLS       R1, R1, #1
+  0x080052E6:  448F         ADD        PC, R1
+  0x080052E8:  16           DC.B       0x16                     ; '\x16'
+  0x080052E9:  0B           DC.B       0x0B                     ; '\v'
+  0x080052EA:  0A           DC.B       0x0A                     ; '\n'
+  0x080052EB:  0A           DC.B       0x0A                     ; '\n'
+  0x080052EC:  0A           DC.B       0x0A                     ; '\n'
+  0x080052ED:  0A           DC.B       0x0A                     ; '\n'
+  0x080052EE:  0B           DC.B       0x0B                     ; '\v'
+  0x080052EF:  0A           DC.B       0x0A                     ; '\n'
+  0x080052F0:  0A           DC.B       0x0A                     ; '\n'
+  0x080052F1:  0A           DC.B       0x0A                     ; '\n'
+  0x080052F2:  0A           DC.B       0x0A                     ; '\n'
+  0x080052F3:  28           DC.B       0x28                     ; '('
+  0x080052F4:  35           DC.B       0x35                     ; '5'
+  0x080052F5:  1E           DC.B       0x1E                     ; '\x1E'
+  0x080052F6:  0A           DC.B       0x0A                     ; '\n'
+  0x080052F7:  0A           DC.B       0x0A                     ; '\n'
+  0x080052F8:  3A           DC.B       0x3A                     ; ':'
+  0x080052F9:  0A           DC.B       0x0A                     ; '\n'
+  0x080052FA:  59           DC.B       0x59                     ; 'Y'
+  0x080052FB:  0A           DC.B       0x0A                     ; '\n'
+  0x080052FC:  0A           DC.B       0x0A                     ; '\n'
+  0x080052FD:  53           DC.B       0x53                     ; 'S'
+  0x080052FE:  E7AA         B          .L1                      ; 0x08005256
+  0x08005300:  9905         LDR        R1, [SP, #20]
+  0x08005302:  430F         ORRS       R7, R1
+  0x08005304:  E04A         B          .L26                     ; 0x0800539C
+
.L17:
+  0x08005306:  2825         CMP        R0, #37
+  0x08005308:  D03B         BEQ        .L24                     ; 0x08005382
+  0x0800530A:  2858         CMP        R0, #88
+  0x0800530C:  D03E         BEQ        .L25                     ; 0x0800538C
+  0x0800530E:  2800         CMP        R0, #0
+  0x08005310:  D000         BEQ        .L18                     ; 0x08005314
+  0x08005312:  E7A0         B          .L1                      ; 0x08005256
+
.L18:
+  0x08005314:  E125         B          .L66                     ; 0x08005562
+  0x08005316:  9C08         LDR        R4, [SP, #32]
+  0x08005318:  7821         LDRB       R1, [R4]
+  0x0800531A:  4628         MOV        R0, R5
+  0x0800531C:  F000 FC0C    BL         __SEGGER_RTL_putc        ; 0x08005B38
+  0x08005320:  1D24         ADDS       R4, R4, #4
+  0x08005322:  9408         STR        R4, [SP, #32]
+  0x08005324:  E797         B          .L1                      ; 0x08005256
+  0x08005326:  0638         LSLS       R0, R7, #24
+  0x08005328:  17C0         ASRS       R0, R0, #31
+  0x0800532A:  2123         MOVS       R1, #35
+  0x0800532C:  4001         ANDS       R1, R0
+  0x0800532E:  9107         STR        R1, [SP, #28]
+  0x08005330:  9808         LDR        R0, [SP, #32]
+  0x08005332:  C820         LDM        R0!, {R5}
+  0x08005334:  9008         STR        R0, [SP, #32]
+  0x08005336:  2400         MOVS       R4, #0
+  0x08005338:  E0A1         B          .L46                     ; 0x0800547E
+  0x0800533A:  9B08         LDR        R3, [SP, #32]
+  0x0800533C:  6818         LDR        R0, [R3]
+  0x0800533E:  0739         LSLS       R1, R7, #28
+  0x08005340:  6829         LDR        R1, [R5]
+  0x08005342:  D500         BPL        .L19                     ; 0x08005346
+  0x08005344:  E0F0         B          .L58                     ; 0x08005528
+
.L19:
+  0x08005346:  07BA         LSLS       R2, R7, #30
+  0x08005348:  6001         STR        R1, [R0]
+  0x0800534A:  D400         BMI        .L20                     ; 0x0800534E
+  0x0800534C:  E0ED         B          .L59                     ; 0x0800552A
+
.L20:
+  0x0800534E:  2100         MOVS       R1, #0
+  0x08005350:  6041         STR        R1, [R0, #4]
+  0x08005352:  E0EA         B          .L59                     ; 0x0800552A
+  0x08005354:  0639         LSLS       R1, R7, #24
+  0x08005356:  17C9         ASRS       R1, R1, #31
+  0x08005358:  2330         MOVS       R3, #48
+  0x0800535A:  400B         ANDS       R3, R1
+  0x0800535C:  E01E         B          .L26                     ; 0x0800539C
+  0x0800535E:  9E08         LDR        R6, [SP, #32]
+  0x08005360:  6834         LDR        R4, [R6]
+
.L21:
+  0x08005362:  7821         LDRB       R1, [R4]
+  0x08005364:  2900         CMP        R1, #0
+  0x08005366:  D004         BEQ        .L22                     ; 0x08005372
+  0x08005368:  4628         MOV        R0, R5
+  0x0800536A:  F000 FBE5    BL         __SEGGER_RTL_putc        ; 0x08005B38
+  0x0800536E:  1C64         ADDS       R4, R4, #1
+  0x08005370:  E7F7         B          .L21                     ; 0x08005362
+
.L22:
+  0x08005372:  1D36         ADDS       R6, R6, #4
+  0x08005374:  9608         STR        R6, [SP, #32]
+  0x08005376:  E76E         B          .L1                      ; 0x08005256
+
.L23:
+  0x08005378:  1C49         ADDS       R1, R1, #1
+  0x0800537A:  9109         STR        R1, [SP, #36]
+  0x0800537C:  2104         MOVS       R1, #4
+  0x0800537E:  430F         ORRS       R7, R1
+  0x08005380:  E7A9         B          .L16                     ; 0x080052D6
+
.L24:
+  0x08005382:  2125         MOVS       R1, #37
+  0x08005384:  4628         MOV        R0, R5
+  0x08005386:  F000 FBD7    BL         __SEGGER_RTL_putc        ; 0x08005B38
+  0x0800538A:  E764         B          .L1                      ; 0x08005256
+
.L25:
+  0x0800538C:  9902         LDR        R1, [SP, #8]
+  0x0800538E:  430F         ORRS       R7, R1
+  0x08005390:  0639         LSLS       R1, R7, #24
+  0x08005392:  D503         BPL        .L26                     ; 0x0800539C
+  0x08005394:  4B76         LDR        R3, =0x00003058          ; [PC, #0x01D8] [0x08005570] 
+  0x08005396:  2878         CMP        R0, #120
+  0x08005398:  D100         BNE        .L26                     ; 0x0800539C
+  0x0800539A:  3320         ADDS       R3, #32
+
.L26:
+  0x0800539C:  9307         STR        R3, [SP, #28]
+  0x0800539E:  2102         MOVS       R1, #2
+  0x080053A0:  4039         ANDS       R1, R7
+  0x080053A2:  9A05         LDR        R2, [SP, #20]
+  0x080053A4:  4217         TST        R7, R2
+  0x080053A6:  D105         BNE        .L27                     ; 0x080053B4
+  0x080053A8:  2900         CMP        R1, #0
+  0x080053AA:  9A08         LDR        R2, [SP, #32]
+  0x080053AC:  D108         BNE        .L28                     ; 0x080053C0
+  0x080053AE:  1D11         ADDS       R1, R2, #4
+  0x080053B0:  2400         MOVS       R4, #0
+  0x080053B2:  E00B         B          .L29                     ; 0x080053CC
+
.L27:
+  0x080053B4:  2900         CMP        R1, #0
+  0x080053B6:  9B08         LDR        R3, [SP, #32]
+  0x080053B8:  D10F         BNE        .L30                     ; 0x080053DA
+  0x080053BA:  CB02         LDM        R3!, {R1}
+  0x080053BC:  17CC         ASRS       R4, R1, #31
+  0x080053BE:  E011         B          .L31                     ; 0x080053E4
+
.L28:
+  0x080053C0:  1DD2         ADDS       R2, R2, #7
+  0x080053C2:  2107         MOVS       R1, #7
+  0x080053C4:  438A         BICS       R2, R1
+  0x080053C6:  6854         LDR        R4, [R2, #4]
+  0x080053C8:  4611         MOV        R1, R2
+  0x080053CA:  3108         ADDS       R1, #8
+
.L29:
+  0x080053CC:  6815         LDR        R5, [R2]
+  0x080053CE:  077A         LSLS       R2, R7, #29
+  0x080053D0:  D40E         BMI        .L32                     ; 0x080053F0
+  0x080053D2:  073A         LSLS       R2, R7, #28
+  0x080053D4:  D50E         BPL        .L34                     ; 0x080053F4
+  0x080053D6:  B2ED         UXTB       R5, R5
+  0x080053D8:  E00B         B          .L33                     ; 0x080053F2
+
.L30:
+  0x080053DA:  1DDB         ADDS       R3, R3, #7
+  0x080053DC:  2107         MOVS       R1, #7
+  0x080053DE:  438B         BICS       R3, R1
+  0x080053E0:  CB12         LDM        R3!, {R1, R4}
+  0x080053E2:  3300         ADDS       R3, #0
+
.L31:
+  0x080053E4:  077A         LSLS       R2, R7, #29
+  0x080053E6:  D407         BMI        .L35                     ; 0x080053F8
+  0x080053E8:  073A         LSLS       R2, R7, #28
+  0x080053EA:  D408         BMI        .L36                     ; 0x080053FE
+  0x080053EC:  460D         MOV        R5, R1
+  0x080053EE:  E009         B          .L38                     ; 0x08005404
+
.L32:
+  0x080053F0:  B2AD         UXTH       R5, R5
+
.L33:
+  0x080053F2:  2400         MOVS       R4, #0
+
.L34:
+  0x080053F4:  9108         STR        R1, [SP, #32]
+  0x080053F6:  E017         B          .L42                     ; 0x08005428
+
.L35:
+  0x080053F8:  B20D         SXTH       R5, R1
+  0x080053FA:  0409         LSLS       R1, R1, #16
+  0x080053FC:  E001         B          .L37                     ; 0x08005402
+
.L36:
+  0x080053FE:  B24D         SXTB       R5, R1
+  0x08005400:  0609         LSLS       R1, R1, #24
+
.L37:
+  0x08005402:  17CC         ASRS       R4, R1, #31
+
.L38:
+  0x08005404:  2C00         CMP        R4, #0
+  0x08005406:  9308         STR        R3, [SP, #32]
+  0x08005408:  D405         BMI        .L39                     ; 0x08005416
+  0x0800540A:  06B9         LSLS       R1, R7, #26
+  0x0800540C:  D40A         BMI        .L40                     ; 0x08005424
+  0x0800540E:  0679         LSLS       R1, R7, #25
+  0x08005410:  D50A         BPL        .L42                     ; 0x08005428
+  0x08005412:  2120         MOVS       R1, #32
+  0x08005414:  E007         B          .L41                     ; 0x08005426
+
.L39:
+  0x08005416:  2100         MOVS       R1, #0
+  0x08005418:  426D         RSBS       R5, R5, #0
+  0x0800541A:  41A1         SBCS       R1, R4
+  0x0800541C:  222D         MOVS       R2, #45
+  0x0800541E:  9207         STR        R2, [SP, #28]
+  0x08005420:  460C         MOV        R4, R1
+  0x08005422:  E001         B          .L42                     ; 0x08005428
+
.L40:
+  0x08005424:  212B         MOVS       R1, #43
+
.L41:
+  0x08005426:  9107         STR        R1, [SP, #28]
+
.L42:
+  0x08005428:  4601         MOV        R1, R0
+  0x0800542A:  396F         SUBS       R1, #111
+  0x0800542C:  2600         MOVS       R6, #0
+  0x0800542E:  2909         CMP        R1, #9
+  0x08005430:  D81F         BHI        .L45                     ; 0x08005472
+  0x08005432:  46C0         NOP
+  0x08005434:  4479         ADD        R1, PC
+  0x08005436:  7909         LDRB       R1, [R1, #4]
+  0x08005438:  0049         LSLS       R1, R1, #1
+  0x0800543A:  448F         ADD        PC, R1
+  0x0800543C:  04           DC.B       0x04                     ; '\x04'
+  0x0800543D:  20           DC.B       0x20                     ; ' '
+  0x0800543E:  6A           DC.B       0x6A                     ; 'j'
+  0x0800543F:  6A           DC.B       0x6A                     ; 'j'
+  0x08005440:  6A           DC.B       0x6A                     ; 'j'
+  0x08005441:  6A           DC.B       0x6A                     ; 'j'
+  0x08005442:  25           DC.B       0x25                     ; '%'
+  0x08005443:  6A           DC.B       0x6A                     ; 'j'
+  0x08005444:  6A           DC.B       0x6A                     ; 'j'
+  0x08005445:  20           DC.B       0x20                     ; ' '
+  0x08005446:  4628         MOV        R0, R5
+  0x08005448:  4320         ORRS       R0, R4
+  0x0800544A:  D10E         BNE        .L44                     ; 0x0800546A
+  0x0800544C:  A80D         ADD        R0, SP, #52
+  0x0800544E:  2130         MOVS       R1, #48
+  0x08005450:  7001         STRB       R1, [R0]
+  0x08005452:  2601         MOVS       R6, #1
+  0x08005454:  E009         B          .L44                     ; 0x0800546A
+
.L43:
+  0x08005456:  2007         MOVS       R0, #7
+  0x08005458:  4028         ANDS       R0, R5
+  0x0800545A:  3030         ADDS       R0, #48
+  0x0800545C:  A90D         ADD        R1, SP, #52
+  0x0800545E:  5588         STRB       R0, [R1, R6]
+  0x08005460:  08E8         LSRS       R0, R5, #3
+  0x08005462:  0761         LSLS       R1, R4, #29
+  0x08005464:  1845         ADDS       R5, R0, R1
+  0x08005466:  08E4         LSRS       R4, R4, #3
+  0x08005468:  1C76         ADDS       R6, R6, #1
+
.L44:
+  0x0800546A:  4628         MOV        R0, R5
+  0x0800546C:  4320         ORRS       R0, R4
+  0x0800546E:  D050         BEQ        .L56                     ; 0x08005512
+  0x08005470:  E7F1         B          .L43                     ; 0x08005456
+
.L45:
+  0x08005472:  2869         CMP        R0, #105
+  0x08005474:  D008         BEQ        .L47                     ; 0x08005488
+  0x08005476:  2864         CMP        R0, #100
+  0x08005478:  D006         BEQ        .L47                     ; 0x08005488
+  0x0800547A:  2858         CMP        R0, #88
+  0x0800547C:  D149         BNE        .L56                     ; 0x08005512
+
.L46:
+  0x0800547E:  4628         MOV        R0, R5
+  0x08005480:  4320         ORRS       R0, R4
+  0x08005482:  D02E         BEQ        .L51                     ; 0x080054E2
+  0x08005484:  2600         MOVS       R6, #0
+  0x08005486:  E030         B          .L52                     ; 0x080054EA
+
.L47:
+  0x08005488:  4628         MOV        R0, R5
+  0x0800548A:  4320         ORRS       R0, R4
+  0x0800548C:  D103         BNE        .L48                     ; 0x08005496
+  0x0800548E:  A80D         ADD        R0, SP, #52
+  0x08005490:  2130         MOVS       R1, #48
+  0x08005492:  7001         STRB       R1, [R0]
+  0x08005494:  2601         MOVS       R6, #1
+
.L48:
+  0x08005496:  9803         LDR        R0, [SP, #12]
+  0x08005498:  4007         ANDS       R7, R0
+  0x0800549A:  970A         STR        R7, [SP, #40]
+
.L49:
+  0x0800549C:  4628         MOV        R0, R5
+  0x0800549E:  4320         ORRS       R0, R4
+  0x080054A0:  D037         BEQ        .L56                     ; 0x08005512
+  0x080054A2:  2F00         CMP        R7, #0
+  0x080054A4:  D007         BEQ        .L50                     ; 0x080054B6
+  0x080054A6:  2003         MOVS       R0, #3
+  0x080054A8:  4030         ANDS       R0, R6
+  0x080054AA:  2803         CMP        R0, #3
+  0x080054AC:  D103         BNE        .L50                     ; 0x080054B6
+  0x080054AE:  A80D         ADD        R0, SP, #52
+  0x080054B0:  212C         MOVS       R1, #44
+  0x080054B2:  5581         STRB       R1, [R0, R6]
+  0x080054B4:  1C76         ADDS       R6, R6, #1
+
.L50:
+  0x080054B6:  220A         MOVS       R2, #10
+  0x080054B8:  920B         STR        R2, [SP, #44]
+  0x080054BA:  2300         MOVS       R3, #0
+  0x080054BC:  4628         MOV        R0, R5
+  0x080054BE:  4621         MOV        R1, R4
+  0x080054C0:  F000 FDAF    BL         __aeabi_uldivmod         ; 0x08006022
+  0x080054C4:  900C         STR        R0, [SP, #48]
+  0x080054C6:  460C         MOV        R4, R1
+  0x080054C8:  9A0B         LDR        R2, [SP, #44]
+  0x080054CA:  2300         MOVS       R3, #0
+  0x080054CC:  F000 FB1A    BL         __aeabi_lmul             ; 0x08005B04
+  0x080054D0:  1A28         SUBS       R0, R5, R0
+  0x080054D2:  2130         MOVS       R1, #48
+  0x080054D4:  4301         ORRS       R1, R0
+  0x080054D6:  A80D         ADD        R0, SP, #52
+  0x080054D8:  5581         STRB       R1, [R0, R6]
+  0x080054DA:  1C76         ADDS       R6, R6, #1
+  0x080054DC:  9D0C         LDR        R5, [SP, #48]
+  0x080054DE:  9F0A         LDR        R7, [SP, #40]
+  0x080054E0:  E7DC         B          .L49                     ; 0x0800549C
+
.L51:
+  0x080054E2:  A80D         ADD        R0, SP, #52
+  0x080054E4:  2130         MOVS       R1, #48
+  0x080054E6:  7001         STRB       R1, [R0]
+  0x080054E8:  9E01         LDR        R6, [SP, #4]
+
.L52:
+  0x080054EA:  9802         LDR        R0, [SP, #8]
+  0x080054EC:  4207         TST        R7, R0
+  0x080054EE:  D001         BEQ        .L53                     ; 0x080054F4
+  0x080054F0:  4821         LDR        R0, =__SEGGER_RTL_hex_uc ; [PC, #132] [0x08005578] =0x08006910 
+  0x080054F2:  E00B         B          .L55                     ; 0x0800550C
+
.L53:
+  0x080054F4:  481F         LDR        R0, =__SEGGER_RTL_hex_lc ; [PC, #124] [0x08005574] =0x08006920 
+  0x080054F6:  E009         B          .L55                     ; 0x0800550C
+
.L54:
+  0x080054F8:  210F         MOVS       R1, #15
+  0x080054FA:  4029         ANDS       R1, R5
+  0x080054FC:  5C41         LDRB       R1, [R0, R1]
+  0x080054FE:  AA0D         ADD        R2, SP, #52
+  0x08005500:  5591         STRB       R1, [R2, R6]
+  0x08005502:  0929         LSRS       R1, R5, #4
+  0x08005504:  0722         LSLS       R2, R4, #28
+  0x08005506:  188D         ADDS       R5, R1, R2
+  0x08005508:  0924         LSRS       R4, R4, #4
+  0x0800550A:  1C76         ADDS       R6, R6, #1
+
.L55:
+  0x0800550C:  4629         MOV        R1, R5
+  0x0800550E:  4321         ORRS       R1, R4
+  0x08005510:  D1F2         BNE        .L54                     ; 0x080054F8
+
.L56:
+  0x08005512:  9C07         LDR        R4, [SP, #28]
+  0x08005514:  0A21         LSRS       R1, R4, #8
+  0x08005516:  9D04         LDR        R5, [SP, #16]
+  0x08005518:  D003         BEQ        .L57                     ; 0x08005522
+  0x0800551A:  4628         MOV        R0, R5
+  0x0800551C:  F000 FB0C    BL         __SEGGER_RTL_putc        ; 0x08005B38
+  0x08005520:  E006         B          .L60                     ; 0x08005530
+
.L57:
+  0x08005522:  2C00         CMP        R4, #0
+  0x08005524:  D008         BEQ        .L61                     ; 0x08005538
+  0x08005526:  E003         B          .L60                     ; 0x08005530
+
.L58:
+  0x08005528:  7001         STRB       R1, [R0]
+
.L59:
+  0x0800552A:  1D1B         ADDS       R3, R3, #4
+  0x0800552C:  9308         STR        R3, [SP, #32]
+  0x0800552E:  E692         B          .L1                      ; 0x08005256
+
.L60:
+  0x08005530:  4628         MOV        R0, R5
+  0x08005532:  4621         MOV        R1, R4
+  0x08005534:  F000 FB00    BL         __SEGGER_RTL_putc        ; 0x08005B38
+
.L61:
+  0x08005538:  1E76         SUBS       R6, R6, #1
+  0x0800553A:  DA00         BGE        .L62                     ; 0x0800553E
+  0x0800553C:  E68B         B          .L1                      ; 0x08005256
+
.L62:
+  0x0800553E:  A80D         ADD        R0, SP, #52
+  0x08005540:  5D84         LDRB       R4, [R0, R6]
+  0x08005542:  E7F5         B          .L60                     ; 0x08005530
+
.L63:
+  0x08005544:  68E8         LDR        R0, [R5, #12]
+  0x08005546:  2800         CMP        R0, #0
+  0x08005548:  D005         BEQ        .L64                     ; 0x08005556
+  0x0800554A:  CD06         LDM        R5!, {R1-R2}
+  0x0800554C:  3D08         SUBS       R5, #8
+  0x0800554E:  4291         CMP        R1, R2
+  0x08005550:  D201         BCS        .L64                     ; 0x08005556
+  0x08005552:  9A06         LDR        R2, [SP, #24]
+  0x08005554:  5442         STRB       R2, [R0, R1]
+
.L64:
+  0x08005556:  4628         MOV        R0, R5
+  0x08005558:  F000 FB33    BL         __SEGGER_RTL_prin_flush  ; 0x08005BC2
+  0x0800555C:  6828         LDR        R0, [R5]
+
.L65:
+  0x0800555E:  B013         ADD        SP, SP, #76
+  0x08005560:  BDF0         POP        {R4-R7, PC}
+
.L66:
+  0x08005562:  4628         MOV        R0, R5
+  0x08005564:  F000 FB2D    BL         __SEGGER_RTL_prin_flush  ; 0x08005BC2
+  0x08005568:  2000         MOVS       R0, #0
+  0x0800556A:  43C0         MVNS       R0, R0
+  0x0800556C:  E7F7         B          .L65                     ; 0x0800555E
+  0x0800556E:  46C0         NOP
+  0x08005570:  00003058     DC.W       0x00003058
+  0x08005574:  08006920     DC.W       __SEGGER_RTL_hex_lc
+  0x08005578:  08006910     DC.W       __SEGGER_RTL_hex_uc
+
+

Section .text.libc.__SEGGER_RTL_X_file_stat from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=44, align=4

+
+
__SEGGER_RTL_X_file_stat:
+  0x0800557C:  4601         MOV        R1, R0
+  0x0800557E:  4807         LDR        R0, =stdin               ; [PC, #28] [0x0800559C] =0x20000B9C 
+  0x08005580:  6802         LDR        R2, [R0]
+  0x08005582:  2000         MOVS       R0, #0
+  0x08005584:  4291         CMP        R1, R2
+  0x08005586:  D008         BEQ        .L1                      ; 0x0800559A
+  0x08005588:  4A05         LDR        R2, =stdout              ; [PC, #20] [0x080055A0] =0x20000B98 
+  0x0800558A:  6812         LDR        R2, [R2]
+  0x0800558C:  4291         CMP        R1, R2
+  0x0800558E:  D004         BEQ        .L1                      ; 0x0800559A
+  0x08005590:  4A04         LDR        R2, =stderr              ; [PC, #16] [0x080055A4] =0x20000BA0 
+  0x08005592:  6812         LDR        R2, [R2]
+  0x08005594:  4291         CMP        R1, R2
+  0x08005596:  D000         BEQ        .L1                      ; 0x0800559A
+  0x08005598:  43C0         MVNS       R0, R0
+
.L1:
+  0x0800559A:  4770         BX         LR
+  0x0800559C:  20000B9C     DC.W       stdin
+  0x080055A0:  20000B98     DC.W       stdout
+  0x080055A4:  20000BA0     DC.W       stderr
+
+

Section .text.libc._DoInit from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=84, align=4

+
+
_DoInit:
+  0x080055A8:  480F         LDR        R0, =_SEGGER_RTT         ; [PC, #60] [0x080055E8] =0x20000314 
+  0x080055AA:  2103         MOVS       R1, #3
+  0x080055AC:  6101         STR        R1, [R0, #16]
+  0x080055AE:  6141         STR        R1, [R0, #20]
+  0x080055B0:  4A0E         LDR        R2, =0x08006750          ; [PC, #56] [0x080055EC] 
+  0x080055B2:  6182         STR        R2, [R0, #24]
+  0x080055B4:  490E         LDR        R1, =_acUpBuffer         ; [PC, #56] [0x080055F0] =0x20000769 
+  0x080055B6:  61C1         STR        R1, [R0, #28]
+  0x080055B8:  2101         MOVS       R1, #1
+  0x080055BA:  0289         LSLS       R1, R1, #10
+  0x080055BC:  6201         STR        R1, [R0, #32]
+  0x080055BE:  2100         MOVS       R1, #0
+  0x080055C0:  6281         STR        R1, [R0, #40]
+  0x080055C2:  6241         STR        R1, [R0, #36]
+  0x080055C4:  62C1         STR        R1, [R0, #44]
+  0x080055C6:  6602         STR        R2, [R0, #96]
+  0x080055C8:  4A0A         LDR        R2, =_acDownBuffer       ; [PC, #40] [0x080055F4] =0x20000B69 
+  0x080055CA:  6642         STR        R2, [R0, #100]
+  0x080055CC:  2210         MOVS       R2, #16
+  0x080055CE:  6682         STR        R2, [R0, #104]
+  0x080055D0:  6701         STR        R1, [R0, #112]
+  0x080055D2:  66C1         STR        R1, [R0, #108]
+  0x080055D4:  6741         STR        R1, [R0, #116]
+  0x080055D6:  4A08         LDR        R2, =0x0800674E          ; [PC, #32] [0x080055F8] 
+
.L1:
+  0x080055D8:  2910         CMP        R1, #16
+  0x080055DA:  D004         BEQ        .L2                      ; 0x080055E6
+  0x080055DC:  7813         LDRB       R3, [R2]
+  0x080055DE:  5443         STRB       R3, [R0, R1]
+  0x080055E0:  1E52         SUBS       R2, R2, #1
+  0x080055E2:  1C49         ADDS       R1, R1, #1
+  0x080055E4:  E7F8         B          .L1                      ; 0x080055D8
+
.L2:
+  0x080055E6:  4770         BX         LR
+  0x080055E8:  20000314     DC.W       _SEGGER_RTT
+  0x080055EC:  08006750     DC.W       08006750               ; R_ARM_ABS32
+  0x080055F0:  20000769     DC.W       _acUpBuffer
+  0x080055F4:  20000B69     DC.W       _acDownBuffer
+  0x080055F8:  0800674E     DC.W       0800674E               ; R_ARM_ABS32
+
+

Section .text.libc.SEGGER_RTT_WriteNoLock from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=104, align=4

+
+
SEGGER_RTT_WriteNoLock:
+  0x080055FC:  B5F0         PUSH       {R4-R7, LR}
+  0x080055FE:  B081         SUB        SP, SP, #4
+  0x08005600:  460D         MOV        R5, R1
+  0x08005602:  2118         MOVS       R1, #24
+  0x08005604:  4341         MULS       R1, R0, R1
+  0x08005606:  4816         LDR        R0, =_SEGGER_RTT         ; [PC, #88] [0x08005660] =0x20000314 
+  0x08005608:  1846         ADDS       R6, R0, R1
+  0x0800560A:  6AF0         LDR        R0, [R6, #44]
+  0x0800560C:  3618         ADDS       R6, #24
+  0x0800560E:  2802         CMP        R0, #2
+  0x08005610:  D01E         BEQ        .L3                      ; 0x08005650
+  0x08005612:  4614         MOV        R4, R2
+  0x08005614:  2801         CMP        R0, #1
+  0x08005616:  D00E         BEQ        .L1                      ; 0x08005636
+  0x08005618:  2700         MOVS       R7, #0
+  0x0800561A:  2800         CMP        R0, #0
+  0x0800561C:  D11D         BNE        .L4                      ; 0x0800565A
+  0x0800561E:  4630         MOV        R0, R6
+  0x08005620:  F000 FAF7    BL         _GetAvailWriteSpace      ; 0x08005C12
+  0x08005624:  42A0         CMP        R0, R4
+  0x08005626:  D318         BCC        .L4                      ; 0x0800565A
+  0x08005628:  4630         MOV        R0, R6
+  0x0800562A:  4629         MOV        R1, R5
+  0x0800562C:  4622         MOV        R2, R4
+  0x0800562E:  F000 FAFB    BL         _WriteNoCheck            ; 0x08005C28
+  0x08005632:  4627         MOV        R7, R4
+  0x08005634:  E011         B          .L4                      ; 0x0800565A
+
.L1:
+  0x08005636:  4630         MOV        R0, R6
+  0x08005638:  F000 FAEB    BL         _GetAvailWriteSpace      ; 0x08005C12
+  0x0800563C:  4607         MOV        R7, R0
+  0x0800563E:  42A0         CMP        R0, R4
+  0x08005640:  D300         BCC        .L2                      ; 0x08005644
+  0x08005642:  4627         MOV        R7, R4
+
.L2:
+  0x08005644:  4630         MOV        R0, R6
+  0x08005646:  4629         MOV        R1, R5
+  0x08005648:  463A         MOV        R2, R7
+  0x0800564A:  F000 FAED    BL         _WriteNoCheck            ; 0x08005C28
+  0x0800564E:  E004         B          .L4                      ; 0x0800565A
+
.L3:
+  0x08005650:  4630         MOV        R0, R6
+  0x08005652:  4629         MOV        R1, R5
+  0x08005654:  F000 FD33    BL         _WriteBlocking           ; 0x080060BE
+  0x08005658:  4607         MOV        R7, R0
+
.L4:
+  0x0800565A:  4638         MOV        R0, R7
+  0x0800565C:  B001         ADD        SP, SP, #4
+  0x0800565E:  BDF0         POP        {R4-R7, PC}
+  0x08005660:  20000314     DC.W       _SEGGER_RTT
+
+

Section .text.libc.SEGGER_RTT_Write from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=56, align=4

+
+
SEGGER_RTT_Write:
+  0x08005664:  B5F0         PUSH       {R4-R7, LR}
+  0x08005666:  B081         SUB        SP, SP, #4
+  0x08005668:  4614         MOV        R4, R2
+  0x0800566A:  460D         MOV        R5, R1
+  0x0800566C:  4606         MOV        R6, R0
+  0x0800566E:  480A         LDR        R0, =_SEGGER_RTT         ; [PC, #40] [0x08005698] =0x20000314 
+  0x08005670:  7800         LDRB       R0, [R0]
+  0x08005672:  2800         CMP        R0, #0
+  0x08005674:  D101         BNE        .L1                      ; 0x0800567A
+  0x08005676:  F7FF FF97    BL         _DoInit                  ; 0x080055A8
+
.L1:
+  0x0800567A:  F3EF 8710    MRS        R7, PRIMASK
+  0x0800567E:  2101         MOVS       R1, #1
+  0x08005680:  F381 8810    MSR        PRIMASK, R1
+  0x08005684:  4630         MOV        R0, R6
+  0x08005686:  4629         MOV        R1, R5
+  0x08005688:  4622         MOV        R2, R4
+  0x0800568A:  F7FF FFB7    BL         SEGGER_RTT_WriteNoLock   ; 0x080055FC
+  0x0800568E:  F387 8810    MSR        PRIMASK, R7
+  0x08005692:  B001         ADD        SP, SP, #4
+  0x08005694:  BDF0         POP        {R4-R7, PC}
+  0x08005696:  46C0         NOP
+  0x08005698:  20000314     DC.W       _SEGGER_RTT
+
+

Section .text.libc.__SEGGER_RTL_current_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=20, align=4

+
+
__SEGGER_RTL_current_locale:
+  0x0800569C:  4802         LDR        R0, =__SEGGER_RTL_locale_ptr ; [PC, #8] [0x080056A8] =0x200006D8 
+  0x0800569E:  6800         LDR        R0, [R0]
+  0x080056A0:  2800         CMP        R0, #0
+  0x080056A2:  D100         BNE        .L1                      ; 0x080056A6
+  0x080056A4:  4801         LDR        R0, =__SEGGER_RTL_global_locale ; [PC, #4] [0x080056AC] =0x20000B80 
+
.L1:
+  0x080056A6:  4770         BX         LR
+  0x080056A8:  200006D8     DC.W       __SEGGER_RTL_locale_ptr
+  0x080056AC:  20000B80     DC.W       __SEGGER_RTL_global_locale
+
+

Section .text.libc.__SEGGER_RTL_ascii_isctype from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__SEGGER_RTL_ascii_isctype:
+  0x080056B0:  287F         CMP        R0, #127
+  0x080056B2:  D805         BHI        .L1                      ; 0x080056C0
+  0x080056B4:  4A03         LDR        R2, =__SEGGER_RTL_ascii_ctype_map ; [PC, #12] [0x080056C4] =0x08006930 
+  0x080056B6:  5C12         LDRB       R2, [R2, R0]
+  0x080056B8:  4803         LDR        R0, =__SEGGER_RTL_ascii_ctype_mask ; [PC, #12] [0x080056C8] =0x080067BA 
+  0x080056BA:  5C40         LDRB       R0, [R0, R1]
+  0x080056BC:  4010         ANDS       R0, R2
+  0x080056BE:  4770         BX         LR
+
.L1:
+  0x080056C0:  2000         MOVS       R0, #0
+  0x080056C2:  4770         BX         LR
+  0x080056C4:  08006930     DC.W       __SEGGER_RTL_ascii_ctype_map
+  0x080056C8:  080067BA     DC.W       __SEGGER_RTL_ascii_ctype_mask
+
+

Section .text.libc.__SEGGER_RTL_ascii_iswctype from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__SEGGER_RTL_ascii_iswctype:
+  0x080056CC:  287F         CMP        R0, #127
+  0x080056CE:  D805         BHI        .L1                      ; 0x080056DC
+  0x080056D0:  4A03         LDR        R2, =__SEGGER_RTL_ascii_ctype_map ; [PC, #12] [0x080056E0] =0x08006930 
+  0x080056D2:  5C12         LDRB       R2, [R2, R0]
+  0x080056D4:  4803         LDR        R0, =__SEGGER_RTL_ascii_ctype_mask ; [PC, #12] [0x080056E4] =0x080067BA 
+  0x080056D6:  5C40         LDRB       R0, [R0, R1]
+  0x080056D8:  4010         ANDS       R0, R2
+  0x080056DA:  4770         BX         LR
+
.L1:
+  0x080056DC:  2000         MOVS       R0, #0
+  0x080056DE:  4770         BX         LR
+  0x080056E0:  08006930     DC.W       __SEGGER_RTL_ascii_ctype_map
+  0x080056E4:  080067BA     DC.W       __SEGGER_RTL_ascii_ctype_mask
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=4

+
+
__SEGGER_RTL_c_locale:
+  0x080056E8:  0800650D     DC.W       0800650D               ; R_ARM_ABS32
+  0x080056EC:  08005714     DC.W       __SEGGER_RTL_c_locale_data
+  0x080056F0:  080056F4     DC.W       __SEGGER_RTL_codeset_ascii
+
+

Section .rodata.libc.__SEGGER_RTL_codeset_ascii from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=32, align=4

+
+
__SEGGER_RTL_codeset_ascii:
+  0x080056F4:  080056B1     DC.W       __SEGGER_RTL_ascii_isctype
+  0x080056F8:  0800613B     DC.W       __SEGGER_RTL_ascii_toupper
+  0x080056FC:  08005CDB     DC.W       __SEGGER_RTL_ascii_tolower
+  0x08005700:  080056CD     DC.W       __SEGGER_RTL_ascii_iswctype
+  0x08005704:  08006147     DC.W       __SEGGER_RTL_ascii_towupper
+  0x08005708:  08005CE9     DC.W       __SEGGER_RTL_ascii_towlower
+  0x0800570C:  0800612B     DC.W       __SEGGER_RTL_ascii_wctomb
+  0x08005710:  08005CAD     DC.W       __SEGGER_RTL_ascii_mbtowc
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_data from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=88, align=4

+
+
__SEGGER_RTL_c_locale_data:
+  0x08005714:  0800650F     DC.W       __SEGGER_RTL_data_utf8_period
+  0x08005718:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x0800571C:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x08005720:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x08005724:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x08005728:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x0800572C:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x08005730:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x08005734:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x08005738:  080067B9     DC.W       __SEGGER_RTL_data_empty_string
+  0x0800573C:  FF           DC.B       0xFF                     ; '\xFF'
+  0x0800573D:  FF           DC.B       0xFF                     ; '\xFF'
+  0x0800573E:  FF           DC.B       0xFF                     ; '\xFF'
+  0x0800573F:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005740:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005741:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005742:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005743:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005744:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005745:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005746:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005747:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005748:  FF           DC.B       0xFF                     ; '\xFF'
+  0x08005749:  FF           DC.B       0xFF                     ; '\xFF'
+  0x0800574A:  00           DC.B       0x00                     ; '\0'
+  0x0800574B:  00           DC.B       0x00                     ; '\0'
+  0x0800574C:  080064D3     DC.W       __SEGGER_RTL_c_locale_day_names
+  0x08005750:  0800676B     DC.W       __SEGGER_RTL_c_locale_abbrev_day_names
+  0x08005754:  080062E2     DC.W       __SEGGER_RTL_c_locale_month_names
+  0x08005758:  08006788     DC.W       __SEGGER_RTL_c_locale_abbrev_month_names
+  0x0800575C:  08006339     DC.W       __SEGGER_RTL_c_locale_am_pm_indicator
+  0x08005760:  08006759     DC.W       __SEGGER_RTL_c_locale_date_format
+  0x08005764:  08006762     DC.W       __SEGGER_RTL_c_locale_time_format
+  0x08005768:  08006340     DC.W       __SEGGER_RTL_c_locale_date_time_format
+
+

Section .text.NMI_Handler from PowerPro_lto.o, size=2, align=2

+
+
NMI_Handler:
+  0x0800576C:  E7FE         B          NMI_Handler              ; 0x0800576C
+
+

Section .text.HardFault_Handler from PowerPro_lto.o, size=2, align=2

+
+
HardFault_Handler:
+  0x0800576E:  E7FE         B          HardFault_Handler        ; 0x0800576E
+
+

Section .text.SVC_Handler from PowerPro_lto.o, size=2, align=2

+
+
SVC_Handler:
+  0x08005770:  4770         BX         LR
+
+

Section .text.PendSV_Handler from PowerPro_lto.o, size=2, align=2

+
+
PendSV_Handler:
+  0x08005772:  4770         BX         LR
+
+

Section .text.ADC_DMAHalfConvCplt from PowerPro_lto.o, size=2, align=2

+
+
ADC_DMAHalfConvCplt:
+  0x08005774:  4770         BX         LR
+
+

Section .text.UART_DMATxHalfCplt from PowerPro_lto.o, size=2, align=2

+
+
UART_DMATxHalfCplt:
+  0x08005776:  4770         BX         LR
+
+

Section .text.UART_DMAError from PowerPro_lto.o, size=138, align=2

+
+
UART_DMAError:
+  0x08005778:  B5F0         PUSH       {R4-R7, LR}
+  0x0800577A:  B081         SUB        SP, SP, #4
+  0x0800577C:  6A84         LDR        R4, [R0, #40]
+  0x0800577E:  2088         MOVS       R0, #136
+  0x08005780:  5823         LDR        R3, [R4, R0]
+  0x08005782:  4625         MOV        R5, R4
+  0x08005784:  3588         ADDS       R5, #136
+  0x08005786:  686F         LDR        R7, [R5, #4]
+  0x08005788:  4620         MOV        R0, R4
+  0x0800578A:  3056         ADDS       R0, #86
+  0x0800578C:  6822         LDR        R2, [R4]
+  0x0800578E:  6896         LDR        R6, [R2, #8]
+  0x08005790:  0636         LSLS       R6, R6, #24
+  0x08005792:  D523         BPL        .L1                      ; 0x080057DC
+  0x08005794:  2B21         CMP        R3, #33
+  0x08005796:  D121         BNE        .L1                      ; 0x080057DC
+  0x08005798:  2200         MOVS       R2, #0
+  0x0800579A:  8002         STRH       R2, [R0]
+  0x0800579C:  F3EF 8110    MRS        R1, PRIMASK
+  0x080057A0:  9100         STR        R1, [SP, #0]
+  0x080057A2:  2301         MOVS       R3, #1
+  0x080057A4:  F383 8810    MSR        PRIMASK, R3
+  0x080057A8:  6826         LDR        R6, [R4]
+  0x080057AA:  4602         MOV        R2, R0
+  0x080057AC:  4638         MOV        R0, R7
+  0x080057AE:  6837         LDR        R7, [R6]
+  0x080057B0:  21C0         MOVS       R1, #192
+  0x080057B2:  438F         BICS       R7, R1
+  0x080057B4:  6037         STR        R7, [R6]
+  0x080057B6:  4607         MOV        R7, R0
+  0x080057B8:  4610         MOV        R0, R2
+  0x080057BA:  9900         LDR        R1, [SP, #0]
+  0x080057BC:  F381 8810    MSR        PRIMASK, R1
+  0x080057C0:  F3EF 8110    MRS        R1, PRIMASK
+  0x080057C4:  F383 8810    MSR        PRIMASK, R3
+  0x080057C8:  05DA         LSLS       R2, R3, #23
+  0x080057CA:  6823         LDR        R3, [R4]
+  0x080057CC:  689E         LDR        R6, [R3, #8]
+  0x080057CE:  4396         BICS       R6, R2
+  0x080057D0:  609E         STR        R6, [R3, #8]
+  0x080057D2:  F381 8810    MSR        PRIMASK, R1
+  0x080057D6:  2120         MOVS       R1, #32
+  0x080057D8:  6029         STR        R1, [R5]
+  0x080057DA:  6822         LDR        R2, [R4]
+
.L1:
+  0x080057DC:  6891         LDR        R1, [R2, #8]
+  0x080057DE:  0649         LSLS       R1, R1, #25
+  0x080057E0:  D506         BPL        .L2                      ; 0x080057F0
+  0x080057E2:  2F22         CMP        R7, #34
+  0x080057E4:  D104         BNE        .L2                      ; 0x080057F0
+  0x080057E6:  2100         MOVS       R1, #0
+  0x080057E8:  8101         STRH       R1, [R0, #8]
+  0x080057EA:  4620         MOV        R0, R4
+  0x080057EC:  F7FB FE58    BL         UART_EndRxTransfer       ; 0x080014A0
+
.L2:
+  0x080057F0:  68A8         LDR        R0, [R5, #8]
+  0x080057F2:  2110         MOVS       R1, #16
+  0x080057F4:  4301         ORRS       R1, R0
+  0x080057F6:  60A9         STR        R1, [R5, #8]
+  0x080057F8:  4620         MOV        R0, R4
+  0x080057FA:  F7FE FE8B    BL         HAL_UART_ErrorCallback   ; 0x08004514
+  0x080057FE:  B001         ADD        SP, SP, #4
+  0x08005800:  BDF0         POP        {R4-R7, PC}
+
+

Section .init.WWDG_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
WWDG_IRQHandler:
+  0x08005802:  E7FE         B          WWDG_IRQHandler          ; 0x08005802
+
+

Section .init.RTC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
RTC_IRQHandler:
+  0x08005804:  E7FE         B          RTC_IRQHandler           ; 0x08005804
+
+

Section .init.FLASH_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
FLASH_IRQHandler:
+  0x08005806:  E7FE         B          FLASH_IRQHandler         ; 0x08005806
+
+

Section .init.RCC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
RCC_IRQHandler:
+  0x08005808:  E7FE         B          RCC_IRQHandler           ; 0x08005808
+
+

Section .init.EXTI0_1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI0_1_IRQHandler:
+  0x0800580A:  E7FE         B          EXTI0_1_IRQHandler       ; 0x0800580A
+
+

Section .init.EXTI2_3_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI2_3_IRQHandler:
+  0x0800580C:  E7FE         B          EXTI2_3_IRQHandler       ; 0x0800580C
+
+

Section .init.EXTI4_15_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI4_15_IRQHandler:
+  0x0800580E:  E7FE         B          EXTI4_15_IRQHandler      ; 0x0800580E
+
+

Section .init.DMAMUX1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
DMAMUX1_IRQHandler:
+  0x08005810:  E7FE         B          DMAMUX1_IRQHandler       ; 0x08005810
+
+

Section .init.ADC1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
ADC1_IRQHandler:
+  0x08005812:  E7FE         B          ADC1_IRQHandler          ; 0x08005812
+
+

Section .init.TIM1_BRK_UP_TRG_COM_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM1_BRK_UP_TRG_COM_IRQHandler:
+  0x08005814:  E7FE         B          TIM1_BRK_UP_TRG_COM_IRQHandler ; 0x08005814
+
+

Section .init.TIM1_CC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM1_CC_IRQHandler:
+  0x08005816:  E7FE         B          TIM1_CC_IRQHandler       ; 0x08005816
+
+

Section .init.TIM3_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM3_IRQHandler:
+  0x08005818:  E7FE         B          TIM3_IRQHandler          ; 0x08005818
+
+

Section .init.TIM14_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM14_IRQHandler:
+  0x0800581A:  E7FE         B          TIM14_IRQHandler         ; 0x0800581A
+
+

Section .init.TIM17_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM17_IRQHandler:
+  0x0800581C:  E7FE         B          TIM17_IRQHandler         ; 0x0800581C
+
+

Section .init.I2C1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
I2C1_IRQHandler:
+  0x0800581E:  E7FE         B          I2C1_IRQHandler          ; 0x0800581E
+
+

Section .init.SPI1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
SPI1_IRQHandler:
+  0x08005820:  E7FE         B          SPI1_IRQHandler          ; 0x08005820
+
+

Section .init.USART2_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
USART2_IRQHandler:
+  0x08005822:  E7FE         B          USART2_IRQHandler        ; 0x08005822
+
+

Section .text.libc.fputc from fileops.o (libc_v6m_t_le_eabi_small.a), size=34, align=2

+
+
fputc:
+  0x08005824:  B510         PUSH       {R4, LR}
+  0x08005826:  B082         SUB        SP, SP, #8
+  0x08005828:  460B         MOV        R3, R1
+  0x0800582A:  AC01         ADD        R4, SP, #4
+  0x0800582C:  7020         STRB       R0, [R4]
+  0x0800582E:  2101         MOVS       R1, #1
+  0x08005830:  4620         MOV        R0, R4
+  0x08005832:  460A         MOV        R2, R1
+  0x08005834:  F000 F807    BL         fwrite                   ; 0x08005846
+  0x08005838:  2800         CMP        R0, #0
+  0x0800583A:  D001         BEQ        .L1                      ; 0x08005840
+  0x0800583C:  7820         LDRB       R0, [R4]
+  0x0800583E:  E000         B          .L2                      ; 0x08005842
+
.L1:
+  0x08005840:  43C0         MVNS       R0, R0
+
.L2:
+  0x08005842:  B002         ADD        SP, SP, #8
+  0x08005844:  BD10         POP        {R4, PC}
+
+

Section .text.libc.fwrite from fileops.o (libc_v6m_t_le_eabi_small.a), size=50, align=2

+
+
fwrite:
+  0x08005846:  B5F0         PUSH       {R4-R7, LR}
+  0x08005848:  B081         SUB        SP, SP, #4
+  0x0800584A:  B40E         PUSH       {R1-R3}
+  0x0800584C:  BC70         POP        {R4-R6}
+  0x0800584E:  4607         MOV        R7, R0
+  0x08005850:  4618         MOV        R0, R3
+  0x08005852:  F7FF FE93    BL         __SEGGER_RTL_X_file_stat ; 0x0800557C
+  0x08005856:  4601         MOV        R1, R0
+  0x08005858:  2000         MOVS       R0, #0
+  0x0800585A:  2900         CMP        R1, #0
+  0x0800585C:  D40A         BMI        .L1                      ; 0x08005874
+  0x0800585E:  4365         MULS       R5, R4, R5
+  0x08005860:  42A5         CMP        R5, R4
+  0x08005862:  D307         BCC        .L1                      ; 0x08005874
+  0x08005864:  4630         MOV        R0, R6
+  0x08005866:  4639         MOV        R1, R7
+  0x08005868:  462A         MOV        R2, R5
+  0x0800586A:  F000 F9CD    BL         __SEGGER_RTL_X_file_write ; 0x08005C08
+  0x0800586E:  4621         MOV        R1, R4
+  0x08005870:  F000 FBBB    BL         __aeabi_uidiv            ; 0x08005FEA
+
.L1:
+  0x08005874:  B001         ADD        SP, SP, #4
+  0x08005876:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.__aeabi_fmul from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=182, align=2

+
+
__aeabi_fmul:
+  0x08005878:  B430         PUSH       {R4-R5}
+  0x0800587A:  0005         MOVS       R5, R0
+  0x0800587C:  404D         EORS       R5, R1
+  0x0800587E:  2401         MOVS       R4, #1
+  0x08005880:  07E4         LSLS       R4, R4, #31
+  0x08005882:  4025         ANDS       R5, R4
+  0x08005884:  0042         LSLS       R2, R0, #1
+  0x08005886:  004B         LSLS       R3, R1, #1
+  0x08005888:  0E12         LSRS       R2, R2, #24
+  0x0800588A:  D032         BEQ        .L6                      ; 0x080058F2
+  0x0800588C:  0E1B         LSRS       R3, R3, #24
+  0x0800588E:  D03C         BEQ        .L9                      ; 0x0800590A
+  0x08005890:  2AFF         CMP        R2, #255
+  0x08005892:  D033         BEQ        .L8                      ; 0x080058FC
+  0x08005894:  2BFF         CMP        R3, #255
+  0x08005896:  D03F         BEQ        .L11                     ; 0x08005918
+  0x08005898:  18D2         ADDS       R2, R2, R3
+  0x0800589A:  0200         LSLS       R0, R0, #8
+  0x0800589C:  4320         ORRS       R0, R4
+  0x0800589E:  0A00         LSRS       R0, R0, #8
+  0x080058A0:  0209         LSLS       R1, R1, #8
+  0x080058A2:  4321         ORRS       R1, R4
+  0x080058A4:  0A09         LSRS       R1, R1, #8
+  0x080058A6:  B2C4         UXTB       R4, R0
+  0x080058A8:  434C         MULS       R4, R1, R4
+  0x080058AA:  0A00         LSRS       R0, R0, #8
+  0x080058AC:  B2C3         UXTB       R3, R0
+  0x080058AE:  434B         MULS       R3, R1, R3
+  0x080058B0:  0A00         LSRS       R0, R0, #8
+  0x080058B2:  4348         MULS       R0, R1, R0
+  0x080058B4:  0A21         LSRS       R1, R4, #8
+  0x080058B6:  185B         ADDS       R3, R3, R1
+  0x080058B8:  0A19         LSRS       R1, R3, #8
+  0x080058BA:  1809         ADDS       R1, R1, R0
+  0x080058BC:  D401         BMI        .L1                      ; 0x080058C2
+  0x080058BE:  0049         LSLS       R1, R1, #1
+  0x080058C0:  1E52         SUBS       R2, R2, #1
+
.L1:
+  0x080058C2:  0A08         LSRS       R0, R1, #8
+  0x080058C4:  3A7F         SUBS       R2, #127
+  0x080058C6:  DB2A         BLT        .L12                     ; 0x0800591E
+  0x080058C8:  2AFE         CMP        R2, #254
+  0x080058CA:  D20F         BCS        .L5                      ; 0x080058EC
+  0x080058CC:  05D2         LSLS       R2, R2, #23
+  0x080058CE:  431C         ORRS       R4, R3
+  0x080058D0:  0624         LSLS       R4, R4, #24
+  0x080058D2:  D001         BEQ        .L2                      ; 0x080058D8
+  0x080058D4:  2401         MOVS       R4, #1
+  0x080058D6:  4321         ORRS       R1, R4
+
.L2:
+  0x080058D8:  B2C9         UXTB       R1, R1
+  0x080058DA:  2980         CMP        R1, #128
+  0x080058DC:  4150         ADCS       R0, R2
+  0x080058DE:  2980         CMP        R1, #128
+  0x080058E0:  D101         BNE        .L3                      ; 0x080058E6
+  0x080058E2:  0840         LSRS       R0, R0, #1
+  0x080058E4:  0040         LSLS       R0, R0, #1
+
.L3:
+  0x080058E6:  4328         ORRS       R0, R5
+
.L4:
+  0x080058E8:  BC30         POP        {R4-R5}
+  0x080058EA:  4770         BX         LR
+
.L5:
+  0x080058EC:  20FF         MOVS       R0, #255
+  0x080058EE:  05C0         LSLS       R0, R0, #23
+  0x080058F0:  E7F9         B          .L3                      ; 0x080058E6
+
.L6:
+  0x080058F2:  0E1B         LSRS       R3, R3, #24
+  0x080058F4:  2BFF         CMP        R3, #255
+  0x080058F6:  D00A         BEQ        .L10                     ; 0x0800590E
+
.L7:
+  0x080058F8:  0028         MOVS       R0, R5
+  0x080058FA:  E7F5         B          .L4                      ; 0x080058E8
+
.L8:
+  0x080058FC:  0240         LSLS       R0, R0, #9
+  0x080058FE:  D106         BNE        .L10                     ; 0x0800590E
+  0x08005900:  2BFF         CMP        R3, #255
+  0x08005902:  D1F3         BNE        .L5                      ; 0x080058EC
+  0x08005904:  0249         LSLS       R1, R1, #9
+  0x08005906:  D102         BNE        .L10                     ; 0x0800590E
+  0x08005908:  E7F0         B          .L5                      ; 0x080058EC
+
.L9:
+  0x0800590A:  2AFF         CMP        R2, #255
+  0x0800590C:  D1F4         BNE        .L7                      ; 0x080058F8
+
.L10:
+  0x0800590E:  207F         MOVS       R0, #127
+  0x08005910:  0100         LSLS       R0, R0, #4
+  0x08005912:  300C         ADDS       R0, #12
+  0x08005914:  0500         LSLS       R0, R0, #20
+  0x08005916:  E7E7         B          .L4                      ; 0x080058E8
+
.L11:
+  0x08005918:  0249         LSLS       R1, R1, #9
+  0x0800591A:  D1F8         BNE        .L10                     ; 0x0800590E
+  0x0800591C:  E7E6         B          .L5                      ; 0x080058EC
+
.L12:
+  0x0800591E:  0243         LSLS       R3, R0, #9
+  0x08005920:  1C52         ADDS       R2, R2, #1
+  0x08005922:  D1E9         BNE        .L7                      ; 0x080058F8
+  0x08005924:  125B         ASRS       R3, R3, #9
+  0x08005926:  1C9B         ADDS       R3, R3, #2
+  0x08005928:  D9E6         BLS        .L7                      ; 0x080058F8
+  0x0800592A:  05D8         LSLS       R0, R3, #23
+  0x0800592C:  E7E4         B          .L7                      ; 0x080058F8
+
+

Section .text.libc.__aeabi_dmul_aux from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=394, align=2

+
+
__aeabi_dmul_aux:
+  0x0800592E:  D108         BNE        .L2                      ; 0x08005942
+  0x08005930:  2800         CMP        R0, #0
+  0x08005932:  D106         BNE        .L2                      ; 0x08005942
+  0x08005934:  42F5         CMN        R5, R6
+  0x08005936:  D804         BHI        .L2                      ; 0x08005942
+  0x08005938:  D301         BCC        .L1                      ; 0x0800593E
+  0x0800593A:  2A00         CMP        R2, #0
+  0x0800593C:  D101         BNE        .L2                      ; 0x08005942
+
.L1:
+  0x0800593E:  0D6D         LSRS       R5, R5, #21
+  0x08005940:  D109         BNE        .L4                      ; 0x08005956
+
.L2:
+  0x08005942:  2000         MOVS       R0, #0
+  0x08005944:  43C1         MVNS       R1, R0
+  0x08005946:  0D09         LSRS       R1, R1, #20
+  0x08005948:  04C9         LSLS       R1, R1, #19
+  0x0800594A:  BDF0         POP        {R4-R7, PC}
+
.L3:
+  0x0800594C:  D1F9         BNE        .L2                      ; 0x08005942
+  0x0800594E:  4212         TST        R2, R2
+  0x08005950:  D1F7         BNE        .L2                      ; 0x08005942
+  0x08005952:  0D64         LSRS       R4, R4, #21
+  0x08005954:  D0F5         BEQ        .L2                      ; 0x08005942
+
.L4:
+  0x08005956:  2000         MOVS       R0, #0
+  0x08005958:  43C1         MVNS       R1, R0
+  0x0800595A:  0549         LSLS       R1, R1, #21
+  0x0800595C:  0849         LSRS       R1, R1, #1
+  0x0800595E:  E0A6         B          .L7                      ; 0x08005AAE
+
.L5:
+  0x08005960:  2000         MOVS       R0, #0
+  0x08005962:  4661         MOV        R1, R12
+  0x08005964:  BDF0         POP        {R4-R7, PC}
+
__aeabi_dmul:
+  0x08005966:  B5F0         PUSH       {R4-R7, LR}
+  0x08005968:  2701         MOVS       R7, #1
+  0x0800596A:  07FF         LSLS       R7, R7, #31
+  0x0800596C:  000E         MOVS       R6, R1
+  0x0800596E:  405E         EORS       R6, R3
+  0x08005970:  403E         ANDS       R6, R7
+  0x08005972:  46B4         MOV        R12, R6
+  0x08005974:  0ABE         LSRS       R6, R7, #10
+  0x08005976:  184C         ADDS       R4, R1, R1
+  0x08005978:  18DD         ADDS       R5, R3, R3
+  0x0800597A:  42F4         CMN        R4, R6
+  0x0800597C:  D2D7         BCS        __aeabi_dmul_aux         ; 0x0800592E
+  0x0800597E:  42F5         CMN        R5, R6
+  0x08005980:  D2E4         BCS        .L3                      ; 0x0800594C
+  0x08005982:  0D64         LSRS       R4, R4, #21
+  0x08005984:  D0EC         BEQ        .L5                      ; 0x08005960
+  0x08005986:  0D6D         LSRS       R5, R5, #21
+  0x08005988:  D0EA         BEQ        .L5                      ; 0x08005960
+  0x0800598A:  1964         ADDS       R4, R4, R5
+  0x0800598C:  02C9         LSLS       R1, R1, #11
+  0x0800598E:  4339         ORRS       R1, R7
+  0x08005990:  0D46         LSRS       R6, R0, #21
+  0x08005992:  02C0         LSLS       R0, R0, #11
+  0x08005994:  4331         ORRS       R1, R6
+  0x08005996:  02DB         LSLS       R3, R3, #11
+  0x08005998:  433B         ORRS       R3, R7
+  0x0800599A:  0ADB         LSRS       R3, R3, #11
+  0x0800599C:  B410         PUSH       {R4}
+  0x0800599E:  468E         MOV        LR, R1
+  0x080059A0:  B285         UXTH       R5, R0
+  0x080059A2:  B297         UXTH       R7, R2
+  0x080059A4:  436F         MULS       R7, R5, R7
+  0x080059A6:  0C14         LSRS       R4, R2, #16
+  0x080059A8:  436C         MULS       R4, R5, R4
+  0x080059AA:  0C3E         LSRS       R6, R7, #16
+  0x080059AC:  19A4         ADDS       R4, R4, R6
+  0x080059AE:  0C26         LSRS       R6, R4, #16
+  0x080059B0:  0424         LSLS       R4, R4, #16
+  0x080059B2:  B2BF         UXTH       R7, R7
+  0x080059B4:  4327         ORRS       R7, R4
+  0x080059B6:  B29C         UXTH       R4, R3
+  0x080059B8:  436C         MULS       R4, R5, R4
+  0x080059BA:  19A4         ADDS       R4, R4, R6
+  0x080059BC:  0C19         LSRS       R1, R3, #16
+  0x080059BE:  4369         MULS       R1, R5, R1
+  0x080059C0:  0C25         LSRS       R5, R4, #16
+  0x080059C2:  B2A4         UXTH       R4, R4
+  0x080059C4:  1949         ADDS       R1, R1, R5
+  0x080059C6:  040D         LSLS       R5, R1, #16
+  0x080059C8:  0C09         LSRS       R1, R1, #16
+  0x080059CA:  1964         ADDS       R4, R4, R5
+  0x080059CC:  0C00         LSRS       R0, R0, #16
+  0x080059CE:  B295         UXTH       R5, R2
+  0x080059D0:  4345         MULS       R5, R0, R5
+  0x080059D2:  0C3E         LSRS       R6, R7, #16
+  0x080059D4:  1976         ADDS       R6, R6, R5
+  0x080059D6:  4337         ORRS       R7, R6
+  0x080059D8:  B2BF         UXTH       R7, R7
+  0x080059DA:  0C36         LSRS       R6, R6, #16
+  0x080059DC:  0C15         LSRS       R5, R2, #16
+  0x080059DE:  4345         MULS       R5, R0, R5
+  0x080059E0:  19AD         ADDS       R5, R5, R6
+  0x080059E2:  B2A6         UXTH       R6, R4
+  0x080059E4:  0C24         LSRS       R4, R4, #16
+  0x080059E6:  19AD         ADDS       R5, R5, R6
+  0x080059E8:  042E         LSLS       R6, R5, #16
+  0x080059EA:  4337         ORRS       R7, R6
+  0x080059EC:  0C2E         LSRS       R6, R5, #16
+  0x080059EE:  1936         ADDS       R6, R6, R4
+  0x080059F0:  B29D         UXTH       R5, R3
+  0x080059F2:  4345         MULS       R5, R0, R5
+  0x080059F4:  19AD         ADDS       R5, R5, R6
+  0x080059F6:  B2AC         UXTH       R4, R5
+  0x080059F8:  0C2E         LSRS       R6, R5, #16
+  0x080059FA:  1989         ADDS       R1, R1, R6
+  0x080059FC:  0C1D         LSRS       R5, R3, #16
+  0x080059FE:  4345         MULS       R5, R0, R5
+  0x08005A00:  186D         ADDS       R5, R5, R1
+  0x08005A02:  042E         LSLS       R6, R5, #16
+  0x08005A04:  0C29         LSRS       R1, R5, #16
+  0x08005A06:  4334         ORRS       R4, R6
+  0x08005A08:  4670         MOV        R0, LR
+  0x08005A0A:  B280         UXTH       R0, R0
+  0x08005A0C:  B295         UXTH       R5, R2
+  0x08005A0E:  4345         MULS       R5, R0, R5
+  0x08005A10:  0C3E         LSRS       R6, R7, #16
+  0x08005A12:  1976         ADDS       R6, R6, R5
+  0x08005A14:  4337         ORRS       R7, R6
+  0x08005A16:  B2BF         UXTH       R7, R7
+  0x08005A18:  0C36         LSRS       R6, R6, #16
+  0x08005A1A:  0C15         LSRS       R5, R2, #16
+  0x08005A1C:  4345         MULS       R5, R0, R5
+  0x08005A1E:  19AD         ADDS       R5, R5, R6
+  0x08005A20:  B2A6         UXTH       R6, R4
+  0x08005A22:  19AD         ADDS       R5, R5, R6
+  0x08005A24:  0C24         LSRS       R4, R4, #16
+  0x08005A26:  042E         LSLS       R6, R5, #16
+  0x08005A28:  4337         ORRS       R7, R6
+  0x08005A2A:  0C2E         LSRS       R6, R5, #16
+  0x08005A2C:  1936         ADDS       R6, R6, R4
+  0x08005A2E:  B29D         UXTH       R5, R3
+  0x08005A30:  4345         MULS       R5, R0, R5
+  0x08005A32:  19AD         ADDS       R5, R5, R6
+  0x08005A34:  B2AC         UXTH       R4, R5
+  0x08005A36:  0C2E         LSRS       R6, R5, #16
+  0x08005A38:  1989         ADDS       R1, R1, R6
+  0x08005A3A:  0C1D         LSRS       R5, R3, #16
+  0x08005A3C:  4345         MULS       R5, R0, R5
+  0x08005A3E:  186D         ADDS       R5, R5, R1
+  0x08005A40:  042E         LSLS       R6, R5, #16
+  0x08005A42:  4334         ORRS       R4, R6
+  0x08005A44:  0C29         LSRS       R1, R5, #16
+  0x08005A46:  4675         MOV        R5, LR
+  0x08005A48:  0C2D         LSRS       R5, R5, #16
+  0x08005A4A:  B290         UXTH       R0, R2
+  0x08005A4C:  4368         MULS       R0, R5, R0
+  0x08005A4E:  0C3E         LSRS       R6, R7, #16
+  0x08005A50:  1980         ADDS       R0, R0, R6
+  0x08005A52:  0406         LSLS       R6, R0, #16
+  0x08005A54:  B2BF         UXTH       R7, R7
+  0x08005A56:  433E         ORRS       R6, R7
+  0x08005A58:  0C07         LSRS       R7, R0, #16
+  0x08005A5A:  B2A0         UXTH       R0, R4
+  0x08005A5C:  183F         ADDS       R7, R7, R0
+  0x08005A5E:  0C12         LSRS       R2, R2, #16
+  0x08005A60:  436A         MULS       R2, R5, R2
+  0x08005A62:  19D0         ADDS       R0, R2, R7
+  0x08005A64:  0C02         LSRS       R2, R0, #16
+  0x08005A66:  B280         UXTH       R0, R0
+  0x08005A68:  0C24         LSRS       R4, R4, #16
+  0x08005A6A:  18A4         ADDS       R4, R4, R2
+  0x08005A6C:  B29A         UXTH       R2, R3
+  0x08005A6E:  436A         MULS       R2, R5, R2
+  0x08005A70:  1912         ADDS       R2, R2, R4
+  0x08005A72:  0414         LSLS       R4, R2, #16
+  0x08005A74:  4320         ORRS       R0, R4
+  0x08005A76:  0C12         LSRS       R2, R2, #16
+  0x08005A78:  1889         ADDS       R1, R1, R2
+  0x08005A7A:  0C1B         LSRS       R3, R3, #16
+  0x08005A7C:  436B         MULS       R3, R5, R3
+  0x08005A7E:  18C9         ADDS       R1, R1, R3
+  0x08005A80:  BC10         POP        {R4}
+  0x08005A82:  2701         MOVS       R7, #1
+  0x08005A84:  053D         LSLS       R5, R7, #20
+  0x08005A86:  4229         TST        R1, R5
+  0x08005A88:  D103         BNE        .L6                      ; 0x08005A92
+  0x08005A8A:  19B6         ADDS       R6, R6, R6
+  0x08005A8C:  4140         ADCS       R0, R0
+  0x08005A8E:  4149         ADCS       R1, R1
+  0x08005A90:  1E64         SUBS       R4, R4, #1
+
.L6:
+  0x08005A92:  07FF         LSLS       R7, R7, #31
+  0x08005A94:  0D7D         LSRS       R5, R7, #21
+  0x08005A96:  1E6D         SUBS       R5, R5, #1
+  0x08005A98:  1B64         SUBS       R4, R4, R5
+  0x08005A9A:  DB0B         BLT        .L8                      ; 0x08005AB4
+  0x08005A9C:  006D         LSLS       R5, R5, #1
+  0x08005A9E:  42AC         CMP        R4, R5
+  0x08005AA0:  DA09         BGE        .L9                      ; 0x08005AB6
+  0x08005AA2:  0524         LSLS       R4, R4, #20
+  0x08005AA4:  2500         MOVS       R5, #0
+  0x08005AA6:  0842         LSRS       R2, R0, #1
+  0x08005AA8:  41BE         SBCS       R6, R7
+  0x08005AAA:  4168         ADCS       R0, R5
+  0x08005AAC:  4161         ADCS       R1, R4
+
.L7:
+  0x08005AAE:  4666         MOV        R6, R12
+  0x08005AB0:  4331         ORRS       R1, R6
+  0x08005AB2:  BDF0         POP        {R4-R7, PC}
+
.L8:
+  0x08005AB4:  E754         B          .L5                      ; 0x08005960
+
.L9:
+  0x08005AB6:  E74E         B          .L4                      ; 0x08005956
+
+

Section .text.libc.__aeabi_d2uiz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__aeabi_d2uiz:
+  0x08005AB8:  004A         LSLS       R2, R1, #1
+  0x08005ABA:  D210         BCS        .L1                      ; 0x08005ADE
+  0x08005ABC:  0D52         LSRS       R2, R2, #21
+  0x08005ABE:  2303         MOVS       R3, #3
+  0x08005AC0:  021B         LSLS       R3, R3, #8
+  0x08005AC2:  33FF         ADDS       R3, #255
+  0x08005AC4:  1AD2         SUBS       R2, R2, R3
+  0x08005AC6:  D40A         BMI        .L1                      ; 0x08005ADE
+  0x08005AC8:  4252         RSBS       R2, R2, #0
+  0x08005ACA:  321F         ADDS       R2, #31
+  0x08005ACC:  D409         BMI        .L2                      ; 0x08005AE2
+  0x08005ACE:  0D40         LSRS       R0, R0, #21
+  0x08005AD0:  02C9         LSLS       R1, R1, #11
+  0x08005AD2:  4308         ORRS       R0, R1
+  0x08005AD4:  2301         MOVS       R3, #1
+  0x08005AD6:  07DB         LSLS       R3, R3, #31
+  0x08005AD8:  4318         ORRS       R0, R3
+  0x08005ADA:  40D0         LSRS       R0, R2
+  0x08005ADC:  4770         BX         LR
+
.L1:
+  0x08005ADE:  2000         MOVS       R0, #0
+  0x08005AE0:  4770         BX         LR
+
.L2:
+  0x08005AE2:  17D0         ASRS       R0, R2, #31
+  0x08005AE4:  4770         BX         LR
+
+

Section .text.libc.__aeabi_ui2f from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=30, align=2

+
+
__aeabi_ui2f:
+  0x08005AE6:  229D         MOVS       R2, #157
+  0x08005AE8:  0001         MOVS       R1, R0
+  0x08005AEA:  D00A         BEQ        .L4                      ; 0x08005B02
+  0x08005AEC:  D402         BMI        .L2                      ; 0x08005AF4
+
.L1:
+  0x08005AEE:  1E52         SUBS       R2, R2, #1
+  0x08005AF0:  0049         LSLS       R1, R1, #1
+  0x08005AF2:  D5FC         BPL        .L1                      ; 0x08005AEE
+
.L2:
+  0x08005AF4:  05D2         LSLS       R2, R2, #23
+  0x08005AF6:  0A08         LSRS       R0, R1, #8
+  0x08005AF8:  0609         LSLS       R1, R1, #24
+  0x08005AFA:  4149         ADCS       R1, R1
+  0x08005AFC:  D300         BCC        .L3                      ; 0x08005B00
+  0x08005AFE:  2901         CMP        R1, #1
+
.L3:
+  0x08005B00:  4150         ADCS       R0, R2
+
.L4:
+  0x08005B02:  4770         BX         LR
+
+

Section .text.libc.__aeabi_lmul from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__aeabi_lmul:
+  0x08005B04:  B530         PUSH       {R4-R5, LR}
+  0x08005B06:  4351         MULS       R1, R2, R1
+  0x08005B08:  4343         MULS       R3, R0, R3
+  0x08005B0A:  185C         ADDS       R4, R3, R1
+  0x08005B0C:  0C01         LSRS       R1, R0, #16
+  0x08005B0E:  0C13         LSRS       R3, R2, #16
+  0x08005B10:  000D         MOVS       R5, R1
+  0x08005B12:  435D         MULS       R5, R3, R5
+  0x08005B14:  1964         ADDS       R4, R4, R5
+  0x08005B16:  B292         UXTH       R2, R2
+  0x08005B18:  4351         MULS       R1, R2, R1
+  0x08005B1A:  B280         UXTH       R0, R0
+  0x08005B1C:  4342         MULS       R2, R0, R2
+  0x08005B1E:  0C0D         LSRS       R5, R1, #16
+  0x08005B20:  0409         LSLS       R1, R1, #16
+  0x08005B22:  1852         ADDS       R2, R2, R1
+  0x08005B24:  4165         ADCS       R5, R4
+  0x08005B26:  4358         MULS       R0, R3, R0
+  0x08005B28:  0C01         LSRS       R1, R0, #16
+  0x08005B2A:  0400         LSLS       R0, R0, #16
+  0x08005B2C:  1880         ADDS       R0, R0, R2
+  0x08005B2E:  4169         ADCS       R1, R5
+  0x08005B30:  BD30         POP        {R4-R5, PC}
+
+

Section .text.libc.__aeabi_idiv0 from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=6, align=2

+
+
__aeabi_idiv0:
+  0x08005B32:  2000         MOVS       R0, #0
+  0x08005B34:  2100         MOVS       R1, #0
+  0x08005B36:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_putc from prinops.o (libc_v6m_t_le_eabi_small.a), size=138, align=2

+
+
__SEGGER_RTL_putc:
+  0x08005B38:  B530         PUSH       {R4-R5, LR}
+  0x08005B3A:  B081         SUB        SP, SP, #4
+  0x08005B3C:  4604         MOV        R4, R0
+  0x08005B3E:  4668         MOV        R0, SP
+  0x08005B40:  7001         STRB       R1, [R0]
+  0x08005B42:  6920         LDR        R0, [R4, #16]
+  0x08005B44:  2800         CMP        R0, #0
+  0x08005B46:  D00F         BEQ        .L1                      ; 0x08005B68
+  0x08005B48:  CC0C         LDM        R4!, {R2-R3}
+  0x08005B4A:  3C08         SUBS       R4, #8
+  0x08005B4C:  429A         CMP        R2, R3
+  0x08005B4E:  D233         BCS        .L7                      ; 0x08005BB8
+  0x08005B50:  6962         LDR        R2, [R4, #20]
+  0x08005B52:  1C53         ADDS       R3, R2, #1
+  0x08005B54:  6163         STR        R3, [R4, #20]
+  0x08005B56:  5481         STRB       R1, [R0, R2]
+  0x08005B58:  69A0         LDR        R0, [R4, #24]
+  0x08005B5A:  6961         LDR        R1, [R4, #20]
+  0x08005B5C:  4281         CMP        R1, R0
+  0x08005B5E:  D12B         BNE        .L7                      ; 0x08005BB8
+  0x08005B60:  4620         MOV        R0, R4
+  0x08005B62:  F000 F82E    BL         __SEGGER_RTL_prin_flush  ; 0x08005BC2
+  0x08005B66:  E027         B          .L7                      ; 0x08005BB8
+
.L1:
+  0x08005B68:  68E0         LDR        R0, [R4, #12]
+  0x08005B6A:  2800         CMP        R0, #0
+  0x08005B6C:  D009         BEQ        .L3                      ; 0x08005B82
+  0x08005B6E:  CC0C         LDM        R4!, {R2-R3}
+  0x08005B70:  3C08         SUBS       R4, #8
+  0x08005B72:  429A         CMP        R2, R3
+  0x08005B74:  D220         BCS        .L7                      ; 0x08005BB8
+  0x08005B76:  1C55         ADDS       R5, R2, #1
+  0x08005B78:  429D         CMP        R5, R3
+  0x08005B7A:  D100         BNE        .L2                      ; 0x08005B7E
+  0x08005B7C:  2100         MOVS       R1, #0
+
.L2:
+  0x08005B7E:  5481         STRB       R1, [R0, R2]
+  0x08005B80:  E01A         B          .L7                      ; 0x08005BB8
+
.L3:
+  0x08005B82:  68A0         LDR        R0, [R4, #8]
+  0x08005B84:  2800         CMP        R0, #0
+  0x08005B86:  D008         BEQ        .L4                      ; 0x08005B9A
+  0x08005B88:  CC0C         LDM        R4!, {R2-R3}
+  0x08005B8A:  3C08         SUBS       R4, #8
+  0x08005B8C:  429A         CMP        R2, R3
+  0x08005B8E:  D213         BCS        .L7                      ; 0x08005BB8
+  0x08005B90:  1C55         ADDS       R5, R2, #1
+  0x08005B92:  429D         CMP        R5, R3
+  0x08005B94:  D00D         BEQ        .L5                      ; 0x08005BB2
+  0x08005B96:  B2C9         UXTB       R1, R1
+  0x08005B98:  E00C         B          .L6                      ; 0x08005BB4
+
.L4:
+  0x08005B9A:  6A23         LDR        R3, [R4, #32]
+  0x08005B9C:  2B00         CMP        R3, #0
+  0x08005B9E:  D00B         BEQ        .L7                      ; 0x08005BB8
+  0x08005BA0:  CC03         LDM        R4!, {R0-R1}
+  0x08005BA2:  3C08         SUBS       R4, #8
+  0x08005BA4:  4288         CMP        R0, R1
+  0x08005BA6:  D207         BCS        .L7                      ; 0x08005BB8
+  0x08005BA8:  4669         MOV        R1, SP
+  0x08005BAA:  2201         MOVS       R2, #1
+  0x08005BAC:  4620         MOV        R0, R4
+  0x08005BAE:  4798         BLX        R3
+  0x08005BB0:  E002         B          .L7                      ; 0x08005BB8
+
.L5:
+  0x08005BB2:  2100         MOVS       R1, #0
+
.L6:
+  0x08005BB4:  0092         LSLS       R2, R2, #2
+  0x08005BB6:  5081         STR        R1, [R0, R2]
+
.L7:
+  0x08005BB8:  6820         LDR        R0, [R4]
+  0x08005BBA:  1C40         ADDS       R0, R0, #1
+  0x08005BBC:  6020         STR        R0, [R4]
+  0x08005BBE:  B001         ADD        SP, SP, #4
+  0x08005BC0:  BD30         POP        {R4-R5, PC}
+
+

Section .text.libc.__SEGGER_RTL_prin_flush from prinops.o (libc_v6m_t_le_eabi_small.a), size=26, align=2

+
+
__SEGGER_RTL_prin_flush:
+  0x08005BC2:  B510         PUSH       {R4, LR}
+  0x08005BC4:  6942         LDR        R2, [R0, #20]
+  0x08005BC6:  2A00         CMP        R2, #0
+  0x08005BC8:  D007         BEQ        .L2                      ; 0x08005BDA
+  0x08005BCA:  4604         MOV        R4, R0
+  0x08005BCC:  6A03         LDR        R3, [R0, #32]
+  0x08005BCE:  2B00         CMP        R3, #0
+  0x08005BD0:  D001         BEQ        .L1                      ; 0x08005BD6
+  0x08005BD2:  6921         LDR        R1, [R4, #16]
+  0x08005BD4:  4798         BLX        R3
+
.L1:
+  0x08005BD6:  2000         MOVS       R0, #0
+  0x08005BD8:  6160         STR        R0, [R4, #20]
+
.L2:
+  0x08005BDA:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_init_prin_l from prinops.o (libc_v6m_t_le_eabi_small.a), size=18, align=2

+
+
__SEGGER_RTL_init_prin_l:
+  0x08005BDC:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x08005BDE:  460C         MOV        R4, R1
+  0x08005BE0:  4605         MOV        R5, R0
+  0x08005BE2:  2100         MOVS       R1, #0
+  0x08005BE4:  2224         MOVS       R2, #36
+  0x08005BE6:  F000 FA9A    BL         memset                   ; 0x0800611E
+  0x08005BEA:  61EC         STR        R4, [R5, #28]
+  0x08005BEC:  BDB0         POP        {R4-R5, R7, PC}
+
+

Section .text.libc.vfprintf from prinops.o (libc_v6m_t_le_eabi_small.a), size=26, align=2

+
+
vfprintf:
+  0x08005BEE:  B570         PUSH       {R4-R6, LR}
+  0x08005BF0:  4614         MOV        R4, R2
+  0x08005BF2:  460D         MOV        R5, R1
+  0x08005BF4:  4606         MOV        R6, R0
+  0x08005BF6:  F7FF FD51    BL         __SEGGER_RTL_current_locale ; 0x0800569C
+  0x08005BFA:  4601         MOV        R1, R0
+  0x08005BFC:  4630         MOV        R0, R6
+  0x08005BFE:  462A         MOV        R2, R5
+  0x08005C00:  4623         MOV        R3, R4
+  0x08005C02:  F7FF FACD    BL         vfprintf_l               ; 0x080051A0
+  0x08005C06:  BD70         POP        {R4-R6, PC}
+
+

Section .text.libc.__SEGGER_RTL_X_file_write from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=10, align=2

+
+
__SEGGER_RTL_X_file_write:
+  0x08005C08:  B580         PUSH       {R7, LR}
+  0x08005C0A:  6800         LDR        R0, [R0]
+  0x08005C0C:  F7FF FD2A    BL         SEGGER_RTT_Write         ; 0x08005664
+  0x08005C10:  BD80         POP        {R7, PC}
+
+

Section .text.libc._GetAvailWriteSpace from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=22, align=2

+
+
_GetAvailWriteSpace:
+  0x08005C12:  68C2         LDR        R2, [R0, #12]
+  0x08005C14:  6901         LDR        R1, [R0, #16]
+  0x08005C16:  4291         CMP        R1, R2
+  0x08005C18:  D901         BLS        .L1                      ; 0x08005C1E
+  0x08005C1A:  43D0         MVNS       R0, R2
+  0x08005C1C:  E002         B          .L2                      ; 0x08005C24
+
.L1:
+  0x08005C1E:  43D2         MVNS       R2, R2
+  0x08005C20:  1889         ADDS       R1, R1, R2
+  0x08005C22:  6880         LDR        R0, [R0, #8]
+
.L2:
+  0x08005C24:  1808         ADDS       R0, R1, R0
+  0x08005C26:  4770         BX         LR
+
+

Section .text.libc._WriteNoCheck from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=58, align=2

+
+
_WriteNoCheck:
+  0x08005C28:  B5F0         PUSH       {R4-R7, LR}
+  0x08005C2A:  B081         SUB        SP, SP, #4
+  0x08005C2C:  4615         MOV        R5, R2
+  0x08005C2E:  4604         MOV        R4, R0
+  0x08005C30:  6840         LDR        R0, [R0, #4]
+  0x08005C32:  68A2         LDR        R2, [R4, #8]
+  0x08005C34:  68E6         LDR        R6, [R4, #12]
+  0x08005C36:  1980         ADDS       R0, R0, R6
+  0x08005C38:  1B97         SUBS       R7, R2, R6
+  0x08005C3A:  42BD         CMP        R5, R7
+  0x08005C3C:  D204         BCS        .L1                      ; 0x08005C48
+  0x08005C3E:  462A         MOV        R2, R5
+  0x08005C40:  F000 F82D    BL         memcpy                   ; 0x08005C9E
+  0x08005C44:  1975         ADDS       R5, R6, R5
+  0x08005C46:  E009         B          .L2                      ; 0x08005C5C
+
.L1:
+  0x08005C48:  460E         MOV        R6, R1
+  0x08005C4A:  463A         MOV        R2, R7
+  0x08005C4C:  F000 F827    BL         memcpy                   ; 0x08005C9E
+  0x08005C50:  19F1         ADDS       R1, R6, R7
+  0x08005C52:  1BED         SUBS       R5, R5, R7
+  0x08005C54:  6860         LDR        R0, [R4, #4]
+  0x08005C56:  462A         MOV        R2, R5
+  0x08005C58:  F000 F821    BL         memcpy                   ; 0x08005C9E
+
.L2:
+  0x08005C5C:  60E5         STR        R5, [R4, #12]
+  0x08005C5E:  B001         ADD        SP, SP, #4
+  0x08005C60:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.memcmp from strops.o (strops_v6m_t_le_eabi_small.a), size=46, align=2

+
+
memcmp:
+  0x08005C62:  B5F0         PUSH       {R4-R7, LR}
+  0x08005C64:  2A00         CMP        R2, #0
+  0x08005C66:  D00D         BEQ        .L2                      ; 0x08005C84
+  0x08005C68:  1E52         SUBS       R2, R2, #1
+  0x08005C6A:  4613         MOV        R3, R2
+  0x08005C6C:  4604         MOV        R4, R0
+  0x08005C6E:  460D         MOV        R5, R1
+
.L1:
+  0x08005C70:  2B00         CMP        R3, #0
+  0x08005C72:  D009         BEQ        .L3                      ; 0x08005C88
+  0x08005C74:  782E         LDRB       R6, [R5]
+  0x08005C76:  7827         LDRB       R7, [R4]
+  0x08005C78:  42B7         CMP        R7, R6
+  0x08005C7A:  D107         BNE        .L4                      ; 0x08005C8C
+  0x08005C7C:  1E5B         SUBS       R3, R3, #1
+  0x08005C7E:  1C6D         ADDS       R5, R5, #1
+  0x08005C80:  1C64         ADDS       R4, R4, #1
+  0x08005C82:  E7F5         B          .L1                      ; 0x08005C70
+
.L2:
+  0x08005C84:  2000         MOVS       R0, #0
+  0x08005C86:  BDF0         POP        {R4-R7, PC}
+
.L3:
+  0x08005C88:  5C8E         LDRB       R6, [R1, R2]
+  0x08005C8A:  5C87         LDRB       R7, [R0, R2]
+
.L4:
+  0x08005C8C:  1BB8         SUBS       R0, R7, R6
+  0x08005C8E:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.strlen from strops.o (strops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
strlen:
+  0x08005C90:  2100         MOVS       R1, #0
+
.L1:
+  0x08005C92:  5C42         LDRB       R2, [R0, R1]
+  0x08005C94:  1C49         ADDS       R1, R1, #1
+  0x08005C96:  2A00         CMP        R2, #0
+  0x08005C98:  D1FB         BNE        .L1                      ; 0x08005C92
+  0x08005C9A:  1E48         SUBS       R0, R1, #1
+  0x08005C9C:  4770         BX         LR
+
+

Section .text.libc.memcpy from strasmops_arm.o (strops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
memcpy:
+__aeabi_memcpy:
+__aeabi_memcpy4:
+__aeabi_memcpy8:
+  0x08005C9E:  2A00         CMP        R2, #0
+  0x08005CA0:  D003         BEQ        .L2                      ; 0x08005CAA
+
.L1:
+  0x08005CA2:  1E52         SUBS       R2, R2, #1
+  0x08005CA4:  5C8B         LDRB       R3, [R1, R2]
+  0x08005CA6:  5483         STRB       R3, [R0, R2]
+  0x08005CA8:  D1FB         BNE        .L1                      ; 0x08005CA2
+
.L2:
+  0x08005CAA:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_mbtowc from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__SEGGER_RTL_ascii_mbtowc:
+  0x08005CAC:  B510         PUSH       {R4, LR}
+  0x08005CAE:  4604         MOV        R4, R0
+  0x08005CB0:  2000         MOVS       R0, #0
+  0x08005CB2:  2900         CMP        R1, #0
+  0x08005CB4:  D010         BEQ        .L3                      ; 0x08005CD8
+  0x08005CB6:  2A00         CMP        R2, #0
+  0x08005CB8:  D00E         BEQ        .L3                      ; 0x08005CD8
+  0x08005CBA:  7809         LDRB       R1, [R1]
+  0x08005CBC:  B248         SXTB       R0, R1
+  0x08005CBE:  2800         CMP        R0, #0
+  0x08005CC0:  D408         BMI        .L2                      ; 0x08005CD4
+  0x08005CC2:  2C00         CMP        R4, #0
+  0x08005CC4:  D000         BEQ        .L1                      ; 0x08005CC8
+  0x08005CC6:  6021         STR        R1, [R4]
+
.L1:
+  0x08005CC8:  2100         MOVS       R1, #0
+  0x08005CCA:  6019         STR        R1, [R3]
+  0x08005CCC:  6059         STR        R1, [R3, #4]
+  0x08005CCE:  1E41         SUBS       R1, R0, #1
+  0x08005CD0:  4188         SBCS       R0, R1
+  0x08005CD2:  BD10         POP        {R4, PC}
+
.L2:
+  0x08005CD4:  2001         MOVS       R0, #1
+  0x08005CD6:  43C0         MVNS       R0, R0
+
.L3:
+  0x08005CD8:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_ascii_tolower from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
__SEGGER_RTL_ascii_tolower:
+  0x08005CDA:  4601         MOV        R1, R0
+  0x08005CDC:  3941         SUBS       R1, #65
+  0x08005CDE:  291A         CMP        R1, #26
+  0x08005CE0:  D201         BCS        .L1                      ; 0x08005CE6
+  0x08005CE2:  2120         MOVS       R1, #32
+  0x08005CE4:  4308         ORRS       R0, R1
+
.L1:
+  0x08005CE6:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_towlower from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
__SEGGER_RTL_ascii_towlower:
+  0x08005CE8:  4601         MOV        R1, R0
+  0x08005CEA:  3941         SUBS       R1, #65
+  0x08005CEC:  291A         CMP        R1, #26
+  0x08005CEE:  D201         BCS        .L1                      ; 0x08005CF4
+  0x08005CF0:  2120         MOVS       R1, #32
+  0x08005CF2:  4308         ORRS       R0, R1
+
.L1:
+  0x08005CF4:  4770         BX         LR
+
+

Section .text.ADC_DMAConvCplt from PowerPro_lto.o, size=100, align=2

+
+
ADC_DMAConvCplt:
+  0x08005CF6:  B580         PUSH       {R7, LR}
+  0x08005CF8:  6A81         LDR        R1, [R0, #40]
+  0x08005CFA:  6D8A         LDR        R2, [R1, #88]
+  0x08005CFC:  2350         MOVS       R3, #80
+  0x08005CFE:  421A         TST        R2, R3
+  0x08005D00:  6D8A         LDR        R2, [R1, #88]
+  0x08005D02:  D005         BEQ        .L1                      ; 0x08005D10
+  0x08005D04:  06D2         LSLS       R2, R2, #27
+  0x08005D06:  D427         BMI        .L3                      ; 0x08005D58
+  0x08005D08:  6D09         LDR        R1, [R1, #80]
+  0x08005D0A:  6B49         LDR        R1, [R1, #52]
+  0x08005D0C:  4788         BLX        R1
+  0x08005D0E:  BD80         POP        {R7, PC}
+
.L1:
+  0x08005D10:  2001         MOVS       R0, #1
+  0x08005D12:  0243         LSLS       R3, R0, #9
+  0x08005D14:  431A         ORRS       R2, R3
+  0x08005D16:  658A         STR        R2, [R1, #88]
+  0x08005D18:  680A         LDR        R2, [R1]
+  0x08005D1A:  68D3         LDR        R3, [R2, #12]
+  0x08005D1C:  051B         LSLS       R3, R3, #20
+  0x08005D1E:  0F9B         LSRS       R3, R3, #30
+  0x08005D20:  D11A         BNE        .L3                      ; 0x08005D58
+  0x08005D22:  7E8B         LDRB       R3, [R1, #26]
+  0x08005D24:  2B00         CMP        R3, #0
+  0x08005D26:  D117         BNE        .L3                      ; 0x08005D58
+  0x08005D28:  6813         LDR        R3, [R2]
+  0x08005D2A:  071B         LSLS       R3, R3, #28
+  0x08005D2C:  D514         BPL        .L3                      ; 0x08005D58
+  0x08005D2E:  6893         LDR        R3, [R2, #8]
+  0x08005D30:  075B         LSLS       R3, R3, #29
+  0x08005D32:  D40A         BMI        .L2                      ; 0x08005D4A
+  0x08005D34:  6850         LDR        R0, [R2, #4]
+  0x08005D36:  230C         MOVS       R3, #12
+  0x08005D38:  4398         BICS       R0, R3
+  0x08005D3A:  6050         STR        R0, [R2, #4]
+  0x08005D3C:  20FF         MOVS       R0, #255
+  0x08005D3E:  3002         ADDS       R0, #2
+  0x08005D40:  6D8A         LDR        R2, [R1, #88]
+  0x08005D42:  4382         BICS       R2, R0
+  0x08005D44:  1C50         ADDS       R0, R2, #1
+  0x08005D46:  6588         STR        R0, [R1, #88]
+  0x08005D48:  BD80         POP        {R7, PC}
+
.L2:
+  0x08005D4A:  6D8A         LDR        R2, [R1, #88]
+  0x08005D4C:  2320         MOVS       R3, #32
+  0x08005D4E:  4313         ORRS       R3, R2
+  0x08005D50:  658B         STR        R3, [R1, #88]
+  0x08005D52:  6DCA         LDR        R2, [R1, #92]
+  0x08005D54:  4302         ORRS       R2, R0
+  0x08005D56:  65CA         STR        R2, [R1, #92]
+
.L3:
+  0x08005D58:  BD80         POP        {R7, PC}
+
+

Section .text.ADC_DMAError from PowerPro_lto.o, size=20, align=2

+
+
ADC_DMAError:
+  0x08005D5A:  6A80         LDR        R0, [R0, #40]
+  0x08005D5C:  6D81         LDR        R1, [R0, #88]
+  0x08005D5E:  2240         MOVS       R2, #64
+  0x08005D60:  430A         ORRS       R2, R1
+  0x08005D62:  6582         STR        R2, [R0, #88]
+  0x08005D64:  6DC1         LDR        R1, [R0, #92]
+  0x08005D66:  2204         MOVS       R2, #4
+  0x08005D68:  430A         ORRS       R2, R1
+  0x08005D6A:  65C2         STR        R2, [R0, #92]
+  0x08005D6C:  4770         BX         LR
+
+

Section .text.HAL_NVIC_SystemReset from PowerPro_lto.o, size=4, align=2

+
+
HAL_NVIC_SystemReset:
+  0x08005D6E:  F7FA FDDB    BL         __NVIC_SystemReset       ; 0x08000928
+
+

Section .text.UART_DMAReceiveCplt from PowerPro_lto.o, size=168, align=2

+
+
UART_DMAReceiveCplt:
+  0x08005D72:  B5F0         PUSH       {R4-R7, LR}
+  0x08005D74:  B082         SUB        SP, SP, #8
+  0x08005D76:  6A82         LDR        R2, [R0, #40]
+  0x08005D78:  4611         MOV        R1, R2
+  0x08005D7A:  315C         ADDS       R1, #92
+  0x08005D7C:  6803         LDR        R3, [R0]
+  0x08005D7E:  681B         LDR        R3, [R3]
+  0x08005D80:  069B         LSLS       R3, R3, #26
+  0x08005D82:  D43A         BMI        .L1                      ; 0x08005DFA
+  0x08005D84:  4614         MOV        R4, R2
+  0x08005D86:  348C         ADDS       R4, #140
+  0x08005D88:  2300         MOVS       R3, #0
+  0x08005D8A:  804B         STRH       R3, [R1, #2]
+  0x08005D8C:  F3EF 8310    MRS        R3, PRIMASK
+  0x08005D90:  9300         STR        R3, [SP, #0]
+  0x08005D92:  2301         MOVS       R3, #1
+  0x08005D94:  F383 8810    MSR        PRIMASK, R3
+  0x08005D98:  9001         STR        R0, [SP, #4]
+  0x08005D9A:  021E         LSLS       R6, R3, #8
+  0x08005D9C:  6817         LDR        R7, [R2]
+  0x08005D9E:  683D         LDR        R5, [R7]
+  0x08005DA0:  43B5         BICS       R5, R6
+  0x08005DA2:  603D         STR        R5, [R7]
+  0x08005DA4:  9800         LDR        R0, [SP, #0]
+  0x08005DA6:  F380 8810    MSR        PRIMASK, R0
+  0x08005DAA:  F3EF 8010    MRS        R0, PRIMASK
+  0x08005DAE:  F383 8810    MSR        PRIMASK, R3
+  0x08005DB2:  6815         LDR        R5, [R2]
+  0x08005DB4:  68AE         LDR        R6, [R5, #8]
+  0x08005DB6:  439E         BICS       R6, R3
+  0x08005DB8:  60AE         STR        R6, [R5, #8]
+  0x08005DBA:  F380 8810    MSR        PRIMASK, R0
+  0x08005DBE:  F3EF 8010    MRS        R0, PRIMASK
+  0x08005DC2:  9000         STR        R0, [SP, #0]
+  0x08005DC4:  F383 8810    MSR        PRIMASK, R3
+  0x08005DC8:  6815         LDR        R5, [R2]
+  0x08005DCA:  68AE         LDR        R6, [R5, #8]
+  0x08005DCC:  2740         MOVS       R7, #64
+  0x08005DCE:  43BE         BICS       R6, R7
+  0x08005DD0:  60AE         STR        R6, [R5, #8]
+  0x08005DD2:  9801         LDR        R0, [SP, #4]
+  0x08005DD4:  9D00         LDR        R5, [SP, #0]
+  0x08005DD6:  F385 8810    MSR        PRIMASK, R5
+  0x08005DDA:  2520         MOVS       R5, #32
+  0x08005DDC:  6025         STR        R5, [R4]
+  0x08005DDE:  6ED4         LDR        R4, [R2, #108]
+  0x08005DE0:  2C01         CMP        R4, #1
+  0x08005DE2:  D10A         BNE        .L1                      ; 0x08005DFA
+  0x08005DE4:  F3EF 8610    MRS        R6, PRIMASK
+  0x08005DE8:  F383 8810    MSR        PRIMASK, R3
+  0x08005DEC:  6813         LDR        R3, [R2]
+  0x08005DEE:  681C         LDR        R4, [R3]
+  0x08005DF0:  2510         MOVS       R5, #16
+  0x08005DF2:  43AC         BICS       R4, R5
+  0x08005DF4:  601C         STR        R4, [R3]
+  0x08005DF6:  F386 8810    MSR        PRIMASK, R6
+
.L1:
+  0x08005DFA:  2300         MOVS       R3, #0
+  0x08005DFC:  6713         STR        R3, [R2, #112]
+  0x08005DFE:  6ED2         LDR        R2, [R2, #108]
+  0x08005E00:  2A01         CMP        R2, #1
+  0x08005E02:  D108         BNE        .L3                      ; 0x08005E16
+  0x08005E04:  804B         STRH       R3, [R1, #2]
+  0x08005E06:  880A         LDRH       R2, [R1]
+  0x08005E08:  6800         LDR        R0, [R0]
+  0x08005E0A:  6840         LDR        R0, [R0, #4]
+  0x08005E0C:  B283         UXTH       R3, R0
+  0x08005E0E:  4293         CMP        R3, R2
+  0x08005E10:  D200         BCS        .L2                      ; 0x08005E14
+  0x08005E12:  8048         STRH       R0, [R1, #2]
+
.L2:
+  0x08005E14:  8848         LDRH       R0, [R1, #2]
+
.L3:
+  0x08005E16:  B002         ADD        SP, SP, #8
+  0x08005E18:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.UART_DMARxHalfCplt from PowerPro_lto.o, size=36, align=2

+
+
UART_DMARxHalfCplt:
+  0x08005E1A:  6A81         LDR        R1, [R0, #40]
+  0x08005E1C:  2201         MOVS       R2, #1
+  0x08005E1E:  670A         STR        R2, [R1, #112]
+  0x08005E20:  6ECA         LDR        R2, [R1, #108]
+  0x08005E22:  2A01         CMP        R2, #1
+  0x08005E24:  D10A         BNE        .L2                      ; 0x08005E3C
+  0x08005E26:  315C         ADDS       R1, #92
+  0x08005E28:  880A         LDRH       R2, [R1]
+  0x08005E2A:  0853         LSRS       R3, R2, #1
+  0x08005E2C:  804B         STRH       R3, [R1, #2]
+  0x08005E2E:  6800         LDR        R0, [R0]
+  0x08005E30:  6840         LDR        R0, [R0, #4]
+  0x08005E32:  B283         UXTH       R3, R0
+  0x08005E34:  4293         CMP        R3, R2
+  0x08005E36:  D800         BHI        .L1                      ; 0x08005E3A
+  0x08005E38:  8048         STRH       R0, [R1, #2]
+
.L1:
+  0x08005E3A:  8848         LDRH       R0, [R1, #2]
+
.L2:
+  0x08005E3C:  4770         BX         LR
+
+

Section .text.UART_DMAAbortOnError from PowerPro_lto.o, size=16, align=2

+
+
UART_DMAAbortOnError:
+  0x08005E3E:  B580         PUSH       {R7, LR}
+  0x08005E40:  6A80         LDR        R0, [R0, #40]
+  0x08005E42:  215E         MOVS       R1, #94
+  0x08005E44:  2200         MOVS       R2, #0
+  0x08005E46:  5242         STRH       R2, [R0, R1]
+  0x08005E48:  F7FE FB64    BL         HAL_UART_ErrorCallback   ; 0x08004514
+  0x08005E4C:  BD80         POP        {R7, PC}
+
+

Section .text.Error_Handler from PowerPro_lto.o, size=4, align=2

+
+
Error_Handler:
+  0x08005E4E:  B672         CPSID      i
+
.L1:
+  0x08005E50:  E7FE         B          .L1                      ; 0x08005E50
+
+

Section .rodata.UARTPrescTable from PowerPro_lto.o, size=24, align=2

+
+
UARTPrescTable:
+  0x08005E52:  01           DC.B       0x01                     ; '\x01'
+  0x08005E53:  00           DC.B       0x00                     ; '\0'
+  0x08005E54:  02           DC.B       0x02                     ; '\x02'
+  0x08005E55:  00           DC.B       0x00                     ; '\0'
+  0x08005E56:  04           DC.B       0x04                     ; '\x04'
+  0x08005E57:  00           DC.B       0x00                     ; '\0'
+  0x08005E58:  06           DC.B       0x06                     ; '\x06'
+  0x08005E59:  00           DC.B       0x00                     ; '\0'
+  0x08005E5A:  08           DC.B       0x08                     ; '\b'
+  0x08005E5B:  00           DC.B       0x00                     ; '\0'
+  0x08005E5C:  0A           DC.B       0x0A                     ; '\n'
+  0x08005E5D:  00           DC.B       0x00                     ; '\0'
+  0x08005E5E:  0C           DC.B       0x0C                     ; '\x0C'
+  0x08005E5F:  00           DC.B       0x00                     ; '\0'
+  0x08005E60:  10           DC.B       0x10                     ; '\x10'
+  0x08005E61:  00           DC.B       0x00                     ; '\0'
+  0x08005E62:  20           DC.B       0x20                     ; ' '
+  0x08005E63:  00           DC.B       0x00                     ; '\0'
+  0x08005E64:  40           DC.B       0x40                     ; '@'
+  0x08005E65:  00           DC.B       0x00                     ; '\0'
+  0x08005E66:  80           DC.B       0x80                     ; '\x80'
+  0x08005E67:  00           DC.B       0x00                     ; '\0'
+  0x08005E68:  00           DC.B       0x00                     ; '\0'
+  0x08005E69:  01           DC.B       0x01                     ; '\x01'
+
+

Section .init.Reset_Handler from STM32C0xx_Startup.o, size=8, align=2

+
+
reset_handler:
+Reset_Handler:
+  0x08005E6A:  F7FA FBC3    BL         SystemInit               ; 0x080005F4
+  0x08005E6E:  F7FF F961    BL         _start                   ; 0x08005134
+
+

Section .text.libc.__aeabi_ddiv from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=196, align=2

+
+
__aeabi_ddiv:
+  0x08005E72:  B4F0         PUSH       {R4-R7}
+  0x08005E74:  2501         MOVS       R5, #1
+  0x08005E76:  07ED         LSLS       R5, R5, #31
+  0x08005E78:  000C         MOVS       R4, R1
+  0x08005E7A:  405C         EORS       R4, R3
+  0x08005E7C:  402C         ANDS       R4, R5
+  0x08005E7E:  46A4         MOV        R12, R4
+  0x08005E80:  0AAE         LSRS       R6, R5, #10
+  0x08005E82:  184C         ADDS       R4, R1, R1
+  0x08005E84:  18DF         ADDS       R7, R3, R3
+  0x08005E86:  42F4         CMN        R4, R6
+  0x08005E88:  D23D         BCS        .L8                      ; 0x08005F06
+  0x08005E8A:  42F7         CMN        R7, R6
+  0x08005E8C:  D245         BCS        .L10                     ; 0x08005F1A
+  0x08005E8E:  0D64         LSRS       R4, R4, #21
+  0x08005E90:  D04C         BEQ        .L12                     ; 0x08005F2C
+  0x08005E92:  0D7F         LSRS       R7, R7, #21
+  0x08005E94:  D03C         BEQ        .L9                      ; 0x08005F10
+  0x08005E96:  1BE4         SUBS       R4, R4, R7
+  0x08005E98:  02C9         LSLS       R1, R1, #11
+  0x08005E9A:  4329         ORRS       R1, R5
+  0x08005E9C:  0ACF         LSRS       R7, R1, #11
+  0x08005E9E:  02DB         LSLS       R3, R3, #11
+  0x08005EA0:  432B         ORRS       R3, R5
+  0x08005EA2:  0ADB         LSRS       R3, R3, #11
+  0x08005EA4:  0006         MOVS       R6, R0
+  0x08005EA6:  1AB6         SUBS       R6, R6, R2
+  0x08005EA8:  419F         SBCS       R7, R3
+  0x08005EAA:  D204         BCS        .L1                      ; 0x08005EB6
+  0x08005EAC:  1E64         SUBS       R4, R4, #1
+  0x08005EAE:  19B6         ADDS       R6, R6, R6
+  0x08005EB0:  417F         ADCS       R7, R7
+  0x08005EB2:  18B6         ADDS       R6, R6, R2
+  0x08005EB4:  415F         ADCS       R7, R3
+
.L1:
+  0x08005EB6:  1268         ASRS       R0, R5, #9
+  0x08005EB8:  0D80         LSRS       R0, R0, #22
+  0x08005EBA:  1824         ADDS       R4, R4, R0
+  0x08005EBC:  DD38         BLE        .L13                     ; 0x08005F30
+  0x08005EBE:  1800         ADDS       R0, R0, R0
+  0x08005EC0:  4284         CMP        R4, R0
+  0x08005EC2:  D825         BHI        .L9                      ; 0x08005F10
+  0x08005EC4:  0CE8         LSRS       R0, R5, #19
+  0x08005EC6:  2100         MOVS       R1, #0
+
.L2:
+  0x08005EC8:  19B6         ADDS       R6, R6, R6
+  0x08005ECA:  417F         ADCS       R7, R7
+  0x08005ECC:  1AB6         SUBS       R6, R6, R2
+  0x08005ECE:  419F         SBCS       R7, R3
+  0x08005ED0:  D303         BCC        .L3                      ; 0x08005EDA
+  0x08005ED2:  4140         ADCS       R0, R0
+  0x08005ED4:  4149         ADCS       R1, R1
+  0x08005ED6:  D3F7         BCC        .L2                      ; 0x08005EC8
+  0x08005ED8:  E004         B          .L4                      ; 0x08005EE4
+
.L3:
+  0x08005EDA:  18B6         ADDS       R6, R6, R2
+  0x08005EDC:  415F         ADCS       R7, R3
+  0x08005EDE:  1800         ADDS       R0, R0, R0
+  0x08005EE0:  4149         ADCS       R1, R1
+  0x08005EE2:  D3F1         BCC        .L2                      ; 0x08005EC8
+
.L4:
+  0x08005EE4:  0524         LSLS       R4, R4, #20
+  0x08005EE6:  19B6         ADDS       R6, R6, R6
+  0x08005EE8:  417F         ADCS       R7, R7
+  0x08005EEA:  1AB6         SUBS       R6, R6, R2
+  0x08005EEC:  419F         SBCS       R7, R3
+  0x08005EEE:  D305         BCC        .L5                      ; 0x08005EFC
+  0x08005EF0:  4337         ORRS       R7, R6
+  0x08005EF2:  07C2         LSLS       R2, R0, #31
+  0x08005EF4:  4317         ORRS       R7, R2
+  0x08005EF6:  2200         MOVS       R2, #0
+  0x08005EF8:  2F01         CMP        R7, #1
+  0x08005EFA:  4150         ADCS       R0, R2
+
.L5:
+  0x08005EFC:  4161         ADCS       R1, R4
+
.L6:
+  0x08005EFE:  4662         MOV        R2, R12
+  0x08005F00:  4311         ORRS       R1, R2
+
.L7:
+  0x08005F02:  BCF0         POP        {R4-R7}
+  0x08005F04:  4770         BX         LR
+
.L8:
+  0x08005F06:  D10C         BNE        .L11                     ; 0x08005F22
+  0x08005F08:  2800         CMP        R0, #0
+  0x08005F0A:  D10A         BNE        .L11                     ; 0x08005F22
+  0x08005F0C:  42F7         CMN        R7, R6
+  0x08005F0E:  D208         BCS        .L11                     ; 0x08005F22
+
.L9:
+  0x08005F10:  2000         MOVS       R0, #0
+  0x08005F12:  43C1         MVNS       R1, R0
+  0x08005F14:  0D49         LSRS       R1, R1, #21
+  0x08005F16:  0509         LSLS       R1, R1, #20
+  0x08005F18:  E7F1         B          .L6                      ; 0x08005EFE
+
.L10:
+  0x08005F1A:  2A00         CMP        R2, #0
+  0x08005F1C:  D101         BNE        .L11                     ; 0x08005F22
+  0x08005F1E:  42F7         CMN        R7, R6
+  0x08005F20:  D006         BEQ        .L13                     ; 0x08005F30
+
.L11:
+  0x08005F22:  2000         MOVS       R0, #0
+  0x08005F24:  43C1         MVNS       R1, R0
+  0x08005F26:  0D09         LSRS       R1, R1, #20
+  0x08005F28:  04C9         LSLS       R1, R1, #19
+  0x08005F2A:  E7EA         B          .L7                      ; 0x08005F02
+
.L12:
+  0x08005F2C:  0D7F         LSRS       R7, R7, #21
+  0x08005F2E:  D0F8         BEQ        .L11                     ; 0x08005F22
+
.L13:
+  0x08005F30:  2000         MOVS       R0, #0
+  0x08005F32:  4661         MOV        R1, R12
+  0x08005F34:  E7E5         B          .L7                      ; 0x08005F02
+
+

Section .text.libc.__aeabi_d2iz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=52, align=2

+
+
__aeabi_d2iz:
+  0x08005F36:  46F4         MOV        R12, LR
+  0x08005F38:  184A         ADDS       R2, R1, R1
+  0x08005F3A:  D205         BCS        .L2                      ; 0x08005F48
+  0x08005F3C:  F7FF FDBE    BL         0x08005ABC               ; 0x08005ABD = .text.libc.__aeabi_d2uiz+5
+  0x08005F40:  D501         BPL        .L1                      ; 0x08005F46
+  0x08005F42:  17C0         ASRS       R0, R0, #31
+  0x08005F44:  0840         LSRS       R0, R0, #1
+
.L1:
+  0x08005F46:  4760         BX         R12
+
.L2:
+  0x08005F48:  2301         MOVS       R3, #1
+  0x08005F4A:  055B         LSLS       R3, R3, #21
+  0x08005F4C:  42D3         CMN        R3, R2
+  0x08005F4E:  D206         BCS        .L5                      ; 0x08005F5E
+
.L3:
+  0x08005F50:  F7FF FDB4    BL         0x08005ABC               ; 0x08005ABD = .text.libc.__aeabi_d2uiz+5
+  0x08005F54:  D501         BPL        .L4                      ; 0x08005F5A
+  0x08005F56:  2001         MOVS       R0, #1
+  0x08005F58:  07C0         LSLS       R0, R0, #31
+
.L4:
+  0x08005F5A:  4240         RSBS       R0, R0, #0
+  0x08005F5C:  4760         BX         R12
+
.L5:
+  0x08005F5E:  D101         BNE        .L6                      ; 0x08005F64
+  0x08005F60:  4200         TST        R0, R0
+  0x08005F62:  D0F5         BEQ        .L3                      ; 0x08005F50
+
.L6:
+  0x08005F64:  17D0         ASRS       R0, R2, #31
+  0x08005F66:  0840         LSRS       R0, R0, #1
+  0x08005F68:  4770         BX         LR
+
+

Section .text.libc.__aeabi_f2uiz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=36, align=2

+
+
__aeabi_f2uiz:
+  0x08005F6A:  0041         LSLS       R1, R0, #1
+  0x08005F6C:  D20D         BCS        .L2                      ; 0x08005F8A
+  0x08005F6E:  0E09         LSRS       R1, R1, #24
+  0x08005F70:  397F         SUBS       R1, #127
+  0x08005F72:  D40A         BMI        .L2                      ; 0x08005F8A
+  0x08005F74:  4249         RSBS       R1, R1, #0
+  0x08005F76:  311F         ADDS       R1, #31
+  0x08005F78:  D405         BMI        .L1                      ; 0x08005F86
+  0x08005F7A:  0200         LSLS       R0, R0, #8
+  0x08005F7C:  2201         MOVS       R2, #1
+  0x08005F7E:  07D2         LSLS       R2, R2, #31
+  0x08005F80:  4310         ORRS       R0, R2
+  0x08005F82:  40C8         LSRS       R0, R1
+  0x08005F84:  4770         BX         LR
+
.L1:
+  0x08005F86:  17C8         ASRS       R0, R1, #31
+  0x08005F88:  4770         BX         LR
+
.L2:
+  0x08005F8A:  2000         MOVS       R0, #0
+  0x08005F8C:  4770         BX         LR
+
+

Section .text.libc.__aeabi_ui2d from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=28, align=2

+
+
__aeabi_ui2d:
+  0x08005F8E:  2242         MOVS       R2, #66
+  0x08005F90:  0112         LSLS       R2, R2, #4
+  0x08005F92:  1ED2         SUBS       R2, R2, #3
+  0x08005F94:  0001         MOVS       R1, R0
+  0x08005F96:  D007         BEQ        .L3                      ; 0x08005FA8
+  0x08005F98:  D402         BMI        .L2                      ; 0x08005FA0
+
.L1:
+  0x08005F9A:  1E52         SUBS       R2, R2, #1
+  0x08005F9C:  1800         ADDS       R0, R0, R0
+  0x08005F9E:  D5FC         BPL        .L1                      ; 0x08005F9A
+
.L2:
+  0x08005FA0:  0512         LSLS       R2, R2, #20
+  0x08005FA2:  0AC3         LSRS       R3, R0, #11
+  0x08005FA4:  0540         LSLS       R0, R0, #21
+  0x08005FA6:  1899         ADDS       R1, R3, R2
+
.L3:
+  0x08005FA8:  4770         BX         LR
+
+

Section .text.libc.__aeabi_idiv from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=64, align=2

+
+
__aeabi_idiv:
+  0x08005FAA:  17CA         ASRS       R2, R1, #31
+  0x08005FAC:  4051         EORS       R1, R2
+  0x08005FAE:  1A8B         SUBS       R3, R1, R2
+  0x08005FB0:  D017         BEQ        .L6                      ; 0x08005FE2
+  0x08005FB2:  17C1         ASRS       R1, R0, #31
+  0x08005FB4:  404A         EORS       R2, R1
+  0x08005FB6:  4694         MOV        R12, R2
+  0x08005FB8:  4048         EORS       R0, R1
+  0x08005FBA:  1A41         SUBS       R1, R0, R1
+  0x08005FBC:  0848         LSRS       R0, R1, #1
+  0x08005FBE:  001A         MOVS       R2, R3
+  0x08005FC0:  E000         B          .L2                      ; 0x08005FC4
+
.L1:
+  0x08005FC2:  0052         LSLS       R2, R2, #1
+
.L2:
+  0x08005FC4:  4282         CMP        R2, R0
+  0x08005FC6:  D9FC         BLS        .L1                      ; 0x08005FC2
+  0x08005FC8:  2000         MOVS       R0, #0
+  0x08005FCA:  E000         B          .L4                      ; 0x08005FCE
+
.L3:
+  0x08005FCC:  0852         LSRS       R2, R2, #1
+
.L4:
+  0x08005FCE:  4291         CMP        R1, R2
+  0x08005FD0:  D300         BCC        .L5                      ; 0x08005FD4
+  0x08005FD2:  1A89         SUBS       R1, R1, R2
+
.L5:
+  0x08005FD4:  4140         ADCS       R0, R0
+  0x08005FD6:  429A         CMP        R2, R3
+  0x08005FD8:  D1F8         BNE        .L3                      ; 0x08005FCC
+  0x08005FDA:  4662         MOV        R2, R12
+  0x08005FDC:  4050         EORS       R0, R2
+  0x08005FDE:  1A80         SUBS       R0, R0, R2
+  0x08005FE0:  4770         BX         LR
+
.L6:
+  0x08005FE2:  B510         PUSH       {R4, LR}
+  0x08005FE4:  F7FF FDA5    BL         __aeabi_idiv0            ; 0x08005B32
+  0x08005FE8:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__aeabi_uidiv from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=56, align=2

+
+
__aeabi_uidiv:
+  0x08005FEA:  000A         MOVS       R2, R1
+  0x08005FEC:  D015         BEQ        .L8                      ; 0x0800601A
+  0x08005FEE:  0003         MOVS       R3, R0
+  0x08005FF0:  0840         LSRS       R0, R0, #1
+  0x08005FF2:  E000         B          .L2                      ; 0x08005FF6
+
.L1:
+  0x08005FF4:  0052         LSLS       R2, R2, #1
+
.L2:
+  0x08005FF6:  4282         CMP        R2, R0
+  0x08005FF8:  D9FC         BLS        .L1                      ; 0x08005FF4
+  0x08005FFA:  2000         MOVS       R0, #0
+  0x08005FFC:  E000         B          .L4                      ; 0x08006000
+
.L3:
+  0x08005FFE:  0852         LSRS       R2, R2, #1
+
.L4:
+  0x08006000:  1A9B         SUBS       R3, R3, R2
+  0x08006002:  D306         BCC        .L7                      ; 0x08006012
+
.L5:
+  0x08006004:  4140         ADCS       R0, R0
+  0x08006006:  428A         CMP        R2, R1
+  0x08006008:  D1F9         BNE        .L3                      ; 0x08005FFE
+  0x0800600A:  4770         BX         LR
+
.L6:
+  0x0800600C:  0852         LSRS       R2, R2, #1
+  0x0800600E:  189B         ADDS       R3, R3, R2
+  0x08006010:  D2F8         BCS        .L5                      ; 0x08006004
+
.L7:
+  0x08006012:  1800         ADDS       R0, R0, R0
+  0x08006014:  428A         CMP        R2, R1
+  0x08006016:  D1F9         BNE        .L6                      ; 0x0800600C
+  0x08006018:  4770         BX         LR
+
.L8:
+  0x0800601A:  B510         PUSH       {R4, LR}
+  0x0800601C:  F7FF FD89    BL         __aeabi_idiv0            ; 0x08005B32
+  0x08006020:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__aeabi_uldivmod from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=136, align=2

+
+
__aeabi_uldivmod:
+  0x08006022:  B470         PUSH       {R4-R6}
+  0x08006024:  2400         MOVS       R4, #0
+  0x08006026:  2501         MOVS       R5, #1
+  0x08006028:  07ED         LSLS       R5, R5, #31
+  0x0800602A:  2B00         CMP        R3, #0
+  0x0800602C:  D107         BNE        .L1                      ; 0x0800603E
+  0x0800602E:  2900         CMP        R1, #0
+  0x08006030:  D005         BEQ        .L1                      ; 0x0800603E
+  0x08006032:  4283         CMP        R3, R0
+  0x08006034:  D203         BCS        .L1                      ; 0x0800603E
+  0x08006036:  0013         MOVS       R3, R2
+  0x08006038:  2200         MOVS       R2, #0
+  0x0800603A:  002C         MOVS       R4, R5
+  0x0800603C:  2500         MOVS       R5, #0
+
.L1:
+  0x0800603E:  2600         MOVS       R6, #0
+
.L2:
+  0x08006040:  19A4         ADDS       R4, R4, R6
+  0x08006042:  4299         CMP        R1, R3
+  0x08006044:  D100         BNE        .L3                      ; 0x08006048
+  0x08006046:  4290         CMP        R0, R2
+
.L3:
+  0x08006048:  D912         BLS        .L6                      ; 0x08006070
+  0x0800604A:  1892         ADDS       R2, R2, R2
+  0x0800604C:  415B         ADCS       R3, R3
+  0x0800604E:  D203         BCS        .L4                      ; 0x08006058
+  0x08006050:  07EE         LSLS       R6, R5, #31
+  0x08006052:  086D         LSRS       R5, R5, #1
+  0x08006054:  0864         LSRS       R4, R4, #1
+  0x08006056:  E7F3         B          .L2                      ; 0x08006040
+
.L4:
+  0x08006058:  07DE         LSLS       R6, R3, #31
+  0x0800605A:  085B         LSRS       R3, R3, #1
+  0x0800605C:  0852         LSRS       R2, R2, #1
+  0x0800605E:  1992         ADDS       R2, R2, R6
+  0x08006060:  2601         MOVS       R6, #1
+  0x08006062:  07F6         LSLS       R6, R6, #31
+  0x08006064:  199B         ADDS       R3, R3, R6
+  0x08006066:  E003         B          .L6                      ; 0x08006070
+
.L5:
+  0x08006068:  07DE         LSLS       R6, R3, #31
+  0x0800606A:  085B         LSRS       R3, R3, #1
+  0x0800606C:  0852         LSRS       R2, R2, #1
+  0x0800606E:  1992         ADDS       R2, R2, R6
+
.L6:
+  0x08006070:  1A80         SUBS       R0, R0, R2
+  0x08006072:  4199         SBCS       R1, R3
+  0x08006074:  D303         BCC        .L7                      ; 0x0800607E
+  0x08006076:  4164         ADCS       R4, R4
+  0x08006078:  416D         ADCS       R5, R5
+  0x0800607A:  D3F5         BCC        .L5                      ; 0x08006068
+  0x0800607C:  E00F         B          .L9                      ; 0x0800609E
+
.L7:
+  0x0800607E:  1924         ADDS       R4, R4, R4
+  0x08006080:  416D         ADCS       R5, R5
+  0x08006082:  D20A         BCS        .L8                      ; 0x0800609A
+  0x08006084:  07DE         LSLS       R6, R3, #31
+  0x08006086:  085B         LSRS       R3, R3, #1
+  0x08006088:  0852         LSRS       R2, R2, #1
+  0x0800608A:  1992         ADDS       R2, R2, R6
+  0x0800608C:  1880         ADDS       R0, R0, R2
+  0x0800608E:  4159         ADCS       R1, R3
+  0x08006090:  D3F5         BCC        .L7                      ; 0x0800607E
+  0x08006092:  4164         ADCS       R4, R4
+  0x08006094:  416D         ADCS       R5, R5
+  0x08006096:  D3E7         BCC        .L5                      ; 0x08006068
+  0x08006098:  E001         B          .L9                      ; 0x0800609E
+
.L8:
+  0x0800609A:  1880         ADDS       R0, R0, R2
+  0x0800609C:  4159         ADCS       R1, R3
+
.L9:
+  0x0800609E:  0002         MOVS       R2, R0
+  0x080060A0:  000B         MOVS       R3, R1
+  0x080060A2:  0020         MOVS       R0, R4
+  0x080060A4:  0029         MOVS       R1, R5
+  0x080060A6:  BC70         POP        {R4-R6}
+  0x080060A8:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_stream_write from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=2

+
+
__SEGGER_RTL_stream_write:
+  0x080060AA:  B510         PUSH       {R4, LR}
+  0x080060AC:  460C         MOV        R4, R1
+  0x080060AE:  6A43         LDR        R3, [R0, #36]
+  0x080060B0:  2101         MOVS       R1, #1
+  0x080060B2:  4620         MOV        R0, R4
+  0x080060B4:  F7FF FBC7    BL         fwrite                   ; 0x08005846
+  0x080060B8:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_X_file_bufsize from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=2

+
+
__SEGGER_RTL_X_file_bufsize:
+  0x080060BA:  2040         MOVS       R0, #64
+  0x080060BC:  4770         BX         LR
+
+

Section .text.libc._WriteBlocking from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=88, align=2

+
+
_WriteBlocking:
+  0x080060BE:  B5F0         PUSH       {R4-R7, LR}
+  0x080060C0:  B083         SUB        SP, SP, #12
+  0x080060C2:  4617         MOV        R7, R2
+  0x080060C4:  4606         MOV        R6, R0
+  0x080060C6:  68C5         LDR        R5, [R0, #12]
+  0x080060C8:  2000         MOVS       R0, #0
+
.L1:
+  0x080060CA:  9001         STR        R0, [SP, #4]
+  0x080060CC:  6933         LDR        R3, [R6, #16]
+  0x080060CE:  42AB         CMP        R3, R5
+  0x080060D0:  68B0         LDR        R0, [R6, #8]
+  0x080060D2:  D902         BLS        .L2                      ; 0x080060DA
+  0x080060D4:  43EA         MVNS       R2, R5
+  0x080060D6:  189C         ADDS       R4, R3, R2
+  0x080060D8:  E002         B          .L3                      ; 0x080060E0
+
.L2:
+  0x080060DA:  43EA         MVNS       R2, R5
+  0x080060DC:  189A         ADDS       R2, R3, R2
+  0x080060DE:  1814         ADDS       R4, R2, R0
+
.L3:
+  0x080060E0:  1B40         SUBS       R0, R0, R5
+  0x080060E2:  4284         CMP        R4, R0
+  0x080060E4:  D300         BCC        .L4                      ; 0x080060E8
+  0x080060E6:  4604         MOV        R4, R0
+
.L4:
+  0x080060E8:  42BC         CMP        R4, R7
+  0x080060EA:  D300         BCC        .L5                      ; 0x080060EE
+  0x080060EC:  463C         MOV        R4, R7
+
.L5:
+  0x080060EE:  6870         LDR        R0, [R6, #4]
+  0x080060F0:  1940         ADDS       R0, R0, R5
+  0x080060F2:  9102         STR        R1, [SP, #8]
+  0x080060F4:  4622         MOV        R2, R4
+  0x080060F6:  F7FF FDD2    BL         memcpy                   ; 0x08005C9E
+  0x080060FA:  1965         ADDS       R5, R4, R5
+  0x080060FC:  68B0         LDR        R0, [R6, #8]
+  0x080060FE:  4285         CMP        R5, R0
+  0x08006100:  D100         BNE        .L6                      ; 0x08006104
+  0x08006102:  2500         MOVS       R5, #0
+
.L6:
+  0x08006104:  9801         LDR        R0, [SP, #4]
+  0x08006106:  60F5         STR        R5, [R6, #12]
+  0x08006108:  9902         LDR        R1, [SP, #8]
+  0x0800610A:  1909         ADDS       R1, R1, R4
+  0x0800610C:  1820         ADDS       R0, R4, R0
+  0x0800610E:  1B3F         SUBS       R7, R7, R4
+  0x08006110:  D1DB         BNE        .L1                      ; 0x080060CA
+  0x08006112:  B003         ADD        SP, SP, #12
+  0x08006114:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_v6m_t_le_eabi_small.a), size=20, align=2

+
+
__aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x08006116:  2200         MOVS       R2, #0
+
__aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x08006118:  000B         MOVS       R3, R1
+  0x0800611A:  0011         MOVS       R1, R2
+  0x0800611C:  001A         MOVS       R2, R3
+
memset:
+  0x0800611E:  2A00         CMP        R2, #0
+  0x08006120:  D002         BEQ        .L2                      ; 0x08006128
+
.L1:
+  0x08006122:  1E52         SUBS       R2, R2, #1
+  0x08006124:  5481         STRB       R1, [R0, R2]
+  0x08006126:  D1FC         BNE        .L1                      ; 0x08006122
+
.L2:
+  0x08006128:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_wctomb from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=16, align=2

+
+
__SEGGER_RTL_ascii_wctomb:
+  0x0800612A:  4602         MOV        R2, R0
+  0x0800612C:  2001         MOVS       R0, #1
+  0x0800612E:  297F         CMP        R1, #127
+  0x08006130:  D901         BLS        .L1                      ; 0x08006136
+  0x08006132:  43C0         MVNS       R0, R0
+  0x08006134:  4770         BX         LR
+
.L1:
+  0x08006136:  7011         STRB       R1, [R2]
+  0x08006138:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_toupper from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=2

+
+
__SEGGER_RTL_ascii_toupper:
+  0x0800613A:  4601         MOV        R1, R0
+  0x0800613C:  3961         SUBS       R1, #97
+  0x0800613E:  291A         CMP        R1, #26
+  0x08006140:  D200         BCS        .L1                      ; 0x08006144
+  0x08006142:  3820         SUBS       R0, #32
+
.L1:
+  0x08006144:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_towupper from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=2

+
+
__SEGGER_RTL_ascii_towupper:
+  0x08006146:  4601         MOV        R1, R0
+  0x08006148:  3961         SUBS       R1, #97
+  0x0800614A:  291A         CMP        R1, #26
+  0x0800614C:  D200         BCS        .L1                      ; 0x08006150
+  0x0800614E:  3820         SUBS       R0, #32
+
.L1:
+  0x08006150:  4770         BX         LR
+
+

Section .rodata..Lstr.99 from PowerPro_lto.o, size=19, align=1

+
+  0x08006152:  73           DC.B       0x73                     ; 's'
+  0x08006153:  65           DC.B       0x65                     ; 'e'
+  0x08006154:  74           DC.B       0x74                     ; 't'
+  0x08006155:  7A           DC.B       0x7A                     ; 'z'
+  0x08006156:  65           DC.B       0x65                     ; 'e'
+  0x08006157:  20           DC.B       0x20                     ; ' '
+  0x08006158:  6F           DC.B       0x6F                     ; 'o'
+  0x08006159:  70           DC.B       0x70                     ; 'p'
+  0x0800615A:  74           DC.B       0x74                     ; 't'
+  0x0800615B:  69           DC.B       0x69                     ; 'i'
+  0x0800615C:  6F           DC.B       0x6F                     ; 'o'
+  0x0800615D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800615E:  20           DC.B       0x20                     ; ' '
+  0x0800615F:  62           DC.B       0x62                     ; 'b'
+  0x08006160:  79           DC.B       0x79                     ; 'y'
+  0x08006161:  74           DC.B       0x74                     ; 't'
+  0x08006162:  65           DC.B       0x65                     ; 'e'
+  0x08006163:  0D           DC.B       0x0D                     ; '\r'
+  0x08006164:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.9 from PowerPro_lto.o, size=59, align=1

+
+  0x08006165:  4E           DC.B       0x4E                     ; 'N'
+  0x08006166:  65           DC.B       0x65                     ; 'e'
+  0x08006167:  75           DC.B       0x75                     ; 'u'
+  0x08006168:  65           DC.B       0x65                     ; 'e'
+  0x08006169:  20           DC.B       0x20                     ; ' '
+  0x0800616A:  56           DC.B       0x56                     ; 'V'
+  0x0800616B:  65           DC.B       0x65                     ; 'e'
+  0x0800616C:  72           DC.B       0x72                     ; 'r'
+  0x0800616D:  73           DC.B       0x73                     ; 's'
+  0x0800616E:  69           DC.B       0x69                     ; 'i'
+  0x0800616F:  6F           DC.B       0x6F                     ; 'o'
+  0x08006170:  6E           DC.B       0x6E                     ; 'n'
+  0x08006171:  20           DC.B       0x20                     ; ' '
+  0x08006172:  50           DC.B       0x50                     ; 'P'
+  0x08006173:  61           DC.B       0x61                     ; 'a'
+  0x08006174:  72           DC.B       0x72                     ; 'r'
+  0x08006175:  61           DC.B       0x61                     ; 'a'
+  0x08006176:  6D           DC.B       0x6D                     ; 'm'
+  0x08006177:  65           DC.B       0x65                     ; 'e'
+  0x08006178:  74           DC.B       0x74                     ; 't'
+  0x08006179:  65           DC.B       0x65                     ; 'e'
+  0x0800617A:  72           DC.B       0x72                     ; 'r'
+  0x0800617B:  20           DC.B       0x20                     ; ' '
+  0x0800617C:  65           DC.B       0x65                     ; 'e'
+  0x0800617D:  72           DC.B       0x72                     ; 'r'
+  0x0800617E:  6B           DC.B       0x6B                     ; 'k'
+  0x0800617F:  61           DC.B       0x61                     ; 'a'
+  0x08006180:  6E           DC.B       0x6E                     ; 'n'
+  0x08006181:  6E           DC.B       0x6E                     ; 'n'
+  0x08006182:  74           DC.B       0x74                     ; 't'
+  0x08006183:  2C           DC.B       0x2C                     ; ','
+  0x08006184:  20           DC.B       0x20                     ; ' '
+  0x08006185:  73           DC.B       0x73                     ; 's'
+  0x08006186:  63           DC.B       0x63                     ; 'c'
+  0x08006187:  68           DC.B       0x68                     ; 'h'
+  0x08006188:  72           DC.B       0x72                     ; 'r'
+  0x08006189:  65           DC.B       0x65                     ; 'e'
+  0x0800618A:  69           DC.B       0x69                     ; 'i'
+  0x0800618B:  62           DC.B       0x62                     ; 'b'
+  0x0800618C:  65           DC.B       0x65                     ; 'e'
+  0x0800618D:  20           DC.B       0x20                     ; ' '
+  0x0800618E:  57           DC.B       0x57                     ; 'W'
+  0x0800618F:  65           DC.B       0x65                     ; 'e'
+  0x08006190:  72           DC.B       0x72                     ; 'r'
+  0x08006191:  6B           DC.B       0x6B                     ; 'k'
+  0x08006192:  73           DC.B       0x73                     ; 's'
+  0x08006193:  65           DC.B       0x65                     ; 'e'
+  0x08006194:  69           DC.B       0x69                     ; 'i'
+  0x08006195:  6E           DC.B       0x6E                     ; 'n'
+  0x08006196:  73           DC.B       0x73                     ; 's'
+  0x08006197:  74           DC.B       0x74                     ; 't'
+  0x08006198:  65           DC.B       0x65                     ; 'e'
+  0x08006199:  6C           DC.B       0x6C                     ; 'l'
+  0x0800619A:  6C           DC.B       0x6C                     ; 'l'
+  0x0800619B:  75           DC.B       0x75                     ; 'u'
+  0x0800619C:  6E           DC.B       0x6E                     ; 'n'
+  0x0800619D:  67           DC.B       0x67                     ; 'g'
+  0x0800619E:  0D           DC.B       0x0D                     ; '\r'
+  0x0800619F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.7 from PowerPro_lto.o, size=39, align=1

+
+  0x080061A0:  55           DC.B       0x55                     ; 'U'
+  0x080061A1:  61           DC.B       0x61                     ; 'a'
+  0x080061A2:  72           DC.B       0x72                     ; 'r'
+  0x080061A3:  74           DC.B       0x74                     ; 't'
+  0x080061A4:  20           DC.B       0x20                     ; ' '
+  0x080061A5:  45           DC.B       0x45                     ; 'E'
+  0x080061A6:  72           DC.B       0x72                     ; 'r'
+  0x080061A7:  72           DC.B       0x72                     ; 'r'
+  0x080061A8:  6F           DC.B       0x6F                     ; 'o'
+  0x080061A9:  72           DC.B       0x72                     ; 'r'
+  0x080061AA:  20           DC.B       0x20                     ; ' '
+  0x080061AB:  62           DC.B       0x62                     ; 'b'
+  0x080061AC:  65           DC.B       0x65                     ; 'e'
+  0x080061AD:  69           DC.B       0x69                     ; 'i'
+  0x080061AE:  20           DC.B       0x20                     ; ' '
+  0x080061AF:  6E           DC.B       0x6E                     ; 'n'
+  0x080061B0:  65           DC.B       0x65                     ; 'e'
+  0x080061B1:  75           DC.B       0x75                     ; 'u'
+  0x080061B2:  73           DC.B       0x73                     ; 's'
+  0x080061B3:  74           DC.B       0x74                     ; 't'
+  0x080061B4:  61           DC.B       0x61                     ; 'a'
+  0x080061B5:  72           DC.B       0x72                     ; 'r'
+  0x080061B6:  74           DC.B       0x74                     ; 't'
+  0x080061B7:  20           DC.B       0x20                     ; ' '
+  0x080061B8:  6E           DC.B       0x6E                     ; 'n'
+  0x080061B9:  61           DC.B       0x61                     ; 'a'
+  0x080061BA:  63           DC.B       0x63                     ; 'c'
+  0x080061BB:  68           DC.B       0x68                     ; 'h'
+  0x080061BC:  20           DC.B       0x20                     ; ' '
+  0x080061BD:  46           DC.B       0x46                     ; 'F'
+  0x080061BE:  65           DC.B       0x65                     ; 'e'
+  0x080061BF:  68           DC.B       0x68                     ; 'h'
+  0x080061C0:  6C           DC.B       0x6C                     ; 'l'
+  0x080061C1:  65           DC.B       0x65                     ; 'e'
+  0x080061C2:  72           DC.B       0x72                     ; 'r'
+  0x080061C3:  20           DC.B       0x20                     ; ' '
+  0x080061C4:  0A           DC.B       0x0A                     ; '\n'
+  0x080061C5:  0D           DC.B       0x0D                     ; '\r'
+  0x080061C6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18 from PowerPro_lto.o, size=35, align=1

+
+  0x080061C7:  4E           DC.B       0x4E                     ; 'N'
+  0x080061C8:  45           DC.B       0x45                     ; 'E'
+  0x080061C9:  57           DC.B       0x57                     ; 'W'
+  0x080061CA:  5F           DC.B       0x5F                     ; '_'
+  0x080061CB:  53           DC.B       0x53                     ; 'S'
+  0x080061CC:  54           DC.B       0x54                     ; 'T'
+  0x080061CD:  41           DC.B       0x41                     ; 'A'
+  0x080061CE:  54           DC.B       0x54                     ; 'T'
+  0x080061CF:  45           DC.B       0x45                     ; 'E'
+  0x080061D0:  3A           DC.B       0x3A                     ; ':'
+  0x080061D1:  20           DC.B       0x20                     ; ' '
+  0x080061D2:  4C           DC.B       0x4C                     ; 'L'
+  0x080061D3:  56           DC.B       0x56                     ; 'V'
+  0x080061D4:  50           DC.B       0x50                     ; 'P'
+  0x080061D5:  5F           DC.B       0x5F                     ; '_'
+  0x080061D6:  41           DC.B       0x41                     ; 'A'
+  0x080061D7:  75           DC.B       0x75                     ; 'u'
+  0x080061D8:  74           DC.B       0x74                     ; 't'
+  0x080061D9:  6F           DC.B       0x6F                     ; 'o'
+  0x080061DA:  20           DC.B       0x20                     ; ' '
+  0x080061DB:  4F           DC.B       0x4F                     ; 'O'
+  0x080061DC:  6E           DC.B       0x6E                     ; 'n'
+  0x080061DD:  2C           DC.B       0x2C                     ; ','
+  0x080061DE:  20           DC.B       0x20                     ; ' '
+  0x080061DF:  52           DC.B       0x52                     ; 'R'
+  0x080061E0:  65           DC.B       0x65                     ; 'e'
+  0x080061E1:  6C           DC.B       0x6C                     ; 'l'
+  0x080061E2:  61           DC.B       0x61                     ; 'a'
+  0x080061E3:  69           DC.B       0x69                     ; 'i'
+  0x080061E4:  73           DC.B       0x73                     ; 's'
+  0x080061E5:  20           DC.B       0x20                     ; ' '
+  0x080061E6:  6F           DC.B       0x6F                     ; 'o'
+  0x080061E7:  66           DC.B       0x66                     ; 'f'
+  0x080061E8:  66           DC.B       0x66                     ; 'f'
+  0x080061E9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22 from PowerPro_lto.o, size=19, align=1

+
+  0x080061EA:  4E           DC.B       0x4E                     ; 'N'
+  0x080061EB:  45           DC.B       0x45                     ; 'E'
+  0x080061EC:  57           DC.B       0x57                     ; 'W'
+  0x080061ED:  5F           DC.B       0x5F                     ; '_'
+  0x080061EE:  53           DC.B       0x53                     ; 'S'
+  0x080061EF:  54           DC.B       0x54                     ; 'T'
+  0x080061F0:  41           DC.B       0x41                     ; 'A'
+  0x080061F1:  54           DC.B       0x54                     ; 'T'
+  0x080061F2:  45           DC.B       0x45                     ; 'E'
+  0x080061F3:  3A           DC.B       0x3A                     ; ':'
+  0x080061F4:  20           DC.B       0x20                     ; ' '
+  0x080061F5:  4C           DC.B       0x4C                     ; 'L'
+  0x080061F6:  56           DC.B       0x56                     ; 'V'
+  0x080061F7:  50           DC.B       0x50                     ; 'P'
+  0x080061F8:  5F           DC.B       0x5F                     ; '_'
+  0x080061F9:  4F           DC.B       0x4F                     ; 'O'
+  0x080061FA:  46           DC.B       0x46                     ; 'F'
+  0x080061FB:  46           DC.B       0x46                     ; 'F'
+  0x080061FC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18.130 from PowerPro_lto.o, size=39, align=1

+
+  0x080061FD:  4E           DC.B       0x4E                     ; 'N'
+  0x080061FE:  45           DC.B       0x45                     ; 'E'
+  0x080061FF:  57           DC.B       0x57                     ; 'W'
+  0x08006200:  5F           DC.B       0x5F                     ; '_'
+  0x08006201:  53           DC.B       0x53                     ; 'S'
+  0x08006202:  54           DC.B       0x54                     ; 'T'
+  0x08006203:  41           DC.B       0x41                     ; 'A'
+  0x08006204:  54           DC.B       0x54                     ; 'T'
+  0x08006205:  45           DC.B       0x45                     ; 'E'
+  0x08006206:  3A           DC.B       0x3A                     ; ':'
+  0x08006207:  20           DC.B       0x20                     ; ' '
+  0x08006208:  4C           DC.B       0x4C                     ; 'L'
+  0x08006209:  56           DC.B       0x56                     ; 'V'
+  0x0800620A:  50           DC.B       0x50                     ; 'P'
+  0x0800620B:  5F           DC.B       0x5F                     ; '_'
+  0x0800620C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800620D:  56           DC.B       0x56                     ; 'V'
+  0x0800620E:  50           DC.B       0x50                     ; 'P'
+  0x0800620F:  5F           DC.B       0x5F                     ; '_'
+  0x08006210:  41           DC.B       0x41                     ; 'A'
+  0x08006211:  75           DC.B       0x75                     ; 'u'
+  0x08006212:  74           DC.B       0x74                     ; 't'
+  0x08006213:  6F           DC.B       0x6F                     ; 'o'
+  0x08006214:  20           DC.B       0x20                     ; ' '
+  0x08006215:  4F           DC.B       0x4F                     ; 'O'
+  0x08006216:  6E           DC.B       0x6E                     ; 'n'
+  0x08006217:  2C           DC.B       0x2C                     ; ','
+  0x08006218:  20           DC.B       0x20                     ; ' '
+  0x08006219:  52           DC.B       0x52                     ; 'R'
+  0x0800621A:  65           DC.B       0x65                     ; 'e'
+  0x0800621B:  6C           DC.B       0x6C                     ; 'l'
+  0x0800621C:  61           DC.B       0x61                     ; 'a'
+  0x0800621D:  69           DC.B       0x69                     ; 'i'
+  0x0800621E:  73           DC.B       0x73                     ; 's'
+  0x0800621F:  20           DC.B       0x20                     ; ' '
+  0x08006220:  6F           DC.B       0x6F                     ; 'o'
+  0x08006221:  66           DC.B       0x66                     ; 'f'
+  0x08006222:  66           DC.B       0x66                     ; 'f'
+  0x08006223:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.133 from PowerPro_lto.o, size=23, align=1

+
+  0x08006224:  4E           DC.B       0x4E                     ; 'N'
+  0x08006225:  45           DC.B       0x45                     ; 'E'
+  0x08006226:  57           DC.B       0x57                     ; 'W'
+  0x08006227:  5F           DC.B       0x5F                     ; '_'
+  0x08006228:  53           DC.B       0x53                     ; 'S'
+  0x08006229:  54           DC.B       0x54                     ; 'T'
+  0x0800622A:  41           DC.B       0x41                     ; 'A'
+  0x0800622B:  54           DC.B       0x54                     ; 'T'
+  0x0800622C:  45           DC.B       0x45                     ; 'E'
+  0x0800622D:  3A           DC.B       0x3A                     ; ':'
+  0x0800622E:  20           DC.B       0x20                     ; ' '
+  0x0800622F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006230:  56           DC.B       0x56                     ; 'V'
+  0x08006231:  50           DC.B       0x50                     ; 'P'
+  0x08006232:  5F           DC.B       0x5F                     ; '_'
+  0x08006233:  4F           DC.B       0x4F                     ; 'O'
+  0x08006234:  56           DC.B       0x56                     ; 'V'
+  0x08006235:  50           DC.B       0x50                     ; 'P'
+  0x08006236:  5F           DC.B       0x5F                     ; '_'
+  0x08006237:  4F           DC.B       0x4F                     ; 'O'
+  0x08006238:  46           DC.B       0x46                     ; 'F'
+  0x08006239:  46           DC.B       0x46                     ; 'F'
+  0x0800623A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18.153 from PowerPro_lto.o, size=35, align=1

+
+  0x0800623B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800623C:  45           DC.B       0x45                     ; 'E'
+  0x0800623D:  57           DC.B       0x57                     ; 'W'
+  0x0800623E:  5F           DC.B       0x5F                     ; '_'
+  0x0800623F:  53           DC.B       0x53                     ; 'S'
+  0x08006240:  54           DC.B       0x54                     ; 'T'
+  0x08006241:  41           DC.B       0x41                     ; 'A'
+  0x08006242:  54           DC.B       0x54                     ; 'T'
+  0x08006243:  45           DC.B       0x45                     ; 'E'
+  0x08006244:  3A           DC.B       0x3A                     ; ':'
+  0x08006245:  20           DC.B       0x20                     ; ' '
+  0x08006246:  4F           DC.B       0x4F                     ; 'O'
+  0x08006247:  56           DC.B       0x56                     ; 'V'
+  0x08006248:  50           DC.B       0x50                     ; 'P'
+  0x08006249:  5F           DC.B       0x5F                     ; '_'
+  0x0800624A:  41           DC.B       0x41                     ; 'A'
+  0x0800624B:  75           DC.B       0x75                     ; 'u'
+  0x0800624C:  74           DC.B       0x74                     ; 't'
+  0x0800624D:  6F           DC.B       0x6F                     ; 'o'
+  0x0800624E:  20           DC.B       0x20                     ; ' '
+  0x0800624F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006250:  6E           DC.B       0x6E                     ; 'n'
+  0x08006251:  2C           DC.B       0x2C                     ; ','
+  0x08006252:  20           DC.B       0x20                     ; ' '
+  0x08006253:  52           DC.B       0x52                     ; 'R'
+  0x08006254:  65           DC.B       0x65                     ; 'e'
+  0x08006255:  6C           DC.B       0x6C                     ; 'l'
+  0x08006256:  61           DC.B       0x61                     ; 'a'
+  0x08006257:  69           DC.B       0x69                     ; 'i'
+  0x08006258:  73           DC.B       0x73                     ; 's'
+  0x08006259:  20           DC.B       0x20                     ; ' '
+  0x0800625A:  6F           DC.B       0x6F                     ; 'o'
+  0x0800625B:  66           DC.B       0x66                     ; 'f'
+  0x0800625C:  66           DC.B       0x66                     ; 'f'
+  0x0800625D:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.156 from PowerPro_lto.o, size=19, align=1

+
+  0x0800625E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800625F:  45           DC.B       0x45                     ; 'E'
+  0x08006260:  57           DC.B       0x57                     ; 'W'
+  0x08006261:  5F           DC.B       0x5F                     ; '_'
+  0x08006262:  53           DC.B       0x53                     ; 'S'
+  0x08006263:  54           DC.B       0x54                     ; 'T'
+  0x08006264:  41           DC.B       0x41                     ; 'A'
+  0x08006265:  54           DC.B       0x54                     ; 'T'
+  0x08006266:  45           DC.B       0x45                     ; 'E'
+  0x08006267:  3A           DC.B       0x3A                     ; ':'
+  0x08006268:  20           DC.B       0x20                     ; ' '
+  0x08006269:  4F           DC.B       0x4F                     ; 'O'
+  0x0800626A:  56           DC.B       0x56                     ; 'V'
+  0x0800626B:  50           DC.B       0x50                     ; 'P'
+  0x0800626C:  5F           DC.B       0x5F                     ; '_'
+  0x0800626D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800626E:  46           DC.B       0x46                     ; 'F'
+  0x0800626F:  46           DC.B       0x46                     ; 'F'
+  0x08006270:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8.177 from PowerPro_lto.o, size=35, align=1

+
+  0x08006271:  4E           DC.B       0x4E                     ; 'N'
+  0x08006272:  45           DC.B       0x45                     ; 'E'
+  0x08006273:  57           DC.B       0x57                     ; 'W'
+  0x08006274:  5F           DC.B       0x5F                     ; '_'
+  0x08006275:  53           DC.B       0x53                     ; 'S'
+  0x08006276:  54           DC.B       0x54                     ; 'T'
+  0x08006277:  41           DC.B       0x41                     ; 'A'
+  0x08006278:  54           DC.B       0x54                     ; 'T'
+  0x08006279:  45           DC.B       0x45                     ; 'E'
+  0x0800627A:  3A           DC.B       0x3A                     ; ':'
+  0x0800627B:  20           DC.B       0x20                     ; ' '
+  0x0800627C:  53           DC.B       0x53                     ; 'S'
+  0x0800627D:  45           DC.B       0x45                     ; 'E'
+  0x0800627E:  43           DC.B       0x43                     ; 'C'
+  0x0800627F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006280:  4E           DC.B       0x4E                     ; 'N'
+  0x08006281:  44           DC.B       0x44                     ; 'D'
+  0x08006282:  41           DC.B       0x41                     ; 'A'
+  0x08006283:  52           DC.B       0x52                     ; 'R'
+  0x08006284:  59           DC.B       0x59                     ; 'Y'
+  0x08006285:  50           DC.B       0x50                     ; 'P'
+  0x08006286:  52           DC.B       0x52                     ; 'R'
+  0x08006287:  4F           DC.B       0x4F                     ; 'O'
+  0x08006288:  54           DC.B       0x54                     ; 'T'
+  0x08006289:  45           DC.B       0x45                     ; 'E'
+  0x0800628A:  43           DC.B       0x43                     ; 'C'
+  0x0800628B:  54           DC.B       0x54                     ; 'T'
+  0x0800628C:  49           DC.B       0x49                     ; 'I'
+  0x0800628D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800628E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800628F:  5F           DC.B       0x5F                     ; '_'
+  0x08006290:  4F           DC.B       0x4F                     ; 'O'
+  0x08006291:  46           DC.B       0x46                     ; 'F'
+  0x08006292:  46           DC.B       0x46                     ; 'F'
+  0x08006293:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.13.180 from PowerPro_lto.o, size=43, align=1

+
+  0x08006294:  4E           DC.B       0x4E                     ; 'N'
+  0x08006295:  45           DC.B       0x45                     ; 'E'
+  0x08006296:  57           DC.B       0x57                     ; 'W'
+  0x08006297:  5F           DC.B       0x5F                     ; '_'
+  0x08006298:  53           DC.B       0x53                     ; 'S'
+  0x08006299:  54           DC.B       0x54                     ; 'T'
+  0x0800629A:  41           DC.B       0x41                     ; 'A'
+  0x0800629B:  54           DC.B       0x54                     ; 'T'
+  0x0800629C:  45           DC.B       0x45                     ; 'E'
+  0x0800629D:  3A           DC.B       0x3A                     ; ':'
+  0x0800629E:  20           DC.B       0x20                     ; ' '
+  0x0800629F:  4D           DC.B       0x4D                     ; 'M'
+  0x080062A0:  41           DC.B       0x41                     ; 'A'
+  0x080062A1:  49           DC.B       0x49                     ; 'I'
+  0x080062A2:  4E           DC.B       0x4E                     ; 'N'
+  0x080062A3:  53           DC.B       0x53                     ; 'S'
+  0x080062A4:  57           DC.B       0x57                     ; 'W'
+  0x080062A5:  49           DC.B       0x49                     ; 'I'
+  0x080062A6:  54           DC.B       0x54                     ; 'T'
+  0x080062A7:  43           DC.B       0x43                     ; 'C'
+  0x080062A8:  48           DC.B       0x48                     ; 'H'
+  0x080062A9:  5F           DC.B       0x5F                     ; '_'
+  0x080062AA:  45           DC.B       0x45                     ; 'E'
+  0x080062AB:  52           DC.B       0x52                     ; 'R'
+  0x080062AC:  52           DC.B       0x52                     ; 'R'
+  0x080062AD:  4F           DC.B       0x4F                     ; 'O'
+  0x080062AE:  52           DC.B       0x52                     ; 'R'
+  0x080062AF:  2C           DC.B       0x2C                     ; ','
+  0x080062B0:  20           DC.B       0x20                     ; ' '
+  0x080062B1:  54           DC.B       0x54                     ; 'T'
+  0x080062B2:  65           DC.B       0x65                     ; 'e'
+  0x080062B3:  6D           DC.B       0x6D                     ; 'm'
+  0x080062B4:  70           DC.B       0x70                     ; 'p'
+  0x080062B5:  20           DC.B       0x20                     ; ' '
+  0x080062B6:  74           DC.B       0x74                     ; 't'
+  0x080062B7:  6F           DC.B       0x6F                     ; 'o'
+  0x080062B8:  6F           DC.B       0x6F                     ; 'o'
+  0x080062B9:  20           DC.B       0x20                     ; ' '
+  0x080062BA:  68           DC.B       0x68                     ; 'h'
+  0x080062BB:  69           DC.B       0x69                     ; 'i'
+  0x080062BC:  67           DC.B       0x67                     ; 'g'
+  0x080062BD:  68           DC.B       0x68                     ; 'h'
+  0x080062BE:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.203 from PowerPro_lto.o, size=35, align=1

+
+  0x080062BF:  76           DC.B       0x76                     ; 'v'
+  0x080062C0:  6F           DC.B       0x6F                     ; 'o'
+  0x080062C1:  6C           DC.B       0x6C                     ; 'l'
+  0x080062C2:  74           DC.B       0x74                     ; 't'
+  0x080062C3:  61           DC.B       0x61                     ; 'a'
+  0x080062C4:  67           DC.B       0x67                     ; 'g'
+  0x080062C5:  65           DC.B       0x65                     ; 'e'
+  0x080062C6:  20           DC.B       0x20                     ; ' '
+  0x080062C7:  69           DC.B       0x69                     ; 'i'
+  0x080062C8:  6E           DC.B       0x6E                     ; 'n'
+  0x080062C9:  3D           DC.B       0x3D                     ; '='
+  0x080062CA:  20           DC.B       0x20                     ; ' '
+  0x080062CB:  25           DC.B       0x25                     ; '%'
+  0x080062CC:  64           DC.B       0x64                     ; 'd'
+  0x080062CD:  2C           DC.B       0x2C                     ; ','
+  0x080062CE:  20           DC.B       0x20                     ; ' '
+  0x080062CF:  6F           DC.B       0x6F                     ; 'o'
+  0x080062D0:  75           DC.B       0x75                     ; 'u'
+  0x080062D1:  74           DC.B       0x74                     ; 't'
+  0x080062D2:  3D           DC.B       0x3D                     ; '='
+  0x080062D3:  20           DC.B       0x20                     ; ' '
+  0x080062D4:  25           DC.B       0x25                     ; '%'
+  0x080062D5:  64           DC.B       0x64                     ; 'd'
+  0x080062D6:  2C           DC.B       0x2C                     ; ','
+  0x080062D7:  20           DC.B       0x20                     ; ' '
+  0x080062D8:  64           DC.B       0x64                     ; 'd'
+  0x080062D9:  72           DC.B       0x72                     ; 'r'
+  0x080062DA:  6F           DC.B       0x6F                     ; 'o'
+  0x080062DB:  70           DC.B       0x70                     ; 'p'
+  0x080062DC:  20           DC.B       0x20                     ; ' '
+  0x080062DD:  25           DC.B       0x25                     ; '%'
+  0x080062DE:  64           DC.B       0x64                     ; 'd'
+  0x080062DF:  0D           DC.B       0x0D                     ; '\r'
+  0x080062E0:  0A           DC.B       0x0A                     ; '\n'
+  0x080062E1:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_month_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=87, align=1

+
+
__SEGGER_RTL_c_locale_month_names:
+  0x080062E2:  4A           DC.B       0x4A                     ; 'J'
+  0x080062E3:  61           DC.B       0x61                     ; 'a'
+  0x080062E4:  6E           DC.B       0x6E                     ; 'n'
+  0x080062E5:  75           DC.B       0x75                     ; 'u'
+  0x080062E6:  61           DC.B       0x61                     ; 'a'
+  0x080062E7:  72           DC.B       0x72                     ; 'r'
+  0x080062E8:  79           DC.B       0x79                     ; 'y'
+  0x080062E9:  00           DC.B       0x00                     ; '\0'
+  0x080062EA:  46           DC.B       0x46                     ; 'F'
+  0x080062EB:  65           DC.B       0x65                     ; 'e'
+  0x080062EC:  62           DC.B       0x62                     ; 'b'
+  0x080062ED:  72           DC.B       0x72                     ; 'r'
+  0x080062EE:  75           DC.B       0x75                     ; 'u'
+  0x080062EF:  61           DC.B       0x61                     ; 'a'
+  0x080062F0:  72           DC.B       0x72                     ; 'r'
+  0x080062F1:  79           DC.B       0x79                     ; 'y'
+  0x080062F2:  00           DC.B       0x00                     ; '\0'
+  0x080062F3:  4D           DC.B       0x4D                     ; 'M'
+  0x080062F4:  61           DC.B       0x61                     ; 'a'
+  0x080062F5:  72           DC.B       0x72                     ; 'r'
+  0x080062F6:  63           DC.B       0x63                     ; 'c'
+  0x080062F7:  68           DC.B       0x68                     ; 'h'
+  0x080062F8:  00           DC.B       0x00                     ; '\0'
+  0x080062F9:  41           DC.B       0x41                     ; 'A'
+  0x080062FA:  70           DC.B       0x70                     ; 'p'
+  0x080062FB:  72           DC.B       0x72                     ; 'r'
+  0x080062FC:  69           DC.B       0x69                     ; 'i'
+  0x080062FD:  6C           DC.B       0x6C                     ; 'l'
+  0x080062FE:  00           DC.B       0x00                     ; '\0'
+  0x080062FF:  4D           DC.B       0x4D                     ; 'M'
+  0x08006300:  61           DC.B       0x61                     ; 'a'
+  0x08006301:  79           DC.B       0x79                     ; 'y'
+  0x08006302:  00           DC.B       0x00                     ; '\0'
+  0x08006303:  4A           DC.B       0x4A                     ; 'J'
+  0x08006304:  75           DC.B       0x75                     ; 'u'
+  0x08006305:  6E           DC.B       0x6E                     ; 'n'
+  0x08006306:  65           DC.B       0x65                     ; 'e'
+  0x08006307:  00           DC.B       0x00                     ; '\0'
+  0x08006308:  4A           DC.B       0x4A                     ; 'J'
+  0x08006309:  75           DC.B       0x75                     ; 'u'
+  0x0800630A:  6C           DC.B       0x6C                     ; 'l'
+  0x0800630B:  79           DC.B       0x79                     ; 'y'
+  0x0800630C:  00           DC.B       0x00                     ; '\0'
+  0x0800630D:  41           DC.B       0x41                     ; 'A'
+  0x0800630E:  75           DC.B       0x75                     ; 'u'
+  0x0800630F:  67           DC.B       0x67                     ; 'g'
+  0x08006310:  75           DC.B       0x75                     ; 'u'
+  0x08006311:  73           DC.B       0x73                     ; 's'
+  0x08006312:  74           DC.B       0x74                     ; 't'
+  0x08006313:  00           DC.B       0x00                     ; '\0'
+  0x08006314:  53           DC.B       0x53                     ; 'S'
+  0x08006315:  65           DC.B       0x65                     ; 'e'
+  0x08006316:  70           DC.B       0x70                     ; 'p'
+  0x08006317:  74           DC.B       0x74                     ; 't'
+  0x08006318:  65           DC.B       0x65                     ; 'e'
+  0x08006319:  6D           DC.B       0x6D                     ; 'm'
+  0x0800631A:  62           DC.B       0x62                     ; 'b'
+  0x0800631B:  65           DC.B       0x65                     ; 'e'
+  0x0800631C:  72           DC.B       0x72                     ; 'r'
+  0x0800631D:  00           DC.B       0x00                     ; '\0'
+  0x0800631E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800631F:  63           DC.B       0x63                     ; 'c'
+  0x08006320:  74           DC.B       0x74                     ; 't'
+  0x08006321:  6F           DC.B       0x6F                     ; 'o'
+  0x08006322:  62           DC.B       0x62                     ; 'b'
+  0x08006323:  65           DC.B       0x65                     ; 'e'
+  0x08006324:  72           DC.B       0x72                     ; 'r'
+  0x08006325:  00           DC.B       0x00                     ; '\0'
+  0x08006326:  4E           DC.B       0x4E                     ; 'N'
+  0x08006327:  6F           DC.B       0x6F                     ; 'o'
+  0x08006328:  76           DC.B       0x76                     ; 'v'
+  0x08006329:  65           DC.B       0x65                     ; 'e'
+  0x0800632A:  6D           DC.B       0x6D                     ; 'm'
+  0x0800632B:  62           DC.B       0x62                     ; 'b'
+  0x0800632C:  65           DC.B       0x65                     ; 'e'
+  0x0800632D:  72           DC.B       0x72                     ; 'r'
+  0x0800632E:  00           DC.B       0x00                     ; '\0'
+  0x0800632F:  44           DC.B       0x44                     ; 'D'
+  0x08006330:  65           DC.B       0x65                     ; 'e'
+  0x08006331:  63           DC.B       0x63                     ; 'c'
+  0x08006332:  65           DC.B       0x65                     ; 'e'
+  0x08006333:  6D           DC.B       0x6D                     ; 'm'
+  0x08006334:  62           DC.B       0x62                     ; 'b'
+  0x08006335:  65           DC.B       0x65                     ; 'e'
+  0x08006336:  72           DC.B       0x72                     ; 'r'
+  0x08006337:  00           DC.B       0x00                     ; '\0'
+  0x08006338:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_am_pm_indicator from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=7, align=1

+
+
__SEGGER_RTL_c_locale_am_pm_indicator:
+  0x08006339:  41           DC.B       0x41                     ; 'A'
+  0x0800633A:  4D           DC.B       0x4D                     ; 'M'
+  0x0800633B:  00           DC.B       0x00                     ; '\0'
+  0x0800633C:  50           DC.B       0x50                     ; 'P'
+  0x0800633D:  4D           DC.B       0x4D                     ; 'M'
+  0x0800633E:  00           DC.B       0x00                     ; '\0'
+  0x0800633F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_date_time_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=15, align=1

+
+
__SEGGER_RTL_c_locale_date_time_format:
+  0x08006340:  25           DC.B       0x25                     ; '%'
+  0x08006341:  61           DC.B       0x61                     ; 'a'
+  0x08006342:  20           DC.B       0x20                     ; ' '
+  0x08006343:  25           DC.B       0x25                     ; '%'
+  0x08006344:  62           DC.B       0x62                     ; 'b'
+  0x08006345:  20           DC.B       0x20                     ; ' '
+  0x08006346:  25           DC.B       0x25                     ; '%'
+  0x08006347:  65           DC.B       0x65                     ; 'e'
+  0x08006348:  20           DC.B       0x20                     ; ' '
+  0x08006349:  25           DC.B       0x25                     ; '%'
+  0x0800634A:  54           DC.B       0x54                     ; 'T'
+  0x0800634B:  20           DC.B       0x20                     ; ' '
+  0x0800634C:  25           DC.B       0x25                     ; '%'
+  0x0800634D:  59           DC.B       0x59                     ; 'Y'
+  0x0800634E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr from PowerPro_lto.o, size=18, align=1

+
+  0x0800634F:  42           DC.B       0x42                     ; 'B'
+  0x08006350:  55           DC.B       0x55                     ; 'U'
+  0x08006351:  54           DC.B       0x54                     ; 'T'
+  0x08006352:  54           DC.B       0x54                     ; 'T'
+  0x08006353:  4F           DC.B       0x4F                     ; 'O'
+  0x08006354:  4E           DC.B       0x4E                     ; 'N'
+  0x08006355:  3A           DC.B       0x3A                     ; ':'
+  0x08006356:  20           DC.B       0x20                     ; ' '
+  0x08006357:  41           DC.B       0x41                     ; 'A'
+  0x08006358:  75           DC.B       0x75                     ; 'u'
+  0x08006359:  74           DC.B       0x74                     ; 't'
+  0x0800635A:  6F           DC.B       0x6F                     ; 'o'
+  0x0800635B:  20           DC.B       0x20                     ; ' '
+  0x0800635C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800635D:  6F           DC.B       0x6F                     ; 'o'
+  0x0800635E:  64           DC.B       0x64                     ; 'd'
+  0x0800635F:  65           DC.B       0x65                     ; 'e'
+  0x08006360:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8 from PowerPro_lto.o, size=18, align=1

+
+  0x08006361:  4B           DC.B       0x4B                     ; 'K'
+  0x08006362:  6F           DC.B       0x6F                     ; 'o'
+  0x08006363:  6E           DC.B       0x6E                     ; 'n'
+  0x08006364:  66           DC.B       0x66                     ; 'f'
+  0x08006365:  69           DC.B       0x69                     ; 'i'
+  0x08006366:  67           DC.B       0x67                     ; 'g'
+  0x08006367:  20           DC.B       0x20                     ; ' '
+  0x08006368:  76           DC.B       0x76                     ; 'v'
+  0x08006369:  6F           DC.B       0x6F                     ; 'o'
+  0x0800636A:  72           DC.B       0x72                     ; 'r'
+  0x0800636B:  68           DC.B       0x68                     ; 'h'
+  0x0800636C:  61           DC.B       0x61                     ; 'a'
+  0x0800636D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800636E:  64           DC.B       0x64                     ; 'd'
+  0x0800636F:  65           DC.B       0x65                     ; 'e'
+  0x08006370:  6E           DC.B       0x6E                     ; 'n'
+  0x08006371:  0D           DC.B       0x0D                     ; '\r'
+  0x08006372:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.10 from PowerPro_lto.o, size=46, align=1

+
+  0x08006373:  45           DC.B       0x45                     ; 'E'
+  0x08006374:  72           DC.B       0x72                     ; 'r'
+  0x08006375:  73           DC.B       0x73                     ; 's'
+  0x08006376:  74           DC.B       0x74                     ; 't'
+  0x08006377:  73           DC.B       0x73                     ; 's'
+  0x08006378:  74           DC.B       0x74                     ; 't'
+  0x08006379:  61           DC.B       0x61                     ; 'a'
+  0x0800637A:  72           DC.B       0x72                     ; 'r'
+  0x0800637B:  74           DC.B       0x74                     ; 't'
+  0x0800637C:  20           DC.B       0x20                     ; ' '
+  0x0800637D:  65           DC.B       0x65                     ; 'e'
+  0x0800637E:  72           DC.B       0x72                     ; 'r'
+  0x0800637F:  6B           DC.B       0x6B                     ; 'k'
+  0x08006380:  61           DC.B       0x61                     ; 'a'
+  0x08006381:  6E           DC.B       0x6E                     ; 'n'
+  0x08006382:  6E           DC.B       0x6E                     ; 'n'
+  0x08006383:  74           DC.B       0x74                     ; 't'
+  0x08006384:  2C           DC.B       0x2C                     ; ','
+  0x08006385:  20           DC.B       0x20                     ; ' '
+  0x08006386:  73           DC.B       0x73                     ; 's'
+  0x08006387:  63           DC.B       0x63                     ; 'c'
+  0x08006388:  68           DC.B       0x68                     ; 'h'
+  0x08006389:  72           DC.B       0x72                     ; 'r'
+  0x0800638A:  65           DC.B       0x65                     ; 'e'
+  0x0800638B:  69           DC.B       0x69                     ; 'i'
+  0x0800638C:  62           DC.B       0x62                     ; 'b'
+  0x0800638D:  65           DC.B       0x65                     ; 'e'
+  0x0800638E:  20           DC.B       0x20                     ; ' '
+  0x0800638F:  57           DC.B       0x57                     ; 'W'
+  0x08006390:  65           DC.B       0x65                     ; 'e'
+  0x08006391:  72           DC.B       0x72                     ; 'r'
+  0x08006392:  6B           DC.B       0x6B                     ; 'k'
+  0x08006393:  73           DC.B       0x73                     ; 's'
+  0x08006394:  65           DC.B       0x65                     ; 'e'
+  0x08006395:  69           DC.B       0x69                     ; 'i'
+  0x08006396:  6E           DC.B       0x6E                     ; 'n'
+  0x08006397:  73           DC.B       0x73                     ; 's'
+  0x08006398:  74           DC.B       0x74                     ; 't'
+  0x08006399:  65           DC.B       0x65                     ; 'e'
+  0x0800639A:  6C           DC.B       0x6C                     ; 'l'
+  0x0800639B:  6C           DC.B       0x6C                     ; 'l'
+  0x0800639C:  75           DC.B       0x75                     ; 'u'
+  0x0800639D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800639E:  67           DC.B       0x67                     ; 'g'
+  0x0800639F:  0D           DC.B       0x0D                     ; '\r'
+  0x080063A0:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.1 from PowerPro_lto.o, size=14, align=1

+
+  0x080063A1:  75           DC.B       0x75                     ; 'u'
+  0x080063A2:  61           DC.B       0x61                     ; 'a'
+  0x080063A3:  72           DC.B       0x72                     ; 'r'
+  0x080063A4:  74           DC.B       0x74                     ; 't'
+  0x080063A5:  20           DC.B       0x20                     ; ' '
+  0x080063A6:  65           DC.B       0x65                     ; 'e'
+  0x080063A7:  72           DC.B       0x72                     ; 'r'
+  0x080063A8:  72           DC.B       0x72                     ; 'r'
+  0x080063A9:  6F           DC.B       0x6F                     ; 'o'
+  0x080063AA:  72           DC.B       0x72                     ; 'r'
+  0x080063AB:  20           DC.B       0x20                     ; ' '
+  0x080063AC:  0A           DC.B       0x0A                     ; '\n'
+  0x080063AD:  0D           DC.B       0x0D                     ; '\r'
+  0x080063AE:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.117 from PowerPro_lto.o, size=30, align=1

+
+  0x080063AF:  4C           DC.B       0x4C                     ; 'L'
+  0x080063B0:  56           DC.B       0x56                     ; 'V'
+  0x080063B1:  50           DC.B       0x50                     ; 'P'
+  0x080063B2:  5F           DC.B       0x5F                     ; '_'
+  0x080063B3:  53           DC.B       0x53                     ; 'S'
+  0x080063B4:  4D           DC.B       0x4D                     ; 'M'
+  0x080063B5:  5F           DC.B       0x5F                     ; '_'
+  0x080063B6:  4F           DC.B       0x4F                     ; 'O'
+  0x080063B7:  66           DC.B       0x66                     ; 'f'
+  0x080063B8:  66           DC.B       0x66                     ; 'f'
+  0x080063B9:  3A           DC.B       0x3A                     ; ':'
+  0x080063BA:  20           DC.B       0x20                     ; ' '
+  0x080063BB:  4E           DC.B       0x4E                     ; 'N'
+  0x080063BC:  45           DC.B       0x45                     ; 'E'
+  0x080063BD:  57           DC.B       0x57                     ; 'W'
+  0x080063BE:  5F           DC.B       0x5F                     ; '_'
+  0x080063BF:  53           DC.B       0x53                     ; 'S'
+  0x080063C0:  54           DC.B       0x54                     ; 'T'
+  0x080063C1:  41           DC.B       0x41                     ; 'A'
+  0x080063C2:  54           DC.B       0x54                     ; 'T'
+  0x080063C3:  45           DC.B       0x45                     ; 'E'
+  0x080063C4:  3A           DC.B       0x3A                     ; ':'
+  0x080063C5:  20           DC.B       0x20                     ; ' '
+  0x080063C6:  4C           DC.B       0x4C                     ; 'L'
+  0x080063C7:  56           DC.B       0x56                     ; 'V'
+  0x080063C8:  50           DC.B       0x50                     ; 'P'
+  0x080063C9:  5F           DC.B       0x5F                     ; '_'
+  0x080063CA:  4F           DC.B       0x4F                     ; 'O'
+  0x080063CB:  4E           DC.B       0x4E                     ; 'N'
+  0x080063CC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23 from PowerPro_lto.o, size=18, align=1

+
+  0x080063CD:  4E           DC.B       0x4E                     ; 'N'
+  0x080063CE:  45           DC.B       0x45                     ; 'E'
+  0x080063CF:  57           DC.B       0x57                     ; 'W'
+  0x080063D0:  5F           DC.B       0x5F                     ; '_'
+  0x080063D1:  53           DC.B       0x53                     ; 'S'
+  0x080063D2:  54           DC.B       0x54                     ; 'T'
+  0x080063D3:  41           DC.B       0x41                     ; 'A'
+  0x080063D4:  54           DC.B       0x54                     ; 'T'
+  0x080063D5:  45           DC.B       0x45                     ; 'E'
+  0x080063D6:  3A           DC.B       0x3A                     ; ':'
+  0x080063D7:  20           DC.B       0x20                     ; ' '
+  0x080063D8:  4C           DC.B       0x4C                     ; 'L'
+  0x080063D9:  56           DC.B       0x56                     ; 'V'
+  0x080063DA:  50           DC.B       0x50                     ; 'P'
+  0x080063DB:  5F           DC.B       0x5F                     ; '_'
+  0x080063DC:  4F           DC.B       0x4F                     ; 'O'
+  0x080063DD:  4E           DC.B       0x4E                     ; 'N'
+  0x080063DE:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.123 from PowerPro_lto.o, size=38, align=1

+
+  0x080063DF:  4C           DC.B       0x4C                     ; 'L'
+  0x080063E0:  56           DC.B       0x56                     ; 'V'
+  0x080063E1:  50           DC.B       0x50                     ; 'P'
+  0x080063E2:  5F           DC.B       0x5F                     ; '_'
+  0x080063E3:  4F           DC.B       0x4F                     ; 'O'
+  0x080063E4:  56           DC.B       0x56                     ; 'V'
+  0x080063E5:  50           DC.B       0x50                     ; 'P'
+  0x080063E6:  5F           DC.B       0x5F                     ; '_'
+  0x080063E7:  53           DC.B       0x53                     ; 'S'
+  0x080063E8:  4D           DC.B       0x4D                     ; 'M'
+  0x080063E9:  5F           DC.B       0x5F                     ; '_'
+  0x080063EA:  4F           DC.B       0x4F                     ; 'O'
+  0x080063EB:  66           DC.B       0x66                     ; 'f'
+  0x080063EC:  66           DC.B       0x66                     ; 'f'
+  0x080063ED:  3A           DC.B       0x3A                     ; ':'
+  0x080063EE:  20           DC.B       0x20                     ; ' '
+  0x080063EF:  4E           DC.B       0x4E                     ; 'N'
+  0x080063F0:  45           DC.B       0x45                     ; 'E'
+  0x080063F1:  57           DC.B       0x57                     ; 'W'
+  0x080063F2:  5F           DC.B       0x5F                     ; '_'
+  0x080063F3:  53           DC.B       0x53                     ; 'S'
+  0x080063F4:  54           DC.B       0x54                     ; 'T'
+  0x080063F5:  41           DC.B       0x41                     ; 'A'
+  0x080063F6:  54           DC.B       0x54                     ; 'T'
+  0x080063F7:  45           DC.B       0x45                     ; 'E'
+  0x080063F8:  3A           DC.B       0x3A                     ; ':'
+  0x080063F9:  20           DC.B       0x20                     ; ' '
+  0x080063FA:  4C           DC.B       0x4C                     ; 'L'
+  0x080063FB:  56           DC.B       0x56                     ; 'V'
+  0x080063FC:  50           DC.B       0x50                     ; 'P'
+  0x080063FD:  5F           DC.B       0x5F                     ; '_'
+  0x080063FE:  4F           DC.B       0x4F                     ; 'O'
+  0x080063FF:  56           DC.B       0x56                     ; 'V'
+  0x08006400:  50           DC.B       0x50                     ; 'P'
+  0x08006401:  5F           DC.B       0x5F                     ; '_'
+  0x08006402:  4F           DC.B       0x4F                     ; 'O'
+  0x08006403:  4E           DC.B       0x4E                     ; 'N'
+  0x08006404:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.20.132 from PowerPro_lto.o, size=38, align=1

+
+  0x08006405:  4E           DC.B       0x4E                     ; 'N'
+  0x08006406:  45           DC.B       0x45                     ; 'E'
+  0x08006407:  57           DC.B       0x57                     ; 'W'
+  0x08006408:  5F           DC.B       0x5F                     ; '_'
+  0x08006409:  53           DC.B       0x53                     ; 'S'
+  0x0800640A:  54           DC.B       0x54                     ; 'T'
+  0x0800640B:  41           DC.B       0x41                     ; 'A'
+  0x0800640C:  54           DC.B       0x54                     ; 'T'
+  0x0800640D:  45           DC.B       0x45                     ; 'E'
+  0x0800640E:  3A           DC.B       0x3A                     ; ':'
+  0x0800640F:  20           DC.B       0x20                     ; ' '
+  0x08006410:  4C           DC.B       0x4C                     ; 'L'
+  0x08006411:  56           DC.B       0x56                     ; 'V'
+  0x08006412:  50           DC.B       0x50                     ; 'P'
+  0x08006413:  5F           DC.B       0x5F                     ; '_'
+  0x08006414:  4F           DC.B       0x4F                     ; 'O'
+  0x08006415:  56           DC.B       0x56                     ; 'V'
+  0x08006416:  50           DC.B       0x50                     ; 'P'
+  0x08006417:  5F           DC.B       0x5F                     ; '_'
+  0x08006418:  41           DC.B       0x41                     ; 'A'
+  0x08006419:  75           DC.B       0x75                     ; 'u'
+  0x0800641A:  74           DC.B       0x74                     ; 't'
+  0x0800641B:  6F           DC.B       0x6F                     ; 'o'
+  0x0800641C:  20           DC.B       0x20                     ; ' '
+  0x0800641D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800641E:  6E           DC.B       0x6E                     ; 'n'
+  0x0800641F:  2C           DC.B       0x2C                     ; ','
+  0x08006420:  20           DC.B       0x20                     ; ' '
+  0x08006421:  52           DC.B       0x52                     ; 'R'
+  0x08006422:  65           DC.B       0x65                     ; 'e'
+  0x08006423:  6C           DC.B       0x6C                     ; 'l'
+  0x08006424:  61           DC.B       0x61                     ; 'a'
+  0x08006425:  69           DC.B       0x69                     ; 'i'
+  0x08006426:  73           DC.B       0x73                     ; 's'
+  0x08006427:  20           DC.B       0x20                     ; ' '
+  0x08006428:  6F           DC.B       0x6F                     ; 'o'
+  0x08006429:  6E           DC.B       0x6E                     ; 'n'
+  0x0800642A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23.134 from PowerPro_lto.o, size=22, align=1

+
+  0x0800642B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800642C:  45           DC.B       0x45                     ; 'E'
+  0x0800642D:  57           DC.B       0x57                     ; 'W'
+  0x0800642E:  5F           DC.B       0x5F                     ; '_'
+  0x0800642F:  53           DC.B       0x53                     ; 'S'
+  0x08006430:  54           DC.B       0x54                     ; 'T'
+  0x08006431:  41           DC.B       0x41                     ; 'A'
+  0x08006432:  54           DC.B       0x54                     ; 'T'
+  0x08006433:  45           DC.B       0x45                     ; 'E'
+  0x08006434:  3A           DC.B       0x3A                     ; ':'
+  0x08006435:  20           DC.B       0x20                     ; ' '
+  0x08006436:  4C           DC.B       0x4C                     ; 'L'
+  0x08006437:  56           DC.B       0x56                     ; 'V'
+  0x08006438:  50           DC.B       0x50                     ; 'P'
+  0x08006439:  5F           DC.B       0x5F                     ; '_'
+  0x0800643A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800643B:  56           DC.B       0x56                     ; 'V'
+  0x0800643C:  50           DC.B       0x50                     ; 'P'
+  0x0800643D:  5F           DC.B       0x5F                     ; '_'
+  0x0800643E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800643F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006440:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.10.139 from PowerPro_lto.o, size=26, align=1

+
+  0x08006441:  4E           DC.B       0x4E                     ; 'N'
+  0x08006442:  45           DC.B       0x45                     ; 'E'
+  0x08006443:  57           DC.B       0x57                     ; 'W'
+  0x08006444:  5F           DC.B       0x5F                     ; '_'
+  0x08006445:  53           DC.B       0x53                     ; 'S'
+  0x08006446:  54           DC.B       0x54                     ; 'T'
+  0x08006447:  41           DC.B       0x41                     ; 'A'
+  0x08006448:  54           DC.B       0x54                     ; 'T'
+  0x08006449:  45           DC.B       0x45                     ; 'E'
+  0x0800644A:  3A           DC.B       0x3A                     ; ':'
+  0x0800644B:  20           DC.B       0x20                     ; ' '
+  0x0800644C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800644D:  41           DC.B       0x41                     ; 'A'
+  0x0800644E:  49           DC.B       0x49                     ; 'I'
+  0x0800644F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006450:  53           DC.B       0x53                     ; 'S'
+  0x08006451:  57           DC.B       0x57                     ; 'W'
+  0x08006452:  49           DC.B       0x49                     ; 'I'
+  0x08006453:  54           DC.B       0x54                     ; 'T'
+  0x08006454:  43           DC.B       0x43                     ; 'C'
+  0x08006455:  48           DC.B       0x48                     ; 'H'
+  0x08006456:  5F           DC.B       0x5F                     ; '_'
+  0x08006457:  4F           DC.B       0x4F                     ; 'O'
+  0x08006458:  46           DC.B       0x46                     ; 'F'
+  0x08006459:  46           DC.B       0x46                     ; 'F'
+  0x0800645A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.146 from PowerPro_lto.o, size=30, align=1

+
+  0x0800645B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800645C:  56           DC.B       0x56                     ; 'V'
+  0x0800645D:  50           DC.B       0x50                     ; 'P'
+  0x0800645E:  5F           DC.B       0x5F                     ; '_'
+  0x0800645F:  53           DC.B       0x53                     ; 'S'
+  0x08006460:  4D           DC.B       0x4D                     ; 'M'
+  0x08006461:  5F           DC.B       0x5F                     ; '_'
+  0x08006462:  4F           DC.B       0x4F                     ; 'O'
+  0x08006463:  66           DC.B       0x66                     ; 'f'
+  0x08006464:  66           DC.B       0x66                     ; 'f'
+  0x08006465:  3A           DC.B       0x3A                     ; ':'
+  0x08006466:  20           DC.B       0x20                     ; ' '
+  0x08006467:  4E           DC.B       0x4E                     ; 'N'
+  0x08006468:  45           DC.B       0x45                     ; 'E'
+  0x08006469:  57           DC.B       0x57                     ; 'W'
+  0x0800646A:  5F           DC.B       0x5F                     ; '_'
+  0x0800646B:  53           DC.B       0x53                     ; 'S'
+  0x0800646C:  54           DC.B       0x54                     ; 'T'
+  0x0800646D:  41           DC.B       0x41                     ; 'A'
+  0x0800646E:  54           DC.B       0x54                     ; 'T'
+  0x0800646F:  45           DC.B       0x45                     ; 'E'
+  0x08006470:  3A           DC.B       0x3A                     ; ':'
+  0x08006471:  20           DC.B       0x20                     ; ' '
+  0x08006472:  4F           DC.B       0x4F                     ; 'O'
+  0x08006473:  56           DC.B       0x56                     ; 'V'
+  0x08006474:  50           DC.B       0x50                     ; 'P'
+  0x08006475:  5F           DC.B       0x5F                     ; '_'
+  0x08006476:  4F           DC.B       0x4F                     ; 'O'
+  0x08006477:  4E           DC.B       0x4E                     ; 'N'
+  0x08006478:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.20.155 from PowerPro_lto.o, size=38, align=1

+
+  0x08006479:  4E           DC.B       0x4E                     ; 'N'
+  0x0800647A:  45           DC.B       0x45                     ; 'E'
+  0x0800647B:  57           DC.B       0x57                     ; 'W'
+  0x0800647C:  5F           DC.B       0x5F                     ; '_'
+  0x0800647D:  53           DC.B       0x53                     ; 'S'
+  0x0800647E:  54           DC.B       0x54                     ; 'T'
+  0x0800647F:  41           DC.B       0x41                     ; 'A'
+  0x08006480:  54           DC.B       0x54                     ; 'T'
+  0x08006481:  45           DC.B       0x45                     ; 'E'
+  0x08006482:  3A           DC.B       0x3A                     ; ':'
+  0x08006483:  20           DC.B       0x20                     ; ' '
+  0x08006484:  4F           DC.B       0x4F                     ; 'O'
+  0x08006485:  56           DC.B       0x56                     ; 'V'
+  0x08006486:  50           DC.B       0x50                     ; 'P'
+  0x08006487:  5F           DC.B       0x5F                     ; '_'
+  0x08006488:  4F           DC.B       0x4F                     ; 'O'
+  0x08006489:  56           DC.B       0x56                     ; 'V'
+  0x0800648A:  50           DC.B       0x50                     ; 'P'
+  0x0800648B:  5F           DC.B       0x5F                     ; '_'
+  0x0800648C:  41           DC.B       0x41                     ; 'A'
+  0x0800648D:  75           DC.B       0x75                     ; 'u'
+  0x0800648E:  74           DC.B       0x74                     ; 't'
+  0x0800648F:  6F           DC.B       0x6F                     ; 'o'
+  0x08006490:  20           DC.B       0x20                     ; ' '
+  0x08006491:  4F           DC.B       0x4F                     ; 'O'
+  0x08006492:  6E           DC.B       0x6E                     ; 'n'
+  0x08006493:  2C           DC.B       0x2C                     ; ','
+  0x08006494:  20           DC.B       0x20                     ; ' '
+  0x08006495:  52           DC.B       0x52                     ; 'R'
+  0x08006496:  65           DC.B       0x65                     ; 'e'
+  0x08006497:  6C           DC.B       0x6C                     ; 'l'
+  0x08006498:  61           DC.B       0x61                     ; 'a'
+  0x08006499:  69           DC.B       0x69                     ; 'i'
+  0x0800649A:  73           DC.B       0x73                     ; 's'
+  0x0800649B:  20           DC.B       0x20                     ; ' '
+  0x0800649C:  6F           DC.B       0x6F                     ; 'o'
+  0x0800649D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800649E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23.157 from PowerPro_lto.o, size=18, align=1

+
+  0x0800649F:  4E           DC.B       0x4E                     ; 'N'
+  0x080064A0:  45           DC.B       0x45                     ; 'E'
+  0x080064A1:  57           DC.B       0x57                     ; 'W'
+  0x080064A2:  5F           DC.B       0x5F                     ; '_'
+  0x080064A3:  53           DC.B       0x53                     ; 'S'
+  0x080064A4:  54           DC.B       0x54                     ; 'T'
+  0x080064A5:  41           DC.B       0x41                     ; 'A'
+  0x080064A6:  54           DC.B       0x54                     ; 'T'
+  0x080064A7:  45           DC.B       0x45                     ; 'E'
+  0x080064A8:  3A           DC.B       0x3A                     ; ':'
+  0x080064A9:  20           DC.B       0x20                     ; ' '
+  0x080064AA:  4F           DC.B       0x4F                     ; 'O'
+  0x080064AB:  56           DC.B       0x56                     ; 'V'
+  0x080064AC:  50           DC.B       0x50                     ; 'P'
+  0x080064AD:  5F           DC.B       0x5F                     ; '_'
+  0x080064AE:  4F           DC.B       0x4F                     ; 'O'
+  0x080064AF:  4E           DC.B       0x4E                     ; 'N'
+  0x080064B0:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.16.172 from PowerPro_lto.o, size=34, align=1

+
+  0x080064B1:  4E           DC.B       0x4E                     ; 'N'
+  0x080064B2:  45           DC.B       0x45                     ; 'E'
+  0x080064B3:  57           DC.B       0x57                     ; 'W'
+  0x080064B4:  5F           DC.B       0x5F                     ; '_'
+  0x080064B5:  53           DC.B       0x53                     ; 'S'
+  0x080064B6:  54           DC.B       0x54                     ; 'T'
+  0x080064B7:  41           DC.B       0x41                     ; 'A'
+  0x080064B8:  54           DC.B       0x54                     ; 'T'
+  0x080064B9:  45           DC.B       0x45                     ; 'E'
+  0x080064BA:  3A           DC.B       0x3A                     ; ':'
+  0x080064BB:  20           DC.B       0x20                     ; ' '
+  0x080064BC:  53           DC.B       0x53                     ; 'S'
+  0x080064BD:  45           DC.B       0x45                     ; 'E'
+  0x080064BE:  43           DC.B       0x43                     ; 'C'
+  0x080064BF:  4F           DC.B       0x4F                     ; 'O'
+  0x080064C0:  4E           DC.B       0x4E                     ; 'N'
+  0x080064C1:  44           DC.B       0x44                     ; 'D'
+  0x080064C2:  41           DC.B       0x41                     ; 'A'
+  0x080064C3:  52           DC.B       0x52                     ; 'R'
+  0x080064C4:  59           DC.B       0x59                     ; 'Y'
+  0x080064C5:  50           DC.B       0x50                     ; 'P'
+  0x080064C6:  52           DC.B       0x52                     ; 'R'
+  0x080064C7:  4F           DC.B       0x4F                     ; 'O'
+  0x080064C8:  54           DC.B       0x54                     ; 'T'
+  0x080064C9:  45           DC.B       0x45                     ; 'E'
+  0x080064CA:  43           DC.B       0x43                     ; 'C'
+  0x080064CB:  54           DC.B       0x54                     ; 'T'
+  0x080064CC:  49           DC.B       0x49                     ; 'I'
+  0x080064CD:  4F           DC.B       0x4F                     ; 'O'
+  0x080064CE:  4E           DC.B       0x4E                     ; 'N'
+  0x080064CF:  5F           DC.B       0x5F                     ; '_'
+  0x080064D0:  4F           DC.B       0x4F                     ; 'O'
+  0x080064D1:  4E           DC.B       0x4E                     ; 'N'
+  0x080064D2:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_day_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=58, align=1

+
+
__SEGGER_RTL_c_locale_day_names:
+  0x080064D3:  53           DC.B       0x53                     ; 'S'
+  0x080064D4:  75           DC.B       0x75                     ; 'u'
+  0x080064D5:  6E           DC.B       0x6E                     ; 'n'
+  0x080064D6:  64           DC.B       0x64                     ; 'd'
+  0x080064D7:  61           DC.B       0x61                     ; 'a'
+  0x080064D8:  79           DC.B       0x79                     ; 'y'
+  0x080064D9:  00           DC.B       0x00                     ; '\0'
+  0x080064DA:  4D           DC.B       0x4D                     ; 'M'
+  0x080064DB:  6F           DC.B       0x6F                     ; 'o'
+  0x080064DC:  6E           DC.B       0x6E                     ; 'n'
+  0x080064DD:  64           DC.B       0x64                     ; 'd'
+  0x080064DE:  61           DC.B       0x61                     ; 'a'
+  0x080064DF:  79           DC.B       0x79                     ; 'y'
+  0x080064E0:  00           DC.B       0x00                     ; '\0'
+  0x080064E1:  54           DC.B       0x54                     ; 'T'
+  0x080064E2:  75           DC.B       0x75                     ; 'u'
+  0x080064E3:  65           DC.B       0x65                     ; 'e'
+  0x080064E4:  73           DC.B       0x73                     ; 's'
+  0x080064E5:  64           DC.B       0x64                     ; 'd'
+  0x080064E6:  61           DC.B       0x61                     ; 'a'
+  0x080064E7:  79           DC.B       0x79                     ; 'y'
+  0x080064E8:  00           DC.B       0x00                     ; '\0'
+  0x080064E9:  57           DC.B       0x57                     ; 'W'
+  0x080064EA:  65           DC.B       0x65                     ; 'e'
+  0x080064EB:  64           DC.B       0x64                     ; 'd'
+  0x080064EC:  6E           DC.B       0x6E                     ; 'n'
+  0x080064ED:  65           DC.B       0x65                     ; 'e'
+  0x080064EE:  73           DC.B       0x73                     ; 's'
+  0x080064EF:  64           DC.B       0x64                     ; 'd'
+  0x080064F0:  61           DC.B       0x61                     ; 'a'
+  0x080064F1:  79           DC.B       0x79                     ; 'y'
+  0x080064F2:  00           DC.B       0x00                     ; '\0'
+  0x080064F3:  54           DC.B       0x54                     ; 'T'
+  0x080064F4:  68           DC.B       0x68                     ; 'h'
+  0x080064F5:  75           DC.B       0x75                     ; 'u'
+  0x080064F6:  72           DC.B       0x72                     ; 'r'
+  0x080064F7:  73           DC.B       0x73                     ; 's'
+  0x080064F8:  64           DC.B       0x64                     ; 'd'
+  0x080064F9:  61           DC.B       0x61                     ; 'a'
+  0x080064FA:  79           DC.B       0x79                     ; 'y'
+  0x080064FB:  00           DC.B       0x00                     ; '\0'
+  0x080064FC:  46           DC.B       0x46                     ; 'F'
+  0x080064FD:  72           DC.B       0x72                     ; 'r'
+  0x080064FE:  69           DC.B       0x69                     ; 'i'
+  0x080064FF:  64           DC.B       0x64                     ; 'd'
+  0x08006500:  61           DC.B       0x61                     ; 'a'
+  0x08006501:  79           DC.B       0x79                     ; 'y'
+  0x08006502:  00           DC.B       0x00                     ; '\0'
+  0x08006503:  53           DC.B       0x53                     ; 'S'
+  0x08006504:  61           DC.B       0x61                     ; 'a'
+  0x08006505:  74           DC.B       0x74                     ; 't'
+  0x08006506:  75           DC.B       0x75                     ; 'u'
+  0x08006507:  72           DC.B       0x72                     ; 'r'
+  0x08006508:  64           DC.B       0x64                     ; 'd'
+  0x08006509:  61           DC.B       0x61                     ; 'a'
+  0x0800650A:  79           DC.B       0x79                     ; 'y'
+  0x0800650B:  00           DC.B       0x00                     ; '\0'
+  0x0800650C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc..L.str from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=2, align=1

+
+  0x0800650D:  43           DC.B       0x43                     ; 'C'
+  0x0800650E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_data_utf8_period from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=2, align=1

+
+
__SEGGER_RTL_data_utf8_period:
+  0x0800650F:  2E           DC.B       0x2E                     ; '.'
+  0x08006510:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.4 from PowerPro_lto.o, size=17, align=1

+
+  0x08006511:  42           DC.B       0x42                     ; 'B'
+  0x08006512:  55           DC.B       0x55                     ; 'U'
+  0x08006513:  54           DC.B       0x54                     ; 'T'
+  0x08006514:  54           DC.B       0x54                     ; 'T'
+  0x08006515:  4F           DC.B       0x4F                     ; 'O'
+  0x08006516:  4E           DC.B       0x4E                     ; 'N'
+  0x08006517:  3A           DC.B       0x3A                     ; ':'
+  0x08006518:  20           DC.B       0x20                     ; ' '
+  0x08006519:  4F           DC.B       0x4F                     ; 'O'
+  0x0800651A:  66           DC.B       0x66                     ; 'f'
+  0x0800651B:  66           DC.B       0x66                     ; 'f'
+  0x0800651C:  20           DC.B       0x20                     ; ' '
+  0x0800651D:  4D           DC.B       0x4D                     ; 'M'
+  0x0800651E:  6F           DC.B       0x6F                     ; 'o'
+  0x0800651F:  64           DC.B       0x64                     ; 'd'
+  0x08006520:  65           DC.B       0x65                     ; 'e'
+  0x08006521:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12 from PowerPro_lto.o, size=25, align=1

+
+  0x08006522:  6D           DC.B       0x6D                     ; 'm'
+  0x08006523:  6F           DC.B       0x6F                     ; 'o'
+  0x08006524:  64           DC.B       0x64                     ; 'd'
+  0x08006525:  65           DC.B       0x65                     ; 'e'
+  0x08006526:  20           DC.B       0x20                     ; ' '
+  0x08006527:  6E           DC.B       0x6E                     ; 'n'
+  0x08006528:  6F           DC.B       0x6F                     ; 'o'
+  0x08006529:  74           DC.B       0x74                     ; 't'
+  0x0800652A:  20           DC.B       0x20                     ; ' '
+  0x0800652B:  79           DC.B       0x79                     ; 'y'
+  0x0800652C:  65           DC.B       0x65                     ; 'e'
+  0x0800652D:  74           DC.B       0x74                     ; 't'
+  0x0800652E:  20           DC.B       0x20                     ; ' '
+  0x0800652F:  69           DC.B       0x69                     ; 'i'
+  0x08006530:  6D           DC.B       0x6D                     ; 'm'
+  0x08006531:  70           DC.B       0x70                     ; 'p'
+  0x08006532:  6C           DC.B       0x6C                     ; 'l'
+  0x08006533:  65           DC.B       0x65                     ; 'e'
+  0x08006534:  6D           DC.B       0x6D                     ; 'm'
+  0x08006535:  65           DC.B       0x65                     ; 'e'
+  0x08006536:  6E           DC.B       0x6E                     ; 'n'
+  0x08006537:  74           DC.B       0x74                     ; 't'
+  0x08006538:  65           DC.B       0x65                     ; 'e'
+  0x08006539:  64           DC.B       0x64                     ; 'd'
+  0x0800653A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.14 from PowerPro_lto.o, size=17, align=1

+
+  0x0800653B:  4A           DC.B       0x4A                     ; 'J'
+  0x0800653C:  75           DC.B       0x75                     ; 'u'
+  0x0800653D:  6D           DC.B       0x6D                     ; 'm'
+  0x0800653E:  70           DC.B       0x70                     ; 'p'
+  0x0800653F:  20           DC.B       0x20                     ; ' '
+  0x08006540:  68           DC.B       0x68                     ; 'h'
+  0x08006541:  61           DC.B       0x61                     ; 'a'
+  0x08006542:  73           DC.B       0x73                     ; 's'
+  0x08006543:  20           DC.B       0x20                     ; ' '
+  0x08006544:  66           DC.B       0x66                     ; 'f'
+  0x08006545:  61           DC.B       0x61                     ; 'a'
+  0x08006546:  69           DC.B       0x69                     ; 'i'
+  0x08006547:  6C           DC.B       0x6C                     ; 'l'
+  0x08006548:  65           DC.B       0x65                     ; 'e'
+  0x08006549:  64           DC.B       0x64                     ; 'd'
+  0x0800654A:  21           DC.B       0x21                     ; '!'
+  0x0800654B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.5 from PowerPro_lto.o, size=17, align=1

+
+  0x0800654C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800654D:  42           DC.B       0x42                     ; 'B'
+  0x0800654E:  20           DC.B       0x20                     ; ' '
+  0x0800654F:  44           DC.B       0x44                     ; 'D'
+  0x08006550:  4D           DC.B       0x4D                     ; 'M'
+  0x08006551:  41           DC.B       0x41                     ; 'A'
+  0x08006552:  20           DC.B       0x20                     ; ' '
+  0x08006553:  45           DC.B       0x45                     ; 'E'
+  0x08006554:  72           DC.B       0x72                     ; 'r'
+  0x08006555:  72           DC.B       0x72                     ; 'r'
+  0x08006556:  6F           DC.B       0x6F                     ; 'o'
+  0x08006557:  72           DC.B       0x72                     ; 'r'
+  0x08006558:  21           DC.B       0x21                     ; '!'
+  0x08006559:  20           DC.B       0x20                     ; ' '
+  0x0800655A:  0A           DC.B       0x0A                     ; '\n'
+  0x0800655B:  0D           DC.B       0x0D                     ; '\r'
+  0x0800655C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.6 from PowerPro_lto.o, size=17, align=1

+
+  0x0800655D:  4D           DC.B       0x4D                     ; 'M'
+  0x0800655E:  42           DC.B       0x42                     ; 'B'
+  0x0800655F:  20           DC.B       0x20                     ; ' '
+  0x08006560:  4F           DC.B       0x4F                     ; 'O'
+  0x08006561:  52           DC.B       0x52                     ; 'R'
+  0x08006562:  45           DC.B       0x45                     ; 'E'
+  0x08006563:  20           DC.B       0x20                     ; ' '
+  0x08006564:  45           DC.B       0x45                     ; 'E'
+  0x08006565:  72           DC.B       0x72                     ; 'r'
+  0x08006566:  72           DC.B       0x72                     ; 'r'
+  0x08006567:  6F           DC.B       0x6F                     ; 'o'
+  0x08006568:  72           DC.B       0x72                     ; 'r'
+  0x08006569:  21           DC.B       0x21                     ; '!'
+  0x0800656A:  20           DC.B       0x20                     ; ' '
+  0x0800656B:  0A           DC.B       0x0A                     ; '\n'
+  0x0800656C:  0D           DC.B       0x0D                     ; '\r'
+  0x0800656D:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.104 from PowerPro_lto.o, size=17, align=1

+
+  0x0800656E:  45           DC.B       0x45                     ; 'E'
+  0x0800656F:  52           DC.B       0x52                     ; 'R'
+  0x08006570:  52           DC.B       0x52                     ; 'R'
+  0x08006571:  4F           DC.B       0x4F                     ; 'O'
+  0x08006572:  52           DC.B       0x52                     ; 'R'
+  0x08006573:  20           DC.B       0x20                     ; ' '
+  0x08006574:  55           DC.B       0x55                     ; 'U'
+  0x08006575:  61           DC.B       0x61                     ; 'a'
+  0x08006576:  72           DC.B       0x72                     ; 'r'
+  0x08006577:  74           DC.B       0x74                     ; 't'
+  0x08006578:  20           DC.B       0x20                     ; ' '
+  0x08006579:  49           DC.B       0x49                     ; 'I'
+  0x0800657A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800657B:  49           DC.B       0x49                     ; 'I'
+  0x0800657C:  54           DC.B       0x54                     ; 'T'
+  0x0800657D:  0D           DC.B       0x0D                     ; '\r'
+  0x0800657E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.118 from PowerPro_lto.o, size=45, align=1

+
+  0x0800657F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006580:  56           DC.B       0x56                     ; 'V'
+  0x08006581:  50           DC.B       0x50                     ; 'P'
+  0x08006582:  5F           DC.B       0x5F                     ; '_'
+  0x08006583:  53           DC.B       0x53                     ; 'S'
+  0x08006584:  4D           DC.B       0x4D                     ; 'M'
+  0x08006585:  5F           DC.B       0x5F                     ; '_'
+  0x08006586:  4F           DC.B       0x4F                     ; 'O'
+  0x08006587:  66           DC.B       0x66                     ; 'f'
+  0x08006588:  66           DC.B       0x66                     ; 'f'
+  0x08006589:  3A           DC.B       0x3A                     ; ':'
+  0x0800658A:  20           DC.B       0x20                     ; ' '
+  0x0800658B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800658C:  45           DC.B       0x45                     ; 'E'
+  0x0800658D:  57           DC.B       0x57                     ; 'W'
+  0x0800658E:  5F           DC.B       0x5F                     ; '_'
+  0x0800658F:  53           DC.B       0x53                     ; 'S'
+  0x08006590:  54           DC.B       0x54                     ; 'T'
+  0x08006591:  41           DC.B       0x41                     ; 'A'
+  0x08006592:  54           DC.B       0x54                     ; 'T'
+  0x08006593:  45           DC.B       0x45                     ; 'E'
+  0x08006594:  3A           DC.B       0x3A                     ; ':'
+  0x08006595:  20           DC.B       0x20                     ; ' '
+  0x08006596:  4C           DC.B       0x4C                     ; 'L'
+  0x08006597:  56           DC.B       0x56                     ; 'V'
+  0x08006598:  50           DC.B       0x50                     ; 'P'
+  0x08006599:  5F           DC.B       0x5F                     ; '_'
+  0x0800659A:  45           DC.B       0x45                     ; 'E'
+  0x0800659B:  52           DC.B       0x52                     ; 'R'
+  0x0800659C:  52           DC.B       0x52                     ; 'R'
+  0x0800659D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800659E:  52           DC.B       0x52                     ; 'R'
+  0x0800659F:  5F           DC.B       0x5F                     ; '_'
+  0x080065A0:  46           DC.B       0x46                     ; 'F'
+  0x080065A1:  41           DC.B       0x41                     ; 'A'
+  0x080065A2:  55           DC.B       0x55                     ; 'U'
+  0x080065A3:  4C           DC.B       0x4C                     ; 'L'
+  0x080065A4:  54           DC.B       0x54                     ; 'T'
+  0x080065A5:  5F           DC.B       0x5F                     ; '_'
+  0x080065A6:  49           DC.B       0x49                     ; 'I'
+  0x080065A7:  4E           DC.B       0x4E                     ; 'N'
+  0x080065A8:  50           DC.B       0x50                     ; 'P'
+  0x080065A9:  55           DC.B       0x55                     ; 'U'
+  0x080065AA:  54           DC.B       0x54                     ; 'T'
+  0x080065AB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15 from PowerPro_lto.o, size=21, align=1

+
+  0x080065AC:  4E           DC.B       0x4E                     ; 'N'
+  0x080065AD:  45           DC.B       0x45                     ; 'E'
+  0x080065AE:  57           DC.B       0x57                     ; 'W'
+  0x080065AF:  5F           DC.B       0x5F                     ; '_'
+  0x080065B0:  53           DC.B       0x53                     ; 'S'
+  0x080065B1:  54           DC.B       0x54                     ; 'T'
+  0x080065B2:  41           DC.B       0x41                     ; 'A'
+  0x080065B3:  54           DC.B       0x54                     ; 'T'
+  0x080065B4:  45           DC.B       0x45                     ; 'E'
+  0x080065B5:  3A           DC.B       0x3A                     ; ':'
+  0x080065B6:  20           DC.B       0x20                     ; ' '
+  0x080065B7:  4C           DC.B       0x4C                     ; 'L'
+  0x080065B8:  56           DC.B       0x56                     ; 'V'
+  0x080065B9:  50           DC.B       0x50                     ; 'P'
+  0x080065BA:  5F           DC.B       0x5F                     ; '_'
+  0x080065BB:  45           DC.B       0x45                     ; 'E'
+  0x080065BC:  52           DC.B       0x52                     ; 'R'
+  0x080065BD:  52           DC.B       0x52                     ; 'R'
+  0x080065BE:  4F           DC.B       0x4F                     ; 'O'
+  0x080065BF:  52           DC.B       0x52                     ; 'R'
+  0x080065C0:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17 from PowerPro_lto.o, size=9, align=1

+
+  0x080065C1:  4C           DC.B       0x4C                     ; 'L'
+  0x080065C2:  56           DC.B       0x56                     ; 'V'
+  0x080065C3:  50           DC.B       0x50                     ; 'P'
+  0x080065C4:  20           DC.B       0x20                     ; ' '
+  0x080065C5:  4F           DC.B       0x4F                     ; 'O'
+  0x080065C6:  46           DC.B       0x46                     ; 'F'
+  0x080065C7:  46           DC.B       0x46                     ; 'F'
+  0x080065C8:  21           DC.B       0x21                     ; '!'
+  0x080065C9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24 from PowerPro_lto.o, size=25, align=1

+
+  0x080065CA:  4E           DC.B       0x4E                     ; 'N'
+  0x080065CB:  45           DC.B       0x45                     ; 'E'
+  0x080065CC:  57           DC.B       0x57                     ; 'W'
+  0x080065CD:  5F           DC.B       0x5F                     ; '_'
+  0x080065CE:  53           DC.B       0x53                     ; 'S'
+  0x080065CF:  54           DC.B       0x54                     ; 'T'
+  0x080065D0:  41           DC.B       0x41                     ; 'A'
+  0x080065D1:  54           DC.B       0x54                     ; 'T'
+  0x080065D2:  45           DC.B       0x45                     ; 'E'
+  0x080065D3:  3A           DC.B       0x3A                     ; ':'
+  0x080065D4:  20           DC.B       0x20                     ; ' '
+  0x080065D5:  4C           DC.B       0x4C                     ; 'L'
+  0x080065D6:  56           DC.B       0x56                     ; 'V'
+  0x080065D7:  50           DC.B       0x50                     ; 'P'
+  0x080065D8:  5F           DC.B       0x5F                     ; '_'
+  0x080065D9:  4D           DC.B       0x4D                     ; 'M'
+  0x080065DA:  41           DC.B       0x41                     ; 'A'
+  0x080065DB:  4E           DC.B       0x4E                     ; 'N'
+  0x080065DC:  55           DC.B       0x55                     ; 'U'
+  0x080065DD:  41           DC.B       0x41                     ; 'A'
+  0x080065DE:  4C           DC.B       0x4C                     ; 'L'
+  0x080065DF:  5F           DC.B       0x5F                     ; '_'
+  0x080065E0:  4F           DC.B       0x4F                     ; 'O'
+  0x080065E1:  4E           DC.B       0x4E                     ; 'N'
+  0x080065E2:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.124 from PowerPro_lto.o, size=53, align=1

+
+  0x080065E3:  4C           DC.B       0x4C                     ; 'L'
+  0x080065E4:  56           DC.B       0x56                     ; 'V'
+  0x080065E5:  50           DC.B       0x50                     ; 'P'
+  0x080065E6:  5F           DC.B       0x5F                     ; '_'
+  0x080065E7:  4F           DC.B       0x4F                     ; 'O'
+  0x080065E8:  56           DC.B       0x56                     ; 'V'
+  0x080065E9:  50           DC.B       0x50                     ; 'P'
+  0x080065EA:  5F           DC.B       0x5F                     ; '_'
+  0x080065EB:  53           DC.B       0x53                     ; 'S'
+  0x080065EC:  4D           DC.B       0x4D                     ; 'M'
+  0x080065ED:  5F           DC.B       0x5F                     ; '_'
+  0x080065EE:  4F           DC.B       0x4F                     ; 'O'
+  0x080065EF:  66           DC.B       0x66                     ; 'f'
+  0x080065F0:  66           DC.B       0x66                     ; 'f'
+  0x080065F1:  3A           DC.B       0x3A                     ; ':'
+  0x080065F2:  20           DC.B       0x20                     ; ' '
+  0x080065F3:  4E           DC.B       0x4E                     ; 'N'
+  0x080065F4:  45           DC.B       0x45                     ; 'E'
+  0x080065F5:  57           DC.B       0x57                     ; 'W'
+  0x080065F6:  5F           DC.B       0x5F                     ; '_'
+  0x080065F7:  53           DC.B       0x53                     ; 'S'
+  0x080065F8:  54           DC.B       0x54                     ; 'T'
+  0x080065F9:  41           DC.B       0x41                     ; 'A'
+  0x080065FA:  54           DC.B       0x54                     ; 'T'
+  0x080065FB:  45           DC.B       0x45                     ; 'E'
+  0x080065FC:  3A           DC.B       0x3A                     ; ':'
+  0x080065FD:  20           DC.B       0x20                     ; ' '
+  0x080065FE:  4C           DC.B       0x4C                     ; 'L'
+  0x080065FF:  56           DC.B       0x56                     ; 'V'
+  0x08006600:  50           DC.B       0x50                     ; 'P'
+  0x08006601:  5F           DC.B       0x5F                     ; '_'
+  0x08006602:  4F           DC.B       0x4F                     ; 'O'
+  0x08006603:  56           DC.B       0x56                     ; 'V'
+  0x08006604:  50           DC.B       0x50                     ; 'P'
+  0x08006605:  5F           DC.B       0x5F                     ; '_'
+  0x08006606:  45           DC.B       0x45                     ; 'E'
+  0x08006607:  52           DC.B       0x52                     ; 'R'
+  0x08006608:  52           DC.B       0x52                     ; 'R'
+  0x08006609:  4F           DC.B       0x4F                     ; 'O'
+  0x0800660A:  52           DC.B       0x52                     ; 'R'
+  0x0800660B:  5F           DC.B       0x5F                     ; '_'
+  0x0800660C:  46           DC.B       0x46                     ; 'F'
+  0x0800660D:  41           DC.B       0x41                     ; 'A'
+  0x0800660E:  55           DC.B       0x55                     ; 'U'
+  0x0800660F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006610:  54           DC.B       0x54                     ; 'T'
+  0x08006611:  5F           DC.B       0x5F                     ; '_'
+  0x08006612:  49           DC.B       0x49                     ; 'I'
+  0x08006613:  4E           DC.B       0x4E                     ; 'N'
+  0x08006614:  50           DC.B       0x50                     ; 'P'
+  0x08006615:  55           DC.B       0x55                     ; 'U'
+  0x08006616:  54           DC.B       0x54                     ; 'T'
+  0x08006617:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.127 from PowerPro_lto.o, size=25, align=1

+
+  0x08006618:  4E           DC.B       0x4E                     ; 'N'
+  0x08006619:  45           DC.B       0x45                     ; 'E'
+  0x0800661A:  57           DC.B       0x57                     ; 'W'
+  0x0800661B:  5F           DC.B       0x5F                     ; '_'
+  0x0800661C:  53           DC.B       0x53                     ; 'S'
+  0x0800661D:  54           DC.B       0x54                     ; 'T'
+  0x0800661E:  41           DC.B       0x41                     ; 'A'
+  0x0800661F:  54           DC.B       0x54                     ; 'T'
+  0x08006620:  45           DC.B       0x45                     ; 'E'
+  0x08006621:  3A           DC.B       0x3A                     ; ':'
+  0x08006622:  20           DC.B       0x20                     ; ' '
+  0x08006623:  4C           DC.B       0x4C                     ; 'L'
+  0x08006624:  56           DC.B       0x56                     ; 'V'
+  0x08006625:  50           DC.B       0x50                     ; 'P'
+  0x08006626:  5F           DC.B       0x5F                     ; '_'
+  0x08006627:  4F           DC.B       0x4F                     ; 'O'
+  0x08006628:  56           DC.B       0x56                     ; 'V'
+  0x08006629:  50           DC.B       0x50                     ; 'P'
+  0x0800662A:  5F           DC.B       0x5F                     ; '_'
+  0x0800662B:  45           DC.B       0x45                     ; 'E'
+  0x0800662C:  52           DC.B       0x52                     ; 'R'
+  0x0800662D:  52           DC.B       0x52                     ; 'R'
+  0x0800662E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800662F:  52           DC.B       0x52                     ; 'R'
+  0x08006630:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24.125 from PowerPro_lto.o, size=29, align=1

+
+  0x08006631:  4E           DC.B       0x4E                     ; 'N'
+  0x08006632:  45           DC.B       0x45                     ; 'E'
+  0x08006633:  57           DC.B       0x57                     ; 'W'
+  0x08006634:  5F           DC.B       0x5F                     ; '_'
+  0x08006635:  53           DC.B       0x53                     ; 'S'
+  0x08006636:  54           DC.B       0x54                     ; 'T'
+  0x08006637:  41           DC.B       0x41                     ; 'A'
+  0x08006638:  54           DC.B       0x54                     ; 'T'
+  0x08006639:  45           DC.B       0x45                     ; 'E'
+  0x0800663A:  3A           DC.B       0x3A                     ; ':'
+  0x0800663B:  20           DC.B       0x20                     ; ' '
+  0x0800663C:  4C           DC.B       0x4C                     ; 'L'
+  0x0800663D:  56           DC.B       0x56                     ; 'V'
+  0x0800663E:  50           DC.B       0x50                     ; 'P'
+  0x0800663F:  5F           DC.B       0x5F                     ; '_'
+  0x08006640:  4F           DC.B       0x4F                     ; 'O'
+  0x08006641:  56           DC.B       0x56                     ; 'V'
+  0x08006642:  50           DC.B       0x50                     ; 'P'
+  0x08006643:  5F           DC.B       0x5F                     ; '_'
+  0x08006644:  4D           DC.B       0x4D                     ; 'M'
+  0x08006645:  41           DC.B       0x41                     ; 'A'
+  0x08006646:  4E           DC.B       0x4E                     ; 'N'
+  0x08006647:  55           DC.B       0x55                     ; 'U'
+  0x08006648:  41           DC.B       0x41                     ; 'A'
+  0x08006649:  4C           DC.B       0x4C                     ; 'L'
+  0x0800664A:  5F           DC.B       0x5F                     ; '_'
+  0x0800664B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800664C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800664D:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11.135 from PowerPro_lto.o, size=25, align=1

+
+  0x0800664E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800664F:  45           DC.B       0x45                     ; 'E'
+  0x08006650:  57           DC.B       0x57                     ; 'W'
+  0x08006651:  5F           DC.B       0x5F                     ; '_'
+  0x08006652:  53           DC.B       0x53                     ; 'S'
+  0x08006653:  54           DC.B       0x54                     ; 'T'
+  0x08006654:  41           DC.B       0x41                     ; 'A'
+  0x08006655:  54           DC.B       0x54                     ; 'T'
+  0x08006656:  45           DC.B       0x45                     ; 'E'
+  0x08006657:  3A           DC.B       0x3A                     ; ':'
+  0x08006658:  20           DC.B       0x20                     ; ' '
+  0x08006659:  4D           DC.B       0x4D                     ; 'M'
+  0x0800665A:  41           DC.B       0x41                     ; 'A'
+  0x0800665B:  49           DC.B       0x49                     ; 'I'
+  0x0800665C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800665D:  53           DC.B       0x53                     ; 'S'
+  0x0800665E:  57           DC.B       0x57                     ; 'W'
+  0x0800665F:  49           DC.B       0x49                     ; 'I'
+  0x08006660:  54           DC.B       0x54                     ; 'T'
+  0x08006661:  43           DC.B       0x43                     ; 'C'
+  0x08006662:  48           DC.B       0x48                     ; 'H'
+  0x08006663:  5F           DC.B       0x5F                     ; '_'
+  0x08006664:  4F           DC.B       0x4F                     ; 'O'
+  0x08006665:  4E           DC.B       0x4E                     ; 'N'
+  0x08006666:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.147 from PowerPro_lto.o, size=45, align=1

+
+  0x08006667:  4F           DC.B       0x4F                     ; 'O'
+  0x08006668:  56           DC.B       0x56                     ; 'V'
+  0x08006669:  50           DC.B       0x50                     ; 'P'
+  0x0800666A:  5F           DC.B       0x5F                     ; '_'
+  0x0800666B:  53           DC.B       0x53                     ; 'S'
+  0x0800666C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800666D:  5F           DC.B       0x5F                     ; '_'
+  0x0800666E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800666F:  66           DC.B       0x66                     ; 'f'
+  0x08006670:  66           DC.B       0x66                     ; 'f'
+  0x08006671:  3A           DC.B       0x3A                     ; ':'
+  0x08006672:  20           DC.B       0x20                     ; ' '
+  0x08006673:  4E           DC.B       0x4E                     ; 'N'
+  0x08006674:  45           DC.B       0x45                     ; 'E'
+  0x08006675:  57           DC.B       0x57                     ; 'W'
+  0x08006676:  5F           DC.B       0x5F                     ; '_'
+  0x08006677:  53           DC.B       0x53                     ; 'S'
+  0x08006678:  54           DC.B       0x54                     ; 'T'
+  0x08006679:  41           DC.B       0x41                     ; 'A'
+  0x0800667A:  54           DC.B       0x54                     ; 'T'
+  0x0800667B:  45           DC.B       0x45                     ; 'E'
+  0x0800667C:  3A           DC.B       0x3A                     ; ':'
+  0x0800667D:  20           DC.B       0x20                     ; ' '
+  0x0800667E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800667F:  56           DC.B       0x56                     ; 'V'
+  0x08006680:  50           DC.B       0x50                     ; 'P'
+  0x08006681:  5F           DC.B       0x5F                     ; '_'
+  0x08006682:  45           DC.B       0x45                     ; 'E'
+  0x08006683:  52           DC.B       0x52                     ; 'R'
+  0x08006684:  52           DC.B       0x52                     ; 'R'
+  0x08006685:  4F           DC.B       0x4F                     ; 'O'
+  0x08006686:  52           DC.B       0x52                     ; 'R'
+  0x08006687:  5F           DC.B       0x5F                     ; '_'
+  0x08006688:  46           DC.B       0x46                     ; 'F'
+  0x08006689:  41           DC.B       0x41                     ; 'A'
+  0x0800668A:  55           DC.B       0x55                     ; 'U'
+  0x0800668B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800668C:  54           DC.B       0x54                     ; 'T'
+  0x0800668D:  5F           DC.B       0x5F                     ; '_'
+  0x0800668E:  49           DC.B       0x49                     ; 'I'
+  0x0800668F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006690:  50           DC.B       0x50                     ; 'P'
+  0x08006691:  55           DC.B       0x55                     ; 'U'
+  0x08006692:  54           DC.B       0x54                     ; 'T'
+  0x08006693:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.150 from PowerPro_lto.o, size=21, align=1

+
+  0x08006694:  4E           DC.B       0x4E                     ; 'N'
+  0x08006695:  45           DC.B       0x45                     ; 'E'
+  0x08006696:  57           DC.B       0x57                     ; 'W'
+  0x08006697:  5F           DC.B       0x5F                     ; '_'
+  0x08006698:  53           DC.B       0x53                     ; 'S'
+  0x08006699:  54           DC.B       0x54                     ; 'T'
+  0x0800669A:  41           DC.B       0x41                     ; 'A'
+  0x0800669B:  54           DC.B       0x54                     ; 'T'
+  0x0800669C:  45           DC.B       0x45                     ; 'E'
+  0x0800669D:  3A           DC.B       0x3A                     ; ':'
+  0x0800669E:  20           DC.B       0x20                     ; ' '
+  0x0800669F:  4F           DC.B       0x4F                     ; 'O'
+  0x080066A0:  56           DC.B       0x56                     ; 'V'
+  0x080066A1:  50           DC.B       0x50                     ; 'P'
+  0x080066A2:  5F           DC.B       0x5F                     ; '_'
+  0x080066A3:  45           DC.B       0x45                     ; 'E'
+  0x080066A4:  52           DC.B       0x52                     ; 'R'
+  0x080066A5:  52           DC.B       0x52                     ; 'R'
+  0x080066A6:  4F           DC.B       0x4F                     ; 'O'
+  0x080066A7:  52           DC.B       0x52                     ; 'R'
+  0x080066A8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17.152 from PowerPro_lto.o, size=9, align=1

+
+  0x080066A9:  4F           DC.B       0x4F                     ; 'O'
+  0x080066AA:  56           DC.B       0x56                     ; 'V'
+  0x080066AB:  50           DC.B       0x50                     ; 'P'
+  0x080066AC:  20           DC.B       0x20                     ; ' '
+  0x080066AD:  4F           DC.B       0x4F                     ; 'O'
+  0x080066AE:  46           DC.B       0x46                     ; 'F'
+  0x080066AF:  46           DC.B       0x46                     ; 'F'
+  0x080066B0:  21           DC.B       0x21                     ; '!'
+  0x080066B1:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24.148 from PowerPro_lto.o, size=25, align=1

+
+  0x080066B2:  4E           DC.B       0x4E                     ; 'N'
+  0x080066B3:  45           DC.B       0x45                     ; 'E'
+  0x080066B4:  57           DC.B       0x57                     ; 'W'
+  0x080066B5:  5F           DC.B       0x5F                     ; '_'
+  0x080066B6:  53           DC.B       0x53                     ; 'S'
+  0x080066B7:  54           DC.B       0x54                     ; 'T'
+  0x080066B8:  41           DC.B       0x41                     ; 'A'
+  0x080066B9:  54           DC.B       0x54                     ; 'T'
+  0x080066BA:  45           DC.B       0x45                     ; 'E'
+  0x080066BB:  3A           DC.B       0x3A                     ; ':'
+  0x080066BC:  20           DC.B       0x20                     ; ' '
+  0x080066BD:  4F           DC.B       0x4F                     ; 'O'
+  0x080066BE:  56           DC.B       0x56                     ; 'V'
+  0x080066BF:  50           DC.B       0x50                     ; 'P'
+  0x080066C0:  5F           DC.B       0x5F                     ; '_'
+  0x080066C1:  4D           DC.B       0x4D                     ; 'M'
+  0x080066C2:  41           DC.B       0x41                     ; 'A'
+  0x080066C3:  4E           DC.B       0x4E                     ; 'N'
+  0x080066C4:  55           DC.B       0x55                     ; 'U'
+  0x080066C5:  41           DC.B       0x41                     ; 'A'
+  0x080066C6:  4C           DC.B       0x4C                     ; 'L'
+  0x080066C7:  5F           DC.B       0x5F                     ; '_'
+  0x080066C8:  4F           DC.B       0x4F                     ; 'O'
+  0x080066C9:  4E           DC.B       0x4E                     ; 'N'
+  0x080066CA:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.162 from PowerPro_lto.o, size=41, align=1

+
+  0x080066CB:  4E           DC.B       0x4E                     ; 'N'
+  0x080066CC:  45           DC.B       0x45                     ; 'E'
+  0x080066CD:  57           DC.B       0x57                     ; 'W'
+  0x080066CE:  5F           DC.B       0x5F                     ; '_'
+  0x080066CF:  53           DC.B       0x53                     ; 'S'
+  0x080066D0:  54           DC.B       0x54                     ; 'T'
+  0x080066D1:  41           DC.B       0x41                     ; 'A'
+  0x080066D2:  54           DC.B       0x54                     ; 'T'
+  0x080066D3:  45           DC.B       0x45                     ; 'E'
+  0x080066D4:  3A           DC.B       0x3A                     ; ':'
+  0x080066D5:  20           DC.B       0x20                     ; ' '
+  0x080066D6:  53           DC.B       0x53                     ; 'S'
+  0x080066D7:  45           DC.B       0x45                     ; 'E'
+  0x080066D8:  43           DC.B       0x43                     ; 'C'
+  0x080066D9:  4F           DC.B       0x4F                     ; 'O'
+  0x080066DA:  4E           DC.B       0x4E                     ; 'N'
+  0x080066DB:  44           DC.B       0x44                     ; 'D'
+  0x080066DC:  41           DC.B       0x41                     ; 'A'
+  0x080066DD:  52           DC.B       0x52                     ; 'R'
+  0x080066DE:  59           DC.B       0x59                     ; 'Y'
+  0x080066DF:  50           DC.B       0x50                     ; 'P'
+  0x080066E0:  52           DC.B       0x52                     ; 'R'
+  0x080066E1:  4F           DC.B       0x4F                     ; 'O'
+  0x080066E2:  54           DC.B       0x54                     ; 'T'
+  0x080066E3:  45           DC.B       0x45                     ; 'E'
+  0x080066E4:  43           DC.B       0x43                     ; 'C'
+  0x080066E5:  54           DC.B       0x54                     ; 'T'
+  0x080066E6:  49           DC.B       0x49                     ; 'I'
+  0x080066E7:  4F           DC.B       0x4F                     ; 'O'
+  0x080066E8:  4E           DC.B       0x4E                     ; 'N'
+  0x080066E9:  5F           DC.B       0x5F                     ; '_'
+  0x080066EA:  4D           DC.B       0x4D                     ; 'M'
+  0x080066EB:  41           DC.B       0x41                     ; 'A'
+  0x080066EC:  4E           DC.B       0x4E                     ; 'N'
+  0x080066ED:  55           DC.B       0x55                     ; 'U'
+  0x080066EE:  41           DC.B       0x41                     ; 'A'
+  0x080066EF:  4C           DC.B       0x4C                     ; 'L'
+  0x080066F0:  5F           DC.B       0x5F                     ; '_'
+  0x080066F1:  4F           DC.B       0x4F                     ; 'O'
+  0x080066F2:  4E           DC.B       0x4E                     ; 'N'
+  0x080066F3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.9.178 from PowerPro_lto.o, size=29, align=1

+
+  0x080066F4:  46           DC.B       0x46                     ; 'F'
+  0x080066F5:  41           DC.B       0x41                     ; 'A'
+  0x080066F6:  55           DC.B       0x55                     ; 'U'
+  0x080066F7:  4C           DC.B       0x4C                     ; 'L'
+  0x080066F8:  54           DC.B       0x54                     ; 'T'
+  0x080066F9:  20           DC.B       0x20                     ; ' '
+  0x080066FA:  56           DC.B       0x56                     ; 'V'
+  0x080066FB:  4F           DC.B       0x4F                     ; 'O'
+  0x080066FC:  4C           DC.B       0x4C                     ; 'L'
+  0x080066FD:  54           DC.B       0x54                     ; 'T'
+  0x080066FE:  41           DC.B       0x41                     ; 'A'
+  0x080066FF:  47           DC.B       0x47                     ; 'G'
+  0x08006700:  45           DC.B       0x45                     ; 'E'
+  0x08006701:  20           DC.B       0x20                     ; ' '
+  0x08006702:  44           DC.B       0x44                     ; 'D'
+  0x08006703:  52           DC.B       0x52                     ; 'R'
+  0x08006704:  4F           DC.B       0x4F                     ; 'O'
+  0x08006705:  50           DC.B       0x50                     ; 'P'
+  0x08006706:  20           DC.B       0x20                     ; ' '
+  0x08006707:  44           DC.B       0x44                     ; 'D'
+  0x08006708:  45           DC.B       0x45                     ; 'E'
+  0x08006709:  54           DC.B       0x54                     ; 'T'
+  0x0800670A:  45           DC.B       0x45                     ; 'E'
+  0x0800670B:  43           DC.B       0x43                     ; 'C'
+  0x0800670C:  54           DC.B       0x54                     ; 'T'
+  0x0800670D:  45           DC.B       0x45                     ; 'E'
+  0x0800670E:  44           DC.B       0x44                     ; 'D'
+  0x0800670F:  21           DC.B       0x21                     ; '!'
+  0x08006710:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.173 from PowerPro_lto.o, size=37, align=1

+
+  0x08006711:  4E           DC.B       0x4E                     ; 'N'
+  0x08006712:  45           DC.B       0x45                     ; 'E'
+  0x08006713:  57           DC.B       0x57                     ; 'W'
+  0x08006714:  5F           DC.B       0x5F                     ; '_'
+  0x08006715:  53           DC.B       0x53                     ; 'S'
+  0x08006716:  54           DC.B       0x54                     ; 'T'
+  0x08006717:  41           DC.B       0x41                     ; 'A'
+  0x08006718:  54           DC.B       0x54                     ; 'T'
+  0x08006719:  45           DC.B       0x45                     ; 'E'
+  0x0800671A:  3A           DC.B       0x3A                     ; ':'
+  0x0800671B:  20           DC.B       0x20                     ; ' '
+  0x0800671C:  53           DC.B       0x53                     ; 'S'
+  0x0800671D:  45           DC.B       0x45                     ; 'E'
+  0x0800671E:  43           DC.B       0x43                     ; 'C'
+  0x0800671F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006720:  4E           DC.B       0x4E                     ; 'N'
+  0x08006721:  44           DC.B       0x44                     ; 'D'
+  0x08006722:  41           DC.B       0x41                     ; 'A'
+  0x08006723:  52           DC.B       0x52                     ; 'R'
+  0x08006724:  59           DC.B       0x59                     ; 'Y'
+  0x08006725:  50           DC.B       0x50                     ; 'P'
+  0x08006726:  52           DC.B       0x52                     ; 'R'
+  0x08006727:  4F           DC.B       0x4F                     ; 'O'
+  0x08006728:  54           DC.B       0x54                     ; 'T'
+  0x08006729:  45           DC.B       0x45                     ; 'E'
+  0x0800672A:  43           DC.B       0x43                     ; 'C'
+  0x0800672B:  54           DC.B       0x54                     ; 'T'
+  0x0800672C:  49           DC.B       0x49                     ; 'I'
+  0x0800672D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800672E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800672F:  5F           DC.B       0x5F                     ; '_'
+  0x08006730:  45           DC.B       0x45                     ; 'E'
+  0x08006731:  52           DC.B       0x52                     ; 'R'
+  0x08006732:  52           DC.B       0x52                     ; 'R'
+  0x08006733:  4F           DC.B       0x4F                     ; 'O'
+  0x08006734:  52           DC.B       0x52                     ; 'R'
+  0x08006735:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str from PowerPro_lto.o, size=9, align=1

+
+  0x08006736:  6D           DC.B       0x6D                     ; 'm'
+  0x08006737:  6F           DC.B       0x6F                     ; 'o'
+  0x08006738:  64           DC.B       0x64                     ; 'd'
+  0x08006739:  65           DC.B       0x65                     ; 'e'
+  0x0800673A:  3D           DC.B       0x3D                     ; '='
+  0x0800673B:  25           DC.B       0x25                     ; '%'
+  0x0800673C:  69           DC.B       0x69                     ; 'i'
+  0x0800673D:  0A           DC.B       0x0A                     ; '\n'
+  0x0800673E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc._DoInit._aInitStr from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=17, align=1

+
+
_DoInit._aInitStr:
+  0x0800673F:  00           DC.B       0x00                     ; '\0'
+  0x08006740:  00           DC.B       0x00                     ; '\0'
+  0x08006741:  00           DC.B       0x00                     ; '\0'
+  0x08006742:  00           DC.B       0x00                     ; '\0'
+  0x08006743:  00           DC.B       0x00                     ; '\0'
+  0x08006744:  00           DC.B       0x00                     ; '\0'
+  0x08006745:  54           DC.B       0x54                     ; 'T'
+  0x08006746:  54           DC.B       0x54                     ; 'T'
+  0x08006747:  52           DC.B       0x52                     ; 'R'
+  0x08006748:  20           DC.B       0x20                     ; ' '
+  0x08006749:  52           DC.B       0x52                     ; 'R'
+  0x0800674A:  45           DC.B       0x45                     ; 'E'
+  0x0800674B:  47           DC.B       0x47                     ; 'G'
+  0x0800674C:  47           DC.B       0x47                     ; 'G'
+  0x0800674D:  45           DC.B       0x45                     ; 'E'
+  0x0800674E:  53           DC.B       0x53                     ; 'S'
+  0x0800674F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc..L.str from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=9, align=1

+
+  0x08006750:  54           DC.B       0x54                     ; 'T'
+  0x08006751:  65           DC.B       0x65                     ; 'e'
+  0x08006752:  72           DC.B       0x72                     ; 'r'
+  0x08006753:  6D           DC.B       0x6D                     ; 'm'
+  0x08006754:  69           DC.B       0x69                     ; 'i'
+  0x08006755:  6E           DC.B       0x6E                     ; 'n'
+  0x08006756:  61           DC.B       0x61                     ; 'a'
+  0x08006757:  6C           DC.B       0x6C                     ; 'l'
+  0x08006758:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_date_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=9, align=1

+
+
__SEGGER_RTL_c_locale_date_format:
+  0x08006759:  25           DC.B       0x25                     ; '%'
+  0x0800675A:  6D           DC.B       0x6D                     ; 'm'
+  0x0800675B:  2F           DC.B       0x2F                     ; '/'
+  0x0800675C:  25           DC.B       0x25                     ; '%'
+  0x0800675D:  64           DC.B       0x64                     ; 'd'
+  0x0800675E:  2F           DC.B       0x2F                     ; '/'
+  0x0800675F:  25           DC.B       0x25                     ; '%'
+  0x08006760:  79           DC.B       0x79                     ; 'y'
+  0x08006761:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_time_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=9, align=1

+
+
__SEGGER_RTL_c_locale_time_format:
+  0x08006762:  25           DC.B       0x25                     ; '%'
+  0x08006763:  48           DC.B       0x48                     ; 'H'
+  0x08006764:  3A           DC.B       0x3A                     ; ':'
+  0x08006765:  25           DC.B       0x25                     ; '%'
+  0x08006766:  4D           DC.B       0x4D                     ; 'M'
+  0x08006767:  3A           DC.B       0x3A                     ; ':'
+  0x08006768:  25           DC.B       0x25                     ; '%'
+  0x08006769:  53           DC.B       0x53                     ; 'S'
+  0x0800676A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_abbrev_day_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=29, align=1

+
+
__SEGGER_RTL_c_locale_abbrev_day_names:
+  0x0800676B:  53           DC.B       0x53                     ; 'S'
+  0x0800676C:  75           DC.B       0x75                     ; 'u'
+  0x0800676D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800676E:  00           DC.B       0x00                     ; '\0'
+  0x0800676F:  4D           DC.B       0x4D                     ; 'M'
+  0x08006770:  6F           DC.B       0x6F                     ; 'o'
+  0x08006771:  6E           DC.B       0x6E                     ; 'n'
+  0x08006772:  00           DC.B       0x00                     ; '\0'
+  0x08006773:  54           DC.B       0x54                     ; 'T'
+  0x08006774:  75           DC.B       0x75                     ; 'u'
+  0x08006775:  65           DC.B       0x65                     ; 'e'
+  0x08006776:  00           DC.B       0x00                     ; '\0'
+  0x08006777:  57           DC.B       0x57                     ; 'W'
+  0x08006778:  65           DC.B       0x65                     ; 'e'
+  0x08006779:  64           DC.B       0x64                     ; 'd'
+  0x0800677A:  00           DC.B       0x00                     ; '\0'
+  0x0800677B:  54           DC.B       0x54                     ; 'T'
+  0x0800677C:  68           DC.B       0x68                     ; 'h'
+  0x0800677D:  75           DC.B       0x75                     ; 'u'
+  0x0800677E:  00           DC.B       0x00                     ; '\0'
+  0x0800677F:  46           DC.B       0x46                     ; 'F'
+  0x08006780:  72           DC.B       0x72                     ; 'r'
+  0x08006781:  69           DC.B       0x69                     ; 'i'
+  0x08006782:  00           DC.B       0x00                     ; '\0'
+  0x08006783:  53           DC.B       0x53                     ; 'S'
+  0x08006784:  61           DC.B       0x61                     ; 'a'
+  0x08006785:  74           DC.B       0x74                     ; 't'
+  0x08006786:  00           DC.B       0x00                     ; '\0'
+  0x08006787:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_abbrev_month_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=49, align=1

+
+
__SEGGER_RTL_c_locale_abbrev_month_names:
+  0x08006788:  4A           DC.B       0x4A                     ; 'J'
+  0x08006789:  61           DC.B       0x61                     ; 'a'
+  0x0800678A:  6E           DC.B       0x6E                     ; 'n'
+  0x0800678B:  00           DC.B       0x00                     ; '\0'
+  0x0800678C:  46           DC.B       0x46                     ; 'F'
+  0x0800678D:  65           DC.B       0x65                     ; 'e'
+  0x0800678E:  62           DC.B       0x62                     ; 'b'
+  0x0800678F:  00           DC.B       0x00                     ; '\0'
+  0x08006790:  4D           DC.B       0x4D                     ; 'M'
+  0x08006791:  61           DC.B       0x61                     ; 'a'
+  0x08006792:  72           DC.B       0x72                     ; 'r'
+  0x08006793:  00           DC.B       0x00                     ; '\0'
+  0x08006794:  41           DC.B       0x41                     ; 'A'
+  0x08006795:  70           DC.B       0x70                     ; 'p'
+  0x08006796:  72           DC.B       0x72                     ; 'r'
+  0x08006797:  00           DC.B       0x00                     ; '\0'
+  0x08006798:  4D           DC.B       0x4D                     ; 'M'
+  0x08006799:  61           DC.B       0x61                     ; 'a'
+  0x0800679A:  79           DC.B       0x79                     ; 'y'
+  0x0800679B:  00           DC.B       0x00                     ; '\0'
+  0x0800679C:  4A           DC.B       0x4A                     ; 'J'
+  0x0800679D:  75           DC.B       0x75                     ; 'u'
+  0x0800679E:  6E           DC.B       0x6E                     ; 'n'
+  0x0800679F:  00           DC.B       0x00                     ; '\0'
+  0x080067A0:  4A           DC.B       0x4A                     ; 'J'
+  0x080067A1:  75           DC.B       0x75                     ; 'u'
+  0x080067A2:  6C           DC.B       0x6C                     ; 'l'
+  0x080067A3:  00           DC.B       0x00                     ; '\0'
+  0x080067A4:  41           DC.B       0x41                     ; 'A'
+  0x080067A5:  75           DC.B       0x75                     ; 'u'
+  0x080067A6:  67           DC.B       0x67                     ; 'g'
+  0x080067A7:  00           DC.B       0x00                     ; '\0'
+  0x080067A8:  53           DC.B       0x53                     ; 'S'
+  0x080067A9:  65           DC.B       0x65                     ; 'e'
+  0x080067AA:  70           DC.B       0x70                     ; 'p'
+  0x080067AB:  00           DC.B       0x00                     ; '\0'
+  0x080067AC:  4F           DC.B       0x4F                     ; 'O'
+  0x080067AD:  63           DC.B       0x63                     ; 'c'
+  0x080067AE:  74           DC.B       0x74                     ; 't'
+  0x080067AF:  00           DC.B       0x00                     ; '\0'
+  0x080067B0:  4E           DC.B       0x4E                     ; 'N'
+  0x080067B1:  6F           DC.B       0x6F                     ; 'o'
+  0x080067B2:  76           DC.B       0x76                     ; 'v'
+  0x080067B3:  00           DC.B       0x00                     ; '\0'
+  0x080067B4:  44           DC.B       0x44                     ; 'D'
+  0x080067B5:  65           DC.B       0x65                     ; 'e'
+  0x080067B6:  63           DC.B       0x63                     ; 'c'
+  0x080067B7:  00           DC.B       0x00                     ; '\0'
+  0x080067B8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_data_empty_string from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=1, align=1

+
+
__SEGGER_RTL_data_empty_string:
+  0x080067B9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_ascii_ctype_mask from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=13, align=1

+
+
__SEGGER_RTL_ascii_ctype_mask:
+  0x080067BA:  00           DC.B       0x00                     ; '\0'
+  0x080067BB:  07           DC.B       0x07                     ; '\x07'
+  0x080067BC:  03           DC.B       0x03                     ; '\x03'
+  0x080067BD:  20           DC.B       0x20                     ; ' '
+  0x080067BE:  04           DC.B       0x04                     ; '\x04'
+  0x080067BF:  17           DC.B       0x17                     ; '\x17'
+  0x080067C0:  02           DC.B       0x02                     ; '\x02'
+  0x080067C1:  01           DC.B       0x01                     ; '\x01'
+  0x080067C2:  08           DC.B       0x08                     ; '\b'
+  0x080067C3:  57           DC.B       0x57                     ; 'W'
+  0x080067C4:  10           DC.B       0x10                     ; '\x10'
+  0x080067C5:  40           DC.B       0x40                     ; '@'
+  0x080067C6:  80           DC.B       0x80                     ; '\x80'
+
+

Section .init_array from STM32C0xx_Startup.o, size=4, align=4

+
+  0x080067C8:  08000605     DC.W       SystemCoreClockUpdate
+
+

Section .rodata.UARTEx_SetNbDataToProcess.numerator from PowerPro_lto.o, size=8, align=1

+
+
UARTEx_SetNbDataToProcess.numerator:
+  0x080067CC:  01           DC.B       0x01                     ; '\x01'
+  0x080067CD:  01           DC.B       0x01                     ; '\x01'
+  0x080067CE:  01           DC.B       0x01                     ; '\x01'
+  0x080067CF:  03           DC.B       0x03                     ; '\x03'
+  0x080067D0:  07           DC.B       0x07                     ; '\x07'
+  0x080067D1:  01           DC.B       0x01                     ; '\x01'
+  0x080067D2:  00           DC.B       0x00                     ; '\0'
+  0x080067D3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.UARTEx_SetNbDataToProcess.denominator from PowerPro_lto.o, size=8, align=1

+
+
UARTEx_SetNbDataToProcess.denominator:
+  0x080067D4:  08           DC.B       0x08                     ; '\b'
+  0x080067D5:  04           DC.B       0x04                     ; '\x04'
+  0x080067D6:  02           DC.B       0x02                     ; '\x02'
+  0x080067D7:  04           DC.B       0x04                     ; '\x04'
+  0x080067D8:  08           DC.B       0x08                     ; '\b'
+  0x080067D9:  01           DC.B       0x01                     ; '\x01'
+  0x080067DA:  01           DC.B       0x01                     ; '\x01'
+  0x080067DB:  01           DC.B       0x01                     ; '\x01'
+
+

Section .rodata..Lstr.3 from PowerPro_lto.o, size=28, align=1

+
+  0x080067DC:  42           DC.B       0x42                     ; 'B'
+  0x080067DD:  55           DC.B       0x55                     ; 'U'
+  0x080067DE:  54           DC.B       0x54                     ; 'T'
+  0x080067DF:  54           DC.B       0x54                     ; 'T'
+  0x080067E0:  4F           DC.B       0x4F                     ; 'O'
+  0x080067E1:  4E           DC.B       0x4E                     ; 'N'
+  0x080067E2:  3A           DC.B       0x3A                     ; ':'
+  0x080067E3:  20           DC.B       0x20                     ; ' '
+  0x080067E4:  41           DC.B       0x41                     ; 'A'
+  0x080067E5:  75           DC.B       0x75                     ; 'u'
+  0x080067E6:  74           DC.B       0x74                     ; 't'
+  0x080067E7:  6F           DC.B       0x6F                     ; 'o'
+  0x080067E8:  20           DC.B       0x20                     ; ' '
+  0x080067E9:  4D           DC.B       0x4D                     ; 'M'
+  0x080067EA:  6F           DC.B       0x6F                     ; 'o'
+  0x080067EB:  64           DC.B       0x64                     ; 'd'
+  0x080067EC:  65           DC.B       0x65                     ; 'e'
+  0x080067ED:  20           DC.B       0x20                     ; ' '
+  0x080067EE:  4D           DC.B       0x4D                     ; 'M'
+  0x080067EF:  61           DC.B       0x61                     ; 'a'
+  0x080067F0:  6E           DC.B       0x6E                     ; 'n'
+  0x080067F1:  75           DC.B       0x75                     ; 'u'
+  0x080067F2:  61           DC.B       0x61                     ; 'a'
+  0x080067F3:  6C           DC.B       0x6C                     ; 'l'
+  0x080067F4:  20           DC.B       0x20                     ; ' '
+  0x080067F5:  4F           DC.B       0x4F                     ; 'O'
+  0x080067F6:  6E           DC.B       0x6E                     ; 'n'
+  0x080067F7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11 from PowerPro_lto.o, size=20, align=1

+
+  0x080067F8:  64           DC.B       0x64                     ; 'd'
+  0x080067F9:  65           DC.B       0x65                     ; 'e'
+  0x080067FA:  62           DC.B       0x62                     ; 'b'
+  0x080067FB:  75           DC.B       0x75                     ; 'u'
+  0x080067FC:  67           DC.B       0x67                     ; 'g'
+  0x080067FD:  20           DC.B       0x20                     ; ' '
+  0x080067FE:  69           DC.B       0x69                     ; 'i'
+  0x080067FF:  6F           DC.B       0x6F                     ; 'o'
+  0x08006800:  20           DC.B       0x20                     ; ' '
+  0x08006801:  74           DC.B       0x74                     ; 't'
+  0x08006802:  65           DC.B       0x65                     ; 'e'
+  0x08006803:  73           DC.B       0x73                     ; 's'
+  0x08006804:  74           DC.B       0x74                     ; 't'
+  0x08006805:  2E           DC.B       0x2E                     ; '.'
+  0x08006806:  2E           DC.B       0x2E                     ; '.'
+  0x08006807:  2E           DC.B       0x2E                     ; '.'
+  0x08006808:  6F           DC.B       0x6F                     ; 'o'
+  0x08006809:  6B           DC.B       0x6B                     ; 'k'
+  0x0800680A:  0D           DC.B       0x0D                     ; '\r'
+  0x0800680B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.13 from PowerPro_lto.o, size=16, align=1

+
+  0x0800680C:  55           DC.B       0x55                     ; 'U'
+  0x0800680D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800680E:  4B           DC.B       0x4B                     ; 'K'
+  0x0800680F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006810:  4F           DC.B       0x4F                     ; 'O'
+  0x08006811:  57           DC.B       0x57                     ; 'W'
+  0x08006812:  4E           DC.B       0x4E                     ; 'N'
+  0x08006813:  20           DC.B       0x20                     ; ' '
+  0x08006814:  43           DC.B       0x43                     ; 'C'
+  0x08006815:  4F           DC.B       0x4F                     ; 'O'
+  0x08006816:  4D           DC.B       0x4D                     ; 'M'
+  0x08006817:  4D           DC.B       0x4D                     ; 'M'
+  0x08006818:  41           DC.B       0x41                     ; 'A'
+  0x08006819:  4E           DC.B       0x4E                     ; 'N'
+  0x0800681A:  44           DC.B       0x44                     ; 'D'
+  0x0800681B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.2 from PowerPro_lto.o, size=16, align=1

+
+  0x0800681C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800681D:  42           DC.B       0x42                     ; 'B'
+  0x0800681E:  20           DC.B       0x20                     ; ' '
+  0x0800681F:  46           DC.B       0x46                     ; 'F'
+  0x08006820:  45           DC.B       0x45                     ; 'E'
+  0x08006821:  20           DC.B       0x20                     ; ' '
+  0x08006822:  45           DC.B       0x45                     ; 'E'
+  0x08006823:  72           DC.B       0x72                     ; 'r'
+  0x08006824:  72           DC.B       0x72                     ; 'r'
+  0x08006825:  6F           DC.B       0x6F                     ; 'o'
+  0x08006826:  72           DC.B       0x72                     ; 'r'
+  0x08006827:  21           DC.B       0x21                     ; '!'
+  0x08006828:  20           DC.B       0x20                     ; ' '
+  0x08006829:  0A           DC.B       0x0A                     ; '\n'
+  0x0800682A:  0D           DC.B       0x0D                     ; '\r'
+  0x0800682B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.3 from PowerPro_lto.o, size=16, align=1

+
+  0x0800682C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800682D:  42           DC.B       0x42                     ; 'B'
+  0x0800682E:  20           DC.B       0x20                     ; ' '
+  0x0800682F:  50           DC.B       0x50                     ; 'P'
+  0x08006830:  45           DC.B       0x45                     ; 'E'
+  0x08006831:  20           DC.B       0x20                     ; ' '
+  0x08006832:  45           DC.B       0x45                     ; 'E'
+  0x08006833:  72           DC.B       0x72                     ; 'r'
+  0x08006834:  72           DC.B       0x72                     ; 'r'
+  0x08006835:  6F           DC.B       0x6F                     ; 'o'
+  0x08006836:  72           DC.B       0x72                     ; 'r'
+  0x08006837:  21           DC.B       0x21                     ; '!'
+  0x08006838:  20           DC.B       0x20                     ; ' '
+  0x08006839:  0A           DC.B       0x0A                     ; '\n'
+  0x0800683A:  0D           DC.B       0x0D                     ; '\r'
+  0x0800683B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.4 from PowerPro_lto.o, size=16, align=1

+
+  0x0800683C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800683D:  42           DC.B       0x42                     ; 'B'
+  0x0800683E:  20           DC.B       0x20                     ; ' '
+  0x0800683F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006840:  45           DC.B       0x45                     ; 'E'
+  0x08006841:  20           DC.B       0x20                     ; ' '
+  0x08006842:  45           DC.B       0x45                     ; 'E'
+  0x08006843:  72           DC.B       0x72                     ; 'r'
+  0x08006844:  72           DC.B       0x72                     ; 'r'
+  0x08006845:  6F           DC.B       0x6F                     ; 'o'
+  0x08006846:  72           DC.B       0x72                     ; 'r'
+  0x08006847:  21           DC.B       0x21                     ; '!'
+  0x08006848:  20           DC.B       0x20                     ; ' '
+  0x08006849:  0A           DC.B       0x0A                     ; '\n'
+  0x0800684A:  0D           DC.B       0x0D                     ; '\r'
+  0x0800684B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19 from PowerPro_lto.o, size=8, align=1

+
+  0x0800684C:  4C           DC.B       0x4C                     ; 'L'
+  0x0800684D:  56           DC.B       0x56                     ; 'V'
+  0x0800684E:  50           DC.B       0x50                     ; 'P'
+  0x0800684F:  20           DC.B       0x20                     ; ' '
+  0x08006850:  4F           DC.B       0x4F                     ; 'O'
+  0x08006851:  4E           DC.B       0x4E                     ; 'N'
+  0x08006852:  21           DC.B       0x21                     ; '!'
+  0x08006853:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17.129 from PowerPro_lto.o, size=16, align=1

+
+  0x08006854:  4C           DC.B       0x4C                     ; 'L'
+  0x08006855:  56           DC.B       0x56                     ; 'V'
+  0x08006856:  50           DC.B       0x50                     ; 'P'
+  0x08006857:  20           DC.B       0x20                     ; ' '
+  0x08006858:  4F           DC.B       0x4F                     ; 'O'
+  0x08006859:  52           DC.B       0x52                     ; 'R'
+  0x0800685A:  20           DC.B       0x20                     ; ' '
+  0x0800685B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800685C:  56           DC.B       0x56                     ; 'V'
+  0x0800685D:  50           DC.B       0x50                     ; 'P'
+  0x0800685E:  20           DC.B       0x20                     ; ' '
+  0x0800685F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006860:  46           DC.B       0x46                     ; 'F'
+  0x08006861:  46           DC.B       0x46                     ; 'F'
+  0x08006862:  21           DC.B       0x21                     ; '!'
+  0x08006863:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19.131 from PowerPro_lto.o, size=16, align=1

+
+  0x08006864:  4C           DC.B       0x4C                     ; 'L'
+  0x08006865:  56           DC.B       0x56                     ; 'V'
+  0x08006866:  50           DC.B       0x50                     ; 'P'
+  0x08006867:  20           DC.B       0x20                     ; ' '
+  0x08006868:  41           DC.B       0x41                     ; 'A'
+  0x08006869:  4E           DC.B       0x4E                     ; 'N'
+  0x0800686A:  44           DC.B       0x44                     ; 'D'
+  0x0800686B:  20           DC.B       0x20                     ; ' '
+  0x0800686C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800686D:  56           DC.B       0x56                     ; 'V'
+  0x0800686E:  50           DC.B       0x50                     ; 'P'
+  0x0800686F:  20           DC.B       0x20                     ; ' '
+  0x08006870:  4F           DC.B       0x4F                     ; 'O'
+  0x08006871:  4E           DC.B       0x4E                     ; 'N'
+  0x08006872:  21           DC.B       0x21                     ; '!'
+  0x08006873:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8.136 from PowerPro_lto.o, size=28, align=1

+
+  0x08006874:  4E           DC.B       0x4E                     ; 'N'
+  0x08006875:  45           DC.B       0x45                     ; 'E'
+  0x08006876:  57           DC.B       0x57                     ; 'W'
+  0x08006877:  5F           DC.B       0x5F                     ; '_'
+  0x08006878:  53           DC.B       0x53                     ; 'S'
+  0x08006879:  54           DC.B       0x54                     ; 'T'
+  0x0800687A:  41           DC.B       0x41                     ; 'A'
+  0x0800687B:  54           DC.B       0x54                     ; 'T'
+  0x0800687C:  45           DC.B       0x45                     ; 'E'
+  0x0800687D:  3A           DC.B       0x3A                     ; ':'
+  0x0800687E:  20           DC.B       0x20                     ; ' '
+  0x0800687F:  4D           DC.B       0x4D                     ; 'M'
+  0x08006880:  41           DC.B       0x41                     ; 'A'
+  0x08006881:  49           DC.B       0x49                     ; 'I'
+  0x08006882:  4E           DC.B       0x4E                     ; 'N'
+  0x08006883:  53           DC.B       0x53                     ; 'S'
+  0x08006884:  57           DC.B       0x57                     ; 'W'
+  0x08006885:  49           DC.B       0x49                     ; 'I'
+  0x08006886:  54           DC.B       0x54                     ; 'T'
+  0x08006887:  43           DC.B       0x43                     ; 'C'
+  0x08006888:  48           DC.B       0x48                     ; 'H'
+  0x08006889:  5F           DC.B       0x5F                     ; '_'
+  0x0800688A:  45           DC.B       0x45                     ; 'E'
+  0x0800688B:  52           DC.B       0x52                     ; 'R'
+  0x0800688C:  52           DC.B       0x52                     ; 'R'
+  0x0800688D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800688E:  52           DC.B       0x52                     ; 'R'
+  0x0800688F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.138 from PowerPro_lto.o, size=32, align=1

+
+  0x08006890:  4E           DC.B       0x4E                     ; 'N'
+  0x08006891:  45           DC.B       0x45                     ; 'E'
+  0x08006892:  57           DC.B       0x57                     ; 'W'
+  0x08006893:  5F           DC.B       0x5F                     ; '_'
+  0x08006894:  53           DC.B       0x53                     ; 'S'
+  0x08006895:  54           DC.B       0x54                     ; 'T'
+  0x08006896:  41           DC.B       0x41                     ; 'A'
+  0x08006897:  54           DC.B       0x54                     ; 'T'
+  0x08006898:  45           DC.B       0x45                     ; 'E'
+  0x08006899:  3A           DC.B       0x3A                     ; ':'
+  0x0800689A:  20           DC.B       0x20                     ; ' '
+  0x0800689B:  4D           DC.B       0x4D                     ; 'M'
+  0x0800689C:  41           DC.B       0x41                     ; 'A'
+  0x0800689D:  49           DC.B       0x49                     ; 'I'
+  0x0800689E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800689F:  53           DC.B       0x53                     ; 'S'
+  0x080068A0:  57           DC.B       0x57                     ; 'W'
+  0x080068A1:  49           DC.B       0x49                     ; 'I'
+  0x080068A2:  54           DC.B       0x54                     ; 'T'
+  0x080068A3:  43           DC.B       0x43                     ; 'C'
+  0x080068A4:  48           DC.B       0x48                     ; 'H'
+  0x080068A5:  5F           DC.B       0x5F                     ; '_'
+  0x080068A6:  4D           DC.B       0x4D                     ; 'M'
+  0x080068A7:  41           DC.B       0x41                     ; 'A'
+  0x080068A8:  4E           DC.B       0x4E                     ; 'N'
+  0x080068A9:  55           DC.B       0x55                     ; 'U'
+  0x080068AA:  41           DC.B       0x41                     ; 'A'
+  0x080068AB:  4C           DC.B       0x4C                     ; 'L'
+  0x080068AC:  5F           DC.B       0x5F                     ; '_'
+  0x080068AD:  4F           DC.B       0x4F                     ; 'O'
+  0x080068AE:  4E           DC.B       0x4E                     ; 'N'
+  0x080068AF:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19.154 from PowerPro_lto.o, size=8, align=1

+
+  0x080068B0:  4F           DC.B       0x4F                     ; 'O'
+  0x080068B1:  56           DC.B       0x56                     ; 'V'
+  0x080068B2:  50           DC.B       0x50                     ; 'P'
+  0x080068B3:  20           DC.B       0x20                     ; ' '
+  0x080068B4:  4F           DC.B       0x4F                     ; 'O'
+  0x080068B5:  4E           DC.B       0x4E                     ; 'N'
+  0x080068B6:  21           DC.B       0x21                     ; '!'
+  0x080068B7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11.179 from PowerPro_lto.o, size=60, align=1

+
+  0x080068B8:  42           DC.B       0x42                     ; 'B'
+  0x080068B9:  4D           DC.B       0x4D                     ; 'M'
+  0x080068BA:  53           DC.B       0x53                     ; 'S'
+  0x080068BB:  20           DC.B       0x20                     ; ' '
+  0x080068BC:  53           DC.B       0x53                     ; 'S'
+  0x080068BD:  45           DC.B       0x45                     ; 'E'
+  0x080068BE:  43           DC.B       0x43                     ; 'C'
+  0x080068BF:  4F           DC.B       0x4F                     ; 'O'
+  0x080068C0:  4E           DC.B       0x4E                     ; 'N'
+  0x080068C1:  44           DC.B       0x44                     ; 'D'
+  0x080068C2:  41           DC.B       0x41                     ; 'A'
+  0x080068C3:  52           DC.B       0x52                     ; 'R'
+  0x080068C4:  59           DC.B       0x59                     ; 'Y'
+  0x080068C5:  20           DC.B       0x20                     ; ' '
+  0x080068C6:  50           DC.B       0x50                     ; 'P'
+  0x080068C7:  52           DC.B       0x52                     ; 'R'
+  0x080068C8:  4F           DC.B       0x4F                     ; 'O'
+  0x080068C9:  54           DC.B       0x54                     ; 'T'
+  0x080068CA:  45           DC.B       0x45                     ; 'E'
+  0x080068CB:  43           DC.B       0x43                     ; 'C'
+  0x080068CC:  54           DC.B       0x54                     ; 'T'
+  0x080068CD:  49           DC.B       0x49                     ; 'I'
+  0x080068CE:  4F           DC.B       0x4F                     ; 'O'
+  0x080068CF:  4E           DC.B       0x4E                     ; 'N'
+  0x080068D0:  20           DC.B       0x20                     ; ' '
+  0x080068D1:  46           DC.B       0x46                     ; 'F'
+  0x080068D2:  41           DC.B       0x41                     ; 'A'
+  0x080068D3:  55           DC.B       0x55                     ; 'U'
+  0x080068D4:  4C           DC.B       0x4C                     ; 'L'
+  0x080068D5:  54           DC.B       0x54                     ; 'T'
+  0x080068D6:  20           DC.B       0x20                     ; ' '
+  0x080068D7:  45           DC.B       0x45                     ; 'E'
+  0x080068D8:  56           DC.B       0x56                     ; 'V'
+  0x080068D9:  45           DC.B       0x45                     ; 'E'
+  0x080068DA:  4E           DC.B       0x4E                     ; 'N'
+  0x080068DB:  54           DC.B       0x54                     ; 'T'
+  0x080068DC:  20           DC.B       0x20                     ; ' '
+  0x080068DD:  44           DC.B       0x44                     ; 'D'
+  0x080068DE:  45           DC.B       0x45                     ; 'E'
+  0x080068DF:  54           DC.B       0x54                     ; 'T'
+  0x080068E0:  45           DC.B       0x45                     ; 'E'
+  0x080068E1:  43           DC.B       0x43                     ; 'C'
+  0x080068E2:  54           DC.B       0x54                     ; 'T'
+  0x080068E3:  45           DC.B       0x45                     ; 'E'
+  0x080068E4:  44           DC.B       0x44                     ; 'D'
+  0x080068E5:  20           DC.B       0x20                     ; ' '
+  0x080068E6:  28           DC.B       0x28                     ; '('
+  0x080068E7:  4C           DC.B       0x4C                     ; 'L'
+  0x080068E8:  56           DC.B       0x56                     ; 'V'
+  0x080068E9:  50           DC.B       0x50                     ; 'P'
+  0x080068EA:  20           DC.B       0x20                     ; ' '
+  0x080068EB:  26           DC.B       0x26                     ; '&'
+  0x080068EC:  20           DC.B       0x20                     ; ' '
+  0x080068ED:  4F           DC.B       0x4F                     ; 'O'
+  0x080068EE:  56           DC.B       0x56                     ; 'V'
+  0x080068EF:  50           DC.B       0x50                     ; 'P'
+  0x080068F0:  20           DC.B       0x20                     ; ' '
+  0x080068F1:  29           DC.B       0x29                     ; ')'
+  0x080068F2:  21           DC.B       0x21                     ; '!'
+  0x080068F3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.14.174 from PowerPro_lto.o, size=28, align=1

+
+  0x080068F4:  46           DC.B       0x46                     ; 'F'
+  0x080068F5:  41           DC.B       0x41                     ; 'A'
+  0x080068F6:  55           DC.B       0x55                     ; 'U'
+  0x080068F7:  4C           DC.B       0x4C                     ; 'L'
+  0x080068F8:  54           DC.B       0x54                     ; 'T'
+  0x080068F9:  20           DC.B       0x20                     ; ' '
+  0x080068FA:  49           DC.B       0x49                     ; 'I'
+  0x080068FB:  4E           DC.B       0x4E                     ; 'N'
+  0x080068FC:  50           DC.B       0x50                     ; 'P'
+  0x080068FD:  55           DC.B       0x55                     ; 'U'
+  0x080068FE:  54           DC.B       0x54                     ; 'T'
+  0x080068FF:  20           DC.B       0x20                     ; ' '
+  0x08006900:  45           DC.B       0x45                     ; 'E'
+  0x08006901:  56           DC.B       0x56                     ; 'V'
+  0x08006902:  45           DC.B       0x45                     ; 'E'
+  0x08006903:  4E           DC.B       0x4E                     ; 'N'
+  0x08006904:  54           DC.B       0x54                     ; 'T'
+  0x08006905:  20           DC.B       0x20                     ; ' '
+  0x08006906:  44           DC.B       0x44                     ; 'D'
+  0x08006907:  45           DC.B       0x45                     ; 'E'
+  0x08006908:  54           DC.B       0x54                     ; 'T'
+  0x08006909:  45           DC.B       0x45                     ; 'E'
+  0x0800690A:  43           DC.B       0x43                     ; 'C'
+  0x0800690B:  54           DC.B       0x54                     ; 'T'
+  0x0800690C:  45           DC.B       0x45                     ; 'E'
+  0x0800690D:  44           DC.B       0x44                     ; 'D'
+  0x0800690E:  21           DC.B       0x21                     ; '!'
+  0x0800690F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_hex_uc from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=1

+
+
__SEGGER_RTL_hex_uc:
+  0x08006910:  30           DC.B       0x30                     ; '0'
+  0x08006911:  31           DC.B       0x31                     ; '1'
+  0x08006912:  32           DC.B       0x32                     ; '2'
+  0x08006913:  33           DC.B       0x33                     ; '3'
+  0x08006914:  34           DC.B       0x34                     ; '4'
+  0x08006915:  35           DC.B       0x35                     ; '5'
+  0x08006916:  36           DC.B       0x36                     ; '6'
+  0x08006917:  37           DC.B       0x37                     ; '7'
+  0x08006918:  38           DC.B       0x38                     ; '8'
+  0x08006919:  39           DC.B       0x39                     ; '9'
+  0x0800691A:  41           DC.B       0x41                     ; 'A'
+  0x0800691B:  42           DC.B       0x42                     ; 'B'
+  0x0800691C:  43           DC.B       0x43                     ; 'C'
+  0x0800691D:  44           DC.B       0x44                     ; 'D'
+  0x0800691E:  45           DC.B       0x45                     ; 'E'
+  0x0800691F:  46           DC.B       0x46                     ; 'F'
+
+

Section .rodata.libc.__SEGGER_RTL_hex_lc from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=1

+
+
__SEGGER_RTL_hex_lc:
+  0x08006920:  30           DC.B       0x30                     ; '0'
+  0x08006921:  31           DC.B       0x31                     ; '1'
+  0x08006922:  32           DC.B       0x32                     ; '2'
+  0x08006923:  33           DC.B       0x33                     ; '3'
+  0x08006924:  34           DC.B       0x34                     ; '4'
+  0x08006925:  35           DC.B       0x35                     ; '5'
+  0x08006926:  36           DC.B       0x36                     ; '6'
+  0x08006927:  37           DC.B       0x37                     ; '7'
+  0x08006928:  38           DC.B       0x38                     ; '8'
+  0x08006929:  39           DC.B       0x39                     ; '9'
+  0x0800692A:  61           DC.B       0x61                     ; 'a'
+  0x0800692B:  62           DC.B       0x62                     ; 'b'
+  0x0800692C:  63           DC.B       0x63                     ; 'c'
+  0x0800692D:  64           DC.B       0x64                     ; 'd'
+  0x0800692E:  65           DC.B       0x65                     ; 'e'
+  0x0800692F:  66           DC.B       0x66                     ; 'f'
+
+

Section .rodata.libc.__SEGGER_RTL_ascii_ctype_map from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=128, align=1

+
+
__SEGGER_RTL_ascii_ctype_map:
+  0x08006930:  20           DC.B       0x20                     ; ' '
+  0x08006931:  20           DC.B       0x20                     ; ' '
+  0x08006932:  20           DC.B       0x20                     ; ' '
+  0x08006933:  20           DC.B       0x20                     ; ' '
+  0x08006934:  20           DC.B       0x20                     ; ' '
+  0x08006935:  20           DC.B       0x20                     ; ' '
+  0x08006936:  20           DC.B       0x20                     ; ' '
+  0x08006937:  20           DC.B       0x20                     ; ' '
+  0x08006938:  20           DC.B       0x20                     ; ' '
+  0x08006939:  68           DC.B       0x68                     ; 'h'
+  0x0800693A:  28           DC.B       0x28                     ; '('
+  0x0800693B:  28           DC.B       0x28                     ; '('
+  0x0800693C:  28           DC.B       0x28                     ; '('
+  0x0800693D:  28           DC.B       0x28                     ; '('
+  0x0800693E:  20           DC.B       0x20                     ; ' '
+  0x0800693F:  20           DC.B       0x20                     ; ' '
+  0x08006940:  20           DC.B       0x20                     ; ' '
+  0x08006941:  20           DC.B       0x20                     ; ' '
+  0x08006942:  20           DC.B       0x20                     ; ' '
+  0x08006943:  20           DC.B       0x20                     ; ' '
+  0x08006944:  20           DC.B       0x20                     ; ' '
+  0x08006945:  20           DC.B       0x20                     ; ' '
+  0x08006946:  20           DC.B       0x20                     ; ' '
+  0x08006947:  20           DC.B       0x20                     ; ' '
+  0x08006948:  20           DC.B       0x20                     ; ' '
+  0x08006949:  20           DC.B       0x20                     ; ' '
+  0x0800694A:  20           DC.B       0x20                     ; ' '
+  0x0800694B:  20           DC.B       0x20                     ; ' '
+  0x0800694C:  20           DC.B       0x20                     ; ' '
+  0x0800694D:  20           DC.B       0x20                     ; ' '
+  0x0800694E:  20           DC.B       0x20                     ; ' '
+  0x0800694F:  20           DC.B       0x20                     ; ' '
+  0x08006950:  48           DC.B       0x48                     ; 'H'
+  0x08006951:  10           DC.B       0x10                     ; '\x10'
+  0x08006952:  10           DC.B       0x10                     ; '\x10'
+  0x08006953:  10           DC.B       0x10                     ; '\x10'
+  0x08006954:  10           DC.B       0x10                     ; '\x10'
+  0x08006955:  10           DC.B       0x10                     ; '\x10'
+  0x08006956:  10           DC.B       0x10                     ; '\x10'
+  0x08006957:  10           DC.B       0x10                     ; '\x10'
+  0x08006958:  10           DC.B       0x10                     ; '\x10'
+  0x08006959:  10           DC.B       0x10                     ; '\x10'
+  0x0800695A:  10           DC.B       0x10                     ; '\x10'
+  0x0800695B:  10           DC.B       0x10                     ; '\x10'
+  0x0800695C:  10           DC.B       0x10                     ; '\x10'
+  0x0800695D:  10           DC.B       0x10                     ; '\x10'
+  0x0800695E:  10           DC.B       0x10                     ; '\x10'
+  0x0800695F:  10           DC.B       0x10                     ; '\x10'
+  0x08006960:  84           DC.B       0x84                     ; '\x84'
+  0x08006961:  84           DC.B       0x84                     ; '\x84'
+  0x08006962:  84           DC.B       0x84                     ; '\x84'
+  0x08006963:  84           DC.B       0x84                     ; '\x84'
+  0x08006964:  84           DC.B       0x84                     ; '\x84'
+  0x08006965:  84           DC.B       0x84                     ; '\x84'
+  0x08006966:  84           DC.B       0x84                     ; '\x84'
+  0x08006967:  84           DC.B       0x84                     ; '\x84'
+  0x08006968:  84           DC.B       0x84                     ; '\x84'
+  0x08006969:  84           DC.B       0x84                     ; '\x84'
+  0x0800696A:  10           DC.B       0x10                     ; '\x10'
+  0x0800696B:  10           DC.B       0x10                     ; '\x10'
+  0x0800696C:  10           DC.B       0x10                     ; '\x10'
+  0x0800696D:  10           DC.B       0x10                     ; '\x10'
+  0x0800696E:  10           DC.B       0x10                     ; '\x10'
+  0x0800696F:  10           DC.B       0x10                     ; '\x10'
+  0x08006970:  10           DC.B       0x10                     ; '\x10'
+  0x08006971:  81           DC.B       0x81                     ; '\x81'
+  0x08006972:  81           DC.B       0x81                     ; '\x81'
+  0x08006973:  81           DC.B       0x81                     ; '\x81'
+  0x08006974:  81           DC.B       0x81                     ; '\x81'
+  0x08006975:  81           DC.B       0x81                     ; '\x81'
+  0x08006976:  81           DC.B       0x81                     ; '\x81'
+  0x08006977:  01           DC.B       0x01                     ; '\x01'
+  0x08006978:  01           DC.B       0x01                     ; '\x01'
+  0x08006979:  01           DC.B       0x01                     ; '\x01'
+  0x0800697A:  01           DC.B       0x01                     ; '\x01'
+  0x0800697B:  01           DC.B       0x01                     ; '\x01'
+  0x0800697C:  01           DC.B       0x01                     ; '\x01'
+  0x0800697D:  01           DC.B       0x01                     ; '\x01'
+  0x0800697E:  01           DC.B       0x01                     ; '\x01'
+  0x0800697F:  01           DC.B       0x01                     ; '\x01'
+  0x08006980:  01           DC.B       0x01                     ; '\x01'
+  0x08006981:  01           DC.B       0x01                     ; '\x01'
+  0x08006982:  01           DC.B       0x01                     ; '\x01'
+  0x08006983:  01           DC.B       0x01                     ; '\x01'
+  0x08006984:  01           DC.B       0x01                     ; '\x01'
+  0x08006985:  01           DC.B       0x01                     ; '\x01'
+  0x08006986:  01           DC.B       0x01                     ; '\x01'
+  0x08006987:  01           DC.B       0x01                     ; '\x01'
+  0x08006988:  01           DC.B       0x01                     ; '\x01'
+  0x08006989:  01           DC.B       0x01                     ; '\x01'
+  0x0800698A:  01           DC.B       0x01                     ; '\x01'
+  0x0800698B:  10           DC.B       0x10                     ; '\x10'
+  0x0800698C:  10           DC.B       0x10                     ; '\x10'
+  0x0800698D:  10           DC.B       0x10                     ; '\x10'
+  0x0800698E:  10           DC.B       0x10                     ; '\x10'
+  0x0800698F:  10           DC.B       0x10                     ; '\x10'
+  0x08006990:  10           DC.B       0x10                     ; '\x10'
+  0x08006991:  82           DC.B       0x82                     ; '\x82'
+  0x08006992:  82           DC.B       0x82                     ; '\x82'
+  0x08006993:  82           DC.B       0x82                     ; '\x82'
+  0x08006994:  82           DC.B       0x82                     ; '\x82'
+  0x08006995:  82           DC.B       0x82                     ; '\x82'
+  0x08006996:  82           DC.B       0x82                     ; '\x82'
+  0x08006997:  02           DC.B       0x02                     ; '\x02'
+  0x08006998:  02           DC.B       0x02                     ; '\x02'
+  0x08006999:  02           DC.B       0x02                     ; '\x02'
+  0x0800699A:  02           DC.B       0x02                     ; '\x02'
+  0x0800699B:  02           DC.B       0x02                     ; '\x02'
+  0x0800699C:  02           DC.B       0x02                     ; '\x02'
+  0x0800699D:  02           DC.B       0x02                     ; '\x02'
+  0x0800699E:  02           DC.B       0x02                     ; '\x02'
+  0x0800699F:  02           DC.B       0x02                     ; '\x02'
+  0x080069A0:  02           DC.B       0x02                     ; '\x02'
+  0x080069A1:  02           DC.B       0x02                     ; '\x02'
+  0x080069A2:  02           DC.B       0x02                     ; '\x02'
+  0x080069A3:  02           DC.B       0x02                     ; '\x02'
+  0x080069A4:  02           DC.B       0x02                     ; '\x02'
+  0x080069A5:  02           DC.B       0x02                     ; '\x02'
+  0x080069A6:  02           DC.B       0x02                     ; '\x02'
+  0x080069A7:  02           DC.B       0x02                     ; '\x02'
+  0x080069A8:  02           DC.B       0x02                     ; '\x02'
+  0x080069A9:  02           DC.B       0x02                     ; '\x02'
+  0x080069AA:  02           DC.B       0x02                     ; '\x02'
+  0x080069AB:  10           DC.B       0x10                     ; '\x10'
+  0x080069AC:  10           DC.B       0x10                     ; '\x10'
+  0x080069AD:  10           DC.B       0x10                     ; '\x10'
+  0x080069AE:  10           DC.B       0x10                     ; '\x10'
+  0x080069AF:  20           DC.B       0x20                     ; ' '
+
+

Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=36, align=4

+
+
__SEGGER_init_ctors:
+  0x080069B0:  B500         PUSH       {LR}
+  0x080069B2:  4806         LDR        R0, =0x080067C8          ; [PC, #24] [0x080069CC] 
+  0x080069B4:  4906         LDR        R1, =UARTEx_SetNbDataToProcess.numerator ; [PC, #24] [0x080069D0] =0x080067CC 
+
.L1:
+  0x080069B6:  4288         CMP        R0, R1
+  0x080069B8:  D005         BEQ        .L2                      ; 0x080069C6
+  0x080069BA:  6802         LDR        R2, [R0]
+  0x080069BC:  3004         ADDS       R0, #4
+  0x080069BE:  B403         PUSH       {R0-R1}
+  0x080069C0:  4790         BLX        R2
+  0x080069C2:  BC03         POP        {R0-R1}
+  0x080069C4:  E7F7         B          .L1                      ; 0x080069B6
+
.L2:
+  0x080069C6:  BC08         POP        {R3}
+  0x080069C8:  4718         BX         R3
+  0x080069CA:  0000         NOP
+  0x080069CC:  080067C8     DC.W       080067C8               ; R_ARM_ABS32
+  0x080069D0:  080067CC     DC.W       UARTEx_SetNbDataToProcess.numerator
+
+

Section .segger.init.table from [ Linker created ], size=180, align=4

+
+  0x080069D4:  08006AB1     DC.W       __SEGGER_init_zero
+  0x080069D8:  00           DC.B       0x00                     ; '\0'
+  0x080069D9:  00           DC.B       0x00                     ; '\0'
+  0x080069DA:  00           DC.B       0x00                     ; '\0'
+  0x080069DB:  20           DC.B       0x20                     ; ' '
+  0x080069DC:  3B           DC.B       0x3B                     ; ';'
+  0x080069DD:  07           DC.B       0x07                     ; '\x07'
+  0x080069DE:  00           DC.B       0x00                     ; '\0'
+  0x080069DF:  00           DC.B       0x00                     ; '\0'
+  0x080069E0:  08006AB1     DC.W       __SEGGER_init_zero
+  0x080069E4:  3C           DC.B       0x3C                     ; '<'
+  0x080069E5:  07           DC.B       0x07                     ; '\x07'
+  0x080069E6:  00           DC.B       0x00                     ; '\0'
+  0x080069E7:  20           DC.B       0x20                     ; ' '
+  0x080069E8:  01           DC.B       0x01                     ; '\x01'
+  0x080069E9:  00           DC.B       0x00                     ; '\0'
+  0x080069EA:  00           DC.B       0x00                     ; '\0'
+  0x080069EB:  00           DC.B       0x00                     ; '\0'
+  0x080069EC:  08006AB1     DC.W       __SEGGER_init_zero
+  0x080069F0:  40           DC.B       0x40                     ; '@'
+  0x080069F1:  07           DC.B       0x07                     ; '\x07'
+  0x080069F2:  00           DC.B       0x00                     ; '\0'
+  0x080069F3:  20           DC.B       0x20                     ; ' '
+  0x080069F4:  01           DC.B       0x01                     ; '\x01'
+  0x080069F5:  00           DC.B       0x00                     ; '\0'
+  0x080069F6:  00           DC.B       0x00                     ; '\0'
+  0x080069F7:  00           DC.B       0x00                     ; '\0'
+  0x080069F8:  08006AB1     DC.W       __SEGGER_init_zero
+  0x080069FC:  44           DC.B       0x44                     ; 'D'
+  0x080069FD:  07           DC.B       0x07                     ; '\x07'
+  0x080069FE:  00           DC.B       0x00                     ; '\0'
+  0x080069FF:  20           DC.B       0x20                     ; ' '
+  0x08006A00:  01           DC.B       0x01                     ; '\x01'
+  0x08006A01:  00           DC.B       0x00                     ; '\0'
+  0x08006A02:  00           DC.B       0x00                     ; '\0'
+  0x08006A03:  00           DC.B       0x00                     ; '\0'
+  0x08006A04:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A08:  48           DC.B       0x48                     ; 'H'
+  0x08006A09:  07           DC.B       0x07                     ; '\x07'
+  0x08006A0A:  00           DC.B       0x00                     ; '\0'
+  0x08006A0B:  20           DC.B       0x20                     ; ' '
+  0x08006A0C:  01           DC.B       0x01                     ; '\x01'
+  0x08006A0D:  00           DC.B       0x00                     ; '\0'
+  0x08006A0E:  00           DC.B       0x00                     ; '\0'
+  0x08006A0F:  00           DC.B       0x00                     ; '\0'
+  0x08006A10:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A14:  4C           DC.B       0x4C                     ; 'L'
+  0x08006A15:  07           DC.B       0x07                     ; '\x07'
+  0x08006A16:  00           DC.B       0x00                     ; '\0'
+  0x08006A17:  20           DC.B       0x20                     ; ' '
+  0x08006A18:  01           DC.B       0x01                     ; '\x01'
+  0x08006A19:  00           DC.B       0x00                     ; '\0'
+  0x08006A1A:  00           DC.B       0x00                     ; '\0'
+  0x08006A1B:  00           DC.B       0x00                     ; '\0'
+  0x08006A1C:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A20:  50           DC.B       0x50                     ; 'P'
+  0x08006A21:  07           DC.B       0x07                     ; '\x07'
+  0x08006A22:  00           DC.B       0x00                     ; '\0'
+  0x08006A23:  20           DC.B       0x20                     ; ' '
+  0x08006A24:  01           DC.B       0x01                     ; '\x01'
+  0x08006A25:  00           DC.B       0x00                     ; '\0'
+  0x08006A26:  00           DC.B       0x00                     ; '\0'
+  0x08006A27:  00           DC.B       0x00                     ; '\0'
+  0x08006A28:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A2C:  54           DC.B       0x54                     ; 'T'
+  0x08006A2D:  07           DC.B       0x07                     ; '\x07'
+  0x08006A2E:  00           DC.B       0x00                     ; '\0'
+  0x08006A2F:  20           DC.B       0x20                     ; ' '
+  0x08006A30:  01           DC.B       0x01                     ; '\x01'
+  0x08006A31:  00           DC.B       0x00                     ; '\0'
+  0x08006A32:  00           DC.B       0x00                     ; '\0'
+  0x08006A33:  00           DC.B       0x00                     ; '\0'
+  0x08006A34:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A38:  58           DC.B       0x58                     ; 'X'
+  0x08006A39:  07           DC.B       0x07                     ; '\x07'
+  0x08006A3A:  00           DC.B       0x00                     ; '\0'
+  0x08006A3B:  20           DC.B       0x20                     ; ' '
+  0x08006A3C:  01           DC.B       0x01                     ; '\x01'
+  0x08006A3D:  00           DC.B       0x00                     ; '\0'
+  0x08006A3E:  00           DC.B       0x00                     ; '\0'
+  0x08006A3F:  00           DC.B       0x00                     ; '\0'
+  0x08006A40:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A44:  5C           DC.B       0x5C                     ; '\\'
+  0x08006A45:  07           DC.B       0x07                     ; '\x07'
+  0x08006A46:  00           DC.B       0x00                     ; '\0'
+  0x08006A47:  20           DC.B       0x20                     ; ' '
+  0x08006A48:  01           DC.B       0x01                     ; '\x01'
+  0x08006A49:  00           DC.B       0x00                     ; '\0'
+  0x08006A4A:  00           DC.B       0x00                     ; '\0'
+  0x08006A4B:  00           DC.B       0x00                     ; '\0'
+  0x08006A4C:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A50:  60           DC.B       0x60                     ; '`'
+  0x08006A51:  07           DC.B       0x07                     ; '\x07'
+  0x08006A52:  00           DC.B       0x00                     ; '\0'
+  0x08006A53:  20           DC.B       0x20                     ; ' '
+  0x08006A54:  01           DC.B       0x01                     ; '\x01'
+  0x08006A55:  00           DC.B       0x00                     ; '\0'
+  0x08006A56:  00           DC.B       0x00                     ; '\0'
+  0x08006A57:  00           DC.B       0x00                     ; '\0'
+  0x08006A58:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A5C:  64           DC.B       0x64                     ; 'd'
+  0x08006A5D:  07           DC.B       0x07                     ; '\x07'
+  0x08006A5E:  00           DC.B       0x00                     ; '\0'
+  0x08006A5F:  20           DC.B       0x20                     ; ' '
+  0x08006A60:  01           DC.B       0x01                     ; '\x01'
+  0x08006A61:  00           DC.B       0x00                     ; '\0'
+  0x08006A62:  00           DC.B       0x00                     ; '\0'
+  0x08006A63:  00           DC.B       0x00                     ; '\0'
+  0x08006A64:  08006AB1     DC.W       __SEGGER_init_zero
+  0x08006A68:  68           DC.B       0x68                     ; 'h'
+  0x08006A69:  07           DC.B       0x07                     ; '\x07'
+  0x08006A6A:  00           DC.B       0x00                     ; '\0'
+  0x08006A6B:  20           DC.B       0x20                     ; ' '
+  0x08006A6C:  11           DC.B       0x11                     ; '\x11'
+  0x08006A6D:  04           DC.B       0x04                     ; '\x04'
+  0x08006A6E:  00           DC.B       0x00                     ; '\0'
+  0x08006A6F:  00           DC.B       0x00                     ; '\0'
+  0x08006A70:  08006AC3     DC.W       __SEGGER_init_copy
+  0x08006A74:  80           DC.B       0x80                     ; '\x80'
+  0x08006A75:  0B           DC.B       0x0B                     ; '\v'
+  0x08006A76:  00           DC.B       0x00                     ; '\0'
+  0x08006A77:  20           DC.B       0x20                     ; ' '
+  0x08006A78:  08006A88     DC.W       08006A88               ; R_ARM_ABS32
+  0x08006A7C:  28           DC.B       0x28                     ; '('
+  0x08006A7D:  00           DC.B       0x00                     ; '\0'
+  0x08006A7E:  00           DC.B       0x00                     ; '\0'
+  0x08006A7F:  00           DC.B       0x00                     ; '\0'
+  0x08006A80:  080069B1     DC.W       __SEGGER_init_ctors
+  0x08006A84:  0800513F     DC.W       __SEGGER_init_done
+
+

Section .segger.init.data from [ Linker created ], size=40, align=4

+
+  0x08006A88:  E8           DC.B       0xE8                     ; '\xE8'
+  0x08006A89:  56           DC.B       0x56                     ; 'V'
+  0x08006A8A:  00           DC.B       0x00                     ; '\0'
+  0x08006A8B:  08           DC.B       0x08                     ; '\b'
+  0x08006A8C:  E8           DC.B       0xE8                     ; '\xE8'
+  0x08006A8D:  56           DC.B       0x56                     ; 'V'
+  0x08006A8E:  00           DC.B       0x00                     ; '\0'
+  0x08006A8F:  08           DC.B       0x08                     ; '\b'
+  0x08006A90:  E8           DC.B       0xE8                     ; '\xE8'
+  0x08006A91:  56           DC.B       0x56                     ; 'V'
+  0x08006A92:  00           DC.B       0x00                     ; '\0'
+  0x08006A93:  08           DC.B       0x08                     ; '\b'
+  0x08006A94:  E8           DC.B       0xE8                     ; '\xE8'
+  0x08006A95:  56           DC.B       0x56                     ; 'V'
+  0x08006A96:  00           DC.B       0x00                     ; '\0'
+  0x08006A97:  08           DC.B       0x08                     ; '\b'
+  0x08006A98:  E8           DC.B       0xE8                     ; '\xE8'
+  0x08006A99:  56           DC.B       0x56                     ; 'V'
+  0x08006A9A:  00           DC.B       0x00                     ; '\0'
+  0x08006A9B:  08           DC.B       0x08                     ; '\b'
+  0x08006A9C:  04           DC.B       0x04                     ; '\x04'
+  0x08006A9D:  00           DC.B       0x00                     ; '\0'
+  0x08006A9E:  00           DC.B       0x00                     ; '\0'
+  0x08006A9F:  00           DC.B       0x00                     ; '\0'
+  0x08006AA0:  CC           DC.B       0xCC                     ; '\xCC'
+  0x08006AA1:  06           DC.B       0x06                     ; '\x06'
+  0x08006AA2:  00           DC.B       0x00                     ; '\0'
+  0x08006AA3:  20           DC.B       0x20                     ; ' '
+  0x08006AA4:  D0           DC.B       0xD0                     ; '\xD0'
+  0x08006AA5:  06           DC.B       0x06                     ; '\x06'
+  0x08006AA6:  00           DC.B       0x00                     ; '\0'
+  0x08006AA7:  20           DC.B       0x20                     ; ' '
+  0x08006AA8:  D4           DC.B       0xD4                     ; '\xD4'
+  0x08006AA9:  06           DC.B       0x06                     ; '\x06'
+  0x08006AAA:  00           DC.B       0x00                     ; '\0'
+  0x08006AAB:  20           DC.B       0x20                     ; ' '
+  0x08006AAC:  00           DC.B       0x00                     ; '\0'
+  0x08006AAD:  1B           DC.B       0x1B                     ; '\x1B'
+  0x08006AAE:  B7           DC.B       0xB7                     ; '\xB7'
+  0x08006AAF:  00           DC.B       0x00                     ; '\0'
+
+

Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=18, align=2

+
+
__SEGGER_init_zero:
+  0x08006AB0:  6820         LDR        R0, [R4]
+  0x08006AB2:  6861         LDR        R1, [R4, #4]
+  0x08006AB4:  3408         ADDS       R4, #8
+  0x08006AB6:  2200         MOVS       R2, #0
+  0x08006AB8:  E000         B          .L2                      ; 0x08006ABC
+
.L1:
+  0x08006ABA:  5442         STRB       R2, [R0, R1]
+
.L2:
+  0x08006ABC:  1E49         SUBS       R1, R1, #1
+  0x08006ABE:  D5FC         BPL        .L1                      ; 0x08006ABA
+  0x08006AC0:  4770         BX         LR
+
+

Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=20, align=2

+
+
__SEGGER_init_copy:
+  0x08006AC2:  6820         LDR        R0, [R4]
+  0x08006AC4:  6861         LDR        R1, [R4, #4]
+  0x08006AC6:  68A2         LDR        R2, [R4, #8]
+  0x08006AC8:  340C         ADDS       R4, #12
+  0x08006ACA:  E001         B          .L2                      ; 0x08006AD0
+
.L1:
+  0x08006ACC:  5C8B         LDRB       R3, [R1, R2]
+  0x08006ACE:  5483         STRB       R3, [R0, R2]
+
.L2:
+  0x08006AD0:  1E52         SUBS       R2, R2, #1
+  0x08006AD2:  D5FB         BPL        .L1                      ; 0x08006ACC
+  0x08006AD4:  4770         BX         LR
+
+

Section .RAM1 from PowerPro_lto.o, size=564, align=4

+
+
modbusData:
+  0x20000000:  00           DC.B       0x00                     ; '\0'
+  0x20000001:  00           DC.B       0x00                     ; '\0'
+  0x20000002:  00           DC.B       0x00                     ; '\0'
+  0x20000003:  00           DC.B       0x00                     ; '\0'
+  0x20000004:  00           DC.B       0x00                     ; '\0'
+  0x20000005:  00           DC.B       0x00                     ; '\0'
+  0x20000006:  00           DC.B       0x00                     ; '\0'
+  0x20000007:  00           DC.B       0x00                     ; '\0'
+  0x20000008:  00           DC.B       0x00                     ; '\0'
+  0x20000009:  00           DC.B       0x00                     ; '\0'
+  0x2000000A:  00           DC.B       0x00                     ; '\0'
+  0x2000000B:  00           DC.B       0x00                     ; '\0'
+  0x2000000C:  00           DC.B       0x00                     ; '\0'
+  0x2000000D:  00           DC.B       0x00                     ; '\0'
+  0x2000000E:  00           DC.B       0x00                     ; '\0'
+  0x2000000F:  00           DC.B       0x00                     ; '\0'
+  0x20000010:  00           DC.B       0x00                     ; '\0'
+  0x20000011:  00           DC.B       0x00                     ; '\0'
+  0x20000012:  00           DC.B       0x00                     ; '\0'
+  0x20000013:  00           DC.B       0x00                     ; '\0'
+  0x20000014:  00           DC.B       0x00                     ; '\0'
+  0x20000015:  00           DC.B       0x00                     ; '\0'
+  0x20000016:  00           DC.B       0x00                     ; '\0'
+  0x20000017:  00           DC.B       0x00                     ; '\0'
+  0x20000018:  00           DC.B       0x00                     ; '\0'
+  0x20000019:  00           DC.B       0x00                     ; '\0'
+  0x2000001A:  00           DC.B       0x00                     ; '\0'
+  0x2000001B:  00           DC.B       0x00                     ; '\0'
+  0x2000001C:  00           DC.B       0x00                     ; '\0'
+  0x2000001D:  00           DC.B       0x00                     ; '\0'
+  0x2000001E:  00           DC.B       0x00                     ; '\0'
+  0x2000001F:  00           DC.B       0x00                     ; '\0'
+  0x20000020:  00           DC.B       0x00                     ; '\0'
+  0x20000021:  00           DC.B       0x00                     ; '\0'
+  0x20000022:  00           DC.B       0x00                     ; '\0'
+  0x20000023:  00           DC.B       0x00                     ; '\0'
+  0x20000024:  00           DC.B       0x00                     ; '\0'
+  0x20000025:  00           DC.B       0x00                     ; '\0'
+  0x20000026:  00           DC.B       0x00                     ; '\0'
+  0x20000027:  00           DC.B       0x00                     ; '\0'
+  0x20000028:  00           DC.B       0x00                     ; '\0'
+  0x20000029:  00           DC.B       0x00                     ; '\0'
+  0x2000002A:  00           DC.B       0x00                     ; '\0'
+  0x2000002B:  00           DC.B       0x00                     ; '\0'
+  0x2000002C:  00           DC.B       0x00                     ; '\0'
+  0x2000002D:  00           DC.B       0x00                     ; '\0'
+  0x2000002E:  00           DC.B       0x00                     ; '\0'
+  0x2000002F:  00           DC.B       0x00                     ; '\0'
+  0x20000030:  00           DC.B       0x00                     ; '\0'
+  0x20000031:  00           DC.B       0x00                     ; '\0'
+  0x20000032:  00           DC.B       0x00                     ; '\0'
+  0x20000033:  00           DC.B       0x00                     ; '\0'
+  0x20000034:  00           DC.B       0x00                     ; '\0'
+  0x20000035:  00           DC.B       0x00                     ; '\0'
+  0x20000036:  00           DC.B       0x00                     ; '\0'
+  0x20000037:  00           DC.B       0x00                     ; '\0'
+  0x20000038:  00           DC.B       0x00                     ; '\0'
+  0x20000039:  00           DC.B       0x00                     ; '\0'
+  0x2000003A:  00           DC.B       0x00                     ; '\0'
+  0x2000003B:  00           DC.B       0x00                     ; '\0'
+  0x2000003C:  00           DC.B       0x00                     ; '\0'
+  0x2000003D:  00           DC.B       0x00                     ; '\0'
+  0x2000003E:  00           DC.B       0x00                     ; '\0'
+  0x2000003F:  00           DC.B       0x00                     ; '\0'
+  0x20000040:  00           DC.B       0x00                     ; '\0'
+  0x20000041:  00           DC.B       0x00                     ; '\0'
+  0x20000042:  00           DC.B       0x00                     ; '\0'
+  0x20000043:  00           DC.B       0x00                     ; '\0'
+  0x20000044:  00           DC.B       0x00                     ; '\0'
+  0x20000045:  00           DC.B       0x00                     ; '\0'
+  0x20000046:  00           DC.B       0x00                     ; '\0'
+  0x20000047:  00           DC.B       0x00                     ; '\0'
+  0x20000048:  00           DC.B       0x00                     ; '\0'
+  0x20000049:  00           DC.B       0x00                     ; '\0'
+  0x2000004A:  00           DC.B       0x00                     ; '\0'
+  0x2000004B:  00           DC.B       0x00                     ; '\0'
+  0x2000004C:  00           DC.B       0x00                     ; '\0'
+  0x2000004D:  00           DC.B       0x00                     ; '\0'
+  0x2000004E:  00           DC.B       0x00                     ; '\0'
+  0x2000004F:  00           DC.B       0x00                     ; '\0'
+  0x20000050:  00           DC.B       0x00                     ; '\0'
+  0x20000051:  00           DC.B       0x00                     ; '\0'
+  0x20000052:  00           DC.B       0x00                     ; '\0'
+  0x20000053:  00           DC.B       0x00                     ; '\0'
+  0x20000054:  00           DC.B       0x00                     ; '\0'
+  0x20000055:  00           DC.B       0x00                     ; '\0'
+  0x20000056:  00           DC.B       0x00                     ; '\0'
+  0x20000057:  00           DC.B       0x00                     ; '\0'
+  0x20000058:  00           DC.B       0x00                     ; '\0'
+  0x20000059:  00           DC.B       0x00                     ; '\0'
+  0x2000005A:  00           DC.B       0x00                     ; '\0'
+  0x2000005B:  00           DC.B       0x00                     ; '\0'
+  0x2000005C:  00           DC.B       0x00                     ; '\0'
+  0x2000005D:  00           DC.B       0x00                     ; '\0'
+  0x2000005E:  00           DC.B       0x00                     ; '\0'
+  0x2000005F:  00           DC.B       0x00                     ; '\0'
+  0x20000060:  00           DC.B       0x00                     ; '\0'
+  0x20000061:  00           DC.B       0x00                     ; '\0'
+  0x20000062:  00           DC.B       0x00                     ; '\0'
+  0x20000063:  00           DC.B       0x00                     ; '\0'
+  0x20000064:  00           DC.B       0x00                     ; '\0'
+  0x20000065:  00           DC.B       0x00                     ; '\0'
+  0x20000066:  00           DC.B       0x00                     ; '\0'
+  0x20000067:  00           DC.B       0x00                     ; '\0'
+  0x20000068:  00           DC.B       0x00                     ; '\0'
+  0x20000069:  00           DC.B       0x00                     ; '\0'
+  0x2000006A:  00           DC.B       0x00                     ; '\0'
+  0x2000006B:  00           DC.B       0x00                     ; '\0'
+  0x2000006C:  00           DC.B       0x00                     ; '\0'
+  0x2000006D:  00           DC.B       0x00                     ; '\0'
+  0x2000006E:  00           DC.B       0x00                     ; '\0'
+  0x2000006F:  00           DC.B       0x00                     ; '\0'
+  0x20000070:  00           DC.B       0x00                     ; '\0'
+  0x20000071:  00           DC.B       0x00                     ; '\0'
+  0x20000072:  00           DC.B       0x00                     ; '\0'
+  0x20000073:  00           DC.B       0x00                     ; '\0'
+  0x20000074:  00           DC.B       0x00                     ; '\0'
+  0x20000075:  00           DC.B       0x00                     ; '\0'
+  0x20000076:  00           DC.B       0x00                     ; '\0'
+  0x20000077:  00           DC.B       0x00                     ; '\0'
+  0x20000078:  00           DC.B       0x00                     ; '\0'
+  0x20000079:  00           DC.B       0x00                     ; '\0'
+  0x2000007A:  00           DC.B       0x00                     ; '\0'
+  0x2000007B:  00           DC.B       0x00                     ; '\0'
+  0x2000007C:  00           DC.B       0x00                     ; '\0'
+  0x2000007D:  00           DC.B       0x00                     ; '\0'
+  0x2000007E:  00           DC.B       0x00                     ; '\0'
+  0x2000007F:  00           DC.B       0x00                     ; '\0'
+  0x20000080:  00           DC.B       0x00                     ; '\0'
+  0x20000081:  00           DC.B       0x00                     ; '\0'
+  0x20000082:  00           DC.B       0x00                     ; '\0'
+  0x20000083:  00           DC.B       0x00                     ; '\0'
+  0x20000084:  00           DC.B       0x00                     ; '\0'
+  0x20000085:  00           DC.B       0x00                     ; '\0'
+  0x20000086:  00           DC.B       0x00                     ; '\0'
+  0x20000087:  00           DC.B       0x00                     ; '\0'
+  0x20000088:  00           DC.B       0x00                     ; '\0'
+  0x20000089:  00           DC.B       0x00                     ; '\0'
+  0x2000008A:  00           DC.B       0x00                     ; '\0'
+  0x2000008B:  00           DC.B       0x00                     ; '\0'
+  0x2000008C:  00           DC.B       0x00                     ; '\0'
+  0x2000008D:  00           DC.B       0x00                     ; '\0'
+  0x2000008E:  00           DC.B       0x00                     ; '\0'
+  0x2000008F:  00           DC.B       0x00                     ; '\0'
+  0x20000090:  00           DC.B       0x00                     ; '\0'
+  0x20000091:  00           DC.B       0x00                     ; '\0'
+  0x20000092:  00           DC.B       0x00                     ; '\0'
+  0x20000093:  00           DC.B       0x00                     ; '\0'
+  0x20000094:  00           DC.B       0x00                     ; '\0'
+  0x20000095:  00           DC.B       0x00                     ; '\0'
+  0x20000096:  00           DC.B       0x00                     ; '\0'
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+  0x200001D4:  00           DC.B       0x00                     ; '\0'
+  0x200001D5:  00           DC.B       0x00                     ; '\0'
+  0x200001D6:  00           DC.B       0x00                     ; '\0'
+  0x200001D7:  00           DC.B       0x00                     ; '\0'
+  0x200001D8:  00           DC.B       0x00                     ; '\0'
+  0x200001D9:  00           DC.B       0x00                     ; '\0'
+  0x200001DA:  00           DC.B       0x00                     ; '\0'
+  0x200001DB:  00           DC.B       0x00                     ; '\0'
+  0x200001DC:  00           DC.B       0x00                     ; '\0'
+  0x200001DD:  00           DC.B       0x00                     ; '\0'
+  0x200001DE:  00           DC.B       0x00                     ; '\0'
+  0x200001DF:  00           DC.B       0x00                     ; '\0'
+  0x200001E0:  00           DC.B       0x00                     ; '\0'
+  0x200001E1:  00           DC.B       0x00                     ; '\0'
+  0x200001E2:  00           DC.B       0x00                     ; '\0'
+  0x200001E3:  00           DC.B       0x00                     ; '\0'
+  0x200001E4:  00           DC.B       0x00                     ; '\0'
+  0x200001E5:  00           DC.B       0x00                     ; '\0'
+  0x200001E6:  00           DC.B       0x00                     ; '\0'
+  0x200001E7:  00           DC.B       0x00                     ; '\0'
+  0x200001E8:  00           DC.B       0x00                     ; '\0'
+  0x200001E9:  00           DC.B       0x00                     ; '\0'
+  0x200001EA:  00           DC.B       0x00                     ; '\0'
+  0x200001EB:  00           DC.B       0x00                     ; '\0'
+  0x200001EC:  00           DC.B       0x00                     ; '\0'
+  0x200001ED:  00           DC.B       0x00                     ; '\0'
+  0x200001EE:  00           DC.B       0x00                     ; '\0'
+  0x200001EF:  00           DC.B       0x00                     ; '\0'
+  0x200001F0:  00           DC.B       0x00                     ; '\0'
+  0x200001F1:  00           DC.B       0x00                     ; '\0'
+  0x200001F2:  00           DC.B       0x00                     ; '\0'
+  0x200001F3:  00           DC.B       0x00                     ; '\0'
+  0x200001F4:  00           DC.B       0x00                     ; '\0'
+  0x200001F5:  00           DC.B       0x00                     ; '\0'
+  0x200001F6:  00           DC.B       0x00                     ; '\0'
+  0x200001F7:  00           DC.B       0x00                     ; '\0'
+  0x200001F8:  00           DC.B       0x00                     ; '\0'
+  0x200001F9:  00           DC.B       0x00                     ; '\0'
+  0x200001FA:  00           DC.B       0x00                     ; '\0'
+  0x200001FB:  00           DC.B       0x00                     ; '\0'
+  0x200001FC:  00           DC.B       0x00                     ; '\0'
+  0x200001FD:  00           DC.B       0x00                     ; '\0'
+  0x200001FE:  00           DC.B       0x00                     ; '\0'
+  0x200001FF:  00           DC.B       0x00                     ; '\0'
+  0x20000200:  00           DC.B       0x00                     ; '\0'
+  0x20000201:  00           DC.B       0x00                     ; '\0'
+  0x20000202:  00           DC.B       0x00                     ; '\0'
+  0x20000203:  00           DC.B       0x00                     ; '\0'
+  0x20000204:  00           DC.B       0x00                     ; '\0'
+  0x20000205:  00           DC.B       0x00                     ; '\0'
+  0x20000206:  00           DC.B       0x00                     ; '\0'
+  0x20000207:  00           DC.B       0x00                     ; '\0'
+  0x20000208:  00           DC.B       0x00                     ; '\0'
+  0x20000209:  00           DC.B       0x00                     ; '\0'
+  0x2000020A:  00           DC.B       0x00                     ; '\0'
+  0x2000020B:  00           DC.B       0x00                     ; '\0'
+  0x2000020C:  00           DC.B       0x00                     ; '\0'
+  0x2000020D:  00           DC.B       0x00                     ; '\0'
+  0x2000020E:  00           DC.B       0x00                     ; '\0'
+  0x2000020F:  00           DC.B       0x00                     ; '\0'
+  0x20000210:  00           DC.B       0x00                     ; '\0'
+  0x20000211:  00           DC.B       0x00                     ; '\0'
+  0x20000212:  00           DC.B       0x00                     ; '\0'
+  0x20000213:  00           DC.B       0x00                     ; '\0'
+  0x20000214:  00           DC.B       0x00                     ; '\0'
+  0x20000215:  00           DC.B       0x00                     ; '\0'
+  0x20000216:  00           DC.B       0x00                     ; '\0'
+  0x20000217:  00           DC.B       0x00                     ; '\0'
+  0x20000218:  00           DC.B       0x00                     ; '\0'
+  0x20000219:  00           DC.B       0x00                     ; '\0'
+  0x2000021A:  00           DC.B       0x00                     ; '\0'
+  0x2000021B:  00           DC.B       0x00                     ; '\0'
+  0x2000021C:  00           DC.B       0x00                     ; '\0'
+  0x2000021D:  00           DC.B       0x00                     ; '\0'
+  0x2000021E:  00           DC.B       0x00                     ; '\0'
+  0x2000021F:  00           DC.B       0x00                     ; '\0'
+  0x20000220:  00           DC.B       0x00                     ; '\0'
+  0x20000221:  00           DC.B       0x00                     ; '\0'
+  0x20000222:  00           DC.B       0x00                     ; '\0'
+  0x20000223:  00           DC.B       0x00                     ; '\0'
+  0x20000224:  00           DC.B       0x00                     ; '\0'
+  0x20000225:  00           DC.B       0x00                     ; '\0'
+  0x20000226:  00           DC.B       0x00                     ; '\0'
+  0x20000227:  00           DC.B       0x00                     ; '\0'
+  0x20000228:  00           DC.B       0x00                     ; '\0'
+  0x20000229:  00           DC.B       0x00                     ; '\0'
+  0x2000022A:  00           DC.B       0x00                     ; '\0'
+  0x2000022B:  00           DC.B       0x00                     ; '\0'
+  0x2000022C:  00           DC.B       0x00                     ; '\0'
+  0x2000022D:  00           DC.B       0x00                     ; '\0'
+  0x2000022E:  00           DC.B       0x00                     ; '\0'
+  0x2000022F:  00           DC.B       0x00                     ; '\0'
+  0x20000230:  00           DC.B       0x00                     ; '\0'
+  0x20000231:  00           DC.B       0x00                     ; '\0'
+  0x20000232:  00           DC.B       0x00                     ; '\0'
+  0x20000233:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.sys_data from PowerPro_lto.o, size=224, align=4

+
+
sys_data:
+  0x20000234:  76           DC.B       0x76                     ; 'v'
+  0x20000235:  6F           DC.B       0x6F                     ; 'o'
+  0x20000236:  6C           DC.B       0x6C                     ; 'l'
+  0x20000237:  74           DC.B       0x74                     ; 't'
+  0x20000238:  61           DC.B       0x61                     ; 'a'
+  0x20000239:  67           DC.B       0x67                     ; 'g'
+  0x2000023A:  65           DC.B       0x65                     ; 'e'
+  0x2000023B:  20           DC.B       0x20                     ; ' '
+  0x2000023C:  69           DC.B       0x69                     ; 'i'
+  0x2000023D:  6E           DC.B       0x6E                     ; 'n'
+  0x2000023E:  3D           DC.B       0x3D                     ; '='
+  0x2000023F:  20           DC.B       0x20                     ; ' '
+  0x20000240:  25           DC.B       0x25                     ; '%'
+  0x20000241:  64           DC.B       0x64                     ; 'd'
+  0x20000242:  2C           DC.B       0x2C                     ; ','
+  0x20000243:  20           DC.B       0x20                     ; ' '
+  0x20000244:  6F           DC.B       0x6F                     ; 'o'
+  0x20000245:  75           DC.B       0x75                     ; 'u'
+  0x20000246:  74           DC.B       0x74                     ; 't'
+  0x20000247:  3D           DC.B       0x3D                     ; '='
+  0x20000248:  20           DC.B       0x20                     ; ' '
+  0x20000249:  25           DC.B       0x25                     ; '%'
+  0x2000024A:  64           DC.B       0x64                     ; 'd'
+  0x2000024B:  2C           DC.B       0x2C                     ; ','
+  0x2000024C:  20           DC.B       0x20                     ; ' '
+  0x2000024D:  64           DC.B       0x64                     ; 'd'
+  0x2000024E:  72           DC.B       0x72                     ; 'r'
+  0x2000024F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000250:  70           DC.B       0x70                     ; 'p'
+  0x20000251:  20           DC.B       0x20                     ; ' '
+  0x20000252:  25           DC.B       0x25                     ; '%'
+  0x20000253:  64           DC.B       0x64                     ; 'd'
+  0x20000254:  0D           DC.B       0x0D                     ; '\r'
+  0x20000255:  0A           DC.B       0x0A                     ; '\n'
+  0x20000256:  00           DC.B       0x00                     ; '\0'
+  0x20000257:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000258:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000259:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000025A:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000025B:  EC           DC.B       0xEC                     ; '\xEC'
+  0x2000025C:  00           DC.B       0x00                     ; '\0'
+  0x2000025D:  00           DC.B       0x00                     ; '\0'
+  0x2000025E:  08           DC.B       0x08                     ; '\b'
+  0x2000025F:  06           DC.B       0x06                     ; '\x06'
+  0x20000260:  00           DC.B       0x00                     ; '\0'
+  0x20000261:  00           DC.B       0x00                     ; '\0'
+  0x20000262:  00           DC.B       0x00                     ; '\0'
+  0x20000263:  02           DC.B       0x02                     ; '\x02'
+  0x20000264:  01           DC.B       0x01                     ; '\x01'
+  0x20000265:  00           DC.B       0x00                     ; '\0'
+  0x20000266:  00           DC.B       0x00                     ; '\0'
+  0x20000267:  01           DC.B       0x01                     ; '\x01'
+  0x20000268:  00           DC.B       0x00                     ; '\0'
+  0x20000269:  54           DC.B       0x54                     ; 'T'
+  0x2000026A:  00           DC.B       0x00                     ; '\0'
+  0x2000026B:  00           DC.B       0x00                     ; '\0'
+  0x2000026C:  00           DC.B       0x00                     ; '\0'
+  0x2000026D:  00           DC.B       0x00                     ; '\0'
+  0x2000026E:  00           DC.B       0x00                     ; '\0'
+  0x2000026F:  00           DC.B       0x00                     ; '\0'
+  0x20000270:  00           DC.B       0x00                     ; '\0'
+  0x20000271:  00           DC.B       0x00                     ; '\0'
+  0x20000272:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000273:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000274:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000275:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000276:  EC           DC.B       0xEC                     ; '\xEC'
+  0x20000277:  00           DC.B       0x00                     ; '\0'
+  0x20000278:  00           DC.B       0x00                     ; '\0'
+  0x20000279:  08           DC.B       0x08                     ; '\b'
+  0x2000027A:  0A           DC.B       0x0A                     ; '\n'
+  0x2000027B:  00           DC.B       0x00                     ; '\0'
+  0x2000027C:  00           DC.B       0x00                     ; '\0'
+  0x2000027D:  00           DC.B       0x00                     ; '\0'
+  0x2000027E:  02           DC.B       0x02                     ; '\x02'
+  0x2000027F:  01           DC.B       0x01                     ; '\x01'
+  0x20000280:  00           DC.B       0x00                     ; '\0'
+  0x20000281:  00           DC.B       0x00                     ; '\0'
+  0x20000282:  01           DC.B       0x01                     ; '\x01'
+  0x20000283:  00           DC.B       0x00                     ; '\0'
+  0x20000284:  56           DC.B       0x56                     ; 'V'
+  0x20000285:  00           DC.B       0x00                     ; '\0'
+  0x20000286:  00           DC.B       0x00                     ; '\0'
+  0x20000287:  00           DC.B       0x00                     ; '\0'
+  0x20000288:  00           DC.B       0x00                     ; '\0'
+  0x20000289:  00           DC.B       0x00                     ; '\0'
+  0x2000028A:  00           DC.B       0x00                     ; '\0'
+  0x2000028B:  00           DC.B       0x00                     ; '\0'
+  0x2000028C:  00           DC.B       0x00                     ; '\0'
+  0x2000028D:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000028E:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000028F:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000290:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000291:  EC           DC.B       0xEC                     ; '\xEC'
+  0x20000292:  00           DC.B       0x00                     ; '\0'
+  0x20000293:  00           DC.B       0x00                     ; '\0'
+  0x20000294:  08           DC.B       0x08                     ; '\b'
+  0x20000295:  0C           DC.B       0x0C                     ; '\x0C'
+  0x20000296:  00           DC.B       0x00                     ; '\0'
+  0x20000297:  00           DC.B       0x00                     ; '\0'
+  0x20000298:  00           DC.B       0x00                     ; '\0'
+  0x20000299:  02           DC.B       0x02                     ; '\x02'
+  0x2000029A:  01           DC.B       0x01                     ; '\x01'
+  0x2000029B:  00           DC.B       0x00                     ; '\0'
+  0x2000029C:  00           DC.B       0x00                     ; '\0'
+  0x2000029D:  01           DC.B       0x01                     ; '\x01'
+  0x2000029E:  00           DC.B       0x00                     ; '\0'
+  0x2000029F:  57           DC.B       0x57                     ; 'W'
+  0x200002A0:  00           DC.B       0x00                     ; '\0'
+  0x200002A1:  00           DC.B       0x00                     ; '\0'
+  0x200002A2:  00           DC.B       0x00                     ; '\0'
+  0x200002A3:  00           DC.B       0x00                     ; '\0'
+  0x200002A4:  00           DC.B       0x00                     ; '\0'
+  0x200002A5:  00           DC.B       0x00                     ; '\0'
+  0x200002A6:  00           DC.B       0x00                     ; '\0'
+  0x200002A7:  00           DC.B       0x00                     ; '\0'
+  0x200002A8:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002A9:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002AA:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002AB:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002AC:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200002AD:  02           DC.B       0x02                     ; '\x02'
+  0x200002AE:  00           DC.B       0x00                     ; '\0'
+  0x200002AF:  08           DC.B       0x08                     ; '\b'
+  0x200002B0:  06           DC.B       0x06                     ; '\x06'
+  0x200002B1:  00           DC.B       0x00                     ; '\0'
+  0x200002B2:  00           DC.B       0x00                     ; '\0'
+  0x200002B3:  00           DC.B       0x00                     ; '\0'
+  0x200002B4:  80           DC.B       0x80                     ; '\x80'
+  0x200002B5:  01           DC.B       0x01                     ; '\x01'
+  0x200002B6:  00           DC.B       0x00                     ; '\0'
+  0x200002B7:  00           DC.B       0x00                     ; '\0'
+  0x200002B8:  01           DC.B       0x01                     ; '\x01'
+  0x200002B9:  00           DC.B       0x00                     ; '\0'
+  0x200002BA:  54           DC.B       0x54                     ; 'T'
+  0x200002BB:  84           DC.B       0x84                     ; '\x84'
+  0x200002BC:  01           DC.B       0x01                     ; '\x01'
+  0x200002BD:  00           DC.B       0x00                     ; '\0'
+  0x200002BE:  00           DC.B       0x00                     ; '\0'
+  0x200002BF:  32           DC.B       0x32                     ; '2'
+  0x200002C0:  02           DC.B       0x02                     ; '\x02'
+  0x200002C1:  00           DC.B       0x00                     ; '\0'
+  0x200002C2:  00           DC.B       0x00                     ; '\0'
+  0x200002C3:  01           DC.B       0x01                     ; '\x01'
+  0x200002C4:  00           DC.B       0x00                     ; '\0'
+  0x200002C5:  54           DC.B       0x54                     ; 'T'
+  0x200002C6:  7E           DC.B       0x7E                     ; '~'
+  0x200002C7:  02           DC.B       0x02                     ; '\x02'
+  0x200002C8:  00           DC.B       0x00                     ; '\0'
+  0x200002C9:  00           DC.B       0x00                     ; '\0'
+  0x200002CA:  70           DC.B       0x70                     ; 'p'
+  0x200002CB:  03           DC.B       0x03                     ; '\x03'
+  0x200002CC:  00           DC.B       0x00                     ; '\0'
+  0x200002CD:  00           DC.B       0x00                     ; '\0'
+  0x200002CE:  01           DC.B       0x01                     ; '\x01'
+  0x200002CF:  00           DC.B       0x00                     ; '\0'
+  0x200002D0:  54           DC.B       0x54                     ; 'T'
+  0x200002D1:  72           DC.B       0x72                     ; 'r'
+  0x200002D2:  03           DC.B       0x03                     ; '\x03'
+  0x200002D3:  00           DC.B       0x00                     ; '\0'
+  0x200002D4:  00           DC.B       0x00                     ; '\0'
+  0x200002D5:  92           DC.B       0x92                     ; '\x92'
+  0x200002D6:  03           DC.B       0x03                     ; '\x03'
+  0x200002D7:  00           DC.B       0x00                     ; '\0'
+  0x200002D8:  00           DC.B       0x00                     ; '\0'
+  0x200002D9:  01           DC.B       0x01                     ; '\x01'
+  0x200002DA:  00           DC.B       0x00                     ; '\0'
+  0x200002DB:  54           DC.B       0x54                     ; 'T'
+  0x200002DC:  00           DC.B       0x00                     ; '\0'
+  0x200002DD:  00           DC.B       0x00                     ; '\0'
+  0x200002DE:  00           DC.B       0x00                     ; '\0'
+  0x200002DF:  00           DC.B       0x00                     ; '\0'
+  0x200002E0:  00           DC.B       0x00                     ; '\0'
+  0x200002E1:  00           DC.B       0x00                     ; '\0'
+  0x200002E2:  00           DC.B       0x00                     ; '\0'
+  0x200002E3:  00           DC.B       0x00                     ; '\0'
+  0x200002E4:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E5:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E6:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E7:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E8:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200002E9:  02           DC.B       0x02                     ; '\x02'
+  0x200002EA:  00           DC.B       0x00                     ; '\0'
+  0x200002EB:  08           DC.B       0x08                     ; '\b'
+  0x200002EC:  10           DC.B       0x10                     ; '\x10'
+  0x200002ED:  00           DC.B       0x00                     ; '\0'
+  0x200002EE:  00           DC.B       0x00                     ; '\0'
+  0x200002EF:  00           DC.B       0x00                     ; '\0'
+  0x200002F0:  B6           DC.B       0xB6                     ; '\xB6'
+  0x200002F1:  00           DC.B       0x00                     ; '\0'
+  0x200002F2:  00           DC.B       0x00                     ; '\0'
+  0x200002F3:  00           DC.B       0x00                     ; '\0'
+  0x200002F4:  01           DC.B       0x01                     ; '\x01'
+  0x200002F5:  00           DC.B       0x00                     ; '\0'
+  0x200002F6:  53           DC.B       0x53                     ; 'S'
+  0x200002F7:  EC           DC.B       0xEC                     ; '\xEC'
+  0x200002F8:  00           DC.B       0x00                     ; '\0'
+  0x200002F9:  00           DC.B       0x00                     ; '\0'
+  0x200002FA:  00           DC.B       0x00                     ; '\0'
+  0x200002FB:  3E           DC.B       0x3E                     ; '>'
+  0x200002FC:  01           DC.B       0x01                     ; '\x01'
+  0x200002FD:  00           DC.B       0x00                     ; '\0'
+  0x200002FE:  00           DC.B       0x00                     ; '\0'
+  0x200002FF:  01           DC.B       0x01                     ; '\x01'
+  0x20000300:  00           DC.B       0x00                     ; '\0'
+  0x20000301:  53           DC.B       0x53                     ; 'S'
+  0x20000302:  56           DC.B       0x56                     ; 'V'
+  0x20000303:  01           DC.B       0x01                     ; '\x01'
+  0x20000304:  00           DC.B       0x00                     ; '\0'
+  0x20000305:  00           DC.B       0x00                     ; '\0'
+  0x20000306:  5E           DC.B       0x5E                     ; '^'
+  0x20000307:  01           DC.B       0x01                     ; '\x01'
+  0x20000308:  00           DC.B       0x00                     ; '\0'
+  0x20000309:  00           DC.B       0x00                     ; '\0'
+  0x2000030A:  01           DC.B       0x01                     ; '\x01'
+  0x2000030B:  00           DC.B       0x00                     ; '\0'
+  0x2000030C:  53           DC.B       0x53                     ; 'S'
+  0x2000030D:  72           DC.B       0x72                     ; 'r'
+  0x2000030E:  01           DC.B       0x01                     ; '\x01'
+  0x2000030F:  00           DC.B       0x00                     ; '\0'
+  0x20000310:  00           DC.B       0x00                     ; '\0'
+  0x20000311:  80           DC.B       0x80                     ; '\x80'
+  0x20000312:  01           DC.B       0x01                     ; '\x01'
+  0x20000313:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc._SEGGER_RTT from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=168, align=4

+
+
_SEGGER_RTT:
+  0x20000314:  30           DC.B       0x30                     ; '0'
+  0x20000315:  31           DC.B       0x31                     ; '1'
+  0x20000316:  32           DC.B       0x32                     ; '2'
+  0x20000317:  33           DC.B       0x33                     ; '3'
+  0x20000318:  34           DC.B       0x34                     ; '4'
+  0x20000319:  35           DC.B       0x35                     ; '5'
+  0x2000031A:  36           DC.B       0x36                     ; '6'
+  0x2000031B:  37           DC.B       0x37                     ; '7'
+  0x2000031C:  38           DC.B       0x38                     ; '8'
+  0x2000031D:  39           DC.B       0x39                     ; '9'
+  0x2000031E:  41           DC.B       0x41                     ; 'A'
+  0x2000031F:  42           DC.B       0x42                     ; 'B'
+  0x20000320:  43           DC.B       0x43                     ; 'C'
+  0x20000321:  44           DC.B       0x44                     ; 'D'
+  0x20000322:  45           DC.B       0x45                     ; 'E'
+  0x20000323:  46           DC.B       0x46                     ; 'F'
+  0x20000324:  00           DC.B       0x00                     ; '\0'
+  0x20000325:  00           DC.B       0x00                     ; '\0'
+  0x20000326:  00           DC.B       0x00                     ; '\0'
+  0x20000327:  00           DC.B       0x00                     ; '\0'
+  0x20000328:  00           DC.B       0x00                     ; '\0'
+  0x20000329:  00           DC.B       0x00                     ; '\0'
+  0x2000032A:  54           DC.B       0x54                     ; 'T'
+  0x2000032B:  54           DC.B       0x54                     ; 'T'
+  0x2000032C:  52           DC.B       0x52                     ; 'R'
+  0x2000032D:  20           DC.B       0x20                     ; ' '
+  0x2000032E:  52           DC.B       0x52                     ; 'R'
+  0x2000032F:  45           DC.B       0x45                     ; 'E'
+  0x20000330:  47           DC.B       0x47                     ; 'G'
+  0x20000331:  47           DC.B       0x47                     ; 'G'
+  0x20000332:  45           DC.B       0x45                     ; 'E'
+  0x20000333:  53           DC.B       0x53                     ; 'S'
+  0x20000334:  00           DC.B       0x00                     ; '\0'
+  0x20000335:  54           DC.B       0x54                     ; 'T'
+  0x20000336:  65           DC.B       0x65                     ; 'e'
+  0x20000337:  72           DC.B       0x72                     ; 'r'
+  0x20000338:  6D           DC.B       0x6D                     ; 'm'
+  0x20000339:  69           DC.B       0x69                     ; 'i'
+  0x2000033A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000033B:  61           DC.B       0x61                     ; 'a'
+  0x2000033C:  6C           DC.B       0x6C                     ; 'l'
+  0x2000033D:  00           DC.B       0x00                     ; '\0'
+  0x2000033E:  00           DC.B       0x00                     ; '\0'
+  0x2000033F:  53           DC.B       0x53                     ; 'S'
+  0x20000340:  45           DC.B       0x45                     ; 'E'
+  0x20000341:  47           DC.B       0x47                     ; 'G'
+  0x20000342:  47           DC.B       0x47                     ; 'G'
+  0x20000343:  45           DC.B       0x45                     ; 'E'
+  0x20000344:  52           DC.B       0x52                     ; 'R'
+  0x20000345:  20           DC.B       0x20                     ; ' '
+  0x20000346:  43           DC.B       0x43                     ; 'C'
+  0x20000347:  2F           DC.B       0x2F                     ; '/'
+  0x20000348:  43           DC.B       0x43                     ; 'C'
+  0x20000349:  2B           DC.B       0x2B                     ; '+'
+  0x2000034A:  2B           DC.B       0x2B                     ; '+'
+  0x2000034B:  20           DC.B       0x20                     ; ' '
+  0x2000034C:  63           DC.B       0x63                     ; 'c'
+  0x2000034D:  6F           DC.B       0x6F                     ; 'o'
+  0x2000034E:  6D           DC.B       0x6D                     ; 'm'
+  0x2000034F:  70           DC.B       0x70                     ; 'p'
+  0x20000350:  69           DC.B       0x69                     ; 'i'
+  0x20000351:  6C           DC.B       0x6C                     ; 'l'
+  0x20000352:  65           DC.B       0x65                     ; 'e'
+  0x20000353:  72           DC.B       0x72                     ; 'r'
+  0x20000354:  20           DC.B       0x20                     ; ' '
+  0x20000355:  76           DC.B       0x76                     ; 'v'
+  0x20000356:  65           DC.B       0x65                     ; 'e'
+  0x20000357:  72           DC.B       0x72                     ; 'r'
+  0x20000358:  73           DC.B       0x73                     ; 's'
+  0x20000359:  69           DC.B       0x69                     ; 'i'
+  0x2000035A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000035B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000035C:  20           DC.B       0x20                     ; ' '
+  0x2000035D:  32           DC.B       0x32                     ; '2'
+  0x2000035E:  30           DC.B       0x30                     ; '0'
+  0x2000035F:  2E           DC.B       0x2E                     ; '.'
+  0x20000360:  31           DC.B       0x31                     ; '1'
+  0x20000361:  2E           DC.B       0x2E                     ; '.'
+  0x20000362:  32           DC.B       0x32                     ; '2'
+  0x20000363:  20           DC.B       0x20                     ; ' '
+  0x20000364:  28           DC.B       0x28                     ; '('
+  0x20000365:  62           DC.B       0x62                     ; 'b'
+  0x20000366:  61           DC.B       0x61                     ; 'a'
+  0x20000367:  73           DC.B       0x73                     ; 's'
+  0x20000368:  65           DC.B       0x65                     ; 'e'
+  0x20000369:  64           DC.B       0x64                     ; 'd'
+  0x2000036A:  20           DC.B       0x20                     ; ' '
+  0x2000036B:  6F           DC.B       0x6F                     ; 'o'
+  0x2000036C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000036D:  20           DC.B       0x20                     ; ' '
+  0x2000036E:  63           DC.B       0x63                     ; 'c'
+  0x2000036F:  6C           DC.B       0x6C                     ; 'l'
+  0x20000370:  61           DC.B       0x61                     ; 'a'
+  0x20000371:  6E           DC.B       0x6E                     ; 'n'
+  0x20000372:  67           DC.B       0x67                     ; 'g'
+  0x20000373:  20           DC.B       0x20                     ; ' '
+  0x20000374:  32           DC.B       0x32                     ; '2'
+  0x20000375:  30           DC.B       0x30                     ; '0'
+  0x20000376:  2E           DC.B       0x2E                     ; '.'
+  0x20000377:  31           DC.B       0x31                     ; '1'
+  0x20000378:  2E           DC.B       0x2E                     ; '.'
+  0x20000379:  38           DC.B       0x38                     ; '8'
+  0x2000037A:  29           DC.B       0x29                     ; ')'
+  0x2000037B:  00           DC.B       0x00                     ; '\0'
+  0x2000037C:  41           DC.B       0x41                     ; 'A'
+  0x2000037D:  35           DC.B       0x35                     ; '5'
+  0x2000037E:  00           DC.B       0x00                     ; '\0'
+  0x2000037F:  00           DC.B       0x00                     ; '\0'
+  0x20000380:  00           DC.B       0x00                     ; '\0'
+  0x20000381:  61           DC.B       0x61                     ; 'a'
+  0x20000382:  65           DC.B       0x65                     ; 'e'
+  0x20000383:  61           DC.B       0x61                     ; 'a'
+  0x20000384:  62           DC.B       0x62                     ; 'b'
+  0x20000385:  69           DC.B       0x69                     ; 'i'
+  0x20000386:  00           DC.B       0x00                     ; '\0'
+  0x20000387:  01           DC.B       0x01                     ; '\x01'
+  0x20000388:  2B           DC.B       0x2B                     ; '+'
+  0x20000389:  00           DC.B       0x00                     ; '\0'
+  0x2000038A:  00           DC.B       0x00                     ; '\0'
+  0x2000038B:  00           DC.B       0x00                     ; '\0'
+  0x2000038C:  43           DC.B       0x43                     ; 'C'
+  0x2000038D:  32           DC.B       0x32                     ; '2'
+  0x2000038E:  2E           DC.B       0x2E                     ; '.'
+  0x2000038F:  30           DC.B       0x30                     ; '0'
+  0x20000390:  39           DC.B       0x39                     ; '9'
+  0x20000391:  00           DC.B       0x00                     ; '\0'
+  0x20000392:  06           DC.B       0x06                     ; '\x06'
+  0x20000393:  0C           DC.B       0x0C                     ; '\x0C'
+  0x20000394:  07           DC.B       0x07                     ; '\x07'
+  0x20000395:  4D           DC.B       0x4D                     ; 'M'
+  0x20000396:  08           DC.B       0x08                     ; '\b'
+  0x20000397:  00           DC.B       0x00                     ; '\0'
+  0x20000398:  09           DC.B       0x09                     ; '\t'
+  0x20000399:  01           DC.B       0x01                     ; '\x01'
+  0x2000039A:  0E           DC.B       0x0E                     ; '\x0E'
+  0x2000039B:  00           DC.B       0x00                     ; '\0'
+  0x2000039C:  11           DC.B       0x11                     ; '\x11'
+  0x2000039D:  01           DC.B       0x01                     ; '\x01'
+  0x2000039E:  12           DC.B       0x12                     ; '\x12'
+  0x2000039F:  04           DC.B       0x04                     ; '\x04'
+  0x200003A0:  14           DC.B       0x14                     ; '\x14'
+  0x200003A1:  01           DC.B       0x01                     ; '\x01'
+  0x200003A2:  15           DC.B       0x15                     ; '\x15'
+  0x200003A3:  00           DC.B       0x00                     ; '\0'
+  0x200003A4:  17           DC.B       0x17                     ; '\x17'
+  0x200003A5:  03           DC.B       0x03                     ; '\x03'
+  0x200003A6:  18           DC.B       0x18                     ; '\x18'
+  0x200003A7:  01           DC.B       0x01                     ; '\x01'
+  0x200003A8:  19           DC.B       0x19                     ; '\x19'
+  0x200003A9:  01           DC.B       0x01                     ; '\x01'
+  0x200003AA:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200003AB:  01           DC.B       0x01                     ; '\x01'
+  0x200003AC:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200003AD:  04           DC.B       0x04                     ; '\x04'
+  0x200003AE:  22           DC.B       0x22                     ; '\"'
+  0x200003AF:  00           DC.B       0x00                     ; '\0'
+  0x200003B0:  26           DC.B       0x26                     ; '&'
+  0x200003B1:  01           DC.B       0x01                     ; '\x01'
+  0x200003B2:  00           DC.B       0x00                     ; '\0'
+  0x200003B3:  00           DC.B       0x00                     ; '\0'
+  0x200003B4:  00           DC.B       0x00                     ; '\0'
+  0x200003B5:  00           DC.B       0x00                     ; '\0'
+  0x200003B6:  00           DC.B       0x00                     ; '\0'
+  0x200003B7:  00           DC.B       0x00                     ; '\0'
+  0x200003B8:  00           DC.B       0x00                     ; '\0'
+  0x200003B9:  00           DC.B       0x00                     ; '\0'
+  0x200003BA:  00           DC.B       0x00                     ; '\0'
+  0x200003BB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.huart1 from PowerPro_lto.o, size=148, align=4

+
+
huart1:
+  0x200003BC:  73           DC.B       0x73                     ; 's'
+  0x200003BD:  65           DC.B       0x65                     ; 'e'
+  0x200003BE:  74           DC.B       0x74                     ; 't'
+  0x200003BF:  7A           DC.B       0x7A                     ; 'z'
+  0x200003C0:  65           DC.B       0x65                     ; 'e'
+  0x200003C1:  20           DC.B       0x20                     ; ' '
+  0x200003C2:  6F           DC.B       0x6F                     ; 'o'
+  0x200003C3:  70           DC.B       0x70                     ; 'p'
+  0x200003C4:  74           DC.B       0x74                     ; 't'
+  0x200003C5:  69           DC.B       0x69                     ; 'i'
+  0x200003C6:  6F           DC.B       0x6F                     ; 'o'
+  0x200003C7:  6E           DC.B       0x6E                     ; 'n'
+  0x200003C8:  20           DC.B       0x20                     ; ' '
+  0x200003C9:  62           DC.B       0x62                     ; 'b'
+  0x200003CA:  79           DC.B       0x79                     ; 'y'
+  0x200003CB:  74           DC.B       0x74                     ; 't'
+  0x200003CC:  65           DC.B       0x65                     ; 'e'
+  0x200003CD:  0D           DC.B       0x0D                     ; '\r'
+  0x200003CE:  00           DC.B       0x00                     ; '\0'
+  0x200003CF:  4B           DC.B       0x4B                     ; 'K'
+  0x200003D0:  6F           DC.B       0x6F                     ; 'o'
+  0x200003D1:  6E           DC.B       0x6E                     ; 'n'
+  0x200003D2:  66           DC.B       0x66                     ; 'f'
+  0x200003D3:  69           DC.B       0x69                     ; 'i'
+  0x200003D4:  67           DC.B       0x67                     ; 'g'
+  0x200003D5:  20           DC.B       0x20                     ; ' '
+  0x200003D6:  76           DC.B       0x76                     ; 'v'
+  0x200003D7:  6F           DC.B       0x6F                     ; 'o'
+  0x200003D8:  72           DC.B       0x72                     ; 'r'
+  0x200003D9:  68           DC.B       0x68                     ; 'h'
+  0x200003DA:  61           DC.B       0x61                     ; 'a'
+  0x200003DB:  6E           DC.B       0x6E                     ; 'n'
+  0x200003DC:  64           DC.B       0x64                     ; 'd'
+  0x200003DD:  65           DC.B       0x65                     ; 'e'
+  0x200003DE:  6E           DC.B       0x6E                     ; 'n'
+  0x200003DF:  0D           DC.B       0x0D                     ; '\r'
+  0x200003E0:  00           DC.B       0x00                     ; '\0'
+  0x200003E1:  4E           DC.B       0x4E                     ; 'N'
+  0x200003E2:  65           DC.B       0x65                     ; 'e'
+  0x200003E3:  75           DC.B       0x75                     ; 'u'
+  0x200003E4:  65           DC.B       0x65                     ; 'e'
+  0x200003E5:  20           DC.B       0x20                     ; ' '
+  0x200003E6:  56           DC.B       0x56                     ; 'V'
+  0x200003E7:  65           DC.B       0x65                     ; 'e'
+  0x200003E8:  72           DC.B       0x72                     ; 'r'
+  0x200003E9:  73           DC.B       0x73                     ; 's'
+  0x200003EA:  69           DC.B       0x69                     ; 'i'
+  0x200003EB:  6F           DC.B       0x6F                     ; 'o'
+  0x200003EC:  6E           DC.B       0x6E                     ; 'n'
+  0x200003ED:  20           DC.B       0x20                     ; ' '
+  0x200003EE:  50           DC.B       0x50                     ; 'P'
+  0x200003EF:  61           DC.B       0x61                     ; 'a'
+  0x200003F0:  72           DC.B       0x72                     ; 'r'
+  0x200003F1:  61           DC.B       0x61                     ; 'a'
+  0x200003F2:  6D           DC.B       0x6D                     ; 'm'
+  0x200003F3:  65           DC.B       0x65                     ; 'e'
+  0x200003F4:  74           DC.B       0x74                     ; 't'
+  0x200003F5:  65           DC.B       0x65                     ; 'e'
+  0x200003F6:  72           DC.B       0x72                     ; 'r'
+  0x200003F7:  20           DC.B       0x20                     ; ' '
+  0x200003F8:  65           DC.B       0x65                     ; 'e'
+  0x200003F9:  72           DC.B       0x72                     ; 'r'
+  0x200003FA:  6B           DC.B       0x6B                     ; 'k'
+  0x200003FB:  61           DC.B       0x61                     ; 'a'
+  0x200003FC:  6E           DC.B       0x6E                     ; 'n'
+  0x200003FD:  6E           DC.B       0x6E                     ; 'n'
+  0x200003FE:  74           DC.B       0x74                     ; 't'
+  0x200003FF:  2C           DC.B       0x2C                     ; ','
+  0x20000400:  20           DC.B       0x20                     ; ' '
+  0x20000401:  73           DC.B       0x73                     ; 's'
+  0x20000402:  63           DC.B       0x63                     ; 'c'
+  0x20000403:  68           DC.B       0x68                     ; 'h'
+  0x20000404:  72           DC.B       0x72                     ; 'r'
+  0x20000405:  65           DC.B       0x65                     ; 'e'
+  0x20000406:  69           DC.B       0x69                     ; 'i'
+  0x20000407:  62           DC.B       0x62                     ; 'b'
+  0x20000408:  65           DC.B       0x65                     ; 'e'
+  0x20000409:  20           DC.B       0x20                     ; ' '
+  0x2000040A:  57           DC.B       0x57                     ; 'W'
+  0x2000040B:  65           DC.B       0x65                     ; 'e'
+  0x2000040C:  72           DC.B       0x72                     ; 'r'
+  0x2000040D:  6B           DC.B       0x6B                     ; 'k'
+  0x2000040E:  73           DC.B       0x73                     ; 's'
+  0x2000040F:  65           DC.B       0x65                     ; 'e'
+  0x20000410:  69           DC.B       0x69                     ; 'i'
+  0x20000411:  6E           DC.B       0x6E                     ; 'n'
+  0x20000412:  73           DC.B       0x73                     ; 's'
+  0x20000413:  74           DC.B       0x74                     ; 't'
+  0x20000414:  65           DC.B       0x65                     ; 'e'
+  0x20000415:  6C           DC.B       0x6C                     ; 'l'
+  0x20000416:  6C           DC.B       0x6C                     ; 'l'
+  0x20000417:  75           DC.B       0x75                     ; 'u'
+  0x20000418:  6E           DC.B       0x6E                     ; 'n'
+  0x20000419:  67           DC.B       0x67                     ; 'g'
+  0x2000041A:  0D           DC.B       0x0D                     ; '\r'
+  0x2000041B:  00           DC.B       0x00                     ; '\0'
+  0x2000041C:  45           DC.B       0x45                     ; 'E'
+  0x2000041D:  72           DC.B       0x72                     ; 'r'
+  0x2000041E:  73           DC.B       0x73                     ; 's'
+  0x2000041F:  74           DC.B       0x74                     ; 't'
+  0x20000420:  73           DC.B       0x73                     ; 's'
+  0x20000421:  74           DC.B       0x74                     ; 't'
+  0x20000422:  61           DC.B       0x61                     ; 'a'
+  0x20000423:  72           DC.B       0x72                     ; 'r'
+  0x20000424:  74           DC.B       0x74                     ; 't'
+  0x20000425:  20           DC.B       0x20                     ; ' '
+  0x20000426:  65           DC.B       0x65                     ; 'e'
+  0x20000427:  72           DC.B       0x72                     ; 'r'
+  0x20000428:  6B           DC.B       0x6B                     ; 'k'
+  0x20000429:  61           DC.B       0x61                     ; 'a'
+  0x2000042A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000042B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000042C:  74           DC.B       0x74                     ; 't'
+  0x2000042D:  2C           DC.B       0x2C                     ; ','
+  0x2000042E:  20           DC.B       0x20                     ; ' '
+  0x2000042F:  73           DC.B       0x73                     ; 's'
+  0x20000430:  63           DC.B       0x63                     ; 'c'
+  0x20000431:  68           DC.B       0x68                     ; 'h'
+  0x20000432:  72           DC.B       0x72                     ; 'r'
+  0x20000433:  65           DC.B       0x65                     ; 'e'
+  0x20000434:  69           DC.B       0x69                     ; 'i'
+  0x20000435:  62           DC.B       0x62                     ; 'b'
+  0x20000436:  65           DC.B       0x65                     ; 'e'
+  0x20000437:  20           DC.B       0x20                     ; ' '
+  0x20000438:  57           DC.B       0x57                     ; 'W'
+  0x20000439:  65           DC.B       0x65                     ; 'e'
+  0x2000043A:  72           DC.B       0x72                     ; 'r'
+  0x2000043B:  6B           DC.B       0x6B                     ; 'k'
+  0x2000043C:  73           DC.B       0x73                     ; 's'
+  0x2000043D:  65           DC.B       0x65                     ; 'e'
+  0x2000043E:  69           DC.B       0x69                     ; 'i'
+  0x2000043F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000440:  73           DC.B       0x73                     ; 's'
+  0x20000441:  74           DC.B       0x74                     ; 't'
+  0x20000442:  65           DC.B       0x65                     ; 'e'
+  0x20000443:  6C           DC.B       0x6C                     ; 'l'
+  0x20000444:  6C           DC.B       0x6C                     ; 'l'
+  0x20000445:  75           DC.B       0x75                     ; 'u'
+  0x20000446:  6E           DC.B       0x6E                     ; 'n'
+  0x20000447:  67           DC.B       0x67                     ; 'g'
+  0x20000448:  0D           DC.B       0x0D                     ; '\r'
+  0x20000449:  00           DC.B       0x00                     ; '\0'
+  0x2000044A:  64           DC.B       0x64                     ; 'd'
+  0x2000044B:  65           DC.B       0x65                     ; 'e'
+  0x2000044C:  62           DC.B       0x62                     ; 'b'
+  0x2000044D:  75           DC.B       0x75                     ; 'u'
+  0x2000044E:  67           DC.B       0x67                     ; 'g'
+  0x2000044F:  20           DC.B       0x20                     ; ' '
+
+

Section .bss.hadc1 from PowerPro_lto.o, size=100, align=4

+
+
hadc1:
+  0x20000450:  73           DC.B       0x73                     ; 's'
+  0x20000451:  65           DC.B       0x65                     ; 'e'
+  0x20000452:  74           DC.B       0x74                     ; 't'
+  0x20000453:  7A           DC.B       0x7A                     ; 'z'
+  0x20000454:  65           DC.B       0x65                     ; 'e'
+  0x20000455:  20           DC.B       0x20                     ; ' '
+  0x20000456:  6F           DC.B       0x6F                     ; 'o'
+  0x20000457:  70           DC.B       0x70                     ; 'p'
+  0x20000458:  74           DC.B       0x74                     ; 't'
+  0x20000459:  69           DC.B       0x69                     ; 'i'
+  0x2000045A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000045B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000045C:  20           DC.B       0x20                     ; ' '
+  0x2000045D:  62           DC.B       0x62                     ; 'b'
+  0x2000045E:  79           DC.B       0x79                     ; 'y'
+  0x2000045F:  74           DC.B       0x74                     ; 't'
+  0x20000460:  65           DC.B       0x65                     ; 'e'
+  0x20000461:  0D           DC.B       0x0D                     ; '\r'
+  0x20000462:  00           DC.B       0x00                     ; '\0'
+  0x20000463:  4B           DC.B       0x4B                     ; 'K'
+  0x20000464:  6F           DC.B       0x6F                     ; 'o'
+  0x20000465:  6E           DC.B       0x6E                     ; 'n'
+  0x20000466:  66           DC.B       0x66                     ; 'f'
+  0x20000467:  69           DC.B       0x69                     ; 'i'
+  0x20000468:  67           DC.B       0x67                     ; 'g'
+  0x20000469:  20           DC.B       0x20                     ; ' '
+  0x2000046A:  76           DC.B       0x76                     ; 'v'
+  0x2000046B:  6F           DC.B       0x6F                     ; 'o'
+  0x2000046C:  72           DC.B       0x72                     ; 'r'
+  0x2000046D:  68           DC.B       0x68                     ; 'h'
+  0x2000046E:  61           DC.B       0x61                     ; 'a'
+  0x2000046F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000470:  64           DC.B       0x64                     ; 'd'
+  0x20000471:  65           DC.B       0x65                     ; 'e'
+  0x20000472:  6E           DC.B       0x6E                     ; 'n'
+  0x20000473:  0D           DC.B       0x0D                     ; '\r'
+  0x20000474:  00           DC.B       0x00                     ; '\0'
+  0x20000475:  4E           DC.B       0x4E                     ; 'N'
+  0x20000476:  65           DC.B       0x65                     ; 'e'
+  0x20000477:  75           DC.B       0x75                     ; 'u'
+  0x20000478:  65           DC.B       0x65                     ; 'e'
+  0x20000479:  20           DC.B       0x20                     ; ' '
+  0x2000047A:  56           DC.B       0x56                     ; 'V'
+  0x2000047B:  65           DC.B       0x65                     ; 'e'
+  0x2000047C:  72           DC.B       0x72                     ; 'r'
+  0x2000047D:  73           DC.B       0x73                     ; 's'
+  0x2000047E:  69           DC.B       0x69                     ; 'i'
+  0x2000047F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000480:  6E           DC.B       0x6E                     ; 'n'
+  0x20000481:  20           DC.B       0x20                     ; ' '
+  0x20000482:  50           DC.B       0x50                     ; 'P'
+  0x20000483:  61           DC.B       0x61                     ; 'a'
+  0x20000484:  72           DC.B       0x72                     ; 'r'
+  0x20000485:  61           DC.B       0x61                     ; 'a'
+  0x20000486:  6D           DC.B       0x6D                     ; 'm'
+  0x20000487:  65           DC.B       0x65                     ; 'e'
+  0x20000488:  74           DC.B       0x74                     ; 't'
+  0x20000489:  65           DC.B       0x65                     ; 'e'
+  0x2000048A:  72           DC.B       0x72                     ; 'r'
+  0x2000048B:  20           DC.B       0x20                     ; ' '
+  0x2000048C:  65           DC.B       0x65                     ; 'e'
+  0x2000048D:  72           DC.B       0x72                     ; 'r'
+  0x2000048E:  6B           DC.B       0x6B                     ; 'k'
+  0x2000048F:  61           DC.B       0x61                     ; 'a'
+  0x20000490:  6E           DC.B       0x6E                     ; 'n'
+  0x20000491:  6E           DC.B       0x6E                     ; 'n'
+  0x20000492:  74           DC.B       0x74                     ; 't'
+  0x20000493:  2C           DC.B       0x2C                     ; ','
+  0x20000494:  20           DC.B       0x20                     ; ' '
+  0x20000495:  73           DC.B       0x73                     ; 's'
+  0x20000496:  63           DC.B       0x63                     ; 'c'
+  0x20000497:  68           DC.B       0x68                     ; 'h'
+  0x20000498:  72           DC.B       0x72                     ; 'r'
+  0x20000499:  65           DC.B       0x65                     ; 'e'
+  0x2000049A:  69           DC.B       0x69                     ; 'i'
+  0x2000049B:  62           DC.B       0x62                     ; 'b'
+  0x2000049C:  65           DC.B       0x65                     ; 'e'
+  0x2000049D:  20           DC.B       0x20                     ; ' '
+  0x2000049E:  57           DC.B       0x57                     ; 'W'
+  0x2000049F:  65           DC.B       0x65                     ; 'e'
+  0x200004A0:  72           DC.B       0x72                     ; 'r'
+  0x200004A1:  6B           DC.B       0x6B                     ; 'k'
+  0x200004A2:  73           DC.B       0x73                     ; 's'
+  0x200004A3:  65           DC.B       0x65                     ; 'e'
+  0x200004A4:  69           DC.B       0x69                     ; 'i'
+  0x200004A5:  6E           DC.B       0x6E                     ; 'n'
+  0x200004A6:  73           DC.B       0x73                     ; 's'
+  0x200004A7:  74           DC.B       0x74                     ; 't'
+  0x200004A8:  65           DC.B       0x65                     ; 'e'
+  0x200004A9:  6C           DC.B       0x6C                     ; 'l'
+  0x200004AA:  6C           DC.B       0x6C                     ; 'l'
+  0x200004AB:  75           DC.B       0x75                     ; 'u'
+  0x200004AC:  6E           DC.B       0x6E                     ; 'n'
+  0x200004AD:  67           DC.B       0x67                     ; 'g'
+  0x200004AE:  0D           DC.B       0x0D                     ; '\r'
+  0x200004AF:  00           DC.B       0x00                     ; '\0'
+  0x200004B0:  45           DC.B       0x45                     ; 'E'
+  0x200004B1:  72           DC.B       0x72                     ; 'r'
+  0x200004B2:  73           DC.B       0x73                     ; 's'
+  0x200004B3:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.hdma_usart1_tx from PowerPro_lto.o, size=92, align=4

+
+
hdma_usart1_tx:
+  0x200004B4:  00           DC.B       0x00                     ; '\0'
+  0x200004B5:  1B           DC.B       0x1B                     ; '\x1B'
+  0x200004B6:  B7           DC.B       0xB7                     ; '\xB7'
+  0x200004B7:  00           DC.B       0x00                     ; '\0'
+  0x200004B8:  04           DC.B       0x04                     ; '\x04'
+  0x200004B9:  00           DC.B       0x00                     ; '\0'
+  0x200004BA:  00           DC.B       0x00                     ; '\0'
+  0x200004BB:  00           DC.B       0x00                     ; '\0'
+  0x200004BC:  00           DC.B       0x00                     ; '\0'
+  0x200004BD:  00           DC.B       0x00                     ; '\0'
+  0x200004BE:  00           DC.B       0x00                     ; '\0'
+  0x200004BF:  00           DC.B       0x00                     ; '\0'
+  0x200004C0:  00           DC.B       0x00                     ; '\0'
+  0x200004C1:  00           DC.B       0x00                     ; '\0'
+  0x200004C2:  00           DC.B       0x00                     ; '\0'
+  0x200004C3:  00           DC.B       0x00                     ; '\0'
+  0x200004C4:  00           DC.B       0x00                     ; '\0'
+  0x200004C5:  00           DC.B       0x00                     ; '\0'
+  0x200004C6:  00           DC.B       0x00                     ; '\0'
+  0x200004C7:  00           DC.B       0x00                     ; '\0'
+  0x200004C8:  00           DC.B       0x00                     ; '\0'
+  0x200004C9:  00           DC.B       0x00                     ; '\0'
+  0x200004CA:  00           DC.B       0x00                     ; '\0'
+  0x200004CB:  00           DC.B       0x00                     ; '\0'
+  0x200004CC:  00           DC.B       0x00                     ; '\0'
+  0x200004CD:  00           DC.B       0x00                     ; '\0'
+  0x200004CE:  00           DC.B       0x00                     ; '\0'
+  0x200004CF:  00           DC.B       0x00                     ; '\0'
+  0x200004D0:  00           DC.B       0x00                     ; '\0'
+  0x200004D1:  00           DC.B       0x00                     ; '\0'
+  0x200004D2:  00           DC.B       0x00                     ; '\0'
+  0x200004D3:  00           DC.B       0x00                     ; '\0'
+  0x200004D4:  00           DC.B       0x00                     ; '\0'
+  0x200004D5:  00           DC.B       0x00                     ; '\0'
+  0x200004D6:  00           DC.B       0x00                     ; '\0'
+  0x200004D7:  00           DC.B       0x00                     ; '\0'
+  0x200004D8:  00           DC.B       0x00                     ; '\0'
+  0x200004D9:  00           DC.B       0x00                     ; '\0'
+  0x200004DA:  00           DC.B       0x00                     ; '\0'
+  0x200004DB:  00           DC.B       0x00                     ; '\0'
+  0x200004DC:  01           DC.B       0x01                     ; '\x01'
+  0x200004DD:  00           DC.B       0x00                     ; '\0'
+  0x200004DE:  00           DC.B       0x00                     ; '\0'
+  0x200004DF:  00           DC.B       0x00                     ; '\0'
+  0x200004E0:  02           DC.B       0x02                     ; '\x02'
+  0x200004E1:  00           DC.B       0x00                     ; '\0'
+  0x200004E2:  00           DC.B       0x00                     ; '\0'
+  0x200004E3:  00           DC.B       0x00                     ; '\0'
+  0x200004E4:  03           DC.B       0x03                     ; '\x03'
+  0x200004E5:  00           DC.B       0x00                     ; '\0'
+  0x200004E6:  00           DC.B       0x00                     ; '\0'
+  0x200004E7:  00           DC.B       0x00                     ; '\0'
+  0x200004E8:  04           DC.B       0x04                     ; '\x04'
+  0x200004E9:  00           DC.B       0x00                     ; '\0'
+  0x200004EA:  00           DC.B       0x00                     ; '\0'
+  0x200004EB:  00           DC.B       0x00                     ; '\0'
+  0x200004EC:  06           DC.B       0x06                     ; '\x06'
+  0x200004ED:  00           DC.B       0x00                     ; '\0'
+  0x200004EE:  00           DC.B       0x00                     ; '\0'
+  0x200004EF:  00           DC.B       0x00                     ; '\0'
+  0x200004F0:  07           DC.B       0x07                     ; '\x07'
+  0x200004F1:  00           DC.B       0x00                     ; '\0'
+  0x200004F2:  00           DC.B       0x00                     ; '\0'
+  0x200004F3:  00           DC.B       0x00                     ; '\0'
+  0x200004F4:  08           DC.B       0x08                     ; '\b'
+  0x200004F5:  00           DC.B       0x00                     ; '\0'
+  0x200004F6:  00           DC.B       0x00                     ; '\0'
+  0x200004F7:  00           DC.B       0x00                     ; '\0'
+  0x200004F8:  09           DC.B       0x09                     ; '\t'
+  0x200004F9:  00           DC.B       0x00                     ; '\0'
+  0x200004FA:  00           DC.B       0x00                     ; '\0'
+  0x200004FB:  00           DC.B       0x00                     ; '\0'
+  0x200004FC:  00           DC.B       0x00                     ; '\0'
+  0x200004FD:  00           DC.B       0x00                     ; '\0'
+  0x200004FE:  00           DC.B       0x00                     ; '\0'
+  0x200004FF:  00           DC.B       0x00                     ; '\0'
+  0x20000500:  00           DC.B       0x00                     ; '\0'
+  0x20000501:  00           DC.B       0x00                     ; '\0'
+  0x20000502:  00           DC.B       0x00                     ; '\0'
+  0x20000503:  00           DC.B       0x00                     ; '\0'
+  0x20000504:  00           DC.B       0x00                     ; '\0'
+  0x20000505:  00           DC.B       0x00                     ; '\0'
+  0x20000506:  00           DC.B       0x00                     ; '\0'
+  0x20000507:  00           DC.B       0x00                     ; '\0'
+  0x20000508:  00           DC.B       0x00                     ; '\0'
+  0x20000509:  00           DC.B       0x00                     ; '\0'
+  0x2000050A:  00           DC.B       0x00                     ; '\0'
+  0x2000050B:  00           DC.B       0x00                     ; '\0'
+  0x2000050C:  01           DC.B       0x01                     ; '\x01'
+  0x2000050D:  00           DC.B       0x00                     ; '\0'
+  0x2000050E:  00           DC.B       0x00                     ; '\0'
+  0x2000050F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.hdma_usart1_rx from PowerPro_lto.o, size=92, align=4

+
+
hdma_usart1_rx:
+  0x20000510:  00           DC.B       0x00                     ; '\0'
+  0x20000511:  1B           DC.B       0x1B                     ; '\x1B'
+  0x20000512:  B7           DC.B       0xB7                     ; '\xB7'
+  0x20000513:  00           DC.B       0x00                     ; '\0'
+  0x20000514:  04           DC.B       0x04                     ; '\x04'
+  0x20000515:  00           DC.B       0x00                     ; '\0'
+  0x20000516:  00           DC.B       0x00                     ; '\0'
+  0x20000517:  00           DC.B       0x00                     ; '\0'
+  0x20000518:  00           DC.B       0x00                     ; '\0'
+  0x20000519:  00           DC.B       0x00                     ; '\0'
+  0x2000051A:  00           DC.B       0x00                     ; '\0'
+  0x2000051B:  00           DC.B       0x00                     ; '\0'
+  0x2000051C:  00           DC.B       0x00                     ; '\0'
+  0x2000051D:  00           DC.B       0x00                     ; '\0'
+  0x2000051E:  00           DC.B       0x00                     ; '\0'
+  0x2000051F:  00           DC.B       0x00                     ; '\0'
+  0x20000520:  00           DC.B       0x00                     ; '\0'
+  0x20000521:  00           DC.B       0x00                     ; '\0'
+  0x20000522:  00           DC.B       0x00                     ; '\0'
+  0x20000523:  00           DC.B       0x00                     ; '\0'
+  0x20000524:  00           DC.B       0x00                     ; '\0'
+  0x20000525:  00           DC.B       0x00                     ; '\0'
+  0x20000526:  00           DC.B       0x00                     ; '\0'
+  0x20000527:  00           DC.B       0x00                     ; '\0'
+  0x20000528:  00           DC.B       0x00                     ; '\0'
+  0x20000529:  00           DC.B       0x00                     ; '\0'
+  0x2000052A:  00           DC.B       0x00                     ; '\0'
+  0x2000052B:  00           DC.B       0x00                     ; '\0'
+  0x2000052C:  00           DC.B       0x00                     ; '\0'
+  0x2000052D:  00           DC.B       0x00                     ; '\0'
+  0x2000052E:  00           DC.B       0x00                     ; '\0'
+  0x2000052F:  00           DC.B       0x00                     ; '\0'
+  0x20000530:  00           DC.B       0x00                     ; '\0'
+  0x20000531:  00           DC.B       0x00                     ; '\0'
+  0x20000532:  00           DC.B       0x00                     ; '\0'
+  0x20000533:  00           DC.B       0x00                     ; '\0'
+  0x20000534:  00           DC.B       0x00                     ; '\0'
+  0x20000535:  00           DC.B       0x00                     ; '\0'
+  0x20000536:  00           DC.B       0x00                     ; '\0'
+  0x20000537:  00           DC.B       0x00                     ; '\0'
+  0x20000538:  01           DC.B       0x01                     ; '\x01'
+  0x20000539:  00           DC.B       0x00                     ; '\0'
+  0x2000053A:  00           DC.B       0x00                     ; '\0'
+  0x2000053B:  00           DC.B       0x00                     ; '\0'
+  0x2000053C:  02           DC.B       0x02                     ; '\x02'
+  0x2000053D:  00           DC.B       0x00                     ; '\0'
+  0x2000053E:  00           DC.B       0x00                     ; '\0'
+  0x2000053F:  00           DC.B       0x00                     ; '\0'
+  0x20000540:  03           DC.B       0x03                     ; '\x03'
+  0x20000541:  00           DC.B       0x00                     ; '\0'
+  0x20000542:  00           DC.B       0x00                     ; '\0'
+  0x20000543:  00           DC.B       0x00                     ; '\0'
+  0x20000544:  04           DC.B       0x04                     ; '\x04'
+  0x20000545:  00           DC.B       0x00                     ; '\0'
+  0x20000546:  00           DC.B       0x00                     ; '\0'
+  0x20000547:  00           DC.B       0x00                     ; '\0'
+  0x20000548:  06           DC.B       0x06                     ; '\x06'
+  0x20000549:  00           DC.B       0x00                     ; '\0'
+  0x2000054A:  00           DC.B       0x00                     ; '\0'
+  0x2000054B:  00           DC.B       0x00                     ; '\0'
+  0x2000054C:  07           DC.B       0x07                     ; '\x07'
+  0x2000054D:  00           DC.B       0x00                     ; '\0'
+  0x2000054E:  00           DC.B       0x00                     ; '\0'
+  0x2000054F:  00           DC.B       0x00                     ; '\0'
+  0x20000550:  08           DC.B       0x08                     ; '\b'
+  0x20000551:  00           DC.B       0x00                     ; '\0'
+  0x20000552:  00           DC.B       0x00                     ; '\0'
+  0x20000553:  00           DC.B       0x00                     ; '\0'
+  0x20000554:  09           DC.B       0x09                     ; '\t'
+  0x20000555:  00           DC.B       0x00                     ; '\0'
+  0x20000556:  00           DC.B       0x00                     ; '\0'
+  0x20000557:  00           DC.B       0x00                     ; '\0'
+  0x20000558:  00           DC.B       0x00                     ; '\0'
+  0x20000559:  00           DC.B       0x00                     ; '\0'
+  0x2000055A:  00           DC.B       0x00                     ; '\0'
+  0x2000055B:  00           DC.B       0x00                     ; '\0'
+  0x2000055C:  00           DC.B       0x00                     ; '\0'
+  0x2000055D:  00           DC.B       0x00                     ; '\0'
+  0x2000055E:  00           DC.B       0x00                     ; '\0'
+  0x2000055F:  00           DC.B       0x00                     ; '\0'
+  0x20000560:  00           DC.B       0x00                     ; '\0'
+  0x20000561:  00           DC.B       0x00                     ; '\0'
+  0x20000562:  00           DC.B       0x00                     ; '\0'
+  0x20000563:  00           DC.B       0x00                     ; '\0'
+  0x20000564:  00           DC.B       0x00                     ; '\0'
+  0x20000565:  00           DC.B       0x00                     ; '\0'
+  0x20000566:  00           DC.B       0x00                     ; '\0'
+  0x20000567:  00           DC.B       0x00                     ; '\0'
+  0x20000568:  01           DC.B       0x01                     ; '\x01'
+  0x20000569:  00           DC.B       0x00                     ; '\0'
+  0x2000056A:  00           DC.B       0x00                     ; '\0'
+  0x2000056B:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.hdma_adc1 from PowerPro_lto.o, size=92, align=4

+
+
hdma_adc1:
+  0x2000056C:  00           DC.B       0x00                     ; '\0'
+  0x2000056D:  1B           DC.B       0x1B                     ; '\x1B'
+  0x2000056E:  B7           DC.B       0xB7                     ; '\xB7'
+  0x2000056F:  00           DC.B       0x00                     ; '\0'
+  0x20000570:  04           DC.B       0x04                     ; '\x04'
+  0x20000571:  00           DC.B       0x00                     ; '\0'
+  0x20000572:  00           DC.B       0x00                     ; '\0'
+  0x20000573:  00           DC.B       0x00                     ; '\0'
+  0x20000574:  00           DC.B       0x00                     ; '\0'
+  0x20000575:  00           DC.B       0x00                     ; '\0'
+  0x20000576:  00           DC.B       0x00                     ; '\0'
+  0x20000577:  00           DC.B       0x00                     ; '\0'
+  0x20000578:  00           DC.B       0x00                     ; '\0'
+  0x20000579:  00           DC.B       0x00                     ; '\0'
+  0x2000057A:  00           DC.B       0x00                     ; '\0'
+  0x2000057B:  00           DC.B       0x00                     ; '\0'
+  0x2000057C:  00           DC.B       0x00                     ; '\0'
+  0x2000057D:  00           DC.B       0x00                     ; '\0'
+  0x2000057E:  00           DC.B       0x00                     ; '\0'
+  0x2000057F:  00           DC.B       0x00                     ; '\0'
+  0x20000580:  00           DC.B       0x00                     ; '\0'
+  0x20000581:  00           DC.B       0x00                     ; '\0'
+  0x20000582:  00           DC.B       0x00                     ; '\0'
+  0x20000583:  00           DC.B       0x00                     ; '\0'
+  0x20000584:  00           DC.B       0x00                     ; '\0'
+  0x20000585:  00           DC.B       0x00                     ; '\0'
+  0x20000586:  00           DC.B       0x00                     ; '\0'
+  0x20000587:  00           DC.B       0x00                     ; '\0'
+  0x20000588:  00           DC.B       0x00                     ; '\0'
+  0x20000589:  00           DC.B       0x00                     ; '\0'
+  0x2000058A:  00           DC.B       0x00                     ; '\0'
+  0x2000058B:  00           DC.B       0x00                     ; '\0'
+  0x2000058C:  00           DC.B       0x00                     ; '\0'
+  0x2000058D:  00           DC.B       0x00                     ; '\0'
+  0x2000058E:  00           DC.B       0x00                     ; '\0'
+  0x2000058F:  00           DC.B       0x00                     ; '\0'
+  0x20000590:  00           DC.B       0x00                     ; '\0'
+  0x20000591:  00           DC.B       0x00                     ; '\0'
+  0x20000592:  00           DC.B       0x00                     ; '\0'
+  0x20000593:  00           DC.B       0x00                     ; '\0'
+  0x20000594:  01           DC.B       0x01                     ; '\x01'
+  0x20000595:  00           DC.B       0x00                     ; '\0'
+  0x20000596:  00           DC.B       0x00                     ; '\0'
+  0x20000597:  00           DC.B       0x00                     ; '\0'
+  0x20000598:  02           DC.B       0x02                     ; '\x02'
+  0x20000599:  00           DC.B       0x00                     ; '\0'
+  0x2000059A:  00           DC.B       0x00                     ; '\0'
+  0x2000059B:  00           DC.B       0x00                     ; '\0'
+  0x2000059C:  03           DC.B       0x03                     ; '\x03'
+  0x2000059D:  00           DC.B       0x00                     ; '\0'
+  0x2000059E:  00           DC.B       0x00                     ; '\0'
+  0x2000059F:  00           DC.B       0x00                     ; '\0'
+  0x200005A0:  04           DC.B       0x04                     ; '\x04'
+  0x200005A1:  00           DC.B       0x00                     ; '\0'
+  0x200005A2:  00           DC.B       0x00                     ; '\0'
+  0x200005A3:  00           DC.B       0x00                     ; '\0'
+  0x200005A4:  06           DC.B       0x06                     ; '\x06'
+  0x200005A5:  00           DC.B       0x00                     ; '\0'
+  0x200005A6:  00           DC.B       0x00                     ; '\0'
+  0x200005A7:  00           DC.B       0x00                     ; '\0'
+  0x200005A8:  07           DC.B       0x07                     ; '\x07'
+  0x200005A9:  00           DC.B       0x00                     ; '\0'
+  0x200005AA:  00           DC.B       0x00                     ; '\0'
+  0x200005AB:  00           DC.B       0x00                     ; '\0'
+  0x200005AC:  08           DC.B       0x08                     ; '\b'
+  0x200005AD:  00           DC.B       0x00                     ; '\0'
+  0x200005AE:  00           DC.B       0x00                     ; '\0'
+  0x200005AF:  00           DC.B       0x00                     ; '\0'
+  0x200005B0:  09           DC.B       0x09                     ; '\t'
+  0x200005B1:  00           DC.B       0x00                     ; '\0'
+  0x200005B2:  00           DC.B       0x00                     ; '\0'
+  0x200005B3:  00           DC.B       0x00                     ; '\0'
+  0x200005B4:  00           DC.B       0x00                     ; '\0'
+  0x200005B5:  00           DC.B       0x00                     ; '\0'
+  0x200005B6:  00           DC.B       0x00                     ; '\0'
+  0x200005B7:  00           DC.B       0x00                     ; '\0'
+  0x200005B8:  00           DC.B       0x00                     ; '\0'
+  0x200005B9:  00           DC.B       0x00                     ; '\0'
+  0x200005BA:  00           DC.B       0x00                     ; '\0'
+  0x200005BB:  00           DC.B       0x00                     ; '\0'
+  0x200005BC:  00           DC.B       0x00                     ; '\0'
+  0x200005BD:  00           DC.B       0x00                     ; '\0'
+  0x200005BE:  00           DC.B       0x00                     ; '\0'
+  0x200005BF:  00           DC.B       0x00                     ; '\0'
+  0x200005C0:  00           DC.B       0x00                     ; '\0'
+  0x200005C1:  00           DC.B       0x00                     ; '\0'
+  0x200005C2:  00           DC.B       0x00                     ; '\0'
+  0x200005C3:  00           DC.B       0x00                     ; '\0'
+  0x200005C4:  01           DC.B       0x01                     ; '\x01'
+  0x200005C5:  00           DC.B       0x00                     ; '\0'
+  0x200005C6:  00           DC.B       0x00                     ; '\0'
+  0x200005C7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.htim17 from PowerPro_lto.o, size=76, align=4

+
+
htim17:
+  0x200005C8:  00           DC.B       0x00                     ; '\0'
+  0x200005C9:  00           DC.B       0x00                     ; '\0'
+  0x200005CA:  00           DC.B       0x00                     ; '\0'
+  0x200005CB:  00           DC.B       0x00                     ; '\0'
+  0x200005CC:  73           DC.B       0x73                     ; 's'
+  0x200005CD:  65           DC.B       0x65                     ; 'e'
+  0x200005CE:  74           DC.B       0x74                     ; 't'
+  0x200005CF:  7A           DC.B       0x7A                     ; 'z'
+  0x200005D0:  65           DC.B       0x65                     ; 'e'
+  0x200005D1:  20           DC.B       0x20                     ; ' '
+  0x200005D2:  6F           DC.B       0x6F                     ; 'o'
+  0x200005D3:  70           DC.B       0x70                     ; 'p'
+  0x200005D4:  74           DC.B       0x74                     ; 't'
+  0x200005D5:  69           DC.B       0x69                     ; 'i'
+  0x200005D6:  6F           DC.B       0x6F                     ; 'o'
+  0x200005D7:  6E           DC.B       0x6E                     ; 'n'
+  0x200005D8:  20           DC.B       0x20                     ; ' '
+  0x200005D9:  62           DC.B       0x62                     ; 'b'
+  0x200005DA:  79           DC.B       0x79                     ; 'y'
+  0x200005DB:  74           DC.B       0x74                     ; 't'
+  0x200005DC:  65           DC.B       0x65                     ; 'e'
+  0x200005DD:  0D           DC.B       0x0D                     ; '\r'
+  0x200005DE:  00           DC.B       0x00                     ; '\0'
+  0x200005DF:  4B           DC.B       0x4B                     ; 'K'
+  0x200005E0:  6F           DC.B       0x6F                     ; 'o'
+  0x200005E1:  6E           DC.B       0x6E                     ; 'n'
+  0x200005E2:  66           DC.B       0x66                     ; 'f'
+  0x200005E3:  69           DC.B       0x69                     ; 'i'
+  0x200005E4:  67           DC.B       0x67                     ; 'g'
+  0x200005E5:  20           DC.B       0x20                     ; ' '
+  0x200005E6:  76           DC.B       0x76                     ; 'v'
+  0x200005E7:  6F           DC.B       0x6F                     ; 'o'
+  0x200005E8:  72           DC.B       0x72                     ; 'r'
+  0x200005E9:  68           DC.B       0x68                     ; 'h'
+  0x200005EA:  61           DC.B       0x61                     ; 'a'
+  0x200005EB:  6E           DC.B       0x6E                     ; 'n'
+  0x200005EC:  64           DC.B       0x64                     ; 'd'
+  0x200005ED:  65           DC.B       0x65                     ; 'e'
+  0x200005EE:  6E           DC.B       0x6E                     ; 'n'
+  0x200005EF:  0D           DC.B       0x0D                     ; '\r'
+  0x200005F0:  00           DC.B       0x00                     ; '\0'
+  0x200005F1:  4E           DC.B       0x4E                     ; 'N'
+  0x200005F2:  65           DC.B       0x65                     ; 'e'
+  0x200005F3:  75           DC.B       0x75                     ; 'u'
+  0x200005F4:  65           DC.B       0x65                     ; 'e'
+  0x200005F5:  20           DC.B       0x20                     ; ' '
+  0x200005F6:  56           DC.B       0x56                     ; 'V'
+  0x200005F7:  65           DC.B       0x65                     ; 'e'
+  0x200005F8:  72           DC.B       0x72                     ; 'r'
+  0x200005F9:  73           DC.B       0x73                     ; 's'
+  0x200005FA:  69           DC.B       0x69                     ; 'i'
+  0x200005FB:  6F           DC.B       0x6F                     ; 'o'
+  0x200005FC:  6E           DC.B       0x6E                     ; 'n'
+  0x200005FD:  20           DC.B       0x20                     ; ' '
+  0x200005FE:  50           DC.B       0x50                     ; 'P'
+  0x200005FF:  61           DC.B       0x61                     ; 'a'
+  0x20000600:  72           DC.B       0x72                     ; 'r'
+  0x20000601:  61           DC.B       0x61                     ; 'a'
+  0x20000602:  6D           DC.B       0x6D                     ; 'm'
+  0x20000603:  65           DC.B       0x65                     ; 'e'
+  0x20000604:  74           DC.B       0x74                     ; 't'
+  0x20000605:  65           DC.B       0x65                     ; 'e'
+  0x20000606:  72           DC.B       0x72                     ; 'r'
+  0x20000607:  20           DC.B       0x20                     ; ' '
+  0x20000608:  65           DC.B       0x65                     ; 'e'
+  0x20000609:  72           DC.B       0x72                     ; 'r'
+  0x2000060A:  6B           DC.B       0x6B                     ; 'k'
+  0x2000060B:  61           DC.B       0x61                     ; 'a'
+  0x2000060C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000060D:  6E           DC.B       0x6E                     ; 'n'
+  0x2000060E:  74           DC.B       0x74                     ; 't'
+  0x2000060F:  2C           DC.B       0x2C                     ; ','
+  0x20000610:  20           DC.B       0x20                     ; ' '
+  0x20000611:  73           DC.B       0x73                     ; 's'
+  0x20000612:  63           DC.B       0x63                     ; 'c'
+  0x20000613:  68           DC.B       0x68                     ; 'h'
+
+

Section .bss.htim16 from PowerPro_lto.o, size=76, align=4

+
+
htim16:
+  0x20000614:  73           DC.B       0x73                     ; 's'
+  0x20000615:  65           DC.B       0x65                     ; 'e'
+  0x20000616:  74           DC.B       0x74                     ; 't'
+  0x20000617:  7A           DC.B       0x7A                     ; 'z'
+  0x20000618:  65           DC.B       0x65                     ; 'e'
+  0x20000619:  20           DC.B       0x20                     ; ' '
+  0x2000061A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000061B:  70           DC.B       0x70                     ; 'p'
+  0x2000061C:  74           DC.B       0x74                     ; 't'
+  0x2000061D:  69           DC.B       0x69                     ; 'i'
+  0x2000061E:  6F           DC.B       0x6F                     ; 'o'
+  0x2000061F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000620:  20           DC.B       0x20                     ; ' '
+  0x20000621:  62           DC.B       0x62                     ; 'b'
+  0x20000622:  79           DC.B       0x79                     ; 'y'
+  0x20000623:  74           DC.B       0x74                     ; 't'
+  0x20000624:  65           DC.B       0x65                     ; 'e'
+  0x20000625:  0D           DC.B       0x0D                     ; '\r'
+  0x20000626:  00           DC.B       0x00                     ; '\0'
+  0x20000627:  4B           DC.B       0x4B                     ; 'K'
+  0x20000628:  6F           DC.B       0x6F                     ; 'o'
+  0x20000629:  6E           DC.B       0x6E                     ; 'n'
+  0x2000062A:  66           DC.B       0x66                     ; 'f'
+  0x2000062B:  69           DC.B       0x69                     ; 'i'
+  0x2000062C:  67           DC.B       0x67                     ; 'g'
+  0x2000062D:  20           DC.B       0x20                     ; ' '
+  0x2000062E:  76           DC.B       0x76                     ; 'v'
+  0x2000062F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000630:  72           DC.B       0x72                     ; 'r'
+  0x20000631:  68           DC.B       0x68                     ; 'h'
+  0x20000632:  61           DC.B       0x61                     ; 'a'
+  0x20000633:  6E           DC.B       0x6E                     ; 'n'
+  0x20000634:  64           DC.B       0x64                     ; 'd'
+  0x20000635:  65           DC.B       0x65                     ; 'e'
+  0x20000636:  6E           DC.B       0x6E                     ; 'n'
+  0x20000637:  0D           DC.B       0x0D                     ; '\r'
+  0x20000638:  00           DC.B       0x00                     ; '\0'
+  0x20000639:  4E           DC.B       0x4E                     ; 'N'
+  0x2000063A:  65           DC.B       0x65                     ; 'e'
+  0x2000063B:  75           DC.B       0x75                     ; 'u'
+  0x2000063C:  65           DC.B       0x65                     ; 'e'
+  0x2000063D:  20           DC.B       0x20                     ; ' '
+  0x2000063E:  56           DC.B       0x56                     ; 'V'
+  0x2000063F:  65           DC.B       0x65                     ; 'e'
+  0x20000640:  72           DC.B       0x72                     ; 'r'
+  0x20000641:  73           DC.B       0x73                     ; 's'
+  0x20000642:  69           DC.B       0x69                     ; 'i'
+  0x20000643:  6F           DC.B       0x6F                     ; 'o'
+  0x20000644:  6E           DC.B       0x6E                     ; 'n'
+  0x20000645:  20           DC.B       0x20                     ; ' '
+  0x20000646:  50           DC.B       0x50                     ; 'P'
+  0x20000647:  61           DC.B       0x61                     ; 'a'
+  0x20000648:  72           DC.B       0x72                     ; 'r'
+  0x20000649:  61           DC.B       0x61                     ; 'a'
+  0x2000064A:  6D           DC.B       0x6D                     ; 'm'
+  0x2000064B:  65           DC.B       0x65                     ; 'e'
+  0x2000064C:  74           DC.B       0x74                     ; 't'
+  0x2000064D:  65           DC.B       0x65                     ; 'e'
+  0x2000064E:  72           DC.B       0x72                     ; 'r'
+  0x2000064F:  20           DC.B       0x20                     ; ' '
+  0x20000650:  65           DC.B       0x65                     ; 'e'
+  0x20000651:  72           DC.B       0x72                     ; 'r'
+  0x20000652:  6B           DC.B       0x6B                     ; 'k'
+  0x20000653:  61           DC.B       0x61                     ; 'a'
+  0x20000654:  6E           DC.B       0x6E                     ; 'n'
+  0x20000655:  6E           DC.B       0x6E                     ; 'n'
+  0x20000656:  74           DC.B       0x74                     ; 't'
+  0x20000657:  2C           DC.B       0x2C                     ; ','
+  0x20000658:  20           DC.B       0x20                     ; ' '
+  0x20000659:  73           DC.B       0x73                     ; 's'
+  0x2000065A:  63           DC.B       0x63                     ; 'c'
+  0x2000065B:  68           DC.B       0x68                     ; 'h'
+  0x2000065C:  72           DC.B       0x72                     ; 'r'
+  0x2000065D:  65           DC.B       0x65                     ; 'e'
+  0x2000065E:  69           DC.B       0x69                     ; 'i'
+  0x2000065F:  62           DC.B       0x62                     ; 'b'
+
+

Section .bss.adcData from PowerPro_lto.o, size=20, align=4

+
+
adcData:
+  0x20000660:  73           DC.B       0x73                     ; 's'
+  0x20000661:  65           DC.B       0x65                     ; 'e'
+  0x20000662:  74           DC.B       0x74                     ; 't'
+  0x20000663:  7A           DC.B       0x7A                     ; 'z'
+  0x20000664:  65           DC.B       0x65                     ; 'e'
+  0x20000665:  20           DC.B       0x20                     ; ' '
+  0x20000666:  6F           DC.B       0x6F                     ; 'o'
+  0x20000667:  70           DC.B       0x70                     ; 'p'
+  0x20000668:  74           DC.B       0x74                     ; 't'
+  0x20000669:  69           DC.B       0x69                     ; 'i'
+  0x2000066A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000066B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000066C:  20           DC.B       0x20                     ; ' '
+  0x2000066D:  62           DC.B       0x62                     ; 'b'
+  0x2000066E:  79           DC.B       0x79                     ; 'y'
+  0x2000066F:  74           DC.B       0x74                     ; 't'
+  0x20000670:  65           DC.B       0x65                     ; 'e'
+  0x20000671:  0D           DC.B       0x0D                     ; '\r'
+  0x20000672:  00           DC.B       0x00                     ; '\0'
+  0x20000673:  4B           DC.B       0x4B                     ; 'K'
+
+

Section .bss.flash_device_parameter_default from PowerPro_lto.o, size=16, align=4

+
+
flash_device_parameter_default:
+  0x20000674:  00           DC.B       0x00                     ; '\0'
+  0x20000675:  00           DC.B       0x00                     ; '\0'
+  0x20000676:  00           DC.B       0x00                     ; '\0'
+  0x20000677:  00           DC.B       0x00                     ; '\0'
+  0x20000678:  73           DC.B       0x73                     ; 's'
+  0x20000679:  65           DC.B       0x65                     ; 'e'
+  0x2000067A:  74           DC.B       0x74                     ; 't'
+  0x2000067B:  7A           DC.B       0x7A                     ; 'z'
+  0x2000067C:  65           DC.B       0x65                     ; 'e'
+  0x2000067D:  20           DC.B       0x20                     ; ' '
+  0x2000067E:  6F           DC.B       0x6F                     ; 'o'
+  0x2000067F:  70           DC.B       0x70                     ; 'p'
+  0x20000680:  74           DC.B       0x74                     ; 't'
+  0x20000681:  69           DC.B       0x69                     ; 'i'
+  0x20000682:  6F           DC.B       0x6F                     ; 'o'
+  0x20000683:  6E           DC.B       0x6E                     ; 'n'
+
+

Section .bss.voltageUout from PowerPro_lto.o, size=4, align=4

+
+
voltageUout:
+  0x20000684:  76           DC.B       0x76                     ; 'v'
+  0x20000685:  6F           DC.B       0x6F                     ; 'o'
+  0x20000686:  6C           DC.B       0x6C                     ; 'l'
+  0x20000687:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.voltageUin from PowerPro_lto.o, size=4, align=4

+
+
voltageUin:
+  0x20000688:  76           DC.B       0x76                     ; 'v'
+  0x20000689:  6F           DC.B       0x6F                     ; 'o'
+  0x2000068A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000068B:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.uwTick from PowerPro_lto.o, size=4, align=4

+
+
uwTick:
+  0x2000068C:  00           DC.B       0x00                     ; '\0'
+  0x2000068D:  1B           DC.B       0x1B                     ; '\x1B'
+  0x2000068E:  B7           DC.B       0xB7                     ; '\xB7'
+  0x2000068F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.temp from PowerPro_lto.o, size=4, align=4

+
+
temp:
+  0x20000690:  00           DC.B       0x00                     ; '\0'
+  0x20000691:  00           DC.B       0x00                     ; '\0'
+  0x20000692:  00           DC.B       0x00                     ; '\0'
+  0x20000693:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.relais_temperature from PowerPro_lto.o, size=4, align=4

+
+
relais_temperature:
+  0x20000694:  76           DC.B       0x76                     ; 'v'
+  0x20000695:  6F           DC.B       0x6F                     ; 'o'
+  0x20000696:  6C           DC.B       0x6C                     ; 'l'
+  0x20000697:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterSET from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterSET:
+  0x20000698:  76           DC.B       0x76                     ; 'v'
+  0x20000699:  6F           DC.B       0x6F                     ; 'o'
+  0x2000069A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000069B:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterRT from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterRT:
+  0x2000069C:  00           DC.B       0x00                     ; '\0'
+  0x2000069D:  00           DC.B       0x00                     ; '\0'
+  0x2000069E:  00           DC.B       0x00                     ; '\0'
+  0x2000069F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeCounterRESET from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterRESET:
+  0x200006A0:  76           DC.B       0x76                     ; 'v'
+  0x200006A1:  6F           DC.B       0x6F                     ; 'o'
+  0x200006A2:  6C           DC.B       0x6C                     ; 'l'
+  0x200006A3:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterGN from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterGN:
+  0x200006A4:  00           DC.B       0x00                     ; '\0'
+  0x200006A5:  00           DC.B       0x00                     ; '\0'
+  0x200006A6:  00           DC.B       0x00                     ; '\0'
+  0x200006A7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounter:
+  0x200006A8:  00           DC.B       0x00                     ; '\0'
+  0x200006A9:  00           DC.B       0x00                     ; '\0'
+  0x200006AA:  00           DC.B       0x00                     ; '\0'
+  0x200006AB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.oldTimeMSTick from PowerPro_lto.o, size=4, align=4

+
+
oldTimeMSTick:
+  0x200006AC:  73           DC.B       0x73                     ; 's'
+  0x200006AD:  65           DC.B       0x65                     ; 'e'
+  0x200006AE:  74           DC.B       0x74                     ; 't'
+  0x200006AF:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.offTimeCounterRT from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounterRT:
+  0x200006B0:  00           DC.B       0x00                     ; '\0'
+  0x200006B1:  00           DC.B       0x00                     ; '\0'
+  0x200006B2:  00           DC.B       0x00                     ; '\0'
+  0x200006B3:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeCounterGN from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounterGN:
+  0x200006B4:  00           DC.B       0x00                     ; '\0'
+  0x200006B5:  00           DC.B       0x00                     ; '\0'
+  0x200006B6:  00           DC.B       0x00                     ; '\0'
+  0x200006B7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounter:
+  0x200006B8:  00           DC.B       0x00                     ; '\0'
+  0x200006B9:  00           DC.B       0x00                     ; '\0'
+  0x200006BA:  00           DC.B       0x00                     ; '\0'
+  0x200006BB:  00           DC.B       0x00                     ; '\0'
+
+ +
+
numberOfBlinks:
+  0x200006BC:  00           DC.B       0x00                     ; '\0'
+  0x200006BD:  00           DC.B       0x00                     ; '\0'
+  0x200006BE:  00           DC.B       0x00                     ; '\0'
+  0x200006BF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.msCounter from PowerPro_lto.o, size=4, align=4

+
+
msCounter:
+  0x200006C0:  73           DC.B       0x73                     ; 's'
+  0x200006C1:  65           DC.B       0x65                     ; 'e'
+  0x200006C2:  74           DC.B       0x74                     ; 't'
+  0x200006C3:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.longPressCounterButtonOn from PowerPro_lto.o, size=4, align=4

+
+
longPressCounterButtonOn:
+  0x200006C4:  42           DC.B       0x42                     ; 'B'
+  0x200006C5:  55           DC.B       0x55                     ; 'U'
+  0x200006C6:  54           DC.B       0x54                     ; 'T'
+  0x200006C7:  54           DC.B       0x54                     ; 'T'
+
+

Section .bss.longPressCounterButtonOff from PowerPro_lto.o, size=4, align=4

+
+
longPressCounterButtonOff:
+  0x200006C8:  42           DC.B       0x42                     ; 'B'
+  0x200006C9:  55           DC.B       0x55                     ; 'U'
+  0x200006CA:  54           DC.B       0x54                     ; 'T'
+  0x200006CB:  54           DC.B       0x54                     ; 'T'
+
+

Section .bss.libc.__SEGGER_RTL_stdout_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stdout_file:
+  0x200006CC:  00           DC.B       0x00                     ; '\0'
+  0x200006CD:  00           DC.B       0x00                     ; '\0'
+  0x200006CE:  00           DC.B       0x00                     ; '\0'
+  0x200006CF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_stdin_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stdin_file:
+  0x200006D0:  00           DC.B       0x00                     ; '\0'
+  0x200006D1:  00           DC.B       0x00                     ; '\0'
+  0x200006D2:  00           DC.B       0x00                     ; '\0'
+  0x200006D3:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_stderr_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stderr_file:
+  0x200006D4:  00           DC.B       0x00                     ; '\0'
+  0x200006D5:  00           DC.B       0x00                     ; '\0'
+  0x200006D6:  00           DC.B       0x00                     ; '\0'
+  0x200006D7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_locale_ptr from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_locale_ptr:
+  0x200006D8:  43           DC.B       0x43                     ; 'C'
+  0x200006D9:  00           DC.B       0x00                     ; '\0'
+  0x200006DA:  50           DC.B       0x50                     ; 'P'
+  0x200006DB:  4F           DC.B       0x4F                     ; 'O'
+
+

Section .bss.ic_overflows from PowerPro_lto.o, size=4, align=4

+
+
ic_overflows:
+  0x200006DC:  73           DC.B       0x73                     ; 's'
+  0x200006DD:  65           DC.B       0x65                     ; 'e'
+  0x200006DE:  74           DC.B       0x74                     ; 't'
+  0x200006DF:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.frequency from PowerPro_lto.o, size=4, align=4

+
+
frequency:
+  0x200006E0:  73           DC.B       0x73                     ; 's'
+  0x200006E1:  65           DC.B       0x65                     ; 'e'
+  0x200006E2:  74           DC.B       0x74                     ; 't'
+  0x200006E3:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.dropLimitCounter from PowerPro_lto.o, size=4, align=4

+
+
dropLimitCounter:
+  0x200006E4:  76           DC.B       0x76                     ; 'v'
+  0x200006E5:  6F           DC.B       0x6F                     ; 'o'
+  0x200006E6:  6C           DC.B       0x6C                     ; 'l'
+  0x200006E7:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.calTemperatureSensor30Value from PowerPro_lto.o, size=4, align=4

+
+
calTemperatureSensor30Value:
+  0x200006E8:  00           DC.B       0x00                     ; '\0'
+  0x200006E9:  00           DC.B       0x00                     ; '\0'
+  0x200006EA:  00           DC.B       0x00                     ; '\0'
+  0x200006EB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkCounter from PowerPro_lto.o, size=4, align=4

+
+
blinkCounter:
+  0x200006EC:  00           DC.B       0x00                     ; '\0'
+  0x200006ED:  00           DC.B       0x00                     ; '\0'
+  0x200006EE:  00           DC.B       0x00                     ; '\0'
+  0x200006EF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.autoRetryMode.170 from PowerPro_lto.o, size=4, align=4

+
+
autoRetryMode.170:
+  0x200006F0:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F1:  45           DC.B       0x45                     ; 'E'
+  0x200006F2:  57           DC.B       0x57                     ; 'W'
+  0x200006F3:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.autoRetryMode from PowerPro_lto.o, size=4, align=4

+
+
autoRetryMode:
+  0x200006F4:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F5:  45           DC.B       0x45                     ; 'E'
+  0x200006F6:  57           DC.B       0x57                     ; 'W'
+  0x200006F7:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.oldtime.175 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.oldtime.175:
+  0x200006F8:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F9:  45           DC.B       0x45                     ; 'E'
+  0x200006FA:  57           DC.B       0x57                     ; 'W'
+  0x200006FB:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.oldtime:
+  0x200006FC:  4E           DC.B       0x4E                     ; 'N'
+  0x200006FD:  45           DC.B       0x45                     ; 'E'
+  0x200006FE:  57           DC.B       0x57                     ; 'W'
+  0x200006FF:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176:
+  0x20000700:  4E           DC.B       0x4E                     ; 'N'
+  0x20000701:  45           DC.B       0x45                     ; 'E'
+  0x20000702:  57           DC.B       0x57                     ; 'W'
+  0x20000703:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter:
+  0x20000704:  4E           DC.B       0x4E                     ; 'N'
+  0x20000705:  45           DC.B       0x45                     ; 'E'
+  0x20000706:  57           DC.B       0x57                     ; 'W'
+  0x20000707:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.retry_counter.181 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.retry_counter.181:
+  0x20000708:  4E           DC.B       0x4E                     ; 'N'
+  0x20000709:  45           DC.B       0x45                     ; 'E'
+  0x2000070A:  57           DC.B       0x57                     ; 'W'
+  0x2000070B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.retry_counter from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.retry_counter:
+  0x2000070C:  4E           DC.B       0x4E                     ; 'N'
+  0x2000070D:  45           DC.B       0x45                     ; 'E'
+  0x2000070E:  57           DC.B       0x57                     ; 'W'
+  0x2000070F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182:
+  0x20000710:  4E           DC.B       0x4E                     ; 'N'
+  0x20000711:  45           DC.B       0x45                     ; 'E'
+  0x20000712:  57           DC.B       0x57                     ; 'W'
+  0x20000713:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.oldTimeMSTick from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.oldTimeMSTick:
+  0x20000714:  4E           DC.B       0x4E                     ; 'N'
+  0x20000715:  45           DC.B       0x45                     ; 'E'
+  0x20000716:  57           DC.B       0x57                     ; 'W'
+  0x20000717:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.OVP_SM_On.ovpTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
OVP_SM_On.ovpTimeCounter:
+  0x20000718:  4F           DC.B       0x4F                     ; 'O'
+  0x20000719:  56           DC.B       0x56                     ; 'V'
+  0x2000071A:  50           DC.B       0x50                     ; 'P'
+  0x2000071B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.OVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
OVP_SM_On.oldtime:
+  0x2000071C:  4F           DC.B       0x4F                     ; 'O'
+  0x2000071D:  56           DC.B       0x56                     ; 'V'
+  0x2000071E:  50           DC.B       0x50                     ; 'P'
+  0x2000071F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
LVP_SM_On.oldtime:
+  0x20000720:  4C           DC.B       0x4C                     ; 'L'
+  0x20000721:  56           DC.B       0x56                     ; 'V'
+  0x20000722:  50           DC.B       0x50                     ; 'P'
+  0x20000723:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_SM_On.lvpTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
LVP_SM_On.lvpTimeCounter:
+  0x20000724:  4C           DC.B       0x4C                     ; 'L'
+  0x20000725:  56           DC.B       0x56                     ; 'V'
+  0x20000726:  50           DC.B       0x50                     ; 'P'
+  0x20000727:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_OVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
LVP_OVP_SM_On.oldtime:
+  0x20000728:  4C           DC.B       0x4C                     ; 'L'
+  0x20000729:  56           DC.B       0x56                     ; 'V'
+  0x2000072A:  50           DC.B       0x50                     ; 'P'
+  0x2000072B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_OVP_SM_On.lvpAndOvpInputTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter:
+  0x2000072C:  4C           DC.B       0x4C                     ; 'L'
+  0x2000072D:  56           DC.B       0x56                     ; 'V'
+  0x2000072E:  50           DC.B       0x50                     ; 'P'
+  0x2000072F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.relaisState from PowerPro_lto.o, size=1, align=4

+
+
relaisState:
+  0x20000730:  76           DC.B       0x76                     ; 'v'
+
+

Section .bss.smState.171 from PowerPro_lto.o, size=1, align=1

+
+
smState.171:
+  0x20000731:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.160 from PowerPro_lto.o, size=1, align=1

+
+
smState.160:
+  0x20000732:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.145 from PowerPro_lto.o, size=1, align=1

+
+
smState.145:
+  0x20000733:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.pauseTime from PowerPro_lto.o, size=1, align=4

+
+
pauseTime:
+  0x20000734:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.smState.137 from PowerPro_lto.o, size=1, align=1

+
+
smState.137:
+  0x20000735:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.122 from PowerPro_lto.o, size=1, align=1

+
+
smState.122:
+  0x20000736:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.smState from PowerPro_lto.o, size=1, align=1

+
+
smState:
+  0x20000737:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.pFlash.0 from PowerPro_lto.o, size=1, align=4

+
+
pFlash.0:
+  0x20000738:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.mode from PowerPro_lto.o, size=1, align=1

+
+
mode:
+  0x20000739:  6D           DC.B       0x6D                     ; 'm'
+
+

Section .bss.buttonState from PowerPro_lto.o, size=1, align=1

+
+
buttonState:
+  0x2000073A:  42           DC.B       0x42                     ; 'B'
+
+

Section .bss.onTimeRT from PowerPro_lto.o, size=1, align=4

+
+
onTimeRT:
+  0x2000073C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeGN from PowerPro_lto.o, size=1, align=4

+
+
onTimeGN:
+  0x20000740:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTime from PowerPro_lto.o, size=1, align=4

+
+
onTime:
+  0x20000744:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeRT from PowerPro_lto.o, size=1, align=4

+
+
offTimeRT:
+  0x20000748:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeGN from PowerPro_lto.o, size=1, align=4

+
+
offTimeGN:
+  0x2000074C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTime from PowerPro_lto.o, size=1, align=4

+
+
offTime:
+  0x20000750:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkModeRT from PowerPro_lto.o, size=1, align=4

+
+
blinkModeRT:
+  0x20000754:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkModeGN from PowerPro_lto.o, size=1, align=4

+
+
blinkModeGN:
+  0x20000758:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.alarmMode from PowerPro_lto.o, size=1, align=4

+
+
alarmMode:
+  0x2000075C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.OVP_SM_On.ovpInput from PowerPro_lto.o, size=1, align=4

+
+
OVP_SM_On.ovpInput:
+  0x20000760:  4F           DC.B       0x4F                     ; 'O'
+
+

Section .bss.LVP_SM_On.lvpInput from PowerPro_lto.o, size=1, align=4

+
+
LVP_SM_On.lvpInput:
+  0x20000764:  4C           DC.B       0x4C                     ; 'L'
+
+

Section .bss.LVP_OVP_SM_On.lvpOROvpInput from PowerPro_lto.o, size=1, align=4

+
+
LVP_OVP_SM_On.lvpOROvpInput:
+  0x20000768:  4C           DC.B       0x4C                     ; 'L'
+
+

Section .bss.libc._acUpBuffer from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=1024, align=1

+
+
_acUpBuffer:
+  0x20000769:  00           DC.B       0x00                     ; '\0'
+  0x2000076A:  53           DC.B       0x53                     ; 'S'
+  0x2000076B:  45           DC.B       0x45                     ; 'E'
+  0x2000076C:  47           DC.B       0x47                     ; 'G'
+  0x2000076D:  47           DC.B       0x47                     ; 'G'
+  0x2000076E:  45           DC.B       0x45                     ; 'E'
+  0x2000076F:  52           DC.B       0x52                     ; 'R'
+  0x20000770:  20           DC.B       0x20                     ; ' '
+  0x20000771:  43           DC.B       0x43                     ; 'C'
+  0x20000772:  2F           DC.B       0x2F                     ; '/'
+  0x20000773:  43           DC.B       0x43                     ; 'C'
+  0x20000774:  2B           DC.B       0x2B                     ; '+'
+  0x20000775:  2B           DC.B       0x2B                     ; '+'
+  0x20000776:  20           DC.B       0x20                     ; ' '
+  0x20000777:  63           DC.B       0x63                     ; 'c'
+  0x20000778:  6F           DC.B       0x6F                     ; 'o'
+  0x20000779:  6D           DC.B       0x6D                     ; 'm'
+  0x2000077A:  70           DC.B       0x70                     ; 'p'
+  0x2000077B:  69           DC.B       0x69                     ; 'i'
+  0x2000077C:  6C           DC.B       0x6C                     ; 'l'
+  0x2000077D:  65           DC.B       0x65                     ; 'e'
+  0x2000077E:  72           DC.B       0x72                     ; 'r'
+  0x2000077F:  20           DC.B       0x20                     ; ' '
+  0x20000780:  76           DC.B       0x76                     ; 'v'
+  0x20000781:  65           DC.B       0x65                     ; 'e'
+  0x20000782:  72           DC.B       0x72                     ; 'r'
+  0x20000783:  73           DC.B       0x73                     ; 's'
+  0x20000784:  69           DC.B       0x69                     ; 'i'
+  0x20000785:  6F           DC.B       0x6F                     ; 'o'
+  0x20000786:  6E           DC.B       0x6E                     ; 'n'
+  0x20000787:  20           DC.B       0x20                     ; ' '
+  0x20000788:  32           DC.B       0x32                     ; '2'
+  0x20000789:  30           DC.B       0x30                     ; '0'
+  0x2000078A:  2E           DC.B       0x2E                     ; '.'
+  0x2000078B:  31           DC.B       0x31                     ; '1'
+  0x2000078C:  2E           DC.B       0x2E                     ; '.'
+  0x2000078D:  32           DC.B       0x32                     ; '2'
+  0x2000078E:  20           DC.B       0x20                     ; ' '
+  0x2000078F:  28           DC.B       0x28                     ; '('
+  0x20000790:  62           DC.B       0x62                     ; 'b'
+  0x20000791:  61           DC.B       0x61                     ; 'a'
+  0x20000792:  73           DC.B       0x73                     ; 's'
+  0x20000793:  65           DC.B       0x65                     ; 'e'
+  0x20000794:  64           DC.B       0x64                     ; 'd'
+  0x20000795:  20           DC.B       0x20                     ; ' '
+  0x20000796:  6F           DC.B       0x6F                     ; 'o'
+  0x20000797:  6E           DC.B       0x6E                     ; 'n'
+  0x20000798:  20           DC.B       0x20                     ; ' '
+  0x20000799:  63           DC.B       0x63                     ; 'c'
+  0x2000079A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000079B:  61           DC.B       0x61                     ; 'a'
+  0x2000079C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000079D:  67           DC.B       0x67                     ; 'g'
+  0x2000079E:  20           DC.B       0x20                     ; ' '
+  0x2000079F:  32           DC.B       0x32                     ; '2'
+  0x200007A0:  30           DC.B       0x30                     ; '0'
+  0x200007A1:  2E           DC.B       0x2E                     ; '.'
+  0x200007A2:  31           DC.B       0x31                     ; '1'
+  0x200007A3:  2E           DC.B       0x2E                     ; '.'
+  0x200007A4:  38           DC.B       0x38                     ; '8'
+  0x200007A5:  29           DC.B       0x29                     ; ')'
+  0x200007A6:  00           DC.B       0x00                     ; '\0'
+  0x200007A7:  41           DC.B       0x41                     ; 'A'
+  0x200007A8:  35           DC.B       0x35                     ; '5'
+  0x200007A9:  00           DC.B       0x00                     ; '\0'
+  0x200007AA:  00           DC.B       0x00                     ; '\0'
+  0x200007AB:  00           DC.B       0x00                     ; '\0'
+  0x200007AC:  61           DC.B       0x61                     ; 'a'
+  0x200007AD:  65           DC.B       0x65                     ; 'e'
+  0x200007AE:  61           DC.B       0x61                     ; 'a'
+  0x200007AF:  62           DC.B       0x62                     ; 'b'
+  0x200007B0:  69           DC.B       0x69                     ; 'i'
+  0x200007B1:  00           DC.B       0x00                     ; '\0'
+  0x200007B2:  01           DC.B       0x01                     ; '\x01'
+  0x200007B3:  2B           DC.B       0x2B                     ; '+'
+  0x200007B4:  00           DC.B       0x00                     ; '\0'
+  0x200007B5:  00           DC.B       0x00                     ; '\0'
+  0x200007B6:  00           DC.B       0x00                     ; '\0'
+  0x200007B7:  43           DC.B       0x43                     ; 'C'
+  0x200007B8:  32           DC.B       0x32                     ; '2'
+  0x200007B9:  2E           DC.B       0x2E                     ; '.'
+  0x200007BA:  30           DC.B       0x30                     ; '0'
+  0x200007BB:  39           DC.B       0x39                     ; '9'
+  0x200007BC:  00           DC.B       0x00                     ; '\0'
+  0x200007BD:  06           DC.B       0x06                     ; '\x06'
+  0x200007BE:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200007BF:  07           DC.B       0x07                     ; '\x07'
+  0x200007C0:  4D           DC.B       0x4D                     ; 'M'
+  0x200007C1:  08           DC.B       0x08                     ; '\b'
+  0x200007C2:  00           DC.B       0x00                     ; '\0'
+  0x200007C3:  09           DC.B       0x09                     ; '\t'
+  0x200007C4:  01           DC.B       0x01                     ; '\x01'
+  0x200007C5:  0E           DC.B       0x0E                     ; '\x0E'
+  0x200007C6:  00           DC.B       0x00                     ; '\0'
+  0x200007C7:  11           DC.B       0x11                     ; '\x11'
+  0x200007C8:  01           DC.B       0x01                     ; '\x01'
+  0x200007C9:  12           DC.B       0x12                     ; '\x12'
+  0x200007CA:  04           DC.B       0x04                     ; '\x04'
+  0x200007CB:  14           DC.B       0x14                     ; '\x14'
+  0x200007CC:  01           DC.B       0x01                     ; '\x01'
+  0x200007CD:  15           DC.B       0x15                     ; '\x15'
+  0x200007CE:  00           DC.B       0x00                     ; '\0'
+  0x200007CF:  17           DC.B       0x17                     ; '\x17'
+  0x200007D0:  03           DC.B       0x03                     ; '\x03'
+  0x200007D1:  18           DC.B       0x18                     ; '\x18'
+  0x200007D2:  01           DC.B       0x01                     ; '\x01'
+  0x200007D3:  19           DC.B       0x19                     ; '\x19'
+  0x200007D4:  01           DC.B       0x01                     ; '\x01'
+  0x200007D5:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200007D6:  01           DC.B       0x01                     ; '\x01'
+  0x200007D7:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200007D8:  04           DC.B       0x04                     ; '\x04'
+  0x200007D9:  22           DC.B       0x22                     ; '\"'
+  0x200007DA:  00           DC.B       0x00                     ; '\0'
+  0x200007DB:  26           DC.B       0x26                     ; '&'
+  0x200007DC:  01           DC.B       0x01                     ; '\x01'
+  0x200007DD:  00           DC.B       0x00                     ; '\0'
+  0x200007DE:  00           DC.B       0x00                     ; '\0'
+  0x200007DF:  00           DC.B       0x00                     ; '\0'
+  0x200007E0:  00           DC.B       0x00                     ; '\0'
+  0x200007E1:  00           DC.B       0x00                     ; '\0'
+  0x200007E2:  00           DC.B       0x00                     ; '\0'
+  0x200007E3:  00           DC.B       0x00                     ; '\0'
+  0x200007E4:  00           DC.B       0x00                     ; '\0'
+  0x200007E5:  00           DC.B       0x00                     ; '\0'
+  0x200007E6:  00           DC.B       0x00                     ; '\0'
+  0x200007E7:  00           DC.B       0x00                     ; '\0'
+  0x200007E8:  00           DC.B       0x00                     ; '\0'
+  0x200007E9:  00           DC.B       0x00                     ; '\0'
+  0x200007EA:  00           DC.B       0x00                     ; '\0'
+  0x200007EB:  00           DC.B       0x00                     ; '\0'
+  0x200007EC:  00           DC.B       0x00                     ; '\0'
+  0x200007ED:  00           DC.B       0x00                     ; '\0'
+  0x200007EE:  00           DC.B       0x00                     ; '\0'
+  0x200007EF:  40           DC.B       0x40                     ; '@'
+  0x200007F0:  06           DC.B       0x06                     ; '\x06'
+  0x200007F1:  00           DC.B       0x00                     ; '\0'
+  0x200007F2:  00           DC.B       0x00                     ; '\0'
+  0x200007F3:  00           DC.B       0x00                     ; '\0'
+  0x200007F4:  00           DC.B       0x00                     ; '\0'
+  0x200007F5:  00           DC.B       0x00                     ; '\0'
+  0x200007F6:  00           DC.B       0x00                     ; '\0'
+  0x200007F7:  00           DC.B       0x00                     ; '\0'
+  0x200007F8:  00           DC.B       0x00                     ; '\0'
+  0x200007F9:  00           DC.B       0x00                     ; '\0'
+  0x200007FA:  00           DC.B       0x00                     ; '\0'
+  0x200007FB:  04           DC.B       0x04                     ; '\x04'
+  0x200007FC:  00           DC.B       0x00                     ; '\0'
+  0x200007FD:  F1           DC.B       0xF1                     ; '\xF1'
+  0x200007FE:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200007FF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000800:  00           DC.B       0x00                     ; '\0'
+  0x20000801:  00           DC.B       0x00                     ; '\0'
+  0x20000802:  00           DC.B       0x00                     ; '\0'
+  0x20000803:  00           DC.B       0x00                     ; '\0'
+  0x20000804:  00           DC.B       0x00                     ; '\0'
+  0x20000805:  00           DC.B       0x00                     ; '\0'
+  0x20000806:  00           DC.B       0x00                     ; '\0'
+  0x20000807:  00           DC.B       0x00                     ; '\0'
+  0x20000808:  00           DC.B       0x00                     ; '\0'
+  0x20000809:  00           DC.B       0x00                     ; '\0'
+  0x2000080A:  00           DC.B       0x00                     ; '\0'
+  0x2000080B:  00           DC.B       0x00                     ; '\0'
+  0x2000080C:  00           DC.B       0x00                     ; '\0'
+  0x2000080D:  03           DC.B       0x03                     ; '\x03'
+  0x2000080E:  00           DC.B       0x00                     ; '\0'
+  0x2000080F:  AA           DC.B       0xAA                     ; '\xAA'
+  0x20000810:  00           DC.B       0x00                     ; '\0'
+  0x20000811:  00           DC.B       0x00                     ; '\0'
+  0x20000812:  00           DC.B       0x00                     ; '\0'
+  0x20000813:  01           DC.B       0x01                     ; '\x01'
+  0x20000814:  00           DC.B       0x00                     ; '\0'
+  0x20000815:  00           DC.B       0x00                     ; '\0'
+  0x20000816:  00           DC.B       0x00                     ; '\0'
+  0x20000817:  54           DC.B       0x54                     ; 'T'
+  0x20000818:  00           DC.B       0x00                     ; '\0'
+  0x20000819:  00           DC.B       0x00                     ; '\0'
+  0x2000081A:  00           DC.B       0x00                     ; '\0'
+  0x2000081B:  02           DC.B       0x02                     ; '\x02'
+  0x2000081C:  00           DC.B       0x00                     ; '\0'
+  0x2000081D:  05           DC.B       0x05                     ; '\x05'
+  0x2000081E:  00           DC.B       0x00                     ; '\0'
+  0x2000081F:  32           DC.B       0x32                     ; '2'
+  0x20000820:  06           DC.B       0x06                     ; '\x06'
+  0x20000821:  00           DC.B       0x00                     ; '\0'
+  0x20000822:  00           DC.B       0x00                     ; '\0'
+  0x20000823:  84           DC.B       0x84                     ; '\x84'
+  0x20000824:  00           DC.B       0x00                     ; '\0'
+  0x20000825:  00           DC.B       0x00                     ; '\0'
+  0x20000826:  00           DC.B       0x00                     ; '\0'
+  0x20000827:  00           DC.B       0x00                     ; '\0'
+  0x20000828:  00           DC.B       0x00                     ; '\0'
+  0x20000829:  00           DC.B       0x00                     ; '\0'
+  0x2000082A:  00           DC.B       0x00                     ; '\0'
+  0x2000082B:  00           DC.B       0x00                     ; '\0'
+  0x2000082C:  00           DC.B       0x00                     ; '\0'
+  0x2000082D:  03           DC.B       0x03                     ; '\x03'
+  0x2000082E:  00           DC.B       0x00                     ; '\0'
+  0x2000082F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000830:  00           DC.B       0x00                     ; '\0'
+  0x20000831:  00           DC.B       0x00                     ; '\0'
+  0x20000832:  00           DC.B       0x00                     ; '\0'
+  0x20000833:  00           DC.B       0x00                     ; '\0'
+  0x20000834:  00           DC.B       0x00                     ; '\0'
+  0x20000835:  00           DC.B       0x00                     ; '\0'
+  0x20000836:  00           DC.B       0x00                     ; '\0'
+  0x20000837:  00           DC.B       0x00                     ; '\0'
+  0x20000838:  00           DC.B       0x00                     ; '\0'
+  0x20000839:  00           DC.B       0x00                     ; '\0'
+  0x2000083A:  00           DC.B       0x00                     ; '\0'
+  0x2000083B:  00           DC.B       0x00                     ; '\0'
+  0x2000083C:  00           DC.B       0x00                     ; '\0'
+  0x2000083D:  05           DC.B       0x05                     ; '\x05'
+  0x2000083E:  00           DC.B       0x00                     ; '\0'
+  0x2000083F:  32           DC.B       0x32                     ; '2'
+  0x20000840:  06           DC.B       0x06                     ; '\x06'
+  0x20000841:  00           DC.B       0x00                     ; '\0'
+  0x20000842:  00           DC.B       0x00                     ; '\0'
+  0x20000843:  40           DC.B       0x40                     ; '@'
+  0x20000844:  00           DC.B       0x00                     ; '\0'
+  0x20000845:  00           DC.B       0x00                     ; '\0'
+  0x20000846:  00           DC.B       0x00                     ; '\0'
+  0x20000847:  00           DC.B       0x00                     ; '\0'
+  0x20000848:  00           DC.B       0x00                     ; '\0'
+  0x20000849:  00           DC.B       0x00                     ; '\0'
+  0x2000084A:  00           DC.B       0x00                     ; '\0'
+  0x2000084B:  00           DC.B       0x00                     ; '\0'
+  0x2000084C:  00           DC.B       0x00                     ; '\0'
+  0x2000084D:  05           DC.B       0x05                     ; '\x05'
+  0x2000084E:  00           DC.B       0x00                     ; '\0'
+  0x2000084F:  EE           DC.B       0xEE                     ; '\xEE'
+  0x20000850:  01           DC.B       0x01                     ; '\x01'
+  0x20000851:  00           DC.B       0x00                     ; '\0'
+  0x20000852:  00           DC.B       0x00                     ; '\0'
+  0x20000853:  00           DC.B       0x00                     ; '\0'
+  0x20000854:  00           DC.B       0x00                     ; '\0'
+  0x20000855:  00           DC.B       0x00                     ; '\0'
+  0x20000856:  00           DC.B       0x00                     ; '\0'
+  0x20000857:  00           DC.B       0x00                     ; '\0'
+  0x20000858:  04           DC.B       0x04                     ; '\x04'
+  0x20000859:  00           DC.B       0x00                     ; '\0'
+  0x2000085A:  00           DC.B       0x00                     ; '\0'
+  0x2000085B:  01           DC.B       0x01                     ; '\x01'
+  0x2000085C:  00           DC.B       0x00                     ; '\0'
+  0x2000085D:  51           DC.B       0x51                     ; 'Q'
+  0x2000085E:  00           DC.B       0x00                     ; '\0'
+  0x2000085F:  DC           DC.B       0xDC                     ; '\xDC'
+  0x20000860:  02           DC.B       0x02                     ; '\x02'
+  0x20000861:  00           DC.B       0x00                     ; '\0'
+  0x20000862:  00           DC.B       0x00                     ; '\0'
+  0x20000863:  00           DC.B       0x00                     ; '\0'
+  0x20000864:  00           DC.B       0x00                     ; '\0'
+  0x20000865:  00           DC.B       0x00                     ; '\0'
+  0x20000866:  00           DC.B       0x00                     ; '\0'
+  0x20000867:  10           DC.B       0x10                     ; '\x10'
+  0x20000868:  00           DC.B       0x00                     ; '\0'
+  0x20000869:  00           DC.B       0x00                     ; '\0'
+  0x2000086A:  00           DC.B       0x00                     ; '\0'
+  0x2000086B:  01           DC.B       0x01                     ; '\x01'
+  0x2000086C:  00           DC.B       0x00                     ; '\0'
+  0x2000086D:  52           DC.B       0x52                     ; 'R'
+  0x2000086E:  00           DC.B       0x00                     ; '\0'
+  0x2000086F:  05           DC.B       0x05                     ; '\x05'
+  0x20000870:  01           DC.B       0x01                     ; '\x01'
+  0x20000871:  00           DC.B       0x00                     ; '\0'
+  0x20000872:  00           DC.B       0x00                     ; '\0'
+  0x20000873:  00           DC.B       0x00                     ; '\0'
+  0x20000874:  00           DC.B       0x00                     ; '\0'
+  0x20000875:  00           DC.B       0x00                     ; '\0'
+  0x20000876:  00           DC.B       0x00                     ; '\0'
+  0x20000877:  11           DC.B       0x11                     ; '\x11'
+  0x20000878:  00           DC.B       0x00                     ; '\0'
+  0x20000879:  00           DC.B       0x00                     ; '\0'
+  0x2000087A:  00           DC.B       0x00                     ; '\0'
+  0x2000087B:  01           DC.B       0x01                     ; '\x01'
+  0x2000087C:  00           DC.B       0x00                     ; '\0'
+  0x2000087D:  4F           DC.B       0x4F                     ; 'O'
+  0x2000087E:  00           DC.B       0x00                     ; '\0'
+  0x2000087F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000880:  00           DC.B       0x00                     ; '\0'
+  0x20000881:  00           DC.B       0x00                     ; '\0'
+  0x20000882:  00           DC.B       0x00                     ; '\0'
+  0x20000883:  00           DC.B       0x00                     ; '\0'
+  0x20000884:  00           DC.B       0x00                     ; '\0'
+  0x20000885:  00           DC.B       0x00                     ; '\0'
+  0x20000886:  00           DC.B       0x00                     ; '\0'
+  0x20000887:  00           DC.B       0x00                     ; '\0'
+  0x20000888:  00           DC.B       0x00                     ; '\0'
+  0x20000889:  00           DC.B       0x00                     ; '\0'
+  0x2000088A:  00           DC.B       0x00                     ; '\0'
+  0x2000088B:  00           DC.B       0x00                     ; '\0'
+  0x2000088C:  00           DC.B       0x00                     ; '\0'
+  0x2000088D:  07           DC.B       0x07                     ; '\x07'
+  0x2000088E:  00           DC.B       0x00                     ; '\0'
+  0x2000088F:  32           DC.B       0x32                     ; '2'
+  0x20000890:  06           DC.B       0x06                     ; '\x06'
+  0x20000891:  00           DC.B       0x00                     ; '\0'
+  0x20000892:  00           DC.B       0x00                     ; '\0'
+  0x20000893:  84           DC.B       0x84                     ; '\x84'
+  0x20000894:  00           DC.B       0x00                     ; '\0'
+  0x20000895:  00           DC.B       0x00                     ; '\0'
+  0x20000896:  00           DC.B       0x00                     ; '\0'
+  0x20000897:  00           DC.B       0x00                     ; '\0'
+  0x20000898:  00           DC.B       0x00                     ; '\0'
+  0x20000899:  00           DC.B       0x00                     ; '\0'
+  0x2000089A:  00           DC.B       0x00                     ; '\0'
+  0x2000089B:  00           DC.B       0x00                     ; '\0'
+  0x2000089C:  00           DC.B       0x00                     ; '\0'
+  0x2000089D:  07           DC.B       0x07                     ; '\x07'
+  0x2000089E:  00           DC.B       0x00                     ; '\0'
+  0x2000089F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008A0:  00           DC.B       0x00                     ; '\0'
+  0x200008A1:  00           DC.B       0x00                     ; '\0'
+  0x200008A2:  00           DC.B       0x00                     ; '\0'
+  0x200008A3:  00           DC.B       0x00                     ; '\0'
+  0x200008A4:  00           DC.B       0x00                     ; '\0'
+  0x200008A5:  00           DC.B       0x00                     ; '\0'
+  0x200008A6:  00           DC.B       0x00                     ; '\0'
+  0x200008A7:  00           DC.B       0x00                     ; '\0'
+  0x200008A8:  00           DC.B       0x00                     ; '\0'
+  0x200008A9:  00           DC.B       0x00                     ; '\0'
+  0x200008AA:  00           DC.B       0x00                     ; '\0'
+  0x200008AB:  00           DC.B       0x00                     ; '\0'
+  0x200008AC:  00           DC.B       0x00                     ; '\0'
+  0x200008AD:  09           DC.B       0x09                     ; '\t'
+  0x200008AE:  00           DC.B       0x00                     ; '\0'
+  0x200008AF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008B0:  00           DC.B       0x00                     ; '\0'
+  0x200008B1:  00           DC.B       0x00                     ; '\0'
+  0x200008B2:  00           DC.B       0x00                     ; '\0'
+  0x200008B3:  00           DC.B       0x00                     ; '\0'
+  0x200008B4:  00           DC.B       0x00                     ; '\0'
+  0x200008B5:  00           DC.B       0x00                     ; '\0'
+  0x200008B6:  00           DC.B       0x00                     ; '\0'
+  0x200008B7:  00           DC.B       0x00                     ; '\0'
+  0x200008B8:  00           DC.B       0x00                     ; '\0'
+  0x200008B9:  00           DC.B       0x00                     ; '\0'
+  0x200008BA:  00           DC.B       0x00                     ; '\0'
+  0x200008BB:  00           DC.B       0x00                     ; '\0'
+  0x200008BC:  00           DC.B       0x00                     ; '\0'
+  0x200008BD:  0B           DC.B       0x0B                     ; '\v'
+  0x200008BE:  00           DC.B       0x00                     ; '\0'
+  0x200008BF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008C0:  00           DC.B       0x00                     ; '\0'
+  0x200008C1:  00           DC.B       0x00                     ; '\0'
+  0x200008C2:  00           DC.B       0x00                     ; '\0'
+  0x200008C3:  00           DC.B       0x00                     ; '\0'
+  0x200008C4:  00           DC.B       0x00                     ; '\0'
+  0x200008C5:  00           DC.B       0x00                     ; '\0'
+  0x200008C6:  00           DC.B       0x00                     ; '\0'
+  0x200008C7:  00           DC.B       0x00                     ; '\0'
+  0x200008C8:  00           DC.B       0x00                     ; '\0'
+  0x200008C9:  00           DC.B       0x00                     ; '\0'
+  0x200008CA:  00           DC.B       0x00                     ; '\0'
+  0x200008CB:  00           DC.B       0x00                     ; '\0'
+  0x200008CC:  00           DC.B       0x00                     ; '\0'
+  0x200008CD:  0D           DC.B       0x0D                     ; '\r'
+  0x200008CE:  00           DC.B       0x00                     ; '\0'
+  0x200008CF:  32           DC.B       0x32                     ; '2'
+  0x200008D0:  06           DC.B       0x06                     ; '\x06'
+  0x200008D1:  00           DC.B       0x00                     ; '\0'
+  0x200008D2:  00           DC.B       0x00                     ; '\0'
+  0x200008D3:  84           DC.B       0x84                     ; '\x84'
+  0x200008D4:  00           DC.B       0x00                     ; '\0'
+  0x200008D5:  00           DC.B       0x00                     ; '\0'
+  0x200008D6:  00           DC.B       0x00                     ; '\0'
+  0x200008D7:  00           DC.B       0x00                     ; '\0'
+  0x200008D8:  00           DC.B       0x00                     ; '\0'
+  0x200008D9:  00           DC.B       0x00                     ; '\0'
+  0x200008DA:  00           DC.B       0x00                     ; '\0'
+  0x200008DB:  00           DC.B       0x00                     ; '\0'
+  0x200008DC:  00           DC.B       0x00                     ; '\0'
+  0x200008DD:  0D           DC.B       0x0D                     ; '\r'
+  0x200008DE:  00           DC.B       0x00                     ; '\0'
+  0x200008DF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008E0:  00           DC.B       0x00                     ; '\0'
+  0x200008E1:  00           DC.B       0x00                     ; '\0'
+  0x200008E2:  00           DC.B       0x00                     ; '\0'
+  0x200008E3:  00           DC.B       0x00                     ; '\0'
+  0x200008E4:  00           DC.B       0x00                     ; '\0'
+  0x200008E5:  00           DC.B       0x00                     ; '\0'
+  0x200008E6:  00           DC.B       0x00                     ; '\0'
+  0x200008E7:  00           DC.B       0x00                     ; '\0'
+  0x200008E8:  00           DC.B       0x00                     ; '\0'
+  0x200008E9:  00           DC.B       0x00                     ; '\0'
+  0x200008EA:  00           DC.B       0x00                     ; '\0'
+  0x200008EB:  00           DC.B       0x00                     ; '\0'
+  0x200008EC:  00           DC.B       0x00                     ; '\0'
+  0x200008ED:  0F           DC.B       0x0F                     ; '\x0F'
+  0x200008EE:  00           DC.B       0x00                     ; '\0'
+  0x200008EF:  32           DC.B       0x32                     ; '2'
+  0x200008F0:  06           DC.B       0x06                     ; '\x06'
+  0x200008F1:  00           DC.B       0x00                     ; '\0'
+  0x200008F2:  00           DC.B       0x00                     ; '\0'
+  0x200008F3:  68           DC.B       0x68                     ; 'h'
+  0x200008F4:  00           DC.B       0x00                     ; '\0'
+  0x200008F5:  00           DC.B       0x00                     ; '\0'
+  0x200008F6:  00           DC.B       0x00                     ; '\0'
+  0x200008F7:  00           DC.B       0x00                     ; '\0'
+  0x200008F8:  00           DC.B       0x00                     ; '\0'
+  0x200008F9:  00           DC.B       0x00                     ; '\0'
+  0x200008FA:  00           DC.B       0x00                     ; '\0'
+  0x200008FB:  00           DC.B       0x00                     ; '\0'
+  0x200008FC:  00           DC.B       0x00                     ; '\0'
+  0x200008FD:  0F           DC.B       0x0F                     ; '\x0F'
+  0x200008FE:  00           DC.B       0x00                     ; '\0'
+  0x200008FF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000900:  00           DC.B       0x00                     ; '\0'
+  0x20000901:  00           DC.B       0x00                     ; '\0'
+  0x20000902:  00           DC.B       0x00                     ; '\0'
+  0x20000903:  00           DC.B       0x00                     ; '\0'
+  0x20000904:  00           DC.B       0x00                     ; '\0'
+  0x20000905:  00           DC.B       0x00                     ; '\0'
+  0x20000906:  00           DC.B       0x00                     ; '\0'
+  0x20000907:  00           DC.B       0x00                     ; '\0'
+  0x20000908:  00           DC.B       0x00                     ; '\0'
+  0x20000909:  00           DC.B       0x00                     ; '\0'
+  0x2000090A:  00           DC.B       0x00                     ; '\0'
+  0x2000090B:  00           DC.B       0x00                     ; '\0'
+  0x2000090C:  00           DC.B       0x00                     ; '\0'
+  0x2000090D:  11           DC.B       0x11                     ; '\x11'
+  0x2000090E:  00           DC.B       0x00                     ; '\0'
+  0x2000090F:  E5           DC.B       0xE5                     ; '\xE5'
+  0x20000910:  05           DC.B       0x05                     ; '\x05'
+  0x20000911:  00           DC.B       0x00                     ; '\0'
+  0x20000912:  00           DC.B       0x00                     ; '\0'
+  0x20000913:  01           DC.B       0x01                     ; '\x01'
+  0x20000914:  00           DC.B       0x00                     ; '\0'
+  0x20000915:  00           DC.B       0x00                     ; '\0'
+  0x20000916:  00           DC.B       0x00                     ; '\0'
+  0x20000917:  16           DC.B       0x16                     ; '\x16'
+  0x20000918:  00           DC.B       0x00                     ; '\0'
+  0x20000919:  00           DC.B       0x00                     ; '\0'
+  0x2000091A:  00           DC.B       0x00                     ; '\0'
+  0x2000091B:  02           DC.B       0x02                     ; '\x02'
+  0x2000091C:  00           DC.B       0x00                     ; '\0'
+  0x2000091D:  13           DC.B       0x13                     ; '\x13'
+  0x2000091E:  00           DC.B       0x00                     ; '\0'
+  0x2000091F:  08           DC.B       0x08                     ; '\b'
+  0x20000920:  05           DC.B       0x05                     ; '\x05'
+  0x20000921:  00           DC.B       0x00                     ; '\0'
+  0x20000922:  00           DC.B       0x00                     ; '\0'
+  0x20000923:  01           DC.B       0x01                     ; '\x01'
+  0x20000924:  00           DC.B       0x00                     ; '\0'
+  0x20000925:  00           DC.B       0x00                     ; '\0'
+  0x20000926:  00           DC.B       0x00                     ; '\0'
+  0x20000927:  3A           DC.B       0x3A                     ; ':'
+  0x20000928:  00           DC.B       0x00                     ; '\0'
+  0x20000929:  00           DC.B       0x00                     ; '\0'
+  0x2000092A:  00           DC.B       0x00                     ; '\0'
+  0x2000092B:  02           DC.B       0x02                     ; '\x02'
+  0x2000092C:  00           DC.B       0x00                     ; '\0'
+  0x2000092D:  14           DC.B       0x14                     ; '\x14'
+  0x2000092E:  00           DC.B       0x00                     ; '\0'
+  0x2000092F:  7E           DC.B       0x7E                     ; '~'
+  0x20000930:  05           DC.B       0x05                     ; '\x05'
+  0x20000931:  00           DC.B       0x00                     ; '\0'
+  0x20000932:  00           DC.B       0x00                     ; '\0'
+  0x20000933:  01           DC.B       0x01                     ; '\x01'
+  0x20000934:  00           DC.B       0x00                     ; '\0'
+  0x20000935:  00           DC.B       0x00                     ; '\0'
+  0x20000936:  00           DC.B       0x00                     ; '\0'
+  0x20000937:  58           DC.B       0x58                     ; 'X'
+  0x20000938:  00           DC.B       0x00                     ; '\0'
+  0x20000939:  00           DC.B       0x00                     ; '\0'
+  0x2000093A:  00           DC.B       0x00                     ; '\0'
+  0x2000093B:  02           DC.B       0x02                     ; '\x02'
+  0x2000093C:  00           DC.B       0x00                     ; '\0'
+  0x2000093D:  16           DC.B       0x16                     ; '\x16'
+  0x2000093E:  00           DC.B       0x00                     ; '\0'
+  0x2000093F:  32           DC.B       0x32                     ; '2'
+  0x20000940:  06           DC.B       0x06                     ; '\x06'
+  0x20000941:  00           DC.B       0x00                     ; '\0'
+  0x20000942:  00           DC.B       0x00                     ; '\0'
+  0x20000943:  64           DC.B       0x64                     ; 'd'
+  0x20000944:  00           DC.B       0x00                     ; '\0'
+  0x20000945:  00           DC.B       0x00                     ; '\0'
+  0x20000946:  00           DC.B       0x00                     ; '\0'
+  0x20000947:  00           DC.B       0x00                     ; '\0'
+  0x20000948:  00           DC.B       0x00                     ; '\0'
+  0x20000949:  00           DC.B       0x00                     ; '\0'
+  0x2000094A:  00           DC.B       0x00                     ; '\0'
+  0x2000094B:  00           DC.B       0x00                     ; '\0'
+  0x2000094C:  00           DC.B       0x00                     ; '\0'
+  0x2000094D:  11           DC.B       0x11                     ; '\x11'
+  0x2000094E:  00           DC.B       0x00                     ; '\0'
+  0x2000094F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000950:  00           DC.B       0x00                     ; '\0'
+  0x20000951:  00           DC.B       0x00                     ; '\0'
+  0x20000952:  00           DC.B       0x00                     ; '\0'
+  0x20000953:  00           DC.B       0x00                     ; '\0'
+  0x20000954:  00           DC.B       0x00                     ; '\0'
+  0x20000955:  00           DC.B       0x00                     ; '\0'
+  0x20000956:  00           DC.B       0x00                     ; '\0'
+  0x20000957:  00           DC.B       0x00                     ; '\0'
+  0x20000958:  00           DC.B       0x00                     ; '\0'
+  0x20000959:  00           DC.B       0x00                     ; '\0'
+  0x2000095A:  00           DC.B       0x00                     ; '\0'
+  0x2000095B:  00           DC.B       0x00                     ; '\0'
+  0x2000095C:  00           DC.B       0x00                     ; '\0'
+  0x2000095D:  13           DC.B       0x13                     ; '\x13'
+  0x2000095E:  00           DC.B       0x00                     ; '\0'
+  0x2000095F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000960:  00           DC.B       0x00                     ; '\0'
+  0x20000961:  00           DC.B       0x00                     ; '\0'
+  0x20000962:  00           DC.B       0x00                     ; '\0'
+  0x20000963:  00           DC.B       0x00                     ; '\0'
+  0x20000964:  00           DC.B       0x00                     ; '\0'
+  0x20000965:  00           DC.B       0x00                     ; '\0'
+  0x20000966:  00           DC.B       0x00                     ; '\0'
+  0x20000967:  00           DC.B       0x00                     ; '\0'
+  0x20000968:  00           DC.B       0x00                     ; '\0'
+  0x20000969:  00           DC.B       0x00                     ; '\0'
+  0x2000096A:  00           DC.B       0x00                     ; '\0'
+  0x2000096B:  00           DC.B       0x00                     ; '\0'
+  0x2000096C:  00           DC.B       0x00                     ; '\0'
+  0x2000096D:  14           DC.B       0x14                     ; '\x14'
+  0x2000096E:  00           DC.B       0x00                     ; '\0'
+  0x2000096F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000970:  00           DC.B       0x00                     ; '\0'
+  0x20000971:  00           DC.B       0x00                     ; '\0'
+  0x20000972:  00           DC.B       0x00                     ; '\0'
+  0x20000973:  00           DC.B       0x00                     ; '\0'
+  0x20000974:  00           DC.B       0x00                     ; '\0'
+  0x20000975:  00           DC.B       0x00                     ; '\0'
+  0x20000976:  00           DC.B       0x00                     ; '\0'
+  0x20000977:  00           DC.B       0x00                     ; '\0'
+  0x20000978:  00           DC.B       0x00                     ; '\0'
+  0x20000979:  00           DC.B       0x00                     ; '\0'
+  0x2000097A:  00           DC.B       0x00                     ; '\0'
+  0x2000097B:  00           DC.B       0x00                     ; '\0'
+  0x2000097C:  00           DC.B       0x00                     ; '\0'
+  0x2000097D:  16           DC.B       0x16                     ; '\x16'
+  0x2000097E:  00           DC.B       0x00                     ; '\0'
+  0x2000097F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000980:  00           DC.B       0x00                     ; '\0'
+  0x20000981:  00           DC.B       0x00                     ; '\0'
+  0x20000982:  00           DC.B       0x00                     ; '\0'
+  0x20000983:  00           DC.B       0x00                     ; '\0'
+  0x20000984:  00           DC.B       0x00                     ; '\0'
+  0x20000985:  00           DC.B       0x00                     ; '\0'
+  0x20000986:  00           DC.B       0x00                     ; '\0'
+  0x20000987:  00           DC.B       0x00                     ; '\0'
+  0x20000988:  00           DC.B       0x00                     ; '\0'
+  0x20000989:  00           DC.B       0x00                     ; '\0'
+  0x2000098A:  00           DC.B       0x00                     ; '\0'
+  0x2000098B:  00           DC.B       0x00                     ; '\0'
+  0x2000098C:  00           DC.B       0x00                     ; '\0'
+  0x2000098D:  18           DC.B       0x18                     ; '\x18'
+  0x2000098E:  00           DC.B       0x00                     ; '\0'
+  0x2000098F:  32           DC.B       0x32                     ; '2'
+  0x20000990:  06           DC.B       0x06                     ; '\x06'
+  0x20000991:  00           DC.B       0x00                     ; '\0'
+  0x20000992:  00           DC.B       0x00                     ; '\0'
+  0x20000993:  64           DC.B       0x64                     ; 'd'
+  0x20000994:  00           DC.B       0x00                     ; '\0'
+  0x20000995:  00           DC.B       0x00                     ; '\0'
+  0x20000996:  00           DC.B       0x00                     ; '\0'
+  0x20000997:  00           DC.B       0x00                     ; '\0'
+  0x20000998:  00           DC.B       0x00                     ; '\0'
+  0x20000999:  00           DC.B       0x00                     ; '\0'
+  0x2000099A:  00           DC.B       0x00                     ; '\0'
+  0x2000099B:  00           DC.B       0x00                     ; '\0'
+  0x2000099C:  00           DC.B       0x00                     ; '\0'
+  0x2000099D:  18           DC.B       0x18                     ; '\x18'
+  0x2000099E:  00           DC.B       0x00                     ; '\0'
+  0x2000099F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009A0:  00           DC.B       0x00                     ; '\0'
+  0x200009A1:  00           DC.B       0x00                     ; '\0'
+  0x200009A2:  00           DC.B       0x00                     ; '\0'
+  0x200009A3:  00           DC.B       0x00                     ; '\0'
+  0x200009A4:  00           DC.B       0x00                     ; '\0'
+  0x200009A5:  00           DC.B       0x00                     ; '\0'
+  0x200009A6:  00           DC.B       0x00                     ; '\0'
+  0x200009A7:  00           DC.B       0x00                     ; '\0'
+  0x200009A8:  00           DC.B       0x00                     ; '\0'
+  0x200009A9:  00           DC.B       0x00                     ; '\0'
+  0x200009AA:  00           DC.B       0x00                     ; '\0'
+  0x200009AB:  00           DC.B       0x00                     ; '\0'
+  0x200009AC:  00           DC.B       0x00                     ; '\0'
+  0x200009AD:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200009AE:  00           DC.B       0x00                     ; '\0'
+  0x200009AF:  32           DC.B       0x32                     ; '2'
+  0x200009B0:  06           DC.B       0x06                     ; '\x06'
+  0x200009B1:  00           DC.B       0x00                     ; '\0'
+  0x200009B2:  00           DC.B       0x00                     ; '\0'
+  0x200009B3:  34           DC.B       0x34                     ; '4'
+  0x200009B4:  00           DC.B       0x00                     ; '\0'
+  0x200009B5:  00           DC.B       0x00                     ; '\0'
+  0x200009B6:  00           DC.B       0x00                     ; '\0'
+  0x200009B7:  00           DC.B       0x00                     ; '\0'
+  0x200009B8:  00           DC.B       0x00                     ; '\0'
+  0x200009B9:  00           DC.B       0x00                     ; '\0'
+  0x200009BA:  00           DC.B       0x00                     ; '\0'
+  0x200009BB:  00           DC.B       0x00                     ; '\0'
+  0x200009BC:  00           DC.B       0x00                     ; '\0'
+  0x200009BD:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200009BE:  00           DC.B       0x00                     ; '\0'
+  0x200009BF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009C0:  00           DC.B       0x00                     ; '\0'
+  0x200009C1:  00           DC.B       0x00                     ; '\0'
+  0x200009C2:  00           DC.B       0x00                     ; '\0'
+  0x200009C3:  00           DC.B       0x00                     ; '\0'
+  0x200009C4:  00           DC.B       0x00                     ; '\0'
+  0x200009C5:  00           DC.B       0x00                     ; '\0'
+  0x200009C6:  00           DC.B       0x00                     ; '\0'
+  0x200009C7:  00           DC.B       0x00                     ; '\0'
+  0x200009C8:  00           DC.B       0x00                     ; '\0'
+  0x200009C9:  00           DC.B       0x00                     ; '\0'
+  0x200009CA:  00           DC.B       0x00                     ; '\0'
+  0x200009CB:  00           DC.B       0x00                     ; '\0'
+  0x200009CC:  00           DC.B       0x00                     ; '\0'
+  0x200009CD:  1C           DC.B       0x1C                     ; '\x1C'
+  0x200009CE:  00           DC.B       0x00                     ; '\0'
+  0x200009CF:  32           DC.B       0x32                     ; '2'
+  0x200009D0:  06           DC.B       0x06                     ; '\x06'
+  0x200009D1:  00           DC.B       0x00                     ; '\0'
+  0x200009D2:  00           DC.B       0x00                     ; '\0'
+  0x200009D3:  34           DC.B       0x34                     ; '4'
+  0x200009D4:  00           DC.B       0x00                     ; '\0'
+  0x200009D5:  00           DC.B       0x00                     ; '\0'
+  0x200009D6:  00           DC.B       0x00                     ; '\0'
+  0x200009D7:  00           DC.B       0x00                     ; '\0'
+  0x200009D8:  00           DC.B       0x00                     ; '\0'
+  0x200009D9:  00           DC.B       0x00                     ; '\0'
+  0x200009DA:  00           DC.B       0x00                     ; '\0'
+  0x200009DB:  00           DC.B       0x00                     ; '\0'
+  0x200009DC:  00           DC.B       0x00                     ; '\0'
+  0x200009DD:  1C           DC.B       0x1C                     ; '\x1C'
+  0x200009DE:  00           DC.B       0x00                     ; '\0'
+  0x200009DF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009E0:  00           DC.B       0x00                     ; '\0'
+  0x200009E1:  00           DC.B       0x00                     ; '\0'
+  0x200009E2:  00           DC.B       0x00                     ; '\0'
+  0x200009E3:  00           DC.B       0x00                     ; '\0'
+  0x200009E4:  00           DC.B       0x00                     ; '\0'
+  0x200009E5:  00           DC.B       0x00                     ; '\0'
+  0x200009E6:  00           DC.B       0x00                     ; '\0'
+  0x200009E7:  00           DC.B       0x00                     ; '\0'
+  0x200009E8:  00           DC.B       0x00                     ; '\0'
+  0x200009E9:  00           DC.B       0x00                     ; '\0'
+  0x200009EA:  00           DC.B       0x00                     ; '\0'
+  0x200009EB:  00           DC.B       0x00                     ; '\0'
+  0x200009EC:  00           DC.B       0x00                     ; '\0'
+  0x200009ED:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200009EE:  00           DC.B       0x00                     ; '\0'
+  0x200009EF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009F0:  00           DC.B       0x00                     ; '\0'
+  0x200009F1:  00           DC.B       0x00                     ; '\0'
+  0x200009F2:  00           DC.B       0x00                     ; '\0'
+  0x200009F3:  00           DC.B       0x00                     ; '\0'
+  0x200009F4:  00           DC.B       0x00                     ; '\0'
+  0x200009F5:  00           DC.B       0x00                     ; '\0'
+  0x200009F6:  00           DC.B       0x00                     ; '\0'
+  0x200009F7:  00           DC.B       0x00                     ; '\0'
+  0x200009F8:  00           DC.B       0x00                     ; '\0'
+  0x200009F9:  00           DC.B       0x00                     ; '\0'
+  0x200009FA:  00           DC.B       0x00                     ; '\0'
+  0x200009FB:  00           DC.B       0x00                     ; '\0'
+  0x200009FC:  00           DC.B       0x00                     ; '\0'
+  0x200009FD:  20           DC.B       0x20                     ; ' '
+  0x200009FE:  00           DC.B       0x00                     ; '\0'
+  0x200009FF:  32           DC.B       0x32                     ; '2'
+  0x20000A00:  06           DC.B       0x06                     ; '\x06'
+  0x20000A01:  00           DC.B       0x00                     ; '\0'
+  0x20000A02:  00           DC.B       0x00                     ; '\0'
+  0x20000A03:  2C           DC.B       0x2C                     ; ','
+  0x20000A04:  00           DC.B       0x00                     ; '\0'
+  0x20000A05:  00           DC.B       0x00                     ; '\0'
+  0x20000A06:  00           DC.B       0x00                     ; '\0'
+  0x20000A07:  00           DC.B       0x00                     ; '\0'
+  0x20000A08:  00           DC.B       0x00                     ; '\0'
+  0x20000A09:  00           DC.B       0x00                     ; '\0'
+  0x20000A0A:  00           DC.B       0x00                     ; '\0'
+  0x20000A0B:  00           DC.B       0x00                     ; '\0'
+  0x20000A0C:  00           DC.B       0x00                     ; '\0'
+  0x20000A0D:  20           DC.B       0x20                     ; ' '
+  0x20000A0E:  00           DC.B       0x00                     ; '\0'
+  0x20000A0F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A10:  00           DC.B       0x00                     ; '\0'
+  0x20000A11:  00           DC.B       0x00                     ; '\0'
+  0x20000A12:  00           DC.B       0x00                     ; '\0'
+  0x20000A13:  00           DC.B       0x00                     ; '\0'
+  0x20000A14:  00           DC.B       0x00                     ; '\0'
+  0x20000A15:  00           DC.B       0x00                     ; '\0'
+  0x20000A16:  00           DC.B       0x00                     ; '\0'
+  0x20000A17:  00           DC.B       0x00                     ; '\0'
+  0x20000A18:  00           DC.B       0x00                     ; '\0'
+  0x20000A19:  00           DC.B       0x00                     ; '\0'
+  0x20000A1A:  00           DC.B       0x00                     ; '\0'
+  0x20000A1B:  00           DC.B       0x00                     ; '\0'
+  0x20000A1C:  00           DC.B       0x00                     ; '\0'
+  0x20000A1D:  22           DC.B       0x22                     ; '\"'
+  0x20000A1E:  00           DC.B       0x00                     ; '\0'
+  0x20000A1F:  32           DC.B       0x32                     ; '2'
+  0x20000A20:  06           DC.B       0x06                     ; '\x06'
+  0x20000A21:  00           DC.B       0x00                     ; '\0'
+  0x20000A22:  00           DC.B       0x00                     ; '\0'
+  0x20000A23:  48           DC.B       0x48                     ; 'H'
+  0x20000A24:  00           DC.B       0x00                     ; '\0'
+  0x20000A25:  00           DC.B       0x00                     ; '\0'
+  0x20000A26:  00           DC.B       0x00                     ; '\0'
+  0x20000A27:  00           DC.B       0x00                     ; '\0'
+  0x20000A28:  00           DC.B       0x00                     ; '\0'
+  0x20000A29:  00           DC.B       0x00                     ; '\0'
+  0x20000A2A:  00           DC.B       0x00                     ; '\0'
+  0x20000A2B:  00           DC.B       0x00                     ; '\0'
+  0x20000A2C:  00           DC.B       0x00                     ; '\0'
+  0x20000A2D:  22           DC.B       0x22                     ; '\"'
+  0x20000A2E:  00           DC.B       0x00                     ; '\0'
+  0x20000A2F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A30:  00           DC.B       0x00                     ; '\0'
+  0x20000A31:  00           DC.B       0x00                     ; '\0'
+  0x20000A32:  00           DC.B       0x00                     ; '\0'
+  0x20000A33:  00           DC.B       0x00                     ; '\0'
+  0x20000A34:  00           DC.B       0x00                     ; '\0'
+  0x20000A35:  00           DC.B       0x00                     ; '\0'
+  0x20000A36:  00           DC.B       0x00                     ; '\0'
+  0x20000A37:  00           DC.B       0x00                     ; '\0'
+  0x20000A38:  00           DC.B       0x00                     ; '\0'
+  0x20000A39:  00           DC.B       0x00                     ; '\0'
+  0x20000A3A:  00           DC.B       0x00                     ; '\0'
+  0x20000A3B:  00           DC.B       0x00                     ; '\0'
+  0x20000A3C:  00           DC.B       0x00                     ; '\0'
+  0x20000A3D:  24           DC.B       0x24                     ; '$'
+  0x20000A3E:  00           DC.B       0x00                     ; '\0'
+  0x20000A3F:  32           DC.B       0x32                     ; '2'
+  0x20000A40:  06           DC.B       0x06                     ; '\x06'
+  0x20000A41:  00           DC.B       0x00                     ; '\0'
+  0x20000A42:  00           DC.B       0x00                     ; '\0'
+  0x20000A43:  54           DC.B       0x54                     ; 'T'
+  0x20000A44:  00           DC.B       0x00                     ; '\0'
+  0x20000A45:  00           DC.B       0x00                     ; '\0'
+  0x20000A46:  00           DC.B       0x00                     ; '\0'
+  0x20000A47:  00           DC.B       0x00                     ; '\0'
+  0x20000A48:  00           DC.B       0x00                     ; '\0'
+  0x20000A49:  00           DC.B       0x00                     ; '\0'
+  0x20000A4A:  00           DC.B       0x00                     ; '\0'
+  0x20000A4B:  00           DC.B       0x00                     ; '\0'
+  0x20000A4C:  00           DC.B       0x00                     ; '\0'
+  0x20000A4D:  24           DC.B       0x24                     ; '$'
+  0x20000A4E:  00           DC.B       0x00                     ; '\0'
+  0x20000A4F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A50:  00           DC.B       0x00                     ; '\0'
+  0x20000A51:  00           DC.B       0x00                     ; '\0'
+  0x20000A52:  00           DC.B       0x00                     ; '\0'
+  0x20000A53:  00           DC.B       0x00                     ; '\0'
+  0x20000A54:  00           DC.B       0x00                     ; '\0'
+  0x20000A55:  00           DC.B       0x00                     ; '\0'
+  0x20000A56:  00           DC.B       0x00                     ; '\0'
+  0x20000A57:  00           DC.B       0x00                     ; '\0'
+  0x20000A58:  00           DC.B       0x00                     ; '\0'
+  0x20000A59:  00           DC.B       0x00                     ; '\0'
+  0x20000A5A:  00           DC.B       0x00                     ; '\0'
+  0x20000A5B:  00           DC.B       0x00                     ; '\0'
+  0x20000A5C:  00           DC.B       0x00                     ; '\0'
+  0x20000A5D:  26           DC.B       0x26                     ; '&'
+  0x20000A5E:  00           DC.B       0x00                     ; '\0'
+  0x20000A5F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A60:  00           DC.B       0x00                     ; '\0'
+  0x20000A61:  00           DC.B       0x00                     ; '\0'
+  0x20000A62:  00           DC.B       0x00                     ; '\0'
+  0x20000A63:  00           DC.B       0x00                     ; '\0'
+  0x20000A64:  00           DC.B       0x00                     ; '\0'
+  0x20000A65:  00           DC.B       0x00                     ; '\0'
+  0x20000A66:  00           DC.B       0x00                     ; '\0'
+  0x20000A67:  00           DC.B       0x00                     ; '\0'
+  0x20000A68:  00           DC.B       0x00                     ; '\0'
+  0x20000A69:  00           DC.B       0x00                     ; '\0'
+  0x20000A6A:  00           DC.B       0x00                     ; '\0'
+  0x20000A6B:  00           DC.B       0x00                     ; '\0'
+  0x20000A6C:  00           DC.B       0x00                     ; '\0'
+  0x20000A6D:  28           DC.B       0x28                     ; '('
+  0x20000A6E:  00           DC.B       0x00                     ; '\0'
+  0x20000A6F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A70:  00           DC.B       0x00                     ; '\0'
+  0x20000A71:  00           DC.B       0x00                     ; '\0'
+  0x20000A72:  00           DC.B       0x00                     ; '\0'
+  0x20000A73:  00           DC.B       0x00                     ; '\0'
+  0x20000A74:  00           DC.B       0x00                     ; '\0'
+  0x20000A75:  00           DC.B       0x00                     ; '\0'
+  0x20000A76:  00           DC.B       0x00                     ; '\0'
+  0x20000A77:  00           DC.B       0x00                     ; '\0'
+  0x20000A78:  00           DC.B       0x00                     ; '\0'
+  0x20000A79:  00           DC.B       0x00                     ; '\0'
+  0x20000A7A:  00           DC.B       0x00                     ; '\0'
+  0x20000A7B:  00           DC.B       0x00                     ; '\0'
+  0x20000A7C:  00           DC.B       0x00                     ; '\0'
+  0x20000A7D:  2A           DC.B       0x2A                     ; '*'
+  0x20000A7E:  00           DC.B       0x00                     ; '\0'
+  0x20000A7F:  32           DC.B       0x32                     ; '2'
+  0x20000A80:  06           DC.B       0x06                     ; '\x06'
+  0x20000A81:  00           DC.B       0x00                     ; '\0'
+  0x20000A82:  00           DC.B       0x00                     ; '\0'
+  0x20000A83:  1C           DC.B       0x1C                     ; '\x1C'
+  0x20000A84:  00           DC.B       0x00                     ; '\0'
+  0x20000A85:  00           DC.B       0x00                     ; '\0'
+  0x20000A86:  00           DC.B       0x00                     ; '\0'
+  0x20000A87:  00           DC.B       0x00                     ; '\0'
+  0x20000A88:  00           DC.B       0x00                     ; '\0'
+  0x20000A89:  00           DC.B       0x00                     ; '\0'
+  0x20000A8A:  00           DC.B       0x00                     ; '\0'
+  0x20000A8B:  00           DC.B       0x00                     ; '\0'
+  0x20000A8C:  00           DC.B       0x00                     ; '\0'
+  0x20000A8D:  2A           DC.B       0x2A                     ; '*'
+  0x20000A8E:  00           DC.B       0x00                     ; '\0'
+  0x20000A8F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A90:  00           DC.B       0x00                     ; '\0'
+  0x20000A91:  00           DC.B       0x00                     ; '\0'
+  0x20000A92:  00           DC.B       0x00                     ; '\0'
+  0x20000A93:  00           DC.B       0x00                     ; '\0'
+  0x20000A94:  00           DC.B       0x00                     ; '\0'
+  0x20000A95:  00           DC.B       0x00                     ; '\0'
+  0x20000A96:  00           DC.B       0x00                     ; '\0'
+  0x20000A97:  00           DC.B       0x00                     ; '\0'
+  0x20000A98:  00           DC.B       0x00                     ; '\0'
+  0x20000A99:  00           DC.B       0x00                     ; '\0'
+  0x20000A9A:  00           DC.B       0x00                     ; '\0'
+  0x20000A9B:  00           DC.B       0x00                     ; '\0'
+  0x20000A9C:  00           DC.B       0x00                     ; '\0'
+  0x20000A9D:  2C           DC.B       0x2C                     ; ','
+  0x20000A9E:  00           DC.B       0x00                     ; '\0'
+  0x20000A9F:  32           DC.B       0x32                     ; '2'
+  0x20000AA0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AA1:  00           DC.B       0x00                     ; '\0'
+  0x20000AA2:  00           DC.B       0x00                     ; '\0'
+  0x20000AA3:  10           DC.B       0x10                     ; '\x10'
+  0x20000AA4:  00           DC.B       0x00                     ; '\0'
+  0x20000AA5:  00           DC.B       0x00                     ; '\0'
+  0x20000AA6:  00           DC.B       0x00                     ; '\0'
+  0x20000AA7:  00           DC.B       0x00                     ; '\0'
+  0x20000AA8:  00           DC.B       0x00                     ; '\0'
+  0x20000AA9:  00           DC.B       0x00                     ; '\0'
+  0x20000AAA:  00           DC.B       0x00                     ; '\0'
+  0x20000AAB:  00           DC.B       0x00                     ; '\0'
+  0x20000AAC:  00           DC.B       0x00                     ; '\0'
+  0x20000AAD:  2C           DC.B       0x2C                     ; ','
+  0x20000AAE:  00           DC.B       0x00                     ; '\0'
+  0x20000AAF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AB0:  00           DC.B       0x00                     ; '\0'
+  0x20000AB1:  00           DC.B       0x00                     ; '\0'
+  0x20000AB2:  00           DC.B       0x00                     ; '\0'
+  0x20000AB3:  00           DC.B       0x00                     ; '\0'
+  0x20000AB4:  00           DC.B       0x00                     ; '\0'
+  0x20000AB5:  00           DC.B       0x00                     ; '\0'
+  0x20000AB6:  00           DC.B       0x00                     ; '\0'
+  0x20000AB7:  00           DC.B       0x00                     ; '\0'
+  0x20000AB8:  00           DC.B       0x00                     ; '\0'
+  0x20000AB9:  00           DC.B       0x00                     ; '\0'
+  0x20000ABA:  00           DC.B       0x00                     ; '\0'
+  0x20000ABB:  00           DC.B       0x00                     ; '\0'
+  0x20000ABC:  00           DC.B       0x00                     ; '\0'
+  0x20000ABD:  2E           DC.B       0x2E                     ; '.'
+  0x20000ABE:  00           DC.B       0x00                     ; '\0'
+  0x20000ABF:  32           DC.B       0x32                     ; '2'
+  0x20000AC0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AC1:  00           DC.B       0x00                     ; '\0'
+  0x20000AC2:  00           DC.B       0x00                     ; '\0'
+  0x20000AC3:  10           DC.B       0x10                     ; '\x10'
+  0x20000AC4:  00           DC.B       0x00                     ; '\0'
+  0x20000AC5:  00           DC.B       0x00                     ; '\0'
+  0x20000AC6:  00           DC.B       0x00                     ; '\0'
+  0x20000AC7:  00           DC.B       0x00                     ; '\0'
+  0x20000AC8:  00           DC.B       0x00                     ; '\0'
+  0x20000AC9:  00           DC.B       0x00                     ; '\0'
+  0x20000ACA:  00           DC.B       0x00                     ; '\0'
+  0x20000ACB:  00           DC.B       0x00                     ; '\0'
+  0x20000ACC:  00           DC.B       0x00                     ; '\0'
+  0x20000ACD:  2E           DC.B       0x2E                     ; '.'
+  0x20000ACE:  00           DC.B       0x00                     ; '\0'
+  0x20000ACF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AD0:  00           DC.B       0x00                     ; '\0'
+  0x20000AD1:  00           DC.B       0x00                     ; '\0'
+  0x20000AD2:  00           DC.B       0x00                     ; '\0'
+  0x20000AD3:  00           DC.B       0x00                     ; '\0'
+  0x20000AD4:  00           DC.B       0x00                     ; '\0'
+  0x20000AD5:  00           DC.B       0x00                     ; '\0'
+  0x20000AD6:  00           DC.B       0x00                     ; '\0'
+  0x20000AD7:  00           DC.B       0x00                     ; '\0'
+  0x20000AD8:  00           DC.B       0x00                     ; '\0'
+  0x20000AD9:  00           DC.B       0x00                     ; '\0'
+  0x20000ADA:  00           DC.B       0x00                     ; '\0'
+  0x20000ADB:  00           DC.B       0x00                     ; '\0'
+  0x20000ADC:  00           DC.B       0x00                     ; '\0'
+  0x20000ADD:  30           DC.B       0x30                     ; '0'
+  0x20000ADE:  00           DC.B       0x00                     ; '\0'
+  0x20000ADF:  32           DC.B       0x32                     ; '2'
+  0x20000AE0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AE1:  00           DC.B       0x00                     ; '\0'
+  0x20000AE2:  00           DC.B       0x00                     ; '\0'
+  0x20000AE3:  60           DC.B       0x60                     ; '`'
+  0x20000AE4:  00           DC.B       0x00                     ; '\0'
+  0x20000AE5:  00           DC.B       0x00                     ; '\0'
+  0x20000AE6:  00           DC.B       0x00                     ; '\0'
+  0x20000AE7:  00           DC.B       0x00                     ; '\0'
+  0x20000AE8:  00           DC.B       0x00                     ; '\0'
+  0x20000AE9:  00           DC.B       0x00                     ; '\0'
+  0x20000AEA:  00           DC.B       0x00                     ; '\0'
+  0x20000AEB:  00           DC.B       0x00                     ; '\0'
+  0x20000AEC:  00           DC.B       0x00                     ; '\0'
+  0x20000AED:  30           DC.B       0x30                     ; '0'
+  0x20000AEE:  00           DC.B       0x00                     ; '\0'
+  0x20000AEF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AF0:  00           DC.B       0x00                     ; '\0'
+  0x20000AF1:  00           DC.B       0x00                     ; '\0'
+  0x20000AF2:  00           DC.B       0x00                     ; '\0'
+  0x20000AF3:  00           DC.B       0x00                     ; '\0'
+  0x20000AF4:  00           DC.B       0x00                     ; '\0'
+  0x20000AF5:  00           DC.B       0x00                     ; '\0'
+  0x20000AF6:  00           DC.B       0x00                     ; '\0'
+  0x20000AF7:  00           DC.B       0x00                     ; '\0'
+  0x20000AF8:  00           DC.B       0x00                     ; '\0'
+  0x20000AF9:  00           DC.B       0x00                     ; '\0'
+  0x20000AFA:  00           DC.B       0x00                     ; '\0'
+  0x20000AFB:  00           DC.B       0x00                     ; '\0'
+  0x20000AFC:  00           DC.B       0x00                     ; '\0'
+  0x20000AFD:  32           DC.B       0x32                     ; '2'
+  0x20000AFE:  00           DC.B       0x00                     ; '\0'
+  0x20000AFF:  32           DC.B       0x32                     ; '2'
+  0x20000B00:  06           DC.B       0x06                     ; '\x06'
+  0x20000B01:  00           DC.B       0x00                     ; '\0'
+  0x20000B02:  00           DC.B       0x00                     ; '\0'
+  0x20000B03:  60           DC.B       0x60                     ; '`'
+  0x20000B04:  00           DC.B       0x00                     ; '\0'
+  0x20000B05:  00           DC.B       0x00                     ; '\0'
+  0x20000B06:  00           DC.B       0x00                     ; '\0'
+  0x20000B07:  00           DC.B       0x00                     ; '\0'
+  0x20000B08:  00           DC.B       0x00                     ; '\0'
+  0x20000B09:  00           DC.B       0x00                     ; '\0'
+  0x20000B0A:  00           DC.B       0x00                     ; '\0'
+  0x20000B0B:  00           DC.B       0x00                     ; '\0'
+  0x20000B0C:  00           DC.B       0x00                     ; '\0'
+  0x20000B0D:  32           DC.B       0x32                     ; '2'
+  0x20000B0E:  00           DC.B       0x00                     ; '\0'
+  0x20000B0F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B10:  00           DC.B       0x00                     ; '\0'
+  0x20000B11:  00           DC.B       0x00                     ; '\0'
+  0x20000B12:  00           DC.B       0x00                     ; '\0'
+  0x20000B13:  00           DC.B       0x00                     ; '\0'
+  0x20000B14:  00           DC.B       0x00                     ; '\0'
+  0x20000B15:  00           DC.B       0x00                     ; '\0'
+  0x20000B16:  00           DC.B       0x00                     ; '\0'
+  0x20000B17:  00           DC.B       0x00                     ; '\0'
+  0x20000B18:  00           DC.B       0x00                     ; '\0'
+  0x20000B19:  00           DC.B       0x00                     ; '\0'
+  0x20000B1A:  00           DC.B       0x00                     ; '\0'
+  0x20000B1B:  00           DC.B       0x00                     ; '\0'
+  0x20000B1C:  00           DC.B       0x00                     ; '\0'
+  0x20000B1D:  34           DC.B       0x34                     ; '4'
+  0x20000B1E:  00           DC.B       0x00                     ; '\0'
+  0x20000B1F:  32           DC.B       0x32                     ; '2'
+  0x20000B20:  06           DC.B       0x06                     ; '\x06'
+  0x20000B21:  00           DC.B       0x00                     ; '\0'
+  0x20000B22:  00           DC.B       0x00                     ; '\0'
+  0x20000B23:  50           DC.B       0x50                     ; 'P'
+  0x20000B24:  00           DC.B       0x00                     ; '\0'
+  0x20000B25:  00           DC.B       0x00                     ; '\0'
+  0x20000B26:  00           DC.B       0x00                     ; '\0'
+  0x20000B27:  00           DC.B       0x00                     ; '\0'
+  0x20000B28:  00           DC.B       0x00                     ; '\0'
+  0x20000B29:  00           DC.B       0x00                     ; '\0'
+  0x20000B2A:  00           DC.B       0x00                     ; '\0'
+  0x20000B2B:  00           DC.B       0x00                     ; '\0'
+  0x20000B2C:  00           DC.B       0x00                     ; '\0'
+  0x20000B2D:  34           DC.B       0x34                     ; '4'
+  0x20000B2E:  00           DC.B       0x00                     ; '\0'
+  0x20000B2F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B30:  00           DC.B       0x00                     ; '\0'
+  0x20000B31:  00           DC.B       0x00                     ; '\0'
+  0x20000B32:  00           DC.B       0x00                     ; '\0'
+  0x20000B33:  00           DC.B       0x00                     ; '\0'
+  0x20000B34:  00           DC.B       0x00                     ; '\0'
+  0x20000B35:  00           DC.B       0x00                     ; '\0'
+  0x20000B36:  00           DC.B       0x00                     ; '\0'
+  0x20000B37:  00           DC.B       0x00                     ; '\0'
+  0x20000B38:  00           DC.B       0x00                     ; '\0'
+  0x20000B39:  00           DC.B       0x00                     ; '\0'
+  0x20000B3A:  00           DC.B       0x00                     ; '\0'
+  0x20000B3B:  00           DC.B       0x00                     ; '\0'
+  0x20000B3C:  00           DC.B       0x00                     ; '\0'
+  0x20000B3D:  36           DC.B       0x36                     ; '6'
+  0x20000B3E:  00           DC.B       0x00                     ; '\0'
+  0x20000B3F:  32           DC.B       0x32                     ; '2'
+  0x20000B40:  06           DC.B       0x06                     ; '\x06'
+  0x20000B41:  00           DC.B       0x00                     ; '\0'
+  0x20000B42:  00           DC.B       0x00                     ; '\0'
+  0x20000B43:  50           DC.B       0x50                     ; 'P'
+  0x20000B44:  00           DC.B       0x00                     ; '\0'
+  0x20000B45:  00           DC.B       0x00                     ; '\0'
+  0x20000B46:  00           DC.B       0x00                     ; '\0'
+  0x20000B47:  00           DC.B       0x00                     ; '\0'
+  0x20000B48:  00           DC.B       0x00                     ; '\0'
+  0x20000B49:  00           DC.B       0x00                     ; '\0'
+  0x20000B4A:  00           DC.B       0x00                     ; '\0'
+  0x20000B4B:  00           DC.B       0x00                     ; '\0'
+  0x20000B4C:  00           DC.B       0x00                     ; '\0'
+  0x20000B4D:  36           DC.B       0x36                     ; '6'
+  0x20000B4E:  00           DC.B       0x00                     ; '\0'
+  0x20000B4F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B50:  00           DC.B       0x00                     ; '\0'
+  0x20000B51:  00           DC.B       0x00                     ; '\0'
+  0x20000B52:  00           DC.B       0x00                     ; '\0'
+  0x20000B53:  00           DC.B       0x00                     ; '\0'
+  0x20000B54:  00           DC.B       0x00                     ; '\0'
+  0x20000B55:  00           DC.B       0x00                     ; '\0'
+  0x20000B56:  00           DC.B       0x00                     ; '\0'
+  0x20000B57:  00           DC.B       0x00                     ; '\0'
+  0x20000B58:  00           DC.B       0x00                     ; '\0'
+  0x20000B59:  00           DC.B       0x00                     ; '\0'
+  0x20000B5A:  00           DC.B       0x00                     ; '\0'
+  0x20000B5B:  00           DC.B       0x00                     ; '\0'
+  0x20000B5C:  00           DC.B       0x00                     ; '\0'
+  0x20000B5D:  38           DC.B       0x38                     ; '8'
+  0x20000B5E:  00           DC.B       0x00                     ; '\0'
+  0x20000B5F:  32           DC.B       0x32                     ; '2'
+  0x20000B60:  06           DC.B       0x06                     ; '\x06'
+  0x20000B61:  00           DC.B       0x00                     ; '\0'
+  0x20000B62:  00           DC.B       0x00                     ; '\0'
+  0x20000B63:  34           DC.B       0x34                     ; '4'
+  0x20000B64:  00           DC.B       0x00                     ; '\0'
+  0x20000B65:  00           DC.B       0x00                     ; '\0'
+  0x20000B66:  00           DC.B       0x00                     ; '\0'
+  0x20000B67:  00           DC.B       0x00                     ; '\0'
+  0x20000B68:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc._acDownBuffer from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=16, align=1

+
+
_acDownBuffer:
+  0x20000B69:  00           DC.B       0x00                     ; '\0'
+  0x20000B6A:  53           DC.B       0x53                     ; 'S'
+  0x20000B6B:  45           DC.B       0x45                     ; 'E'
+  0x20000B6C:  47           DC.B       0x47                     ; 'G'
+  0x20000B6D:  47           DC.B       0x47                     ; 'G'
+  0x20000B6E:  45           DC.B       0x45                     ; 'E'
+  0x20000B6F:  52           DC.B       0x52                     ; 'R'
+  0x20000B70:  20           DC.B       0x20                     ; ' '
+  0x20000B71:  43           DC.B       0x43                     ; 'C'
+  0x20000B72:  2F           DC.B       0x2F                     ; '/'
+  0x20000B73:  43           DC.B       0x43                     ; 'C'
+  0x20000B74:  2B           DC.B       0x2B                     ; '+'
+  0x20000B75:  2B           DC.B       0x2B                     ; '+'
+  0x20000B76:  20           DC.B       0x20                     ; ' '
+  0x20000B77:  63           DC.B       0x63                     ; 'c'
+  0x20000B78:  6F           DC.B       0x6F                     ; 'o'
+
+

Section .no_init from PowerPro_lto.o, size=1, align=4

+
+
bootLoaderMark:
+  0x20000B7C:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.libc.__SEGGER_RTL_global_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=20, align=4

+
+
__SEGGER_RTL_global_locale:
+__RAL_global_locale:
+  0x20000B80:  080056E8     DC.W       __SEGGER_RTL_c_locale
+  0x20000B84:  080056E8     DC.W       __SEGGER_RTL_c_locale
+  0x20000B88:  080056E8     DC.W       __SEGGER_RTL_c_locale
+  0x20000B8C:  080056E8     DC.W       __SEGGER_RTL_c_locale
+  0x20000B90:  080056E8     DC.W       __SEGGER_RTL_c_locale
+
+

Section .data.uwTickPrio from PowerPro_lto.o, size=4, align=4

+
+
uwTickPrio:
+  0x20000B94:  04           DC.B       0x04                     ; '\x04'
+  0x20000B95:  00           DC.B       0x00                     ; '\0'
+  0x20000B96:  00           DC.B       0x00                     ; '\0'
+  0x20000B97:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.libc.stdout from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stdout:
+  0x20000B98:  200006CC     DC.W       __SEGGER_RTL_stdout_file
+
+

Section .data.libc.stdin from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stdin:
+  0x20000B9C:  200006D0     DC.W       __SEGGER_RTL_stdin_file
+
+

Section .data.libc.stderr from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stderr:
+  0x20000BA0:  200006D4     DC.W       __SEGGER_RTL_stderr_file
+
+

Section .data.SystemCoreClock from PowerPro_lto.o, size=4, align=4

+
+
SystemCoreClock:
+  0x20000BA4:  00           DC.B       0x00                     ; '\0'
+  0x20000BA5:  1B           DC.B       0x1B                     ; '\x1B'
+  0x20000BA6:  B7           DC.B       0xB7                     ; '\xB7'
+  0x20000BA7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.block.stack from [ Linker created ], size=2048, align=8

+
+  0x20002800:  00           DC.B       0x00                     ; '\0'
+  0x20002801:  00           DC.B       0x00                     ; '\0'
+  0x20002802:  00           DC.B       0x00                     ; '\0'
+  0x20002803:  00           DC.B       0x00                     ; '\0'
+  0x20002804:  00           DC.B       0x00                     ; '\0'
+  0x20002805:  00           DC.B       0x00                     ; '\0'
+  0x20002806:  00           DC.B       0x00                     ; '\0'
+  0x20002807:  00           DC.B       0x00                     ; '\0'
+  0x20002808:  00           DC.B       0x00                     ; '\0'
+  0x20002809:  00           DC.B       0x00                     ; '\0'
+  0x2000280A:  00           DC.B       0x00                     ; '\0'
+  0x2000280B:  00           DC.B       0x00                     ; '\0'
+  0x2000280C:  00           DC.B       0x00                     ; '\0'
+  0x2000280D:  00           DC.B       0x00                     ; '\0'
+  0x2000280E:  00           DC.B       0x00                     ; '\0'
+  0x2000280F:  00           DC.B       0x00                     ; '\0'
+  0x20002810:  00           DC.B       0x00                     ; '\0'
+  0x20002811:  00           DC.B       0x00                     ; '\0'
+  0x20002812:  00           DC.B       0x00                     ; '\0'
+  0x20002813:  00           DC.B       0x00                     ; '\0'
+  0x20002814:  00           DC.B       0x00                     ; '\0'
+  0x20002815:  00           DC.B       0x00                     ; '\0'
+  0x20002816:  00           DC.B       0x00                     ; '\0'
+  0x20002817:  00           DC.B       0x00                     ; '\0'
+  0x20002818:  00           DC.B       0x00                     ; '\0'
+  0x20002819:  00           DC.B       0x00                     ; '\0'
+  0x2000281A:  00           DC.B       0x00                     ; '\0'
+  0x2000281B:  00           DC.B       0x00                     ; '\0'
+  0x2000281C:  00           DC.B       0x00                     ; '\0'
+  0x2000281D:  00           DC.B       0x00                     ; '\0'
+  0x2000281E:  00           DC.B       0x00                     ; '\0'
+  0x2000281F:  00           DC.B       0x00                     ; '\0'
+  0x20002820:  00           DC.B       0x00                     ; '\0'
+  0x20002821:  00           DC.B       0x00                     ; '\0'
+  0x20002822:  00           DC.B       0x00                     ; '\0'
+  0x20002823:  00           DC.B       0x00                     ; '\0'
+  0x20002824:  00           DC.B       0x00                     ; '\0'
+  0x20002825:  00           DC.B       0x00                     ; '\0'
+  0x20002826:  00           DC.B       0x00                     ; '\0'
+  0x20002827:  00           DC.B       0x00                     ; '\0'
+  0x20002828:  00           DC.B       0x00                     ; '\0'
+  0x20002829:  00           DC.B       0x00                     ; '\0'
+  0x2000282A:  00           DC.B       0x00                     ; '\0'
+  0x2000282B:  00           DC.B       0x00                     ; '\0'
+  0x2000282C:  00           DC.B       0x00                     ; '\0'
+  0x2000282D:  00           DC.B       0x00                     ; '\0'
+  0x2000282E:  00           DC.B       0x00                     ; '\0'
+  0x2000282F:  00           DC.B       0x00                     ; '\0'
+  0x20002830:  00           DC.B       0x00                     ; '\0'
+  0x20002831:  00           DC.B       0x00                     ; '\0'
+  0x20002832:  00           DC.B       0x00                     ; '\0'
+  0x20002833:  00           DC.B       0x00                     ; '\0'
+  0x20002834:  00           DC.B       0x00                     ; '\0'
+  0x20002835:  00           DC.B       0x00                     ; '\0'
+  0x20002836:  00           DC.B       0x00                     ; '\0'
+  0x20002837:  00           DC.B       0x00                     ; '\0'
+  0x20002838:  00           DC.B       0x00                     ; '\0'
+  0x20002839:  00           DC.B       0x00                     ; '\0'
+  0x2000283A:  00           DC.B       0x00                     ; '\0'
+  0x2000283B:  00           DC.B       0x00                     ; '\0'
+  0x2000283C:  00           DC.B       0x00                     ; '\0'
+  0x2000283D:  00           DC.B       0x00                     ; '\0'
+  0x2000283E:  00           DC.B       0x00                     ; '\0'
+  0x2000283F:  00           DC.B       0x00                     ; '\0'
+  0x20002840:  00           DC.B       0x00                     ; '\0'
+  0x20002841:  00           DC.B       0x00                     ; '\0'
+  0x20002842:  00           DC.B       0x00                     ; '\0'
+  0x20002843:  00           DC.B       0x00                     ; '\0'
+  0x20002844:  00           DC.B       0x00                     ; '\0'
+  0x20002845:  00           DC.B       0x00                     ; '\0'
+  0x20002846:  00           DC.B       0x00                     ; '\0'
+  0x20002847:  00           DC.B       0x00                     ; '\0'
+  0x20002848:  00           DC.B       0x00                     ; '\0'
+  0x20002849:  00           DC.B       0x00                     ; '\0'
+  0x2000284A:  00           DC.B       0x00                     ; '\0'
+  0x2000284B:  00           DC.B       0x00                     ; '\0'
+  0x2000284C:  00           DC.B       0x00                     ; '\0'
+  0x2000284D:  00           DC.B       0x00                     ; '\0'
+  0x2000284E:  00           DC.B       0x00                     ; '\0'
+  0x2000284F:  00           DC.B       0x00                     ; '\0'
+  0x20002850:  00           DC.B       0x00                     ; '\0'
+  0x20002851:  00           DC.B       0x00                     ; '\0'
+  0x20002852:  00           DC.B       0x00                     ; '\0'
+  0x20002853:  00           DC.B       0x00                     ; '\0'
+  0x20002854:  00           DC.B       0x00                     ; '\0'
+  0x20002855:  00           DC.B       0x00                     ; '\0'
+  0x20002856:  00           DC.B       0x00                     ; '\0'
+  0x20002857:  00           DC.B       0x00                     ; '\0'
+  0x20002858:  00           DC.B       0x00                     ; '\0'
+  0x20002859:  00           DC.B       0x00                     ; '\0'
+  0x2000285A:  00           DC.B       0x00                     ; '\0'
+  0x2000285B:  00           DC.B       0x00                     ; '\0'
+  0x2000285C:  00           DC.B       0x00                     ; '\0'
+  0x2000285D:  00           DC.B       0x00                     ; '\0'
+  0x2000285E:  00           DC.B       0x00                     ; '\0'
+  0x2000285F:  00           DC.B       0x00                     ; '\0'
+  0x20002860:  00           DC.B       0x00                     ; '\0'
+  0x20002861:  00           DC.B       0x00                     ; '\0'
+  0x20002862:  00           DC.B       0x00                     ; '\0'
+  0x20002863:  00           DC.B       0x00                     ; '\0'
+  0x20002864:  00           DC.B       0x00                     ; '\0'
+  0x20002865:  00           DC.B       0x00                     ; '\0'
+  0x20002866:  00           DC.B       0x00                     ; '\0'
+  0x20002867:  00           DC.B       0x00                     ; '\0'
+  0x20002868:  00           DC.B       0x00                     ; '\0'
+  0x20002869:  00           DC.B       0x00                     ; '\0'
+  0x2000286A:  00           DC.B       0x00                     ; '\0'
+  0x2000286B:  00           DC.B       0x00                     ; '\0'
+  0x2000286C:  00           DC.B       0x00                     ; '\0'
+  0x2000286D:  00           DC.B       0x00                     ; '\0'
+  0x2000286E:  00           DC.B       0x00                     ; '\0'
+  0x2000286F:  00           DC.B       0x00                     ; '\0'
+  0x20002870:  00           DC.B       0x00                     ; '\0'
+  0x20002871:  00           DC.B       0x00                     ; '\0'
+  0x20002872:  00           DC.B       0x00                     ; '\0'
+  0x20002873:  00           DC.B       0x00                     ; '\0'
+  0x20002874:  00           DC.B       0x00                     ; '\0'
+  0x20002875:  00           DC.B       0x00                     ; '\0'
+  0x20002876:  00           DC.B       0x00                     ; '\0'
+  0x20002877:  00           DC.B       0x00                     ; '\0'
+  0x20002878:  00           DC.B       0x00                     ; '\0'
+  0x20002879:  00           DC.B       0x00                     ; '\0'
+  0x2000287A:  00           DC.B       0x00                     ; '\0'
+  0x2000287B:  00           DC.B       0x00                     ; '\0'
+  0x2000287C:  00           DC.B       0x00                     ; '\0'
+  0x2000287D:  00           DC.B       0x00                     ; '\0'
+  0x2000287E:  00           DC.B       0x00                     ; '\0'
+  0x2000287F:  00           DC.B       0x00                     ; '\0'
+  0x20002880:  00           DC.B       0x00                     ; '\0'
+  0x20002881:  00           DC.B       0x00                     ; '\0'
+  0x20002882:  00           DC.B       0x00                     ; '\0'
+  0x20002883:  00           DC.B       0x00                     ; '\0'
+  0x20002884:  00           DC.B       0x00                     ; '\0'
+  0x20002885:  00           DC.B       0x00                     ; '\0'
+  0x20002886:  00           DC.B       0x00                     ; '\0'
+  0x20002887:  00           DC.B       0x00                     ; '\0'
+  0x20002888:  00           DC.B       0x00                     ; '\0'
+  0x20002889:  00           DC.B       0x00                     ; '\0'
+  0x2000288A:  00           DC.B       0x00                     ; '\0'
+  0x2000288B:  00           DC.B       0x00                     ; '\0'
+  0x2000288C:  00           DC.B       0x00                     ; '\0'
+  0x2000288D:  00           DC.B       0x00                     ; '\0'
+  0x2000288E:  00           DC.B       0x00                     ; '\0'
+  0x2000288F:  00           DC.B       0x00                     ; '\0'
+  0x20002890:  00           DC.B       0x00                     ; '\0'
+  0x20002891:  00           DC.B       0x00                     ; '\0'
+  0x20002892:  00           DC.B       0x00                     ; '\0'
+  0x20002893:  00           DC.B       0x00                     ; '\0'
+  0x20002894:  00           DC.B       0x00                     ; '\0'
+  0x20002895:  00           DC.B       0x00                     ; '\0'
+  0x20002896:  00           DC.B       0x00                     ; '\0'
+  0x20002897:  00           DC.B       0x00                     ; '\0'
+  0x20002898:  00           DC.B       0x00                     ; '\0'
+  0x20002899:  00           DC.B       0x00                     ; '\0'
+  0x2000289A:  00           DC.B       0x00                     ; '\0'
+  0x2000289B:  00           DC.B       0x00                     ; '\0'
+  0x2000289C:  00           DC.B       0x00                     ; '\0'
+  0x2000289D:  00           DC.B       0x00                     ; '\0'
+  0x2000289E:  00           DC.B       0x00                     ; '\0'
+  0x2000289F:  00           DC.B       0x00                     ; '\0'
+  0x200028A0:  00           DC.B       0x00                     ; '\0'
+  0x200028A1:  00           DC.B       0x00                     ; '\0'
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+  0x20002FF6:  00           DC.B       0x00                     ; '\0'
+  0x20002FF7:  00           DC.B       0x00                     ; '\0'
+  0x20002FF8:  00           DC.B       0x00                     ; '\0'
+  0x20002FF9:  00           DC.B       0x00                     ; '\0'
+  0x20002FFA:  00           DC.B       0x00                     ; '\0'
+  0x20002FFB:  00           DC.B       0x00                     ; '\0'
+  0x20002FFC:  00           DC.B       0x00                     ; '\0'
+  0x20002FFD:  00           DC.B       0x00                     ; '\0'
+  0x20002FFE:  00           DC.B       0x00                     ; '\0'
+  0x20002FFF:  00           DC.B       0x00                     ; '\0'
+
+

LINK SUMMARY

+ +
+ 24 720 bytes read-only  code    + 
+  2 625 bytes read-only  data    =  27 345 bytes read-only (total)
+  4 992 bytes read-write data
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSizeUsedUnusedAlignment Loss
FLASH08000000-080077FF30 72027 349 89.03%3 371 10.97%0 0.00%
RAM20000000-20002FFF12 2884 992 40.62%7 260 59.08%36 0.29%
+ +
+Link complete: 0 error.
+
+ Index: /trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1369 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49 + Copyright (c) 2017-2025 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 19 548 1 659 8 1 466 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 216 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 19 792 1 659 8 1 466 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_balanced.a 2 812 32 + mbops_timeops_v6m_t_le_eabi_balanced.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 478 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 74 + strops_v6m_t_le_eabi_balanced.a 142 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 3 696 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 208 2 048 + ============================================= ========== ========== ========== ========== + Total: 23 488 2 466 40 4 738 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 960 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 146 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 992 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 348 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 412 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 34 + strops.o (strops_v6m_t_le_eabi_balanced.a) 108 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (11 members from 5 archives) 3 696 599 32 1 224 + Objects (4 files) 19 792 1 659 8 1 466 + Linker created (shared data, fills, blocks): 208 2 048 + ============================================= ========== ========== ========== ========== + Total: 23 488 2 466 40 4 738 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 208 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 208 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 19 792 1 659 8 1 466 + Archives (5 files) 3 696 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 23 488 2 466 40 4 738 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000B3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000B4-080000C3 SysTick_Handler 16 4 Code RX PowerPro_lto.o + 080000C4-080000D3 DMA1_Channel1_IRQHandler 16 4 Code RX PowerPro_lto.o + 080000D4-080000EB DMA1_Channel2_3_IRQHandler + 24 4 Code RX PowerPro_lto.o + 080000EC-08000293 TIM16_IRQHandler 424 4 Code RX PowerPro_lto.o + 08000294-080002CB HAL_TIM_IC_CaptureCallback + 56 4 Code RX PowerPro_lto.o + 080002CC-080002DB SystemInit 16 4 Code RX PowerPro_lto.o + 080002DC-0800032B SystemCoreClockUpdate 80 4 Code RX PowerPro_lto.o + 0800032C-0800038B HAL_InitTick 96 4 Code RX PowerPro_lto.o + 0800038C-080005E7 HAL_ADC_ConfigChannel 604 4 Code RX PowerPro_lto.o + 080005E8-080006CB HAL_DMA_Init 228 4 Code RX PowerPro_lto.o + 080006CC-0800078B HAL_DMA_Start_IT 192 4 Code RX PowerPro_lto.o + 0800078C-08000867 HAL_DMA_IRQHandler 220 4 Code RX PowerPro_lto.o + 08000868-080009EF HAL_GPIO_Init 392 4 Code RX PowerPro_lto.o + 080009F0-08000A43 HAL_RCC_GetSysClockFreq 84 4 Code RX PowerPro_lto.o + 08000A44-08000A83 HAL_RCC_GetPCLK1Freq 64 4 Code RX PowerPro_lto.o + 08000A84-08000B8F HAL_RCCEx_PeriphCLKConfig 268 4 Code RX PowerPro_lto.o + 08000B90-08000C5B HAL_TIM_Base_Init 204 4 Code RX PowerPro_lto.o + 08000C5C-08000CF3 TIM_Base_SetConfig 152 4 Code RX PowerPro_lto.o + 08000CF4-08000D67 UART_WaitOnFlagUntilTimeout + 116 4 Code RX PowerPro_lto.o + 08000D68-08000DC7 UART_EndRxTransfer 96 4 Code RX PowerPro_lto.o + 08000DC8-08000E17 UART_DMATransmitCplt 80 4 Code RX PowerPro_lto.o + 08000E18-08000F2F UART_DMAError 280 4 Code RX PowerPro_lto.o + 08000F30-08001027 HAL_UART_Receive_DMA 248 4 Code RX PowerPro_lto.o + 08001028-08004097 main 12 400 4 Code RX PowerPro_lto.o + 08004098-0800471B MODE_SECONDARYPROTECTION_Exec + 1 668 4 Code RX PowerPro_lto.o + 0800471C-08004B87 MODE_SECONDARYPROTECTION_PLUS_Exec + 1 132 4 Code RX PowerPro_lto.o + 08004B88-08004BC3 mbCrc16 60 4 Code RX PowerPro_lto.o + 08004BC4-08004C03 AHBPrescTable 64 4 Cnst RO PowerPro_lto.o + 08004C04-08004C23 APBPrescTable 32 4 Cnst RO PowerPro_lto.o + 08004C24-08004C33 [.rodata..Lswitch.table.UART_SetConfig] + 16 4 Cnst RO PowerPro_lto.o + 08004C34-08004C47 _start 20 4 Code RX SEGGER_THUMB_Startup.o + 08004C48-08004C57 putchar 16 4 Code RX fileops.o (libc_v6m_t_le_eabi_balanced.a) + 08004C58-08004C83 puts 44 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(libc_v6m_t_le_eabi_balanced.a) + 08004F78-08004F9F printf 40 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 08004FA0-0800535F __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code RX __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 08005360-08005393 __SEGGER_RTL_X_file_stat 52 4 Code RX prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 08005394-080053E7 _DoInit 84 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 080053E8-0800544F SEGGER_RTT_WriteNoLock 104 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 08005450-08005487 SEGGER_RTT_Write 56 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 08005488-080054F3 strlen 108 4 Code RX strops.o (strops_v6m_t_le_eabi_balanced.a) + 080054F4-08005507 __aeabi_memclr 20 4 Code RX strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 08005508-0800551B __SEGGER_RTL_current_locale + 20 4 Code RX mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0800551C-08005537 __SEGGER_RTL_ascii_isctype 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(libc_v6m_t_le_eabi_balanced.a) + __aeabi_f2uiz 0x08004D7D 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fmul 0x080055D9 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 0x08004DA1 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv 0x08004DD9 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv0 0x08005711 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 0x080056E1 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 0x080054F5 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr4 0x080054F5 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr8 0x080054F5 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy 0x08005719 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy4 0x08005719 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy8 0x08005719 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset 0x080054F7 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 0x080054F7 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 0x080054F7 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 0x08004DBD 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 0x080056C1 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 0x08004E19 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 0x08004E51 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uldivmod 0x08004E61 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __startup_complete 0x08004C3F 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x08004C35 14 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x08004C43 2 4 Code Gb SEGGER_THUMB_Startup.o + fputc 0x0800574D 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 0x08005BBB 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x08001029 12 400 4 Code Gb PowerPro_lto.o + mbCrc16 0x08004B89 60 4 Code Lc PowerPro_lto.o + memcpy 0x08005719 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + memset 0x080054FD 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + printf 0x08004F79 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + putchar 0x08004C49 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + puts 0x08004C59 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x08005BB3 2 Code Gb STM32C0xx_Startup.o + strlen 0x08005489 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + vfprintf 0x0800599D 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x08004F01 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 SysTick_Handler 16 4 Code Gb PowerPro_lto.o + 0x080000C5 DMA1_Channel1_IRQHandler 16 4 Code Gb PowerPro_lto.o + 0x080000D5 DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + 0x080000ED TIM16_IRQHandler 424 4 Code Gb PowerPro_lto.o + 0x08000295 HAL_TIM_IC_CaptureCallback + 56 4 Code Lc PowerPro_lto.o + 0x080002CD SystemInit 16 4 Code Gb PowerPro_lto.o + 0x080002DD SystemCoreClockUpdate 80 4 Code Gb PowerPro_lto.o + 0x0800032D HAL_InitTick 96 4 Code Lc PowerPro_lto.o + 0x0800038D HAL_ADC_ConfigChannel 604 4 Code Lc PowerPro_lto.o + 0x080005E9 HAL_DMA_Init 228 4 Code Lc PowerPro_lto.o + 0x080006CD HAL_DMA_Start_IT 192 4 Code Lc PowerPro_lto.o + 0x0800078D HAL_DMA_IRQHandler 220 4 Code Lc PowerPro_lto.o + 0x08000869 HAL_GPIO_Init 392 4 Code Lc PowerPro_lto.o + 0x080009F1 HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + 0x08000A45 HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + 0x08000A85 HAL_RCCEx_PeriphCLKConfig 268 4 Code Lc PowerPro_lto.o + 0x08000B91 HAL_TIM_Base_Init 204 4 Code Lc PowerPro_lto.o + 0x08000C5D TIM_Base_SetConfig 152 4 Code Lc PowerPro_lto.o + 0x08000CF5 UART_WaitOnFlagUntilTimeout + 116 4 Code Lc PowerPro_lto.o + 0x08000D69 UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + 0x08000DC9 UART_DMATransmitCplt 80 4 Code Lc PowerPro_lto.o + 0x08000E19 UART_DMAError 280 4 Code Lc PowerPro_lto.o + 0x08000F31 HAL_UART_Receive_DMA 248 4 Code Lc PowerPro_lto.o + 0x08001029 main 12 400 4 Code Gb PowerPro_lto.o + 0x08004099 MODE_SECONDARYPROTECTION_Exec + 1 668 4 Code Lc PowerPro_lto.o + 0x0800471D MODE_SECONDARYPROTECTION_PLUS_Exec + 1 132 4 Code Lc PowerPro_lto.o + 0x08004B89 mbCrc16 60 4 Code Lc PowerPro_lto.o + 0x08004C35 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004C3F __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004C3F __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004C43 exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08004C49 putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004C59 puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004C85 __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D49 __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004D7D __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004DA1 __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004DBD __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004DD9 __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004E19 __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004E51 __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004E61 __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004F01 vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004F79 printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004FA1 __SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004FA1 __SEGGER_RTL_vfprintf 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005361 __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005395 _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080053E9 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005451 SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005489 strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054F5 __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054F5 __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054F5 __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054F7 __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054F7 __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054F7 __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080054FD memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005509 __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x0800551D __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08005539 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080055D9 __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800568F NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005691 __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080056BF HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x080056C1 __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080056DF SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x080056E1 __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800570F PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x08005711 __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005717 ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + 0x08005719 memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005719 __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005719 __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005719 __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x08005727 UART_DMATxHalfCplt 2 2 Code Lc PowerPro_lto.o + 0x08005729 WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800572B RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800572D FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800572F RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005731 EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005733 EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005735 EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005737 DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005739 ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800573B TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x0800573D TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800573F TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005741 TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005743 TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005745 I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005747 SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x08005749 USART1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800574B USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x0800574D fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800576F __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080057A7 __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080058F9 __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08005983 __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800599D vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x080059B7 __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080059C1 _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080059D7 _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08005A11 __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 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__SEGGER_RTL_vfprintf_int_nwp + 960 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + HAL_ADC_ConfigChannel 604 4 Code Lc PowerPro_lto.o + TIM16_IRQHandler 424 4 Code Gb PowerPro_lto.o + __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_GPIO_Init 392 4 Code Lc PowerPro_lto.o + UART_DMAError 280 4 Code Lc PowerPro_lto.o + HAL_RCCEx_PeriphCLKConfig 268 4 Code Lc PowerPro_lto.o + HAL_UART_Receive_DMA 248 4 Code Lc PowerPro_lto.o + HAL_DMA_Init 228 4 Code Lc PowerPro_lto.o + HAL_DMA_IRQHandler 220 4 Code Lc PowerPro_lto.o + HAL_TIM_Base_Init 204 4 Code Lc PowerPro_lto.o + __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_DMA_Start_IT 192 4 Code Lc PowerPro_lto.o + __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + UART_DMAReceiveCplt 164 2 Code Lc PowerPro_lto.o + __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + TIM_Base_SetConfig 152 4 Code Lc PowerPro_lto.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_WaitOnFlagUntilTimeout + 116 4 Code Lc PowerPro_lto.o + strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + ADC_DMAConvCplt 100 2 Code Lc PowerPro_lto.o + HAL_InitTick 96 4 Code Lc PowerPro_lto.o + UART_EndRxTransfer 96 4 Code Lc PowerPro_lto.o + _WriteBlocking 88 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SystemCoreClockUpdate 80 4 Code Gb PowerPro_lto.o + UART_DMATransmitCplt 80 4 Code Lc PowerPro_lto.o + HAL_RCC_GetPCLK1Freq 64 4 Code Lc PowerPro_lto.o + __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbCrc16 60 4 Code Lc PowerPro_lto.o + _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_TIM_IC_CaptureCallback + 56 4 Code Lc PowerPro_lto.o + SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_mbtowc 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_DMARxHalfCplt 36 2 Code Lc PowerPro_lto.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + DMA1_Channel2_3_IRQHandler + 24 4 Code Gb PowerPro_lto.o + _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ADC_DMAError 20 2 Code Lc PowerPro_lto.o + __SEGGER_RTL_current_locale + 20 4 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Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/PowerPro_link.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/PowerPro_link.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/PowerPro_link.ind (revision 41) @@ -0,0 +1,10 @@ +Output/Release_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o +Output/Release_24V/Obj/PowerPro/stm32c031xx_Vectors.o +Output/Release_24V/Obj/PowerPro/STM32C0xx_Startup.o +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a" Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_24V/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_24V/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_24V/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/eeprom.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/eeprom.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/eeprom.d (revision 41) @@ -0,0 +1,49 @@ +Output/Release_24V/Obj/PowerPro/eeprom.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\eeprom.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\string.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_24V/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,70 @@ +Output/Release_24V/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/modbus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/modbus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/modbus.d (revision 41) @@ -0,0 +1,48 @@ +Output/Release_24V/Obj/PowerPro/modbus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modbus.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_24V/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_24V/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_24V/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_24V/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,53 @@ +Output/Release_24V/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,53 @@ +Output/Release_24V/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_24V/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_24V/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_24V/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release_24V/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/sysdata.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/sysdata.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/sysdata.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release_24V/Obj/PowerPro/sysdata.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\sysdata.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Release_24V/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_24V/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_24V/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_24V/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,49 @@ +Output/Release_24V/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.htm =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.htm (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.htm (revision 41) @@ -0,0 +1,37742 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ +
+SEGGER ARM Linker 4.44c compiled Feb 13 2026 18:40:49
+Copyright (c) 2017-2025 SEGGER Microcontroller GmbH    www.segger.com
+
+ +
+--add-region:FLASH1=0x00007800@0x08000000
+--add-region:RAM1=0x00003000@0x20000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Release_48V/Exe/PowerPro.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=6-M
+--silent
+-TD:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf
+--defsym=__STACKSIZE__=2048
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=1024
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_int_nwp
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.elf
+D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/PowerPro_lto.o
+Output/Release_48V/Obj/PowerPro/SEGGER_THUMB_Startup.o
+Output/Release_48V/Obj/PowerPro/stm32c031xx_Vectors.o
+Output/Release_48V/Obj/PowerPro/STM32C0xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf'

+
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32C0xx_Flash.icf
+Purpose : STM32C0xx linker script for application placement in Flash,
+          for use with the SEGGER Linker.
+Maps    : STM32C011D6Yx, STM32C011F4Px, STM32C011F4Ux, STM32C011F6Px, 
+          STM32C011F6Ux, STM32C011J4Mx, STM32C011J6Mx, STM32C031C4Tx, 
+          STM32C031C4Ux, STM32C031C6Tx, STM32C031C6Ux, STM32C031F4Px, 
+          STM32C031F6Px, STM32C031G4Ux, STM32C031G6Ux, STM32C031K4Tx, 
+          STM32C031K4Ux, STM32C031K6Tx, STM32C031K6Ux
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM   = RAM1;
+
+//
+// Block definitions
+//
+define block vectors                        { section .vectors };                                   // Vector table section
+define block vectors_ram                    { section .vectors_ram };                               // Vector table section
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { block vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1                             { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { block vectors };                                      // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1                               { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM                       { block vectors_ram };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x08000000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x08000000180256stm32c031xx_Vectors.o
+

place at 0x20003000

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#5> at line 111, col 45": place in [0x08000000 to 0x080077ff] with maximum packing

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UARTEx_SetNbDataToProcess.denominatorCnst0x0800687081PowerPro_lto.o
[.rodata..Lstr.3]Cnst0x08006878281PowerPro_lto.o
[.rodata..Lstr.11]Cnst0x08006894201PowerPro_lto.o
[.rodata..Lstr.13]Cnst0x080068A8161PowerPro_lto.o
[.rodata..L.str.2]Cnst0x080068B8161PowerPro_lto.o
[.rodata..L.str.3]Cnst0x080068C8161PowerPro_lto.o
[.rodata..L.str.4]Cnst0x080068D8161PowerPro_lto.o
[.rodata..Lstr.19]Cnst0x080068E881PowerPro_lto.o
[.rodata..Lstr.17.129]Cnst0x080068F0161PowerPro_lto.o
[.rodata..Lstr.19.131]Cnst0x08006900161PowerPro_lto.o
[.rodata..Lstr.8.136]Cnst0x08006910281PowerPro_lto.o
[.rodata..Lstr.12.138]Cnst0x0800692C321PowerPro_lto.o
[.rodata..Lstr.19.154]Cnst0x0800694C81PowerPro_lto.o
[.rodata..Lstr.11.179]Cnst0x08006954601PowerPro_lto.o
[.rodata..Lstr.14.174]Cnst0x08006990281PowerPro_lto.o
__SEGGER_RTL_hex_ucCnst0x080069AC161prinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_hex_lcCnst0x080069BC161prinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_ctype_mapCnst0x080069CC1281mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_init_ctorsCode0x08006A4C364SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_table__Cnst0x08006A701804[ Linker created ]
__SEGGER_init_data__Cnst0x08006B24404[ Linker created ]
__SEGGER_init_zeroCode0x08006B4C182SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__SEGGER_init_copyCode0x08006B5E202SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
+

"<#6> at line 122, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
modbusDataZero0x200000005644PowerPro_lto.o
+

"<#9> at line 128, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
sys_dataZero0x200002342244PowerPro_lto.o
_SEGGER_RTTZero0x200003141684SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
huart1Zero0x200003BC1484PowerPro_lto.o
hadc1Zero0x200004501004PowerPro_lto.o
hdma_usart1_txZero0x200004B4924PowerPro_lto.o
hdma_usart1_rxZero0x20000510924PowerPro_lto.o
hdma_adc1Zero0x2000056C924PowerPro_lto.o
htim17Zero0x200005C8764PowerPro_lto.o
htim16Zero0x20000614764PowerPro_lto.o
adcDataZero0x20000660204PowerPro_lto.o
flash_device_parameter_defaultZero0x20000674164PowerPro_lto.o
voltageUoutZero0x2000068444PowerPro_lto.o
voltageUinZero0x2000068844PowerPro_lto.o
uwTickZero0x2000068C44PowerPro_lto.o
tempZero0x2000069044PowerPro_lto.o
relais_temperatureZero0x2000069444PowerPro_lto.o
onTimeCounterSETZero0x2000069844PowerPro_lto.o
onTimeCounterRTZero0x2000069C44PowerPro_lto.o
onTimeCounterRESETZero0x200006A044PowerPro_lto.o
onTimeCounterGNZero0x200006A444PowerPro_lto.o
onTimeCounterZero0x200006A844PowerPro_lto.o
oldTimeMSTickZero0x200006AC44PowerPro_lto.o
offTimeCounterRTZero0x200006B044PowerPro_lto.o
offTimeCounterGNZero0x200006B444PowerPro_lto.o
offTimeCounterZero0x200006B844PowerPro_lto.o
numberOfBlinksZero0x200006BC44PowerPro_lto.o
msCounterZero0x200006C044PowerPro_lto.o
longPressCounterButtonOnZero0x200006C444PowerPro_lto.o
longPressCounterButtonOffZero0x200006C844PowerPro_lto.o
__SEGGER_RTL_stdout_fileZero0x200006CC44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_fileZero0x200006D044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_fileZero0x200006D444prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_locale_ptrZero0x200006D844mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
ic_overflowsZero0x200006DC44PowerPro_lto.o
frequencyZero0x200006E044PowerPro_lto.o
dropLimitCounterZero0x200006E444PowerPro_lto.o
calTemperatureSensor30ValueZero0x200006E844PowerPro_lto.o
blinkCounterZero0x200006EC44PowerPro_lto.o
autoRetryMode.170Zero0x200006F044PowerPro_lto.o
autoRetryModeZero0x200006F444PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.175Zero0x200006F844PowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtimeZero0x200006FC44PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176Zero0x2000070044PowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounterZero0x2000070444PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.181Zero0x2000070844PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counterZero0x2000070C44PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182Zero0x2000071044PowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTickZero0x2000071444PowerPro_lto.o
OVP_SM_On.ovpTimeCounterZero0x2000071844PowerPro_lto.o
OVP_SM_On.oldtimeZero0x2000071C44PowerPro_lto.o
LVP_SM_On.oldtimeZero0x2000072044PowerPro_lto.o
LVP_SM_On.lvpTimeCounterZero0x2000072444PowerPro_lto.o
LVP_OVP_SM_On.oldtimeZero0x2000072844PowerPro_lto.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounterZero0x2000072C44PowerPro_lto.o
relaisStateZero0x2000073014PowerPro_lto.o
smState.171Zero0x2000073111PowerPro_lto.o
smState.160Zero0x2000073211PowerPro_lto.o
smState.145Zero0x2000073311PowerPro_lto.o
pauseTimeZero0x2000073414PowerPro_lto.o
smState.137Zero0x2000073511PowerPro_lto.o
smState.122Zero0x2000073611PowerPro_lto.o
smStateZero0x2000073711PowerPro_lto.o
pFlash.0Zero0x2000073814PowerPro_lto.o
modeZero0x2000073911PowerPro_lto.o
buttonStateZero0x2000073A11PowerPro_lto.o
onTimeRTZero0x2000073C14PowerPro_lto.o
onTimeGNZero0x2000074014PowerPro_lto.o
[.bss.block.heap]None0x200007408[ Linker created ]
onTimeZero0x2000074414PowerPro_lto.o
offTimeRTZero0x2000074814PowerPro_lto.o
offTimeGNZero0x2000074C14PowerPro_lto.o
offTimeZero0x2000075014PowerPro_lto.o
blinkModeRTZero0x2000075414PowerPro_lto.o
blinkModeGNZero0x2000075814PowerPro_lto.o
alarmModeZero0x2000075C14PowerPro_lto.o
OVP_SM_On.ovpInputZero0x2000076014PowerPro_lto.o
LVP_SM_On.lvpInputZero0x2000076414PowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInputZero0x2000076814PowerPro_lto.o
_acUpBufferZero0x200007691 0241SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBufferZero0x20000B69161SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
bootLoaderMarkNone0x20000B7C14PowerPro_lto.o
__SEGGER_RTL_global_localeInit0x20000B80204mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
uwTickPrioInit0x20000B9444PowerPro_lto.o
stdoutInit0x20000B9844prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdinInit0x20000B9C44prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stderrInit0x20000BA044prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
SystemCoreClockInit0x20000BA444PowerPro_lto.o
[.bss.block.stack]None0x200028002 0488[ Linker created ]
+

"<#10> at line 132, col 45": place in [0x20000000 to 0x20002fff] with auto order

+ + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x200007408[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
PowerPro_lto.o21 1501 80681 680
SEGGER_THUMB_Startup.o20
stm32c031xx_Vectors.o214
STM32C0xx_Startup.o8
Subtotal (4 objects)21 3921 80681 680
libc_v6m_t_le_eabi_small.a2 65632
mbops_timeops_v6m_t_le_eabi_small.a190541204
prinops_rtt_v6m_t_le_eabi_small.a47026121 220
SEGGER_crtinit_v6m_t_le_eabi_small.a74
strops_v6m_t_le_eabi_small.a94
Subtotal (5 archives)3 484599321 224
Linker created (shared data, fills, blocks):2202 048
Total:24 8762 625404 952
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)840
fileops.o (libc_v6m_t_le_eabi_small.a)144
floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)992
intasmops_arm.o (libc_v6m_t_le_eabi_small.a)308
mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)190541204
prinops.o (libc_v6m_t_le_eabi_small.a)37232
prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)581212
SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)74
SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)412261 208
strasmops_arm.o (strops_v6m_t_le_eabi_small.a)34
strops.o (strops_v6m_t_le_eabi_small.a)60
Subtotal (11 members from 5 archives)3 484599321 224
Objects (4 files)21 3921 80681 680
Linker created (shared data, fills, blocks):2202 048
Total:24 8762 625404 952
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table220
Memory for block 'stack'2 048
Subtotal (linker created):2202 048
Objects (4 files)21 3921 80681 680
Archives (5 files)3 484599321 224
Total:24 8762 625404 952
+

MODULE DETAIL

+

Module PowerPro_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
main11 536
MODE_SECONDARYPROTECTION_Exec1 660
MODE_SECONDARYPROTECTION_PLUS_Exec1 108
HAL_UART_Init972
USART1_IRQHandler944
HAL_ADC_ConfigChannel608
HAL_GPIO_Init380
TIM16_IRQHandler288
EEPROM_Write280
HAL_RCCEx_PeriphCLKConfig268
HAL_UART_Receive_DMA248
HAL_DMA_Init224
HAL_TIM_Base_Init204
HAL_DMA_Start_IT196
UART_DMAReceiveCplt168
HAL_UART_ErrorCallback168
HAL_DMA_IRQHandler164
TIM_Base_SetConfig144
UART_DMAError138
ADC_DMAConvCplt100
HAL_InitTick96
UART_WaitOnFlagUntilTimeout96
UART_EndRxTransfer96
JumpToBootloader92
HAL_RCC_GetSysClockFreq84
UARTEx_SetNbDataToProcess84
SystemCoreClockUpdate80
FLASH_WaitForLastOperation80
UART_DMATransmitCplt80
HAL_RCC_GetPCLK1Freq64
EEPROM_StoreConfig60
HAL_TIM_IC_CaptureCallback56
mbCrc1656
EEPROM_WriteDefaults48
UART_DMARxHalfCplt36
EEPROM_ReadDeviceParameter36
HAL_FLASH_Unlock32
__NVIC_SystemReset28
DMA1_Channel2_3_IRQHandler24
HAL_Delay20
ADC_DMAError20
SysTick_Handler16
DMA1_Channel1_IRQHandler16
SystemInit16
UART_DMAAbortOnError16
HAL_NVIC_SystemReset4
Error_Handler4
NMI_Handler2
HardFault_Handler2
SVC_Handler2
PendSV_Handler2
ADC_DMAHalfConvCplt2
UART_DMATxHalfCplt2
AHBPrescTable64
[.rodata..Lstr.11.179]60
[.rodata..Lstr.9]59
[.rodata..Lstr.124]53
[.rodata..Lstr.10]46
[.rodata..Lstr.118]45
[.rodata..Lstr.147]45
[.rodata..Lstr.13.180]43
[.rodata..Lstr.22.162]41
[.rodata..L.str.7]39
[.rodata..Lstr.18.130]39
[.rodata..Lstr.12.123]38
[.rodata..Lstr.20.132]38
[.rodata..Lstr.20.155]38
[.rodata..Lstr.15.173]37
[.rodata..Lstr.18]35
[.rodata..Lstr.18.153]35
[.rodata..Lstr.8.177]35
[.rodata..L.str.203]35
[.rodata..Lstr.16.172]34
APBPrescTable32
[.rodata..Lstr.12.138]32
[.rodata..Lstr.12.117]30
[.rodata..Lstr.12.146]30
[.rodata..Lstr.24.125]29
[.rodata..Lstr.9.178]29
[.rodata..Lstr.3]28
[.rodata..Lstr.8.136]28
[.rodata..Lstr.14.174]28
[.rodata..Lstr.10.139]26
[.rodata..Lstr.12]25
[.rodata..Lstr.24]25
[.rodata..Lstr.15.127]25
[.rodata..Lstr.11.135]25
[.rodata..Lstr.24.148]25
UARTPrescTable24
[.rodata..Lstr.22.133]23
[.rodata..Lstr.23.134]22
[.rodata..Lstr.15]21
[.rodata..Lstr.15.150]21
[.rodata..Lstr.11]20
[.rodata..Lstr.99]19
[.rodata..Lstr.22]19
[.rodata..Lstr.22.156]19
[.rodata..Lstr]18
[.rodata..Lstr.8]18
[.rodata..Lstr.23]18
[.rodata..Lstr.23.157]18
[.rodata..Lstr.4]17
[.rodata..Lstr.14]17
[.rodata..L.str.5]17
[.rodata..L.str.6]17
[.rodata..Lstr.104]17
[.rodata..Lswitch.table.UART_SetConfig]16
[.rodata..Lstr.13]16
[.rodata..L.str.2]16
[.rodata..L.str.3]16
[.rodata..L.str.4]16
[.rodata..Lstr.17.129]16
[.rodata..Lstr.19.131]16
[.rodata..L.str.1]14
[.rodata..Lstr.17]9
[.rodata..Lstr.17.152]9
[.rodata..L.str]9
UARTEx_SetNbDataToProcess.numerator8
UARTEx_SetNbDataToProcess.denominator8
[.rodata..Lstr.19]8
[.rodata..Lstr.19.154]8
SystemCoreClock4
uwTickPrio4
modbusData564
sys_data224
huart1148
hadc1100
hdma_adc192
hdma_usart1_rx92
hdma_usart1_tx92
htim1776
htim1676
adcData20
flash_device_parameter_default16
uwTick4
longPressCounterButtonOn4
longPressCounterButtonOff4
onTimeCounter4
offTimeCounter4
calTemperatureSensor30Value4
temp4
onTimeCounterGN4
offTimeCounterGN4
onTimeCounterRT4
offTimeCounterRT4
blinkCounter4
numberOfBlinks4
ic_overflows4
oldTimeMSTick4
msCounter4
frequency4
LVP_SM_On.lvpTimeCounter4
LVP_SM_On.oldtime4
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter4
LVP_OVP_SM_On.oldtime4
OVP_SM_On.ovpTimeCounter4
OVP_SM_On.oldtime4
autoRetryMode4
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter4
SECONDARYPROTECTION_SM_On.oldtime4
SECONDARYPROTECTION_SM_Error.retry_counter4
SECONDARYPROTECTION_SM_Error.oldTimeMSTick4
autoRetryMode.1704
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1764
SECONDARYPROTECTION_SM_On.oldtime.1754
SECONDARYPROTECTION_SM_Error.retry_counter.1814
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.1824
relais_temperature4
onTimeCounterSET4
onTimeCounterRESET4
dropLimitCounter4
voltageUin4
voltageUout4
pFlash.01
buttonState1
alarmMode1
offTime1
onTime1
blinkModeGN1
offTimeGN1
onTimeGN1
blinkModeRT1
offTimeRT1
pauseTime1
onTimeRT1
bootLoaderMark1
smState1
LVP_SM_On.lvpInput1
smState.1221
LVP_OVP_SM_On.lvpOROvpInput1
smState.1371
smState.1451
OVP_SM_On.ovpInput1
smState.1601
smState.1711
mode1
relaisState1
Total:21 1501 80681 680
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32c031xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors180
WWDG_IRQHandler2
RTC_IRQHandler2
FLASH_IRQHandler2
RCC_IRQHandler2
EXTI0_1_IRQHandler2
EXTI2_3_IRQHandler2
EXTI4_15_IRQHandler2
DMAMUX1_IRQHandler2
ADC1_IRQHandler2
TIM1_BRK_UP_TRG_COM_IRQHandler2
TIM1_CC_IRQHandler2
TIM3_IRQHandler2
TIM14_IRQHandler2
TIM17_IRQHandler2
I2C1_IRQHandler2
SPI1_IRQHandler2
USART2_IRQHandler2
Total:214
+

Module STM32C0xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler8
Total:8
+

Module fileops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
fwrite50
puts44
fputc34
putchar16
Total:144
+

Module floatasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_dmul_aux394
__aeabi_ddiv196
__aeabi_fmul182
__aeabi_d2iz52
__aeabi_d2uiz46
__aeabi_f2uiz36
__aeabi_ui2f30
__aeabi_i2d28
__aeabi_ui2d28
Total:992
+

Module intasmops_arm.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_uldivmod136
__aeabi_idiv64
__aeabi_uidiv56
__aeabi_lmul46
__aeabi_idiv06
Total:308
+

Module prinops.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_putc138
vfprintf_l108
printf40
__SEGGER_RTL_prin_flush26
vfprintf26
__SEGGER_RTL_init_prin_l18
__SEGGER_RTL_stream_write16
__SEGGER_RTL_hex_uc16
__SEGGER_RTL_hex_lc16
Total:37232
+

Module __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_vfprintf_int_nwp840
Total:840
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_X_file_stat44
__SEGGER_RTL_X_file_write10
__SEGGER_RTL_X_file_bufsize4
stdin4
stdout4
stderr4
__SEGGER_RTL_stdin_file4
__SEGGER_RTL_stdout_file4
__SEGGER_RTL_stderr_file4
Total:581212
+

Module SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
SEGGER_RTT_WriteNoLock104
_WriteBlocking88
_DoInit84
_WriteNoCheck58
SEGGER_RTT_Write56
_GetAvailWriteSpace22
_DoInit._aInitStr17
[.rodata.libc..L.str]9
_acUpBuffer1 024
_SEGGER_RTT168
_acDownBuffer16
Total:412261 208
+

Module strops.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
memcmp46
strlen14
Total:60
+

Module strasmops_arm.o (strops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr20
memcpy14
Total:34
+

Module mbops.o (mbops_timeops_v6m_t_le_eabi_small.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_RTL_ascii_mbtowc46
__SEGGER_RTL_ascii_isctype28
__SEGGER_RTL_ascii_iswctype28
__SEGGER_RTL_current_locale20
__SEGGER_RTL_ascii_wctomb16
__SEGGER_RTL_ascii_tolower14
__SEGGER_RTL_ascii_towlower14
__SEGGER_RTL_ascii_toupper12
__SEGGER_RTL_ascii_towupper12
__SEGGER_RTL_ascii_ctype_map128
__SEGGER_RTL_c_locale_data88
__SEGGER_RTL_c_locale_month_names87
__SEGGER_RTL_c_locale_day_names58
__SEGGER_RTL_c_locale_abbrev_month_names49
__SEGGER_RTL_codeset_ascii32
__SEGGER_RTL_c_locale_abbrev_day_names29
__SEGGER_RTL_c_locale_date_time_format15
__SEGGER_RTL_ascii_ctype_mask13
__SEGGER_RTL_c_locale12
__SEGGER_RTL_c_locale_date_format9
__SEGGER_RTL_c_locale_time_format9
__SEGGER_RTL_c_locale_am_pm_indicator7
[.rodata.libc..L.str]2
__SEGGER_RTL_data_utf8_period2
__SEGGER_RTL_data_empty_string1
__SEGGER_RTL_global_locale20
__SEGGER_RTL_locale_ptr4
Total:190541204
+

All modules

+ + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:24 8762 405402 904
+

SECTION DETAIL

+

Sections by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSymbol or [section] NameSizeAlInitAcObject File
08000000-080000B3_vectors180256CodeRXstm32c031xx_Vectors.o
080000B4-080000C3SysTick_Handler164CodeRXPowerPro_lto.o
080000C4-080000D3DMA1_Channel1_IRQHandler164CodeRXPowerPro_lto.o
080000D4-080000EBDMA1_Channel2_3_IRQHandler244CodeRXPowerPro_lto.o
080000EC-0800020BTIM16_IRQHandler2884CodeRXPowerPro_lto.o
0800020C-080005BBUSART1_IRQHandler9444CodeRXPowerPro_lto.o
080005BC-080005F3HAL_TIM_IC_CaptureCallback564CodeRXPowerPro_lto.o
080005F4-08000603SystemInit164CodeRXPowerPro_lto.o
08000604-08000653SystemCoreClockUpdate804CodeRXPowerPro_lto.o
08000654-080006B3HAL_InitTick964CodeRXPowerPro_lto.o
080006B4-080006C7HAL_Delay204CodeRXPowerPro_lto.o
080006C8-08000927HAL_ADC_ConfigChannel6084CodeRXPowerPro_lto.o
08000928-08000943__NVIC_SystemReset284CodeRXPowerPro_lto.o
08000944-08000A23HAL_DMA_Init2244CodeRXPowerPro_lto.o
08000A24-08000AE7HAL_DMA_Start_IT1964CodeRXPowerPro_lto.o
08000AE8-08000B8BHAL_DMA_IRQHandler1644CodeRXPowerPro_lto.o
08000B8C-08000BDBFLASH_WaitForLastOperation804CodeRXPowerPro_lto.o
08000BDC-08000BFBHAL_FLASH_Unlock324CodeRXPowerPro_lto.o
08000BFC-08000D77HAL_GPIO_Init3804CodeRXPowerPro_lto.o
08000D78-08000DCBHAL_RCC_GetSysClockFreq844CodeRXPowerPro_lto.o
08000DCC-08000E0BHAL_RCC_GetPCLK1Freq644CodeRXPowerPro_lto.o
08000E0C-08000F17HAL_RCCEx_PeriphCLKConfig2684CodeRXPowerPro_lto.o
08000F18-08000FE3HAL_TIM_Base_Init2044CodeRXPowerPro_lto.o
08000FE4-08001073TIM_Base_SetConfig1444CodeRXPowerPro_lto.o
08001074-0800143FHAL_UART_Init9724CodeRXPowerPro_lto.o
08001440-0800149FUART_WaitOnFlagUntilTimeout964CodeRXPowerPro_lto.o
080014A0-080014FFUART_EndRxTransfer964CodeRXPowerPro_lto.o
08001500-0800154FUART_DMATransmitCplt804CodeRXPowerPro_lto.o
08001550-08001647HAL_UART_Receive_DMA2484CodeRXPowerPro_lto.o
08001648-0800169BUARTEx_SetNbDataToProcess844CodeRXPowerPro_lto.o
0800169C-080017B3EEPROM_Write2804CodeRXPowerPro_lto.o
080017B4-080017E3EEPROM_WriteDefaults484CodeRXPowerPro_lto.o
080017E4-08001807EEPROM_ReadDeviceParameter364CodeRXPowerPro_lto.o
08001808-08001843EEPROM_StoreConfig604CodeRXPowerPro_lto.o
08001844-08004553main11 5364CodeRXPowerPro_lto.o
08004554-080045AFJumpToBootloader924CodeRXPowerPro_lto.o
080045B0-08004657HAL_UART_ErrorCallback1684CodeRXPowerPro_lto.o
08004658-0800468FmbCrc16564CodeRXPowerPro_lto.o
08004690-08004D0BMODE_SECONDARYPROTECTION_Exec1 6604CodeRXPowerPro_lto.o
08004D0C-0800515FMODE_SECONDARYPROTECTION_PLUS_Exec1 1084CodeRXPowerPro_lto.o
08005160-0800519FAHBPrescTable644CnstROPowerPro_lto.o
080051A0-080051BFAPBPrescTable324CnstROPowerPro_lto.o
080051C0-080051CF[.rodata..Lswitch.table.UART_SetConfig]164CnstROPowerPro_lto.o
080051D0-080051E3_start204CodeRXSEGGER_THUMB_Startup.o
080051E4-080051F3putchar164CodeRXfileops.o (libc_v6m_t_le_eabi_small.a)
080051F4-0800521Fputs444CodeRXfileops.o (libc_v6m_t_le_eabi_small.a)
08005220-0800523B__aeabi_i2d284CodeRXfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0800523C-080052A7vfprintf_l1084CodeRXprinops.o (libc_v6m_t_le_eabi_small.a)
080052A8-080052CFprintf404CodeRXprinops.o (libc_v6m_t_le_eabi_small.a)
080052D0-08005617__SEGGER_RTL_vfprintf_int_nwp8404CodeRX__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
08005618-08005643__SEGGER_RTL_X_file_stat444CodeRXprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
08005644-08005697_DoInit844CodeRXSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
08005698-080056FFSEGGER_RTT_WriteNoLock1044CodeRXSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
08005700-08005737SEGGER_RTT_Write564CodeRXSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
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2000072C-2000072FLVP_OVP_SM_On.lvpAndOvpInputTimeCounter44ZeroZIPowerPro_lto.o
20000730-20000730relaisState14ZeroZIPowerPro_lto.o
20000731-20000731smState.17111ZeroZIPowerPro_lto.o
20000732-20000732smState.16011ZeroZIPowerPro_lto.o
20000733-20000733smState.14511ZeroZIPowerPro_lto.o
20000734-20000734pauseTime14ZeroZIPowerPro_lto.o
20000735-20000735smState.13711ZeroZIPowerPro_lto.o
20000736-20000736smState.12211ZeroZIPowerPro_lto.o
20000737-20000737smState11ZeroZIPowerPro_lto.o
20000738-20000738pFlash.014ZeroZIPowerPro_lto.o
20000739-20000739mode11ZeroZIPowerPro_lto.o
2000073A-2000073AbuttonState11ZeroZIPowerPro_lto.o
2000073B-2000073B( UNUSED .=.+1 )1-------
2000073C-2000073ConTimeRT14ZeroZIPowerPro_lto.o
2000073D-2000073F( ALIGN .=.+3 )3-------
20000740-20000740onTimeGN14ZeroZIPowerPro_lto.o
20000741-20000743( ALIGN .=.+3 )3-------
20000744-20000744onTime14ZeroZIPowerPro_lto.o
20000745-20000747( ALIGN .=.+3 )3-------
20000748-20000748offTimeRT14ZeroZIPowerPro_lto.o
20000749-2000074B( ALIGN .=.+3 )3-------
2000074C-2000074CoffTimeGN14ZeroZIPowerPro_lto.o
2000074D-2000074F( ALIGN .=.+3 )3-------
20000750-20000750offTime14ZeroZIPowerPro_lto.o
20000751-20000753( ALIGN .=.+3 )3-------
20000754-20000754blinkModeRT14ZeroZIPowerPro_lto.o
20000755-20000757( ALIGN .=.+3 )3-------
20000758-20000758blinkModeGN14ZeroZIPowerPro_lto.o
20000759-2000075B( ALIGN .=.+3 )3-------
2000075C-2000075CalarmMode14ZeroZIPowerPro_lto.o
2000075D-2000075F( ALIGN .=.+3 )3-------
20000760-20000760OVP_SM_On.ovpInput14ZeroZIPowerPro_lto.o
20000761-20000763( ALIGN .=.+3 )3-------
20000764-20000764LVP_SM_On.lvpInput14ZeroZIPowerPro_lto.o
20000765-20000767( ALIGN .=.+3 )3-------
20000768-20000768LVP_OVP_SM_On.lvpOROvpInput14ZeroZIPowerPro_lto.o
20000769-20000B68_acUpBuffer1 0241ZeroZISEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B69-20000B78_acDownBuffer161ZeroZISEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B79-20000B7B( UNUSED .=.+3 )3-------
20000B7C-20000B7CbootLoaderMark14NoneZIPowerPro_lto.o
20000B7D-20000B7F( ALIGN .=.+3 )3-------
20000B80-20000B93__SEGGER_RTL_global_locale204InitRWmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
20000B94-20000B97uwTickPrio44InitRWPowerPro_lto.o
20000B98-20000B9Bstdout44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000B9C-20000B9Fstdin44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000BA0-20000BA3stderr44InitRWprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
20000BA4-20000BA7SystemCoreClock44InitRWPowerPro_lto.o
20000BA8-200027FF( UNUSED .=.+7256 )7 256-------
20002800-20002FFF[.bss.block.stack]2 0488NoneZI[ Linker created ]
+

UNUSED MEMORY SUMMARY

+

Detail

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeReason
08006863-080068631Unused memory between sections '.rodata.libc.__SEGGER_RTL_ascii_ctype_mask' and '.init_array'
08006B72-1FFFFFFF402 625 678Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.RAM1'
2000073B-2000073B1Unused memory between sections '.bss.buttonState' and '.bss.onTimeRT'
2000073D-2000073F3Filler between sections '.bss.onTimeRT' and '.bss.onTimeGN' as align=4
NOTE: section '.bss.onTimeRT' has size 1 that is not a multiple of its alignment 4
20000741-200007433Filler between sections '.bss.onTimeGN' and '.bss.onTime' as align=4
NOTE: section '.bss.onTimeGN' has size 1 that is not a multiple of its alignment 4
20000745-200007473Filler between sections '.bss.onTime' and '.bss.offTimeRT' as align=4
NOTE: section '.bss.onTime' has size 1 that is not a multiple of its alignment 4
20000749-2000074B3Filler between sections '.bss.offTimeRT' and '.bss.offTimeGN' as align=4
NOTE: section '.bss.offTimeRT' has size 1 that is not a multiple of its alignment 4
2000074D-2000074F3Filler between sections '.bss.offTimeGN' and '.bss.offTime' as align=4
NOTE: section '.bss.offTimeGN' has size 1 that is not a multiple of its alignment 4
20000751-200007533Filler between sections '.bss.offTime' and '.bss.blinkModeRT' as align=4
NOTE: section '.bss.offTime' has size 1 that is not a multiple of its alignment 4
20000755-200007573Filler between sections '.bss.blinkModeRT' and '.bss.blinkModeGN' as align=4
NOTE: section '.bss.blinkModeRT' has size 1 that is not a multiple of its alignment 4
20000759-2000075B3Filler between sections '.bss.blinkModeGN' and '.bss.alarmMode' as align=4
NOTE: section '.bss.blinkModeGN' has size 1 that is not a multiple of its alignment 4
2000075D-2000075F3Filler between sections '.bss.alarmMode' and '.bss.OVP_SM_On.ovpInput' as align=4
NOTE: section '.bss.alarmMode' has size 1 that is not a multiple of its alignment 4
20000761-200007633Filler between sections '.bss.OVP_SM_On.ovpInput' and '.bss.LVP_SM_On.lvpInput' as align=4
NOTE: section '.bss.OVP_SM_On.ovpInput' has size 1 that is not a multiple of its alignment 4
20000765-200007673Filler between sections '.bss.LVP_SM_On.lvpInput' and '.bss.LVP_OVP_SM_On.lvpOROvpInput' as align=4
NOTE: section '.bss.LVP_SM_On.lvpInput' has size 1 that is not a multiple of its alignment 4
20000B79-20000B7B3Unused memory between sections '.bss.libc._acDownBuffer' and '.no_init'
20000B7D-20000B7F3Filler between sections '.no_init' and '.data.libc.__SEGGER_RTL_global_locale' as align=4
NOTE: section '.no_init' has size 1 that is not a multiple of its alignment 4
20000BA8-200027FF7 256Unused memory between sections '.data.SystemCoreClock' and '.bss.block.stack'
+

INITIALIZATION TABLE

+

Constructor list

+ + + + + + + + + + + +
Table
Address		Called
Address		Called
Symbol or [section] name
0x080068640x08000605SystemCoreClockUpdate
+

Initialize by zero

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000000-20000233564modbusData
20000234-20000313224sys_data
20000314-200003BB168_SEGGER_RTT
200003BC-2000044F148huart1
20000450-200004B3100hadc1
200004B4-2000050F92hdma_usart1_tx
20000510-2000056B92hdma_usart1_rx
2000056C-200005C792hdma_adc1
200005C8-2000061376htim17
20000614-2000065F76htim16
20000660-2000067320adcData
20000674-2000068316flash_device_parameter_default
20000684-200006874voltageUout
20000688-2000068B4voltageUin
2000068C-2000068F4uwTick
20000690-200006934temp
20000694-200006974relais_temperature
20000698-2000069B4onTimeCounterSET
2000069C-2000069F4onTimeCounterRT
200006A0-200006A34onTimeCounterRESET
200006A4-200006A74onTimeCounterGN
200006A8-200006AB4onTimeCounter
200006AC-200006AF4oldTimeMSTick
200006B0-200006B34offTimeCounterRT
200006B4-200006B74offTimeCounterGN
200006B8-200006BB4offTimeCounter
200006BC-200006BF4numberOfBlinks
200006C0-200006C34msCounter
200006C4-200006C74longPressCounterButtonOn
200006C8-200006CB4longPressCounterButtonOff
200006CC-200006CF4__SEGGER_RTL_stdout_file
200006D0-200006D34__SEGGER_RTL_stdin_file
200006D4-200006D74__SEGGER_RTL_stderr_file
200006D8-200006DB4__SEGGER_RTL_locale_ptr
200006DC-200006DF4ic_overflows
200006E0-200006E34frequency
200006E4-200006E74dropLimitCounter
200006E8-200006EB4calTemperatureSensor30Value
200006EC-200006EF4blinkCounter
200006F0-200006F34autoRetryMode.170
200006F4-200006F74autoRetryMode
200006F8-200006FB4SECONDARYPROTECTION_SM_On.oldtime.175
200006FC-200006FF4SECONDARYPROTECTION_SM_On.oldtime
20000700-200007034SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176
20000704-200007074SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
20000708-2000070B4SECONDARYPROTECTION_SM_Error.retry_counter.181
2000070C-2000070F4SECONDARYPROTECTION_SM_Error.retry_counter
20000710-200007134SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182
20000714-200007174SECONDARYPROTECTION_SM_Error.oldTimeMSTick
20000718-2000071B4OVP_SM_On.ovpTimeCounter
2000071C-2000071F4OVP_SM_On.oldtime
20000720-200007234LVP_SM_On.oldtime
20000724-200007274LVP_SM_On.lvpTimeCounter
20000728-2000072B4LVP_OVP_SM_On.oldtime
2000072C-2000072F4LVP_OVP_SM_On.lvpAndOvpInputTimeCounter
20000730-200007301relaisState
20000731-200007311smState.171
20000732-200007321smState.160
20000733-200007331smState.145
20000734-200007341pauseTime
20000735-200007351smState.137
20000736-200007361smState.122
20000737-200007371smState
20000738-200007381pFlash.0
20000739-200007391mode
2000073A-2000073A1buttonState
20000000-2000073A1 851Total (66 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000073C-2000073C1onTimeRT
2000073C-2000073C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000740-200007401onTimeGN
20000740-200007401Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000744-200007441onTime
20000744-200007441Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000748-200007481offTimeRT
20000748-200007481Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000074C-2000074C1offTimeGN
2000074C-2000074C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000750-200007501offTime
20000750-200007501Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000754-200007541blinkModeRT
20000754-200007541Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000758-200007581blinkModeGN
20000758-200007581Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
2000075C-2000075C1alarmMode
2000075C-2000075C1Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000760-200007601OVP_SM_On.ovpInput
20000760-200007601Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by zero

+
RangeSizeSymbol or [section] name
20000764-200007641LVP_SM_On.lvpInput
20000764-200007641Total (1 sections)
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+
RangeSizeSymbol or [section] name
20000768-200007681LVP_OVP_SM_On.lvpOROvpInput
20000769-20000B681 024_acUpBuffer
20000B69-20000B7816_acDownBuffer
20000768-20000B781 041Total (3 sections)
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Summary

+
RangeSizeSymbol or [section] name
20000B80-20000B9320__SEGGER_RTL_global_locale
20000B94-20000B974uwTickPrio
20000B98-20000B9B4stdout
20000B9C-20000B9F4stdin
20000BA0-20000BA34stderr
20000BA4-20000BA74SystemCoreClock
20000B80-20000BA740Total (6 sections)
+ + + + + + + + + + + + + + + + + + + + +
DescriptionSize
Initialization table180 bytes
Source image40 bytes
Destination image2 943 bytes
Saving2 723 bytes
+

LINKER-CREATED VENEERS

+

Arm-Arm range extension veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Thumb range extension veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Arm-Thumb mode switch veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Arm mode switch veneers

+ + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Veneer TypeSize
Thumb-Arm mode switch0
Arm-Thumb mode switch0
Thumb-Thumb range extension0
Arm-Arm range extension0
Total:0
+

SYMBOL LIST

+

Function symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
ADC1_IRQHandler0x080058AF2CodeWkstm32c031xx_Vectors.o
ADC_DMAConvCplt0x08005D931002CodeLcPowerPro_lto.o
ADC_DMAError0x08005DF7202CodeLcPowerPro_lto.o
ADC_DMAHalfConvCplt0x0800581122CodeLcPowerPro_lto.o
DMA1_Channel1_IRQHandler0x080000C5164CodeGbPowerPro_lto.o
DMA1_Channel2_3_IRQHandler0x080000D5244CodeGbPowerPro_lto.o
DMAMUX1_IRQHandler0x080058AD2CodeWkstm32c031xx_Vectors.o
EEPROM_ReadDeviceParameter0x080017E5364CodeLcPowerPro_lto.o
EEPROM_StoreConfig0x08001809604CodeLcPowerPro_lto.o
EEPROM_Write0x0800169D2804CodeLcPowerPro_lto.o
EEPROM_WriteDefaults0x080017B5484CodeLcPowerPro_lto.o
EXTI0_1_IRQHandler0x080058A72CodeWkstm32c031xx_Vectors.o
EXTI2_3_IRQHandler0x080058A92CodeWkstm32c031xx_Vectors.o
EXTI4_15_IRQHandler0x080058AB2CodeWkstm32c031xx_Vectors.o
Error_Handler0x08005EEB42CodeLcPowerPro_lto.o
FLASH_IRQHandler0x080058A32CodeWkstm32c031xx_Vectors.o
FLASH_WaitForLastOperation0x08000B8D804CodeLcPowerPro_lto.o
HAL_ADC_ConfigChannel0x080006C96084CodeLcPowerPro_lto.o
HAL_DMA_IRQHandler0x08000AE91644CodeLcPowerPro_lto.o
HAL_DMA_Init0x080009452244CodeLcPowerPro_lto.o
HAL_DMA_Start_IT0x08000A251964CodeLcPowerPro_lto.o
HAL_Delay0x080006B5204CodeLcPowerPro_lto.o
HAL_FLASH_Unlock0x08000BDD324CodeLcPowerPro_lto.o
HAL_GPIO_Init0x08000BFD3804CodeLcPowerPro_lto.o
HAL_InitTick0x08000655964CodeLcPowerPro_lto.o
HAL_NVIC_SystemReset0x08005E0B42CodeLcPowerPro_lto.o
HAL_RCCEx_PeriphCLKConfig0x08000E0D2684CodeLcPowerPro_lto.o
HAL_RCC_GetPCLK1Freq0x08000DCD644CodeLcPowerPro_lto.o
HAL_RCC_GetSysClockFreq0x08000D79844CodeLcPowerPro_lto.o
HAL_TIM_Base_Init0x08000F192044CodeLcPowerPro_lto.o
HAL_TIM_IC_CaptureCallback0x080005BD564CodeLcPowerPro_lto.o
HAL_UART_ErrorCallback0x080045B11684CodeLcPowerPro_lto.o
HAL_UART_Init0x080010759724CodeLcPowerPro_lto.o
HAL_UART_Receive_DMA0x080015512484CodeLcPowerPro_lto.o
HardFault_Handler0x0800580B22CodeGbPowerPro_lto.o
I2C1_IRQHandler0x080058BB2CodeWkstm32c031xx_Vectors.o
JumpToBootloader0x08004555924CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_Exec0x080046911 6604CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_PLUS_Exec0x08004D0D1 1084CodeLcPowerPro_lto.o
NMI_Handler0x0800580922CodeGbPowerPro_lto.o
PendSV_Handler0x0800580F22CodeGbPowerPro_lto.o
RCC_IRQHandler0x080058A52CodeWkstm32c031xx_Vectors.o
RTC_IRQHandler0x080058A12CodeWkstm32c031xx_Vectors.o
Reset_Handler0x08005F072CodeGbSTM32C0xx_Startup.o
SEGGER_RTT_Write0x08005701564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteNoLock0x080056991044CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
SPI1_IRQHandler0x080058BD2CodeWkstm32c031xx_Vectors.o
SVC_Handler0x0800580D22CodeGbPowerPro_lto.o
SysTick_Handler0x080000B5164CodeGbPowerPro_lto.o
SystemCoreClockUpdate0x08000605804CodeGbPowerPro_lto.o
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+

Function symbols by address

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0x08005D3B__aeabi_memcpy42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08005D3B__aeabi_memcpy2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x08005D49__SEGGER_RTL_ascii_mbtowc462CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08005D77__SEGGER_RTL_ascii_tolower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08005D85__SEGGER_RTL_ascii_towlower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08005D93ADC_DMAConvCplt1002CodeLcPowerPro_lto.o
0x08005DF7ADC_DMAError202CodeLcPowerPro_lto.o
0x08005E0BHAL_NVIC_SystemReset42CodeLcPowerPro_lto.o
0x08005E0FUART_DMAReceiveCplt1682CodeLcPowerPro_lto.o
0x08005EB7UART_DMARxHalfCplt362CodeLcPowerPro_lto.o
0x08005EDBUART_DMAAbortOnError162CodeLcPowerPro_lto.o
0x08005EEBError_Handler42CodeLcPowerPro_lto.o
0x08005F07reset_handler2CodeGbSTM32C0xx_Startup.o
0x08005F07Reset_Handler2CodeGbSTM32C0xx_Startup.o
0x08005F0F__aeabi_ddiv1962CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08005FD3__aeabi_d2iz522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08006007__aeabi_f2uiz362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x0800602B__aeabi_ui2d282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08006047__aeabi_idiv642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08006087__aeabi_uidiv562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x080060BF__aeabi_uldivmod1362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
0x08006147__SEGGER_RTL_stream_write162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
0x08006157__SEGGER_RTL_X_file_bufsize42CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x0800615B_WriteBlocking882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x080061B3__aeabi_memclr82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061B3__aeabi_memclr42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061B3__aeabi_memclr202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061B5__aeabi_memset82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061B5__aeabi_memset42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061B5__aeabi_memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061BBmemset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
0x080061C7__SEGGER_RTL_ascii_wctomb162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080061D7__SEGGER_RTL_ascii_toupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080061E3__SEGGER_RTL_ascii_towupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x08006A4D__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
0x08006B4D__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
0x08006B5F__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
+

Function symbols by descending size

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Symbol nameSizeAlignTypeBdObject File
main11 5364CodeGbPowerPro_lto.o
MODE_SECONDARYPROTECTION_Exec1 6604CodeLcPowerPro_lto.o
MODE_SECONDARYPROTECTION_PLUS_Exec1 1084CodeLcPowerPro_lto.o
HAL_UART_Init9724CodeLcPowerPro_lto.o
USART1_IRQHandler9444CodeGbPowerPro_lto.o
__SEGGER_RTL_vfprintf8404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_vfprintf_int_nwp8404CodeGb__SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a)
HAL_ADC_ConfigChannel6084CodeLcPowerPro_lto.o
__aeabi_dmul_aux3942CodeLcfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
HAL_GPIO_Init3804CodeLcPowerPro_lto.o
TIM16_IRQHandler2884CodeGbPowerPro_lto.o
EEPROM_Write2804CodeLcPowerPro_lto.o
HAL_RCCEx_PeriphCLKConfig2684CodeLcPowerPro_lto.o
HAL_UART_Receive_DMA2484CodeLcPowerPro_lto.o
HAL_DMA_Init2244CodeLcPowerPro_lto.o
HAL_TIM_Base_Init2044CodeLcPowerPro_lto.o
HAL_DMA_Start_IT1964CodeLcPowerPro_lto.o
__aeabi_ddiv1962CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_fmul1822CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
HAL_UART_ErrorCallback1684CodeLcPowerPro_lto.o
UART_DMAReceiveCplt1682CodeLcPowerPro_lto.o
HAL_DMA_IRQHandler1644CodeLcPowerPro_lto.o
TIM_Base_SetConfig1444CodeLcPowerPro_lto.o
UART_DMAError1382CodeLcPowerPro_lto.o
__SEGGER_RTL_putc1382CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__aeabi_uldivmod1362CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
vfprintf_l1084CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
SEGGER_RTT_WriteNoLock1044CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
ADC_DMAConvCplt1002CodeLcPowerPro_lto.o
HAL_InitTick964CodeLcPowerPro_lto.o
UART_EndRxTransfer964CodeLcPowerPro_lto.o
UART_WaitOnFlagUntilTimeout964CodeLcPowerPro_lto.o
JumpToBootloader924CodeLcPowerPro_lto.o
_WriteBlocking882CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
HAL_RCC_GetSysClockFreq844CodeLcPowerPro_lto.o
UARTEx_SetNbDataToProcess844CodeLcPowerPro_lto.o
_DoInit844CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
FLASH_WaitForLastOperation804CodeLcPowerPro_lto.o
SystemCoreClockUpdate804CodeGbPowerPro_lto.o
UART_DMATransmitCplt804CodeLcPowerPro_lto.o
HAL_RCC_GetPCLK1Freq644CodeLcPowerPro_lto.o
__aeabi_idiv642CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
EEPROM_StoreConfig604CodeLcPowerPro_lto.o
_WriteNoCheck582CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
HAL_TIM_IC_CaptureCallback564CodeLcPowerPro_lto.o
SEGGER_RTT_Write564CodeGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_uidiv562CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
mbCrc16564CodeLcPowerPro_lto.o
__aeabi_d2iz522CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
fwrite502CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
EEPROM_WriteDefaults484CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_mbtowc462CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__aeabi_d2uiz462CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_lmul462CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
memcmp462CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_stat444CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
puts444CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
printf404CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
EEPROM_ReadDeviceParameter364CodeLcPowerPro_lto.o
UART_DMARxHalfCplt362CodeLcPowerPro_lto.o
__aeabi_f2uiz362CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
fputc342CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
HAL_FLASH_Unlock324CodeLcPowerPro_lto.o
__aeabi_ui2f302CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__NVIC_SystemReset284CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_isctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_iswctype284CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__aeabi_ui2d282CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_prin_flush262CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
vfprintf262CodeWkprinops.o (libc_v6m_t_le_eabi_small.a)
DMA1_Channel2_3_IRQHandler244CodeGbPowerPro_lto.o
_GetAvailWriteSpace222CodeLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_i2d224CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
ADC_DMAError202CodeLcPowerPro_lto.o
HAL_Delay204CodeLcPowerPro_lto.o
__SEGGER_RTL_current_locale204CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
__aeabi_memclr202CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_init_prin_l182CodeGbprinops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a)
DMA1_Channel1_IRQHandler164CodeGbPowerPro_lto.o
SysTick_Handler164CodeGbPowerPro_lto.o
SystemInit164CodeGbPowerPro_lto.o
UART_DMAAbortOnError162CodeLcPowerPro_lto.o
__SEGGER_RTL_ascii_wctomb162CodeGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stream_write162CodeLcprinops.o (libc_v6m_t_le_eabi_small.a)
putchar164CodeWkfileops.o (libc_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_tolower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towlower142CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
_start144CodeGbSEGGER_THUMB_Startup.o
memcpy142CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
strlen142CodeWkstrops.o (strops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_toupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_ascii_towupper122CodeLcmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_X_file_write102CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__aeabi_idiv062CodeWkintasmops_arm.o (libc_v6m_t_le_eabi_small.a)
Error_Handler42CodeLcPowerPro_lto.o
HAL_NVIC_SystemReset42CodeLcPowerPro_lto.o
__SEGGER_RTL_X_file_bufsize42CodeGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
ADC_DMAHalfConvCplt22CodeLcPowerPro_lto.o
HardFault_Handler22CodeGbPowerPro_lto.o
NMI_Handler22CodeGbPowerPro_lto.o
PendSV_Handler22CodeGbPowerPro_lto.o
SVC_Handler22CodeGbPowerPro_lto.o
UART_DMATxHalfCplt22CodeLcPowerPro_lto.o
exit24CodeGbSEGGER_THUMB_Startup.o
ADC1_IRQHandler2CodeWkstm32c031xx_Vectors.o
DMAMUX1_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI0_1_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI2_3_IRQHandler2CodeWkstm32c031xx_Vectors.o
EXTI4_15_IRQHandler2CodeWkstm32c031xx_Vectors.o
FLASH_IRQHandler2CodeWkstm32c031xx_Vectors.o
I2C1_IRQHandler2CodeWkstm32c031xx_Vectors.o
RCC_IRQHandler2CodeWkstm32c031xx_Vectors.o
RTC_IRQHandler2CodeWkstm32c031xx_Vectors.o
Reset_Handler2CodeGbSTM32C0xx_Startup.o
SPI1_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM14_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM17_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM1_BRK_UP_TRG_COM_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM1_CC_IRQHandler2CodeWkstm32c031xx_Vectors.o
TIM3_IRQHandler2CodeWkstm32c031xx_Vectors.o
USART2_IRQHandler2CodeWkstm32c031xx_Vectors.o
WWDG_IRQHandler2CodeWkstm32c031xx_Vectors.o
__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
__aeabi_dmul2CodeWkfloatasmops_arm.o (libc_v6m_t_le_eabi_small.a)
__aeabi_memclr42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memclr82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memcpy82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset42CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__aeabi_memset82CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
__startup_complete4CodeGbSEGGER_THUMB_Startup.o
memset2CodeWkstrasmops_arm.o (strops_v6m_t_le_eabi_small.a)
reset_handler2CodeGbSTM32C0xx_Startup.o
+

Read-write data symbols by name

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Symbol nameAddressSizeAlignTypeBdObject File
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter0x2000072C44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInput0x2000076814ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.oldtime0x2000072844ZeroLcPowerPro_lto.o
LVP_SM_On.lvpInput0x2000076414ZeroLcPowerPro_lto.o
LVP_SM_On.lvpTimeCounter0x2000072444ZeroLcPowerPro_lto.o
LVP_SM_On.oldtime0x2000072044ZeroLcPowerPro_lto.o
OVP_SM_On.oldtime0x2000071C44ZeroLcPowerPro_lto.o
OVP_SM_On.ovpInput0x2000076014ZeroLcPowerPro_lto.o
OVP_SM_On.ovpTimeCounter0x2000071844ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick0x2000071444ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.1820x2000071044ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter0x2000070C44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.1810x2000070844ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter0x2000070444ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.1760x2000070044ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime0x200006FC44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.1750x200006F844ZeroLcPowerPro_lto.o
SystemCoreClock0x20000BA444InitLcPowerPro_lto.o
_SEGGER_RTT0x200003141684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
__RAL_global_locale0x20000B80204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_global_locale0x20000B80204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_locale_ptr0x200006D844ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_file0x200006D444ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_file0x200006D044ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdout_file0x200006CC44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acDownBuffer0x20000B6916ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
_acUpBuffer0x200007691 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
adcData0x20000660204ZeroLcPowerPro_lto.o
alarmMode0x2000075C14ZeroLcPowerPro_lto.o
autoRetryMode0x200006F444ZeroLcPowerPro_lto.o
autoRetryMode.1700x200006F044ZeroLcPowerPro_lto.o
blinkCounter0x200006EC44ZeroLcPowerPro_lto.o
blinkModeGN0x2000075814ZeroLcPowerPro_lto.o
blinkModeRT0x2000075414ZeroLcPowerPro_lto.o
bootLoaderMark0x20000B7C14NoneLcPowerPro_lto.o
buttonState0x2000073A1ZeroLcPowerPro_lto.o
calTemperatureSensor30Value0x200006E844ZeroLcPowerPro_lto.o
dropLimitCounter0x200006E444ZeroLcPowerPro_lto.o
flash_device_parameter_default0x20000674164ZeroLcPowerPro_lto.o
frequency0x200006E044ZeroLcPowerPro_lto.o
hadc10x200004501004ZeroLcPowerPro_lto.o
hdma_adc10x2000056C924ZeroLcPowerPro_lto.o
hdma_usart1_rx0x20000510924ZeroLcPowerPro_lto.o
hdma_usart1_tx0x200004B4924ZeroLcPowerPro_lto.o
htim160x20000614764ZeroLcPowerPro_lto.o
htim170x200005C8764ZeroLcPowerPro_lto.o
huart10x200003BC1484ZeroLcPowerPro_lto.o
ic_overflows0x200006DC44ZeroLcPowerPro_lto.o
longPressCounterButtonOff0x200006C844ZeroLcPowerPro_lto.o
longPressCounterButtonOn0x200006C444ZeroLcPowerPro_lto.o
modbusData0x200000005644ZeroLcPowerPro_lto.o
mode0x200007391ZeroLcPowerPro_lto.o
msCounter0x200006C044ZeroLcPowerPro_lto.o
numberOfBlinks0x200006BC44ZeroLcPowerPro_lto.o
offTime0x2000075014ZeroLcPowerPro_lto.o
offTimeCounter0x200006B844ZeroLcPowerPro_lto.o
offTimeCounterGN0x200006B444ZeroLcPowerPro_lto.o
offTimeCounterRT0x200006B044ZeroLcPowerPro_lto.o
offTimeGN0x2000074C14ZeroLcPowerPro_lto.o
offTimeRT0x2000074814ZeroLcPowerPro_lto.o
oldTimeMSTick0x200006AC44ZeroLcPowerPro_lto.o
onTime0x2000074414ZeroLcPowerPro_lto.o
onTimeCounter0x200006A844ZeroLcPowerPro_lto.o
onTimeCounterGN0x200006A444ZeroLcPowerPro_lto.o
onTimeCounterRESET0x200006A044ZeroLcPowerPro_lto.o
onTimeCounterRT0x2000069C44ZeroLcPowerPro_lto.o
onTimeCounterSET0x2000069844ZeroLcPowerPro_lto.o
onTimeGN0x2000074014ZeroLcPowerPro_lto.o
onTimeRT0x2000073C14ZeroLcPowerPro_lto.o
pFlash.00x2000073814ZeroLcPowerPro_lto.o
pauseTime0x2000073414ZeroLcPowerPro_lto.o
relaisState0x2000073014ZeroLcPowerPro_lto.o
relais_temperature0x2000069444ZeroLcPowerPro_lto.o
smState0x200007371ZeroLcPowerPro_lto.o
smState.1220x200007361ZeroLcPowerPro_lto.o
smState.1370x200007351ZeroLcPowerPro_lto.o
smState.1450x200007331ZeroLcPowerPro_lto.o
smState.1600x200007321ZeroLcPowerPro_lto.o
smState.1710x200007311ZeroLcPowerPro_lto.o
stderr0x20000BA044InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdin0x20000B9C44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdout0x20000B9844InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
sys_data0x200002342244ZeroLcPowerPro_lto.o
temp0x2000069044ZeroLcPowerPro_lto.o
uwTick0x2000068C44ZeroLcPowerPro_lto.o
uwTickPrio0x20000B9444InitLcPowerPro_lto.o
voltageUin0x2000068844ZeroLcPowerPro_lto.o
voltageUout0x2000068444ZeroLcPowerPro_lto.o
+

Read-write data symbols by address

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AddressSymbol nameSizeAlignTypeBdObject File
0x20000000modbusData5644ZeroLcPowerPro_lto.o
0x20000234sys_data2244ZeroLcPowerPro_lto.o
0x20000314_SEGGER_RTT1684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200003BChuart11484ZeroLcPowerPro_lto.o
0x20000450hadc11004ZeroLcPowerPro_lto.o
0x200004B4hdma_usart1_tx924ZeroLcPowerPro_lto.o
0x20000510hdma_usart1_rx924ZeroLcPowerPro_lto.o
0x2000056Chdma_adc1924ZeroLcPowerPro_lto.o
0x200005C8htim17764ZeroLcPowerPro_lto.o
0x20000614htim16764ZeroLcPowerPro_lto.o
0x20000660adcData204ZeroLcPowerPro_lto.o
0x20000674flash_device_parameter_default164ZeroLcPowerPro_lto.o
0x20000684voltageUout44ZeroLcPowerPro_lto.o
0x20000688voltageUin44ZeroLcPowerPro_lto.o
0x2000068CuwTick44ZeroLcPowerPro_lto.o
0x20000690temp44ZeroLcPowerPro_lto.o
0x20000694relais_temperature44ZeroLcPowerPro_lto.o
0x20000698onTimeCounterSET44ZeroLcPowerPro_lto.o
0x2000069ConTimeCounterRT44ZeroLcPowerPro_lto.o
0x200006A0onTimeCounterRESET44ZeroLcPowerPro_lto.o
0x200006A4onTimeCounterGN44ZeroLcPowerPro_lto.o
0x200006A8onTimeCounter44ZeroLcPowerPro_lto.o
0x200006AColdTimeMSTick44ZeroLcPowerPro_lto.o
0x200006B0offTimeCounterRT44ZeroLcPowerPro_lto.o
0x200006B4offTimeCounterGN44ZeroLcPowerPro_lto.o
0x200006B8offTimeCounter44ZeroLcPowerPro_lto.o
0x200006BCnumberOfBlinks44ZeroLcPowerPro_lto.o
0x200006C0msCounter44ZeroLcPowerPro_lto.o
0x200006C4longPressCounterButtonOn44ZeroLcPowerPro_lto.o
0x200006C8longPressCounterButtonOff44ZeroLcPowerPro_lto.o
0x200006CC__SEGGER_RTL_stdout_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200006D0__SEGGER_RTL_stdin_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200006D4__SEGGER_RTL_stderr_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x200006D8__SEGGER_RTL_locale_ptr44ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x200006DCic_overflows44ZeroLcPowerPro_lto.o
0x200006E0frequency44ZeroLcPowerPro_lto.o
0x200006E4dropLimitCounter44ZeroLcPowerPro_lto.o
0x200006E8calTemperatureSensor30Value44ZeroLcPowerPro_lto.o
0x200006ECblinkCounter44ZeroLcPowerPro_lto.o
0x200006F0autoRetryMode.17044ZeroLcPowerPro_lto.o
0x200006F4autoRetryMode44ZeroLcPowerPro_lto.o
0x200006F8SECONDARYPROTECTION_SM_On.oldtime.17544ZeroLcPowerPro_lto.o
0x200006FCSECONDARYPROTECTION_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x20000700SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.17644ZeroLcPowerPro_lto.o
0x20000704SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
0x20000708SECONDARYPROTECTION_SM_Error.retry_counter.18144ZeroLcPowerPro_lto.o
0x2000070CSECONDARYPROTECTION_SM_Error.retry_counter44ZeroLcPowerPro_lto.o
0x20000710SECONDARYPROTECTION_SM_Error.oldTimeMSTick.18244ZeroLcPowerPro_lto.o
0x20000714SECONDARYPROTECTION_SM_Error.oldTimeMSTick44ZeroLcPowerPro_lto.o
0x20000718OVP_SM_On.ovpTimeCounter44ZeroLcPowerPro_lto.o
0x2000071COVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x20000720LVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x20000724LVP_SM_On.lvpTimeCounter44ZeroLcPowerPro_lto.o
0x20000728LVP_OVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
0x2000072CLVP_OVP_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
0x20000730relaisState14ZeroLcPowerPro_lto.o
0x20000731smState.1711ZeroLcPowerPro_lto.o
0x20000732smState.1601ZeroLcPowerPro_lto.o
0x20000733smState.1451ZeroLcPowerPro_lto.o
0x20000734pauseTime14ZeroLcPowerPro_lto.o
0x20000735smState.1371ZeroLcPowerPro_lto.o
0x20000736smState.1221ZeroLcPowerPro_lto.o
0x20000737smState1ZeroLcPowerPro_lto.o
0x20000738pFlash.014ZeroLcPowerPro_lto.o
0x20000739mode1ZeroLcPowerPro_lto.o
0x2000073AbuttonState1ZeroLcPowerPro_lto.o
0x2000073ConTimeRT14ZeroLcPowerPro_lto.o
0x20000740onTimeGN14ZeroLcPowerPro_lto.o
0x20000744onTime14ZeroLcPowerPro_lto.o
0x20000748offTimeRT14ZeroLcPowerPro_lto.o
0x2000074CoffTimeGN14ZeroLcPowerPro_lto.o
0x20000750offTime14ZeroLcPowerPro_lto.o
0x20000754blinkModeRT14ZeroLcPowerPro_lto.o
0x20000758blinkModeGN14ZeroLcPowerPro_lto.o
0x2000075CalarmMode14ZeroLcPowerPro_lto.o
0x20000760OVP_SM_On.ovpInput14ZeroLcPowerPro_lto.o
0x20000764LVP_SM_On.lvpInput14ZeroLcPowerPro_lto.o
0x20000768LVP_OVP_SM_On.lvpOROvpInput14ZeroLcPowerPro_lto.o
0x20000769_acUpBuffer1 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000B69_acDownBuffer16ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000B7CbootLoaderMark14NoneLcPowerPro_lto.o
0x20000B80__SEGGER_RTL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x20000B80__RAL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x20000B94uwTickPrio44InitLcPowerPro_lto.o
0x20000B98stdout44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000B9Cstdin44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000BA0stderr44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
0x20000BA4SystemCoreClock44InitLcPowerPro_lto.o
+

Read-write data symbols by descending size

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Symbol nameSizeAlignTypeBdObject File
_acUpBuffer1 024ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
modbusData5644ZeroLcPowerPro_lto.o
sys_data2244ZeroLcPowerPro_lto.o
_SEGGER_RTT1684ZeroGbSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
huart11484ZeroLcPowerPro_lto.o
hadc11004ZeroLcPowerPro_lto.o
hdma_adc1924ZeroLcPowerPro_lto.o
hdma_usart1_rx924ZeroLcPowerPro_lto.o
hdma_usart1_tx924ZeroLcPowerPro_lto.o
htim16764ZeroLcPowerPro_lto.o
htim17764ZeroLcPowerPro_lto.o
__RAL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_global_locale204InitGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
adcData204ZeroLcPowerPro_lto.o
_acDownBuffer16ZeroLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
flash_device_parameter_default164ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
LVP_SM_On.lvpTimeCounter44ZeroLcPowerPro_lto.o
LVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
OVP_SM_On.oldtime44ZeroLcPowerPro_lto.o
OVP_SM_On.ovpTimeCounter44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.18244ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_Error.retry_counter.18144ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.17644ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime44ZeroLcPowerPro_lto.o
SECONDARYPROTECTION_SM_On.oldtime.17544ZeroLcPowerPro_lto.o
SystemCoreClock44InitLcPowerPro_lto.o
__SEGGER_RTL_locale_ptr44ZeroGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stderr_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdin_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
__SEGGER_RTL_stdout_file44ZeroLcprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
autoRetryMode44ZeroLcPowerPro_lto.o
autoRetryMode.17044ZeroLcPowerPro_lto.o
blinkCounter44ZeroLcPowerPro_lto.o
calTemperatureSensor30Value44ZeroLcPowerPro_lto.o
dropLimitCounter44ZeroLcPowerPro_lto.o
frequency44ZeroLcPowerPro_lto.o
ic_overflows44ZeroLcPowerPro_lto.o
longPressCounterButtonOff44ZeroLcPowerPro_lto.o
longPressCounterButtonOn44ZeroLcPowerPro_lto.o
msCounter44ZeroLcPowerPro_lto.o
numberOfBlinks44ZeroLcPowerPro_lto.o
offTimeCounter44ZeroLcPowerPro_lto.o
offTimeCounterGN44ZeroLcPowerPro_lto.o
offTimeCounterRT44ZeroLcPowerPro_lto.o
oldTimeMSTick44ZeroLcPowerPro_lto.o
onTimeCounter44ZeroLcPowerPro_lto.o
onTimeCounterGN44ZeroLcPowerPro_lto.o
onTimeCounterRESET44ZeroLcPowerPro_lto.o
onTimeCounterRT44ZeroLcPowerPro_lto.o
onTimeCounterSET44ZeroLcPowerPro_lto.o
relais_temperature44ZeroLcPowerPro_lto.o
stderr44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdin44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
stdout44InitGbprinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a)
temp44ZeroLcPowerPro_lto.o
uwTick44ZeroLcPowerPro_lto.o
uwTickPrio44InitLcPowerPro_lto.o
voltageUin44ZeroLcPowerPro_lto.o
voltageUout44ZeroLcPowerPro_lto.o
LVP_OVP_SM_On.lvpOROvpInput14ZeroLcPowerPro_lto.o
LVP_SM_On.lvpInput14ZeroLcPowerPro_lto.o
OVP_SM_On.ovpInput14ZeroLcPowerPro_lto.o
alarmMode14ZeroLcPowerPro_lto.o
blinkModeGN14ZeroLcPowerPro_lto.o
blinkModeRT14ZeroLcPowerPro_lto.o
bootLoaderMark14NoneLcPowerPro_lto.o
buttonState1ZeroLcPowerPro_lto.o
mode1ZeroLcPowerPro_lto.o
offTime14ZeroLcPowerPro_lto.o
offTimeGN14ZeroLcPowerPro_lto.o
offTimeRT14ZeroLcPowerPro_lto.o
onTime14ZeroLcPowerPro_lto.o
onTimeGN14ZeroLcPowerPro_lto.o
onTimeRT14ZeroLcPowerPro_lto.o
pFlash.014ZeroLcPowerPro_lto.o
pauseTime14ZeroLcPowerPro_lto.o
relaisState14ZeroLcPowerPro_lto.o
smState1ZeroLcPowerPro_lto.o
smState.1221ZeroLcPowerPro_lto.o
smState.1371ZeroLcPowerPro_lto.o
smState.1451ZeroLcPowerPro_lto.o
smState.1601ZeroLcPowerPro_lto.o
smState.1711ZeroLcPowerPro_lto.o
+

Read-only data symbols by name

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Read-only data symbols by address

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AddressSymbol nameSizeAlignTypeBdObject File
0x08005160AHBPrescTable644CnstLcPowerPro_lto.o
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0x08005784__SEGGER_RTL_c_locale124CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
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0x08005EEEUARTPrescTable242CnstLcPowerPro_lto.o
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0x080065AB__SEGGER_RTL_data_utf8_period2CnstGbmbops.o (mbops_timeops_v6m_t_le_eabi_small.a)
0x080067DB_DoInit._aInitStr17CnstLcSEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a)
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0x08006868UARTEx_SetNbDataToProcess.numerator8CnstLcPowerPro_lto.o
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0x08006B24__SEGGER_init_data__[40]4CnstLc[ Linker created ]
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Untyped symbols by name

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Symbol nameValueSizeAlignTypeBdObject File
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__FLASH1_segment_start__0x08000000----Gb[ Linker created ]
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__ctors_end__0x08006868----Gb[ Linker created ]
__ctors_start__0x08006864----Gb[ Linker created ]
__stack_end__0x20003000----Gb[ Linker created ]
__thread_pointer$0x00000000----Gb[ Linker created ]
_vectors0x08000000[180]256CodeGbstm32c031xx_Vectors.o
_vectors_end0x080000B4256CodeLcstm32c031xx_Vectors.o
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Untyped symbols by address

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ValueSymbol nameSizeAlignTypeBdObject File
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0x00000800__STACKSIZE__----Gb[ Linker created ]
0x00003000__RAM_segment_used_size__----Gb[ Linker created ]
0x00003000__RAM_segment_size__----Gb[ Linker created ]
0x00003000__RAM1_segment_used_size__----Gb[ Linker created ]
0x00003000__RAM1_segment_size__----Gb[ Linker created ]
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0x080000B4_vectors_end256CodeLcstm32c031xx_Vectors.o
0x08006864__ctors_start__----Gb[ Linker created ]
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0x20000000__RAM_segment_used_start__----Gb[ Linker created ]
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0x20000000__RAM1_segment_used_start__----Gb[ Linker created ]
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0x20003000__stack_end__----Gb[ Linker created ]
0x20003000__RAM_segment_used_end__----Gb[ Linker created ]
0x20003000__RAM_segment_end__----Gb[ Linker created ]
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0x20003000__RAM1_segment_end__----Gb[ Linker created ]
+

REGION LIST

+

Regions by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSize
FLASH08000000-080077FF30 720
FLASH108000000-080077FF30 720
RAM20000000-20002FFF12 288
RAM120000000-20002FFF12 288
+

Analysis

+FLASH: + Identical to region FLASH1 + +FLASH1: + Identical to region FLASH + +RAM: + Identical to region RAM1 + +RAM1: + Identical to region RAM +

BLOCK LIST

+

Blocks by name

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSizeOrdering
ctors08006864-080068674Auto
stack20002800-20002FFF2 048Auto
vectors08000000-080000B3180Auto
+

Blocks by address

+ + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeNameOrdering
08000000-080000B3180vectorsAuto
08006864-080068674ctorsAuto
20002800-20002FFF2 048stackAuto
+

STACK SIZES

+

Functions by stack size

+ + + + + + +
Function nameStackObject File
+

Functions without stack size information

+ HAL_DMA_IRQHandler + HAL_TIM_IC_CaptureCallback + HAL_UART_ErrorCallback + UART_EndRxTransfer + UART_DMAAbortOnError + HAL_RCC_GetPCLK1Freq + HAL_InitTick + HAL_Delay + ADC_DMAConvCplt + ADC_DMAHalfConvCplt + ADC_DMAError + HAL_ADC_ConfigChannel + HAL_NVIC_SystemReset + __NVIC_SystemReset + HAL_DMA_Init + HAL_DMA_Start_IT + FLASH_WaitForLastOperation + HAL_FLASH_Unlock + HAL_GPIO_Init + HAL_RCC_GetSysClockFreq + HAL_RCCEx_PeriphCLKConfig + HAL_TIM_Base_Init + TIM_Base_SetConfig + HAL_UART_Init + UART_WaitOnFlagUntilTimeout + Error_Handler + UART_DMATransmitCplt + UART_DMATxHalfCplt + UART_DMAError + HAL_UART_Receive_DMA + UART_DMARxHalfCplt + UART_DMAReceiveCplt + UARTEx_SetNbDataToProcess + EEPROM_Write + EEPROM_WriteDefaults + EEPROM_ReadDeviceParameter + EEPROM_StoreConfig + mbCrc16 + MODE_SECONDARYPROTECTION_PLUS_Exec + MODE_SECONDARYPROTECTION_Exec + JumpToBootloader + NMI_Handler + HardFault_Handler + SVC_Handler + PendSV_Handler + SysTick_Handler + DMA1_Channel1_IRQHandler + DMA1_Channel2_3_IRQHandler + TIM16_IRQHandler + USART1_IRQHandler + SystemInit + SystemCoreClockUpdate + main + _start + __SEGGER_init_done + __startup_complete + exit + WWDG_IRQHandler + RTC_IRQHandler + FLASH_IRQHandler + RCC_IRQHandler + EXTI0_1_IRQHandler + EXTI2_3_IRQHandler + EXTI4_15_IRQHandler + DMAMUX1_IRQHandler + ADC1_IRQHandler + TIM1_BRK_UP_TRG_COM_IRQHandler + TIM1_CC_IRQHandler + TIM3_IRQHandler + TIM14_IRQHandler + TIM17_IRQHandler + I2C1_IRQHandler + SPI1_IRQHandler + USART2_IRQHandler + reset_handler + Reset_Handler + putchar + fputc + fwrite + puts + __aeabi_dmul_aux + .L__aeabi_d2uiz_fast_entry + __aeabi_fmul + __aeabi_dmul + __aeabi_ddiv + __aeabi_d2iz + __aeabi_f2uiz + __aeabi_d2uiz + __aeabi_i2d + __aeabi_ui2f + __aeabi_ui2d + __aeabi_lmul + __aeabi_idiv + __aeabi_idiv0 + __aeabi_uidiv + __aeabi_uldivmod + __SEGGER_RTL_stream_write + __SEGGER_RTL_putc + __SEGGER_RTL_prin_flush + __SEGGER_RTL_init_prin_l + vfprintf + vfprintf_l + printf + __SEGGER_RTL_vfprintf_int_nwp + __SEGGER_init_zero + __SEGGER_init_copy + __SEGGER_init_ctors + __SEGGER_RTL_X_file_stat + __SEGGER_RTL_X_file_bufsize + __SEGGER_RTL_X_file_write + _DoInit + _GetAvailWriteSpace + _WriteNoCheck + _WriteBlocking + SEGGER_RTT_WriteNoLock + SEGGER_RTT_Write + memcmp + strlen + memcpy + __aeabi_memcpy + __aeabi_memcpy4 + __aeabi_memcpy8 + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset + __SEGGER_RTL_ascii_isctype + __SEGGER_RTL_ascii_toupper + __SEGGER_RTL_ascii_tolower + __SEGGER_RTL_ascii_iswctype + __SEGGER_RTL_ascii_towupper + __SEGGER_RTL_ascii_towlower + __SEGGER_RTL_current_locale + __SEGGER_RTL_ascii_mbtowc + __SEGGER_RTL_ascii_wctomb + __SEGGER_RTL_vfprintf +

UNUSED INPUTS

+

Unused object files

+No unused object files +

ABSOLUTE LISTING

+

Section .vectors from stm32c031xx_Vectors.o, size=180, align=256

+
+
_vectors:
+  0x08000000:  20003000     DC.W       20003000               ; R_ARM_ABS32
+  0x08000004:  08005F07     DC.W       reset_handler
+  0x08000008:  08005809     DC.W       NMI_Handler
+  0x0800000C:  0800580B     DC.W       HardFault_Handler
+  0x08000010:  00           DC.B       0x00                     ; '\0'
+  0x08000011:  00           DC.B       0x00                     ; '\0'
+  0x08000012:  00           DC.B       0x00                     ; '\0'
+  0x08000013:  00           DC.B       0x00                     ; '\0'
+  0x08000014:  00           DC.B       0x00                     ; '\0'
+  0x08000015:  00           DC.B       0x00                     ; '\0'
+  0x08000016:  00           DC.B       0x00                     ; '\0'
+  0x08000017:  00           DC.B       0x00                     ; '\0'
+  0x08000018:  00           DC.B       0x00                     ; '\0'
+  0x08000019:  00           DC.B       0x00                     ; '\0'
+  0x0800001A:  00           DC.B       0x00                     ; '\0'
+  0x0800001B:  00           DC.B       0x00                     ; '\0'
+  0x0800001C:  00           DC.B       0x00                     ; '\0'
+  0x0800001D:  00           DC.B       0x00                     ; '\0'
+  0x0800001E:  00           DC.B       0x00                     ; '\0'
+  0x0800001F:  00           DC.B       0x00                     ; '\0'
+  0x08000020:  00           DC.B       0x00                     ; '\0'
+  0x08000021:  00           DC.B       0x00                     ; '\0'
+  0x08000022:  00           DC.B       0x00                     ; '\0'
+  0x08000023:  00           DC.B       0x00                     ; '\0'
+  0x08000024:  00           DC.B       0x00                     ; '\0'
+  0x08000025:  00           DC.B       0x00                     ; '\0'
+  0x08000026:  00           DC.B       0x00                     ; '\0'
+  0x08000027:  00           DC.B       0x00                     ; '\0'
+  0x08000028:  00           DC.B       0x00                     ; '\0'
+  0x08000029:  00           DC.B       0x00                     ; '\0'
+  0x0800002A:  00           DC.B       0x00                     ; '\0'
+  0x0800002B:  00           DC.B       0x00                     ; '\0'
+  0x0800002C:  0800580D     DC.W       SVC_Handler
+  0x08000030:  00           DC.B       0x00                     ; '\0'
+  0x08000031:  00           DC.B       0x00                     ; '\0'
+  0x08000032:  00           DC.B       0x00                     ; '\0'
+  0x08000033:  00           DC.B       0x00                     ; '\0'
+  0x08000034:  00           DC.B       0x00                     ; '\0'
+  0x08000035:  00           DC.B       0x00                     ; '\0'
+  0x08000036:  00           DC.B       0x00                     ; '\0'
+  0x08000037:  00           DC.B       0x00                     ; '\0'
+  0x08000038:  0800580F     DC.W       PendSV_Handler
+  0x0800003C:  080000B5     DC.W       SysTick_Handler
+  0x08000040:  0800589F     DC.W       WWDG_IRQHandler
+  0x08000044:  00           DC.B       0x00                     ; '\0'
+  0x08000045:  00           DC.B       0x00                     ; '\0'
+  0x08000046:  00           DC.B       0x00                     ; '\0'
+  0x08000047:  00           DC.B       0x00                     ; '\0'
+  0x08000048:  080058A1     DC.W       RTC_IRQHandler
+  0x0800004C:  080058A3     DC.W       FLASH_IRQHandler
+  0x08000050:  080058A5     DC.W       RCC_IRQHandler
+  0x08000054:  080058A7     DC.W       EXTI0_1_IRQHandler
+  0x08000058:  080058A9     DC.W       EXTI2_3_IRQHandler
+  0x0800005C:  080058AB     DC.W       EXTI4_15_IRQHandler
+  0x08000060:  00           DC.B       0x00                     ; '\0'
+  0x08000061:  00           DC.B       0x00                     ; '\0'
+  0x08000062:  00           DC.B       0x00                     ; '\0'
+  0x08000063:  00           DC.B       0x00                     ; '\0'
+  0x08000064:  080000C5     DC.W       DMA1_Channel1_IRQHandler
+  0x08000068:  080000D5     DC.W       DMA1_Channel2_3_IRQHandler
+  0x0800006C:  080058AD     DC.W       DMAMUX1_IRQHandler
+  0x08000070:  080058AF     DC.W       ADC1_IRQHandler
+  0x08000074:  080058B1     DC.W       TIM1_BRK_UP_TRG_COM_IRQHandler
+  0x08000078:  080058B3     DC.W       TIM1_CC_IRQHandler
+  0x0800007C:  00           DC.B       0x00                     ; '\0'
+  0x0800007D:  00           DC.B       0x00                     ; '\0'
+  0x0800007E:  00           DC.B       0x00                     ; '\0'
+  0x0800007F:  00           DC.B       0x00                     ; '\0'
+  0x08000080:  080058B5     DC.W       TIM3_IRQHandler
+  0x08000084:  00           DC.B       0x00                     ; '\0'
+  0x08000085:  00           DC.B       0x00                     ; '\0'
+  0x08000086:  00           DC.B       0x00                     ; '\0'
+  0x08000087:  00           DC.B       0x00                     ; '\0'
+  0x08000088:  00           DC.B       0x00                     ; '\0'
+  0x08000089:  00           DC.B       0x00                     ; '\0'
+  0x0800008A:  00           DC.B       0x00                     ; '\0'
+  0x0800008B:  00           DC.B       0x00                     ; '\0'
+  0x0800008C:  080058B7     DC.W       TIM14_IRQHandler
+  0x08000090:  00           DC.B       0x00                     ; '\0'
+  0x08000091:  00           DC.B       0x00                     ; '\0'
+  0x08000092:  00           DC.B       0x00                     ; '\0'
+  0x08000093:  00           DC.B       0x00                     ; '\0'
+  0x08000094:  080000ED     DC.W       TIM16_IRQHandler
+  0x08000098:  080058B9     DC.W       TIM17_IRQHandler
+  0x0800009C:  080058BB     DC.W       I2C1_IRQHandler
+  0x080000A0:  00           DC.B       0x00                     ; '\0'
+  0x080000A1:  00           DC.B       0x00                     ; '\0'
+  0x080000A2:  00           DC.B       0x00                     ; '\0'
+  0x080000A3:  00           DC.B       0x00                     ; '\0'
+  0x080000A4:  080058BD     DC.W       SPI1_IRQHandler
+  0x080000A8:  00           DC.B       0x00                     ; '\0'
+  0x080000A9:  00           DC.B       0x00                     ; '\0'
+  0x080000AA:  00           DC.B       0x00                     ; '\0'
+  0x080000AB:  00           DC.B       0x00                     ; '\0'
+  0x080000AC:  0800020D     DC.W       USART1_IRQHandler
+  0x080000B0:  080058BF     DC.W       USART2_IRQHandler
+
+

Section .text.SysTick_Handler from PowerPro_lto.o, size=16, align=4

+
+
SysTick_Handler:
+_vectors_end:
+  0x080000B4:  4802         LDR        R0, =uwTick              ; [PC, #8] [0x080000C0] =0x2000068C 
+  0x080000B6:  6801         LDR        R1, [R0]
+  0x080000B8:  1C49         ADDS       R1, R1, #1
+  0x080000BA:  6001         STR        R1, [R0]
+  0x080000BC:  4770         BX         LR
+  0x080000BE:  46C0         NOP
+  0x080000C0:  2000068C     DC.W       uwTick
+
+

Section .text.DMA1_Channel1_IRQHandler from PowerPro_lto.o, size=16, align=4

+
+
DMA1_Channel1_IRQHandler:
+  0x080000C4:  B580         PUSH       {R7, LR}
+  0x080000C6:  4802         LDR        R0, =hdma_adc1           ; [PC, #8] [0x080000D0] =0x2000056C 
+  0x080000C8:  F000 FD0E    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000CC:  BD80         POP        {R7, PC}
+  0x080000CE:  46C0         NOP
+  0x080000D0:  2000056C     DC.W       hdma_adc1
+
+

Section .text.DMA1_Channel2_3_IRQHandler from PowerPro_lto.o, size=24, align=4

+
+
DMA1_Channel2_3_IRQHandler:
+  0x080000D4:  B580         PUSH       {R7, LR}
+  0x080000D6:  4803         LDR        R0, =hdma_usart1_rx      ; [PC, #12] [0x080000E4] =0x20000510 
+  0x080000D8:  F000 FD06    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000DC:  4802         LDR        R0, =hdma_usart1_tx      ; [PC, #8] [0x080000E8] =0x200004B4 
+  0x080000DE:  F000 FD03    BL         HAL_DMA_IRQHandler       ; 0x08000AE8
+  0x080000E2:  BD80         POP        {R7, PC}
+  0x080000E4:  20000510     DC.W       hdma_usart1_rx
+  0x080000E8:  200004B4     DC.W       hdma_usart1_tx
+
+

Section .text.TIM16_IRQHandler from PowerPro_lto.o, size=288, align=4

+
+
TIM16_IRQHandler:
+  0x080000EC:  B5F0         PUSH       {R4-R7, LR}
+  0x080000EE:  B081         SUB        SP, SP, #4
+  0x080000F0:  4C40         LDR        R4, =htim16              ; [PC, #0x0100] [0x080001F4] =0x20000614 
+  0x080000F2:  6820         LDR        R0, [R4]
+  0x080000F4:  68C6         LDR        R6, [R0, #12]
+  0x080000F6:  6907         LDR        R7, [R0, #16]
+  0x080000F8:  07B9         LSLS       R1, R7, #30
+  0x080000FA:  4D3F         LDR        R5, =0xFFFFFEFF          ; [PC, #252] [0x080001F8] 
+  0x080000FC:  D50E         BPL        .L2                      ; 0x0800011C
+  0x080000FE:  07B1         LSLS       R1, R6, #30
+  0x08000100:  D50C         BPL        .L2                      ; 0x0800011C
+  0x08000102:  4629         MOV        R1, R5
+  0x08000104:  31FE         ADDS       R1, #254
+  0x08000106:  6101         STR        R1, [R0, #16]
+  0x08000108:  2101         MOVS       R1, #1
+  0x0800010A:  7721         STRB       R1, [R4, #28]
+  0x0800010C:  6980         LDR        R0, [R0, #24]
+  0x0800010E:  0780         LSLS       R0, R0, #30
+  0x08000110:  D002         BEQ        .L1                      ; 0x08000118
+  0x08000112:  4620         MOV        R0, R4
+  0x08000114:  F000 FA52    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L1:
+  0x08000118:  2000         MOVS       R0, #0
+  0x0800011A:  7720         STRB       R0, [R4, #28]
+
.L2:
+  0x0800011C:  0778         LSLS       R0, R7, #29
+  0x0800011E:  D510         BPL        .L4                      ; 0x08000142
+  0x08000120:  0770         LSLS       R0, R6, #29
+  0x08000122:  D50E         BPL        .L4                      ; 0x08000142
+  0x08000124:  6820         LDR        R0, [R4]
+  0x08000126:  4629         MOV        R1, R5
+  0x08000128:  31FC         ADDS       R1, #252
+  0x0800012A:  6101         STR        R1, [R0, #16]
+  0x0800012C:  2102         MOVS       R1, #2
+  0x0800012E:  7721         STRB       R1, [R4, #28]
+  0x08000130:  6980         LDR        R0, [R0, #24]
+  0x08000132:  0580         LSLS       R0, R0, #22
+  0x08000134:  0F80         LSRS       R0, R0, #30
+  0x08000136:  D002         BEQ        .L3                      ; 0x0800013E
+  0x08000138:  4620         MOV        R0, R4
+  0x0800013A:  F000 FA3F    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L3:
+  0x0800013E:  2000         MOVS       R0, #0
+  0x08000140:  7720         STRB       R0, [R4, #28]
+
.L4:
+  0x08000142:  0738         LSLS       R0, R7, #28
+  0x08000144:  D50F         BPL        .L6                      ; 0x08000166
+  0x08000146:  0730         LSLS       R0, R6, #28
+  0x08000148:  D50D         BPL        .L6                      ; 0x08000166
+  0x0800014A:  6820         LDR        R0, [R4]
+  0x0800014C:  4629         MOV        R1, R5
+  0x0800014E:  31F8         ADDS       R1, #248
+  0x08000150:  6101         STR        R1, [R0, #16]
+  0x08000152:  2104         MOVS       R1, #4
+  0x08000154:  7721         STRB       R1, [R4, #28]
+  0x08000156:  69C0         LDR        R0, [R0, #28]
+  0x08000158:  0780         LSLS       R0, R0, #30
+  0x0800015A:  D002         BEQ        .L5                      ; 0x08000162
+  0x0800015C:  4620         MOV        R0, R4
+  0x0800015E:  F000 FA2D    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L5:
+  0x08000162:  2000         MOVS       R0, #0
+  0x08000164:  7720         STRB       R0, [R4, #28]
+
.L6:
+  0x08000166:  06F8         LSLS       R0, R7, #27
+  0x08000168:  D510         BPL        .L8                      ; 0x0800018C
+  0x0800016A:  06F0         LSLS       R0, R6, #27
+  0x0800016C:  D50E         BPL        .L8                      ; 0x0800018C
+  0x0800016E:  6820         LDR        R0, [R4]
+  0x08000170:  4629         MOV        R1, R5
+  0x08000172:  31F0         ADDS       R1, #240
+  0x08000174:  6101         STR        R1, [R0, #16]
+  0x08000176:  2108         MOVS       R1, #8
+  0x08000178:  7721         STRB       R1, [R4, #28]
+  0x0800017A:  69C0         LDR        R0, [R0, #28]
+  0x0800017C:  0580         LSLS       R0, R0, #22
+  0x0800017E:  0F80         LSRS       R0, R0, #30
+  0x08000180:  D002         BEQ        .L7                      ; 0x08000188
+  0x08000182:  4620         MOV        R0, R4
+  0x08000184:  F000 FA1A    BL         HAL_TIM_IC_CaptureCallback ; 0x080005BC
+
.L7:
+  0x08000188:  2000         MOVS       R0, #0
+  0x0800018A:  7720         STRB       R0, [R4, #28]
+
.L8:
+  0x0800018C:  07F8         LSLS       R0, R7, #31
+  0x0800018E:  D010         BEQ        .L9                      ; 0x080001B2
+  0x08000190:  07F0         LSLS       R0, R6, #31
+  0x08000192:  D00E         BEQ        .L9                      ; 0x080001B2
+  0x08000194:  6820         LDR        R0, [R4]
+  0x08000196:  4629         MOV        R1, R5
+  0x08000198:  31FF         ADDS       R1, #255
+  0x0800019A:  6101         STR        R1, [R0, #16]
+  0x0800019C:  4917         LDR        R1, =0x40014400          ; [PC, #92] [0x080001FC] 
+  0x0800019E:  4288         CMP        R0, R1
+  0x080001A0:  D107         BNE        .L9                      ; 0x080001B2
+  0x080001A2:  4817         LDR        R0, =ic_overflows        ; [PC, #92] [0x08000200] =0x200006DC 
+  0x080001A4:  6801         LDR        R1, [R0]
+  0x080001A6:  1C49         ADDS       R1, R1, #1
+  0x080001A8:  6001         STR        R1, [R0]
+  0x080001AA:  D202         BCS        .L9                      ; 0x080001B2
+  0x080001AC:  4815         LDR        R0, =frequency           ; [PC, #84] [0x08000204] =0x200006E0 
+  0x080001AE:  2100         MOVS       R1, #0
+  0x080001B0:  6001         STR        R1, [R0]
+
.L9:
+  0x080001B2:  2041         MOVS       R0, #65
+  0x080001B4:  01C0         LSLS       R0, R0, #7
+  0x080001B6:  4207         TST        R7, R0
+  0x080001B8:  D004         BEQ        .L10                     ; 0x080001C4
+  0x080001BA:  0630         LSLS       R0, R6, #24
+  0x080001BC:  D502         BPL        .L10                     ; 0x080001C4
+  0x080001BE:  6820         LDR        R0, [R4]
+  0x080001C0:  4911         LDR        R1, =0xFFFFDF7F          ; [PC, #68] [0x08000208] 
+  0x080001C2:  6101         STR        R1, [R0, #16]
+
.L10:
+  0x080001C4:  05F8         LSLS       R0, R7, #23
+  0x080001C6:  D503         BPL        .L11                     ; 0x080001D0
+  0x080001C8:  0630         LSLS       R0, R6, #24
+  0x080001CA:  D501         BPL        .L11                     ; 0x080001D0
+  0x080001CC:  6820         LDR        R0, [R4]
+  0x080001CE:  6105         STR        R5, [R0, #16]
+
.L11:
+  0x080001D0:  0678         LSLS       R0, R7, #25
+  0x080001D2:  D505         BPL        .L12                     ; 0x080001E0
+  0x080001D4:  0670         LSLS       R0, R6, #25
+  0x080001D6:  D503         BPL        .L12                     ; 0x080001E0
+  0x080001D8:  6820         LDR        R0, [R4]
+  0x080001DA:  4629         MOV        R1, R5
+  0x080001DC:  31C0         ADDS       R1, #192
+  0x080001DE:  6101         STR        R1, [R0, #16]
+
.L12:
+  0x080001E0:  06B8         LSLS       R0, R7, #26
+  0x080001E2:  D504         BPL        .L13                     ; 0x080001EE
+  0x080001E4:  06B0         LSLS       R0, R6, #26
+  0x080001E6:  D502         BPL        .L13                     ; 0x080001EE
+  0x080001E8:  6820         LDR        R0, [R4]
+  0x080001EA:  35E0         ADDS       R5, #224
+  0x080001EC:  6105         STR        R5, [R0, #16]
+
.L13:
+  0x080001EE:  B001         ADD        SP, SP, #4
+  0x080001F0:  BDF0         POP        {R4-R7, PC}
+  0x080001F2:  46C0         NOP
+  0x080001F4:  20000614     DC.W       htim16
+  0x080001F8:  FFFFFEFF     DC.W       0xFFFFFEFF
+  0x080001FC:  40014400     DC.W       0x40014400
+  0x08000200:  200006DC     DC.W       ic_overflows
+  0x08000204:  200006E0     DC.W       frequency
+  0x08000208:  FFFFDF7F     DC.W       0xFFFFDF7F
+
+

Section .text.USART1_IRQHandler from PowerPro_lto.o, size=944, align=4

+
+
USART1_IRQHandler:
+  0x0800020C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800020E:  B085         SUB        SP, SP, #20
+  0x08000210:  4CE3         LDR        R4, =huart1              ; [PC, #0x038C] [0x080005A0] =0x200003BC 
+  0x08000212:  2101         MOVS       R1, #1
+  0x08000214:  6820         LDR        R0, [R4]
+  0x08000216:  9104         STR        R1, [SP, #16]
+  0x08000218:  02CE         LSLS       R6, R1, #11
+  0x0800021A:  69C3         LDR        R3, [R0, #28]
+  0x0800021C:  4631         MOV        R1, R6
+  0x0800021E:  310F         ADDS       R1, #15
+  0x08000220:  420B         TST        R3, R1
+  0x08000222:  6801         LDR        R1, [R0]
+  0x08000224:  6882         LDR        R2, [R0, #8]
+  0x08000226:  D067         BEQ        .L7                      ; 0x080002F8
+  0x08000228:  9603         STR        R6, [SP, #12]
+  0x0800022A:  4FDE         LDR        R7, =0x04000120          ; [PC, #0x0378] [0x080005A4] 
+  0x0800022C:  400F         ANDS       R7, R1
+  0x0800022E:  9D04         LDR        R5, [SP, #16]
+  0x08000230:  072E         LSLS       R6, R5, #28
+  0x08000232:  9602         STR        R6, [SP, #8]
+  0x08000234:  1C76         ADDS       R6, R6, #1
+  0x08000236:  4016         ANDS       R6, R2
+  0x08000238:  19F7         ADDS       R7, R6, R7
+  0x0800023A:  D066         BEQ        .L8                      ; 0x0800030A
+  0x0800023C:  07DF         LSLS       R7, R3, #31
+  0x0800023E:  D009         BEQ        .L1                      ; 0x08000254
+  0x08000240:  05CF         LSLS       R7, R1, #23
+  0x08000242:  D507         BPL        .L1                      ; 0x08000254
+  0x08000244:  6205         STR        R5, [R0, #32]
+  0x08000246:  2590         MOVS       R5, #144
+  0x08000248:  9501         STR        R5, [SP, #4]
+  0x0800024A:  5967         LDR        R7, [R4, R5]
+  0x0800024C:  9D04         LDR        R5, [SP, #16]
+  0x0800024E:  432F         ORRS       R7, R5
+  0x08000250:  9D01         LDR        R5, [SP, #4]
+  0x08000252:  5167         STR        R7, [R4, R5]
+
.L1:
+  0x08000254:  079F         LSLS       R7, R3, #30
+  0x08000256:  D50A         BPL        .L2                      ; 0x0800026E
+  0x08000258:  07D7         LSLS       R7, R2, #31
+  0x0800025A:  D008         BEQ        .L2                      ; 0x0800026E
+  0x0800025C:  2702         MOVS       R7, #2
+  0x0800025E:  6207         STR        R7, [R0, #32]
+  0x08000260:  2790         MOVS       R7, #144
+  0x08000262:  9701         STR        R7, [SP, #4]
+  0x08000264:  59E5         LDR        R5, [R4, R7]
+  0x08000266:  2704         MOVS       R7, #4
+  0x08000268:  432F         ORRS       R7, R5
+  0x0800026A:  9D01         LDR        R5, [SP, #4]
+  0x0800026C:  5167         STR        R7, [R4, R5]
+
.L2:
+  0x0800026E:  075F         LSLS       R7, R3, #29
+  0x08000270:  D50B         BPL        .L3                      ; 0x0800028A
+  0x08000272:  07D7         LSLS       R7, R2, #31
+  0x08000274:  D009         BEQ        .L3                      ; 0x0800028A
+  0x08000276:  2704         MOVS       R7, #4
+  0x08000278:  6207         STR        R7, [R0, #32]
+  0x0800027A:  2590         MOVS       R5, #144
+  0x0800027C:  9500         STR        R5, [SP, #0]
+  0x0800027E:  5965         LDR        R5, [R4, R5]
+  0x08000280:  9501         STR        R5, [SP, #4]
+  0x08000282:  2702         MOVS       R7, #2
+  0x08000284:  432F         ORRS       R7, R5
+  0x08000286:  9D00         LDR        R5, [SP, #0]
+  0x08000288:  5167         STR        R7, [R4, R5]
+
.L3:
+  0x0800028A:  071F         LSLS       R7, R3, #28
+  0x0800028C:  D509         BPL        .L4                      ; 0x080002A2
+  0x0800028E:  2720         MOVS       R7, #32
+  0x08000290:  400F         ANDS       R7, R1
+  0x08000292:  433E         ORRS       R6, R7
+  0x08000294:  D005         BEQ        .L4                      ; 0x080002A2
+  0x08000296:  2508         MOVS       R5, #8
+  0x08000298:  6205         STR        R5, [R0, #32]
+  0x0800029A:  2790         MOVS       R7, #144
+  0x0800029C:  59E6         LDR        R6, [R4, R7]
+  0x0800029E:  432E         ORRS       R6, R5
+  0x080002A0:  51E6         STR        R6, [R4, R7]
+
.L4:
+  0x080002A2:  9F03         LDR        R7, [SP, #12]
+  0x080002A4:  423B         TST        R3, R7
+  0x080002A6:  D007         BEQ        .L5                      ; 0x080002B8
+  0x080002A8:  014E         LSLS       R6, R1, #5
+  0x080002AA:  D505         BPL        .L5                      ; 0x080002B8
+  0x080002AC:  6207         STR        R7, [R0, #32]
+  0x080002AE:  2690         MOVS       R6, #144
+  0x080002B0:  59A5         LDR        R5, [R4, R6]
+  0x080002B2:  2720         MOVS       R7, #32
+  0x080002B4:  432F         ORRS       R7, R5
+  0x080002B6:  51A7         STR        R7, [R4, R6]
+
.L5:
+  0x080002B8:  2690         MOVS       R6, #144
+  0x080002BA:  59A7         LDR        R7, [R4, R6]
+  0x080002BC:  2F00         CMP        R7, #0
+  0x080002BE:  D065         BEQ        .L17                     ; 0x0800038C
+  0x080002C0:  069B         LSLS       R3, R3, #26
+  0x080002C2:  D50B         BPL        .L6                      ; 0x080002DC
+  0x080002C4:  2320         MOVS       R3, #32
+  0x080002C6:  4019         ANDS       R1, R3
+  0x080002C8:  9B02         LDR        R3, [SP, #8]
+  0x080002CA:  401A         ANDS       R2, R3
+  0x080002CC:  430A         ORRS       R2, R1
+  0x080002CE:  D005         BEQ        .L6                      ; 0x080002DC
+  0x080002D0:  6F61         LDR        R1, [R4, #116]
+  0x080002D2:  2900         CMP        R1, #0
+  0x080002D4:  D002         BEQ        .L6                      ; 0x080002DC
+  0x080002D6:  4620         MOV        R0, R4
+  0x080002D8:  4788         BLX        R1
+  0x080002DA:  6820         LDR        R0, [R4]
+
.L6:
+  0x080002DC:  59A1         LDR        R1, [R4, R6]
+  0x080002DE:  2228         MOVS       R2, #40
+  0x080002E0:  400A         ANDS       R2, R1
+  0x080002E2:  6880         LDR        R0, [R0, #8]
+  0x080002E4:  2740         MOVS       R7, #64
+  0x080002E6:  4038         ANDS       R0, R7
+  0x080002E8:  1880         ADDS       R0, R0, R2
+  0x080002EA:  4620         MOV        R0, R4
+  0x080002EC:  D13D         BNE        .L13                     ; 0x0800036A
+  0x080002EE:  F004 F95F    BL         HAL_UART_ErrorCallback   ; 0x080045B0
+  0x080002F2:  2000         MOVS       R0, #0
+  0x080002F4:  51A0         STR        R0, [R4, R6]
+  0x080002F6:  E049         B          .L17                     ; 0x0800038C
+
.L7:
+  0x080002F8:  069E         LSLS       R6, R3, #26
+  0x080002FA:  D506         BPL        .L8                      ; 0x0800030A
+  0x080002FC:  2620         MOVS       R6, #32
+  0x080002FE:  400E         ANDS       R6, R1
+  0x08000300:  9D04         LDR        R5, [SP, #16]
+  0x08000302:  072F         LSLS       R7, R5, #28
+  0x08000304:  4017         ANDS       R7, R2
+  0x08000306:  19F6         ADDS       R6, R6, R7
+  0x08000308:  D13B         BNE        .L15                     ; 0x08000382
+
.L8:
+  0x0800030A:  6EE6         LDR        R6, [R4, #108]
+  0x0800030C:  2E01         CMP        R6, #1
+  0x0800030E:  D103         BNE        .L9                      ; 0x08000318
+  0x08000310:  06DE         LSLS       R6, R3, #27
+  0x08000312:  D501         BPL        .L9                      ; 0x08000318
+  0x08000314:  06CE         LSLS       R6, R1, #27
+  0x08000316:  D43B         BMI        .L18                     ; 0x08000390
+
.L9:
+  0x08000318:  02DE         LSLS       R6, R3, #11
+  0x0800031A:  D501         BPL        .L10                     ; 0x08000320
+  0x0800031C:  0256         LSLS       R6, R2, #9
+  0x0800031E:  D420         BMI        .L12                     ; 0x08000362
+
.L10:
+  0x08000320:  0618         LSLS       R0, R3, #24
+  0x08000322:  D506         BPL        .L11                     ; 0x08000332
+  0x08000324:  2080         MOVS       R0, #128
+  0x08000326:  4008         ANDS       R0, R1
+  0x08000328:  9D04         LDR        R5, [SP, #16]
+  0x0800032A:  05EE         LSLS       R6, R5, #23
+  0x0800032C:  4032         ANDS       R2, R6
+  0x0800032E:  1880         ADDS       R0, R0, R2
+  0x08000330:  D125         BNE        .L14                     ; 0x0800037E
+
.L11:
+  0x08000332:  0658         LSLS       R0, R3, #25
+  0x08000334:  D52A         BPL        .L17                     ; 0x0800038C
+  0x08000336:  0648         LSLS       R0, R1, #25
+  0x08000338:  D528         BPL        .L17                     ; 0x0800038C
+  0x0800033A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800033E:  9904         LDR        R1, [SP, #16]
+  0x08000340:  F381 8810    MSR        PRIMASK, R1
+  0x08000344:  6821         LDR        R1, [R4]
+  0x08000346:  680A         LDR        R2, [R1]
+  0x08000348:  2340         MOVS       R3, #64
+  0x0800034A:  439A         BICS       R2, R3
+  0x0800034C:  600A         STR        R2, [R1]
+  0x0800034E:  F380 8810    MSR        PRIMASK, R0
+  0x08000352:  2088         MOVS       R0, #136
+  0x08000354:  2120         MOVS       R1, #32
+  0x08000356:  5021         STR        R1, [R4, R0]
+  0x08000358:  4897         LDR        R0, =0x20000026          ; [PC, #0x025C] [0x080005B8] 
+  0x0800035A:  2100         MOVS       R1, #0
+  0x0800035C:  7001         STRB       R1, [R0]
+  0x0800035E:  67A1         STR        R1, [R4, #120]
+  0x08000360:  E014         B          .L17                     ; 0x0800038C
+
.L12:
+  0x08000362:  9904         LDR        R1, [SP, #16]
+  0x08000364:  0509         LSLS       R1, R1, #20
+  0x08000366:  6201         STR        R1, [R0, #32]
+  0x08000368:  E010         B          .L17                     ; 0x0800038C
+
.L13:
+  0x0800036A:  F001 F899    BL         UART_EndRxTransfer       ; 0x080014A0
+  0x0800036E:  6820         LDR        R0, [R4]
+  0x08000370:  6880         LDR        R0, [R0, #8]
+  0x08000372:  0640         LSLS       R0, R0, #25
+  0x08000374:  D446         BMI        .L21                     ; 0x08000404
+  0x08000376:  4620         MOV        R0, R4
+  0x08000378:  F004 F91A    BL         HAL_UART_ErrorCallback   ; 0x080045B0
+  0x0800037C:  E006         B          .L17                     ; 0x0800038C
+
.L14:
+  0x0800037E:  6FA1         LDR        R1, [R4, #120]
+  0x08000380:  E000         B          .L16                     ; 0x08000384
+
.L15:
+  0x08000382:  6F61         LDR        R1, [R4, #116]
+
.L16:
+  0x08000384:  2900         CMP        R1, #0
+  0x08000386:  D001         BEQ        .L17                     ; 0x0800038C
+  0x08000388:  4620         MOV        R0, R4
+  0x0800038A:  4788         BLX        R1
+
.L17:
+  0x0800038C:  B005         ADD        SP, SP, #20
+  0x0800038E:  BDF0         POP        {R4-R7, PC}
+
.L18:
+  0x08000390:  2110         MOVS       R1, #16
+  0x08000392:  6201         STR        R1, [R0, #32]
+  0x08000394:  6880         LDR        R0, [R0, #8]
+  0x08000396:  0640         LSLS       R0, R0, #25
+  0x08000398:  D500         BPL        .L19                     ; 0x0800039C
+  0x0800039A:  E076         B          .L25                     ; 0x0800048A
+
.L19:
+  0x0800039C:  235E         MOVS       R3, #94
+  0x0800039E:  5AE0         LDRH       R0, [R4, R3]
+  0x080003A0:  225C         MOVS       R2, #92
+  0x080003A2:  5AA2         LDRH       R2, [R4, R2]
+  0x080003A4:  5AE3         LDRH       R3, [R4, R3]
+  0x080003A6:  2B00         CMP        R3, #0
+  0x080003A8:  D0F0         BEQ        .L17                     ; 0x0800038C
+  0x080003AA:  4282         CMP        R2, R0
+  0x080003AC:  D0EE         BEQ        .L17                     ; 0x0800038C
+  0x080003AE:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003B2:  9D04         LDR        R5, [SP, #16]
+  0x080003B4:  F385 8810    MSR        PRIMASK, R5
+  0x080003B8:  4A7C         LDR        R2, =0xFFFFFEFF          ; [PC, #0x01F0] [0x080005AC] 
+  0x080003BA:  3A20         SUBS       R2, #32
+  0x080003BC:  6823         LDR        R3, [R4]
+  0x080003BE:  681E         LDR        R6, [R3]
+  0x080003C0:  4016         ANDS       R6, R2
+  0x080003C2:  601E         STR        R6, [R3]
+  0x080003C4:  F380 8810    MSR        PRIMASK, R0
+  0x080003C8:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003CC:  F385 8810    MSR        PRIMASK, R5
+  0x080003D0:  6822         LDR        R2, [R4]
+  0x080003D2:  6893         LDR        R3, [R2, #8]
+  0x080003D4:  4E77         LDR        R6, =0xEFFFFFFE          ; [PC, #0x01DC] [0x080005B4] 
+  0x080003D6:  401E         ANDS       R6, R3
+  0x080003D8:  6096         STR        R6, [R2, #8]
+  0x080003DA:  F380 8810    MSR        PRIMASK, R0
+  0x080003DE:  208C         MOVS       R0, #140
+  0x080003E0:  2220         MOVS       R2, #32
+  0x080003E2:  5022         STR        R2, [R4, R0]
+  0x080003E4:  2000         MOVS       R0, #0
+  0x080003E6:  6760         STR        R0, [R4, #116]
+  0x080003E8:  66E0         STR        R0, [R4, #108]
+  0x080003EA:  F3EF 8010    MRS        R0, PRIMASK
+  0x080003EE:  F385 8810    MSR        PRIMASK, R5
+  0x080003F2:  6822         LDR        R2, [R4]
+  0x080003F4:  6813         LDR        R3, [R2]
+  0x080003F6:  438B         BICS       R3, R1
+  0x080003F8:  6013         STR        R3, [R2]
+  0x080003FA:  F380 8810    MSR        PRIMASK, R0
+
.L20:
+  0x080003FE:  2002         MOVS       R0, #2
+  0x08000400:  6720         STR        R0, [R4, #112]
+  0x08000402:  E7C3         B          .L17                     ; 0x0800038C
+
.L21:
+  0x08000404:  F3EF 8010    MRS        R0, PRIMASK
+  0x08000408:  9904         LDR        R1, [SP, #16]
+  0x0800040A:  F381 8810    MSR        PRIMASK, R1
+  0x0800040E:  6821         LDR        R1, [R4]
+  0x08000410:  688A         LDR        R2, [R1, #8]
+  0x08000412:  43BA         BICS       R2, R7
+  0x08000414:  608A         STR        R2, [R1, #8]
+  0x08000416:  F380 8810    MSR        PRIMASK, R0
+  0x0800041A:  2080         MOVS       R0, #128
+  0x0800041C:  5820         LDR        R0, [R4, R0]
+  0x0800041E:  2800         CMP        R0, #0
+  0x08000420:  D100         BNE        .L22                     ; 0x08000424
+  0x08000422:  E0AC         B          .L31                     ; 0x0800057E
+
.L22:
+  0x08000424:  4601         MOV        R1, R0
+  0x08000426:  3124         ADDS       R1, #36
+  0x08000428:  9A04         LDR        R2, [SP, #16]
+  0x0800042A:  700A         STRB       R2, [R1]
+  0x0800042C:  4A5E         LDR        R2, =UART_DMAAbortOnError ; [PC, #0x0178] [0x080005A8] =0x08005EDB 
+  0x0800042E:  6382         STR        R2, [R0, #56]
+  0x08000430:  784A         LDRB       R2, [R1, #1]
+  0x08000432:  2A02         CMP        R2, #2
+  0x08000434:  D000         BEQ        .L23                     ; 0x08000438
+  0x08000436:  E0A6         B          .L32                     ; 0x08000586
+
.L23:
+  0x08000438:  6802         LDR        R2, [R0]
+  0x0800043A:  6813         LDR        R3, [R2]
+  0x0800043C:  240E         MOVS       R4, #14
+  0x0800043E:  43A3         BICS       R3, R4
+  0x08000440:  6013         STR        R3, [R2]
+  0x08000442:  6813         LDR        R3, [R2]
+  0x08000444:  9D04         LDR        R5, [SP, #16]
+  0x08000446:  43AB         BICS       R3, R5
+  0x08000448:  6013         STR        R3, [R2]
+  0x0800044A:  6C43         LDR        R3, [R0, #68]
+  0x0800044C:  681C         LDR        R4, [R3]
+  0x0800044E:  4A57         LDR        R2, =0xFFFFFEFF          ; [PC, #0x015C] [0x080005AC] 
+  0x08000450:  4014         ANDS       R4, R2
+  0x08000452:  601C         STR        R4, [R3]
+  0x08000454:  6C03         LDR        R3, [R0, #64]
+  0x08000456:  241C         MOVS       R4, #28
+  0x08000458:  401C         ANDS       R4, R3
+  0x0800045A:  462B         MOV        R3, R5
+  0x0800045C:  40A3         LSLS       R3, R4
+  0x0800045E:  4C54         LDR        R4, =0x40020004          ; [PC, #0x0150] [0x080005B0] 
+  0x08000460:  6826         LDR        R6, [R4]
+  0x08000462:  431E         ORRS       R6, R3
+  0x08000464:  6026         STR        R6, [R4]
+  0x08000466:  6C83         LDR        R3, [R0, #72]
+  0x08000468:  6CC4         LDR        R4, [R0, #76]
+  0x0800046A:  605C         STR        R4, [R3, #4]
+  0x0800046C:  6D03         LDR        R3, [R0, #80]
+  0x0800046E:  2B00         CMP        R3, #0
+  0x08000470:  D005         BEQ        .L24                     ; 0x0800047E
+  0x08000472:  681C         LDR        R4, [R3]
+  0x08000474:  4014         ANDS       R4, R2
+  0x08000476:  601C         STR        R4, [R3]
+  0x08000478:  6D42         LDR        R2, [R0, #84]
+  0x0800047A:  6D83         LDR        R3, [R0, #88]
+  0x0800047C:  6053         STR        R3, [R2, #4]
+
.L24:
+  0x0800047E:  2200         MOVS       R2, #0
+  0x08000480:  700A         STRB       R2, [R1]
+  0x08000482:  704D         STRB       R5, [R1, #1]
+  0x08000484:  F005 FD29    BL         UART_DMAAbortOnError     ; 0x08005EDA
+  0x08000488:  E780         B          .L17                     ; 0x0800038C
+
.L25:
+  0x0800048A:  205C         MOVS       R0, #92
+  0x0800048C:  5A20         LDRH       R0, [R4, R0]
+  0x0800048E:  2680         MOVS       R6, #128
+  0x08000490:  59A2         LDR        R2, [R4, R6]
+  0x08000492:  6812         LDR        R2, [R2]
+  0x08000494:  6853         LDR        R3, [R2, #4]
+  0x08000496:  B29F         UXTH       R7, R3
+  0x08000498:  2F00         CMP        R7, #0
+  0x0800049A:  D068         BEQ        .L28                     ; 0x0800056E
+  0x0800049C:  4287         CMP        R7, R0
+  0x0800049E:  D266         BCS        .L28                     ; 0x0800056E
+  0x080004A0:  275E         MOVS       R7, #94
+  0x080004A2:  53E3         STRH       R3, [R4, R7]
+  0x080004A4:  6812         LDR        R2, [R2]
+  0x080004A6:  0692         LSLS       R2, R2, #26
+  0x080004A8:  D500         BPL        .L26                     ; 0x080004AC
+  0x080004AA:  E074         B          .L35                     ; 0x08000596
+
.L26:
+  0x080004AC:  F3EF 8310    MRS        R3, PRIMASK
+  0x080004B0:  9D04         LDR        R5, [SP, #16]
+  0x080004B2:  F385 8810    MSR        PRIMASK, R5
+  0x080004B6:  9703         STR        R7, [SP, #12]
+  0x080004B8:  6827         LDR        R7, [R4]
+  0x080004BA:  683A         LDR        R2, [R7]
+  0x080004BC:  483B         LDR        R0, =0xFFFFFEFF          ; [PC, #236] [0x080005AC] 
+  0x080004BE:  4002         ANDS       R2, R0
+  0x080004C0:  603A         STR        R2, [R7]
+  0x080004C2:  F383 8810    MSR        PRIMASK, R3
+  0x080004C6:  F3EF 8210    MRS        R2, PRIMASK
+  0x080004CA:  F385 8810    MSR        PRIMASK, R5
+  0x080004CE:  6823         LDR        R3, [R4]
+  0x080004D0:  689F         LDR        R7, [R3, #8]
+  0x080004D2:  43AF         BICS       R7, R5
+  0x080004D4:  609F         STR        R7, [R3, #8]
+  0x080004D6:  F382 8810    MSR        PRIMASK, R2
+  0x080004DA:  F3EF 8210    MRS        R2, PRIMASK
+  0x080004DE:  F385 8810    MSR        PRIMASK, R5
+  0x080004E2:  6823         LDR        R3, [R4]
+  0x080004E4:  689F         LDR        R7, [R3, #8]
+  0x080004E6:  2040         MOVS       R0, #64
+  0x080004E8:  4387         BICS       R7, R0
+  0x080004EA:  609F         STR        R7, [R3, #8]
+  0x080004EC:  F382 8810    MSR        PRIMASK, R2
+  0x080004F0:  208C         MOVS       R0, #140
+  0x080004F2:  2220         MOVS       R2, #32
+  0x080004F4:  5022         STR        R2, [R4, R0]
+  0x080004F6:  2300         MOVS       R3, #0
+  0x080004F8:  66E3         STR        R3, [R4, #108]
+  0x080004FA:  F3EF 8010    MRS        R0, PRIMASK
+  0x080004FE:  F385 8810    MSR        PRIMASK, R5
+  0x08000502:  6822         LDR        R2, [R4]
+  0x08000504:  6817         LDR        R7, [R2]
+  0x08000506:  438F         BICS       R7, R1
+  0x08000508:  6017         STR        R7, [R2]
+  0x0800050A:  9F03         LDR        R7, [SP, #12]
+  0x0800050C:  F380 8810    MSR        PRIMASK, R0
+  0x08000510:  59A6         LDR        R6, [R4, R6]
+  0x08000512:  2E00         CMP        R6, #0
+  0x08000514:  D03F         BEQ        .L35                     ; 0x08000596
+  0x08000516:  4631         MOV        R1, R6
+  0x08000518:  3124         ADDS       R1, #36
+  0x0800051A:  7848         LDRB       R0, [R1, #1]
+  0x0800051C:  2802         CMP        R0, #2
+  0x0800051E:  D137         BNE        .L33                     ; 0x08000590
+  0x08000520:  9302         STR        R3, [SP, #8]
+  0x08000522:  6830         LDR        R0, [R6]
+  0x08000524:  6802         LDR        R2, [R0]
+  0x08000526:  270E         MOVS       R7, #14
+  0x08000528:  43BA         BICS       R2, R7
+  0x0800052A:  6002         STR        R2, [R0]
+  0x0800052C:  6C72         LDR        R2, [R6, #68]
+  0x0800052E:  6817         LDR        R7, [R2]
+  0x08000530:  4B1E         LDR        R3, =0xFFFFFEFF          ; [PC, #120] [0x080005AC] 
+  0x08000532:  401F         ANDS       R7, R3
+  0x08000534:  6017         STR        R7, [R2]
+  0x08000536:  6802         LDR        R2, [R0]
+  0x08000538:  43AA         BICS       R2, R5
+  0x0800053A:  6002         STR        R2, [R0]
+  0x0800053C:  6C30         LDR        R0, [R6, #64]
+  0x0800053E:  221C         MOVS       R2, #28
+  0x08000540:  4002         ANDS       R2, R0
+  0x08000542:  4628         MOV        R0, R5
+  0x08000544:  4090         LSLS       R0, R2
+  0x08000546:  4A1A         LDR        R2, =0x40020004          ; [PC, #104] [0x080005B0] 
+  0x08000548:  6817         LDR        R7, [R2]
+  0x0800054A:  4307         ORRS       R7, R0
+  0x0800054C:  6017         STR        R7, [R2]
+  0x0800054E:  6CB0         LDR        R0, [R6, #72]
+  0x08000550:  6CF2         LDR        R2, [R6, #76]
+  0x08000552:  6042         STR        R2, [R0, #4]
+  0x08000554:  6D37         LDR        R7, [R6, #80]
+  0x08000556:  2F00         CMP        R7, #0
+  0x08000558:  D005         BEQ        .L27                     ; 0x08000566
+  0x0800055A:  6838         LDR        R0, [R7]
+  0x0800055C:  4018         ANDS       R0, R3
+  0x0800055E:  6038         STR        R0, [R7]
+  0x08000560:  6D70         LDR        R0, [R6, #84]
+  0x08000562:  6DB2         LDR        R2, [R6, #88]
+  0x08000564:  6042         STR        R2, [R0, #4]
+
.L27:
+  0x08000566:  704D         STRB       R5, [R1, #1]
+  0x08000568:  9F03         LDR        R7, [SP, #12]
+  0x0800056A:  9B02         LDR        R3, [SP, #8]
+  0x0800056C:  E012         B          .L34                     ; 0x08000594
+
.L28:
+  0x0800056E:  42B8         CMP        R0, R7
+  0x08000570:  D000         BEQ        .L29                     ; 0x08000574
+  0x08000572:  E70B         B          .L17                     ; 0x0800038C
+
.L29:
+  0x08000574:  6810         LDR        R0, [R2]
+  0x08000576:  0680         LSLS       R0, R0, #26
+  0x08000578:  D400         BMI        .L30                     ; 0x0800057C
+  0x0800057A:  E707         B          .L17                     ; 0x0800038C
+
.L30:
+  0x0800057C:  E73F         B          .L20                     ; 0x080003FE
+
.L31:
+  0x0800057E:  4808         LDR        R0, =huart1              ; [PC, #32] [0x080005A0] =0x200003BC 
+  0x08000580:  F004 F816    BL         HAL_UART_ErrorCallback   ; 0x080045B0
+  0x08000584:  E702         B          .L17                     ; 0x0800038C
+
.L32:
+  0x08000586:  2104         MOVS       R1, #4
+  0x08000588:  63C1         STR        R1, [R0, #60]
+  0x0800058A:  F005 FCA6    BL         UART_DMAAbortOnError     ; 0x08005EDA
+  0x0800058E:  E6FD         B          .L17                     ; 0x0800038C
+
.L33:
+  0x08000590:  2004         MOVS       R0, #4
+  0x08000592:  63F0         STR        R0, [R6, #60]
+
.L34:
+  0x08000594:  700B         STRB       R3, [R1]
+
.L35:
+  0x08000596:  2002         MOVS       R0, #2
+  0x08000598:  6720         STR        R0, [R4, #112]
+  0x0800059A:  5BE0         LDRH       R0, [R4, R7]
+  0x0800059C:  E6F6         B          .L17                     ; 0x0800038C
+  0x0800059E:  46C0         NOP
+  0x080005A0:  200003BC     DC.W       huart1
+  0x080005A4:  04000120     DC.W       0x04000120
+  0x080005A8:  08005EDB     DC.W       UART_DMAAbortOnError
+  0x080005AC:  FFFFFEFF     DC.W       0xFFFFFEFF
+  0x080005B0:  40020004     DC.W       0x40020004
+  0x080005B4:  EFFFFFFE     DC.W       0xEFFFFFFE
+  0x080005B8:  20000026     DC.W       20000026               ; R_ARM_ABS32
+
+

Section .text.HAL_TIM_IC_CaptureCallback from PowerPro_lto.o, size=56, align=4

+
+
HAL_TIM_IC_CaptureCallback:
+  0x080005BC:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080005BE:  4605         MOV        R5, R0
+  0x080005C0:  7F00         LDRB       R0, [R0, #28]
+  0x080005C2:  2801         CMP        R0, #1
+  0x080005C4:  D111         BNE        .L1                      ; 0x080005EA
+  0x080005C6:  6828         LDR        R0, [R5]
+  0x080005C8:  6B44         LDR        R4, [R0, #52]
+  0x080005CA:  F000 FBFF    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x080005CE:  4907         LDR        R1, =ic_overflows        ; [PC, #28] [0x080005EC] =0x200006DC 
+  0x080005D0:  2200         MOVS       R2, #0
+  0x080005D2:  600A         STR        R2, [R1]
+  0x080005D4:  6829         LDR        R1, [R5]
+  0x080005D6:  6A8B         LDR        R3, [R1, #40]
+  0x080005D8:  624A         STR        R2, [R1, #36]
+  0x080005DA:  1C59         ADDS       R1, R3, #1
+  0x080005DC:  F005 FD53    BL         __aeabi_uidiv            ; 0x08006086
+  0x080005E0:  4621         MOV        R1, R4
+  0x080005E2:  F005 FD50    BL         __aeabi_uidiv            ; 0x08006086
+  0x080005E6:  4902         LDR        R1, =frequency           ; [PC, #8] [0x080005F0] =0x200006E0 
+  0x080005E8:  6008         STR        R0, [R1]
+
.L1:
+  0x080005EA:  BDB0         POP        {R4-R5, R7, PC}
+  0x080005EC:  200006DC     DC.W       ic_overflows
+  0x080005F0:  200006E0     DC.W       frequency
+
+

Section .text.SystemInit from PowerPro_lto.o, size=16, align=4

+
+
SystemInit:
+  0x080005F4:  2001         MOVS       R0, #1
+  0x080005F6:  06C0         LSLS       R0, R0, #27
+  0x080005F8:  4901         LDR        R1, =0xE000ED08          ; [PC, #4] [0x08000600] 
+  0x080005FA:  6008         STR        R0, [R1]
+  0x080005FC:  4770         BX         LR
+  0x080005FE:  46C0         NOP
+  0x08000600:  E000ED08     DC.W       0xE000ED08
+
+

Section .text.SystemCoreClockUpdate from PowerPro_lto.o, size=80, align=4

+
+
SystemCoreClockUpdate:
+  0x08000604:  490F         LDR        R1, =0x40021000          ; [PC, #60] [0x08000644] 
+  0x08000606:  6888         LDR        R0, [R1, #8]
+  0x08000608:  0680         LSLS       R0, R0, #26
+  0x0800060A:  0F42         LSRS       R2, R0, #29
+  0x0800060C:  480E         LDR        R0, =0x02DC6C00          ; [PC, #56] [0x08000648] 
+  0x0800060E:  2A01         CMP        R2, #1
+  0x08000610:  D00D         BEQ        .L3                      ; 0x0800062E
+  0x08000612:  2A04         CMP        R2, #4
+  0x08000614:  D004         BEQ        .L1                      ; 0x08000620
+  0x08000616:  2A03         CMP        R2, #3
+  0x08000618:  D105         BNE        .L2                      ; 0x08000626
+  0x0800061A:  207D         MOVS       R0, #125
+  0x0800061C:  0200         LSLS       R0, R0, #8
+  0x0800061E:  E006         B          .L3                      ; 0x0800062E
+
.L1:
+  0x08000620:  2001         MOVS       R0, #1
+  0x08000622:  03C0         LSLS       R0, R0, #15
+  0x08000624:  E003         B          .L3                      ; 0x0800062E
+
.L2:
+  0x08000626:  680A         LDR        R2, [R1]
+  0x08000628:  0492         LSLS       R2, R2, #18
+  0x0800062A:  0F52         LSRS       R2, R2, #29
+  0x0800062C:  40D0         LSRS       R0, R2
+
.L3:
+  0x0800062E:  4A07         LDR        R2, =SystemCoreClock     ; [PC, #28] [0x0800064C] =0x20000BA4 
+  0x08000630:  6010         STR        R0, [R2]
+  0x08000632:  6889         LDR        R1, [R1, #8]
+  0x08000634:  0989         LSRS       R1, R1, #6
+  0x08000636:  233C         MOVS       R3, #60
+  0x08000638:  400B         ANDS       R3, R1
+  0x0800063A:  4905         LDR        R1, =AHBPrescTable       ; [PC, #20] [0x08000650] =0x08005160 
+  0x0800063C:  58C9         LDR        R1, [R1, R3]
+  0x0800063E:  40C8         LSRS       R0, R1
+  0x08000640:  6010         STR        R0, [R2]
+  0x08000642:  4770         BX         LR
+  0x08000644:  40021000     DC.W       0x40021000
+  0x08000648:  02DC6C00     DC.W       0x02DC6C00
+  0x0800064C:  20000BA4     DC.W       SystemCoreClock
+  0x08000650:  08005160     DC.W       AHBPrescTable
+
+

Section .text.HAL_InitTick from PowerPro_lto.o, size=96, align=4

+
+
HAL_InitTick:
+  0x08000654:  B5F0         PUSH       {R4-R7, LR}
+  0x08000656:  B081         SUB        SP, SP, #4
+  0x08000658:  4604         MOV        R4, R0
+  0x0800065A:  4811         LDR        R0, =SystemCoreClock     ; [PC, #68] [0x080006A0] =0x20000BA4 
+  0x0800065C:  6800         LDR        R0, [R0]
+  0x0800065E:  217D         MOVS       R1, #125
+  0x08000660:  00C9         LSLS       R1, R1, #3
+  0x08000662:  F005 FD10    BL         __aeabi_uidiv            ; 0x08006086
+  0x08000666:  1E42         SUBS       R2, R0, #1
+  0x08000668:  2001         MOVS       R0, #1
+  0x0800066A:  0E11         LSRS       R1, R2, #24
+  0x0800066C:  D116         BNE        .L1                      ; 0x0800069C
+  0x0800066E:  490D         LDR        R1, =0x00FFFFFF          ; [PC, #52] [0x080006A4] 
+  0x08000670:  4E0D         LDR        R6, =0xE000E010          ; [PC, #52] [0x080006A8] 
+  0x08000672:  6072         STR        R2, [R6, #4]
+  0x08000674:  4A0D         LDR        R2, =0xE000ED20          ; [PC, #52] [0x080006AC] 
+  0x08000676:  6813         LDR        R3, [R2]
+  0x08000678:  400B         ANDS       R3, R1
+  0x0800067A:  2503         MOVS       R5, #3
+  0x0800067C:  07AD         LSLS       R5, R5, #30
+  0x0800067E:  195B         ADDS       R3, R3, R5
+  0x08000680:  6013         STR        R3, [R2]
+  0x08000682:  2300         MOVS       R3, #0
+  0x08000684:  60B3         STR        R3, [R6, #8]
+  0x08000686:  2707         MOVS       R7, #7
+  0x08000688:  6037         STR        R7, [R6]
+  0x0800068A:  2C03         CMP        R4, #3
+  0x0800068C:  D806         BHI        .L1                      ; 0x0800069C
+  0x0800068E:  6810         LDR        R0, [R2]
+  0x08000690:  4008         ANDS       R0, R1
+  0x08000692:  4328         ORRS       R0, R5
+  0x08000694:  6010         STR        R0, [R2]
+  0x08000696:  4806         LDR        R0, =uwTickPrio          ; [PC, #24] [0x080006B0] =0x20000B94 
+  0x08000698:  6004         STR        R4, [R0]
+  0x0800069A:  2000         MOVS       R0, #0
+
.L1:
+  0x0800069C:  B001         ADD        SP, SP, #4
+  0x0800069E:  BDF0         POP        {R4-R7, PC}
+  0x080006A0:  20000BA4     DC.W       SystemCoreClock
+  0x080006A4:  00FFFFFF     DC.W       0x00FFFFFF
+  0x080006A8:  E000E010     DC.W       0xE000E010
+  0x080006AC:  E000ED20     DC.W       0xE000ED20
+  0x080006B0:  20000B94     DC.W       uwTickPrio
+
+

Section .text.HAL_Delay from PowerPro_lto.o, size=20, align=4

+
+
HAL_Delay:
+  0x080006B4:  4903         LDR        R1, =uwTick              ; [PC, #12] [0x080006C4] =0x2000068C 
+  0x080006B6:  680A         LDR        R2, [R1]
+
.L1:
+  0x080006B8:  680B         LDR        R3, [R1]
+  0x080006BA:  1A9B         SUBS       R3, R3, R2
+  0x080006BC:  4283         CMP        R3, R0
+  0x080006BE:  D9FB         BLS        .L1                      ; 0x080006B8
+  0x080006C0:  4770         BX         LR
+  0x080006C2:  46C0         NOP
+  0x080006C4:  2000068C     DC.W       uwTick
+
+

Section .text.HAL_ADC_ConfigChannel from PowerPro_lto.o, size=608, align=4

+
+
HAL_ADC_ConfigChannel:
+  0x080006C8:  B5F0         PUSH       {R4-R7, LR}
+  0x080006CA:  B089         SUB        SP, SP, #36
+  0x080006CC:  2500         MOVS       R5, #0
+  0x080006CE:  9508         STR        R5, [SP, #32]
+  0x080006D0:  2654         MOVS       R6, #84
+  0x080006D2:  4F8C         LDR        R7, =hadc1               ; [PC, #0x0230] [0x08000904] =0x20000450 
+  0x080006D4:  5DB9         LDRB       R1, [R7, R6]
+  0x080006D6:  2901         CMP        R1, #1
+  0x080006D8:  D101         BNE        .L1                      ; 0x080006DE
+  0x080006DA:  2402         MOVS       R4, #2
+  0x080006DC:  E102         B          .L38                     ; 0x080008E4
+
.L1:
+  0x080006DE:  2401         MOVS       R4, #1
+  0x080006E0:  55BC         STRB       R4, [R7, R6]
+  0x080006E2:  6839         LDR        R1, [R7]
+  0x080006E4:  688A         LDR        R2, [R1, #8]
+  0x080006E6:  0752         LSLS       R2, R2, #29
+  0x080006E8:  D422         BMI        .L5                      ; 0x08000730
+  0x080006EA:  9507         STR        R5, [SP, #28]
+  0x080006EC:  693B         LDR        R3, [R7, #16]
+  0x080006EE:  6844         LDR        R4, [R0, #4]
+  0x080006F0:  2C02         CMP        R4, #2
+  0x080006F2:  4D86         LDR        R5, =0x80000004          ; [PC, #0x0218] [0x0800090C] 
+  0x080006F4:  D121         BNE        .L6                      ; 0x0800073A
+  0x080006F6:  2204         MOVS       R2, #4
+  0x080006F8:  4313         ORRS       R3, R2
+  0x080006FA:  42AB         CMP        R3, R5
+  0x080006FC:  6802         LDR        R2, [R0]
+  0x080006FE:  D106         BNE        .L2                      ; 0x0800070E
+  0x08000700:  4881         LDR        R0, =0x007FFFFF          ; [PC, #0x0204] [0x08000908] 
+  0x08000702:  43C0         MVNS       R0, R0
+  0x08000704:  43D3         MVNS       R3, R2
+  0x08000706:  4303         ORRS       R3, R0
+  0x08000708:  6A88         LDR        R0, [R1, #40]
+  0x0800070A:  4018         ANDS       R0, R3
+  0x0800070C:  6288         STR        R0, [R1, #40]
+
.L2:
+  0x0800070E:  9D07         LDR        R5, [SP, #28]
+  0x08000710:  2400         MOVS       R4, #0
+  0x08000712:  2A00         CMP        R2, #0
+  0x08000714:  D400         BMI        .L3                      ; 0x08000718
+  0x08000716:  E0E4         B          .L37                     ; 0x080008E2
+
.L3:
+  0x08000718:  487E         LDR        R0, =0x40012708          ; [PC, #0x01F8] [0x08000914] 
+  0x0800071A:  6801         LDR        R1, [R0]
+  0x0800071C:  4B7F         LDR        R3, =0xA8000400          ; [PC, #0x01FC] [0x0800091C] 
+  0x0800071E:  429A         CMP        R2, R3
+  0x08000720:  D064         BEQ        .L14                     ; 0x080007EC
+  0x08000722:  4B7D         LDR        R3, =0xA4000200          ; [PC, #0x01F4] [0x08000918] 
+  0x08000724:  429A         CMP        R2, R3
+  0x08000726:  D000         BEQ        .L4                      ; 0x0800072A
+  0x08000728:  E0DB         B          .L37                     ; 0x080008E2
+
.L4:
+  0x0800072A:  2201         MOVS       R2, #1
+  0x0800072C:  0592         LSLS       R2, R2, #22
+  0x0800072E:  E05F         B          .L15                     ; 0x080007F0
+
.L5:
+  0x08000730:  6DB8         LDR        R0, [R7, #88]
+  0x08000732:  2120         MOVS       R1, #32
+  0x08000734:  4301         ORRS       R1, R0
+  0x08000736:  65B9         STR        R1, [R7, #88]
+  0x08000738:  E0D3         B          .L37                     ; 0x080008E2
+
.L6:
+  0x0800073A:  2204         MOVS       R2, #4
+  0x0800073C:  4313         ORRS       R3, R2
+  0x0800073E:  42AB         CMP        R3, R5
+  0x08000740:  4D71         LDR        R5, =0x007FFFFF          ; [PC, #0x01C4] [0x08000908] 
+  0x08000742:  6803         LDR        R3, [R0]
+  0x08000744:  D105         BNE        .L7                      ; 0x08000752
+  0x08000746:  461A         MOV        R2, R3
+  0x08000748:  402A         ANDS       R2, R5
+  0x0800074A:  6A8C         LDR        R4, [R1, #40]
+  0x0800074C:  4314         ORRS       R4, R2
+  0x0800074E:  628C         STR        R4, [R1, #40]
+  0x08000750:  E087         B          .L33                     ; 0x08000862
+
.L7:
+  0x08000752:  9604         STR        R6, [SP, #16]
+  0x08000754:  9201         STR        R2, [SP, #4]
+  0x08000756:  4622         MOV        R2, R4
+  0x08000758:  241F         MOVS       R4, #31
+  0x0800075A:  9205         STR        R2, [SP, #20]
+  0x0800075C:  4014         ANDS       R4, R2
+  0x0800075E:  220F         MOVS       R2, #15
+  0x08000760:  9200         STR        R2, [SP, #0]
+  0x08000762:  9406         STR        R4, [SP, #24]
+  0x08000764:  40A2         LSLS       R2, R4
+  0x08000766:  6E3C         LDR        R4, [R7, #96]
+  0x08000768:  9203         STR        R2, [SP, #12]
+  0x0800076A:  4394         BICS       R4, R2
+  0x0800076C:  422B         TST        R3, R5
+  0x0800076E:  9402         STR        R4, [SP, #8]
+  0x08000770:  9E05         LDR        R6, [SP, #20]
+  0x08000772:  D045         BEQ        .L16                     ; 0x08000800
+  0x08000774:  4622         MOV        R2, R4
+  0x08000776:  07DD         LSLS       R5, R3, #31
+  0x08000778:  9D07         LDR        R5, [SP, #28]
+  0x0800077A:  D15F         BNE        .L31                     ; 0x0800083C
+  0x0800077C:  079D         LSLS       R5, R3, #30
+  0x0800077E:  D443         BMI        .L17                     ; 0x08000808
+  0x08000780:  075D         LSLS       R5, R3, #29
+  0x08000782:  D443         BMI        .L18                     ; 0x0800080C
+  0x08000784:  071D         LSLS       R5, R3, #28
+  0x08000786:  D443         BMI        .L19                     ; 0x08000810
+  0x08000788:  06DD         LSLS       R5, R3, #27
+  0x0800078A:  9D01         LDR        R5, [SP, #4]
+  0x0800078C:  D456         BMI        .L31                     ; 0x0800083C
+  0x0800078E:  069A         LSLS       R2, R3, #26
+  0x08000790:  D440         BMI        .L20                     ; 0x08000814
+  0x08000792:  065A         LSLS       R2, R3, #25
+  0x08000794:  D440         BMI        .L21                     ; 0x08000818
+  0x08000796:  061A         LSLS       R2, R3, #24
+  0x08000798:  D440         BMI        .L22                     ; 0x0800081C
+  0x0800079A:  05DA         LSLS       R2, R3, #23
+  0x0800079C:  D440         BMI        .L23                     ; 0x08000820
+  0x0800079E:  059A         LSLS       R2, R3, #22
+  0x080007A0:  D440         BMI        .L24                     ; 0x08000824
+  0x080007A2:  055A         LSLS       R2, R3, #21
+  0x080007A4:  D440         BMI        .L25                     ; 0x08000828
+  0x080007A6:  051A         LSLS       R2, R3, #20
+  0x080007A8:  D440         BMI        .L26                     ; 0x0800082C
+  0x080007AA:  04DA         LSLS       R2, R3, #19
+  0x080007AC:  D440         BMI        .L27                     ; 0x08000830
+  0x080007AE:  049A         LSLS       R2, R3, #18
+  0x080007B0:  D440         BMI        .L28                     ; 0x08000834
+  0x080007B2:  045A         LSLS       R2, R3, #17
+  0x080007B4:  D440         BMI        .L29                     ; 0x08000838
+  0x080007B6:  041A         LSLS       R2, R3, #16
+  0x080007B8:  9D00         LDR        R5, [SP, #0]
+  0x080007BA:  9A02         LDR        R2, [SP, #8]
+  0x080007BC:  D43E         BMI        .L31                     ; 0x0800083C
+  0x080007BE:  03DA         LSLS       R2, R3, #15
+  0x080007C0:  D500         BPL        .L8                      ; 0x080007C4
+  0x080007C2:  E092         B          .L39                     ; 0x080008EA
+
.L8:
+  0x080007C4:  039A         LSLS       R2, R3, #14
+  0x080007C6:  D500         BPL        .L9                      ; 0x080007CA
+  0x080007C8:  E091         B          .L40                     ; 0x080008EE
+
.L9:
+  0x080007CA:  035A         LSLS       R2, R3, #13
+  0x080007CC:  D500         BPL        .L10                     ; 0x080007D0
+  0x080007CE:  E090         B          .L41                     ; 0x080008F2
+
.L10:
+  0x080007D0:  031A         LSLS       R2, R3, #12
+  0x080007D2:  D500         BPL        .L11                     ; 0x080007D6
+  0x080007D4:  E08F         B          .L42                     ; 0x080008F6
+
.L11:
+  0x080007D6:  02DA         LSLS       R2, R3, #11
+  0x080007D8:  D500         BPL        .L12                     ; 0x080007DC
+  0x080007DA:  E08E         B          .L43                     ; 0x080008FA
+
.L12:
+  0x080007DC:  029A         LSLS       R2, R3, #10
+  0x080007DE:  D500         BPL        .L13                     ; 0x080007E2
+  0x080007E0:  E08D         B          .L44                     ; 0x080008FE
+
.L13:
+  0x080007E2:  025A         LSLS       R2, R3, #9
+  0x080007E4:  17D2         ASRS       R2, R2, #31
+  0x080007E6:  2516         MOVS       R5, #22
+  0x080007E8:  4015         ANDS       R5, R2
+  0x080007EA:  E026         B          .L30                     ; 0x0800083A
+
.L14:
+  0x080007EC:  4A46         LDR        R2, =0x007FFFFF          ; [PC, #0x0118] [0x08000908] 
+  0x080007EE:  1C52         ADDS       R2, R2, #1
+
.L15:
+  0x080007F0:  4011         ANDS       R1, R2
+  0x080007F2:  2203         MOVS       R2, #3
+  0x080007F4:  0592         LSLS       R2, R2, #22
+  0x080007F6:  6803         LDR        R3, [R0]
+  0x080007F8:  4393         BICS       R3, R2
+  0x080007FA:  1859         ADDS       R1, R3, R1
+  0x080007FC:  6001         STR        R1, [R0]
+  0x080007FE:  E070         B          .L37                     ; 0x080008E2
+
.L16:
+  0x08000800:  005A         LSLS       R2, R3, #1
+  0x08000802:  0ED5         LSRS       R5, R2, #27
+  0x08000804:  4622         MOV        R2, R4
+  0x08000806:  E019         B          .L31                     ; 0x0800083C
+
.L17:
+  0x08000808:  2501         MOVS       R5, #1
+  0x0800080A:  E017         B          .L31                     ; 0x0800083C
+
.L18:
+  0x0800080C:  2502         MOVS       R5, #2
+  0x0800080E:  E015         B          .L31                     ; 0x0800083C
+
.L19:
+  0x08000810:  2503         MOVS       R5, #3
+  0x08000812:  E013         B          .L31                     ; 0x0800083C
+
.L20:
+  0x08000814:  2505         MOVS       R5, #5
+  0x08000816:  E010         B          .L30                     ; 0x0800083A
+
.L21:
+  0x08000818:  2506         MOVS       R5, #6
+  0x0800081A:  E00E         B          .L30                     ; 0x0800083A
+
.L22:
+  0x0800081C:  2507         MOVS       R5, #7
+  0x0800081E:  E00C         B          .L30                     ; 0x0800083A
+
.L23:
+  0x08000820:  2508         MOVS       R5, #8
+  0x08000822:  E00A         B          .L30                     ; 0x0800083A
+
.L24:
+  0x08000824:  2509         MOVS       R5, #9
+  0x08000826:  E008         B          .L30                     ; 0x0800083A
+
.L25:
+  0x08000828:  250A         MOVS       R5, #10
+  0x0800082A:  E006         B          .L30                     ; 0x0800083A
+
.L26:
+  0x0800082C:  250B         MOVS       R5, #11
+  0x0800082E:  E004         B          .L30                     ; 0x0800083A
+
.L27:
+  0x08000830:  250C         MOVS       R5, #12
+  0x08000832:  E002         B          .L30                     ; 0x0800083A
+
.L28:
+  0x08000834:  250D         MOVS       R5, #13
+  0x08000836:  E000         B          .L30                     ; 0x0800083A
+
.L29:
+  0x08000838:  250E         MOVS       R5, #14
+
.L30:
+  0x0800083A:  9A02         LDR        R2, [SP, #8]
+
.L31:
+  0x0800083C:  9C06         LDR        R4, [SP, #24]
+  0x0800083E:  40A5         LSLS       R5, R4
+  0x08000840:  4315         ORRS       R5, R2
+  0x08000842:  663D         STR        R5, [R7, #96]
+  0x08000844:  08B2         LSRS       R2, R6, #2
+  0x08000846:  69FC         LDR        R4, [R7, #28]
+  0x08000848:  4294         CMP        R4, R2
+  0x0800084A:  D909         BLS        .L32                     ; 0x08000860
+  0x0800084C:  9A03         LDR        R2, [SP, #12]
+  0x0800084E:  43D2         MVNS       R2, R2
+  0x08000850:  6A8C         LDR        R4, [R1, #40]
+  0x08000852:  4014         ANDS       R4, R2
+  0x08000854:  009A         LSLS       R2, R3, #2
+  0x08000856:  0F12         LSRS       R2, R2, #28
+  0x08000858:  9D06         LDR        R5, [SP, #24]
+  0x0800085A:  40AA         LSLS       R2, R5
+  0x0800085C:  4322         ORRS       R2, R4
+  0x0800085E:  628A         STR        R2, [R1, #40]
+
.L32:
+  0x08000860:  9E04         LDR        R6, [SP, #16]
+
.L33:
+  0x08000862:  9D07         LDR        R5, [SP, #28]
+  0x08000864:  021A         LSLS       R2, R3, #8
+  0x08000866:  694C         LDR        R4, [R1, #20]
+  0x08000868:  4394         BICS       R4, R2
+  0x0800086A:  6880         LDR        R0, [R0, #8]
+  0x0800086C:  4010         ANDS       R0, R2
+  0x0800086E:  4A28         LDR        R2, =0x7FFFFF00          ; [PC, #160] [0x08000910] 
+  0x08000870:  4002         ANDS       R2, R0
+  0x08000872:  4322         ORRS       R2, R4
+  0x08000874:  614A         STR        R2, [R1, #20]
+  0x08000876:  2400         MOVS       R4, #0
+  0x08000878:  2B00         CMP        R3, #0
+  0x0800087A:  D532         BPL        .L37                     ; 0x080008E2
+  0x0800087C:  2003         MOVS       R0, #3
+  0x0800087E:  0582         LSLS       R2, R0, #22
+  0x08000880:  4824         LDR        R0, =0x40012708          ; [PC, #144] [0x08000914] 
+  0x08000882:  6805         LDR        R5, [R0]
+  0x08000884:  4629         MOV        R1, R5
+  0x08000886:  4011         ANDS       R1, R2
+  0x08000888:  4823         LDR        R0, =0xA4000200          ; [PC, #140] [0x08000918] 
+  0x0800088A:  4283         CMP        R3, R0
+  0x0800088C:  D11B         BNE        .L35                     ; 0x080008C6
+  0x0800088E:  481E         LDR        R0, =0x007FFFFF          ; [PC, #120] [0x08000908] 
+  0x08000890:  1C40         ADDS       R0, R0, #1
+  0x08000892:  4281         CMP        R1, R0
+  0x08000894:  D217         BCS        .L35                     ; 0x080008C6
+  0x08000896:  4B1F         LDR        R3, =0x40012708          ; [PC, #124] [0x08000914] 
+  0x08000898:  6818         LDR        R0, [R3]
+  0x0800089A:  4390         BICS       R0, R2
+  0x0800089C:  4301         ORRS       R1, R0
+  0x0800089E:  481A         LDR        R0, =0x007FFFFF          ; [PC, #104] [0x08000908] 
+  0x080008A0:  1840         ADDS       R0, R0, R1
+  0x080008A2:  1C40         ADDS       R0, R0, #1
+  0x080008A4:  6018         STR        R0, [R3]
+  0x080008A6:  481E         LDR        R0, =SystemCoreClock     ; [PC, #120] [0x08000920] =0x20000BA4 
+  0x080008A8:  6800         LDR        R0, [R0]
+  0x080008AA:  491E         LDR        R1, =0x00030D40          ; [PC, #120] [0x08000924] 
+  0x080008AC:  F005 FBEB    BL         __aeabi_uidiv            ; 0x08006086
+  0x080008B0:  210C         MOVS       R1, #12
+  0x080008B2:  4341         MULS       R1, R0, R1
+  0x080008B4:  1C48         ADDS       R0, R1, #1
+  0x080008B6:  9D07         LDR        R5, [SP, #28]
+
.L34:
+  0x080008B8:  9008         STR        R0, [SP, #32]
+  0x080008BA:  9808         LDR        R0, [SP, #32]
+  0x080008BC:  2800         CMP        R0, #0
+  0x080008BE:  D010         BEQ        .L37                     ; 0x080008E2
+  0x080008C0:  9808         LDR        R0, [SP, #32]
+  0x080008C2:  1E40         SUBS       R0, R0, #1
+  0x080008C4:  E7F8         B          .L34                     ; 0x080008B8
+
.L35:
+  0x080008C6:  4815         LDR        R0, =0xA8000400          ; [PC, #84] [0x0800091C] 
+  0x080008C8:  4283         CMP        R3, R0
+  0x080008CA:  D109         BNE        .L36                     ; 0x080008E0
+  0x080008CC:  2001         MOVS       R0, #1
+  0x080008CE:  0583         LSLS       R3, R0, #22
+  0x080008D0:  401D         ANDS       R5, R3
+  0x080008D2:  D105         BNE        .L36                     ; 0x080008E0
+  0x080008D4:  4D0F         LDR        R5, =0x40012708          ; [PC, #60] [0x08000914] 
+  0x080008D6:  6828         LDR        R0, [R5]
+  0x080008D8:  4390         BICS       R0, R2
+  0x080008DA:  4301         ORRS       R1, R0
+  0x080008DC:  4319         ORRS       R1, R3
+  0x080008DE:  6029         STR        R1, [R5]
+
.L36:
+  0x080008E0:  9D07         LDR        R5, [SP, #28]
+
.L37:
+  0x080008E2:  55BD         STRB       R5, [R7, R6]
+
.L38:
+  0x080008E4:  4620         MOV        R0, R4
+  0x080008E6:  B009         ADD        SP, SP, #36
+  0x080008E8:  BDF0         POP        {R4-R7, PC}
+
.L39:
+  0x080008EA:  2510         MOVS       R5, #16
+  0x080008EC:  E7A5         B          .L30                     ; 0x0800083A
+
.L40:
+  0x080008EE:  2511         MOVS       R5, #17
+  0x080008F0:  E7A3         B          .L30                     ; 0x0800083A
+
.L41:
+  0x080008F2:  2512         MOVS       R5, #18
+  0x080008F4:  E7A1         B          .L30                     ; 0x0800083A
+
.L42:
+  0x080008F6:  2513         MOVS       R5, #19
+  0x080008F8:  E79F         B          .L30                     ; 0x0800083A
+
.L43:
+  0x080008FA:  2514         MOVS       R5, #20
+  0x080008FC:  E79D         B          .L30                     ; 0x0800083A
+
.L44:
+  0x080008FE:  2515         MOVS       R5, #21
+  0x08000900:  E79B         B          .L30                     ; 0x0800083A
+  0x08000902:  46C0         NOP
+  0x08000904:  20000450     DC.W       hadc1
+  0x08000908:  007FFFFF     DC.W       0x007FFFFF
+  0x0800090C:  80000004     DC.W       0x80000004
+  0x08000910:  7FFFFF00     DC.W       0x7FFFFF00
+  0x08000914:  40012708     DC.W       0x40012708
+  0x08000918:  A4000200     DC.W       0xA4000200
+  0x0800091C:  A8000400     DC.W       0xA8000400
+  0x08000920:  20000BA4     DC.W       SystemCoreClock
+  0x08000924:  00030D40     DC.W       0x00030D40
+
+

Section .text.__NVIC_SystemReset from PowerPro_lto.o, size=28, align=4

+
+
__NVIC_SystemReset:
+  0x08000928:  F3BF 8F4F    DSB        SY
+  0x0800092C:  4803         LDR        R0, =0xE000ED0C          ; [PC, #12] [0x0800093C] 
+  0x0800092E:  4904         LDR        R1, =0x05FA0004          ; [PC, #16] [0x08000940] 
+  0x08000930:  6001         STR        R1, [R0]
+  0x08000932:  F3BF 8F4F    DSB        SY
+
.L1:
+  0x08000936:  BF00         NOP
+  0x08000938:  E7FD         B          .L1                      ; 0x08000936
+  0x0800093A:  46C0         NOP
+  0x0800093C:  E000ED0C     DC.W       0xE000ED0C
+  0x08000940:  05FA0004     DC.W       0x05FA0004
+
+

Section .text.HAL_DMA_Init from PowerPro_lto.o, size=224, align=4

+
+
HAL_DMA_Init:
+  0x08000944:  B5F0         PUSH       {R4-R7, LR}
+  0x08000946:  B083         SUB        SP, SP, #12
+  0x08000948:  2800         CMP        R0, #0
+  0x0800094A:  D03A         BEQ        .L1                      ; 0x080009C2
+  0x0800094C:  4604         MOV        R4, R0
+  0x0800094E:  4601         MOV        R1, R0
+  0x08000950:  3124         ADDS       R1, #36
+  0x08000952:  2002         MOVS       R0, #2
+  0x08000954:  9102         STR        R1, [SP, #8]
+  0x08000956:  7048         STRB       R0, [R1, #1]
+  0x08000958:  6827         LDR        R7, [R4]
+  0x0800095A:  6838         LDR        R0, [R7]
+  0x0800095C:  492C         LDR        R1, =0xFFFF800F          ; [PC, #176] [0x08000A10] 
+  0x0800095E:  4001         ANDS       R1, R0
+  0x08000960:  6039         STR        R1, [R7]
+  0x08000962:  4E2C         LDR        R6, =0x40020800          ; [PC, #176] [0x08000A14] 
+  0x08000964:  4630         MOV        R0, R6
+  0x08000966:  3080         ADDS       R0, #128
+  0x08000968:  64A0         STR        R0, [R4, #72]
+  0x0800096A:  482B         LDR        R0, =0xBFFDFFF8          ; [PC, #172] [0x08000A18] 
+  0x0800096C:  1838         ADDS       R0, R7, R0
+  0x0800096E:  2114         MOVS       R1, #20
+  0x08000970:  F005 FB89    BL         __aeabi_uidiv            ; 0x08006086
+  0x08000974:  0080         LSLS       R0, R0, #2
+  0x08000976:  1981         ADDS       R1, R0, R6
+  0x08000978:  6420         STR        R0, [R4, #64]
+  0x0800097A:  9101         STR        R1, [SP, #4]
+  0x0800097C:  6461         STR        R1, [R4, #68]
+  0x0800097E:  20FC         MOVS       R0, #252
+  0x08000980:  4038         ANDS       R0, R7
+  0x08000982:  3808         SUBS       R0, #8
+  0x08000984:  2114         MOVS       R1, #20
+  0x08000986:  F005 FB7E    BL         __aeabi_uidiv            ; 0x08006086
+  0x0800098A:  211C         MOVS       R1, #28
+  0x0800098C:  4001         ANDS       R1, R0
+  0x0800098E:  2601         MOVS       R6, #1
+  0x08000990:  4630         MOV        R0, R6
+  0x08000992:  4088         LSLS       R0, R1
+  0x08000994:  64E0         STR        R0, [R4, #76]
+  0x08000996:  68E1         LDR        R1, [R4, #12]
+  0x08000998:  6922         LDR        R2, [R4, #16]
+  0x0800099A:  430A         ORRS       R2, R1
+  0x0800099C:  6961         LDR        R1, [R4, #20]
+  0x0800099E:  4311         ORRS       R1, R2
+  0x080009A0:  69A2         LDR        R2, [R4, #24]
+  0x080009A2:  430A         ORRS       R2, R1
+  0x080009A4:  69E1         LDR        R1, [R4, #28]
+  0x080009A6:  4311         ORRS       R1, R2
+  0x080009A8:  6A22         LDR        R2, [R4, #32]
+  0x080009AA:  430A         ORRS       R2, R1
+  0x080009AC:  68A1         LDR        R1, [R4, #8]
+  0x080009AE:  683B         LDR        R3, [R7]
+  0x080009B0:  4313         ORRS       R3, R2
+  0x080009B2:  430B         ORRS       R3, R1
+  0x080009B4:  603B         STR        R3, [R7]
+  0x080009B6:  03B2         LSLS       R2, R6, #14
+  0x080009B8:  4291         CMP        R1, R2
+  0x080009BA:  D104         BNE        .L2                      ; 0x080009C6
+  0x080009BC:  2100         MOVS       R1, #0
+  0x080009BE:  6061         STR        R1, [R4, #4]
+  0x080009C0:  E002         B          .L3                      ; 0x080009C8
+
.L1:
+  0x080009C2:  2001         MOVS       R0, #1
+  0x080009C4:  E021         B          .L5                      ; 0x08000A0A
+
.L2:
+  0x080009C6:  6861         LDR        R1, [R4, #4]
+
.L3:
+  0x080009C8:  B2CF         UXTB       R7, R1
+  0x080009CA:  9A01         LDR        R2, [SP, #4]
+  0x080009CC:  6017         STR        R7, [R2]
+  0x080009CE:  1E49         SUBS       R1, R1, #1
+  0x080009D0:  4A12         LDR        R2, =0x40020884          ; [PC, #72] [0x08000A1C] 
+  0x080009D2:  6010         STR        R0, [R2]
+  0x080009D4:  2000         MOVS       R0, #0
+  0x080009D6:  2903         CMP        R1, #3
+  0x080009D8:  4603         MOV        R3, R0
+  0x080009DA:  4601         MOV        R1, R0
+  0x080009DC:  4605         MOV        R5, R0
+  0x080009DE:  D80D         BHI        .L4                      ; 0x080009FC
+  0x080009E0:  1E79         SUBS       R1, R7, #1
+  0x080009E2:  008B         LSLS       R3, R1, #2
+  0x080009E4:  18D3         ADDS       R3, R2, R3
+  0x080009E6:  67DD         STR        R5, [R3, #124]
+  0x080009E8:  2501         MOVS       R5, #1
+  0x080009EA:  2603         MOVS       R6, #3
+  0x080009EC:  400E         ANDS       R6, R1
+  0x080009EE:  40B5         LSLS       R5, R6
+  0x080009F0:  2601         MOVS       R6, #1
+  0x080009F2:  490B         LDR        R1, =0x40020944          ; [PC, #44] [0x08000A20] 
+  0x080009F4:  600D         STR        R5, [R1]
+  0x080009F6:  337C         ADDS       R3, #124
+  0x080009F8:  32BC         ADDS       R2, #188
+  0x080009FA:  4611         MOV        R1, R2
+
.L4:
+  0x080009FC:  63E0         STR        R0, [R4, #60]
+  0x080009FE:  6523         STR        R3, [R4, #80]
+  0x08000A00:  6561         STR        R1, [R4, #84]
+  0x08000A02:  65A5         STR        R5, [R4, #88]
+  0x08000A04:  9902         LDR        R1, [SP, #8]
+  0x08000A06:  7008         STRB       R0, [R1]
+  0x08000A08:  704E         STRB       R6, [R1, #1]
+
.L5:
+  0x08000A0A:  B003         ADD        SP, SP, #12
+  0x08000A0C:  BDF0         POP        {R4-R7, PC}
+  0x08000A0E:  46C0         NOP
+  0x08000A10:  FFFF800F     DC.W       0xFFFF800F
+  0x08000A14:  40020800     DC.W       0x40020800
+  0x08000A18:  BFFDFFF8     DC.W       0xBFFDFFF8
+  0x08000A1C:  40020884     DC.W       0x40020884
+  0x08000A20:  40020944     DC.W       0x40020944
+
+

Section .text.HAL_DMA_Start_IT from PowerPro_lto.o, size=196, align=4

+
+
HAL_DMA_Start_IT:
+  0x08000A24:  B5F0         PUSH       {R4-R7, LR}
+  0x08000A26:  B084         SUB        SP, SP, #16
+  0x08000A28:  4604         MOV        R4, R0
+  0x08000A2A:  2024         MOVS       R0, #36
+  0x08000A2C:  5C20         LDRB       R0, [R4, R0]
+  0x08000A2E:  2801         CMP        R0, #1
+  0x08000A30:  D101         BNE        .L1                      ; 0x08000A36
+  0x08000A32:  2002         MOVS       R0, #2
+  0x08000A34:  E053         B          .L11                     ; 0x08000ADE
+
.L1:
+  0x08000A36:  4625         MOV        R5, R4
+  0x08000A38:  3524         ADDS       R5, #36
+  0x08000A3A:  7868         LDRB       R0, [R5, #1]
+  0x08000A3C:  2801         CMP        R0, #1
+  0x08000A3E:  D130         BNE        .L5                      ; 0x08000AA2
+  0x08000A40:  9300         STR        R3, [SP, #0]
+  0x08000A42:  9201         STR        R2, [SP, #4]
+  0x08000A44:  2002         MOVS       R0, #2
+  0x08000A46:  7068         STRB       R0, [R5, #1]
+  0x08000A48:  2000         MOVS       R0, #0
+  0x08000A4A:  63E0         STR        R0, [R4, #60]
+  0x08000A4C:  6826         LDR        R6, [R4]
+  0x08000A4E:  6832         LDR        R2, [R6]
+  0x08000A50:  2301         MOVS       R3, #1
+  0x08000A52:  9303         STR        R3, [SP, #12]
+  0x08000A54:  439A         BICS       R2, R3
+  0x08000A56:  6032         STR        R2, [R6]
+  0x08000A58:  6CA2         LDR        R2, [R4, #72]
+  0x08000A5A:  6CE7         LDR        R7, [R4, #76]
+  0x08000A5C:  6057         STR        R7, [R2, #4]
+  0x08000A5E:  6D22         LDR        R2, [R4, #80]
+  0x08000A60:  9202         STR        R2, [SP, #8]
+  0x08000A62:  2A00         CMP        R2, #0
+  0x08000A64:  D002         BEQ        .L2                      ; 0x08000A6C
+  0x08000A66:  6D62         LDR        R2, [R4, #84]
+  0x08000A68:  6DA7         LDR        R7, [R4, #88]
+  0x08000A6A:  6057         STR        R7, [R2, #4]
+
.L2:
+  0x08000A6C:  6C22         LDR        R2, [R4, #64]
+  0x08000A6E:  271C         MOVS       R7, #28
+  0x08000A70:  4017         ANDS       R7, R2
+  0x08000A72:  2201         MOVS       R2, #1
+  0x08000A74:  40BA         LSLS       R2, R7
+  0x08000A76:  4F1B         LDR        R7, =0x40020004          ; [PC, #108] [0x08000AE4] 
+  0x08000A78:  683B         LDR        R3, [R7]
+  0x08000A7A:  4313         ORRS       R3, R2
+  0x08000A7C:  603B         STR        R3, [R7]
+  0x08000A7E:  9A00         LDR        R2, [SP, #0]
+  0x08000A80:  6072         STR        R2, [R6, #4]
+  0x08000A82:  68A2         LDR        R2, [R4, #8]
+  0x08000A84:  2A10         CMP        R2, #16
+  0x08000A86:  9B01         LDR        R3, [SP, #4]
+  0x08000A88:  461A         MOV        R2, R3
+  0x08000A8A:  D000         BEQ        .L3                      ; 0x08000A8E
+  0x08000A8C:  460A         MOV        R2, R1
+
.L3:
+  0x08000A8E:  60B2         STR        R2, [R6, #8]
+  0x08000A90:  D000         BEQ        .L4                      ; 0x08000A94
+  0x08000A92:  4619         MOV        R1, R3
+
.L4:
+  0x08000A94:  60F1         STR        R1, [R6, #12]
+  0x08000A96:  6831         LDR        R1, [R6]
+  0x08000A98:  6B22         LDR        R2, [R4, #48]
+  0x08000A9A:  2A00         CMP        R2, #0
+  0x08000A9C:  D003         BEQ        .L6                      ; 0x08000AA6
+  0x08000A9E:  220E         MOVS       R2, #14
+  0x08000AA0:  E006         B          .L7                      ; 0x08000AB0
+
.L5:
+  0x08000AA2:  2002         MOVS       R0, #2
+  0x08000AA4:  E019         B          .L10                     ; 0x08000ADA
+
.L6:
+  0x08000AA6:  2204         MOVS       R2, #4
+  0x08000AA8:  4391         BICS       R1, R2
+  0x08000AAA:  6031         STR        R1, [R6]
+  0x08000AAC:  6832         LDR        R2, [R6]
+  0x08000AAE:  210A         MOVS       R1, #10
+
.L7:
+  0x08000AB0:  4311         ORRS       R1, R2
+  0x08000AB2:  6031         STR        R1, [R6]
+  0x08000AB4:  9903         LDR        R1, [SP, #12]
+  0x08000AB6:  0209         LSLS       R1, R1, #8
+  0x08000AB8:  6C62         LDR        R2, [R4, #68]
+  0x08000ABA:  6813         LDR        R3, [R2]
+  0x08000ABC:  03DB         LSLS       R3, R3, #15
+  0x08000ABE:  D502         BPL        .L8                      ; 0x08000AC6
+  0x08000AC0:  6813         LDR        R3, [R2]
+  0x08000AC2:  430B         ORRS       R3, R1
+  0x08000AC4:  6013         STR        R3, [R2]
+
.L8:
+  0x08000AC6:  9B02         LDR        R3, [SP, #8]
+  0x08000AC8:  2B00         CMP        R3, #0
+  0x08000ACA:  D002         BEQ        .L9                      ; 0x08000AD2
+  0x08000ACC:  681A         LDR        R2, [R3]
+  0x08000ACE:  430A         ORRS       R2, R1
+  0x08000AD0:  601A         STR        R2, [R3]
+
.L9:
+  0x08000AD2:  6831         LDR        R1, [R6]
+  0x08000AD4:  9A03         LDR        R2, [SP, #12]
+  0x08000AD6:  4311         ORRS       R1, R2
+  0x08000AD8:  6031         STR        R1, [R6]
+
.L10:
+  0x08000ADA:  2100         MOVS       R1, #0
+  0x08000ADC:  7029         STRB       R1, [R5]
+
.L11:
+  0x08000ADE:  B004         ADD        SP, SP, #16
+  0x08000AE0:  BDF0         POP        {R4-R7, PC}
+  0x08000AE2:  46C0         NOP
+  0x08000AE4:  40020004     DC.W       0x40020004
+
+

Section .text.HAL_DMA_IRQHandler from PowerPro_lto.o, size=164, align=4

+
+
HAL_DMA_IRQHandler:
+  0x08000AE8:  B5F0         PUSH       {R4-R7, LR}
+  0x08000AEA:  B081         SUB        SP, SP, #4
+  0x08000AEC:  6C01         LDR        R1, [R0, #64]
+  0x08000AEE:  241C         MOVS       R4, #28
+  0x08000AF0:  400C         ANDS       R4, R1
+  0x08000AF2:  2604         MOVS       R6, #4
+  0x08000AF4:  4633         MOV        R3, R6
+  0x08000AF6:  40A3         LSLS       R3, R4
+  0x08000AF8:  4923         LDR        R1, =0x40020004          ; [PC, #140] [0x08000B88] 
+  0x08000AFA:  1F0A         SUBS       R2, R1, #4
+  0x08000AFC:  6817         LDR        R7, [R2]
+  0x08000AFE:  6802         LDR        R2, [R0]
+  0x08000B00:  6815         LDR        R5, [R2]
+  0x08000B02:  423B         TST        R3, R7
+  0x08000B04:  D001         BEQ        .L1                      ; 0x08000B0A
+  0x08000B06:  0769         LSLS       R1, R5, #29
+  0x08000B08:  D41D         BMI        .L3                      ; 0x08000B46
+
.L1:
+  0x08000B0A:  4603         MOV        R3, R0
+  0x08000B0C:  3324         ADDS       R3, #36
+  0x08000B0E:  2602         MOVS       R6, #2
+  0x08000B10:  40A6         LSLS       R6, R4
+  0x08000B12:  423E         TST        R6, R7
+  0x08000B14:  D001         BEQ        .L2                      ; 0x08000B1A
+  0x08000B16:  07A9         LSLS       R1, R5, #30
+  0x08000B18:  D421         BMI        .L5                      ; 0x08000B5E
+
.L2:
+  0x08000B1A:  40E7         LSRS       R7, R4
+  0x08000B1C:  0739         LSLS       R1, R7, #28
+  0x08000B1E:  D531         BPL        .L8                      ; 0x08000B84
+  0x08000B20:  0729         LSLS       R1, R5, #28
+  0x08000B22:  D52F         BPL        .L8                      ; 0x08000B84
+  0x08000B24:  6811         LDR        R1, [R2]
+  0x08000B26:  250E         MOVS       R5, #14
+  0x08000B28:  43A9         BICS       R1, R5
+  0x08000B2A:  6011         STR        R1, [R2]
+  0x08000B2C:  2101         MOVS       R1, #1
+  0x08000B2E:  460A         MOV        R2, R1
+  0x08000B30:  40A2         LSLS       R2, R4
+  0x08000B32:  4D15         LDR        R5, =0x40020004          ; [PC, #84] [0x08000B88] 
+  0x08000B34:  682C         LDR        R4, [R5]
+  0x08000B36:  4314         ORRS       R4, R2
+  0x08000B38:  602C         STR        R4, [R5]
+  0x08000B3A:  63C1         STR        R1, [R0, #60]
+  0x08000B3C:  2200         MOVS       R2, #0
+  0x08000B3E:  701A         STRB       R2, [R3]
+  0x08000B40:  7059         STRB       R1, [R3, #1]
+  0x08000B42:  6B41         LDR        R1, [R0, #52]
+  0x08000B44:  E01B         B          .L7                      ; 0x08000B7E
+
.L3:
+  0x08000B46:  6811         LDR        R1, [R2]
+  0x08000B48:  0689         LSLS       R1, R1, #26
+  0x08000B4A:  D402         BMI        .L4                      ; 0x08000B52
+  0x08000B4C:  6811         LDR        R1, [R2]
+  0x08000B4E:  43B1         BICS       R1, R6
+  0x08000B50:  6011         STR        R1, [R2]
+
.L4:
+  0x08000B52:  4A0D         LDR        R2, =0x40020004          ; [PC, #52] [0x08000B88] 
+  0x08000B54:  6811         LDR        R1, [R2]
+  0x08000B56:  4319         ORRS       R1, R3
+  0x08000B58:  6011         STR        R1, [R2]
+  0x08000B5A:  6B01         LDR        R1, [R0, #48]
+  0x08000B5C:  E00F         B          .L7                      ; 0x08000B7E
+
.L5:
+  0x08000B5E:  6811         LDR        R1, [R2]
+  0x08000B60:  0689         LSLS       R1, R1, #26
+  0x08000B62:  D405         BMI        .L6                      ; 0x08000B70
+  0x08000B64:  6811         LDR        R1, [R2]
+  0x08000B66:  240A         MOVS       R4, #10
+  0x08000B68:  43A1         BICS       R1, R4
+  0x08000B6A:  6011         STR        R1, [R2]
+  0x08000B6C:  2101         MOVS       R1, #1
+  0x08000B6E:  7059         STRB       R1, [R3, #1]
+
.L6:
+  0x08000B70:  2100         MOVS       R1, #0
+  0x08000B72:  7019         STRB       R1, [R3]
+  0x08000B74:  4A04         LDR        R2, =0x40020004          ; [PC, #16] [0x08000B88] 
+  0x08000B76:  6811         LDR        R1, [R2]
+  0x08000B78:  4331         ORRS       R1, R6
+  0x08000B7A:  6011         STR        R1, [R2]
+  0x08000B7C:  6AC1         LDR        R1, [R0, #44]
+
.L7:
+  0x08000B7E:  2900         CMP        R1, #0
+  0x08000B80:  D000         BEQ        .L8                      ; 0x08000B84
+  0x08000B82:  4788         BLX        R1
+
.L8:
+  0x08000B84:  B001         ADD        SP, SP, #4
+  0x08000B86:  BDF0         POP        {R4-R7, PC}
+  0x08000B88:  40020004     DC.W       0x40020004
+
+

Section .text.FLASH_WaitForLastOperation from PowerPro_lto.o, size=80, align=4

+
+
FLASH_WaitForLastOperation:
+  0x08000B8C:  B510         PUSH       {R4, LR}
+  0x08000B8E:  207D         MOVS       R0, #125
+  0x08000B90:  00C2         LSLS       R2, R0, #3
+  0x08000B92:  480F         LDR        R0, =uwTick              ; [PC, #60] [0x08000BD0] =0x2000068C 
+  0x08000B94:  6801         LDR        R1, [R0]
+  0x08000B96:  188B         ADDS       R3, R1, R2
+  0x08000B98:  490E         LDR        R1, =0x40022010          ; [PC, #56] [0x08000BD4] 
+
.L1:
+  0x08000B9A:  680C         LDR        R4, [R1]
+  0x08000B9C:  03E4         LSLS       R4, R4, #15
+  0x08000B9E:  D504         BPL        .L3                      ; 0x08000BAA
+  0x08000BA0:  6804         LDR        R4, [R0]
+  0x08000BA2:  429C         CMP        R4, R3
+  0x08000BA4:  D3F9         BCC        .L1                      ; 0x08000B9A
+
.L2:
+  0x08000BA6:  2003         MOVS       R0, #3
+  0x08000BA8:  BD10         POP        {R4, PC}
+
.L3:
+  0x08000BAA:  680B         LDR        R3, [R1]
+  0x08000BAC:  4C0A         LDR        R4, =0x0000C3FA          ; [PC, #40] [0x08000BD8] 
+  0x08000BAE:  401C         ANDS       R4, R3
+  0x08000BB0:  600C         STR        R4, [R1]
+  0x08000BB2:  D001         BEQ        .L4                      ; 0x08000BB8
+  0x08000BB4:  2001         MOVS       R0, #1
+  0x08000BB6:  BD10         POP        {R4, PC}
+
.L4:
+  0x08000BB8:  6803         LDR        R3, [R0]
+  0x08000BBA:  189A         ADDS       R2, R3, R2
+
.L5:
+  0x08000BBC:  680B         LDR        R3, [R1]
+  0x08000BBE:  035B         LSLS       R3, R3, #13
+  0x08000BC0:  D503         BPL        .L6                      ; 0x08000BCA
+  0x08000BC2:  6803         LDR        R3, [R0]
+  0x08000BC4:  4293         CMP        R3, R2
+  0x08000BC6:  D3F9         BCC        .L5                      ; 0x08000BBC
+  0x08000BC8:  E7ED         B          .L2                      ; 0x08000BA6
+
.L6:
+  0x08000BCA:  2000         MOVS       R0, #0
+  0x08000BCC:  BD10         POP        {R4, PC}
+  0x08000BCE:  46C0         NOP
+  0x08000BD0:  2000068C     DC.W       uwTick
+  0x08000BD4:  40022010     DC.W       0x40022010
+  0x08000BD8:  0000C3FA     DC.W       0x0000C3FA
+
+

Section .text.HAL_FLASH_Unlock from PowerPro_lto.o, size=32, align=4

+
+
HAL_FLASH_Unlock:
+  0x08000BDC:  4804         LDR        R0, =0x40022008          ; [PC, #16] [0x08000BF0] 
+  0x08000BDE:  68C1         LDR        R1, [R0, #12]
+  0x08000BE0:  2900         CMP        R1, #0
+  0x08000BE2:  D504         BPL        .L1                      ; 0x08000BEE
+  0x08000BE4:  4903         LDR        R1, =0x45670123          ; [PC, #12] [0x08000BF4] 
+  0x08000BE6:  6001         STR        R1, [R0]
+  0x08000BE8:  4903         LDR        R1, =0xCDEF89AB          ; [PC, #12] [0x08000BF8] 
+  0x08000BEA:  6001         STR        R1, [R0]
+  0x08000BEC:  68C0         LDR        R0, [R0, #12]
+
.L1:
+  0x08000BEE:  4770         BX         LR
+  0x08000BF0:  40022008     DC.W       0x40022008
+  0x08000BF4:  45670123     DC.W       0x45670123
+  0x08000BF8:  CDEF89AB     DC.W       0xCDEF89AB
+
+

Section .text.HAL_GPIO_Init from PowerPro_lto.o, size=380, align=4

+
+
HAL_GPIO_Init:
+  0x08000BFC:  B5F0         PUSH       {R4-R7, LR}
+  0x08000BFE:  B08A         SUB        SP, SP, #40
+  0x08000C00:  4A59         LDR        R2, =0x50001400          ; [PC, #0x0164] [0x08000D68] 
+  0x08000C02:  9005         STR        R0, [SP, #20]
+  0x08000C04:  4290         CMP        R0, R2
+  0x08000C06:  D001         BEQ        .L1                      ; 0x08000C0C
+  0x08000C08:  2006         MOVS       R0, #6
+  0x08000C0A:  E000         B          .L2                      ; 0x08000C0E
+
.L1:
+  0x08000C0C:  2005         MOVS       R0, #5
+
.L2:
+  0x08000C0E:  220B         MOVS       R2, #11
+  0x08000C10:  0712         LSLS       R2, R2, #28
+  0x08000C12:  9B05         LDR        R3, [SP, #20]
+  0x08000C14:  189B         ADDS       R3, R3, R2
+  0x08000C16:  220A         MOVS       R2, #10
+  0x08000C18:  41D3         RORS       R3, R2
+  0x08000C1A:  9300         STR        R3, [SP, #0]
+  0x08000C1C:  2B04         CMP        R3, #4
+  0x08000C1E:  D300         BCC        .L3                      ; 0x08000C22
+  0x08000C20:  9000         STR        R0, [SP, #0]
+
.L3:
+  0x08000C22:  9805         LDR        R0, [SP, #20]
+  0x08000C24:  3020         ADDS       R0, #32
+  0x08000C26:  9001         STR        R0, [SP, #4]
+  0x08000C28:  2200         MOVS       R2, #0
+  0x08000C2A:  4617         MOV        R7, R2
+  0x08000C2C:  9207         STR        R2, [SP, #28]
+  0x08000C2E:  9208         STR        R2, [SP, #32]
+
.L4:
+  0x08000C30:  680D         LDR        R5, [R1]
+  0x08000C32:  4628         MOV        R0, R5
+  0x08000C34:  40D0         LSRS       R0, R2
+  0x08000C36:  D100         BNE        .L5                      ; 0x08000C3A
+  0x08000C38:  E093         B          .L19                     ; 0x08000D62
+
.L5:
+  0x08000C3A:  2301         MOVS       R3, #1
+  0x08000C3C:  4618         MOV        R0, R3
+  0x08000C3E:  9209         STR        R2, [SP, #36]
+  0x08000C40:  4090         LSLS       R0, R2
+  0x08000C42:  9004         STR        R0, [SP, #16]
+  0x08000C44:  4005         ANDS       R5, R0
+  0x08000C46:  D100         BNE        .L6                      ; 0x08000C4A
+  0x08000C48:  E081         B          .L18                     ; 0x08000D4E
+
.L6:
+  0x08000C4A:  684A         LDR        R2, [R1, #4]
+  0x08000C4C:  2010         MOVS       R0, #16
+  0x08000C4E:  4310         ORRS       R0, R2
+  0x08000C50:  2812         CMP        R0, #18
+  0x08000C52:  460E         MOV        R6, R1
+  0x08000C54:  9706         STR        R7, [SP, #24]
+  0x08000C56:  D116         BNE        .L7                      ; 0x08000C86
+  0x08000C58:  211C         MOVS       R1, #28
+  0x08000C5A:  9808         LDR        R0, [SP, #32]
+  0x08000C5C:  4001         ANDS       R1, R0
+  0x08000C5E:  270F         MOVS       R7, #15
+  0x08000C60:  463A         MOV        R2, R7
+  0x08000C62:  408A         LSLS       R2, R1
+  0x08000C64:  9809         LDR        R0, [SP, #36]
+  0x08000C66:  08C4         LSRS       R4, R0, #3
+  0x08000C68:  00A4         LSLS       R4, R4, #2
+  0x08000C6A:  9303         STR        R3, [SP, #12]
+  0x08000C6C:  4633         MOV        R3, R6
+  0x08000C6E:  9E01         LDR        R6, [SP, #4]
+  0x08000C70:  5930         LDR        R0, [R6, R4]
+  0x08000C72:  4390         BICS       R0, R2
+  0x08000C74:  691A         LDR        R2, [R3, #16]
+  0x08000C76:  403A         ANDS       R2, R7
+  0x08000C78:  9F06         LDR        R7, [SP, #24]
+  0x08000C7A:  408A         LSLS       R2, R1
+  0x08000C7C:  4302         ORRS       R2, R0
+  0x08000C7E:  5132         STR        R2, [R6, R4]
+  0x08000C80:  461E         MOV        R6, R3
+  0x08000C82:  9B03         LDR        R3, [SP, #12]
+  0x08000C84:  6872         LDR        R2, [R6, #4]
+
.L7:
+  0x08000C86:  2403         MOVS       R4, #3
+  0x08000C88:  4610         MOV        R0, R2
+  0x08000C8A:  4020         ANDS       R0, R4
+  0x08000C8C:  40B8         LSLS       R0, R7
+  0x08000C8E:  9402         STR        R4, [SP, #8]
+  0x08000C90:  40BC         LSLS       R4, R7
+  0x08000C92:  9905         LDR        R1, [SP, #20]
+  0x08000C94:  680F         LDR        R7, [R1]
+  0x08000C96:  43A7         BICS       R7, R4
+  0x08000C98:  4307         ORRS       R7, R0
+  0x08000C9A:  600F         STR        R7, [R1]
+  0x08000C9C:  9F06         LDR        R7, [SP, #24]
+  0x08000C9E:  43E0         MVNS       R0, R4
+  0x08000CA0:  9003         STR        R0, [SP, #12]
+  0x08000CA2:  2A12         CMP        R2, #18
+  0x08000CA4:  4631         MOV        R1, R6
+  0x08000CA6:  D815         BHI        .L9                      ; 0x08000CD4
+  0x08000CA8:  4093         LSLS       R3, R2
+  0x08000CAA:  4832         LDR        R0, =0x00060006          ; [PC, #200] [0x08000D74] 
+  0x08000CAC:  4203         TST        R3, R0
+  0x08000CAE:  D00F         BEQ        .L8                      ; 0x08000CD0
+  0x08000CB0:  9C05         LDR        R4, [SP, #20]
+  0x08000CB2:  68A0         LDR        R0, [R4, #8]
+  0x08000CB4:  9B03         LDR        R3, [SP, #12]
+  0x08000CB6:  4018         ANDS       R0, R3
+  0x08000CB8:  68CB         LDR        R3, [R1, #12]
+  0x08000CBA:  40BB         LSLS       R3, R7
+  0x08000CBC:  4303         ORRS       R3, R0
+  0x08000CBE:  60A3         STR        R3, [R4, #8]
+  0x08000CC0:  0910         LSRS       R0, R2, #4
+  0x08000CC2:  9B09         LDR        R3, [SP, #36]
+  0x08000CC4:  4098         LSLS       R0, R3
+  0x08000CC6:  6863         LDR        R3, [R4, #4]
+  0x08000CC8:  9E04         LDR        R6, [SP, #16]
+  0x08000CCA:  43B3         BICS       R3, R6
+  0x08000CCC:  4303         ORRS       R3, R0
+  0x08000CCE:  6063         STR        R3, [R4, #4]
+
.L8:
+  0x08000CD0:  2A03         CMP        R2, #3
+  0x08000CD2:  D03C         BEQ        .L18                     ; 0x08000D4E
+
.L9:
+  0x08000CD4:  9C05         LDR        R4, [SP, #20]
+  0x08000CD6:  68E0         LDR        R0, [R4, #12]
+  0x08000CD8:  9B03         LDR        R3, [SP, #12]
+  0x08000CDA:  4018         ANDS       R0, R3
+  0x08000CDC:  688B         LDR        R3, [R1, #8]
+  0x08000CDE:  40BB         LSLS       R3, R7
+  0x08000CE0:  4303         ORRS       R3, R0
+  0x08000CE2:  60E3         STR        R3, [R4, #12]
+  0x08000CE4:  00D0         LSLS       R0, R2, #3
+  0x08000CE6:  D532         BPL        .L18                     ; 0x08000D4E
+  0x08000CE8:  2018         MOVS       R0, #24
+  0x08000CEA:  9A07         LDR        R2, [SP, #28]
+  0x08000CEC:  4010         ANDS       R0, R2
+  0x08000CEE:  220F         MOVS       R2, #15
+  0x08000CF0:  4082         LSLS       R2, R0
+  0x08000CF2:  9B09         LDR        R3, [SP, #36]
+  0x08000CF4:  9C02         LDR        R4, [SP, #8]
+  0x08000CF6:  43A3         BICS       R3, R4
+  0x08000CF8:  4C1C         LDR        R4, =0x40021800          ; [PC, #112] [0x08000D6C] 
+  0x08000CFA:  18E4         ADDS       R4, R4, R3
+  0x08000CFC:  6E23         LDR        R3, [R4, #96]
+  0x08000CFE:  4393         BICS       R3, R2
+  0x08000D00:  9A00         LDR        R2, [SP, #0]
+  0x08000D02:  4082         LSLS       R2, R0
+  0x08000D04:  431A         ORRS       R2, R3
+  0x08000D06:  6622         STR        R2, [R4, #96]
+  0x08000D08:  4819         LDR        R0, =0x40021880          ; [PC, #100] [0x08000D70] 
+  0x08000D0A:  6802         LDR        R2, [R0]
+  0x08000D0C:  684B         LDR        R3, [R1, #4]
+  0x08000D0E:  03D8         LSLS       R0, R3, #15
+  0x08000D10:  D501         BPL        .L10                     ; 0x08000D16
+  0x08000D12:  432A         ORRS       R2, R5
+  0x08000D14:  E000         B          .L11                     ; 0x08000D18
+
.L10:
+  0x08000D16:  43AA         BICS       R2, R5
+
.L11:
+  0x08000D18:  4815         LDR        R0, =0x40021880          ; [PC, #84] [0x08000D70] 
+  0x08000D1A:  6002         STR        R2, [R0]
+  0x08000D1C:  6842         LDR        R2, [R0, #4]
+  0x08000D1E:  0398         LSLS       R0, R3, #14
+  0x08000D20:  D501         BPL        .L12                     ; 0x08000D26
+  0x08000D22:  432A         ORRS       R2, R5
+  0x08000D24:  E000         B          .L13                     ; 0x08000D28
+
.L12:
+  0x08000D26:  43AA         BICS       R2, R5
+
.L13:
+  0x08000D28:  4811         LDR        R0, =0x40021880          ; [PC, #68] [0x08000D70] 
+  0x08000D2A:  6042         STR        R2, [R0, #4]
+  0x08000D2C:  480F         LDR        R0, =0x40021800          ; [PC, #60] [0x08000D6C] 
+  0x08000D2E:  6802         LDR        R2, [R0]
+  0x08000D30:  02D8         LSLS       R0, R3, #11
+  0x08000D32:  D501         BPL        .L14                     ; 0x08000D38
+  0x08000D34:  432A         ORRS       R2, R5
+  0x08000D36:  E000         B          .L15                     ; 0x08000D3A
+
.L14:
+  0x08000D38:  43AA         BICS       R2, R5
+
.L15:
+  0x08000D3A:  480C         LDR        R0, =0x40021800          ; [PC, #48] [0x08000D6C] 
+  0x08000D3C:  6002         STR        R2, [R0]
+  0x08000D3E:  6842         LDR        R2, [R0, #4]
+  0x08000D40:  0298         LSLS       R0, R3, #10
+  0x08000D42:  D501         BPL        .L16                     ; 0x08000D48
+  0x08000D44:  432A         ORRS       R2, R5
+  0x08000D46:  E000         B          .L17                     ; 0x08000D4A
+
.L16:
+  0x08000D48:  43AA         BICS       R2, R5
+
.L17:
+  0x08000D4A:  4808         LDR        R0, =0x40021800          ; [PC, #32] [0x08000D6C] 
+  0x08000D4C:  6042         STR        R2, [R0, #4]
+
.L18:
+  0x08000D4E:  9808         LDR        R0, [SP, #32]
+  0x08000D50:  1D00         ADDS       R0, R0, #4
+  0x08000D52:  9008         STR        R0, [SP, #32]
+  0x08000D54:  1CBF         ADDS       R7, R7, #2
+  0x08000D56:  9807         LDR        R0, [SP, #28]
+  0x08000D58:  3008         ADDS       R0, #8
+  0x08000D5A:  9007         STR        R0, [SP, #28]
+  0x08000D5C:  9A09         LDR        R2, [SP, #36]
+  0x08000D5E:  1C52         ADDS       R2, R2, #1
+  0x08000D60:  E766         B          .L4                      ; 0x08000C30
+
.L19:
+  0x08000D62:  B00A         ADD        SP, SP, #40
+  0x08000D64:  BDF0         POP        {R4-R7, PC}
+  0x08000D66:  46C0         NOP
+  0x08000D68:  50001400     DC.W       0x50001400
+  0x08000D6C:  40021800     DC.W       0x40021800
+  0x08000D70:  40021880     DC.W       0x40021880
+  0x08000D74:  00060006     DC.W       0x00060006
+
+

Section .text.HAL_RCC_GetSysClockFreq from PowerPro_lto.o, size=84, align=4

+
+
HAL_RCC_GetSysClockFreq:
+  0x08000D78:  4811         LDR        R0, =0x40021008          ; [PC, #68] [0x08000DC0] 
+  0x08000D7A:  6801         LDR        R1, [R0]
+  0x08000D7C:  0689         LSLS       R1, R1, #26
+  0x08000D7E:  0F49         LSRS       R1, R1, #29
+  0x08000D80:  D006         BEQ        .L1                      ; 0x08000D90
+  0x08000D82:  6802         LDR        R2, [R0]
+  0x08000D84:  2138         MOVS       R1, #56
+  0x08000D86:  400A         ANDS       R2, R1
+  0x08000D88:  2A08         CMP        R2, #8
+  0x08000D8A:  D108         BNE        .L2                      ; 0x08000D9E
+  0x08000D8C:  480D         LDR        R0, =0x007A1200          ; [PC, #52] [0x08000DC4] 
+  0x08000D8E:  4770         BX         LR
+
.L1:
+  0x08000D90:  3808         SUBS       R0, #8
+  0x08000D92:  6800         LDR        R0, [R0]
+  0x08000D94:  0480         LSLS       R0, R0, #18
+  0x08000D96:  0F41         LSRS       R1, R0, #29
+  0x08000D98:  480B         LDR        R0, =0x02DC6C00          ; [PC, #44] [0x08000DC8] 
+  0x08000D9A:  40C8         LSRS       R0, R1
+  0x08000D9C:  4770         BX         LR
+
.L2:
+  0x08000D9E:  6802         LDR        R2, [R0]
+  0x08000DA0:  400A         ANDS       R2, R1
+  0x08000DA2:  2A20         CMP        R2, #32
+  0x08000DA4:  D102         BNE        .L3                      ; 0x08000DAC
+  0x08000DA6:  2001         MOVS       R0, #1
+  0x08000DA8:  03C0         LSLS       R0, R0, #15
+  0x08000DAA:  4770         BX         LR
+
.L3:
+  0x08000DAC:  6800         LDR        R0, [R0]
+  0x08000DAE:  4008         ANDS       R0, R1
+  0x08000DB0:  2818         CMP        R0, #24
+  0x08000DB2:  D001         BEQ        .L4                      ; 0x08000DB8
+  0x08000DB4:  2000         MOVS       R0, #0
+  0x08000DB6:  4770         BX         LR
+
.L4:
+  0x08000DB8:  207D         MOVS       R0, #125
+  0x08000DBA:  0200         LSLS       R0, R0, #8
+  0x08000DBC:  4770         BX         LR
+  0x08000DBE:  46C0         NOP
+  0x08000DC0:  40021008     DC.W       0x40021008
+  0x08000DC4:  007A1200     DC.W       0x007A1200
+  0x08000DC8:  02DC6C00     DC.W       0x02DC6C00
+
+

Section .text.HAL_RCC_GetPCLK1Freq from PowerPro_lto.o, size=64, align=4

+
+
HAL_RCC_GetPCLK1Freq:
+  0x08000DCC:  B580         PUSH       {R7, LR}
+  0x08000DCE:  F7FF FFD3    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+  0x08000DD2:  490A         LDR        R1, =0x40021008          ; [PC, #40] [0x08000DFC] 
+  0x08000DD4:  680A         LDR        R2, [R1]
+  0x08000DD6:  0992         LSRS       R2, R2, #6
+  0x08000DD8:  233C         MOVS       R3, #60
+  0x08000DDA:  4013         ANDS       R3, R2
+  0x08000DDC:  4A08         LDR        R2, =AHBPrescTable       ; [PC, #32] [0x08000E00] =0x08005160 
+  0x08000DDE:  58D2         LDR        R2, [R2, R3]
+  0x08000DE0:  231F         MOVS       R3, #31
+  0x08000DE2:  401A         ANDS       R2, R3
+  0x08000DE4:  40D0         LSRS       R0, R2
+  0x08000DE6:  4A07         LDR        R2, =SystemCoreClock     ; [PC, #28] [0x08000E04] =0x20000BA4 
+  0x08000DE8:  6010         STR        R0, [R2]
+  0x08000DEA:  6809         LDR        R1, [R1]
+  0x08000DEC:  0A89         LSRS       R1, R1, #10
+  0x08000DEE:  221C         MOVS       R2, #28
+  0x08000DF0:  400A         ANDS       R2, R1
+  0x08000DF2:  4905         LDR        R1, =APBPrescTable       ; [PC, #20] [0x08000E08] =0x080051A0 
+  0x08000DF4:  5889         LDR        R1, [R1, R2]
+  0x08000DF6:  4019         ANDS       R1, R3
+  0x08000DF8:  40C8         LSRS       R0, R1
+  0x08000DFA:  BD80         POP        {R7, PC}
+  0x08000DFC:  40021008     DC.W       0x40021008
+  0x08000E00:  08005160     DC.W       AHBPrescTable
+  0x08000E04:  20000BA4     DC.W       SystemCoreClock
+  0x08000E08:  080051A0     DC.W       APBPrescTable
+
+

Section .text.HAL_RCCEx_PeriphCLKConfig from PowerPro_lto.o, size=268, align=4

+
+
HAL_RCCEx_PeriphCLKConfig:
+  0x08000E0C:  B5F0         PUSH       {R4-R7, LR}
+  0x08000E0E:  B084         SUB        SP, SP, #16
+  0x08000E10:  6803         LDR        R3, [R0]
+  0x08000E12:  0659         LSLS       R1, R3, #25
+  0x08000E14:  4A3C         LDR        R2, =0x4002103C          ; [PC, #240] [0x08000F08] 
+  0x08000E16:  D401         BMI        .L1                      ; 0x08000E1C
+  0x08000E18:  2500         MOVS       R5, #0
+  0x08000E1A:  E034         B          .L6                      ; 0x08000E86
+
.L1:
+  0x08000E1C:  2601         MOVS       R6, #1
+  0x08000E1E:  0734         LSLS       R4, R6, #28
+  0x08000E20:  6811         LDR        R1, [R2]
+  0x08000E22:  4021         ANDS       R1, R4
+  0x08000E24:  9102         STR        R1, [SP, #8]
+  0x08000E26:  D106         BNE        .L2                      ; 0x08000E36
+  0x08000E28:  6811         LDR        R1, [R2]
+  0x08000E2A:  4321         ORRS       R1, R4
+  0x08000E2C:  6011         STR        R1, [R2]
+  0x08000E2E:  6811         LDR        R1, [R2]
+  0x08000E30:  4021         ANDS       R1, R4
+  0x08000E32:  9103         STR        R1, [SP, #12]
+  0x08000E34:  9903         LDR        R1, [SP, #12]
+
.L2:
+  0x08000E36:  2103         MOVS       R1, #3
+  0x08000E38:  9101         STR        R1, [SP, #4]
+  0x08000E3A:  020D         LSLS       R5, R1, #8
+  0x08000E3C:  6A17         LDR        R7, [R2, #32]
+  0x08000E3E:  402F         ANDS       R7, R5
+  0x08000E40:  6985         LDR        R5, [R0, #24]
+  0x08000E42:  4932         LDR        R1, =0xFFFFFCFF          ; [PC, #200] [0x08000F0C] 
+  0x08000E44:  D012         BEQ        .L3                      ; 0x08000E6C
+  0x08000E46:  42AF         CMP        R7, R5
+  0x08000E48:  D011         BEQ        .L4                      ; 0x08000E6E
+  0x08000E4A:  9400         STR        R4, [SP, #0]
+  0x08000E4C:  6A17         LDR        R7, [R2, #32]
+  0x08000E4E:  0436         LSLS       R6, R6, #16
+  0x08000E50:  6A14         LDR        R4, [R2, #32]
+  0x08000E52:  4334         ORRS       R4, R6
+  0x08000E54:  6214         STR        R4, [R2, #32]
+  0x08000E56:  6A14         LDR        R4, [R2, #32]
+  0x08000E58:  43B4         BICS       R4, R6
+  0x08000E5A:  6214         STR        R4, [R2, #32]
+  0x08000E5C:  463C         MOV        R4, R7
+  0x08000E5E:  400C         ANDS       R4, R1
+  0x08000E60:  6214         STR        R4, [R2, #32]
+  0x08000E62:  07FC         LSLS       R4, R7, #31
+  0x08000E64:  D13E         BNE        .L12                     ; 0x08000EE4
+  0x08000E66:  462F         MOV        R7, R5
+  0x08000E68:  9C00         LDR        R4, [SP, #0]
+  0x08000E6A:  E000         B          .L4                      ; 0x08000E6E
+
.L3:
+  0x08000E6C:  462F         MOV        R7, R5
+
.L4:
+  0x08000E6E:  460D         MOV        R5, R1
+  0x08000E70:  6A11         LDR        R1, [R2, #32]
+  0x08000E72:  4029         ANDS       R1, R5
+  0x08000E74:  4339         ORRS       R1, R7
+  0x08000E76:  6211         STR        R1, [R2, #32]
+  0x08000E78:  2500         MOVS       R5, #0
+
.L5:
+  0x08000E7A:  9902         LDR        R1, [SP, #8]
+  0x08000E7C:  2900         CMP        R1, #0
+  0x08000E7E:  D102         BNE        .L6                      ; 0x08000E86
+  0x08000E80:  6811         LDR        R1, [R2]
+  0x08000E82:  43A1         BICS       R1, R4
+  0x08000E84:  6011         STR        R1, [R2]
+
.L6:
+  0x08000E86:  07D9         LSLS       R1, R3, #31
+  0x08000E88:  D005         BEQ        .L7                      ; 0x08000E96
+  0x08000E8A:  6991         LDR        R1, [R2, #24]
+  0x08000E8C:  2403         MOVS       R4, #3
+  0x08000E8E:  43A1         BICS       R1, R4
+  0x08000E90:  6884         LDR        R4, [R0, #8]
+  0x08000E92:  430C         ORRS       R4, R1
+  0x08000E94:  6194         STR        R4, [R2, #24]
+
.L7:
+  0x08000E96:  0799         LSLS       R1, R3, #30
+  0x08000E98:  D506         BPL        .L8                      ; 0x08000EA8
+  0x08000E9A:  2103         MOVS       R1, #3
+  0x08000E9C:  0309         LSLS       R1, R1, #12
+  0x08000E9E:  6994         LDR        R4, [R2, #24]
+  0x08000EA0:  438C         BICS       R4, R1
+  0x08000EA2:  68C1         LDR        R1, [R0, #12]
+  0x08000EA4:  4321         ORRS       R1, R4
+  0x08000EA6:  6191         STR        R1, [R2, #24]
+
.L8:
+  0x08000EA8:  0699         LSLS       R1, R3, #26
+  0x08000EAA:  D506         BPL        .L9                      ; 0x08000EBA
+  0x08000EAC:  2103         MOVS       R1, #3
+  0x08000EAE:  0789         LSLS       R1, R1, #30
+  0x08000EB0:  6994         LDR        R4, [R2, #24]
+  0x08000EB2:  438C         BICS       R4, R1
+  0x08000EB4:  6941         LDR        R1, [R0, #20]
+  0x08000EB6:  4321         ORRS       R1, R4
+  0x08000EB8:  6191         STR        R1, [R2, #24]
+
.L9:
+  0x08000EBA:  0759         LSLS       R1, R3, #29
+  0x08000EBC:  D506         BPL        .L10                     ; 0x08000ECC
+  0x08000EBE:  2103         MOVS       R1, #3
+  0x08000EC0:  0389         LSLS       R1, R1, #14
+  0x08000EC2:  6994         LDR        R4, [R2, #24]
+  0x08000EC4:  438C         BICS       R4, R1
+  0x08000EC6:  6901         LDR        R1, [R0, #16]
+  0x08000EC8:  4321         ORRS       R1, R4
+  0x08000ECA:  6191         STR        R1, [R2, #24]
+
.L10:
+  0x08000ECC:  0619         LSLS       R1, R3, #24
+  0x08000ECE:  D506         BPL        .L11                     ; 0x08000EDE
+  0x08000ED0:  3A3C         SUBS       R2, #60
+  0x08000ED2:  6811         LDR        R1, [R2]
+  0x08000ED4:  23E0         MOVS       R3, #224
+  0x08000ED6:  4399         BICS       R1, R3
+  0x08000ED8:  6840         LDR        R0, [R0, #4]
+  0x08000EDA:  4308         ORRS       R0, R1
+  0x08000EDC:  6010         STR        R0, [R2]
+
.L11:
+  0x08000EDE:  4628         MOV        R0, R5
+  0x08000EE0:  B004         ADD        SP, SP, #16
+  0x08000EE2:  BDF0         POP        {R4-R7, PC}
+
.L12:
+  0x08000EE4:  4E0A         LDR        R6, =uwTick              ; [PC, #40] [0x08000F10] =0x2000068C 
+  0x08000EE6:  6837         LDR        R7, [R6]
+
.L13:
+  0x08000EE8:  6A14         LDR        R4, [R2, #32]
+  0x08000EEA:  07A4         LSLS       R4, R4, #30
+  0x08000EEC:  D407         BMI        .L14                     ; 0x08000EFE
+  0x08000EEE:  6834         LDR        R4, [R6]
+  0x08000EF0:  1BE4         SUBS       R4, R4, R7
+  0x08000EF2:  4908         LDR        R1, =0x00001388          ; [PC, #32] [0x08000F14] 
+  0x08000EF4:  428C         CMP        R4, R1
+  0x08000EF6:  D9F7         BLS        .L13                     ; 0x08000EE8
+  0x08000EF8:  9D01         LDR        R5, [SP, #4]
+  0x08000EFA:  9C00         LDR        R4, [SP, #0]
+  0x08000EFC:  E7BD         B          .L5                      ; 0x08000E7A
+
.L14:
+  0x08000EFE:  462F         MOV        R7, R5
+  0x08000F00:  9C00         LDR        R4, [SP, #0]
+  0x08000F02:  4902         LDR        R1, =0xFFFFFCFF          ; [PC, #8] [0x08000F0C] 
+  0x08000F04:  E7B3         B          .L4                      ; 0x08000E6E
+  0x08000F06:  46C0         NOP
+  0x08000F08:  4002103C     DC.W       0x4002103C
+  0x08000F0C:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08000F10:  2000068C     DC.W       uwTick
+  0x08000F14:  00001388     DC.W       0x00001388
+
+

Section .text.HAL_TIM_Base_Init from PowerPro_lto.o, size=204, align=4

+
+
HAL_TIM_Base_Init:
+  0x08000F18:  B570         PUSH       {R4-R6, LR}
+  0x08000F1A:  B086         SUB        SP, SP, #24
+  0x08000F1C:  2800         CMP        R0, #0
+  0x08000F1E:  D01A         BEQ        .L2                      ; 0x08000F56
+  0x08000F20:  4604         MOV        R4, R0
+  0x08000F22:  4605         MOV        R5, R0
+  0x08000F24:  353C         ADDS       R5, #60
+  0x08000F26:  7868         LDRB       R0, [R5, #1]
+  0x08000F28:  2800         CMP        R0, #0
+  0x08000F2A:  D017         BEQ        .L4                      ; 0x08000F5C
+
.L1:
+  0x08000F2C:  2002         MOVS       R0, #2
+  0x08000F2E:  7068         STRB       R0, [R5, #1]
+  0x08000F30:  CC01         LDM        R4!, {R0}
+  0x08000F32:  4621         MOV        R1, R4
+  0x08000F34:  F000 F856    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08000F38:  2001         MOVS       R0, #1
+  0x08000F3A:  7328         STRB       R0, [R5, #12]
+  0x08000F3C:  70A8         STRB       R0, [R5, #2]
+  0x08000F3E:  70E8         STRB       R0, [R5, #3]
+  0x08000F40:  7128         STRB       R0, [R5, #4]
+  0x08000F42:  7168         STRB       R0, [R5, #5]
+  0x08000F44:  71A8         STRB       R0, [R5, #6]
+  0x08000F46:  71E8         STRB       R0, [R5, #7]
+  0x08000F48:  7228         STRB       R0, [R5, #8]
+  0x08000F4A:  7268         STRB       R0, [R5, #9]
+  0x08000F4C:  72A8         STRB       R0, [R5, #10]
+  0x08000F4E:  72E8         STRB       R0, [R5, #11]
+  0x08000F50:  7068         STRB       R0, [R5, #1]
+  0x08000F52:  2000         MOVS       R0, #0
+  0x08000F54:  E000         B          .L3                      ; 0x08000F58
+
.L2:
+  0x08000F56:  2001         MOVS       R0, #1
+
.L3:
+  0x08000F58:  B006         ADD        SP, SP, #24
+  0x08000F5A:  BD70         POP        {R4-R6, PC}
+
.L4:
+  0x08000F5C:  7028         STRB       R0, [R5]
+  0x08000F5E:  6821         LDR        R1, [R4]
+  0x08000F60:  4A1B         LDR        R2, =0x40014800          ; [PC, #108] [0x08000FD0] 
+  0x08000F62:  4291         CMP        R1, R2
+  0x08000F64:  D029         BEQ        .L5                      ; 0x08000FBA
+  0x08000F66:  4A1B         LDR        R2, =0x40014400          ; [PC, #108] [0x08000FD4] 
+  0x08000F68:  4291         CMP        R1, R2
+  0x08000F6A:  D1DF         BNE        .L1                      ; 0x08000F2C
+  0x08000F6C:  491A         LDR        R1, =0x40021034          ; [PC, #104] [0x08000FD8] 
+  0x08000F6E:  68CA         LDR        R2, [R1, #12]
+  0x08000F70:  2601         MOVS       R6, #1
+  0x08000F72:  9603         STR        R6, [SP, #12]
+  0x08000F74:  0473         LSLS       R3, R6, #17
+  0x08000F76:  431A         ORRS       R2, R3
+  0x08000F78:  60CA         STR        R2, [R1, #12]
+  0x08000F7A:  68CA         LDR        R2, [R1, #12]
+  0x08000F7C:  401A         ANDS       R2, R3
+  0x08000F7E:  9200         STR        R2, [SP, #0]
+  0x08000F80:  9A00         LDR        R2, [SP, #0]
+  0x08000F82:  680A         LDR        R2, [R1]
+  0x08000F84:  4332         ORRS       R2, R6
+  0x08000F86:  600A         STR        R2, [R1]
+  0x08000F88:  6809         LDR        R1, [R1]
+  0x08000F8A:  4031         ANDS       R1, R6
+  0x08000F8C:  9100         STR        R1, [SP, #0]
+  0x08000F8E:  9004         STR        R0, [SP, #16]
+  0x08000F90:  2002         MOVS       R0, #2
+  0x08000F92:  9002         STR        R0, [SP, #8]
+  0x08000F94:  2040         MOVS       R0, #64
+  0x08000F96:  9001         STR        R0, [SP, #4]
+  0x08000F98:  9800         LDR        R0, [SP, #0]
+  0x08000F9A:  2005         MOVS       R0, #5
+  0x08000F9C:  9005         STR        R0, [SP, #20]
+  0x08000F9E:  0700         LSLS       R0, R0, #28
+  0x08000FA0:  A901         ADD        R1, SP, #4
+  0x08000FA2:  F7FF FE2B    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x08000FA6:  20FF         MOVS       R0, #255
+  0x08000FA8:  0200         LSLS       R0, R0, #8
+  0x08000FAA:  490C         LDR        R1, =0xE000E414          ; [PC, #48] [0x08000FDC] 
+  0x08000FAC:  680A         LDR        R2, [R1]
+  0x08000FAE:  4382         BICS       R2, R0
+  0x08000FB0:  600A         STR        R2, [R1]
+  0x08000FB2:  0570         LSLS       R0, R6, #21
+  0x08000FB4:  490A         LDR        R1, =0xE000E100          ; [PC, #40] [0x08000FE0] 
+  0x08000FB6:  6008         STR        R0, [R1]
+  0x08000FB8:  E7B8         B          .L1                      ; 0x08000F2C
+
.L5:
+  0x08000FBA:  2001         MOVS       R0, #1
+  0x08000FBC:  0480         LSLS       R0, R0, #18
+  0x08000FBE:  4906         LDR        R1, =0x40021034          ; [PC, #24] [0x08000FD8] 
+  0x08000FC0:  68CA         LDR        R2, [R1, #12]
+  0x08000FC2:  4302         ORRS       R2, R0
+  0x08000FC4:  60CA         STR        R2, [R1, #12]
+  0x08000FC6:  68C9         LDR        R1, [R1, #12]
+  0x08000FC8:  4001         ANDS       R1, R0
+  0x08000FCA:  9101         STR        R1, [SP, #4]
+  0x08000FCC:  9801         LDR        R0, [SP, #4]
+  0x08000FCE:  E7AD         B          .L1                      ; 0x08000F2C
+  0x08000FD0:  40014800     DC.W       0x40014800
+  0x08000FD4:  40014400     DC.W       0x40014400
+  0x08000FD8:  40021034     DC.W       0x40021034
+  0x08000FDC:  E000E414     DC.W       0xE000E414
+  0x08000FE0:  E000E100     DC.W       0xE000E100
+
+

Section .text.TIM_Base_SetConfig from PowerPro_lto.o, size=144, align=4

+
+
TIM_Base_SetConfig:
+  0x08000FE4:  B530         PUSH       {R4-R5, LR}
+  0x08000FE6:  6804         LDR        R4, [R0]
+  0x08000FE8:  4A1D         LDR        R2, =0x40012C00          ; [PC, #116] [0x08001060] 
+  0x08000FEA:  4290         CMP        R0, R2
+  0x08000FEC:  D004         BEQ        .L1                      ; 0x08000FF8
+  0x08000FEE:  4D1D         LDR        R5, =0x40000400          ; [PC, #116] [0x08001064] 
+  0x08000FF0:  42A8         CMP        R0, R5
+  0x08000FF2:  D006         BEQ        .L2                      ; 0x08001002
+  0x08000FF4:  4623         MOV        R3, R4
+  0x08000FF6:  E008         B          .L3                      ; 0x0800100A
+
.L1:
+  0x08000FF8:  2370         MOVS       R3, #112
+  0x08000FFA:  439C         BICS       R4, R3
+  0x08000FFC:  684B         LDR        R3, [R1, #4]
+  0x08000FFE:  4323         ORRS       R3, R4
+  0x08001000:  E00F         B          .L4                      ; 0x08001022
+
.L2:
+  0x08001002:  2370         MOVS       R3, #112
+  0x08001004:  439C         BICS       R4, R3
+  0x08001006:  684B         LDR        R3, [R1, #4]
+  0x08001008:  4323         ORRS       R3, R4
+
.L3:
+  0x0800100A:  42A8         CMP        R0, R5
+  0x0800100C:  D009         BEQ        .L4                      ; 0x08001022
+  0x0800100E:  4C16         LDR        R4, =0x40002000          ; [PC, #88] [0x08001068] 
+  0x08001010:  42A0         CMP        R0, R4
+  0x08001012:  D006         BEQ        .L4                      ; 0x08001022
+  0x08001014:  4C15         LDR        R4, =0x40014800          ; [PC, #84] [0x0800106C] 
+  0x08001016:  42A0         CMP        R0, R4
+  0x08001018:  D003         BEQ        .L4                      ; 0x08001022
+  0x0800101A:  4C15         LDR        R4, =0x40014400          ; [PC, #84] [0x08001070] 
+  0x0800101C:  42A0         CMP        R0, R4
+  0x0800101E:  461C         MOV        R4, R3
+  0x08001020:  D104         BNE        .L5                      ; 0x0800102C
+
.L4:
+  0x08001022:  2403         MOVS       R4, #3
+  0x08001024:  0224         LSLS       R4, R4, #8
+  0x08001026:  43A3         BICS       R3, R4
+  0x08001028:  68CC         LDR        R4, [R1, #12]
+  0x0800102A:  431C         ORRS       R4, R3
+
.L5:
+  0x0800102C:  4290         CMP        R0, R2
+  0x0800102E:  688A         LDR        R2, [R1, #8]
+  0x08001030:  62C2         STR        R2, [R0, #44]
+  0x08001032:  680A         LDR        R2, [R1]
+  0x08001034:  6282         STR        R2, [R0, #40]
+  0x08001036:  694A         LDR        R2, [R1, #20]
+  0x08001038:  D005         BEQ        .L6                      ; 0x08001046
+  0x0800103A:  4B0C         LDR        R3, =0x40014800          ; [PC, #48] [0x0800106C] 
+  0x0800103C:  4298         CMP        R0, R3
+  0x0800103E:  D002         BEQ        .L6                      ; 0x08001046
+  0x08001040:  4B0B         LDR        R3, =0x40014400          ; [PC, #44] [0x08001070] 
+  0x08001042:  4298         CMP        R0, R3
+  0x08001044:  D101         BNE        .L7                      ; 0x0800104A
+
.L6:
+  0x08001046:  6909         LDR        R1, [R1, #16]
+  0x08001048:  6301         STR        R1, [R0, #48]
+
.L7:
+  0x0800104A:  6801         LDR        R1, [R0]
+  0x0800104C:  2304         MOVS       R3, #4
+  0x0800104E:  430B         ORRS       R3, R1
+  0x08001050:  6003         STR        R3, [R0]
+  0x08001052:  2101         MOVS       R1, #1
+  0x08001054:  6141         STR        R1, [R0, #20]
+  0x08001056:  2180         MOVS       R1, #128
+  0x08001058:  438C         BICS       R4, R1
+  0x0800105A:  4314         ORRS       R4, R2
+  0x0800105C:  6004         STR        R4, [R0]
+  0x0800105E:  BD30         POP        {R4-R5, PC}
+  0x08001060:  40012C00     DC.W       0x40012C00
+  0x08001064:  40000400     DC.W       0x40000400
+  0x08001068:  40002000     DC.W       0x40002000
+  0x0800106C:  40014800     DC.W       0x40014800
+  0x08001070:  40014400     DC.W       0x40014400
+
+

Section .text.HAL_UART_Init from PowerPro_lto.o, size=972, align=4

+
+
HAL_UART_Init:
+  0x08001074:  B5F0         PUSH       {R4-R7, LR}
+  0x08001076:  B091         SUB        SP, SP, #68
+  0x08001078:  4EE0         LDR        R6, =huart1              ; [PC, #0x0380] [0x080013FC] =0x200003BC 
+  0x0800107A:  2488         MOVS       R4, #136
+  0x0800107C:  5930         LDR        R0, [R6, R4]
+  0x0800107E:  2800         CMP        R0, #0
+  0x08001080:  6835         LDR        R5, [R6]
+  0x08001082:  9403         STR        R4, [SP, #12]
+  0x08001084:  D168         BNE        .L4                      ; 0x08001158
+  0x08001086:  2084         MOVS       R0, #132
+  0x08001088:  2700         MOVS       R7, #0
+  0x0800108A:  5437         STRB       R7, [R6, R0]
+  0x0800108C:  A805         ADD        R0, SP, #20
+  0x0800108E:  1D00         ADDS       R0, R0, #4
+  0x08001090:  2118         MOVS       R1, #24
+  0x08001092:  F005 F88E    BL         __aeabi_memclr           ; 0x080061B2
+  0x08001096:  48DA         LDR        R0, =0x40013800          ; [PC, #0x0368] [0x08001400] 
+  0x08001098:  4285         CMP        R5, R0
+  0x0800109A:  D15D         BNE        .L4                      ; 0x08001158
+  0x0800109C:  2401         MOVS       R4, #1
+  0x0800109E:  9405         STR        R4, [SP, #20]
+  0x080010A0:  A805         ADD        R0, SP, #20
+  0x080010A2:  F7FF FEB3    BL         HAL_RCCEx_PeriphCLKConfig ; 0x08000E0C
+  0x080010A6:  2800         CMP        R0, #0
+  0x080010A8:  D000         BEQ        .L1                      ; 0x080010AC
+  0x080010AA:  E1A5         B          .L31                     ; 0x080013F8
+
.L1:
+  0x080010AC:  48D5         LDR        R0, =0x40021000          ; [PC, #0x0354] [0x08001404] 
+  0x080010AE:  6C01         LDR        R1, [R0, #64]
+  0x080010B0:  9410         STR        R4, [SP, #64]
+  0x080010B2:  03A2         LSLS       R2, R4, #14
+  0x080010B4:  4311         ORRS       R1, R2
+  0x080010B6:  6401         STR        R1, [R0, #64]
+  0x080010B8:  6C01         LDR        R1, [R0, #64]
+  0x080010BA:  4011         ANDS       R1, R2
+  0x080010BC:  9104         STR        R1, [SP, #16]
+  0x080010BE:  9904         LDR        R1, [SP, #16]
+  0x080010C0:  6B41         LDR        R1, [R0, #52]
+  0x080010C2:  4321         ORRS       R1, R4
+  0x080010C4:  6341         STR        R1, [R0, #52]
+  0x080010C6:  6B40         LDR        R0, [R0, #52]
+  0x080010C8:  9401         STR        R4, [SP, #4]
+  0x080010CA:  4020         ANDS       R0, R4
+  0x080010CC:  9004         STR        R0, [SP, #16]
+  0x080010CE:  970F         STR        R7, [SP, #60]
+  0x080010D0:  970E         STR        R7, [SP, #56]
+  0x080010D2:  2002         MOVS       R0, #2
+  0x080010D4:  900D         STR        R0, [SP, #52]
+  0x080010D6:  2003         MOVS       R0, #3
+  0x080010D8:  0240         LSLS       R0, R0, #9
+  0x080010DA:  900C         STR        R0, [SP, #48]
+  0x080010DC:  9804         LDR        R0, [SP, #16]
+  0x080010DE:  2005         MOVS       R0, #5
+  0x080010E0:  0700         LSLS       R0, R0, #28
+  0x080010E2:  A90C         ADD        R1, SP, #48
+  0x080010E4:  F7FF FD8A    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x080010E8:  4CC7         LDR        R4, =hdma_usart1_rx      ; [PC, #0x031C] [0x08001408] =0x20000510 
+  0x080010EA:  2180         MOVS       R1, #128
+  0x080010EC:  2032         MOVS       R0, #50
+  0x080010EE:  4DC7         LDR        R5, =0x4002001C          ; [PC, #0x031C] [0x0800140C] 
+  0x080010F0:  6025         STR        R5, [R4]
+  0x080010F2:  6060         STR        R0, [R4, #4]
+  0x080010F4:  60A7         STR        R7, [R4, #8]
+  0x080010F6:  60E7         STR        R7, [R4, #12]
+  0x080010F8:  9102         STR        R1, [SP, #8]
+  0x080010FA:  6121         STR        R1, [R4, #16]
+  0x080010FC:  6167         STR        R7, [R4, #20]
+  0x080010FE:  61A7         STR        R7, [R4, #24]
+  0x08001100:  61E7         STR        R7, [R4, #28]
+  0x08001102:  6227         STR        R7, [R4, #32]
+  0x08001104:  4620         MOV        R0, R4
+  0x08001106:  F7FF FC1D    BL         HAL_DMA_Init             ; 0x08000944
+  0x0800110A:  2800         CMP        R0, #0
+  0x0800110C:  D000         BEQ        .L2                      ; 0x08001110
+  0x0800110E:  E173         B          .L31                     ; 0x080013F8
+
.L2:
+  0x08001110:  9A02         LDR        R2, [SP, #8]
+  0x08001112:  50B4         STR        R4, [R6, R2]
+  0x08001114:  62A6         STR        R6, [R4, #40]
+  0x08001116:  4CBE         LDR        R4, =hdma_usart1_tx      ; [PC, #0x02F8] [0x08001410] =0x200004B4 
+  0x08001118:  2010         MOVS       R0, #16
+  0x0800111A:  2133         MOVS       R1, #51
+  0x0800111C:  6227         STR        R7, [R4, #32]
+  0x0800111E:  3514         ADDS       R5, #20
+  0x08001120:  6025         STR        R5, [R4]
+  0x08001122:  6061         STR        R1, [R4, #4]
+  0x08001124:  60A0         STR        R0, [R4, #8]
+  0x08001126:  60E7         STR        R7, [R4, #12]
+  0x08001128:  6122         STR        R2, [R4, #16]
+  0x0800112A:  6167         STR        R7, [R4, #20]
+  0x0800112C:  61A7         STR        R7, [R4, #24]
+  0x0800112E:  61E7         STR        R7, [R4, #28]
+  0x08001130:  4620         MOV        R0, R4
+  0x08001132:  F7FF FC07    BL         HAL_DMA_Init             ; 0x08000944
+  0x08001136:  2800         CMP        R0, #0
+  0x08001138:  D000         BEQ        .L3                      ; 0x0800113C
+  0x0800113A:  E15D         B          .L31                     ; 0x080013F8
+
.L3:
+  0x0800113C:  62A6         STR        R6, [R4, #40]
+  0x0800113E:  67F4         STR        R4, [R6, #124]
+  0x08001140:  20FF         MOVS       R0, #255
+  0x08001142:  0600         LSLS       R0, R0, #24
+  0x08001144:  49B3         LDR        R1, =0xE000E418          ; [PC, #0x02CC] [0x08001414] 
+  0x08001146:  680A         LDR        R2, [R1]
+  0x08001148:  4382         BICS       R2, R0
+  0x0800114A:  600A         STR        R2, [R1]
+  0x0800114C:  9801         LDR        R0, [SP, #4]
+  0x0800114E:  06C0         LSLS       R0, R0, #27
+  0x08001150:  49B1         LDR        R1, =0xE000E100          ; [PC, #0x02C4] [0x08001418] 
+  0x08001152:  6008         STR        R0, [R1]
+  0x08001154:  6835         LDR        R5, [R6]
+  0x08001156:  9C03         LDR        R4, [SP, #12]
+
.L4:
+  0x08001158:  2024         MOVS       R0, #36
+  0x0800115A:  5130         STR        R0, [R6, R4]
+  0x0800115C:  6828         LDR        R0, [R5]
+  0x0800115E:  2401         MOVS       R4, #1
+  0x08001160:  43A0         BICS       R0, R4
+  0x08001162:  6028         STR        R0, [R5]
+  0x08001164:  6AB0         LDR        R0, [R6, #40]
+  0x08001166:  2800         CMP        R0, #0
+  0x08001168:  D048         BEQ        .L12                     ; 0x080011FC
+  0x0800116A:  0701         LSLS       R1, R0, #28
+  0x0800116C:  D505         BPL        .L5                      ; 0x0800117A
+  0x0800116E:  03E1         LSLS       R1, R4, #15
+  0x08001170:  686A         LDR        R2, [R5, #4]
+  0x08001172:  438A         BICS       R2, R1
+  0x08001174:  6BB1         LDR        R1, [R6, #56]
+  0x08001176:  4311         ORRS       R1, R2
+  0x08001178:  6069         STR        R1, [R5, #4]
+
.L5:
+  0x0800117A:  07C1         LSLS       R1, R0, #31
+  0x0800117C:  D005         BEQ        .L6                      ; 0x0800118A
+  0x0800117E:  0461         LSLS       R1, R4, #17
+  0x08001180:  686A         LDR        R2, [R5, #4]
+  0x08001182:  438A         BICS       R2, R1
+  0x08001184:  6AF1         LDR        R1, [R6, #44]
+  0x08001186:  4311         ORRS       R1, R2
+  0x08001188:  6069         STR        R1, [R5, #4]
+
.L6:
+  0x0800118A:  0781         LSLS       R1, R0, #30
+  0x0800118C:  D505         BPL        .L7                      ; 0x0800119A
+  0x0800118E:  0421         LSLS       R1, R4, #16
+  0x08001190:  686A         LDR        R2, [R5, #4]
+  0x08001192:  438A         BICS       R2, R1
+  0x08001194:  6B31         LDR        R1, [R6, #48]
+  0x08001196:  4311         ORRS       R1, R2
+  0x08001198:  6069         STR        R1, [R5, #4]
+
.L7:
+  0x0800119A:  0741         LSLS       R1, R0, #29
+  0x0800119C:  D505         BPL        .L8                      ; 0x080011AA
+  0x0800119E:  04A1         LSLS       R1, R4, #18
+  0x080011A0:  686A         LDR        R2, [R5, #4]
+  0x080011A2:  438A         BICS       R2, R1
+  0x080011A4:  6B71         LDR        R1, [R6, #52]
+  0x080011A6:  4311         ORRS       R1, R2
+  0x080011A8:  6069         STR        R1, [R5, #4]
+
.L8:
+  0x080011AA:  06C1         LSLS       R1, R0, #27
+  0x080011AC:  D505         BPL        .L9                      ; 0x080011BA
+  0x080011AE:  0321         LSLS       R1, R4, #12
+  0x080011B0:  68AA         LDR        R2, [R5, #8]
+  0x080011B2:  438A         BICS       R2, R1
+  0x080011B4:  6BF1         LDR        R1, [R6, #60]
+  0x080011B6:  4311         ORRS       R1, R2
+  0x080011B8:  60A9         STR        R1, [R5, #8]
+
.L9:
+  0x080011BA:  0681         LSLS       R1, R0, #26
+  0x080011BC:  D505         BPL        .L10                     ; 0x080011CA
+  0x080011BE:  0361         LSLS       R1, R4, #13
+  0x080011C0:  68AA         LDR        R2, [R5, #8]
+  0x080011C2:  438A         BICS       R2, R1
+  0x080011C4:  6C31         LDR        R1, [R6, #64]
+  0x080011C6:  4311         ORRS       R1, R2
+  0x080011C8:  60A9         STR        R1, [R5, #8]
+
.L10:
+  0x080011CA:  0641         LSLS       R1, R0, #25
+  0x080011CC:  D50E         BPL        .L11                     ; 0x080011EC
+  0x080011CE:  0521         LSLS       R1, R4, #20
+  0x080011D0:  686A         LDR        R2, [R5, #4]
+  0x080011D2:  438A         BICS       R2, R1
+  0x080011D4:  6C73         LDR        R3, [R6, #68]
+  0x080011D6:  431A         ORRS       R2, R3
+  0x080011D8:  606A         STR        R2, [R5, #4]
+  0x080011DA:  428B         CMP        R3, R1
+  0x080011DC:  D106         BNE        .L11                     ; 0x080011EC
+  0x080011DE:  2103         MOVS       R1, #3
+  0x080011E0:  0549         LSLS       R1, R1, #21
+  0x080011E2:  686A         LDR        R2, [R5, #4]
+  0x080011E4:  438A         BICS       R2, R1
+  0x080011E6:  6CB1         LDR        R1, [R6, #72]
+  0x080011E8:  4311         ORRS       R1, R2
+  0x080011EA:  6069         STR        R1, [R5, #4]
+
.L11:
+  0x080011EC:  0600         LSLS       R0, R0, #24
+  0x080011EE:  D505         BPL        .L12                     ; 0x080011FC
+  0x080011F0:  04E0         LSLS       R0, R4, #19
+  0x080011F2:  6869         LDR        R1, [R5, #4]
+  0x080011F4:  4381         BICS       R1, R0
+  0x080011F6:  6CF0         LDR        R0, [R6, #76]
+  0x080011F8:  4308         ORRS       R0, R1
+  0x080011FA:  6068         STR        R0, [R5, #4]
+
.L12:
+  0x080011FC:  6828         LDR        R0, [R5]
+  0x080011FE:  4987         LDR        R1, =0xCFFF69F3          ; [PC, #0x021C] [0x0800141C] 
+  0x08001200:  4001         ANDS       R1, R0
+  0x08001202:  68B0         LDR        R0, [R6, #8]
+  0x08001204:  6932         LDR        R2, [R6, #16]
+  0x08001206:  4302         ORRS       R2, R0
+  0x08001208:  6970         LDR        R0, [R6, #20]
+  0x0800120A:  4310         ORRS       R0, R2
+  0x0800120C:  4308         ORRS       R0, R1
+  0x0800120E:  69F1         LDR        R1, [R6, #28]
+  0x08001210:  4308         ORRS       R0, R1
+  0x08001212:  6028         STR        R0, [R5]
+  0x08001214:  2003         MOVS       R0, #3
+  0x08001216:  9002         STR        R0, [SP, #8]
+  0x08001218:  0300         LSLS       R0, R0, #12
+  0x0800121A:  686A         LDR        R2, [R5, #4]
+  0x0800121C:  4382         BICS       R2, R0
+  0x0800121E:  68F0         LDR        R0, [R6, #12]
+  0x08001220:  4310         ORRS       R0, R2
+  0x08001222:  6068         STR        R0, [R5, #4]
+  0x08001224:  69B0         LDR        R0, [R6, #24]
+  0x08001226:  6A32         LDR        R2, [R6, #32]
+  0x08001228:  4302         ORRS       R2, R0
+  0x0800122A:  68A8         LDR        R0, [R5, #8]
+  0x0800122C:  4B7C         LDR        R3, =0x11FFF4FF          ; [PC, #0x01F0] [0x08001420] 
+  0x0800122E:  4003         ANDS       R3, R0
+  0x08001230:  4313         ORRS       R3, R2
+  0x08001232:  60AB         STR        R3, [R5, #8]
+  0x08001234:  6AE8         LDR        R0, [R5, #44]
+  0x08001236:  220F         MOVS       R2, #15
+  0x08001238:  4390         BICS       R0, R2
+  0x0800123A:  6A77         LDR        R7, [R6, #36]
+  0x0800123C:  4338         ORRS       R0, R7
+  0x0800123E:  62E8         STR        R0, [R5, #44]
+  0x08001240:  4878         LDR        R0, =0x40004400          ; [PC, #0x01E0] [0x08001424] 
+  0x08001242:  4285         CMP        R5, R0
+  0x08001244:  D009         BEQ        .L13                     ; 0x0800125A
+  0x08001246:  486E         LDR        R0, =0x40013800          ; [PC, #0x01B8] [0x08001400] 
+  0x08001248:  4285         CMP        R5, R0
+  0x0800124A:  D108         BNE        .L14                     ; 0x0800125E
+  0x0800124C:  486D         LDR        R0, =0x40021000          ; [PC, #0x01B4] [0x08001404] 
+  0x0800124E:  6D40         LDR        R0, [R0, #84]
+  0x08001250:  0780         LSLS       R0, R0, #30
+  0x08001252:  0F00         LSRS       R0, R0, #28
+  0x08001254:  4A74         LDR        R2, =0x080051C0          ; [PC, #0x01D0] [0x08001428] 
+  0x08001256:  5812         LDR        R2, [R2, R0]
+  0x08001258:  E002         B          .L15                     ; 0x08001260
+
.L13:
+  0x0800125A:  2200         MOVS       R2, #0
+  0x0800125C:  E000         B          .L15                     ; 0x08001260
+
.L14:
+  0x0800125E:  2210         MOVS       R2, #16
+
.L15:
+  0x08001260:  03E0         LSLS       R0, R4, #15
+  0x08001262:  4281         CMP        R1, R0
+  0x08001264:  D10E         BNE        .L17                     ; 0x08001284
+  0x08001266:  2A08         CMP        R2, #8
+  0x08001268:  D900         BLS        .L16                     ; 0x0800126C
+  0x0800126A:  E08C         B          .L25                     ; 0x08001386
+
.L16:
+  0x0800126C:  447A         ADD        R2, PC
+  0x0800126E:  7912         LDRB       R2, [R2, #4]
+  0x08001270:  0052         LSLS       R2, R2, #1
+  0x08001272:  4497         ADD        PC, R2
+  0x08001274:  04           DC.B       0x04                     ; '\x04'
+  0x08001275:  88           DC.B       0x88                     ; '\x88'
+  0x08001276:  17           DC.B       0x17                     ; '\x17'
+  0x08001277:  88           DC.B       0x88                     ; '\x88'
+  0x08001278:  29           DC.B       0x29                     ; ')'
+  0x08001279:  88           DC.B       0x88                     ; '\x88'
+  0x0800127A:  88           DC.B       0x88                     ; '\x88'
+  0x0800127B:  88           DC.B       0x88                     ; '\x88'
+  0x0800127C:  2E           DC.B       0x2E                     ; '.'
+  0x0800127D:  00           DC.B       0x00                     ; '\0'
+  0x0800127E:  F7FF FDA5    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x08001282:  E023         B          .L19                     ; 0x080012CC
+
.L17:
+  0x08001284:  2A08         CMP        R2, #8
+  0x08001286:  D900         BLS        .L18                     ; 0x0800128A
+  0x08001288:  E07D         B          .L25                     ; 0x08001386
+
.L18:
+  0x0800128A:  46C0         NOP
+  0x0800128C:  447A         ADD        R2, PC
+  0x0800128E:  7912         LDRB       R2, [R2, #4]
+  0x08001290:  0052         LSLS       R2, R2, #1
+  0x08001292:  4497         ADD        PC, R2
+  0x08001294:  04           DC.B       0x04                     ; '\x04'
+  0x08001295:  78           DC.B       0x78                     ; 'x'
+  0x08001296:  10           DC.B       0x10                     ; '\x10'
+  0x08001297:  78           DC.B       0x78                     ; 'x'
+  0x08001298:  33           DC.B       0x33                     ; '3'
+  0x08001299:  78           DC.B       0x78                     ; 'x'
+  0x0800129A:  78           DC.B       0x78                     ; 'x'
+  0x0800129B:  78           DC.B       0x78                     ; 'x'
+  0x0800129C:  38           DC.B       0x38                     ; '8'
+  0x0800129D:  00           DC.B       0x00                     ; '\0'
+  0x0800129E:  F7FF FD95    BL         HAL_RCC_GetPCLK1Freq     ; 0x08000DCC
+  0x080012A2:  E02D         B          .L21                     ; 0x08001300
+  0x080012A4:  4857         LDR        R0, =0x40021000          ; [PC, #0x015C] [0x08001404] 
+  0x080012A6:  6800         LDR        R0, [R0]
+  0x080012A8:  0600         LSLS       R0, R0, #24
+  0x080012AA:  0F40         LSRS       R0, R0, #29
+  0x080012AC:  1C41         ADDS       R1, R0, #1
+  0x080012AE:  485F         LDR        R0, =0x02DC6C00          ; [PC, #0x017C] [0x0800142C] 
+  0x080012B0:  F004 FEE9    BL         __aeabi_uidiv            ; 0x08006086
+  0x080012B4:  E00D         B          .L20                     ; 0x080012D2
+  0x080012B6:  4853         LDR        R0, =0x40021000          ; [PC, #0x014C] [0x08001404] 
+  0x080012B8:  6800         LDR        R0, [R0]
+  0x080012BA:  0600         LSLS       R0, R0, #24
+  0x080012BC:  0F40         LSRS       R0, R0, #29
+  0x080012BE:  1C41         ADDS       R1, R0, #1
+  0x080012C0:  485A         LDR        R0, =0x02DC6C00          ; [PC, #0x0168] [0x0800142C] 
+  0x080012C2:  F004 FEE0    BL         __aeabi_uidiv            ; 0x08006086
+  0x080012C6:  E01E         B          .L22                     ; 0x08001306
+  0x080012C8:  F7FF FD56    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+
.L19:
+  0x080012CC:  2800         CMP        R0, #0
+  0x080012CE:  D02B         BEQ        .L24                     ; 0x08001328
+  0x080012D0:  6A77         LDR        R7, [R6, #36]
+
.L20:
+  0x080012D2:  0079         LSLS       R1, R7, #1
+  0x080012D4:  4A56         LDR        R2, =UARTPrescTable      ; [PC, #0x0158] [0x08001430] =0x08005EEE 
+  0x080012D6:  5A51         LDRH       R1, [R2, R1]
+  0x080012D8:  F004 FED5    BL         __aeabi_uidiv            ; 0x08006086
+  0x080012DC:  0040         LSLS       R0, R0, #1
+  0x080012DE:  6871         LDR        R1, [R6, #4]
+  0x080012E0:  084A         LSRS       R2, R1, #1
+  0x080012E2:  1810         ADDS       R0, R2, R0
+  0x080012E4:  F004 FECF    BL         __aeabi_uidiv            ; 0x08006086
+  0x080012E8:  4602         MOV        R2, R0
+  0x080012EA:  3A10         SUBS       R2, #16
+  0x080012EC:  4951         LDR        R1, =0x0000FFF0          ; [PC, #0x0144] [0x08001434] 
+  0x080012EE:  428A         CMP        R2, R1
+  0x080012F0:  D249         BCS        .L25                     ; 0x08001386
+  0x080012F2:  4001         ANDS       R1, R0
+  0x080012F4:  0700         LSLS       R0, R0, #28
+  0x080012F6:  0F40         LSRS       R0, R0, #29
+  0x080012F8:  4308         ORRS       R0, R1
+  0x080012FA:  E013         B          .L23                     ; 0x08001324
+  0x080012FC:  F7FF FD3C    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+
.L21:
+  0x08001300:  2800         CMP        R0, #0
+  0x08001302:  D011         BEQ        .L24                     ; 0x08001328
+  0x08001304:  6A77         LDR        R7, [R6, #36]
+
.L22:
+  0x08001306:  0079         LSLS       R1, R7, #1
+  0x08001308:  4A49         LDR        R2, =UARTPrescTable      ; [PC, #0x0124] [0x08001430] =0x08005EEE 
+  0x0800130A:  5A51         LDRH       R1, [R2, R1]
+  0x0800130C:  F004 FEBB    BL         __aeabi_uidiv            ; 0x08006086
+  0x08001310:  6871         LDR        R1, [R6, #4]
+  0x08001312:  084A         LSRS       R2, R1, #1
+  0x08001314:  1810         ADDS       R0, R2, R0
+  0x08001316:  F004 FEB6    BL         __aeabi_uidiv            ; 0x08006086
+  0x0800131A:  4601         MOV        R1, R0
+  0x0800131C:  3910         SUBS       R1, #16
+  0x0800131E:  4A45         LDR        R2, =0x0000FFF0          ; [PC, #0x0114] [0x08001434] 
+  0x08001320:  4291         CMP        R1, R2
+  0x08001322:  D230         BCS        .L25                     ; 0x08001386
+
.L23:
+  0x08001324:  6831         LDR        R1, [R6]
+  0x08001326:  60C8         STR        R0, [R1, #12]
+
.L24:
+  0x08001328:  2009         MOVS       R0, #9
+  0x0800132A:  9001         STR        R0, [SP, #4]
+  0x0800132C:  02C1         LSLS       R1, R0, #11
+  0x0800132E:  6830         LDR        R0, [R6]
+  0x08001330:  6842         LDR        R2, [R0, #4]
+  0x08001332:  438A         BICS       R2, R1
+  0x08001334:  6042         STR        R2, [R0, #4]
+  0x08001336:  6881         LDR        R1, [R0, #8]
+  0x08001338:  222A         MOVS       R2, #42
+  0x0800133A:  4391         BICS       R1, R2
+  0x0800133C:  6081         STR        R1, [R0, #8]
+  0x0800133E:  6801         LDR        R1, [R0]
+  0x08001340:  4321         ORRS       R1, R4
+  0x08001342:  6001         STR        R1, [R0]
+  0x08001344:  2190         MOVS       R1, #144
+  0x08001346:  2700         MOVS       R7, #0
+  0x08001348:  5077         STR        R7, [R6, R1]
+  0x0800134A:  6777         STR        R7, [R6, #116]
+  0x0800134C:  67B7         STR        R7, [R6, #120]
+  0x0800134E:  493A         LDR        R1, =0x00010001          ; [PC, #232] [0x08001438] 
+  0x08001350:  66B1         STR        R1, [R6, #104]
+  0x08001352:  493A         LDR        R1, =uwTick              ; [PC, #232] [0x0800143C] =0x2000068C 
+  0x08001354:  680D         LDR        R5, [R1]
+  0x08001356:  6801         LDR        R1, [R0]
+  0x08001358:  0709         LSLS       R1, R1, #28
+  0x0800135A:  D51B         BPL        .L27                     ; 0x08001394
+  0x0800135C:  0560         LSLS       R0, R4, #21
+  0x0800135E:  4629         MOV        R1, R5
+  0x08001360:  F000 F86E    BL         UART_WaitOnFlagUntilTimeout ; 0x08001440
+  0x08001364:  2800         CMP        R0, #0
+  0x08001366:  D014         BEQ        .L26                     ; 0x08001392
+  0x08001368:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800136C:  F384 8810    MSR        PRIMASK, R4
+  0x08001370:  6831         LDR        R1, [R6]
+  0x08001372:  680A         LDR        R2, [R1]
+  0x08001374:  2380         MOVS       R3, #128
+  0x08001376:  439A         BICS       R2, R3
+  0x08001378:  600A         STR        R2, [R1]
+  0x0800137A:  F380 8810    MSR        PRIMASK, R0
+  0x0800137E:  2020         MOVS       R0, #32
+  0x08001380:  9C02         LDR        R4, [SP, #8]
+  0x08001382:  9A03         LDR        R2, [SP, #12]
+  0x08001384:  E032         B          .L29                     ; 0x080013EC
+
.L25:
+  0x08001386:  2000         MOVS       R0, #0
+  0x08001388:  6770         STR        R0, [R6, #116]
+  0x0800138A:  67B0         STR        R0, [R6, #120]
+  0x0800138C:  482A         LDR        R0, =0x00010001          ; [PC, #168] [0x08001438] 
+  0x0800138E:  66B0         STR        R0, [R6, #104]
+  0x08001390:  E02F         B          .L30                     ; 0x080013F2
+
.L26:
+  0x08001392:  6830         LDR        R0, [R6]
+
.L27:
+  0x08001394:  6800         LDR        R0, [R0]
+  0x08001396:  0740         LSLS       R0, R0, #29
+  0x08001398:  D51F         BPL        .L28                     ; 0x080013DA
+  0x0800139A:  05A0         LSLS       R0, R4, #22
+  0x0800139C:  4629         MOV        R1, R5
+  0x0800139E:  F000 F84F    BL         UART_WaitOnFlagUntilTimeout ; 0x08001440
+  0x080013A2:  2800         CMP        R0, #0
+  0x080013A4:  D019         BEQ        .L28                     ; 0x080013DA
+  0x080013A6:  F3EF 8010    MRS        R0, PRIMASK
+  0x080013AA:  F384 8810    MSR        PRIMASK, R4
+  0x080013AE:  9901         LDR        R1, [SP, #4]
+  0x080013B0:  0149         LSLS       R1, R1, #5
+  0x080013B2:  6832         LDR        R2, [R6]
+  0x080013B4:  6813         LDR        R3, [R2]
+  0x080013B6:  438B         BICS       R3, R1
+  0x080013B8:  6013         STR        R3, [R2]
+  0x080013BA:  F380 8810    MSR        PRIMASK, R0
+  0x080013BE:  F3EF 8010    MRS        R0, PRIMASK
+  0x080013C2:  F384 8810    MSR        PRIMASK, R4
+  0x080013C6:  6831         LDR        R1, [R6]
+  0x080013C8:  688A         LDR        R2, [R1, #8]
+  0x080013CA:  43A2         BICS       R2, R4
+  0x080013CC:  608A         STR        R2, [R1, #8]
+  0x080013CE:  F380 8810    MSR        PRIMASK, R0
+  0x080013D2:  2020         MOVS       R0, #32
+  0x080013D4:  228C         MOVS       R2, #140
+  0x080013D6:  9C02         LDR        R4, [SP, #8]
+  0x080013D8:  E008         B          .L29                     ; 0x080013EC
+
.L28:
+  0x080013DA:  2088         MOVS       R0, #136
+  0x080013DC:  2120         MOVS       R1, #32
+  0x080013DE:  5031         STR        R1, [R6, R0]
+  0x080013E0:  208C         MOVS       R0, #140
+  0x080013E2:  5031         STR        R1, [R6, R0]
+  0x080013E4:  66F7         STR        R7, [R6, #108]
+  0x080013E6:  2270         MOVS       R2, #112
+  0x080013E8:  4638         MOV        R0, R7
+  0x080013EA:  463C         MOV        R4, R7
+
.L29:
+  0x080013EC:  2184         MOVS       R1, #132
+  0x080013EE:  5477         STRB       R7, [R6, R1]
+  0x080013F0:  50B0         STR        R0, [R6, R2]
+
.L30:
+  0x080013F2:  4620         MOV        R0, R4
+  0x080013F4:  B011         ADD        SP, SP, #68
+  0x080013F6:  BDF0         POP        {R4-R7, PC}
+
.L31:
+  0x080013F8:  F004 FD77    BL         Error_Handler            ; 0x08005EEA
+  0x080013FC:  200003BC     DC.W       huart1
+  0x08001400:  40013800     DC.W       0x40013800
+  0x08001404:  40021000     DC.W       0x40021000
+  0x08001408:  20000510     DC.W       hdma_usart1_rx
+  0x0800140C:  4002001C     DC.W       0x4002001C
+  0x08001410:  200004B4     DC.W       hdma_usart1_tx
+  0x08001414:  E000E418     DC.W       0xE000E418
+  0x08001418:  E000E100     DC.W       0xE000E100
+  0x0800141C:  CFFF69F3     DC.W       0xCFFF69F3
+  0x08001420:  11FFF4FF     DC.W       0x11FFF4FF
+  0x08001424:  40004400     DC.W       0x40004400
+  0x08001428:  080051C0     DC.W       080051C0               ; R_ARM_ABS32
+  0x0800142C:  02DC6C00     DC.W       0x02DC6C00
+  0x08001430:  08005EEE     DC.W       UARTPrescTable
+  0x08001434:  0000FFF0     DC.W       0x0000FFF0
+  0x08001438:  00010001     DC.W       0x00010001
+  0x0800143C:  2000068C     DC.W       uwTick
+
+

Section .text.UART_WaitOnFlagUntilTimeout from PowerPro_lto.o, size=96, align=4

+
+
UART_WaitOnFlagUntilTimeout:
+  0x08001440:  B570         PUSH       {R4-R6, LR}
+  0x08001442:  4D15         LDR        R5, =huart1              ; [PC, #84] [0x08001498] =0x200003BC 
+  0x08001444:  682A         LDR        R2, [R5]
+  0x08001446:  2401         MOVS       R4, #1
+  0x08001448:  02E3         LSLS       R3, R4, #11
+
.L1:
+  0x0800144A:  69D6         LDR        R6, [R2, #28]
+  0x0800144C:  4006         ANDS       R6, R0
+  0x0800144E:  4286         CMP        R6, R0
+  0x08001450:  D010         BEQ        .L2                      ; 0x08001474
+  0x08001452:  4E12         LDR        R6, =uwTick              ; [PC, #72] [0x0800149C] =0x2000068C 
+  0x08001454:  6836         LDR        R6, [R6]
+  0x08001456:  1A76         SUBS       R6, R6, R1
+  0x08001458:  0E76         LSRS       R6, R6, #25
+  0x0800145A:  D10D         BNE        .L3                      ; 0x08001478
+  0x0800145C:  6816         LDR        R6, [R2]
+  0x0800145E:  0776         LSLS       R6, R6, #29
+  0x08001460:  D5F3         BPL        .L1                      ; 0x0800144A
+  0x08001462:  69D6         LDR        R6, [R2, #28]
+  0x08001464:  0736         LSLS       R6, R6, #28
+  0x08001466:  D409         BMI        .L4                      ; 0x0800147C
+  0x08001468:  69D6         LDR        R6, [R2, #28]
+  0x0800146A:  421E         TST        R6, R3
+  0x0800146C:  D0ED         BEQ        .L1                      ; 0x0800144A
+  0x0800146E:  2403         MOVS       R4, #3
+  0x08001470:  2620         MOVS       R6, #32
+  0x08001472:  E005         B          .L5                      ; 0x08001480
+
.L2:
+  0x08001474:  2400         MOVS       R4, #0
+  0x08001476:  E00C         B          .L6                      ; 0x08001492
+
.L3:
+  0x08001478:  2403         MOVS       R4, #3
+  0x0800147A:  E00A         B          .L6                      ; 0x08001492
+
.L4:
+  0x0800147C:  2308         MOVS       R3, #8
+  0x0800147E:  461E         MOV        R6, R3
+
.L5:
+  0x08001480:  6213         STR        R3, [R2, #32]
+  0x08001482:  4628         MOV        R0, R5
+  0x08001484:  F000 F80C    BL         UART_EndRxTransfer       ; 0x080014A0
+  0x08001488:  2084         MOVS       R0, #132
+  0x0800148A:  2100         MOVS       R1, #0
+  0x0800148C:  5429         STRB       R1, [R5, R0]
+  0x0800148E:  2090         MOVS       R0, #144
+  0x08001490:  502E         STR        R6, [R5, R0]
+
.L6:
+  0x08001492:  4620         MOV        R0, R4
+  0x08001494:  BD70         POP        {R4-R6, PC}
+  0x08001496:  46C0         NOP
+  0x08001498:  200003BC     DC.W       huart1
+  0x0800149C:  2000068C     DC.W       uwTick
+
+

Section .text.UART_EndRxTransfer from PowerPro_lto.o, size=96, align=4

+
+
UART_EndRxTransfer:
+  0x080014A0:  B530         PUSH       {R4-R5, LR}
+  0x080014A2:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014A6:  2101         MOVS       R1, #1
+  0x080014A8:  F381 8810    MSR        PRIMASK, R1
+  0x080014AC:  2309         MOVS       R3, #9
+  0x080014AE:  015B         LSLS       R3, R3, #5
+  0x080014B0:  6804         LDR        R4, [R0]
+  0x080014B2:  6825         LDR        R5, [R4]
+  0x080014B4:  439D         BICS       R5, R3
+  0x080014B6:  6025         STR        R5, [R4]
+  0x080014B8:  F382 8810    MSR        PRIMASK, R2
+  0x080014BC:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014C0:  F381 8810    MSR        PRIMASK, R1
+  0x080014C4:  6803         LDR        R3, [R0]
+  0x080014C6:  689C         LDR        R4, [R3, #8]
+  0x080014C8:  4D0C         LDR        R5, =0xEFFFFFFE          ; [PC, #48] [0x080014FC] 
+  0x080014CA:  4025         ANDS       R5, R4
+  0x080014CC:  609D         STR        R5, [R3, #8]
+  0x080014CE:  F382 8810    MSR        PRIMASK, R2
+  0x080014D2:  6EC2         LDR        R2, [R0, #108]
+  0x080014D4:  2A01         CMP        R2, #1
+  0x080014D6:  D10A         BNE        .L1                      ; 0x080014EE
+  0x080014D8:  F3EF 8210    MRS        R2, PRIMASK
+  0x080014DC:  F381 8810    MSR        PRIMASK, R1
+  0x080014E0:  6801         LDR        R1, [R0]
+  0x080014E2:  680B         LDR        R3, [R1]
+  0x080014E4:  2410         MOVS       R4, #16
+  0x080014E6:  43A3         BICS       R3, R4
+  0x080014E8:  600B         STR        R3, [R1]
+  0x080014EA:  F382 8810    MSR        PRIMASK, R2
+
.L1:
+  0x080014EE:  218C         MOVS       R1, #140
+  0x080014F0:  2220         MOVS       R2, #32
+  0x080014F2:  5042         STR        R2, [R0, R1]
+  0x080014F4:  2100         MOVS       R1, #0
+  0x080014F6:  6741         STR        R1, [R0, #116]
+  0x080014F8:  66C1         STR        R1, [R0, #108]
+  0x080014FA:  BD30         POP        {R4-R5, PC}
+  0x080014FC:  EFFFFFFE     DC.W       0xEFFFFFFE
+
+

Section .text.UART_DMATransmitCplt from PowerPro_lto.o, size=80, align=4

+
+
UART_DMATransmitCplt:
+  0x08001500:  B530         PUSH       {R4-R5, LR}
+  0x08001502:  6A81         LDR        R1, [R0, #40]
+  0x08001504:  6800         LDR        R0, [R0]
+  0x08001506:  6800         LDR        R0, [R0]
+  0x08001508:  0680         LSLS       R0, R0, #26
+  0x0800150A:  D41A         BMI        .L1                      ; 0x08001542
+  0x0800150C:  2056         MOVS       R0, #86
+  0x0800150E:  2200         MOVS       R2, #0
+  0x08001510:  520A         STRH       R2, [R1, R0]
+  0x08001512:  F3EF 8010    MRS        R0, PRIMASK
+  0x08001516:  2201         MOVS       R2, #1
+  0x08001518:  F382 8810    MSR        PRIMASK, R2
+  0x0800151C:  680B         LDR        R3, [R1]
+  0x0800151E:  689C         LDR        R4, [R3, #8]
+  0x08001520:  2580         MOVS       R5, #128
+  0x08001522:  43AC         BICS       R4, R5
+  0x08001524:  609C         STR        R4, [R3, #8]
+  0x08001526:  F380 8810    MSR        PRIMASK, R0
+  0x0800152A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800152E:  F382 8810    MSR        PRIMASK, R2
+  0x08001532:  6809         LDR        R1, [R1]
+  0x08001534:  680A         LDR        R2, [R1]
+  0x08001536:  2340         MOVS       R3, #64
+  0x08001538:  4313         ORRS       R3, R2
+  0x0800153A:  600B         STR        R3, [R1]
+  0x0800153C:  F380 8810    MSR        PRIMASK, R0
+  0x08001540:  BD30         POP        {R4-R5, PC}
+
.L1:
+  0x08001542:  4802         LDR        R0, =0x20000026          ; [PC, #8] [0x0800154C] 
+  0x08001544:  2100         MOVS       R1, #0
+  0x08001546:  7001         STRB       R1, [R0]
+  0x08001548:  BD30         POP        {R4-R5, PC}
+  0x0800154A:  46C0         NOP
+  0x0800154C:  20000026     DC.W       20000026               ; R_ARM_ABS32
+
+

Section .text.HAL_UART_Receive_DMA from PowerPro_lto.o, size=248, align=4

+
+
HAL_UART_Receive_DMA:
+  0x08001550:  B5F0         PUSH       {R4-R7, LR}
+  0x08001552:  B083         SUB        SP, SP, #12
+  0x08001554:  4604         MOV        R4, R0
+  0x08001556:  4607         MOV        R7, R0
+  0x08001558:  3780         ADDS       R7, #128
+  0x0800155A:  68F8         LDR        R0, [R7, #12]
+  0x0800155C:  2820         CMP        R0, #32
+  0x0800155E:  D142         BNE        .L3                      ; 0x080015E6
+  0x08001560:  000A         MOVS       R2, R1
+  0x08001562:  D042         BEQ        .L4                      ; 0x080015EA
+  0x08001564:  2301         MOVS       R3, #1
+  0x08001566:  0318         LSLS       R0, R3, #12
+  0x08001568:  68A1         LDR        R1, [R4, #8]
+  0x0800156A:  4281         CMP        R1, R0
+  0x0800156C:  D104         BNE        .L1                      ; 0x08001578
+  0x0800156E:  6920         LDR        R0, [R4, #16]
+  0x08001570:  2800         CMP        R0, #0
+  0x08001572:  D101         BNE        .L1                      ; 0x08001578
+  0x08001574:  07D0         LSLS       R0, R2, #31
+  0x08001576:  D138         BNE        .L4                      ; 0x080015EA
+
.L1:
+  0x08001578:  4620         MOV        R0, R4
+  0x0800157A:  305C         ADDS       R0, #92
+  0x0800157C:  2500         MOVS       R5, #0
+  0x0800157E:  66E5         STR        R5, [R4, #108]
+  0x08001580:  6821         LDR        R1, [R4]
+  0x08001582:  6849         LDR        R1, [R1, #4]
+  0x08001584:  0209         LSLS       R1, R1, #8
+  0x08001586:  9302         STR        R3, [SP, #8]
+  0x08001588:  D50D         BPL        .L2                      ; 0x080015A6
+  0x0800158A:  F3EF 8110    MRS        R1, PRIMASK
+  0x0800158E:  9101         STR        R1, [SP, #4]
+  0x08001590:  F383 8810    MSR        PRIMASK, R3
+  0x08001594:  069B         LSLS       R3, R3, #26
+  0x08001596:  6826         LDR        R6, [R4]
+  0x08001598:  6831         LDR        R1, [R6]
+  0x0800159A:  4319         ORRS       R1, R3
+  0x0800159C:  9B02         LDR        R3, [SP, #8]
+  0x0800159E:  6031         STR        R1, [R6]
+  0x080015A0:  9901         LDR        R1, [SP, #4]
+  0x080015A2:  F381 8810    MSR        PRIMASK, R1
+
.L2:
+  0x080015A6:  613D         STR        R5, [R7, #16]
+  0x080015A8:  65A2         STR        R2, [R4, #88]
+  0x080015AA:  021E         LSLS       R6, R3, #8
+  0x080015AC:  8006         STRH       R6, [R0]
+  0x080015AE:  2022         MOVS       R0, #34
+  0x080015B0:  60F8         STR        R0, [R7, #12]
+  0x080015B2:  6838         LDR        R0, [R7]
+  0x080015B4:  2800         CMP        R0, #0
+  0x080015B6:  D01A         BEQ        .L5                      ; 0x080015EE
+  0x080015B8:  4B21         LDR        R3, =UART_DMARxHalfCplt  ; [PC, #132] [0x08001640] =0x08005EB7 
+  0x080015BA:  4631         MOV        R1, R6
+  0x080015BC:  4E21         LDR        R6, =UART_DMAReceiveCplt ; [PC, #132] [0x08001644] =0x08005E0F 
+  0x080015BE:  62C6         STR        R6, [R0, #44]
+  0x080015C0:  460E         MOV        R6, R1
+  0x080015C2:  6303         STR        R3, [R0, #48]
+  0x080015C4:  491D         LDR        R1, =UART_DMAError       ; [PC, #116] [0x0800163C] =0x08005815 
+  0x080015C6:  6341         STR        R1, [R0, #52]
+  0x080015C8:  6385         STR        R5, [R0, #56]
+  0x080015CA:  6821         LDR        R1, [R4]
+  0x080015CC:  3124         ADDS       R1, #36
+  0x080015CE:  4633         MOV        R3, R6
+  0x080015D0:  F7FF FA28    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080015D4:  9902         LDR        R1, [SP, #8]
+  0x080015D6:  2800         CMP        R0, #0
+  0x080015D8:  D009         BEQ        .L5                      ; 0x080015EE
+  0x080015DA:  2010         MOVS       R0, #16
+  0x080015DC:  6138         STR        R0, [R7, #16]
+  0x080015DE:  2020         MOVS       R0, #32
+  0x080015E0:  60F8         STR        R0, [R7, #12]
+  0x080015E2:  460D         MOV        R5, R1
+  0x080015E4:  E027         B          .L7                      ; 0x08001636
+
.L3:
+  0x080015E6:  2502         MOVS       R5, #2
+  0x080015E8:  E025         B          .L7                      ; 0x08001636
+
.L4:
+  0x080015EA:  2501         MOVS       R5, #1
+  0x080015EC:  E023         B          .L7                      ; 0x08001636
+
.L5:
+  0x080015EE:  6920         LDR        R0, [R4, #16]
+  0x080015F0:  2800         CMP        R0, #0
+  0x080015F2:  D00A         BEQ        .L6                      ; 0x0800160A
+  0x080015F4:  F3EF 8010    MRS        R0, PRIMASK
+  0x080015F8:  2101         MOVS       R1, #1
+  0x080015FA:  F381 8810    MSR        PRIMASK, R1
+  0x080015FE:  6821         LDR        R1, [R4]
+  0x08001600:  680A         LDR        R2, [R1]
+  0x08001602:  4332         ORRS       R2, R6
+  0x08001604:  600A         STR        R2, [R1]
+  0x08001606:  F380 8810    MSR        PRIMASK, R0
+
.L6:
+  0x0800160A:  F3EF 8010    MRS        R0, PRIMASK
+  0x0800160E:  2101         MOVS       R1, #1
+  0x08001610:  F381 8810    MSR        PRIMASK, R1
+  0x08001614:  6822         LDR        R2, [R4]
+  0x08001616:  6893         LDR        R3, [R2, #8]
+  0x08001618:  430B         ORRS       R3, R1
+  0x0800161A:  6093         STR        R3, [R2, #8]
+  0x0800161C:  F380 8810    MSR        PRIMASK, R0
+  0x08001620:  F3EF 8010    MRS        R0, PRIMASK
+  0x08001624:  F381 8810    MSR        PRIMASK, R1
+  0x08001628:  6821         LDR        R1, [R4]
+  0x0800162A:  688A         LDR        R2, [R1, #8]
+  0x0800162C:  2340         MOVS       R3, #64
+  0x0800162E:  4313         ORRS       R3, R2
+  0x08001630:  608B         STR        R3, [R1, #8]
+  0x08001632:  F380 8810    MSR        PRIMASK, R0
+
.L7:
+  0x08001636:  4628         MOV        R0, R5
+  0x08001638:  B003         ADD        SP, SP, #12
+  0x0800163A:  BDF0         POP        {R4-R7, PC}
+  0x0800163C:  08005815     DC.W       UART_DMAError
+  0x08001640:  08005EB7     DC.W       UART_DMARxHalfCplt
+  0x08001644:  08005E0F     DC.W       UART_DMAReceiveCplt
+
+

Section .text.UARTEx_SetNbDataToProcess from PowerPro_lto.o, size=84, align=4

+
+
UARTEx_SetNbDataToProcess:
+  0x08001648:  B5F0         PUSH       {R4-R7, LR}
+  0x0800164A:  B081         SUB        SP, SP, #4
+  0x0800164C:  4D10         LDR        R5, =huart1              ; [PC, #64] [0x08001690] =0x200003BC 
+  0x0800164E:  6E68         LDR        R0, [R5, #100]
+  0x08001650:  2800         CMP        R0, #0
+  0x08001652:  D015         BEQ        .L1                      ; 0x08001680
+  0x08001654:  6828         LDR        R0, [R5]
+  0x08001656:  6881         LDR        R1, [R0, #8]
+  0x08001658:  9100         STR        R1, [SP, #0]
+  0x0800165A:  6880         LDR        R0, [R0, #8]
+  0x0800165C:  0F40         LSRS       R0, R0, #29
+  0x0800165E:  4F0D         LDR        R7, =UARTEx_SetNbDataToProcess.denominator ; [PC, #52] [0x08001694] =0x08006870 
+  0x08001660:  5C39         LDRB       R1, [R7, R0]
+  0x08001662:  4E0D         LDR        R6, =UARTEx_SetNbDataToProcess.numerator ; [PC, #52] [0x08001698] =0x08006868 
+  0x08001664:  5C30         LDRB       R0, [R6, R0]
+  0x08001666:  00C0         LSLS       R0, R0, #3
+  0x08001668:  F004 FD0D    BL         __aeabi_uidiv            ; 0x08006086
+  0x0800166C:  4604         MOV        R4, R0
+  0x0800166E:  9800         LDR        R0, [SP, #0]
+  0x08001670:  0100         LSLS       R0, R0, #4
+  0x08001672:  0F40         LSRS       R0, R0, #29
+  0x08001674:  5C39         LDRB       R1, [R7, R0]
+  0x08001676:  5C30         LDRB       R0, [R6, R0]
+  0x08001678:  00C0         LSLS       R0, R0, #3
+  0x0800167A:  F004 FD04    BL         __aeabi_uidiv            ; 0x08006086
+  0x0800167E:  E001         B          .L2                      ; 0x08001684
+
.L1:
+  0x08001680:  2401         MOVS       R4, #1
+  0x08001682:  4620         MOV        R0, R4
+
.L2:
+  0x08001684:  2168         MOVS       R1, #104
+  0x08001686:  5268         STRH       R0, [R5, R1]
+  0x08001688:  206A         MOVS       R0, #106
+  0x0800168A:  522C         STRH       R4, [R5, R0]
+  0x0800168C:  B001         ADD        SP, SP, #4
+  0x0800168E:  BDF0         POP        {R4-R7, PC}
+  0x08001690:  200003BC     DC.W       huart1
+  0x08001694:  08006870     DC.W       UARTEx_SetNbDataToProcess.denominator
+  0x08001698:  08006868     DC.W       UARTEx_SetNbDataToProcess.numerator
+
+

Section .text.EEPROM_Write from PowerPro_lto.o, size=280, align=4

+
+
EEPROM_Write:
+  0x0800169C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800169E:  B08B         SUB        SP, SP, #44
+  0x080016A0:  493F         LDR        R1, =0x08007800          ; [PC, #252] [0x080017A0] 
+  0x080016A2:  2210         MOVS       R2, #16
+  0x080016A4:  9009         STR        R0, [SP, #36]
+  0x080016A6:  F004 FB2A    BL         memcmp                   ; 0x08005CFE
+  0x080016AA:  2800         CMP        R0, #0
+  0x080016AC:  D029         BEQ        .L4                      ; 0x08001702
+  0x080016AE:  F7FF FA95    BL         HAL_FLASH_Unlock         ; 0x08000BDC
+  0x080016B2:  4F3C         LDR        R7, =pFlash.0            ; [PC, #240] [0x080017A4] =0x20000738 
+  0x080016B4:  7838         LDRB       R0, [R7]
+  0x080016B6:  2800         CMP        R0, #0
+  0x080016B8:  4E3B         LDR        R6, =0x40022014          ; [PC, #236] [0x080017A8] 
+  0x080016BA:  D11C         BNE        .L3                      ; 0x080016F6
+  0x080016BC:  2501         MOVS       R5, #1
+  0x080016BE:  703D         STRB       R5, [R7]
+  0x080016C0:  F7FF FA64    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x080016C4:  2800         CMP        R0, #0
+  0x080016C6:  D114         BNE        .L2                      ; 0x080016F2
+  0x080016C8:  200F         MOVS       R0, #15
+  0x080016CA:  43C0         MVNS       R0, R0
+  0x080016CC:  4604         MOV        R4, R0
+
.L1:
+  0x080016CE:  6831         LDR        R1, [R6]
+  0x080016D0:  3408         ADDS       R4, #8
+  0x080016D2:  D018         BEQ        .L5                      ; 0x08001706
+  0x080016D4:  4A35         LDR        R2, =0xFFFEFF85          ; [PC, #212] [0x080017AC] 
+  0x080016D6:  4011         ANDS       R1, R2
+  0x080016D8:  1840         ADDS       R0, R0, R1
+  0x080016DA:  4935         LDR        R1, =0x0001008A          ; [PC, #212] [0x080017B0] 
+  0x080016DC:  1840         ADDS       R0, R0, R1
+  0x080016DE:  6030         STR        R0, [R6]
+  0x080016E0:  F7FF FA54    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x080016E4:  2800         CMP        R0, #0
+  0x080016E6:  4620         MOV        R0, R4
+  0x080016E8:  D0F1         BEQ        .L1                      ; 0x080016CE
+  0x080016EA:  6830         LDR        R0, [R6]
+  0x080016EC:  2102         MOVS       R1, #2
+  0x080016EE:  4388         BICS       R0, R1
+  0x080016F0:  6030         STR        R0, [R6]
+
.L2:
+  0x080016F2:  2000         MOVS       R0, #0
+  0x080016F4:  7038         STRB       R0, [R7]
+
.L3:
+  0x080016F6:  2001         MOVS       R0, #1
+  0x080016F8:  07C0         LSLS       R0, R0, #31
+  0x080016FA:  6831         LDR        R1, [R6]
+  0x080016FC:  4301         ORRS       R1, R0
+  0x080016FE:  6031         STR        R1, [R6]
+  0x08001700:  6830         LDR        R0, [R6]
+
.L4:
+  0x08001702:  B00B         ADD        SP, SP, #44
+  0x08001704:  BDF0         POP        {R4-R7, PC}
+
.L5:
+  0x08001706:  2002         MOVS       R0, #2
+  0x08001708:  4381         BICS       R1, R0
+  0x0800170A:  6031         STR        R1, [R6]
+  0x0800170C:  2200         MOVS       R2, #0
+  0x0800170E:  703A         STRB       R2, [R7]
+  0x08001710:  4823         LDR        R0, =0x08007800          ; [PC, #140] [0x080017A0] 
+  0x08001712:  1D00         ADDS       R0, R0, #4
+
.L6:
+  0x08001714:  900A         STR        R0, [SP, #40]
+  0x08001716:  2A0F         CMP        R2, #15
+  0x08001718:  D8ED         BHI        .L3                      ; 0x080016F6
+  0x0800171A:  703D         STRB       R5, [R7]
+  0x0800171C:  9909         LDR        R1, [SP, #36]
+  0x0800171E:  1888         ADDS       R0, R1, R2
+  0x08001720:  7903         LDRB       R3, [R0, #4]
+  0x08001722:  9304         STR        R3, [SP, #16]
+  0x08001724:  462C         MOV        R4, R5
+  0x08001726:  7945         LDRB       R5, [R0, #5]
+  0x08001728:  7983         LDRB       R3, [R0, #6]
+  0x0800172A:  9302         STR        R3, [SP, #8]
+  0x0800172C:  79C3         LDRB       R3, [R0, #7]
+  0x0800172E:  9301         STR        R3, [SP, #4]
+  0x08001730:  9208         STR        R2, [SP, #32]
+  0x08001732:  5C89         LDRB       R1, [R1, R2]
+  0x08001734:  9107         STR        R1, [SP, #28]
+  0x08001736:  7841         LDRB       R1, [R0, #1]
+  0x08001738:  9103         STR        R1, [SP, #12]
+  0x0800173A:  7881         LDRB       R1, [R0, #2]
+  0x0800173C:  9106         STR        R1, [SP, #24]
+  0x0800173E:  78C0         LDRB       R0, [R0, #3]
+  0x08001740:  9005         STR        R0, [SP, #20]
+  0x08001742:  F7FF FA23    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x08001746:  2800         CMP        R0, #0
+  0x08001748:  D1D3         BNE        .L2                      ; 0x080016F2
+  0x0800174A:  0228         LSLS       R0, R5, #8
+  0x0800174C:  9904         LDR        R1, [SP, #16]
+  0x0800174E:  1840         ADDS       R0, R0, R1
+  0x08001750:  9902         LDR        R1, [SP, #8]
+  0x08001752:  0409         LSLS       R1, R1, #16
+  0x08001754:  9A01         LDR        R2, [SP, #4]
+  0x08001756:  0612         LSLS       R2, R2, #24
+  0x08001758:  1851         ADDS       R1, R2, R1
+  0x0800175A:  1808         ADDS       R0, R1, R0
+  0x0800175C:  9903         LDR        R1, [SP, #12]
+  0x0800175E:  0209         LSLS       R1, R1, #8
+  0x08001760:  9A07         LDR        R2, [SP, #28]
+  0x08001762:  1889         ADDS       R1, R1, R2
+  0x08001764:  9A06         LDR        R2, [SP, #24]
+  0x08001766:  0412         LSLS       R2, R2, #16
+  0x08001768:  9B05         LDR        R3, [SP, #20]
+  0x0800176A:  061B         LSLS       R3, R3, #24
+  0x0800176C:  189A         ADDS       R2, R3, R2
+  0x0800176E:  1851         ADDS       R1, R2, R1
+  0x08001770:  6832         LDR        R2, [R6]
+  0x08001772:  4322         ORRS       R2, R4
+  0x08001774:  6032         STR        R2, [R6]
+  0x08001776:  9B0A         LDR        R3, [SP, #40]
+  0x08001778:  1F1A         SUBS       R2, R3, #4
+  0x0800177A:  6011         STR        R1, [R2]
+  0x0800177C:  F3BF 8F6F    ISB        SY
+  0x08001780:  6018         STR        R0, [R3]
+  0x08001782:  F7FF FA03    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x08001786:  6831         LDR        R1, [R6]
+  0x08001788:  43A1         BICS       R1, R4
+  0x0800178A:  6031         STR        R1, [R6]
+  0x0800178C:  2100         MOVS       R1, #0
+  0x0800178E:  7039         STRB       R1, [R7]
+  0x08001790:  2800         CMP        R0, #0
+  0x08001792:  9A08         LDR        R2, [SP, #32]
+  0x08001794:  D1AF         BNE        .L3                      ; 0x080016F6
+  0x08001796:  4625         MOV        R5, R4
+  0x08001798:  980A         LDR        R0, [SP, #40]
+  0x0800179A:  3008         ADDS       R0, #8
+  0x0800179C:  3208         ADDS       R2, #8
+  0x0800179E:  E7B9         B          .L6                      ; 0x08001714
+  0x080017A0:  08007800     DC.W       0x08007800
+  0x080017A4:  20000738     DC.W       pFlash.0
+  0x080017A8:  40022014     DC.W       0x40022014
+  0x080017AC:  FFFEFF85     DC.W       0xFFFEFF85
+  0x080017B0:  0001008A     DC.W       0x0001008A
+
+

Section .text.EEPROM_WriteDefaults from PowerPro_lto.o, size=48, align=4

+
+
EEPROM_WriteDefaults:
+  0x080017B4:  B580         PUSH       {R7, LR}
+  0x080017B6:  480A         LDR        R0, =flash_device_parameter_default ; [PC, #40] [0x080017E0] =0x20000674 
+  0x080017B8:  2100         MOVS       R1, #0
+  0x080017BA:  73C1         STRB       R1, [R0, #15]
+  0x080017BC:  2202         MOVS       R2, #2
+  0x080017BE:  7382         STRB       R2, [R0, #14]
+  0x080017C0:  7341         STRB       R1, [R0, #13]
+  0x080017C2:  2201         MOVS       R2, #1
+  0x080017C4:  7302         STRB       R2, [R0, #12]
+  0x080017C6:  72C1         STRB       R1, [R0, #11]
+  0x080017C8:  7282         STRB       R2, [R0, #10]
+  0x080017CA:  7241         STRB       R1, [R0, #9]
+  0x080017CC:  7201         STRB       R1, [R0, #8]
+  0x080017CE:  71C1         STRB       R1, [R0, #7]
+  0x080017D0:  7181         STRB       R1, [R0, #6]
+  0x080017D2:  224B         MOVS       R2, #75
+  0x080017D4:  7142         STRB       R2, [R0, #5]
+  0x080017D6:  7101         STRB       R1, [R0, #4]
+  0x080017D8:  F7FF FF60    BL         EEPROM_Write             ; 0x0800169C
+  0x080017DC:  BD80         POP        {R7, PC}
+  0x080017DE:  46C0         NOP
+  0x080017E0:  20000674     DC.W       flash_device_parameter_default
+
+

Section .text.EEPROM_ReadDeviceParameter from PowerPro_lto.o, size=36, align=4

+
+
EEPROM_ReadDeviceParameter:
+  0x080017E4:  B530         PUSH       {R4-R5, LR}
+  0x080017E6:  4806         LDR        R0, =0x08007800          ; [PC, #24] [0x08001800] 
+  0x080017E8:  8981         LDRH       R1, [R0, #12]
+  0x080017EA:  8942         LDRH       R2, [R0, #10]
+  0x080017EC:  8903         LDRH       R3, [R0, #8]
+  0x080017EE:  6804         LDR        R4, [R0]
+  0x080017F0:  6840         LDR        R0, [R0, #4]
+  0x080017F2:  4D04         LDR        R5, =sys_data            ; [PC, #16] [0x08001804] =0x20000234 
+  0x080017F4:  606C         STR        R4, [R5, #4]
+  0x080017F6:  6128         STR        R0, [R5, #16]
+  0x080017F8:  82AB         STRH       R3, [R5, #20]
+  0x080017FA:  82EA         STRH       R2, [R5, #22]
+  0x080017FC:  8329         STRH       R1, [R5, #24]
+  0x080017FE:  BD30         POP        {R4-R5, PC}
+  0x08001800:  08007800     DC.W       0x08007800
+  0x08001804:  20000234     DC.W       sys_data
+
+

Section .text.EEPROM_StoreConfig from PowerPro_lto.o, size=60, align=4

+
+
EEPROM_StoreConfig:
+  0x08001808:  B5F0         PUSH       {R4-R7, LR}
+  0x0800180A:  B085         SUB        SP, SP, #20
+  0x0800180C:  490B         LDR        R1, =0x08007800          ; [PC, #44] [0x0800183C] 
+  0x0800180E:  AA01         ADD        R2, SP, #4
+  0x08001810:  4613         MOV        R3, R2
+  0x08001812:  C9F0         LDM        R1!, {R4-R7}
+  0x08001814:  C3F0         STM        R3!, {R4-R7}
+  0x08001816:  2800         CMP        R0, #0
+  0x08001818:  4809         LDR        R0, =sys_data            ; [PC, #36] [0x08001840] =0x20000234 
+  0x0800181A:  6901         LDR        R1, [R0, #16]
+  0x0800181C:  8A83         LDRH       R3, [R0, #20]
+  0x0800181E:  8113         STRH       R3, [R2, #8]
+  0x08001820:  8AC3         LDRH       R3, [R0, #22]
+  0x08001822:  8153         STRH       R3, [R2, #10]
+  0x08001824:  8B03         LDRH       R3, [R0, #24]
+  0x08001826:  8193         STRH       R3, [R2, #12]
+  0x08001828:  9102         STR        R1, [SP, #8]
+  0x0800182A:  D001         BEQ        .L1                      ; 0x08001830
+  0x0800182C:  6840         LDR        R0, [R0, #4]
+  0x0800182E:  9001         STR        R0, [SP, #4]
+
.L1:
+  0x08001830:  A801         ADD        R0, SP, #4
+  0x08001832:  F7FF FF33    BL         EEPROM_Write             ; 0x0800169C
+  0x08001836:  B005         ADD        SP, SP, #20
+  0x08001838:  BDF0         POP        {R4-R7, PC}
+  0x0800183A:  46C0         NOP
+  0x0800183C:  08007800     DC.W       0x08007800
+  0x08001840:  20000234     DC.W       sys_data
+
+

Section .text.main from PowerPro_lto.o, size=11536, align=4

+
+
main:
+  0x08001844:  B500         PUSH       {LR}
+  0x08001846:  B0B5         SUB        SP, SP, #212
+  0x08001848:  49F6         LDR        R1, =bootLoaderMark      ; [PC, #0x03D8] [0x08001C24] =0x20000B7C 
+  0x0800184A:  7808         LDRB       R0, [R1]
+  0x0800184C:  2801         CMP        R0, #1
+  0x0800184E:  D101         BNE        .L1                      ; 0x08001854
+  0x08001850:  F002 FE43    BL         .L287                    ; 0x080044DA
+
.L1:
+  0x08001854:  4EF4         LDR        R6, =0x40022000          ; [PC, #0x03D0] [0x08001C28] 
+  0x08001856:  6A30         LDR        R0, [R6, #32]
+  0x08001858:  01C0         LSLS       R0, R0, #7
+  0x0800185A:  D51F         BPL        .L3                      ; 0x0800189C
+  0x0800185C:  48F3         LDR        R0, =0x080061EE          ; [PC, #0x03CC] [0x08001C2C] 
+  0x0800185E:  F003 FCC9    BL         puts                     ; 0x080051F4
+  0x08001862:  F7FF F9BB    BL         HAL_FLASH_Unlock         ; 0x08000BDC
+  0x08001866:  F7FF F991    BL         FLASH_WaitForLastOperation ; 0x08000B8C
+  0x0800186A:  6970         LDR        R0, [R6, #20]
+  0x0800186C:  0040         LSLS       R0, R0, #1
+  0x0800186E:  D504         BPL        .L2                      ; 0x0800187A
+  0x08001870:  48EF         LDR        R0, =0x08192A3B          ; [PC, #0x03BC] [0x08001C30] 
+  0x08001872:  60F0         STR        R0, [R6, #12]
+  0x08001874:  48EF         LDR        R0, =0x4C5D6E7F          ; [PC, #0x03BC] [0x08001C34] 
+  0x08001876:  60F0         STR        R0, [R6, #12]
+  0x08001878:  6970         LDR        R0, [R6, #20]
+
.L2:
+  0x0800187A:  4CEF         LDR        R4, =FLASH_WaitForLastOperation ; [PC, #0x03BC] [0x08001C38] =0x08000B8D 
+  0x0800187C:  47A0         BLX        R4
+  0x0800187E:  2501         MOVS       R5, #1
+  0x08001880:  0628         LSLS       R0, R5, #24
+  0x08001882:  6A31         LDR        R1, [R6, #32]
+  0x08001884:  4381         BICS       R1, R0
+  0x08001886:  6231         STR        R1, [R6, #32]
+  0x08001888:  47A0         BLX        R4
+  0x0800188A:  0468         LSLS       R0, R5, #17
+  0x0800188C:  6971         LDR        R1, [R6, #20]
+  0x0800188E:  4301         ORRS       R1, R0
+  0x08001890:  6171         STR        R1, [R6, #20]
+  0x08001892:  47A0         BLX        R4
+  0x08001894:  06E8         LSLS       R0, R5, #27
+  0x08001896:  6971         LDR        R1, [R6, #20]
+  0x08001898:  4301         ORRS       R1, R0
+  0x0800189A:  6171         STR        R1, [R6, #20]
+
.L3:
+  0x0800189C:  2003         MOVS       R0, #3
+  0x0800189E:  9015         STR        R0, [SP, #84]
+  0x080018A0:  F7FE FED8    BL         HAL_InitTick             ; 0x08000654
+  0x080018A4:  2800         CMP        R0, #0
+  0x080018A6:  4CE5         LDR        R4, =0x40021000          ; [PC, #0x0394] [0x08001C3C] 
+  0x080018A8:  D10F         BNE        .L4                      ; 0x080018CA
+  0x080018AA:  6C20         LDR        R0, [R4, #64]
+  0x080018AC:  2101         MOVS       R1, #1
+  0x080018AE:  4308         ORRS       R0, R1
+  0x080018B0:  6420         STR        R0, [R4, #64]
+  0x080018B2:  6C20         LDR        R0, [R4, #64]
+  0x080018B4:  4008         ANDS       R0, R1
+  0x080018B6:  9029         STR        R0, [SP, #164]
+  0x080018B8:  9829         LDR        R0, [SP, #164]
+  0x080018BA:  0708         LSLS       R0, R1, #28
+  0x080018BC:  6BE1         LDR        R1, [R4, #60]
+  0x080018BE:  4301         ORRS       R1, R0
+  0x080018C0:  63E1         STR        R1, [R4, #60]
+  0x080018C2:  6BE1         LDR        R1, [R4, #60]
+  0x080018C4:  4001         ANDS       R1, R0
+  0x080018C6:  9129         STR        R1, [SP, #164]
+  0x080018C8:  9829         LDR        R0, [SP, #164]
+
.L4:
+  0x080018CA:  6830         LDR        R0, [R6]
+  0x080018CC:  2107         MOVS       R1, #7
+  0x080018CE:  9123         STR        R1, [SP, #140]
+  0x080018D0:  4388         BICS       R0, R1
+  0x080018D2:  6030         STR        R0, [R6]
+  0x080018D4:  2501         MOVS       R5, #1
+  0x080018D6:  032B         LSLS       R3, R5, #12
+  0x080018D8:  68A0         LDR        R0, [R4, #8]
+  0x080018DA:  0680         LSLS       R0, R0, #26
+  0x080018DC:  0F40         LSRS       R0, R0, #29
+  0x080018DE:  4FD8         LDR        R7, =0x000003C7          ; [PC, #0x0360] [0x08001C40] 
+  0x080018E0:  48D8         LDR        R0, =0xFFFFC7FF          ; [PC, #0x0360] [0x08001C44] 
+  0x080018E2:  9314         STR        R3, [SP, #80]
+  0x080018E4:  D013         BEQ        .L6                      ; 0x0800190E
+  0x080018E6:  6821         LDR        R1, [R4]
+  0x080018E8:  4001         ANDS       R1, R0
+  0x080018EA:  4319         ORRS       R1, R3
+  0x080018EC:  6021         STR        R1, [R4]
+  0x080018EE:  0228         LSLS       R0, R5, #8
+  0x080018F0:  6821         LDR        R1, [R4]
+  0x080018F2:  4301         ORRS       R1, R0
+  0x080018F4:  6021         STR        R1, [R4]
+  0x080018F6:  48D4         LDR        R0, =uwTick              ; [PC, #0x0350] [0x08001C48] =0x2000068C 
+  0x080018F8:  6801         LDR        R1, [R0]
+
.L5:
+  0x080018FA:  463A         MOV        R2, R7
+  0x080018FC:  3239         ADDS       R2, #57
+  0x080018FE:  6823         LDR        R3, [R4]
+  0x08001900:  4213         TST        R3, R2
+  0x08001902:  D11E         BNE        .L9                      ; 0x08001942
+  0x08001904:  6802         LDR        R2, [R0]
+  0x08001906:  1A52         SUBS       R2, R2, R1
+  0x08001908:  2A02         CMP        R2, #2
+  0x0800190A:  D9F6         BLS        .L5                      ; 0x080018FA
+  0x0800190C:  E017         B          .L7                      ; 0x0800193E
+
.L6:
+  0x0800190E:  217F         MOVS       R1, #127
+  0x08001910:  0209         LSLS       R1, R1, #8
+  0x08001912:  6862         LDR        R2, [R4, #4]
+  0x08001914:  438A         BICS       R2, R1
+  0x08001916:  03A9         LSLS       R1, R5, #14
+  0x08001918:  1851         ADDS       R1, R2, R1
+  0x0800191A:  6061         STR        R1, [R4, #4]
+  0x0800191C:  6821         LDR        R1, [R4]
+  0x0800191E:  4001         ANDS       R1, R0
+  0x08001920:  4319         ORRS       R1, R3
+  0x08001922:  6021         STR        R1, [R4]
+  0x08001924:  6820         LDR        R0, [R4]
+  0x08001926:  0480         LSLS       R0, R0, #18
+  0x08001928:  0F40         LSRS       R0, R0, #29
+  0x0800192A:  49C8         LDR        R1, =0x02DC6C00          ; [PC, #0x0320] [0x08001C4C] 
+  0x0800192C:  40C1         LSRS       R1, R0
+  0x0800192E:  48C8         LDR        R0, =SystemCoreClock     ; [PC, #0x0320] [0x08001C50] =0x20000BA4 
+  0x08001930:  6001         STR        R1, [R0]
+  0x08001932:  48C8         LDR        R0, =uwTickPrio          ; [PC, #0x0320] [0x08001C54] =0x20000B94 
+  0x08001934:  6800         LDR        R0, [R0]
+  0x08001936:  F7FE FE8D    BL         HAL_InitTick             ; 0x08000654
+  0x0800193A:  2800         CMP        R0, #0
+  0x0800193C:  D008         BEQ        .L10                     ; 0x08001950
+
.L7:
+  0x0800193E:  B672         CPSID      i
+
.L8:
+  0x08001940:  E7FE         B          .L8                      ; 0x08001940
+
.L9:
+  0x08001942:  207F         MOVS       R0, #127
+  0x08001944:  0200         LSLS       R0, R0, #8
+  0x08001946:  6861         LDR        R1, [R4, #4]
+  0x08001948:  4381         BICS       R1, R0
+  0x0800194A:  03A8         LSLS       R0, R5, #14
+  0x0800194C:  1808         ADDS       R0, R1, R0
+  0x0800194E:  6060         STR        R0, [R4, #4]
+
.L10:
+  0x08001950:  6830         LDR        R0, [R6]
+  0x08001952:  207B         MOVS       R0, #123
+  0x08001954:  0200         LSLS       R0, R0, #8
+  0x08001956:  68A1         LDR        R1, [R4, #8]
+  0x08001958:  4381         BICS       R1, R0
+  0x0800195A:  220B         MOVS       R2, #11
+  0x0800195C:  0210         LSLS       R0, R2, #8
+  0x0800195E:  1808         ADDS       R0, R1, R0
+  0x08001960:  60A0         STR        R0, [R4, #8]
+  0x08001962:  48BD         LDR        R0, =0xFFFFF0FE          ; [PC, #0x02F4] [0x08001C58] 
+  0x08001964:  1C40         ADDS       R0, R0, #1
+  0x08001966:  68A1         LDR        R1, [R4, #8]
+  0x08001968:  4001         ANDS       R1, R0
+  0x0800196A:  60A1         STR        R1, [R4, #8]
+  0x0800196C:  4639         MOV        R1, R7
+  0x0800196E:  3139         ADDS       R1, #57
+  0x08001970:  6820         LDR        R0, [R4]
+  0x08001972:  9122         STR        R1, [SP, #136]
+  0x08001974:  4208         TST        R0, R1
+  0x08001976:  D03C         BEQ        .L15                     ; 0x080019F2
+  0x08001978:  68A0         LDR        R0, [R4, #8]
+  0x0800197A:  9923         LDR        R1, [SP, #140]
+  0x0800197C:  4388         BICS       R0, R1
+  0x0800197E:  60A0         STR        R0, [R4, #8]
+  0x08001980:  48B1         LDR        R0, =uwTick              ; [PC, #0x02C4] [0x08001C48] =0x2000068C 
+  0x08001982:  6800         LDR        R0, [R0]
+
.L11:
+  0x08001984:  68A1         LDR        R1, [R4, #8]
+  0x08001986:  0689         LSLS       R1, R1, #26
+  0x08001988:  0F49         LSRS       R1, R1, #29
+  0x0800198A:  D006         BEQ        .L12                     ; 0x0800199A
+  0x0800198C:  49AE         LDR        R1, =uwTick              ; [PC, #0x02B8] [0x08001C48] =0x2000068C 
+  0x0800198E:  6809         LDR        R1, [R1]
+  0x08001990:  1A09         SUBS       R1, R1, R0
+  0x08001992:  4BB2         LDR        R3, =0x00001388          ; [PC, #0x02C8] [0x08001C5C] 
+  0x08001994:  4299         CMP        R1, R3
+  0x08001996:  D9F5         BLS        .L11                     ; 0x08001984
+  0x08001998:  E02B         B          .L15                     ; 0x080019F2
+
.L12:
+  0x0800199A:  6830         LDR        R0, [R6]
+  0x0800199C:  0740         LSLS       R0, R0, #29
+  0x0800199E:  D00F         BEQ        .L14                     ; 0x080019C0
+  0x080019A0:  6830         LDR        R0, [R6]
+  0x080019A2:  9923         LDR        R1, [SP, #140]
+  0x080019A4:  4388         BICS       R0, R1
+  0x080019A6:  6030         STR        R0, [R6]
+  0x080019A8:  48A7         LDR        R0, =uwTick              ; [PC, #0x029C] [0x08001C48] =0x2000068C 
+  0x080019AA:  6800         LDR        R0, [R0]
+
.L13:
+  0x080019AC:  6831         LDR        R1, [R6]
+  0x080019AE:  0749         LSLS       R1, R1, #29
+  0x080019B0:  D006         BEQ        .L14                     ; 0x080019C0
+  0x080019B2:  49A5         LDR        R1, =uwTick              ; [PC, #0x0294] [0x08001C48] =0x2000068C 
+  0x080019B4:  6809         LDR        R1, [R1]
+  0x080019B6:  1A09         SUBS       R1, R1, R0
+  0x080019B8:  4BA8         LDR        R3, =0x00001388          ; [PC, #0x02A0] [0x08001C5C] 
+  0x080019BA:  4299         CMP        R1, R3
+  0x080019BC:  D9F6         BLS        .L13                     ; 0x080019AC
+  0x080019BE:  E018         B          .L15                     ; 0x080019F2
+
.L14:
+  0x080019C0:  9823         LDR        R0, [SP, #140]
+  0x080019C2:  0300         LSLS       R0, R0, #12
+  0x080019C4:  68A1         LDR        R1, [R4, #8]
+  0x080019C6:  4381         BICS       R1, R0
+  0x080019C8:  60A1         STR        R1, [R4, #8]
+  0x080019CA:  9206         STR        R2, [SP, #24]
+  0x080019CC:  F7FF F9D4    BL         HAL_RCC_GetSysClockFreq  ; 0x08000D78
+  0x080019D0:  68A1         LDR        R1, [R4, #8]
+  0x080019D2:  0989         LSRS       R1, R1, #6
+  0x080019D4:  263C         MOVS       R6, #60
+  0x080019D6:  4031         ANDS       R1, R6
+  0x080019D8:  4AA1         LDR        R2, =AHBPrescTable       ; [PC, #0x0284] [0x08001C60] =0x08005160 
+  0x080019DA:  5851         LDR        R1, [R2, R1]
+  0x080019DC:  221F         MOVS       R2, #31
+  0x080019DE:  400A         ANDS       R2, R1
+  0x080019E0:  40D0         LSRS       R0, R2
+  0x080019E2:  499B         LDR        R1, =SystemCoreClock     ; [PC, #0x026C] [0x08001C50] =0x20000BA4 
+  0x080019E4:  6008         STR        R0, [R1]
+  0x080019E6:  489B         LDR        R0, =uwTickPrio          ; [PC, #0x026C] [0x08001C54] =0x20000B94 
+  0x080019E8:  6800         LDR        R0, [R0]
+  0x080019EA:  F7FE FE33    BL         HAL_InitTick             ; 0x08000654
+  0x080019EE:  2800         CMP        R0, #0
+  0x080019F0:  D001         BEQ        .L17                     ; 0x080019F6
+
.L15:
+  0x080019F2:  B672         CPSID      i
+
.L16:
+  0x080019F4:  E7FE         B          .L16                     ; 0x080019F4
+
.L17:
+  0x080019F6:  223C         MOVS       R2, #60
+  0x080019F8:  2600         MOVS       R6, #0
+  0x080019FA:  962D         STR        R6, [SP, #180]
+  0x080019FC:  962C         STR        R6, [SP, #176]
+  0x080019FE:  6B60         LDR        R0, [R4, #52]
+  0x08001A00:  2102         MOVS       R1, #2
+  0x08001A02:  4308         ORRS       R0, R1
+  0x08001A04:  6360         STR        R0, [R4, #52]
+  0x08001A06:  6B60         LDR        R0, [R4, #52]
+  0x08001A08:  9112         STR        R1, [SP, #72]
+  0x08001A0A:  4008         ANDS       R0, R1
+  0x08001A0C:  9030         STR        R0, [SP, #192]
+  0x08001A0E:  9830         LDR        R0, [SP, #192]
+  0x08001A10:  6B60         LDR        R0, [R4, #52]
+  0x08001A12:  2104         MOVS       R1, #4
+  0x08001A14:  4308         ORRS       R0, R1
+  0x08001A16:  6360         STR        R0, [R4, #52]
+  0x08001A18:  6B60         LDR        R0, [R4, #52]
+  0x08001A1A:  910F         STR        R1, [SP, #60]
+  0x08001A1C:  4008         ANDS       R0, R1
+  0x08001A1E:  9030         STR        R0, [SP, #192]
+  0x08001A20:  9830         LDR        R0, [SP, #192]
+  0x08001A22:  6B60         LDR        R0, [R4, #52]
+  0x08001A24:  4328         ORRS       R0, R5
+  0x08001A26:  6360         STR        R0, [R4, #52]
+  0x08001A28:  6B60         LDR        R0, [R4, #52]
+  0x08001A2A:  4028         ANDS       R0, R5
+  0x08001A2C:  9030         STR        R0, [SP, #192]
+  0x08001A2E:  9830         LDR        R0, [SP, #192]
+  0x08001A30:  9915         LDR        R1, [SP, #84]
+  0x08001A32:  038B         LSLS       R3, R1, #14
+  0x08001A34:  931E         STR        R3, [SP, #120]
+  0x08001A36:  498B         LDR        R1, =0x50000818          ; [PC, #0x022C] [0x08001C64] 
+  0x08001A38:  610B         STR        R3, [R1, #16]
+  0x08001A3A:  0229         LSLS       R1, R5, #8
+  0x08001A3C:  9110         STR        R1, [SP, #64]
+  0x08001A3E:  4B8A         LDR        R3, =0x50000010          ; [PC, #0x0228] [0x08001C68] 
+  0x08001A40:  6199         STR        R1, [R3, #24]
+  0x08001A42:  498A         LDR        R1, =0x50000410          ; [PC, #0x0228] [0x08001C6C] 
+  0x08001A44:  2338         MOVS       R3, #56
+  0x08001A46:  9320         STR        R3, [SP, #128]
+  0x08001A48:  618B         STR        R3, [R1, #24]
+  0x08001A4A:  952B         STR        R5, [SP, #172]
+  0x08001A4C:  962A         STR        R6, [SP, #168]
+  0x08001A4E:  9729         STR        R7, [SP, #164]
+  0x08001A50:  3910         SUBS       R1, #16
+  0x08001A52:  4608         MOV        R0, R1
+  0x08001A54:  911F         STR        R1, [SP, #124]
+  0x08001A56:  921D         STR        R2, [SP, #116]
+  0x08001A58:  A929         ADD        R1, SP, #164
+  0x08001A5A:  9121         STR        R1, [SP, #132]
+  0x08001A5C:  4F84         LDR        R7, =HAL_GPIO_Init       ; [PC, #0x0210] [0x08001C70] =0x08000BFD 
+  0x08001A5E:  47B8         BLX        R7
+  0x08001A60:  962C         STR        R6, [SP, #176]
+  0x08001A62:  962B         STR        R6, [SP, #172]
+  0x08001A64:  952A         STR        R5, [SP, #168]
+  0x08001A66:  981E         LDR        R0, [SP, #120]
+  0x08001A68:  9029         STR        R0, [SP, #164]
+  0x08001A6A:  487E         LDR        R0, =0x50000818          ; [PC, #0x01F8] [0x08001C64] 
+  0x08001A6C:  3818         SUBS       R0, #24
+  0x08001A6E:  901E         STR        R0, [SP, #120]
+  0x08001A70:  9921         LDR        R1, [SP, #132]
+  0x08001A72:  47B8         BLX        R7
+  0x08001A74:  952B         STR        R5, [SP, #172]
+  0x08001A76:  962A         STR        R6, [SP, #168]
+  0x08001A78:  9815         LDR        R0, [SP, #84]
+  0x08001A7A:  9029         STR        R0, [SP, #164]
+  0x08001A7C:  4F7A         LDR        R7, =0x50000010          ; [PC, #0x01E8] [0x08001C68] 
+  0x08001A7E:  3F10         SUBS       R7, #16
+  0x08001A80:  4638         MOV        R0, R7
+  0x08001A82:  9921         LDR        R1, [SP, #132]
+  0x08001A84:  4A7A         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01E8] [0x08001C70] =0x08000BFD 
+  0x08001A86:  4790         BLX        R2
+  0x08001A88:  962C         STR        R6, [SP, #176]
+  0x08001A8A:  962B         STR        R6, [SP, #172]
+  0x08001A8C:  952A         STR        R5, [SP, #168]
+  0x08001A8E:  9810         LDR        R0, [SP, #64]
+  0x08001A90:  9029         STR        R0, [SP, #164]
+  0x08001A92:  4638         MOV        R0, R7
+  0x08001A94:  9921         LDR        R1, [SP, #132]
+  0x08001A96:  4A76         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01D8] [0x08001C70] =0x08000BFD 
+  0x08001A98:  4790         BLX        R2
+  0x08001A9A:  962B         STR        R6, [SP, #172]
+  0x08001A9C:  962A         STR        R6, [SP, #168]
+  0x08001A9E:  2040         MOVS       R0, #64
+  0x08001AA0:  9007         STR        R0, [SP, #28]
+  0x08001AA2:  9029         STR        R0, [SP, #164]
+  0x08001AA4:  981E         LDR        R0, [SP, #120]
+  0x08001AA6:  9921         LDR        R1, [SP, #132]
+  0x08001AA8:  4A71         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01C4] [0x08001C70] =0x08000BFD 
+  0x08001AAA:  4790         BLX        R2
+  0x08001AAC:  962B         STR        R6, [SP, #172]
+  0x08001AAE:  962A         STR        R6, [SP, #168]
+  0x08001AB0:  2009         MOVS       R0, #9
+  0x08001AB2:  0300         LSLS       R0, R0, #12
+  0x08001AB4:  9029         STR        R0, [SP, #164]
+  0x08001AB6:  9709         STR        R7, [SP, #36]
+  0x08001AB8:  4638         MOV        R0, R7
+  0x08001ABA:  9F21         LDR        R7, [SP, #132]
+  0x08001ABC:  4639         MOV        R1, R7
+  0x08001ABE:  4A6C         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x01B0] [0x08001C70] =0x08000BFD 
+  0x08001AC0:  4790         BLX        R2
+  0x08001AC2:  962C         STR        R6, [SP, #176]
+  0x08001AC4:  962B         STR        R6, [SP, #172]
+  0x08001AC6:  952A         STR        R5, [SP, #168]
+  0x08001AC8:  9820         LDR        R0, [SP, #128]
+  0x08001ACA:  9029         STR        R0, [SP, #164]
+  0x08001ACC:  981F         LDR        R0, [SP, #124]
+  0x08001ACE:  4639         MOV        R1, R7
+  0x08001AD0:  4A67         LDR        R2, =HAL_GPIO_Init       ; [PC, #0x019C] [0x08001C70] =0x08000BFD 
+  0x08001AD2:  4790         BLX        R2
+  0x08001AD4:  6BA0         LDR        R0, [R4, #56]
+  0x08001AD6:  4328         ORRS       R0, R5
+  0x08001AD8:  63A0         STR        R0, [R4, #56]
+  0x08001ADA:  6BA0         LDR        R0, [R4, #56]
+  0x08001ADC:  4028         ANDS       R0, R5
+  0x08001ADE:  9029         STR        R0, [SP, #164]
+  0x08001AE0:  9829         LDR        R0, [SP, #164]
+  0x08001AE2:  23FF         MOVS       R3, #255
+  0x08001AE4:  0218         LSLS       R0, R3, #8
+  0x08001AE6:  4963         LDR        R1, =0xE000E408          ; [PC, #0x018C] [0x08001C74] 
+  0x08001AE8:  680A         LDR        R2, [R1]
+  0x08001AEA:  4382         BICS       R2, R0
+  0x08001AEC:  600A         STR        R2, [R1]
+  0x08001AEE:  0268         LSLS       R0, R5, #9
+  0x08001AF0:  4A61         LDR        R2, =0xE000E100          ; [PC, #0x0184] [0x08001C78] 
+  0x08001AF2:  6010         STR        R0, [R2]
+  0x08001AF4:  9313         STR        R3, [SP, #76]
+  0x08001AF6:  0418         LSLS       R0, R3, #16
+  0x08001AF8:  680B         LDR        R3, [R1]
+  0x08001AFA:  4383         BICS       R3, R0
+  0x08001AFC:  600B         STR        R3, [R1]
+  0x08001AFE:  9822         LDR        R0, [SP, #136]
+  0x08001B00:  6010         STR        R0, [R2]
+  0x08001B02:  4A5E         LDR        R2, =hadc1               ; [PC, #0x0178] [0x08001C7C] =0x20000450 
+  0x08001B04:  981D         LDR        R0, [SP, #116]
+  0x08001B06:  5415         STRB       R5, [R2, R0]
+  0x08001B08:  202C         MOVS       R0, #44
+  0x08001B0A:  9008         STR        R0, [SP, #32]
+  0x08001B0C:  5415         STRB       R5, [R2, R0]
+  0x08001B0E:  2720         MOVS       R7, #32
+  0x08001B10:  55D6         STRB       R6, [R2, R7]
+  0x08001B12:  2080         MOVS       R0, #128
+  0x08001B14:  211C         MOVS       R1, #28
+  0x08001B16:  9104         STR        R1, [SP, #16]
+  0x08001B18:  6411         STR        R1, [R2, #64]
+  0x08001B1A:  900A         STR        R0, [SP, #40]
+  0x08001B1C:  6450         STR        R0, [R2, #68]
+  0x08001B1E:  6496         STR        R6, [R2, #72]
+  0x08001B20:  64D6         STR        R6, [R2, #76]
+  0x08001B22:  6316         STR        R6, [R2, #48]
+  0x08001B24:  9823         LDR        R0, [SP, #140]
+  0x08001B26:  6350         STR        R0, [R2, #52]
+  0x08001B28:  6256         STR        R6, [R2, #36]
+  0x08001B2A:  6296         STR        R6, [R2, #40]
+  0x08001B2C:  61D5         STR        R5, [R2, #28]
+  0x08001B2E:  7695         STRB       R5, [R2, #26]
+  0x08001B30:  8316         STRH       R6, [R2, #24]
+  0x08001B32:  2108         MOVS       R1, #8
+  0x08001B34:  4852         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0148] [0x08001C80] 
+  0x08001B36:  3018         ADDS       R0, #24
+  0x08001B38:  4B52         LDR        R3, =0x40012400          ; [PC, #0x0148] [0x08001C84] 
+  0x08001B3A:  6013         STR        R3, [R2]
+  0x08001B3C:  6050         STR        R0, [R2, #4]
+  0x08001B3E:  6096         STR        R6, [R2, #8]
+  0x08001B40:  60D6         STR        R6, [R2, #12]
+  0x08001B42:  6110         STR        R0, [R2, #16]
+  0x08001B44:  911B         STR        R1, [SP, #108]
+  0x08001B46:  6151         STR        R1, [R2, #20]
+  0x08001B48:  9626         STR        R6, [SP, #152]
+  0x08001B4A:  9625         STR        R6, [SP, #148]
+  0x08001B4C:  9624         STR        R6, [SP, #144]
+  0x08001B4E:  9621         STR        R6, [SP, #132]
+  0x08001B50:  9627         STR        R6, [SP, #156]
+  0x08001B52:  4616         MOV        R6, R2
+  0x08001B54:  6D90         LDR        R0, [R2, #88]
+  0x08001B56:  2800         CMP        R0, #0
+  0x08001B58:  9720         STR        R7, [SP, #128]
+  0x08001B5A:  D148         BNE        .L20                     ; 0x08001BEE
+  0x08001B5C:  9034         STR        R0, [SP, #208]
+  0x08001B5E:  901F         STR        R0, [SP, #124]
+  0x08001B60:  9033         STR        R0, [SP, #204]
+  0x08001B62:  A829         ADD        R0, SP, #164
+  0x08001B64:  901E         STR        R0, [SP, #120]
+  0x08001B66:  1D00         ADDS       R0, R0, #4
+  0x08001B68:  2118         MOVS       R1, #24
+  0x08001B6A:  F004 FB22    BL         __aeabi_memclr           ; 0x080061B2
+  0x08001B6E:  9729         STR        R7, [SP, #164]
+  0x08001B70:  981E         LDR        R0, [SP, #120]
+  0x08001B72:  F7FF F94B    BL         HAL_RCCEx_PeriphCLKConfig ; 0x08000E0C
+  0x08001B76:  2800         CMP        R0, #0
+  0x08001B78:  D000         BEQ        .L18                     ; 0x08001B7C
+  0x08001B7A:  E2DC         B          .L61                     ; 0x08002136
+
.L18:
+  0x08001B7C:  2201         MOVS       R2, #1
+  0x08001B7E:  0510         LSLS       R0, R2, #20
+  0x08001B80:  6C21         LDR        R1, [R4, #64]
+  0x08001B82:  4301         ORRS       R1, R0
+  0x08001B84:  6421         STR        R1, [R4, #64]
+  0x08001B86:  6C21         LDR        R1, [R4, #64]
+  0x08001B88:  4001         ANDS       R1, R0
+  0x08001B8A:  9128         STR        R1, [SP, #160]
+  0x08001B8C:  9828         LDR        R0, [SP, #160]
+  0x08001B8E:  6B60         LDR        R0, [R4, #52]
+  0x08001B90:  921E         STR        R2, [SP, #120]
+  0x08001B92:  4310         ORRS       R0, R2
+  0x08001B94:  6360         STR        R0, [R4, #52]
+  0x08001B96:  6B60         LDR        R0, [R4, #52]
+  0x08001B98:  4010         ANDS       R0, R2
+  0x08001B9A:  9028         STR        R0, [SP, #160]
+  0x08001B9C:  9F1F         LDR        R7, [SP, #124]
+  0x08001B9E:  9732         STR        R7, [SP, #200]
+  0x08001BA0:  2003         MOVS       R0, #3
+  0x08001BA2:  9031         STR        R0, [SP, #196]
+  0x08001BA4:  981D         LDR        R0, [SP, #116]
+  0x08001BA6:  9030         STR        R0, [SP, #192]
+  0x08001BA8:  9828         LDR        R0, [SP, #160]
+  0x08001BAA:  A930         ADD        R1, SP, #192
+  0x08001BAC:  9809         LDR        R0, [SP, #36]
+  0x08001BAE:  F7FF F825    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x08001BB2:  981E         LDR        R0, [SP, #120]
+  0x08001BB4:  02C2         LSLS       R2, R0, #11
+  0x08001BB6:  4834         LDR        R0, =hdma_adc1           ; [PC, #208] [0x08001C88] =0x2000056C 
+  0x08001BB8:  6207         STR        R7, [R0, #32]
+  0x08001BBA:  4934         LDR        R1, =0x40020008          ; [PC, #208] [0x08001C8C] 
+  0x08001BBC:  6001         STR        R1, [R0]
+  0x08001BBE:  2105         MOVS       R1, #5
+  0x08001BC0:  6041         STR        R1, [R0, #4]
+  0x08001BC2:  6087         STR        R7, [R0, #8]
+  0x08001BC4:  60C7         STR        R7, [R0, #12]
+  0x08001BC6:  990A         LDR        R1, [SP, #40]
+  0x08001BC8:  6101         STR        R1, [R0, #16]
+  0x08001BCA:  9910         LDR        R1, [SP, #64]
+  0x08001BCC:  6141         STR        R1, [R0, #20]
+  0x08001BCE:  6182         STR        R2, [R0, #24]
+  0x08001BD0:  9F20         LDR        R7, [SP, #128]
+  0x08001BD2:  61C7         STR        R7, [R0, #28]
+  0x08001BD4:  F7FE FEB6    BL         HAL_DMA_Init             ; 0x08000944
+  0x08001BD8:  2800         CMP        R0, #0
+  0x08001BDA:  D000         BEQ        .L19                     ; 0x08001BDE
+  0x08001BDC:  E2AB         B          .L61                     ; 0x08002136
+
.L19:
+  0x08001BDE:  2054         MOVS       R0, #84
+  0x08001BE0:  991F         LDR        R1, [SP, #124]
+  0x08001BE2:  5431         STRB       R1, [R6, R0]
+  0x08001BE4:  4828         LDR        R0, =hdma_adc1           ; [PC, #160] [0x08001C88] =0x2000056C 
+  0x08001BE6:  6286         STR        R6, [R0, #40]
+  0x08001BE8:  6530         STR        R0, [R6, #80]
+  0x08001BEA:  65F1         STR        R1, [R6, #92]
+  0x08001BEC:  6833         LDR        R3, [R6]
+
.L20:
+  0x08001BEE:  0728         LSLS       R0, R5, #28
+  0x08001BF0:  901F         STR        R0, [SP, #124]
+  0x08001BF2:  6898         LDR        R0, [R3, #8]
+  0x08001BF4:  00C0         LSLS       R0, R0, #3
+  0x08001BF6:  9F12         LDR        R7, [SP, #72]
+  0x08001BF8:  4A15         LDR        R2, =SystemCoreClock     ; [PC, #84] [0x08001C50] =0x20000BA4 
+  0x08001BFA:  931E         STR        R3, [SP, #120]
+  0x08001BFC:  D44C         BMI        .L22                     ; 0x08001C98
+  0x08001BFE:  6898         LDR        R0, [R3, #8]
+  0x08001C00:  4923         LDR        R1, =0x6FFFFFE8          ; [PC, #140] [0x08001C90] 
+  0x08001C02:  4001         ANDS       R1, R0
+  0x08001C04:  981F         LDR        R0, [SP, #124]
+  0x08001C06:  4301         ORRS       R1, R0
+  0x08001C08:  6099         STR        R1, [R3, #8]
+  0x08001C0A:  6810         LDR        R0, [R2]
+  0x08001C0C:  4921         LDR        R1, =0x00030D40          ; [PC, #132] [0x08001C94] 
+  0x08001C0E:  F004 FA3A    BL         __aeabi_uidiv            ; 0x08006086
+  0x08001C12:  9B1E         LDR        R3, [SP, #120]
+  0x08001C14:  0040         LSLS       R0, R0, #1
+
.L21:
+  0x08001C16:  9027         STR        R0, [SP, #156]
+  0x08001C18:  9827         LDR        R0, [SP, #156]
+  0x08001C1A:  2800         CMP        R0, #0
+  0x08001C1C:  D03C         BEQ        .L22                     ; 0x08001C98
+  0x08001C1E:  9827         LDR        R0, [SP, #156]
+  0x08001C20:  1E40         SUBS       R0, R0, #1
+  0x08001C22:  E7F8         B          .L21                     ; 0x08001C16
+  0x08001C24:  20000B7C     DC.W       bootLoaderMark
+  0x08001C28:  40022000     DC.W       0x40022000
+  0x08001C2C:  080061EE     DC.W       080061EE               ; R_ARM_ABS32
+  0x08001C30:  08192A3B     DC.W       0x08192A3B
+  0x08001C34:  4C5D6E7F     DC.W       0x4C5D6E7F
+  0x08001C38:  08000B8D     DC.W       FLASH_WaitForLastOperation
+  0x08001C3C:  40021000     DC.W       0x40021000
+  0x08001C40:  000003C7     DC.W       0x000003C7
+  0x08001C44:  FFFFC7FF     DC.W       0xFFFFC7FF
+  0x08001C48:  2000068C     DC.W       uwTick
+  0x08001C4C:  02DC6C00     DC.W       0x02DC6C00
+  0x08001C50:  20000BA4     DC.W       SystemCoreClock
+  0x08001C54:  20000B94     DC.W       uwTickPrio
+  0x08001C58:  FFFFF0FE     DC.W       0xFFFFF0FE
+  0x08001C5C:  00001388     DC.W       0x00001388
+  0x08001C60:  08005160     DC.W       AHBPrescTable
+  0x08001C64:  50000818     DC.W       0x50000818
+  0x08001C68:  50000010     DC.W       0x50000010
+  0x08001C6C:  50000410     DC.W       0x50000410
+  0x08001C70:  08000BFD     DC.W       HAL_GPIO_Init
+  0x08001C74:  E000E408     DC.W       0xE000E408
+  0x08001C78:  E000E100     DC.W       0xE000E100
+  0x08001C7C:  20000450     DC.W       hadc1
+  0x08001C80:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08001C84:  40012400     DC.W       0x40012400
+  0x08001C88:  2000056C     DC.W       hdma_adc1
+  0x08001C8C:  40020008     DC.W       0x40020008
+  0x08001C90:  6FFFFFE8     DC.W       0x6FFFFFE8
+  0x08001C94:  00030D40     DC.W       0x00030D40
+
.L22:
+  0x08001C98:  6899         LDR        R1, [R3, #8]
+  0x08001C9A:  981F         LDR        R0, [SP, #124]
+  0x08001C9C:  4001         ANDS       R1, R0
+  0x08001C9E:  911A         STR        R1, [SP, #104]
+  0x08001CA0:  D107         BNE        .L23                     ; 0x08001CB2
+  0x08001CA2:  6DB0         LDR        R0, [R6, #88]
+  0x08001CA4:  2110         MOVS       R1, #16
+  0x08001CA6:  4301         ORRS       R1, R0
+  0x08001CA8:  65B1         STR        R1, [R6, #88]
+  0x08001CAA:  6DF0         LDR        R0, [R6, #92]
+  0x08001CAC:  2101         MOVS       R1, #1
+  0x08001CAE:  4301         ORRS       R1, R0
+  0x08001CB0:  65F1         STR        R1, [R6, #92]
+
.L23:
+  0x08001CB2:  6898         LDR        R0, [R3, #8]
+  0x08001CB4:  990F         LDR        R1, [SP, #60]
+  0x08001CB6:  4008         ANDS       R0, R1
+  0x08001CB8:  6DB2         LDR        R2, [R6, #88]
+  0x08001CBA:  2110         MOVS       R1, #16
+  0x08001CBC:  400A         ANDS       R2, R1
+  0x08001CBE:  1810         ADDS       R0, R2, R0
+  0x08001CC0:  6DB0         LDR        R0, [R6, #88]
+  0x08001CC2:  D001         BEQ        .L24                     ; 0x08001CC8
+  0x08001CC4:  F002 FC11    BL         .L289                    ; 0x080044EA
+
.L24:
+  0x08001CC8:  49CE         LDR        R1, =0xFFFFFEFD          ; [PC, #0x0338] [0x08002004] 
+  0x08001CCA:  4008         ANDS       R0, R1
+  0x08001CCC:  1C80         ADDS       R0, R0, #2
+  0x08001CCE:  65B0         STR        R0, [R6, #88]
+  0x08001CD0:  6930         LDR        R0, [R6, #16]
+  0x08001CD2:  901C         STR        R0, [SP, #112]
+  0x08001CD4:  6898         LDR        R0, [R3, #8]
+  0x08001CD6:  07C0         LSLS       R0, R0, #31
+  0x08001CD8:  D174         BNE        .L33                     ; 0x08001DC4
+  0x08001CDA:  6B30         LDR        R0, [R6, #48]
+  0x08001CDC:  2800         CMP        R0, #0
+  0x08001CDE:  9B14         LDR        R3, [SP, #80]
+  0x08001CE0:  D100         BNE        .L25                     ; 0x08001CE4
+  0x08001CE2:  2300         MOVS       R3, #0
+
.L25:
+  0x08001CE4:  2001         MOVS       R0, #1
+  0x08001CE6:  991C         LDR        R1, [SP, #112]
+  0x08001CE8:  2900         CMP        R1, #0
+  0x08001CEA:  9019         STR        R0, [SP, #100]
+  0x08001CEC:  DA03         BGE        .L26                     ; 0x08001CF6
+  0x08001CEE:  48C6         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0318] [0x08002008] 
+  0x08001CF0:  3017         ADDS       R0, #23
+  0x08001CF2:  4008         ANDS       R0, R1
+  0x08001CF4:  E000         B          .L27                     ; 0x08001CF8
+
.L26:
+  0x08001CF6:  0540         LSLS       R0, R0, #21
+
.L27:
+  0x08001CF8:  68B2         LDR        R2, [R6, #8]
+  0x08001CFA:  4302         ORRS       R2, R0
+  0x08001CFC:  7E30         LDRB       R0, [R6, #24]
+  0x08001CFE:  0380         LSLS       R0, R0, #14
+  0x08001D00:  4310         ORRS       R0, R2
+  0x08001D02:  7E72         LDRB       R2, [R6, #25]
+  0x08001D04:  03D2         LSLS       R2, R2, #15
+  0x08001D06:  4302         ORRS       R2, R0
+  0x08001D08:  7EB0         LDRB       R0, [R6, #26]
+  0x08001D0A:  0347         LSLS       R7, R0, #13
+  0x08001D0C:  4317         ORRS       R7, R2
+  0x08001D0E:  68F2         LDR        R2, [R6, #12]
+  0x08001D10:  433A         ORRS       R2, R7
+  0x08001D12:  431A         ORRS       R2, R3
+  0x08001D14:  9908         LDR        R1, [SP, #32]
+  0x08001D16:  5C73         LDRB       R3, [R6, R1]
+  0x08001D18:  005B         LSLS       R3, R3, #1
+  0x08001D1A:  4313         ORRS       R3, R2
+  0x08001D1C:  9920         LDR        R1, [SP, #128]
+  0x08001D1E:  5C72         LDRB       R2, [R6, R1]
+  0x08001D20:  2A01         CMP        R2, #1
+  0x08001D22:  D10C         BNE        .L29                     ; 0x08001D3E
+  0x08001D24:  2800         CMP        R0, #0
+  0x08001D26:  D007         BEQ        .L28                     ; 0x08001D38
+  0x08001D28:  6DB0         LDR        R0, [R6, #88]
+  0x08001D2A:  4308         ORRS       R0, R1
+  0x08001D2C:  65B0         STR        R0, [R6, #88]
+  0x08001D2E:  6DF0         LDR        R0, [R6, #92]
+  0x08001D30:  9919         LDR        R1, [SP, #100]
+  0x08001D32:  4308         ORRS       R0, R1
+  0x08001D34:  65F0         STR        R0, [R6, #92]
+  0x08001D36:  E002         B          .L29                     ; 0x08001D3E
+
.L28:
+  0x08001D38:  48B4         LDR        R0, =0x0000FFFF          ; [PC, #0x02D0] [0x0800200C] 
+  0x08001D3A:  1C40         ADDS       R0, R0, #1
+  0x08001D3C:  4303         ORRS       R3, R0
+
.L29:
+  0x08001D3E:  6A70         LDR        R0, [R6, #36]
+  0x08001D40:  6AB2         LDR        R2, [R6, #40]
+  0x08001D42:  991E         LDR        R1, [SP, #120]
+  0x08001D44:  68C9         LDR        R1, [R1, #12]
+  0x08001D46:  4FB2         LDR        R7, =0xFFDE0201          ; [PC, #0x02C8] [0x08002010] 
+  0x08001D48:  400F         ANDS       R7, R1
+  0x08001D4A:  2800         CMP        R0, #0
+  0x08001D4C:  D003         BEQ        .L30                     ; 0x08001D56
+  0x08001D4E:  9910         LDR        R1, [SP, #64]
+  0x08001D50:  31C0         ADDS       R1, #192
+  0x08001D52:  4008         ANDS       R0, R1
+  0x08001D54:  4310         ORRS       R0, R2
+
.L30:
+  0x08001D56:  4318         ORRS       R0, R3
+  0x08001D58:  4338         ORRS       R0, R7
+  0x08001D5A:  991E         LDR        R1, [SP, #120]
+  0x08001D5C:  60C8         STR        R0, [R1, #12]
+  0x08001D5E:  2003         MOVS       R0, #3
+  0x08001D60:  0780         LSLS       R0, R0, #30
+  0x08001D62:  6873         LDR        R3, [R6, #4]
+  0x08001D64:  9318         STR        R3, [SP, #96]
+  0x08001D66:  9017         STR        R0, [SP, #92]
+  0x08001D68:  4003         ANDS       R3, R0
+  0x08001D6A:  991D         LDR        R1, [SP, #116]
+  0x08001D6C:  5C71         LDRB       R1, [R6, R1]
+  0x08001D6E:  2901         CMP        R1, #1
+  0x08001D70:  6CF2         LDR        R2, [R6, #76]
+  0x08001D72:  9819         LDR        R0, [SP, #100]
+  0x08001D74:  D109         BNE        .L31                     ; 0x08001D8A
+  0x08001D76:  6C31         LDR        R1, [R6, #64]
+  0x08001D78:  6C77         LDR        R7, [R6, #68]
+  0x08001D7A:  430F         ORRS       R7, R1
+  0x08001D7C:  6CB1         LDR        R1, [R6, #72]
+  0x08001D7E:  4339         ORRS       R1, R7
+  0x08001D80:  4319         ORRS       R1, R3
+  0x08001D82:  4311         ORRS       R1, R2
+  0x08001D84:  4301         ORRS       R1, R0
+  0x08001D86:  460B         MOV        R3, R1
+  0x08001D88:  E000         B          .L32                     ; 0x08001D8C
+
.L31:
+  0x08001D8A:  4313         ORRS       R3, R2
+
.L32:
+  0x08001D8C:  9F1E         LDR        R7, [SP, #120]
+  0x08001D8E:  6939         LDR        R1, [R7, #16]
+  0x08001D90:  4AA0         LDR        R2, =0x1FFFFC02          ; [PC, #0x0280] [0x08002014] 
+  0x08001D92:  400A         ANDS       R2, R1
+  0x08001D94:  431A         ORRS       R2, R3
+  0x08001D96:  463B         MOV        R3, R7
+  0x08001D98:  613A         STR        R2, [R7, #16]
+  0x08001D9A:  07C1         LSLS       R1, R0, #31
+  0x08001D9C:  9A18         LDR        R2, [SP, #96]
+  0x08001D9E:  428A         CMP        R2, R1
+  0x08001DA0:  9F12         LDR        R7, [SP, #72]
+  0x08001DA2:  D00F         BEQ        .L33                     ; 0x08001DC4
+  0x08001DA4:  9917         LDR        R1, [SP, #92]
+  0x08001DA6:  428A         CMP        R2, R1
+  0x08001DA8:  D00C         BEQ        .L33                     ; 0x08001DC4
+  0x08001DAA:  0781         LSLS       R1, R0, #30
+  0x08001DAC:  428A         CMP        R2, R1
+  0x08001DAE:  D009         BEQ        .L33                     ; 0x08001DC4
+  0x08001DB0:  210F         MOVS       R1, #15
+  0x08001DB2:  0489         LSLS       R1, R1, #18
+  0x08001DB4:  400A         ANDS       R2, R1
+  0x08001DB6:  4610         MOV        R0, R2
+  0x08001DB8:  4A97         LDR        R2, =0x40012708          ; [PC, #0x025C] [0x08002018] 
+  0x08001DBA:  6813         LDR        R3, [R2]
+  0x08001DBC:  438B         BICS       R3, R1
+  0x08001DBE:  1818         ADDS       R0, R3, R0
+  0x08001DC0:  9B1E         LDR        R3, [SP, #120]
+  0x08001DC2:  6010         STR        R0, [R2]
+
.L33:
+  0x08001DC4:  6958         LDR        R0, [R3, #20]
+  0x08001DC6:  9923         LDR        R1, [SP, #140]
+  0x08001DC8:  4388         BICS       R0, R1
+  0x08001DCA:  6B72         LDR        R2, [R6, #52]
+  0x08001DCC:  4310         ORRS       R0, R2
+  0x08001DCE:  6158         STR        R0, [R3, #20]
+  0x08001DD0:  6958         LDR        R0, [R3, #20]
+  0x08001DD2:  2170         MOVS       R1, #112
+  0x08001DD4:  4388         BICS       R0, R1
+  0x08001DD6:  6BB1         LDR        R1, [R6, #56]
+  0x08001DD8:  0109         LSLS       R1, R1, #4
+  0x08001DDA:  4301         ORRS       R1, R0
+  0x08001DDC:  6159         STR        R1, [R3, #20]
+  0x08001DDE:  0568         LSLS       R0, R5, #21
+  0x08001DE0:  991C         LDR        R1, [SP, #112]
+  0x08001DE2:  4281         CMP        R1, R0
+  0x08001DE4:  D007         BEQ        .L34                     ; 0x08001DF6
+  0x08001DE6:  2900         CMP        R1, #0
+  0x08001DE8:  D111         BNE        .L35                     ; 0x08001E0E
+  0x08001DEA:  4886         LDR        R0, =0xFFFFFEFD          ; [PC, #0x0218] [0x08002004] 
+  0x08001DEC:  30F3         ADDS       R0, #243
+  0x08001DEE:  6A99         LDR        R1, [R3, #40]
+  0x08001DF0:  4301         ORRS       R1, R0
+  0x08001DF2:  6299         STR        R1, [R3, #40]
+  0x08001DF4:  E00B         B          .L35                     ; 0x08001E0E
+
.L34:
+  0x08001DF6:  6A98         LDR        R0, [R3, #40]
+  0x08001DF8:  69F0         LDR        R0, [R6, #28]
+  0x08001DFA:  0080         LSLS       R0, R0, #2
+  0x08001DFC:  301C         ADDS       R0, #28
+  0x08001DFE:  9904         LDR        R1, [SP, #16]
+  0x08001E00:  4008         ANDS       R0, R1
+  0x08001E02:  4980         LDR        R1, =0xFFFFFEFD          ; [PC, #0x0200] [0x08002004] 
+  0x08001E04:  31F3         ADDS       R1, #243
+  0x08001E06:  4081         LSLS       R1, R0
+  0x08001E08:  6E30         LDR        R0, [R6, #96]
+  0x08001E0A:  4308         ORRS       R0, R1
+  0x08001E0C:  6298         STR        R0, [R3, #40]
+
.L35:
+  0x08001E0E:  6958         LDR        R0, [R3, #20]
+  0x08001E10:  9923         LDR        R1, [SP, #140]
+  0x08001E12:  4008         ANDS       R0, R1
+  0x08001E14:  4290         CMP        R0, R2
+  0x08001E16:  D001         BEQ        .L36                     ; 0x08001E1C
+  0x08001E18:  F002 FB69    BL         .L290                    ; 0x080044EE
+
.L36:
+  0x08001E1C:  9821         LDR        R0, [SP, #132]
+  0x08001E1E:  65F0         STR        R0, [R6, #92]
+  0x08001E20:  6DB0         LDR        R0, [R6, #88]
+  0x08001E22:  2501         MOVS       R5, #1
+  0x08001E24:  4328         ORRS       R0, R5
+  0x08001E26:  43B8         BICS       R0, R7
+  0x08001E28:  65B0         STR        R0, [R6, #88]
+  0x08001E2A:  981A         LDR        R0, [SP, #104]
+  0x08001E2C:  2800         CMP        R0, #0
+  0x08001E2E:  D100         BNE        .L37                     ; 0x08001E32
+  0x08001E30:  E181         B          .L61                     ; 0x08002136
+
.L37:
+  0x08001E32:  9525         STR        R5, [SP, #148]
+  0x08001E34:  06E8         LSLS       R0, R5, #27
+  0x08001E36:  1D00         ADDS       R0, R0, #4
+  0x08001E38:  9024         STR        R0, [SP, #144]
+  0x08001E3A:  A824         ADD        R0, SP, #144
+  0x08001E3C:  F7FE FC44    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E40:  2800         CMP        R0, #0
+  0x08001E42:  D000         BEQ        .L38                     ; 0x08001E46
+  0x08001E44:  E177         B          .L61                     ; 0x08002136
+
.L38:
+  0x08001E46:  4875         LDR        R0, =0x0C000008          ; [PC, #0x01D4] [0x0800201C] 
+  0x08001E48:  9024         STR        R0, [SP, #144]
+  0x08001E4A:  A824         ADD        R0, SP, #144
+  0x08001E4C:  F7FE FC3C    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E50:  2800         CMP        R0, #0
+  0x08001E52:  D000         BEQ        .L39                     ; 0x08001E56
+  0x08001E54:  E16F         B          .L61                     ; 0x08002136
+
.L39:
+  0x08001E56:  981F         LDR        R0, [SP, #124]
+  0x08001E58:  3010         ADDS       R0, #16
+  0x08001E5A:  9024         STR        R0, [SP, #144]
+  0x08001E5C:  A824         ADD        R0, SP, #144
+  0x08001E5E:  F7FE FC33    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E62:  2800         CMP        R0, #0
+  0x08001E64:  D000         BEQ        .L40                     ; 0x08001E68
+  0x08001E66:  E166         B          .L61                     ; 0x08002136
+
.L40:
+  0x08001E68:  486D         LDR        R0, =0x14000020          ; [PC, #0x01B4] [0x08002020] 
+  0x08001E6A:  9024         STR        R0, [SP, #144]
+  0x08001E6C:  A824         ADD        R0, SP, #144
+  0x08001E6E:  F7FE FC2B    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E72:  2800         CMP        R0, #0
+  0x08001E74:  D000         BEQ        .L41                     ; 0x08001E78
+  0x08001E76:  E15E         B          .L61                     ; 0x08002136
+
.L41:
+  0x08001E78:  486A         LDR        R0, =0xA4000200          ; [PC, #0x01A8] [0x08002024] 
+  0x08001E7A:  9024         STR        R0, [SP, #144]
+  0x08001E7C:  A824         ADD        R0, SP, #144
+  0x08001E7E:  F7FE FC23    BL         HAL_ADC_ConfigChannel    ; 0x080006C8
+  0x08001E82:  2800         CMP        R0, #0
+  0x08001E84:  D000         BEQ        .L42                     ; 0x08001E88
+  0x08001E86:  E156         B          .L61                     ; 0x08002136
+
.L42:
+  0x08001E88:  4F67         LDR        R7, =htim16              ; [PC, #0x019C] [0x08002028] =0x20000614 
+  0x08001E8A:  2077         MOVS       R0, #119
+  0x08001E8C:  4967         LDR        R1, =0x40014400          ; [PC, #0x019C] [0x0800202C] 
+  0x08001E8E:  6039         STR        R1, [R7]
+  0x08001E90:  6078         STR        R0, [R7, #4]
+  0x08001E92:  9921         LDR        R1, [SP, #132]
+  0x08001E94:  60B9         STR        R1, [R7, #8]
+  0x08001E96:  485D         LDR        R0, =0x0000FFFF          ; [PC, #0x0174] [0x0800200C] 
+  0x08001E98:  60F8         STR        R0, [R7, #12]
+  0x08001E9A:  6139         STR        R1, [R7, #16]
+  0x08001E9C:  6179         STR        R1, [R7, #20]
+  0x08001E9E:  980A         LDR        R0, [SP, #40]
+  0x08001EA0:  61B8         STR        R0, [R7, #24]
+  0x08001EA2:  4638         MOV        R0, R7
+  0x08001EA4:  F7FF F838    BL         HAL_TIM_Base_Init        ; 0x08000F18
+  0x08001EA8:  2800         CMP        R0, #0
+  0x08001EAA:  D000         BEQ        .L43                     ; 0x08001EAE
+  0x08001EAC:  E143         B          .L61                     ; 0x08002136
+
.L43:
+  0x08001EAE:  263D         MOVS       R6, #61
+  0x08001EB0:  5DB8         LDRB       R0, [R7, R6]
+  0x08001EB2:  2800         CMP        R0, #0
+  0x08001EB4:  D101         BNE        .L44                     ; 0x08001EBA
+  0x08001EB6:  991D         LDR        R1, [SP, #116]
+  0x08001EB8:  5478         STRB       R0, [R7, R1]
+
.L44:
+  0x08001EBA:  9812         LDR        R0, [SP, #72]
+  0x08001EBC:  55B8         STRB       R0, [R7, R6]
+  0x08001EBE:  4639         MOV        R1, R7
+  0x08001EC0:  C901         LDM        R1!, {R0}
+  0x08001EC2:  F7FF F88F    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08001EC6:  2048         MOVS       R0, #72
+  0x08001EC8:  901F         STR        R0, [SP, #124]
+  0x08001ECA:  543D         STRB       R5, [R7, R0]
+  0x08001ECC:  203E         MOVS       R0, #62
+  0x08001ECE:  901C         STR        R0, [SP, #112]
+  0x08001ED0:  543D         STRB       R5, [R7, R0]
+  0x08001ED2:  203F         MOVS       R0, #63
+  0x08001ED4:  901E         STR        R0, [SP, #120]
+  0x08001ED6:  543D         STRB       R5, [R7, R0]
+  0x08001ED8:  9807         LDR        R0, [SP, #28]
+  0x08001EDA:  543D         STRB       R5, [R7, R0]
+  0x08001EDC:  2041         MOVS       R0, #65
+  0x08001EDE:  901A         STR        R0, [SP, #104]
+  0x08001EE0:  543D         STRB       R5, [R7, R0]
+  0x08001EE2:  2042         MOVS       R0, #66
+  0x08001EE4:  9017         STR        R0, [SP, #92]
+  0x08001EE6:  543D         STRB       R5, [R7, R0]
+  0x08001EE8:  2043         MOVS       R0, #67
+  0x08001EEA:  9016         STR        R0, [SP, #88]
+  0x08001EEC:  543D         STRB       R5, [R7, R0]
+  0x08001EEE:  2044         MOVS       R0, #68
+  0x08001EF0:  9011         STR        R0, [SP, #68]
+  0x08001EF2:  543D         STRB       R5, [R7, R0]
+  0x08001EF4:  2045         MOVS       R0, #69
+  0x08001EF6:  9019         STR        R0, [SP, #100]
+  0x08001EF8:  543D         STRB       R5, [R7, R0]
+  0x08001EFA:  2046         MOVS       R0, #70
+  0x08001EFC:  900D         STR        R0, [SP, #52]
+  0x08001EFE:  543D         STRB       R5, [R7, R0]
+  0x08001F00:  2047         MOVS       R0, #71
+  0x08001F02:  900B         STR        R0, [SP, #44]
+  0x08001F04:  543D         STRB       R5, [R7, R0]
+  0x08001F06:  55BD         STRB       R5, [R7, R6]
+  0x08001F08:  981D         LDR        R0, [SP, #116]
+  0x08001F0A:  5C38         LDRB       R0, [R7, R0]
+  0x08001F0C:  2801         CMP        R0, #1
+  0x08001F0E:  D100         BNE        .L45                     ; 0x08001F12
+  0x08001F10:  E111         B          .L61                     ; 0x08002136
+
.L45:
+  0x08001F12:  6838         LDR        R0, [R7]
+  0x08001F14:  6A01         LDR        R1, [R0, #32]
+  0x08001F16:  6A02         LDR        R2, [R0, #32]
+  0x08001F18:  43AA         BICS       R2, R5
+  0x08001F1A:  6202         STR        R2, [R0, #32]
+  0x08001F1C:  6982         LDR        R2, [R0, #24]
+  0x08001F1E:  4B44         LDR        R3, =0x40012C00          ; [PC, #0x0110] [0x08002030] 
+  0x08001F20:  4298         CMP        R0, R3
+  0x08001F22:  960C         STR        R6, [SP, #48]
+  0x08001F24:  D002         BEQ        .L46                     ; 0x08001F2C
+  0x08001F26:  4B43         LDR        R3, =0x40000400          ; [PC, #0x010C] [0x08002034] 
+  0x08001F28:  4298         CMP        R0, R3
+  0x08001F2A:  D101         BNE        .L47                     ; 0x08001F30
+
.L46:
+  0x08001F2C:  2303         MOVS       R3, #3
+  0x08001F2E:  439A         BICS       R2, R3
+
.L47:
+  0x08001F30:  9B1D         LDR        R3, [SP, #116]
+  0x08001F32:  9E21         LDR        R6, [SP, #132]
+  0x08001F34:  54FE         STRB       R6, [R7, R3]
+  0x08001F36:  432A         ORRS       R2, R5
+  0x08001F38:  23F0         MOVS       R3, #240
+  0x08001F3A:  439A         BICS       R2, R3
+  0x08001F3C:  6182         STR        R2, [R0, #24]
+  0x08001F3E:  9A12         LDR        R2, [SP, #72]
+  0x08001F40:  4311         ORRS       R1, R2
+  0x08001F42:  9A1B         LDR        R2, [SP, #108]
+  0x08001F44:  4391         BICS       R1, R2
+  0x08001F46:  6201         STR        R1, [R0, #32]
+  0x08001F48:  6981         LDR        R1, [R0, #24]
+  0x08001F4A:  220C         MOVS       R2, #12
+  0x08001F4C:  920E         STR        R2, [SP, #56]
+  0x08001F4E:  4391         BICS       R1, R2
+  0x08001F50:  6181         STR        R1, [R0, #24]
+  0x08001F52:  4F39         LDR        R7, =htim17              ; [PC, #228] [0x08002038] =0x200005C8 
+  0x08001F54:  4A39         LDR        R2, =0x40014800          ; [PC, #228] [0x0800203C] 
+  0x08001F56:  9910         LDR        R1, [SP, #64]
+  0x08001F58:  31DF         ADDS       R1, #223
+  0x08001F5A:  C744         STM        R7!, {R2, R6}
+  0x08001F5C:  603E         STR        R6, [R7]
+  0x08001F5E:  6079         STR        R1, [R7, #4]
+  0x08001F60:  60BE         STR        R6, [R7, #8]
+  0x08001F62:  60FE         STR        R6, [R7, #12]
+  0x08001F64:  990A         LDR        R1, [SP, #40]
+  0x08001F66:  6139         STR        R1, [R7, #16]
+  0x08001F68:  6981         LDR        R1, [R0, #24]
+  0x08001F6A:  6181         STR        R1, [R0, #24]
+  0x08001F6C:  3F08         SUBS       R7, #8
+  0x08001F6E:  4638         MOV        R0, R7
+  0x08001F70:  F7FE FFD2    BL         HAL_TIM_Base_Init        ; 0x08000F18
+  0x08001F74:  2800         CMP        R0, #0
+  0x08001F76:  D000         BEQ        .L48                     ; 0x08001F7A
+  0x08001F78:  E0DD         B          .L61                     ; 0x08002136
+
.L48:
+  0x08001F7A:  9E0C         LDR        R6, [SP, #48]
+  0x08001F7C:  5DB8         LDRB       R0, [R7, R6]
+  0x08001F7E:  2800         CMP        R0, #0
+  0x08001F80:  D101         BNE        .L49                     ; 0x08001F86
+  0x08001F82:  991D         LDR        R1, [SP, #116]
+  0x08001F84:  5478         STRB       R0, [R7, R1]
+
.L49:
+  0x08001F86:  9812         LDR        R0, [SP, #72]
+  0x08001F88:  55B8         STRB       R0, [R7, R6]
+  0x08001F8A:  CF01         LDM        R7!, {R0}
+  0x08001F8C:  4639         MOV        R1, R7
+  0x08001F8E:  F7FF F829    BL         TIM_Base_SetConfig       ; 0x08000FE4
+  0x08001F92:  4929         LDR        R1, =htim17              ; [PC, #164] [0x08002038] =0x200005C8 
+  0x08001F94:  981F         LDR        R0, [SP, #124]
+  0x08001F96:  540D         STRB       R5, [R1, R0]
+  0x08001F98:  981C         LDR        R0, [SP, #112]
+  0x08001F9A:  540D         STRB       R5, [R1, R0]
+  0x08001F9C:  981E         LDR        R0, [SP, #120]
+  0x08001F9E:  540D         STRB       R5, [R1, R0]
+  0x08001FA0:  9807         LDR        R0, [SP, #28]
+  0x08001FA2:  540D         STRB       R5, [R1, R0]
+  0x08001FA4:  981A         LDR        R0, [SP, #104]
+  0x08001FA6:  540D         STRB       R5, [R1, R0]
+  0x08001FA8:  9817         LDR        R0, [SP, #92]
+  0x08001FAA:  540D         STRB       R5, [R1, R0]
+  0x08001FAC:  9816         LDR        R0, [SP, #88]
+  0x08001FAE:  540D         STRB       R5, [R1, R0]
+  0x08001FB0:  9811         LDR        R0, [SP, #68]
+  0x08001FB2:  540D         STRB       R5, [R1, R0]
+  0x08001FB4:  9819         LDR        R0, [SP, #100]
+  0x08001FB6:  540D         STRB       R5, [R1, R0]
+  0x08001FB8:  980D         LDR        R0, [SP, #52]
+  0x08001FBA:  540D         STRB       R5, [R1, R0]
+  0x08001FBC:  980B         LDR        R0, [SP, #44]
+  0x08001FBE:  540D         STRB       R5, [R1, R0]
+  0x08001FC0:  558D         STRB       R5, [R1, R6]
+  0x08001FC2:  981D         LDR        R0, [SP, #116]
+  0x08001FC4:  5C08         LDRB       R0, [R1, R0]
+  0x08001FC6:  2801         CMP        R0, #1
+  0x08001FC8:  D100         BNE        .L50                     ; 0x08001FCC
+  0x08001FCA:  E0B4         B          .L61                     ; 0x08002136
+
.L50:
+  0x08001FCC:  6808         LDR        R0, [R1]
+  0x08001FCE:  6A01         LDR        R1, [R0, #32]
+  0x08001FD0:  6A02         LDR        R2, [R0, #32]
+  0x08001FD2:  43AA         BICS       R2, R5
+  0x08001FD4:  6202         STR        R2, [R0, #32]
+  0x08001FD6:  9A12         LDR        R2, [SP, #72]
+  0x08001FD8:  4311         ORRS       R1, R2
+  0x08001FDA:  6846         LDR        R6, [R0, #4]
+  0x08001FDC:  6982         LDR        R2, [R0, #24]
+  0x08001FDE:  921F         STR        R2, [SP, #124]
+  0x08001FE0:  4B13         LDR        R3, =0x40012C00          ; [PC, #76] [0x08002030] 
+  0x08001FE2:  4298         CMP        R0, R3
+  0x08001FE4:  D02C         BEQ        .L53                     ; 0x08002040
+  0x08001FE6:  4B15         LDR        R3, =0x40014800          ; [PC, #84] [0x0800203C] 
+  0x08001FE8:  4298         CMP        R0, R3
+  0x08001FEA:  D002         BEQ        .L51                     ; 0x08001FF2
+  0x08001FEC:  4B0F         LDR        R3, =0x40014400          ; [PC, #60] [0x0800202C] 
+  0x08001FEE:  4298         CMP        R0, R3
+  0x08001FF0:  D101         BNE        .L52                     ; 0x08001FF6
+
.L51:
+  0x08001FF2:  9F0E         LDR        R7, [SP, #56]
+  0x08001FF4:  43B9         BICS       R1, R7
+
.L52:
+  0x08001FF6:  4B11         LDR        R3, =0x40014800          ; [PC, #68] [0x0800203C] 
+  0x08001FF8:  4298         CMP        R0, R3
+  0x08001FFA:  D023         BEQ        .L54                     ; 0x08002044
+  0x08001FFC:  4B0B         LDR        R3, =0x40014400          ; [PC, #44] [0x0800202C] 
+  0x08001FFE:  4298         CMP        R0, R3
+  0x08002000:  D020         BEQ        .L54                     ; 0x08002044
+  0x08002002:  E021         B          .L55                     ; 0x08002048
+  0x08002004:  FFFFFEFD     DC.W       0xFFFFFEFD
+  0x08002008:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x0800200C:  0000FFFF     DC.W       0x0000FFFF
+  0x08002010:  FFDE0201     DC.W       0xFFDE0201
+  0x08002014:  1FFFFC02     DC.W       0x1FFFFC02
+  0x08002018:  40012708     DC.W       0x40012708
+  0x0800201C:  0C000008     DC.W       0x0C000008
+  0x08002020:  14000020     DC.W       0x14000020
+  0x08002024:  A4000200     DC.W       0xA4000200
+  0x08002028:  20000614     DC.W       htim16
+  0x0800202C:  40014400     DC.W       0x40014400
+  0x08002030:  40012C00     DC.W       0x40012C00
+  0x08002034:  40000400     DC.W       0x40000400
+  0x08002038:  200005C8     DC.W       htim17
+  0x0800203C:  40014800     DC.W       0x40014800
+
.L53:
+  0x08002040:  9F0E         LDR        R7, [SP, #56]
+  0x08002042:  43B9         BICS       R1, R7
+
.L54:
+  0x08002044:  4BBB         LDR        R3, =0xFFFFFCFF          ; [PC, #0x02EC] [0x08002334] 
+  0x08002046:  401E         ANDS       R6, R3
+
.L55:
+  0x08002048:  4632         MOV        R2, R6
+  0x0800204A:  9F1D         LDR        R7, [SP, #116]
+  0x0800204C:  4BBA         LDR        R3, =htim17              ; [PC, #0x02E8] [0x08002338] =0x200005C8 
+  0x0800204E:  9E21         LDR        R6, [SP, #132]
+  0x08002050:  55DE         STRB       R6, [R3, R7]
+  0x08002052:  6042         STR        R2, [R0, #4]
+  0x08002054:  4BB9         LDR        R3, =0xFFFEFF8C          ; [PC, #0x02E4] [0x0800233C] 
+  0x08002056:  9A1F         LDR        R2, [SP, #124]
+  0x08002058:  401A         ANDS       R2, R3
+  0x0800205A:  3260         ADDS       R2, #96
+  0x0800205C:  6182         STR        R2, [R0, #24]
+  0x0800205E:  6346         STR        R6, [R0, #52]
+  0x08002060:  6201         STR        R1, [R0, #32]
+  0x08002062:  6981         LDR        R1, [R0, #24]
+  0x08002064:  9A1B         LDR        R2, [SP, #108]
+  0x08002066:  4311         ORRS       R1, R2
+  0x08002068:  6181         STR        R1, [R0, #24]
+  0x0800206A:  6981         LDR        R1, [R0, #24]
+  0x0800206C:  9A0F         LDR        R2, [SP, #60]
+  0x0800206E:  4391         BICS       R1, R2
+  0x08002070:  6181         STR        R1, [R0, #24]
+  0x08002072:  6981         LDR        R1, [R0, #24]
+  0x08002074:  6181         STR        R1, [R0, #24]
+  0x08002076:  0369         LSLS       R1, R5, #13
+  0x08002078:  9116         STR        R1, [SP, #88]
+  0x0800207A:  6441         STR        R1, [R0, #68]
+  0x0800207C:  49B0         LDR        R1, =0x40014800          ; [PC, #0x02C0] [0x08002340] 
+  0x0800207E:  4288         CMP        R0, R1
+  0x08002080:  4FB0         LDR        R7, =0x000003C7          ; [PC, #0x02C0] [0x08002344] 
+  0x08002082:  D140         BNE        .L59                     ; 0x08002106
+  0x08002084:  6B60         LDR        R0, [R4, #52]
+  0x08002086:  2601         MOVS       R6, #1
+  0x08002088:  4330         ORRS       R0, R6
+  0x0800208A:  6360         STR        R0, [R4, #52]
+  0x0800208C:  6B60         LDR        R0, [R4, #52]
+  0x0800208E:  4030         ANDS       R0, R6
+  0x08002090:  9030         STR        R0, [SP, #192]
+  0x08002092:  2005         MOVS       R0, #5
+  0x08002094:  902D         STR        R0, [SP, #180]
+  0x08002096:  2000         MOVS       R0, #0
+  0x08002098:  902C         STR        R0, [SP, #176]
+  0x0800209A:  902B         STR        R0, [SP, #172]
+  0x0800209C:  2402         MOVS       R4, #2
+  0x0800209E:  942A         STR        R4, [SP, #168]
+  0x080020A0:  980A         LDR        R0, [SP, #40]
+  0x080020A2:  9029         STR        R0, [SP, #164]
+  0x080020A4:  9830         LDR        R0, [SP, #192]
+  0x080020A6:  A929         ADD        R1, SP, #164
+  0x080020A8:  9809         LDR        R0, [SP, #36]
+  0x080020AA:  F7FE FDA7    BL         HAL_GPIO_Init            ; 0x08000BFC
+  0x080020AE:  49A2         LDR        R1, =htim17              ; [PC, #0x0288] [0x08002338] =0x200005C8 
+  0x080020B0:  9A1C         LDR        R2, [SP, #112]
+  0x080020B2:  5C88         LDRB       R0, [R1, R2]
+  0x080020B4:  2801         CMP        R0, #1
+  0x080020B6:  D13E         BNE        .L61                     ; 0x08002136
+  0x080020B8:  548C         STRB       R4, [R1, R2]
+  0x080020BA:  6808         LDR        R0, [R1]
+  0x080020BC:  6A01         LDR        R1, [R0, #32]
+  0x080020BE:  43B1         BICS       R1, R6
+  0x080020C0:  6201         STR        R1, [R0, #32]
+  0x080020C2:  6A01         LDR        R1, [R0, #32]
+  0x080020C4:  4331         ORRS       R1, R6
+  0x080020C6:  6201         STR        R1, [R0, #32]
+  0x080020C8:  499F         LDR        R1, =0x40000400          ; [PC, #0x027C] [0x08002348] 
+  0x080020CA:  4288         CMP        R0, R1
+  0x080020CC:  D00F         BEQ        .L57                     ; 0x080020EE
+  0x080020CE:  499F         LDR        R1, =0x40012C00          ; [PC, #0x027C] [0x0800234C] 
+  0x080020D0:  4288         CMP        R0, R1
+  0x080020D2:  D005         BEQ        .L56                     ; 0x080020E0
+  0x080020D4:  499A         LDR        R1, =0x40014800          ; [PC, #0x0268] [0x08002340] 
+  0x080020D6:  4288         CMP        R0, R1
+  0x080020D8:  D002         BEQ        .L56                     ; 0x080020E0
+  0x080020DA:  499D         LDR        R1, =0x40014400          ; [PC, #0x0274] [0x08002350] 
+  0x080020DC:  4288         CMP        R0, R1
+  0x080020DE:  D10F         BNE        .L58                     ; 0x08002100
+
.L56:
+  0x080020E0:  03F1         LSLS       R1, R6, #15
+  0x080020E2:  6C42         LDR        R2, [R0, #68]
+  0x080020E4:  430A         ORRS       R2, R1
+  0x080020E6:  6442         STR        R2, [R0, #68]
+  0x080020E8:  4998         LDR        R1, =0x40012C00          ; [PC, #0x0260] [0x0800234C] 
+  0x080020EA:  4288         CMP        R0, R1
+  0x080020EC:  D108         BNE        .L58                     ; 0x08002100
+
.L57:
+  0x080020EE:  4A99         LDR        R2, =0x0000FFFF          ; [PC, #0x0264] [0x08002354] 
+  0x080020F0:  3208         ADDS       R2, #8
+  0x080020F2:  6881         LDR        R1, [R0, #8]
+  0x080020F4:  4011         ANDS       R1, R2
+  0x080020F6:  2906         CMP        R1, #6
+  0x080020F8:  D005         BEQ        .L59                     ; 0x08002106
+  0x080020FA:  0432         LSLS       R2, R6, #16
+  0x080020FC:  4291         CMP        R1, R2
+  0x080020FE:  D002         BEQ        .L59                     ; 0x08002106
+
.L58:
+  0x08002100:  6801         LDR        R1, [R0]
+  0x08002102:  4331         ORRS       R1, R6
+  0x08002104:  6001         STR        R1, [R0]
+
.L59:
+  0x08002106:  4B94         LDR        R3, =0x40003000          ; [PC, #0x0250] [0x08002358] 
+  0x08002108:  4894         LDR        R0, =0x0000CCCC          ; [PC, #0x0250] [0x0800235C] 
+  0x0800210A:  6018         STR        R0, [R3]
+  0x0800210C:  4894         LDR        R0, =0x00005555          ; [PC, #0x0250] [0x08002360] 
+  0x0800210E:  6018         STR        R0, [R3]
+  0x08002110:  9815         LDR        R0, [SP, #84]
+  0x08002112:  6058         STR        R0, [R3, #4]
+  0x08002114:  463C         MOV        R4, R7
+  0x08002116:  3421         ADDS       R4, #33
+  0x08002118:  609C         STR        R4, [R3, #8]
+  0x0800211A:  4892         LDR        R0, =uwTick              ; [PC, #0x0248] [0x08002364] =0x2000068C 
+  0x0800211C:  6800         LDR        R0, [R0]
+  0x0800211E:  9A14         LDR        R2, [SP, #80]
+
.L60:
+  0x08002120:  68D9         LDR        R1, [R3, #12]
+  0x08002122:  0749         LSLS       R1, R1, #29
+  0x08002124:  D009         BEQ        .L62                     ; 0x0800213A
+  0x08002126:  498F         LDR        R1, =uwTick              ; [PC, #0x023C] [0x08002364] =0x2000068C 
+  0x08002128:  6809         LDR        R1, [R1]
+  0x0800212A:  1A09         SUBS       R1, R1, R0
+  0x0800212C:  2932         CMP        R1, #50
+  0x0800212E:  D3F7         BCC        .L60                     ; 0x08002120
+  0x08002130:  68D9         LDR        R1, [R3, #12]
+  0x08002132:  0749         LSLS       R1, R1, #29
+  0x08002134:  D0F4         BEQ        .L60                     ; 0x08002120
+
.L61:
+  0x08002136:  F003 FED8    BL         Error_Handler            ; 0x08005EEA
+
.L62:
+  0x0800213A:  6918         LDR        R0, [R3, #16]
+  0x0800213C:  42A0         CMP        R0, R4
+  0x0800213E:  D102         BNE        .L63                     ; 0x08002146
+  0x08002140:  4889         LDR        R0, =0x0000AAAA          ; [PC, #0x0224] [0x08002368] 
+  0x08002142:  6018         STR        R0, [R3]
+  0x08002144:  E000         B          .L64                     ; 0x08002148
+
.L63:
+  0x08002146:  611C         STR        R4, [R3, #16]
+
.L64:
+  0x08002148:  4F88         LDR        R7, =huart1              ; [PC, #0x0220] [0x0800236C] =0x200003BC 
+  0x0800214A:  4889         LDR        R0, =0x40013800          ; [PC, #0x0224] [0x08002370] 
+  0x0800214C:  6038         STR        R0, [R7]
+  0x0800214E:  204B         MOVS       R0, #75
+  0x08002150:  9005         STR        R0, [SP, #20]
+  0x08002152:  0200         LSLS       R0, R0, #8
+  0x08002154:  901A         STR        R0, [SP, #104]
+  0x08002156:  6078         STR        R0, [R7, #4]
+  0x08002158:  60BA         STR        R2, [R7, #8]
+  0x0800215A:  9821         LDR        R0, [SP, #132]
+  0x0800215C:  60F8         STR        R0, [R7, #12]
+  0x0800215E:  9822         LDR        R0, [SP, #136]
+  0x08002160:  6138         STR        R0, [R7, #16]
+  0x08002162:  980E         LDR        R0, [SP, #56]
+  0x08002164:  6178         STR        R0, [R7, #20]
+  0x08002166:  4638         MOV        R0, R7
+  0x08002168:  3018         ADDS       R0, #24
+  0x0800216A:  2114         MOVS       R1, #20
+  0x0800216C:  F004 F821    BL         __aeabi_memclr           ; 0x080061B2
+  0x08002170:  F7FE FF80    BL         HAL_UART_Init            ; 0x08001074
+  0x08002174:  2800         CMP        R0, #0
+  0x08002176:  D1DE         BNE        .L61                     ; 0x08002136
+  0x08002178:  940B         STR        R4, [SP, #44]
+  0x0800217A:  2684         MOVS       R6, #132
+  0x0800217C:  5DB8         LDRB       R0, [R7, R6]
+  0x0800217E:  2801         CMP        R0, #1
+  0x08002180:  D0D9         BEQ        .L61                     ; 0x08002136
+  0x08002182:  2488         MOVS       R4, #136
+  0x08002184:  2024         MOVS       R0, #36
+  0x08002186:  901F         STR        R0, [SP, #124]
+  0x08002188:  5138         STR        R0, [R7, R4]
+  0x0800218A:  55BD         STRB       R5, [R7, R6]
+  0x0800218C:  6838         LDR        R0, [R7]
+  0x0800218E:  6807         LDR        R7, [R0]
+  0x08002190:  43EA         MVNS       R2, R5
+  0x08002192:  921E         STR        R2, [SP, #120]
+  0x08002194:  6801         LDR        R1, [R0]
+  0x08002196:  4011         ANDS       R1, R2
+  0x08002198:  6001         STR        R1, [R0]
+  0x0800219A:  9923         LDR        R1, [SP, #140]
+  0x0800219C:  0749         LSLS       R1, R1, #29
+  0x0800219E:  6882         LDR        R2, [R0, #8]
+  0x080021A0:  438A         BICS       R2, R1
+  0x080021A2:  6082         STR        R2, [R0, #8]
+  0x080021A4:  F7FF FA50    BL         UARTEx_SetNbDataToProcess ; 0x08001648
+  0x080021A8:  4870         LDR        R0, =huart1              ; [PC, #0x01C0] [0x0800236C] =0x200003BC 
+  0x080021AA:  6800         LDR        R0, [R0]
+  0x080021AC:  6007         STR        R7, [R0]
+  0x080021AE:  9F20         LDR        R7, [SP, #128]
+  0x080021B0:  496E         LDR        R1, =huart1              ; [PC, #0x01B8] [0x0800236C] =0x200003BC 
+  0x080021B2:  510F         STR        R7, [R1, R4]
+  0x080021B4:  9A1F         LDR        R2, [SP, #124]
+  0x080021B6:  510A         STR        R2, [R1, R4]
+  0x080021B8:  558D         STRB       R5, [R1, R6]
+  0x080021BA:  6801         LDR        R1, [R0]
+  0x080021BC:  9117         STR        R1, [SP, #92]
+  0x080021BE:  6801         LDR        R1, [R0]
+  0x080021C0:  9A1E         LDR        R2, [SP, #120]
+  0x080021C2:  4011         ANDS       R1, R2
+  0x080021C4:  6001         STR        R1, [R0]
+  0x080021C6:  9923         LDR        R1, [SP, #140]
+  0x080021C8:  0649         LSLS       R1, R1, #25
+  0x080021CA:  6882         LDR        R2, [R0, #8]
+  0x080021CC:  438A         BICS       R2, R1
+  0x080021CE:  6082         STR        R2, [R0, #8]
+  0x080021D0:  F7FF FA3A    BL         UARTEx_SetNbDataToProcess ; 0x08001648
+  0x080021D4:  4865         LDR        R0, =huart1              ; [PC, #0x0194] [0x0800236C] =0x200003BC 
+  0x080021D6:  6800         LDR        R0, [R0]
+  0x080021D8:  9917         LDR        R1, [SP, #92]
+  0x080021DA:  6001         STR        R1, [R0]
+  0x080021DC:  4963         LDR        R1, =huart1              ; [PC, #0x018C] [0x0800236C] =0x200003BC 
+  0x080021DE:  510F         STR        R7, [R1, R4]
+  0x080021E0:  9A1F         LDR        R2, [SP, #124]
+  0x080021E2:  510A         STR        R2, [R1, R4]
+  0x080021E4:  9B21         LDR        R3, [SP, #132]
+  0x080021E6:  9617         STR        R6, [SP, #92]
+  0x080021E8:  558B         STRB       R3, [R1, R6]
+  0x080021EA:  6801         LDR        R1, [R0]
+  0x080021EC:  6802         LDR        R2, [R0]
+  0x080021EE:  9E1E         LDR        R6, [SP, #120]
+  0x080021F0:  4032         ANDS       R2, R6
+  0x080021F2:  6002         STR        R2, [R0]
+  0x080021F4:  076A         LSLS       R2, R5, #29
+  0x080021F6:  4391         BICS       R1, R2
+  0x080021F8:  6001         STR        R1, [R0]
+  0x080021FA:  485C         LDR        R0, =huart1              ; [PC, #0x0170] [0x0800236C] =0x200003BC 
+  0x080021FC:  940D         STR        R4, [SP, #52]
+  0x080021FE:  5107         STR        R7, [R0, R4]
+  0x08002200:  6643         STR        R3, [R0, #100]
+  0x08002202:  485C         LDR        R0, =0x0800780E          ; [PC, #0x0170] [0x08002374] 
+  0x08002204:  8800         LDRH       R0, [R0]
+  0x08002206:  2802         CMP        R0, #2
+  0x08002208:  D003         BEQ        .L65                     ; 0x08002212
+  0x0800220A:  28FF         CMP        R0, #255
+  0x0800220C:  D105         BNE        .L66                     ; 0x0800221A
+  0x0800220E:  485A         LDR        R0, =0x0800640F          ; [PC, #0x0168] [0x08002378] 
+  0x08002210:  E004         B          .L67                     ; 0x0800221C
+
.L65:
+  0x08002212:  485A         LDR        R0, =0x080063FD          ; [PC, #0x0168] [0x0800237C] 
+  0x08002214:  F002 FFEE    BL         puts                     ; 0x080051F4
+  0x08002218:  E004         B          .L68                     ; 0x08002224
+
.L66:
+  0x0800221A:  4859         LDR        R0, =0x08006201          ; [PC, #0x0164] [0x08002380] 
+
.L67:
+  0x0800221C:  F002 FFEA    BL         puts                     ; 0x080051F4
+  0x08002220:  F7FF FAC8    BL         EEPROM_WriteDefaults     ; 0x080017B4
+
.L68:
+  0x08002224:  9E14         LDR        R6, [SP, #80]
+  0x08002226:  F7FF FADD    BL         EEPROM_ReadDeviceParameter ; 0x080017E4
+  0x0800222A:  9805         LDR        R0, [SP, #20]
+  0x0800222C:  00C0         LSLS       R0, R0, #3
+  0x0800222E:  4C55         LDR        R4, =sys_data            ; [PC, #0x0154] [0x08002384] =0x20000234 
+  0x08002230:  8020         STRH       R0, [R4]
+  0x08002232:  8125         STRH       R5, [R4, #8]
+  0x08002234:  9821         LDR        R0, [SP, #132]
+  0x08002236:  8160         STRH       R0, [R4, #10]
+  0x08002238:  81A0         STRH       R0, [R4, #12]
+  0x0800223A:  4853         LDR        R0, =0x08006894          ; [PC, #0x014C] [0x08002388] 
+  0x0800223C:  F002 FFDA    BL         puts                     ; 0x080051F4
+  0x08002240:  6923         LDR        R3, [R4, #16]
+  0x08002242:  8AA1         LDRH       R1, [R4, #20]
+  0x08002244:  8AE0         LDRH       R0, [R4, #22]
+  0x08002246:  2800         CMP        R0, #0
+  0x08002248:  D001         BEQ        .L69                     ; 0x0800224E
+  0x0800224A:  2803         CMP        R0, #3
+  0x0800224C:  D300         BCC        .L70                     ; 0x08002250
+
.L69:
+  0x0800224E:  2001         MOVS       R0, #1
+
.L70:
+  0x08002250:  2900         CMP        R1, #0
+  0x08002252:  D001         BEQ        .L71                     ; 0x08002258
+  0x08002254:  2901         CMP        R1, #1
+  0x08002256:  D102         BNE        .L72                     ; 0x0800225E
+
.L71:
+  0x08002258:  4607         MOV        R7, R0
+  0x0800225A:  370A         ADDS       R7, #10
+  0x0800225C:  E001         B          .L73                     ; 0x08002262
+
.L72:
+  0x0800225E:  4607         MOV        R7, R0
+  0x08002260:  3709         ADDS       R7, #9
+
.L73:
+  0x08002262:  4A42         LDR        R2, =huart1              ; [PC, #0x0108] [0x0800236C] =0x200003BC 
+  0x08002264:  9323         STR        R3, [SP, #140]
+  0x08002266:  6053         STR        R3, [R2, #4]
+  0x08002268:  4B48         LDR        R3, =modbusData          ; [PC, #0x0120] [0x0800238C] =0x20000000 
+  0x0800226A:  601A         STR        R2, [R3]
+  0x0800226C:  2900         CMP        R1, #0
+  0x0800226E:  4632         MOV        R2, R6
+  0x08002270:  D007         BEQ        .L75                     ; 0x08002282
+  0x08002272:  2901         CMP        R1, #1
+  0x08002274:  D103         BNE        .L74                     ; 0x0800227E
+  0x08002276:  9915         LDR        R1, [SP, #84]
+  0x08002278:  0249         LSLS       R1, R1, #9
+  0x0800227A:  9122         STR        R1, [SP, #136]
+  0x0800227C:  E001         B          .L75                     ; 0x08002282
+
.L74:
+  0x0800227E:  9A21         LDR        R2, [SP, #132]
+  0x08002280:  9222         STR        R2, [SP, #136]
+
.L75:
+  0x08002282:  493A         LDR        R1, =huart1              ; [PC, #232] [0x0800236C] =0x200003BC 
+  0x08002284:  608A         STR        R2, [R1, #8]
+  0x08002286:  9A22         LDR        R2, [SP, #136]
+  0x08002288:  610A         STR        R2, [R1, #16]
+  0x0800228A:  2801         CMP        R0, #1
+  0x0800228C:  D001         BEQ        .L76                     ; 0x08002292
+  0x0800228E:  9816         LDR        R0, [SP, #88]
+  0x08002290:  9021         STR        R0, [SP, #132]
+
.L76:
+  0x08002292:  9821         LDR        R0, [SP, #132]
+  0x08002294:  60C8         STR        R0, [R1, #12]
+  0x08002296:  460C         MOV        R4, R1
+  0x08002298:  F7FE FEEC    BL         HAL_UART_Init            ; 0x08001074
+  0x0800229C:  2800         CMP        R0, #0
+  0x0800229E:  D001         BEQ        .L77                     ; 0x080022A4
+  0x080022A0:  F002 F931    BL         .L292                    ; 0x08004506
+
.L77:
+  0x080022A4:  980D         LDR        R0, [SP, #52]
+  0x080022A6:  5820         LDR        R0, [R4, R0]
+  0x080022A8:  2820         CMP        R0, #32
+  0x080022AA:  9A17         LDR        R2, [SP, #92]
+  0x080022AC:  9B23         LDR        R3, [SP, #140]
+  0x080022AE:  D111         BNE        .L78                     ; 0x080022D4
+  0x080022B0:  4621         MOV        R1, R4
+  0x080022B2:  5CA0         LDRB       R0, [R4, R2]
+  0x080022B4:  2801         CMP        R0, #1
+  0x080022B6:  D00D         BEQ        .L78                     ; 0x080022D4
+  0x080022B8:  9B0D         LDR        R3, [SP, #52]
+  0x080022BA:  981F         LDR        R0, [SP, #124]
+  0x080022BC:  50C8         STR        R0, [R1, R3]
+  0x080022BE:  2000         MOVS       R0, #0
+  0x080022C0:  5488         STRB       R0, [R1, R2]
+  0x080022C2:  2001         MOVS       R0, #1
+  0x080022C4:  05C0         LSLS       R0, R0, #23
+  0x080022C6:  6809         LDR        R1, [R1]
+  0x080022C8:  684A         LDR        R2, [R1, #4]
+  0x080022CA:  4302         ORRS       R2, R0
+  0x080022CC:  604A         STR        R2, [R1, #4]
+  0x080022CE:  9820         LDR        R0, [SP, #128]
+  0x080022D0:  50E0         STR        R0, [R4, R3]
+  0x080022D2:  9B23         LDR        R3, [SP, #140]
+
.L78:
+  0x080022D4:  981A         LDR        R0, [SP, #104]
+  0x080022D6:  1C40         ADDS       R0, R0, #1
+  0x080022D8:  4283         CMP        R3, R0
+  0x080022DA:  4C2C         LDR        R4, =modbusData          ; [PC, #176] [0x0800238C] =0x20000000 
+  0x080022DC:  D209         BCS        .L79                     ; 0x080022F2
+  0x080022DE:  4638         MOV        R0, R7
+  0x080022E0:  F003 FEA3    BL         __aeabi_ui2d             ; 0x0800602A
+  0x080022E4:  2200         MOVS       R2, #0
+  0x080022E6:  4B2A         LDR        R3, =0x400C0000          ; [PC, #168] [0x08002390] 
+  0x080022E8:  F003 FB8B    BL         __aeabi_dmul             ; 0x08005A02
+  0x080022EC:  F003 FC32    BL         __aeabi_d2uiz            ; 0x08005B54
+  0x080022F0:  E007         B          .L80                     ; 0x08002302
+
.L79:
+  0x080022F2:  9815         LDR        R0, [SP, #84]
+  0x080022F4:  0240         LSLS       R0, R0, #9
+  0x080022F6:  30D6         ADDS       R0, #214
+  0x080022F8:  4358         MULS       R0, R3, R0
+  0x080022FA:  4926         LDR        R1, =0x000F4240          ; [PC, #152] [0x08002394] 
+  0x080022FC:  F003 FEC3    BL         __aeabi_uidiv            ; 0x08006086
+  0x08002300:  1C40         ADDS       R0, R0, #1
+
.L80:
+  0x08002302:  4925         LDR        R1, =0xFEFFFFFF          ; [PC, #148] [0x08002398] 
+  0x08002304:  1C49         ADDS       R1, R1, #1
+  0x08002306:  4A19         LDR        R2, =huart1              ; [PC, #100] [0x0800236C] =0x200003BC 
+  0x08002308:  6812         LDR        R2, [R2]
+  0x0800230A:  6953         LDR        R3, [R2, #20]
+  0x0800230C:  400B         ANDS       R3, R1
+  0x0800230E:  4303         ORRS       R3, R0
+  0x08002310:  6153         STR        R3, [R2, #20]
+  0x08002312:  06A8         LSLS       R0, R5, #26
+  0x08002314:  6811         LDR        R1, [R2]
+  0x08002316:  4301         ORRS       R1, R0
+  0x08002318:  6011         STR        R1, [R2]
+  0x0800231A:  6820         LDR        R0, [R4]
+  0x0800231C:  4626         MOV        R6, R4
+  0x0800231E:  3627         ADDS       R6, #39
+  0x08002320:  4631         MOV        R1, R6
+  0x08002322:  F7FF F915    BL         HAL_UART_Receive_DMA     ; 0x08001550
+  0x08002326:  2800         CMP        R0, #0
+  0x08002328:  D03A         BEQ        .L82                     ; 0x080023A0
+  0x0800232A:  481C         LDR        R0, =0x0800643D          ; [PC, #112] [0x0800239C] 
+  0x0800232C:  F002 FFBC    BL         printf                   ; 0x080052A8
+
.L81:
+  0x08002330:  E7FE         B          .L81                     ; 0x08002330
+  0x08002332:  46C0         NOP
+  0x08002334:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08002338:  200005C8     DC.W       htim17
+  0x0800233C:  FFFEFF8C     DC.W       0xFFFEFF8C
+  0x08002340:  40014800     DC.W       0x40014800
+  0x08002344:  000003C7     DC.W       0x000003C7
+  0x08002348:  40000400     DC.W       0x40000400
+  0x0800234C:  40012C00     DC.W       0x40012C00
+  0x08002350:  40014400     DC.W       0x40014400
+  0x08002354:  0000FFFF     DC.W       0x0000FFFF
+  0x08002358:  40003000     DC.W       0x40003000
+  0x0800235C:  0000CCCC     DC.W       0x0000CCCC
+  0x08002360:  00005555     DC.W       0x00005555
+  0x08002364:  2000068C     DC.W       uwTick
+  0x08002368:  0000AAAA     DC.W       0x0000AAAA
+  0x0800236C:  200003BC     DC.W       huart1
+  0x08002370:  40013800     DC.W       0x40013800
+  0x08002374:  0800780E     DC.W       0x0800780E
+  0x08002378:  0800640F     DC.W       0800640F               ; R_ARM_ABS32
+  0x0800237C:  080063FD     DC.W       080063FD               ; R_ARM_ABS32
+  0x08002380:  08006201     DC.W       08006201               ; R_ARM_ABS32
+  0x08002384:  20000234     DC.W       sys_data
+  0x08002388:  08006894     DC.W       08006894               ; R_ARM_ABS32
+  0x0800238C:  20000000     DC.W       modbusData
+  0x08002390:  400C0000     DC.W       0x400C0000
+  0x08002394:  000F4240     DC.W       0x000F4240
+  0x08002398:  FEFFFFFF     DC.W       0xFEFFFFFF
+  0x0800239C:  0800643D     DC.W       0800643D               ; R_ARM_ABS32
+
.L82:
+  0x080023A0:  2026         MOVS       R0, #38
+  0x080023A2:  9617         STR        R6, [SP, #92]
+  0x080023A4:  2100         MOVS       R1, #0
+  0x080023A6:  9022         STR        R0, [SP, #136]
+  0x080023A8:  5421         STRB       R1, [R4, R0]
+  0x080023AA:  61E1         STR        R1, [R4, #28]
+  0x080023AC:  84A1         STRH       R1, [R4, #36]
+  0x080023AE:  8421         STRH       R1, [R4, #32]
+  0x080023B0:  9123         STR        R1, [SP, #140]
+  0x080023B2:  4620         MOV        R0, R4
+  0x080023B4:  301C         ADDS       R0, #28
+  0x080023B6:  7181         STRB       R1, [R0, #6]
+  0x080023B8:  4EFD         LDR        R6, =0x50000410          ; [PC, #0x03F4] [0x080027B0] 
+  0x080023BA:  9820         LDR        R0, [SP, #128]
+  0x080023BC:  60B0         STR        R0, [R6, #8]
+  0x080023BE:  03EF         LSLS       R7, R5, #15
+  0x080023C0:  48FC         LDR        R0, =0x50000818          ; [PC, #0x03F0] [0x080027B4] 
+  0x080023C2:  6007         STR        R7, [R0]
+  0x080023C4:  03AC         LSLS       R4, R5, #14
+  0x080023C6:  6004         STR        R4, [R0]
+  0x080023C8:  9810         LDR        R0, [SP, #64]
+  0x080023CA:  30F4         ADDS       R0, #244
+  0x080023CC:  9009         STR        R0, [SP, #36]
+  0x080023CE:  F7FE F971    BL         HAL_Delay                ; 0x080006B4
+  0x080023D2:  9820         LDR        R0, [SP, #128]
+  0x080023D4:  61B0         STR        R0, [R6, #24]
+  0x080023D6:  971E         STR        R7, [SP, #120]
+  0x080023D8:  48F6         LDR        R0, =0x50000818          ; [PC, #0x03D8] [0x080027B4] 
+  0x080023DA:  6107         STR        R7, [R0, #16]
+  0x080023DC:  4FF6         LDR        R7, =0x000003C7          ; [PC, #0x03D8] [0x080027B8] 
+  0x080023DE:  941F         STR        R4, [SP, #124]
+  0x080023E0:  6104         STR        R4, [R0, #16]
+  0x080023E2:  48F6         LDR        R0, =0x50000010          ; [PC, #0x03D8] [0x080027BC] 
+  0x080023E4:  9910         LDR        R1, [SP, #64]
+  0x080023E6:  6081         STR        R1, [R0, #8]
+  0x080023E8:  981B         LDR        R0, [SP, #108]
+  0x080023EA:  61B0         STR        R0, [R6, #24]
+  0x080023EC:  2410         MOVS       R4, #16
+  0x080023EE:  60B4         STR        R4, [R6, #8]
+  0x080023F0:  2032         MOVS       R0, #50
+  0x080023F2:  9016         STR        R0, [SP, #88]
+  0x080023F4:  F7FE F95E    BL         HAL_Delay                ; 0x080006B4
+  0x080023F8:  941A         STR        R4, [SP, #104]
+  0x080023FA:  61B4         STR        R4, [R6, #24]
+  0x080023FC:  6830         LDR        R0, [R6]
+  0x080023FE:  6831         LDR        R1, [R6]
+  0x08002400:  6832         LDR        R2, [R6]
+  0x08002402:  0992         LSRS       R2, R2, #6
+  0x08002404:  9B0F         LDR        R3, [SP, #60]
+  0x08002406:  401A         ANDS       R2, R3
+  0x08002408:  0989         LSRS       R1, R1, #6
+  0x0800240A:  9B12         LDR        R3, [SP, #72]
+  0x0800240C:  4019         ANDS       R1, R3
+  0x0800240E:  0640         LSLS       R0, R0, #25
+  0x08002410:  0FC0         LSRS       R0, R0, #31
+  0x08002412:  1808         ADDS       R0, R1, R0
+  0x08002414:  1880         ADDS       R0, R0, R2
+  0x08002416:  6831         LDR        R1, [R6]
+  0x08002418:  0989         LSRS       R1, R1, #6
+  0x0800241A:  9A1B         LDR        R2, [SP, #108]
+  0x0800241C:  4011         ANDS       R1, R2
+  0x0800241E:  1841         ADDS       R1, R0, R1
+  0x08002420:  200F         MOVS       R0, #15
+  0x08002422:  9003         STR        R0, [SP, #12]
+  0x08002424:  4041         EORS       R1, R0
+  0x08002426:  4CE6         LDR        R4, =mode                ; [PC, #0x0398] [0x080027C0] =0x20000739 
+  0x08002428:  7021         STRB       R1, [R4]
+  0x0800242A:  48E6         LDR        R0, =0x080067D2          ; [PC, #0x0398] [0x080027C4] 
+  0x0800242C:  F002 FF3C    BL         printf                   ; 0x080052A8
+  0x08002430:  7820         LDRB       R0, [R4]
+  0x08002432:  49E5         LDR        R1, =sys_data            ; [PC, #0x0394] [0x080027C8] =0x20000234 
+  0x08002434:  8508         STRH       R0, [R1, #40]
+  0x08002436:  48E5         LDR        R0, =0x1FFF7568          ; [PC, #0x0394] [0x080027CC] 
+  0x08002438:  8800         LDRH       R0, [R0]
+  0x0800243A:  F003 FBA2    BL         __aeabi_ui2f             ; 0x08005B82
+  0x0800243E:  2173         MOVS       R1, #115
+  0x08002440:  05C9         LSLS       R1, R1, #23
+  0x08002442:  F003 FA67    BL         __aeabi_fmul             ; 0x08005914
+  0x08002446:  49E2         LDR        R1, =0x453B8000          ; [PC, #0x0388] [0x080027D0] 
+  0x08002448:  F003 FA64    BL         __aeabi_fmul             ; 0x08005914
+  0x0800244C:  F003 FDDB    BL         __aeabi_f2uiz            ; 0x08006006
+  0x08002450:  49E0         LDR        R1, =calTemperatureSensor30Value ; [PC, #0x0380] [0x080027D4] =0x200006E8 
+  0x08002452:  6008         STR        R0, [R1]
+  0x08002454:  9823         LDR        R0, [SP, #140]
+  0x08002456:  9029         STR        R0, [SP, #164]
+  0x08002458:  4EDF         LDR        R6, =hadc1               ; [PC, #0x037C] [0x080027D8] =0x20000450 
+  0x0800245A:  2354         MOVS       R3, #84
+  0x0800245C:  5CF0         LDRB       R0, [R6, R3]
+  0x0800245E:  2801         CMP        R0, #1
+  0x08002460:  6834         LDR        R4, [R6]
+  0x08002462:  4628         MOV        R0, R5
+  0x08002464:  9321         STR        R3, [SP, #132]
+  0x08002466:  D069         BEQ        .L93                     ; 0x0800253C
+  0x08002468:  2001         MOVS       R0, #1
+  0x0800246A:  9002         STR        R0, [SP, #8]
+  0x0800246C:  54F0         STRB       R0, [R6, R3]
+  0x0800246E:  68A1         LDR        R1, [R4, #8]
+  0x08002470:  68A2         LDR        R2, [R4, #8]
+  0x08002472:  07D2         LSLS       R2, R2, #31
+  0x08002474:  D020         BEQ        .L85                     ; 0x080024B8
+  0x08002476:  9812         LDR        R0, [SP, #72]
+  0x08002478:  4001         ANDS       R1, R0
+  0x0800247A:  D11D         BNE        .L85                     ; 0x080024B8
+  0x0800247C:  68A1         LDR        R1, [R4, #8]
+  0x0800247E:  2205         MOVS       R2, #5
+  0x08002480:  400A         ANDS       R2, R1
+  0x08002482:  2A01         CMP        R2, #1
+  0x08002484:  D110         BNE        .L84                     ; 0x080024A8
+  0x08002486:  68A1         LDR        R1, [R4, #8]
+  0x08002488:  48D4         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0350] [0x080027DC] 
+  0x0800248A:  4001         ANDS       R1, R0
+  0x0800248C:  9812         LDR        R0, [SP, #72]
+  0x0800248E:  4301         ORRS       R1, R0
+  0x08002490:  60A1         STR        R1, [R4, #8]
+  0x08002492:  9815         LDR        R0, [SP, #84]
+  0x08002494:  6020         STR        R0, [R4]
+  0x08002496:  48D2         LDR        R0, =uwTick              ; [PC, #0x0348] [0x080027E0] =0x2000068C 
+  0x08002498:  6801         LDR        R1, [R0]
+
.L83:
+  0x0800249A:  68A2         LDR        R2, [R4, #8]
+  0x0800249C:  07D2         LSLS       R2, R2, #31
+  0x0800249E:  D00B         BEQ        .L85                     ; 0x080024B8
+  0x080024A0:  6802         LDR        R2, [R0]
+  0x080024A2:  1A52         SUBS       R2, R2, R1
+  0x080024A4:  2A03         CMP        R2, #3
+  0x080024A6:  D3F8         BCC        .L83                     ; 0x0800249A
+
.L84:
+  0x080024A8:  6DB1         LDR        R1, [R6, #88]
+  0x080024AA:  981A         LDR        R0, [SP, #104]
+  0x080024AC:  4301         ORRS       R1, R0
+  0x080024AE:  65B1         STR        R1, [R6, #88]
+  0x080024B0:  6DF1         LDR        R1, [R6, #92]
+  0x080024B2:  9802         LDR        R0, [SP, #8]
+  0x080024B4:  4301         ORRS       R1, R0
+  0x080024B6:  65F1         STR        R1, [R6, #92]
+
.L85:
+  0x080024B8:  68A1         LDR        R1, [R4, #8]
+  0x080024BA:  07C9         LSLS       R1, R1, #31
+  0x080024BC:  6DB1         LDR        R1, [R6, #88]
+  0x080024BE:  D12D         BNE        .L90                     ; 0x0800251C
+  0x080024C0:  48C8         LDR        R0, =0xFFFFFEFD          ; [PC, #0x0320] [0x080027E4] 
+  0x080024C2:  4001         ANDS       R1, R0
+  0x080024C4:  9812         LDR        R0, [SP, #72]
+  0x080024C6:  4301         ORRS       R1, R0
+  0x080024C8:  65B1         STR        R1, [R6, #88]
+  0x080024CA:  68E1         LDR        R1, [R4, #12]
+  0x080024CC:  68E2         LDR        R2, [R4, #12]
+  0x080024CE:  4BC6         LDR        R3, =0xFFFF7FFC          ; [PC, #0x0318] [0x080027E8] 
+  0x080024D0:  4013         ANDS       R3, R2
+  0x080024D2:  60E3         STR        R3, [R4, #12]
+  0x080024D4:  981E         LDR        R0, [SP, #120]
+  0x080024D6:  1CC0         ADDS       R0, R0, #3
+  0x080024D8:  4008         ANDS       R0, R1
+  0x080024DA:  9001         STR        R0, [SP, #4]
+  0x080024DC:  4622         MOV        R2, R4
+  0x080024DE:  32B4         ADDS       R2, #180
+  0x080024E0:  2300         MOVS       R3, #0
+  0x080024E2:  461F         MOV        R7, R3
+
.L86:
+  0x080024E4:  2F08         CMP        R7, #8
+  0x080024E6:  68A1         LDR        R1, [R4, #8]
+  0x080024E8:  48BC         LDR        R0, =0x7FFFFFE8          ; [PC, #0x02F0] [0x080027DC] 
+  0x080024EA:  D101         BNE        .L87                     ; 0x080024F0
+  0x080024EC:  F001 FFA7    BL         .L282                    ; 0x0800443E
+
.L87:
+  0x080024F0:  4001         ANDS       R1, R0
+  0x080024F2:  1841         ADDS       R1, R0, R1
+  0x080024F4:  3118         ADDS       R1, #24
+  0x080024F6:  60A1         STR        R1, [R4, #8]
+
.L88:
+  0x080024F8:  68A1         LDR        R1, [R4, #8]
+  0x080024FA:  2900         CMP        R1, #0
+  0x080024FC:  D507         BPL        .L89                     ; 0x0800250E
+  0x080024FE:  9929         LDR        R1, [SP, #164]
+  0x08002500:  1C49         ADDS       R1, R1, #1
+  0x08002502:  9129         STR        R1, [SP, #164]
+  0x08002504:  9929         LDR        R1, [SP, #164]
+  0x08002506:  0AC9         LSRS       R1, R1, #11
+  0x08002508:  2957         CMP        R1, #87
+  0x0800250A:  D3F5         BCC        .L88                     ; 0x080024F8
+  0x0800250C:  E00C         B          .L92                     ; 0x08002528
+
.L89:
+  0x0800250E:  6811         LDR        R1, [R2]
+  0x08002510:  207F         MOVS       R0, #127
+  0x08002512:  4008         ANDS       R0, R1
+  0x08002514:  1818         ADDS       R0, R3, R0
+  0x08002516:  1C43         ADDS       R3, R0, #1
+  0x08002518:  1C7F         ADDS       R7, R7, #1
+  0x0800251A:  E7E3         B          .L86                     ; 0x080024E4
+
.L90:
+  0x0800251C:  981A         LDR        R0, [SP, #104]
+  0x0800251E:  4301         ORRS       R1, R0
+
.L91:
+  0x08002520:  9823         LDR        R0, [SP, #140]
+  0x08002522:  54F0         STRB       R0, [R6, R3]
+  0x08002524:  65B1         STR        R1, [R6, #88]
+  0x08002526:  E009         B          .L93                     ; 0x0800253C
+
.L92:
+  0x08002528:  2000         MOVS       R0, #0
+  0x0800252A:  9B21         LDR        R3, [SP, #132]
+  0x0800252C:  54F0         STRB       R0, [R6, R3]
+  0x0800252E:  6DB1         LDR        R1, [R6, #88]
+  0x08002530:  9A1A         LDR        R2, [SP, #104]
+  0x08002532:  4311         ORRS       R1, R2
+  0x08002534:  9A12         LDR        R2, [SP, #72]
+  0x08002536:  4391         BICS       R1, R2
+  0x08002538:  65B1         STR        R1, [R6, #88]
+  0x0800253A:  4F9F         LDR        R7, =0x000003C7          ; [PC, #0x027C] [0x080027B8] 
+
.L93:
+  0x0800253C:  68A1         LDR        R1, [R4, #8]
+  0x0800253E:  0749         LSLS       R1, R1, #29
+  0x08002540:  D459         BMI        .L100                    ; 0x080025F6
+  0x08002542:  2800         CMP        R0, #0
+  0x08002544:  D157         BNE        .L100                    ; 0x080025F6
+  0x08002546:  2201         MOVS       R2, #1
+  0x08002548:  54F2         STRB       R2, [R6, R3]
+  0x0800254A:  68E0         LDR        R0, [R4, #12]
+  0x0800254C:  07C0         LSLS       R0, R0, #31
+  0x0800254E:  D10B         BNE        .L95                     ; 0x08002568
+  0x08002550:  68A0         LDR        R0, [R4, #8]
+  0x08002552:  07C0         LSLS       R0, R0, #31
+  0x08002554:  D005         BEQ        .L94                     ; 0x08002562
+  0x08002556:  68A0         LDR        R0, [R4, #8]
+  0x08002558:  49A0         LDR        R1, =0x7FFFFFE8          ; [PC, #0x0280] [0x080027DC] 
+  0x0800255A:  4008         ANDS       R0, R1
+  0x0800255C:  9912         LDR        R1, [SP, #72]
+  0x0800255E:  4308         ORRS       R0, R1
+  0x08002560:  60A0         STR        R0, [R4, #8]
+
.L94:
+  0x08002562:  68E0         LDR        R0, [R4, #12]
+  0x08002564:  4310         ORRS       R0, R2
+  0x08002566:  60E0         STR        R0, [R4, #12]
+
.L95:
+  0x08002568:  2000         MOVS       R0, #0
+  0x0800256A:  9023         STR        R0, [SP, #140]
+  0x0800256C:  9029         STR        R0, [SP, #164]
+  0x0800256E:  68A0         LDR        R0, [R4, #8]
+  0x08002570:  07C0         LSLS       R0, R0, #31
+  0x08002572:  D11D         BNE        .L99                     ; 0x080025B0
+  0x08002574:  4899         LDR        R0, =0x7FFFFFE8          ; [PC, #0x0264] [0x080027DC] 
+  0x08002576:  302F         ADDS       R0, #47
+  0x08002578:  68A1         LDR        R1, [R4, #8]
+  0x0800257A:  4201         TST        R1, R0
+  0x0800257C:  D007         BEQ        .L97                     ; 0x0800258E
+
.L96:
+  0x0800257E:  6DB0         LDR        R0, [R6, #88]
+  0x08002580:  991A         LDR        R1, [SP, #104]
+  0x08002582:  4308         ORRS       R0, R1
+  0x08002584:  65B0         STR        R0, [R6, #88]
+  0x08002586:  6DF0         LDR        R0, [R6, #92]
+  0x08002588:  4310         ORRS       R0, R2
+  0x0800258A:  65F0         STR        R0, [R6, #92]
+  0x0800258C:  E033         B          .L100                    ; 0x080025F6
+
.L97:
+  0x0800258E:  68A0         LDR        R0, [R4, #8]
+  0x08002590:  4992         LDR        R1, =0x7FFFFFE8          ; [PC, #0x0248] [0x080027DC] 
+  0x08002592:  4008         ANDS       R0, R1
+  0x08002594:  4310         ORRS       R0, R2
+  0x08002596:  60A0         STR        R0, [R4, #8]
+  0x08002598:  4894         LDR        R0, =0x40012708          ; [PC, #0x0250] [0x080027EC] 
+  0x0800259A:  6800         LDR        R0, [R0]
+  0x0800259C:  0200         LSLS       R0, R0, #8
+  0x0800259E:  9203         STR        R2, [SP, #12]
+  0x080025A0:  D501         BPL        .L98                     ; 0x080025A6
+  0x080025A2:  F001 FF24    BL         .L275                    ; 0x080043EE
+
.L98:
+  0x080025A6:  7E70         LDRB       R0, [R6, #25]
+  0x080025A8:  2801         CMP        R0, #1
+  0x080025AA:  D001         BEQ        .L99                     ; 0x080025B0
+  0x080025AC:  F001 FF30    BL         .L278                    ; 0x08004410
+
.L99:
+  0x080025B0:  9A23         LDR        R2, [SP, #140]
+  0x080025B2:  54F2         STRB       R2, [R6, R3]
+  0x080025B4:  6DB0         LDR        R0, [R6, #88]
+  0x080025B6:  498E         LDR        R1, =0xFFFFF0FE          ; [PC, #0x0238] [0x080027F0] 
+  0x080025B8:  4008         ANDS       R0, R1
+  0x080025BA:  9910         LDR        R1, [SP, #64]
+  0x080025BC:  4308         ORRS       R0, R1
+  0x080025BE:  65B0         STR        R0, [R6, #88]
+  0x080025C0:  65F2         STR        R2, [R6, #92]
+  0x080025C2:  9804         LDR        R0, [SP, #16]
+  0x080025C4:  6020         STR        R0, [R4]
+  0x080025C6:  6D30         LDR        R0, [R6, #80]
+  0x080025C8:  498A         LDR        R1, =ADC_DMAError        ; [PC, #0x0228] [0x080027F4] =0x08005DF7 
+  0x080025CA:  4A8B         LDR        R2, =ADC_DMAHalfConvCplt ; [PC, #0x022C] [0x080027F8] =0x08005811 
+  0x080025CC:  4B8B         LDR        R3, =ADC_DMAConvCplt     ; [PC, #0x022C] [0x080027FC] =0x08005D93 
+  0x080025CE:  62C3         STR        R3, [R0, #44]
+  0x080025D0:  6302         STR        R2, [R0, #48]
+  0x080025D2:  6341         STR        R1, [R0, #52]
+  0x080025D4:  6861         LDR        R1, [R4, #4]
+  0x080025D6:  9A1A         LDR        R2, [SP, #104]
+  0x080025D8:  4311         ORRS       R1, R2
+  0x080025DA:  6061         STR        R1, [R4, #4]
+  0x080025DC:  3440         ADDS       R4, #64
+  0x080025DE:  4A88         LDR        R2, =adcData             ; [PC, #0x0220] [0x08002800] =0x20000660 
+  0x080025E0:  2305         MOVS       R3, #5
+  0x080025E2:  4621         MOV        R1, R4
+  0x080025E4:  F7FE FA1E    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080025E8:  6830         LDR        R0, [R6]
+  0x080025EA:  6881         LDR        R1, [R0, #8]
+  0x080025EC:  4A7B         LDR        R2, =0x7FFFFFE8          ; [PC, #0x01EC] [0x080027DC] 
+  0x080025EE:  4011         ANDS       R1, R2
+  0x080025F0:  9A0F         LDR        R2, [SP, #60]
+  0x080025F2:  4311         ORRS       R1, R2
+  0x080025F4:  6081         STR        R1, [R0, #8]
+
.L100:
+  0x080025F6:  4B83         LDR        R3, =htim16              ; [PC, #0x020C] [0x08002804] =0x20000614 
+  0x080025F8:  6818         LDR        R0, [R3]
+  0x080025FA:  2200         MOVS       R2, #0
+  0x080025FC:  6242         STR        R2, [R0, #36]
+  0x080025FE:  4982         LDR        R1, =ic_overflows        ; [PC, #0x0208] [0x08002808] =0x200006DC 
+  0x08002600:  9223         STR        R2, [SP, #140]
+  0x08002602:  600A         STR        R2, [R1]
+  0x08002604:  9C0C         LDR        R4, [SP, #48]
+  0x08002606:  5D19         LDRB       R1, [R3, R4]
+  0x08002608:  2901         CMP        R1, #1
+  0x0800260A:  D117         BNE        .L103                    ; 0x0800263C
+  0x0800260C:  2102         MOVS       R1, #2
+  0x0800260E:  5519         STRB       R1, [R3, R4]
+  0x08002610:  68C2         LDR        R2, [R0, #12]
+  0x08002612:  2101         MOVS       R1, #1
+  0x08002614:  430A         ORRS       R2, R1
+  0x08002616:  60C2         STR        R2, [R0, #12]
+  0x08002618:  4A7C         LDR        R2, =0x40012C00          ; [PC, #0x01F0] [0x0800280C] 
+  0x0800261A:  4290         CMP        R0, R2
+  0x0800261C:  D002         BEQ        .L101                    ; 0x08002624
+  0x0800261E:  4A7C         LDR        R2, =0x40000400          ; [PC, #0x01F0] [0x08002810] 
+  0x08002620:  4290         CMP        R0, R2
+  0x08002622:  D108         BNE        .L102                    ; 0x08002636
+
.L101:
+  0x08002624:  4B7B         LDR        R3, =0x0000FFFF          ; [PC, #0x01EC] [0x08002814] 
+  0x08002626:  3308         ADDS       R3, #8
+  0x08002628:  6882         LDR        R2, [R0, #8]
+  0x0800262A:  401A         ANDS       R2, R3
+  0x0800262C:  2A06         CMP        R2, #6
+  0x0800262E:  D005         BEQ        .L103                    ; 0x0800263C
+  0x08002630:  040B         LSLS       R3, R1, #16
+  0x08002632:  429A         CMP        R2, R3
+  0x08002634:  D002         BEQ        .L103                    ; 0x0800263C
+
.L102:
+  0x08002636:  6802         LDR        R2, [R0]
+  0x08002638:  430A         ORRS       R2, R1
+  0x0800263A:  6002         STR        R2, [R0]
+
.L103:
+  0x0800263C:  4A71         LDR        R2, =htim16              ; [PC, #0x01C4] [0x08002804] =0x20000614 
+  0x0800263E:  9B1C         LDR        R3, [SP, #112]
+  0x08002640:  5CD1         LDRB       R1, [R2, R3]
+  0x08002642:  2901         CMP        R1, #1
+  0x08002644:  9911         LDR        R1, [SP, #68]
+  0x08002646:  5C51         LDRB       R1, [R2, R1]
+  0x08002648:  4C73         LDR        R4, =modbusData          ; [PC, #0x01CC] [0x08002818] =0x20000000 
+  0x0800264A:  D121         BNE        .L106                    ; 0x08002690
+  0x0800264C:  2901         CMP        R1, #1
+  0x0800264E:  D11F         BNE        .L106                    ; 0x08002690
+  0x08002650:  2102         MOVS       R1, #2
+  0x08002652:  54D1         STRB       R1, [R2, R3]
+  0x08002654:  9B11         LDR        R3, [SP, #68]
+  0x08002656:  54D1         STRB       R1, [R2, R3]
+  0x08002658:  68C2         LDR        R2, [R0, #12]
+  0x0800265A:  430A         ORRS       R2, R1
+  0x0800265C:  60C2         STR        R2, [R0, #12]
+  0x0800265E:  6A02         LDR        R2, [R0, #32]
+  0x08002660:  2101         MOVS       R1, #1
+  0x08002662:  438A         BICS       R2, R1
+  0x08002664:  6202         STR        R2, [R0, #32]
+  0x08002666:  6A02         LDR        R2, [R0, #32]
+  0x08002668:  430A         ORRS       R2, R1
+  0x0800266A:  6202         STR        R2, [R0, #32]
+  0x0800266C:  4A67         LDR        R2, =0x40012C00          ; [PC, #0x019C] [0x0800280C] 
+  0x0800266E:  4290         CMP        R0, R2
+  0x08002670:  D002         BEQ        .L104                    ; 0x08002678
+  0x08002672:  4A67         LDR        R2, =0x40000400          ; [PC, #0x019C] [0x08002810] 
+  0x08002674:  4290         CMP        R0, R2
+  0x08002676:  D108         BNE        .L105                    ; 0x0800268A
+
.L104:
+  0x08002678:  4B66         LDR        R3, =0x0000FFFF          ; [PC, #0x0198] [0x08002814] 
+  0x0800267A:  3308         ADDS       R3, #8
+  0x0800267C:  6882         LDR        R2, [R0, #8]
+  0x0800267E:  401A         ANDS       R2, R3
+  0x08002680:  2A06         CMP        R2, #6
+  0x08002682:  D005         BEQ        .L106                    ; 0x08002690
+  0x08002684:  040B         LSLS       R3, R1, #16
+  0x08002686:  429A         CMP        R2, R3
+  0x08002688:  D002         BEQ        .L106                    ; 0x08002690
+
.L105:
+  0x0800268A:  6802         LDR        R2, [R0]
+  0x0800268C:  430A         ORRS       R2, R1
+  0x0800268E:  6002         STR        R2, [R0]
+
.L106:
+  0x08002690:  9518         STR        R5, [SP, #96]
+
.L107:
+  0x08002692:  4862         LDR        R0, =0x40003000          ; [PC, #0x0188] [0x0800281C] 
+  0x08002694:  4962         LDR        R1, =0x0000AAAA          ; [PC, #0x0188] [0x08002820] 
+  0x08002696:  6001         STR        R1, [R0]
+  0x08002698:  7D20         LDRB       R0, [R4, #20]
+  0x0800269A:  2801         CMP        R0, #1
+  0x0800269C:  D10E         BNE        .L110                    ; 0x080026BC
+  0x0800269E:  9819         LDR        R0, [SP, #100]
+  0x080026A0:  00C0         LSLS       R0, R0, #3
+  0x080026A2:  9021         STR        R0, [SP, #132]
+  0x080026A4:  5827         LDR        R7, [R4, R0]
+  0x080026A6:  2F05         CMP        R7, #5
+  0x080026A8:  D223         BCS        .L113                    ; 0x080026F2
+
.L108:
+  0x080026AA:  2000         MOVS       R0, #0
+  0x080026AC:  9921         LDR        R1, [SP, #132]
+  0x080026AE:  5060         STR        R0, [R4, R1]
+  0x080026B0:  7520         STRB       R0, [R4, #20]
+  0x080026B2:  208C         MOVS       R0, #140
+  0x080026B4:  2122         MOVS       R1, #34
+  0x080026B6:  4A5B         LDR        R2, =huart1              ; [PC, #0x016C] [0x08002824] =0x200003BC 
+  0x080026B8:  5011         STR        R1, [R2, R0]
+
.L109:
+  0x080026BA:  4F3F         LDR        R7, =0x000003C7          ; [PC, #252] [0x080027B8] 
+
.L110:
+  0x080026BC:  4848         LDR        R0, =uwTick              ; [PC, #0x0120] [0x080027E0] =0x2000068C 
+  0x080026BE:  6800         LDR        R0, [R0]
+  0x080026C0:  4959         LDR        R1, =oldTimeMSTick       ; [PC, #0x0164] [0x08002828] =0x200006AC 
+  0x080026C2:  6809         LDR        R1, [R1]
+  0x080026C4:  4281         CMP        R1, R0
+  0x080026C6:  D102         BNE        .L111                    ; 0x080026CE
+  0x080026C8:  4858         LDR        R0, =msCounter           ; [PC, #0x0160] [0x0800282C] =0x200006C0 
+  0x080026CA:  6800         LDR        R0, [R0]
+  0x080026CC:  E1B5         B          .L151                    ; 0x08002A3A
+
.L111:
+  0x080026CE:  4838         LDR        R0, =0x50000410          ; [PC, #224] [0x080027B0] 
+  0x080026D0:  6800         LDR        R0, [R0]
+  0x080026D2:  07C0         LSLS       R0, R0, #31
+  0x080026D4:  4C56         LDR        R4, =longPressCounterButtonOn ; [PC, #0x0158] [0x08002830] =0x200006C4 
+  0x080026D6:  6820         LDR        R0, [R4]
+  0x080026D8:  D001         BEQ        .L112                    ; 0x080026DE
+  0x080026DA:  1C40         ADDS       R0, R0, #1
+  0x080026DC:  6020         STR        R0, [R4]
+
.L112:
+  0x080026DE:  4955         LDR        R1, =0x00001388          ; [PC, #0x0154] [0x08002834] 
+  0x080026E0:  4288         CMP        R0, R1
+  0x080026E2:  D947         BLS        .L120                    ; 0x08002774
+  0x080026E4:  4854         LDR        R0, =buttonState         ; [PC, #0x0150] [0x08002838] =0x2000073A 
+  0x080026E6:  7800         LDRB       R0, [R0]
+  0x080026E8:  2802         CMP        R0, #2
+  0x080026EA:  D053         BEQ        .L122                    ; 0x08002794
+  0x080026EC:  4853         LDR        R0, =0x08006878          ; [PC, #0x014C] [0x0800283C] 
+  0x080026EE:  9E12         LDR        R6, [SP, #72]
+  0x080026F0:  E04C         B          .L121                    ; 0x0800278C
+
.L113:
+  0x080026F2:  2027         MOVS       R0, #39
+  0x080026F4:  5C20         LDRB       R0, [R4, R0]
+  0x080026F6:  901C         STR        R0, [SP, #112]
+  0x080026F8:  1EBE         SUBS       R6, R7, #2
+  0x080026FA:  9817         LDR        R0, [SP, #92]
+  0x080026FC:  4631         MOV        R1, R6
+  0x080026FE:  F001 FFAB    BL         mbCrc16                  ; 0x08004658
+  0x08002702:  1C79         ADDS       R1, R7, #1
+  0x08002704:  D0D1         BEQ        .L108                    ; 0x080026AA
+  0x08002706:  9917         LDR        R1, [SP, #92]
+  0x08002708:  5D89         LDRB       R1, [R1, R6]
+  0x0800270A:  19E2         ADDS       R2, R4, R7
+  0x0800270C:  9B22         LDR        R3, [SP, #136]
+  0x0800270E:  5CD2         LDRB       R2, [R2, R3]
+  0x08002710:  0212         LSLS       R2, R2, #8
+  0x08002712:  1851         ADDS       R1, R2, R1
+  0x08002714:  4281         CMP        R1, R0
+  0x08002716:  D1C8         BNE        .L108                    ; 0x080026AA
+  0x08002718:  981C         LDR        R0, [SP, #112]
+  0x0800271A:  2800         CMP        R0, #0
+  0x0800271C:  D004         BEQ        .L114                    ; 0x08002728
+  0x0800271E:  482A         LDR        R0, =sys_data            ; [PC, #168] [0x080027C8] =0x20000234 
+  0x08002720:  8B00         LDRH       R0, [R0, #24]
+  0x08002722:  991C         LDR        R1, [SP, #112]
+  0x08002724:  4288         CMP        R0, R1
+  0x08002726:  D1C0         BNE        .L108                    ; 0x080026AA
+
.L114:
+  0x08002728:  9F13         LDR        R7, [SP, #76]
+  0x0800272A:  3728         ADDS       R7, #40
+  0x0800272C:  9B1C         LDR        R3, [SP, #112]
+  0x0800272E:  55E3         STRB       R3, [R4, R7]
+  0x08002730:  218B         MOVS       R1, #139
+  0x08002732:  0088         LSLS       R0, R1, #2
+  0x08002734:  9011         STR        R0, [SP, #68]
+  0x08002736:  2100         MOVS       R1, #0
+  0x08002738:  5021         STR        R1, [R4, R0]
+  0x0800273A:  2228         MOVS       R2, #40
+  0x0800273C:  5CA2         LDRB       R2, [R4, R2]
+  0x0800273E:  2A10         CMP        R2, #16
+  0x08002740:  970C         STR        R7, [SP, #48]
+  0x08002742:  D101         BNE        .L115                    ; 0x08002748
+  0x08002744:  F001 FA29    BL         .L217                    ; 0x08003B9A
+
.L115:
+  0x08002748:  2A06         CMP        R2, #6
+  0x0800274A:  D101         BNE        .L116                    ; 0x08002750
+  0x0800274C:  F001 FA12    BL         .L214                    ; 0x08003B74
+
.L116:
+  0x08002750:  2A03         CMP        R2, #3
+  0x08002752:  D001         BEQ        .L117                    ; 0x08002758
+  0x08002754:  F001 FA2B    BL         .L219                    ; 0x08003BAE
+
.L117:
+  0x08002758:  4A1B         LDR        R2, =sys_data            ; [PC, #108] [0x080027C8] =0x20000234 
+  0x0800275A:  8B12         LDRH       R2, [R2, #24]
+  0x0800275C:  2B00         CMP        R3, #0
+  0x0800275E:  D101         BNE        .L118                    ; 0x08002764
+  0x08002760:  F001 FA41    BL         .L223                    ; 0x08003BE6
+
.L118:
+  0x08002764:  429A         CMP        R2, R3
+  0x08002766:  D101         BNE        .L119                    ; 0x0800276C
+  0x08002768:  F001 FA3D    BL         .L223                    ; 0x08003BE6
+
.L119:
+  0x0800276C:  2386         MOVS       R3, #134
+  0x0800276E:  9A06         LDR        R2, [SP, #24]
+  0x08002770:  F001 FA47    BL         .L225                    ; 0x08003C02
+
.L120:
+  0x08002774:  280B         CMP        R0, #11
+  0x08002776:  D30D         BCC        .L122                    ; 0x08002794
+  0x08002778:  482F         LDR        R0, =buttonState         ; [PC, #188] [0x08002838] =0x2000073A 
+  0x0800277A:  7800         LDRB       R0, [R0]
+  0x0800277C:  490C         LDR        R1, =0x50000410          ; [PC, #48] [0x080027B0] 
+  0x0800277E:  6809         LDR        R1, [R1]
+  0x08002780:  07C9         LSLS       R1, R1, #31
+  0x08002782:  D107         BNE        .L122                    ; 0x08002794
+  0x08002784:  2801         CMP        R0, #1
+  0x08002786:  D005         BEQ        .L122                    ; 0x08002794
+  0x08002788:  2601         MOVS       R6, #1
+  0x0800278A:  48F3         LDR        R0, =0x080063EB          ; [PC, #0x03CC] [0x08002B58] 
+
.L121:
+  0x0800278C:  F002 FD32    BL         puts                     ; 0x080051F4
+  0x08002790:  4829         LDR        R0, =buttonState         ; [PC, #164] [0x08002838] =0x2000073A 
+  0x08002792:  7006         STRB       R6, [R0]
+
.L122:
+  0x08002794:  4806         LDR        R0, =0x50000410          ; [PC, #24] [0x080027B0] 
+  0x08002796:  6800         LDR        R0, [R0]
+  0x08002798:  07C0         LSLS       R0, R0, #31
+  0x0800279A:  D100         BNE        .L123                    ; 0x0800279E
+  0x0800279C:  6020         STR        R0, [R4]
+
.L123:
+  0x0800279E:  4804         LDR        R0, =0x50000410          ; [PC, #16] [0x080027B0] 
+  0x080027A0:  6800         LDR        R0, [R0]
+  0x080027A2:  0780         LSLS       R0, R0, #30
+  0x080027A4:  48ED         LDR        R0, =longPressCounterButtonOff ; [PC, #0x03B4] [0x08002B5C] =0x200006C8 
+  0x080027A6:  D44B         BMI        .L124                    ; 0x08002840
+  0x080027A8:  2100         MOVS       R1, #0
+  0x080027AA:  6001         STR        R1, [R0]
+  0x080027AC:  E056         B          .L125                    ; 0x0800285C
+  0x080027AE:  46C0         NOP
+  0x080027B0:  50000410     DC.W       0x50000410
+  0x080027B4:  50000818     DC.W       0x50000818
+  0x080027B8:  000003C7     DC.W       0x000003C7
+  0x080027BC:  50000010     DC.W       0x50000010
+  0x080027C0:  20000739     DC.W       mode
+  0x080027C4:  080067D2     DC.W       080067D2               ; R_ARM_ABS32
+  0x080027C8:  20000234     DC.W       sys_data
+  0x080027CC:  1FFF7568     DC.W       0x1FFF7568
+  0x080027D0:  453B8000     DC.W       0x453B8000
+  0x080027D4:  200006E8     DC.W       calTemperatureSensor30Value
+  0x080027D8:  20000450     DC.W       hadc1
+  0x080027DC:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x080027E0:  2000068C     DC.W       uwTick
+  0x080027E4:  FFFFFEFD     DC.W       0xFFFFFEFD
+  0x080027E8:  FFFF7FFC     DC.W       0xFFFF7FFC
+  0x080027EC:  40012708     DC.W       0x40012708
+  0x080027F0:  FFFFF0FE     DC.W       0xFFFFF0FE
+  0x080027F4:  08005DF7     DC.W       ADC_DMAError
+  0x080027F8:  08005811     DC.W       ADC_DMAHalfConvCplt
+  0x080027FC:  08005D93     DC.W       ADC_DMAConvCplt
+  0x08002800:  20000660     DC.W       adcData
+  0x08002804:  20000614     DC.W       htim16
+  0x08002808:  200006DC     DC.W       ic_overflows
+  0x0800280C:  40012C00     DC.W       0x40012C00
+  0x08002810:  40000400     DC.W       0x40000400
+  0x08002814:  0000FFFF     DC.W       0x0000FFFF
+  0x08002818:  20000000     DC.W       modbusData
+  0x0800281C:  40003000     DC.W       0x40003000
+  0x08002820:  0000AAAA     DC.W       0x0000AAAA
+  0x08002824:  200003BC     DC.W       huart1
+  0x08002828:  200006AC     DC.W       oldTimeMSTick
+  0x0800282C:  200006C0     DC.W       msCounter
+  0x08002830:  200006C4     DC.W       longPressCounterButtonOn
+  0x08002834:  00001388     DC.W       0x00001388
+  0x08002838:  2000073A     DC.W       buttonState
+  0x0800283C:  08006878     DC.W       08006878               ; R_ARM_ABS32
+
.L124:
+  0x08002840:  6801         LDR        R1, [R0]
+  0x08002842:  1C49         ADDS       R1, R1, #1
+  0x08002844:  6001         STR        R1, [R0]
+  0x08002846:  290B         CMP        R1, #11
+  0x08002848:  D308         BCC        .L125                    ; 0x0800285C
+  0x0800284A:  4CE4         LDR        R4, =buttonState         ; [PC, #0x0390] [0x08002BDC] =0x2000073A 
+  0x0800284C:  7820         LDRB       R0, [R4]
+  0x0800284E:  2800         CMP        R0, #0
+  0x08002850:  D004         BEQ        .L125                    ; 0x0800285C
+  0x08002852:  48E3         LDR        R0, =0x080065AD          ; [PC, #0x038C] [0x08002BE0] 
+  0x08002854:  F002 FCCE    BL         puts                     ; 0x080051F4
+  0x08002858:  2000         MOVS       R0, #0
+  0x0800285A:  7020         STRB       R0, [R4]
+
.L125:
+  0x0800285C:  48E1         LDR        R0, =onTimeCounter       ; [PC, #0x0384] [0x08002BE4] =0x200006A8 
+  0x0800285E:  6801         LDR        R1, [R0]
+  0x08002860:  2900         CMP        R1, #0
+  0x08002862:  D012         BEQ        .L127                    ; 0x0800288A
+  0x08002864:  1E49         SUBS       R1, R1, #1
+  0x08002866:  6001         STR        R1, [R0]
+  0x08002868:  D10F         BNE        .L127                    ; 0x0800288A
+  0x0800286A:  49DF         LDR        R1, =0x50000410          ; [PC, #0x037C] [0x08002BE8] 
+  0x0800286C:  9A20         LDR        R2, [SP, #128]
+  0x0800286E:  618A         STR        R2, [R1, #24]
+  0x08002870:  49DE         LDR        R1, =alarmMode           ; [PC, #0x0378] [0x08002BEC] =0x2000075C 
+  0x08002872:  7809         LDRB       R1, [R1]
+  0x08002874:  2901         CMP        R1, #1
+  0x08002876:  D108         BNE        .L127                    ; 0x0800288A
+  0x08002878:  49DD         LDR        R1, =offTime             ; [PC, #0x0374] [0x08002BF0] =0x20000750 
+  0x0800287A:  780A         LDRB       R2, [R1]
+  0x0800287C:  2A00         CMP        R2, #0
+  0x0800287E:  49DD         LDR        R1, =0x00001388          ; [PC, #0x0374] [0x08002BF4] 
+  0x08002880:  D100         BNE        .L126                    ; 0x08002884
+  0x08002882:  2100         MOVS       R1, #0
+
.L126:
+  0x08002884:  4AF5         LDR        R2, =offTimeCounter      ; [PC, #0x03D4] [0x08002C5C] =0x200006B8 
+  0x08002886:  6011         STR        R1, [R2]
+  0x08002888:  E001         B          .L128                    ; 0x0800288E
+
.L127:
+  0x0800288A:  49F4         LDR        R1, =offTimeCounter      ; [PC, #0x03D0] [0x08002C5C] =0x200006B8 
+  0x0800288C:  6809         LDR        R1, [R1]
+
.L128:
+  0x0800288E:  2900         CMP        R1, #0
+  0x08002890:  D00C         BEQ        .L130                    ; 0x080028AC
+  0x08002892:  1E49         SUBS       R1, R1, #1
+  0x08002894:  4AF1         LDR        R2, =offTimeCounter      ; [PC, #0x03C4] [0x08002C5C] =0x200006B8 
+  0x08002896:  6011         STR        R1, [R2]
+  0x08002898:  D108         BNE        .L130                    ; 0x080028AC
+  0x0800289A:  49F3         LDR        R1, =0x50000410          ; [PC, #0x03CC] [0x08002C68] 
+  0x0800289C:  9A20         LDR        R2, [SP, #128]
+  0x0800289E:  608A         STR        R2, [R1, #8]
+  0x080028A0:  49F3         LDR        R1, =onTime              ; [PC, #0x03CC] [0x08002C70] =0x20000744 
+  0x080028A2:  7809         LDRB       R1, [R1]
+  0x080028A4:  2900         CMP        R1, #0
+  0x080028A6:  D000         BEQ        .L129                    ; 0x080028AA
+  0x080028A8:  21C8         MOVS       R1, #200
+
.L129:
+  0x080028AA:  6001         STR        R1, [R0]
+
.L130:
+  0x080028AC:  4CF1         LDR        R4, =adcData             ; [PC, #0x03C4] [0x08002C74] =0x20000660 
+  0x080028AE:  6820         LDR        R0, [R4]
+  0x080028B0:  49F1         LDR        R1, =0x00000CE4          ; [PC, #0x03C4] [0x08002C78] 
+  0x080028B2:  4348         MULS       R0, R1, R0
+  0x080028B4:  49F1         LDR        R1, =0x00010063          ; [PC, #0x03C4] [0x08002C7C] 
+  0x080028B6:  F003 FBC6    BL         __aeabi_idiv             ; 0x08006046
+  0x080028BA:  49F1         LDR        R1, =0xFFFFFCFF          ; [PC, #0x03C4] [0x08002C80] 
+  0x080028BC:  1808         ADDS       R0, R1, R0
+  0x080028BE:  30A9         ADDS       R0, #169
+  0x080028C0:  210A         MOVS       R1, #10
+  0x080028C2:  F003 FBC0    BL         __aeabi_idiv             ; 0x08006046
+  0x080028C6:  49EF         LDR        R1, =relais_temperature  ; [PC, #0x03BC] [0x08002C84] =0x20000694 
+  0x080028C8:  6008         STR        R0, [R1]
+  0x080028CA:  48EF         LDR        R0, =onTimeCounterSET    ; [PC, #0x03BC] [0x08002C88] =0x20000698 
+  0x080028CC:  6801         LDR        R1, [R0]
+  0x080028CE:  2900         CMP        R1, #0
+  0x080028D0:  D005         BEQ        .L131                    ; 0x080028DE
+  0x080028D2:  1E49         SUBS       R1, R1, #1
+  0x080028D4:  6001         STR        R1, [R0]
+  0x080028D6:  D102         BNE        .L131                    ; 0x080028DE
+  0x080028D8:  48E3         LDR        R0, =0x50000410          ; [PC, #0x038C] [0x08002C68] 
+  0x080028DA:  991B         LDR        R1, [SP, #108]
+  0x080028DC:  6181         STR        R1, [R0, #24]
+
.L131:
+  0x080028DE:  48EB         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03AC] [0x08002C8C] =0x200006A0 
+  0x080028E0:  6801         LDR        R1, [R0]
+  0x080028E2:  2900         CMP        R1, #0
+  0x080028E4:  D005         BEQ        .L132                    ; 0x080028F2
+  0x080028E6:  1E49         SUBS       R1, R1, #1
+  0x080028E8:  6001         STR        R1, [R0]
+  0x080028EA:  D102         BNE        .L132                    ; 0x080028F2
+  0x080028EC:  48DE         LDR        R0, =0x50000410          ; [PC, #0x0378] [0x08002C68] 
+  0x080028EE:  991A         LDR        R1, [SP, #104]
+  0x080028F0:  6181         STR        R1, [R0, #24]
+
.L132:
+  0x080028F2:  48E7         LDR        R0, =onTimeCounterGN     ; [PC, #0x039C] [0x08002C90] =0x200006A4 
+  0x080028F4:  6801         LDR        R1, [R0]
+  0x080028F6:  2900         CMP        R1, #0
+  0x080028F8:  D012         BEQ        .L134                    ; 0x08002920
+  0x080028FA:  1E49         SUBS       R1, R1, #1
+  0x080028FC:  6001         STR        R1, [R0]
+  0x080028FE:  D10F         BNE        .L134                    ; 0x08002920
+  0x08002900:  49E4         LDR        R1, =0x50000818          ; [PC, #0x0390] [0x08002C94] 
+  0x08002902:  9A1F         LDR        R2, [SP, #124]
+  0x08002904:  610A         STR        R2, [R1, #16]
+  0x08002906:  49E4         LDR        R1, =blinkModeGN         ; [PC, #0x0390] [0x08002C98] =0x20000758 
+  0x08002908:  7809         LDRB       R1, [R1]
+  0x0800290A:  2901         CMP        R1, #1
+  0x0800290C:  D108         BNE        .L134                    ; 0x08002920
+  0x0800290E:  49E3         LDR        R1, =offTimeGN           ; [PC, #0x038C] [0x08002C9C] =0x2000074C 
+  0x08002910:  780A         LDRB       R2, [R1]
+  0x08002912:  2A00         CMP        R2, #0
+  0x08002914:  990B         LDR        R1, [SP, #44]
+  0x08002916:  D100         BNE        .L133                    ; 0x0800291A
+  0x08002918:  2100         MOVS       R1, #0
+
.L133:
+  0x0800291A:  4AE1         LDR        R2, =offTimeCounterGN    ; [PC, #0x0384] [0x08002CA0] =0x200006B4 
+  0x0800291C:  6011         STR        R1, [R2]
+  0x0800291E:  E001         B          .L135                    ; 0x08002924
+
.L134:
+  0x08002920:  49DF         LDR        R1, =offTimeCounterGN    ; [PC, #0x037C] [0x08002CA0] =0x200006B4 
+  0x08002922:  6809         LDR        R1, [R1]
+
.L135:
+  0x08002924:  2900         CMP        R1, #0
+  0x08002926:  D00C         BEQ        .L137                    ; 0x08002942
+  0x08002928:  1E49         SUBS       R1, R1, #1
+  0x0800292A:  4AF4         LDR        R2, =offTimeCounterGN    ; [PC, #0x03D0] [0x08002CFC] =0x200006B4 
+  0x0800292C:  6011         STR        R1, [R2]
+  0x0800292E:  D108         BNE        .L137                    ; 0x08002942
+  0x08002930:  49D8         LDR        R1, =0x50000818          ; [PC, #0x0360] [0x08002C94] 
+  0x08002932:  9A1F         LDR        R2, [SP, #124]
+  0x08002934:  600A         STR        R2, [R1]
+  0x08002936:  49F2         LDR        R1, =onTimeGN            ; [PC, #0x03C8] [0x08002D00] =0x20000740 
+  0x08002938:  7809         LDRB       R1, [R1]
+  0x0800293A:  2900         CMP        R1, #0
+  0x0800293C:  D000         BEQ        .L136                    ; 0x08002940
+  0x0800293E:  21C8         MOVS       R1, #200
+
.L136:
+  0x08002940:  6001         STR        R1, [R0]
+
.L137:
+  0x08002942:  48F0         LDR        R0, =onTimeCounterRT     ; [PC, #0x03C0] [0x08002D04] =0x2000069C 
+  0x08002944:  6801         LDR        R1, [R0]
+  0x08002946:  2900         CMP        R1, #0
+  0x08002948:  D002         BEQ        .L138                    ; 0x08002950
+  0x0800294A:  1E49         SUBS       R1, R1, #1
+  0x0800294C:  6001         STR        R1, [R0]
+  0x0800294E:  D006         BEQ        .L140                    ; 0x0800295E
+
.L138:
+  0x08002950:  49F1         LDR        R1, =blinkCounter        ; [PC, #0x03C4] [0x08002D18] =0x200006EC 
+  0x08002952:  6809         LDR        R1, [R1]
+
.L139:
+  0x08002954:  2900         CMP        R1, #0
+  0x08002956:  D018         BEQ        .L143                    ; 0x0800298A
+  0x08002958:  49F0         LDR        R1, =offTimeCounterRT    ; [PC, #0x03C0] [0x08002D1C] =0x200006B0 
+  0x0800295A:  6809         LDR        R1, [R1]
+  0x0800295C:  E021         B          .L145                    ; 0x080029A2
+
.L140:
+  0x0800295E:  49EC         LDR        R1, =0x50000818          ; [PC, #0x03B0] [0x08002D10] 
+  0x08002960:  9A1E         LDR        R2, [SP, #120]
+  0x08002962:  610A         STR        R2, [R1, #16]
+  0x08002964:  49EE         LDR        R1, =blinkModeRT         ; [PC, #0x03B8] [0x08002D20] =0x20000754 
+  0x08002966:  7809         LDRB       R1, [R1]
+  0x08002968:  2901         CMP        R1, #1
+  0x0800296A:  D107         BNE        .L142                    ; 0x0800297C
+  0x0800296C:  49ED         LDR        R1, =offTimeRT           ; [PC, #0x03B4] [0x08002D24] =0x20000748 
+  0x0800296E:  7809         LDRB       R1, [R1]
+  0x08002970:  2900         CMP        R1, #0
+  0x08002972:  D001         BEQ        .L141                    ; 0x08002978
+  0x08002974:  4639         MOV        R1, R7
+  0x08002976:  3121         ADDS       R1, #33
+
.L141:
+  0x08002978:  4AE8         LDR        R2, =offTimeCounterRT    ; [PC, #0x03A0] [0x08002D1C] =0x200006B0 
+  0x0800297A:  6011         STR        R1, [R2]
+
.L142:
+  0x0800297C:  4AE6         LDR        R2, =blinkCounter        ; [PC, #0x0398] [0x08002D18] =0x200006EC 
+  0x0800297E:  6811         LDR        R1, [R2]
+  0x08002980:  2900         CMP        R1, #0
+  0x08002982:  D002         BEQ        .L143                    ; 0x0800298A
+  0x08002984:  1E49         SUBS       R1, R1, #1
+  0x08002986:  6011         STR        R1, [R2]
+  0x08002988:  E7E4         B          .L139                    ; 0x08002954
+
.L143:
+  0x0800298A:  49E7         LDR        R1, =numberOfBlinks      ; [PC, #0x039C] [0x08002D28] =0x200006BC 
+  0x0800298C:  6809         LDR        R1, [R1]
+  0x0800298E:  4AE2         LDR        R2, =blinkCounter        ; [PC, #0x0388] [0x08002D18] =0x200006EC 
+  0x08002990:  6011         STR        R1, [R2]
+  0x08002992:  49E6         LDR        R1, =pauseTime           ; [PC, #0x0398] [0x08002D2C] =0x20000734 
+  0x08002994:  780A         LDRB       R2, [R1]
+  0x08002996:  2A00         CMP        R2, #0
+  0x08002998:  49B4         LDR        R1, =0x00001388          ; [PC, #0x02D0] [0x08002C6C] 
+  0x0800299A:  D100         BNE        .L144                    ; 0x0800299E
+  0x0800299C:  2100         MOVS       R1, #0
+
.L144:
+  0x0800299E:  4ADF         LDR        R2, =offTimeCounterRT    ; [PC, #0x037C] [0x08002D1C] =0x200006B0 
+  0x080029A0:  6011         STR        R1, [R2]
+
.L145:
+  0x080029A2:  2900         CMP        R1, #0
+  0x080029A4:  D00C         BEQ        .L147                    ; 0x080029C0
+  0x080029A6:  1E49         SUBS       R1, R1, #1
+  0x080029A8:  4ADC         LDR        R2, =offTimeCounterRT    ; [PC, #0x0370] [0x08002D1C] =0x200006B0 
+  0x080029AA:  6011         STR        R1, [R2]
+  0x080029AC:  D108         BNE        .L147                    ; 0x080029C0
+  0x080029AE:  49D8         LDR        R1, =0x50000818          ; [PC, #0x0360] [0x08002D10] 
+  0x080029B0:  9A1E         LDR        R2, [SP, #120]
+  0x080029B2:  600A         STR        R2, [R1]
+  0x080029B4:  49DE         LDR        R1, =onTimeRT            ; [PC, #0x0378] [0x08002D30] =0x2000073C 
+  0x080029B6:  7809         LDRB       R1, [R1]
+  0x080029B8:  2900         CMP        R1, #0
+  0x080029BA:  D000         BEQ        .L146                    ; 0x080029BE
+  0x080029BC:  21C8         MOVS       R1, #200
+
.L146:
+  0x080029BE:  6001         STR        R1, [R0]
+
.L147:
+  0x080029C0:  6860         LDR        R0, [R4, #4]
+  0x080029C2:  4DAD         LDR        R5, =0x00000CE4          ; [PC, #0x02B4] [0x08002C78] 
+  0x080029C4:  4368         MULS       R0, R5, R0
+  0x080029C6:  4EAD         LDR        R6, =0x00010063          ; [PC, #0x02B4] [0x08002C7C] 
+  0x080029C8:  4631         MOV        R1, R6
+  0x080029CA:  F003 FB3C    BL         __aeabi_idiv             ; 0x08006046
+  0x080029CE:  4621         MOV        R1, R4
+  0x080029D0:  4604         MOV        R4, R0
+  0x080029D2:  2715         MOVS       R7, #21
+  0x080029D4:  437C         MULS       R4, R7, R4
+  0x080029D6:  48D7         LDR        R0, =voltageUin          ; [PC, #0x035C] [0x08002D34] =0x20000688 
+  0x080029D8:  6004         STR        R4, [R0]
+  0x080029DA:  6888         LDR        R0, [R1, #8]
+  0x080029DC:  4368         MULS       R0, R5, R0
+  0x080029DE:  4631         MOV        R1, R6
+  0x080029E0:  F003 FB31    BL         __aeabi_idiv             ; 0x08006046
+  0x080029E4:  4602         MOV        R2, R0
+  0x080029E6:  437A         MULS       R2, R7, R2
+  0x080029E8:  48D3         LDR        R0, =voltageUout         ; [PC, #0x034C] [0x08002D38] =0x20000684 
+  0x080029EA:  6002         STR        R2, [R0]
+  0x080029EC:  49D3         LDR        R1, =relaisState         ; [PC, #0x034C] [0x08002D3C] =0x20000730 
+  0x080029EE:  48D4         LDR        R0, =dropLimitCounter    ; [PC, #0x0350] [0x08002D40] =0x200006E4 
+  0x080029F0:  7809         LDRB       R1, [R1]
+  0x080029F2:  2901         CMP        R1, #1
+  0x080029F4:  6801         LDR        R1, [R0]
+  0x080029F6:  D112         BNE        .L149                    ; 0x08002A1E
+  0x080029F8:  1AA3         SUBS       R3, R4, R2
+  0x080029FA:  17DE         ASRS       R6, R3, #31
+  0x080029FC:  4073         EORS       R3, R6
+  0x080029FE:  1B9B         SUBS       R3, R3, R6
+  0x08002A00:  2B5B         CMP        R3, #91
+  0x08002A02:  D30C         BCC        .L149                    ; 0x08002A1E
+  0x08002A04:  4FCF         LDR        R7, =0x000003C7          ; [PC, #0x033C] [0x08002D44] 
+  0x08002A06:  463E         MOV        R6, R7
+  0x08002A08:  3621         ADDS       R6, #33
+  0x08002A0A:  42B1         CMP        R1, R6
+  0x08002A0C:  9D18         LDR        R5, [SP, #96]
+  0x08002A0E:  D201         BCS        .L148                    ; 0x08002A14
+  0x08002A10:  1C49         ADDS       R1, R1, #1
+  0x08002A12:  6001         STR        R1, [R0]
+
.L148:
+  0x08002A14:  48CC         LDR        R0, =0x0800635B          ; [PC, #0x0330] [0x08002D48] 
+  0x08002A16:  4621         MOV        R1, R4
+  0x08002A18:  F002 FC46    BL         printf                   ; 0x080052A8
+  0x08002A1C:  E005         B          .L150                    ; 0x08002A2A
+
.L149:
+  0x08002A1E:  2900         CMP        R1, #0
+  0x08002A20:  4FC8         LDR        R7, =0x000003C7          ; [PC, #0x0320] [0x08002D44] 
+  0x08002A22:  9D18         LDR        R5, [SP, #96]
+  0x08002A24:  D001         BEQ        .L150                    ; 0x08002A2A
+  0x08002A26:  1E49         SUBS       R1, R1, #1
+  0x08002A28:  6001         STR        R1, [R0]
+
.L150:
+  0x08002A2A:  48C8         LDR        R0, =uwTick              ; [PC, #0x0320] [0x08002D4C] =0x2000068C 
+  0x08002A2C:  6800         LDR        R0, [R0]
+  0x08002A2E:  49C8         LDR        R1, =oldTimeMSTick       ; [PC, #0x0320] [0x08002D50] =0x200006AC 
+  0x08002A30:  6008         STR        R0, [R1]
+  0x08002A32:  49C8         LDR        R1, =msCounter           ; [PC, #0x0320] [0x08002D54] =0x200006C0 
+  0x08002A34:  6808         LDR        R0, [R1]
+  0x08002A36:  1C40         ADDS       R0, R0, #1
+  0x08002A38:  6008         STR        R0, [R1]
+
.L151:
+  0x08002A3A:  4639         MOV        R1, R7
+  0x08002A3C:  311F         ADDS       R1, #31
+  0x08002A3E:  4288         CMP        R0, R1
+  0x08002A40:  DD6F         BLE        .L156                    ; 0x08002B22
+  0x08002A42:  488C         LDR        R0, =adcData             ; [PC, #0x0230] [0x08002C74] =0x20000660 
+  0x08002A44:  6900         LDR        R0, [R0, #16]
+  0x08002A46:  498C         LDR        R1, =0x00000CE4          ; [PC, #0x0230] [0x08002C78] 
+  0x08002A48:  4348         MULS       R0, R1, R0
+  0x08002A4A:  0C00         LSRS       R0, R0, #16
+  0x08002A4C:  49C2         LDR        R1, =calTemperatureSensor30Value ; [PC, #0x0308] [0x08002D58] =0x200006E8 
+  0x08002A4E:  6809         LDR        R1, [R1]
+  0x08002A50:  1A40         SUBS       R0, R0, R1
+  0x08002A52:  F002 FBE5    BL         __aeabi_i2d              ; 0x08005220
+  0x08002A56:  4AC1         LDR        R2, =0xA3D70A3D          ; [PC, #0x0304] [0x08002D5C] 
+  0x08002A58:  4BC1         LDR        R3, =0x40043D70          ; [PC, #0x0304] [0x08002D60] 
+  0x08002A5A:  F003 FA58    BL         __aeabi_ddiv             ; 0x08005F0E
+  0x08002A5E:  F003 FAB8    BL         __aeabi_d2iz             ; 0x08005FD2
+  0x08002A62:  4604         MOV        R4, R0
+  0x08002A64:  3419         ADDS       R4, #25
+  0x08002A66:  22C8         MOVS       R2, #200
+  0x08002A68:  48BE         LDR        R0, =sys_data            ; [PC, #0x02F8] [0x08002D64] =0x20000234 
+  0x08002A6A:  5284         STRH       R4, [R0, R2]
+  0x08002A6C:  9823         LDR        R0, [SP, #140]
+  0x08002A6E:  1C40         ADDS       R0, R0, #1
+  0x08002A70:  2164         MOVS       R1, #100
+  0x08002A72:  2864         CMP        R0, #100
+  0x08002A74:  D300         BCC        .L152                    ; 0x08002A78
+  0x08002A76:  4608         MOV        R0, R1
+
.L152:
+  0x08002A78:  4BBA         LDR        R3, =sys_data            ; [PC, #0x02E8] [0x08002D64] =0x20000234 
+  0x08002A7A:  5E9B         LDRSH      R3, [R3, R2]
+  0x08002A7C:  2B32         CMP        R3, #50
+  0x08002A7E:  DC00         BGT        .L153                    ; 0x08002A82
+  0x08002A80:  9823         LDR        R0, [SP, #140]
+
.L153:
+  0x08002A82:  1E46         SUBS       R6, R0, #1
+  0x08002A84:  4603         MOV        R3, R0
+  0x08002A86:  41B3         SBCS       R3, R6
+  0x08002A88:  4EB6         LDR        R6, =sys_data            ; [PC, #0x02D8] [0x08002D64] =0x20000234 
+  0x08002A8A:  5EB2         LDRSH      R2, [R6, R2]
+  0x08002A8C:  2601         MOVS       R6, #1
+  0x08002A8E:  2700         MOVS       R7, #0
+  0x08002A90:  2A32         CMP        R2, #50
+  0x08002A92:  4632         MOV        R2, R6
+  0x08002A94:  DB00         BLT        .L154                    ; 0x08002A98
+  0x08002A96:  463A         MOV        R2, R7
+
.L154:
+  0x08002A98:  9721         STR        R7, [SP, #132]
+  0x08002A9A:  401A         ANDS       R2, R3
+  0x08002A9C:  1A82         SUBS       R2, R0, R2
+  0x08002A9E:  2A64         CMP        R2, #100
+  0x08002AA0:  9223         STR        R2, [SP, #140]
+  0x08002AA2:  D300         BCC        .L155                    ; 0x08002AA6
+  0x08002AA4:  460A         MOV        R2, R1
+
.L155:
+  0x08002AA6:  48B0         LDR        R0, =htim17              ; [PC, #0x02C0] [0x08002D68] =0x200005C8 
+  0x08002AA8:  6807         LDR        R7, [R0]
+  0x08002AAA:  6AF8         LDR        R0, [R7, #44]
+  0x08002AAC:  1C40         ADDS       R0, R0, #1
+  0x08002AAE:  4350         MULS       R0, R2, R0
+  0x08002AB0:  F003 FAE9    BL         __aeabi_uidiv            ; 0x08006086
+  0x08002AB4:  6378         STR        R0, [R7, #52]
+  0x08002AB6:  489F         LDR        R0, =voltageUin          ; [PC, #0x027C] [0x08002D34] =0x20000688 
+  0x08002AB8:  6800         LDR        R0, [R0]
+  0x08002ABA:  21CC         MOVS       R1, #204
+  0x08002ABC:  4BA9         LDR        R3, =sys_data            ; [PC, #0x02A4] [0x08002D64] =0x20000234 
+  0x08002ABE:  5258         STRH       R0, [R3, R1]
+  0x08002AC0:  489D         LDR        R0, =voltageUout         ; [PC, #0x0274] [0x08002D38] =0x20000684 
+  0x08002AC2:  6800         LDR        R0, [R0]
+  0x08002AC4:  22CE         MOVS       R2, #206
+  0x08002AC6:  5298         STRH       R0, [R3, R2]
+  0x08002AC8:  5A58         LDRH       R0, [R3, R1]
+  0x08002ACA:  5A99         LDRH       R1, [R3, R2]
+  0x08002ACC:  1A40         SUBS       R0, R0, R1
+  0x08002ACE:  21D0         MOVS       R1, #208
+  0x08002AD0:  5258         STRH       R0, [R3, R1]
+  0x08002AD2:  48A6         LDR        R0, =frequency           ; [PC, #0x0298] [0x08002D6C] =0x200006E0 
+  0x08002AD4:  8800         LDRH       R0, [R0]
+  0x08002AD6:  0840         LSRS       R0, R0, #1
+  0x08002AD8:  991D         LDR        R1, [SP, #116]
+  0x08002ADA:  4348         MULS       R0, R1, R0
+  0x08002ADC:  21D4         MOVS       R1, #212
+  0x08002ADE:  5258         STRH       R0, [R3, R1]
+  0x08002AE0:  20D2         MOVS       R0, #210
+  0x08002AE2:  9923         LDR        R1, [SP, #140]
+  0x08002AE4:  5219         STRH       R1, [R3, R0]
+  0x08002AE6:  489B         LDR        R0, =msCounter           ; [PC, #0x026C] [0x08002D54] =0x200006C0 
+  0x08002AE8:  9921         LDR        R1, [SP, #132]
+  0x08002AEA:  6001         STR        R1, [R0]
+  0x08002AEC:  48A0         LDR        R0, =temp                ; [PC, #0x0280] [0x08002D70] =0x20000690 
+  0x08002AEE:  6004         STR        R4, [R0]
+  0x08002AF0:  4AA0         LDR        R2, =0x50000010          ; [PC, #0x0280] [0x08002D74] 
+  0x08002AF2:  6810         LDR        R0, [R2]
+  0x08002AF4:  4030         ANDS       R0, R6
+  0x08002AF6:  21D8         MOVS       R1, #216
+  0x08002AF8:  5258         STRH       R0, [R3, R1]
+  0x08002AFA:  6810         LDR        R0, [R2]
+  0x08002AFC:  0780         LSLS       R0, R0, #30
+  0x08002AFE:  0FC0         LSRS       R0, R0, #31
+  0x08002B00:  21D6         MOVS       R1, #214
+  0x08002B02:  5258         STRH       R0, [R3, R1]
+  0x08002B04:  4858         LDR        R0, =0x50000410          ; [PC, #0x0160] [0x08002C68] 
+  0x08002B06:  6800         LDR        R0, [R0]
+  0x08002B08:  0880         LSRS       R0, R0, #2
+  0x08002B0A:  4386         BICS       R6, R0
+  0x08002B0C:  20DA         MOVS       R0, #218
+  0x08002B0E:  521E         STRH       R6, [R3, R0]
+  0x08002B10:  488A         LDR        R0, =relaisState         ; [PC, #0x0228] [0x08002D3C] =0x20000730 
+  0x08002B12:  7800         LDRB       R0, [R0]
+  0x08002B14:  21DC         MOVS       R1, #220
+  0x08002B16:  5258         STRH       R0, [R3, R1]
+  0x08002B18:  485A         LDR        R0, =relais_temperature  ; [PC, #0x0168] [0x08002C84] =0x20000694 
+  0x08002B1A:  6800         LDR        R0, [R0]
+  0x08002B1C:  21CA         MOVS       R1, #202
+  0x08002B1E:  5258         STRH       R0, [R3, R1]
+  0x08002B20:  4F88         LDR        R7, =0x000003C7          ; [PC, #0x0220] [0x08002D44] 
+
.L156:
+  0x08002B22:  4895         LDR        R0, =mode                ; [PC, #0x0254] [0x08002D78] =0x20000739 
+  0x08002B24:  7800         LDRB       R0, [R0]
+  0x08002B26:  2807         CMP        R0, #7
+  0x08002B28:  D900         BLS        .L157                    ; 0x08002B2C
+  0x08002B2A:  E15D         B          .L166                    ; 0x08002DE8
+
.L157:
+  0x08002B2C:  463C         MOV        R4, R7
+  0x08002B2E:  46C0         NOP
+  0x08002B30:  4478         ADD        R0, PC
+  0x08002B32:  7900         LDRB       R0, [R0, #4]
+  0x08002B34:  0040         LSLS       R0, R0, #1
+  0x08002B36:  4487         ADD        PC, R0
+  0x08002B38:  03           DC.B       0x03                     ; '\x03'
+  0x08002B39:  82           DC.B       0x82                     ; '\x82'
+  0x08002B3A:  3C           DC.B       0x3C                     ; '<'
+  0x08002B3B:  41           DC.B       0x41                     ; 'A'
+  0x08002B3C:  37           DC.B       0x37                     ; '7'
+  0x08002B3D:  87           DC.B       0x87                     ; '\x87'
+  0x08002B3E:  D9           DC.B       0xD9                     ; '\xD9'
+  0x08002B3F:  46           DC.B       0x46                     ; 'F'
+  0x08002B40:  4C8E         LDR        R4, =smState.137         ; [PC, #0x0238] [0x08002D7C] =0x20000735 
+  0x08002B42:  7820         LDRB       R0, [R4]
+  0x08002B44:  0040         LSLS       R0, R0, #1
+  0x08002B46:  46C0         NOP
+  0x08002B48:  4478         ADD        R0, PC
+  0x08002B4A:  8880         LDRH       R0, [R0, #4]
+  0x08002B4C:  0040         LSLS       R0, R0, #1
+  0x08002B4E:  4487         ADD        PC, R0
+  0x08002B50:  07           DC.B       0x07                     ; '\x07'
+  0x08002B51:  00           DC.B       0x00                     ; '\0'
+  0x08002B52:  B7           DC.B       0xB7                     ; '\xB7'
+  0x08002B53:  03           DC.B       0x03                     ; '\x03'
+  0x08002B54:  81           DC.B       0x81                     ; '\x81'
+  0x08002B55:  01           DC.B       0x01                     ; '\x01'
+  0x08002B56:  C7           DC.B       0xC7                     ; '\xC7'
+  0x08002B57:  01           DC.B       0x01                     ; '\x01'
+  0x08002B58:  080063EB     DC.W       080063EB               ; R_ARM_ABS32
+  0x08002B5C:  200006C8     DC.W       longPressCounterButtonOff
+  0x08002B60:  4841         LDR        R0, =0x50000410          ; [PC, #0x0104] [0x08002C68] 
+  0x08002B62:  6801         LDR        R1, [R0]
+  0x08002B64:  4A3C         LDR        R2, =buttonState         ; [PC, #240] [0x08002C58] =0x2000073A 
+  0x08002B66:  7810         LDRB       R0, [R2]
+  0x08002B68:  2801         CMP        R0, #1
+  0x08002B6A:  D001         BEQ        .L158                    ; 0x08002B70
+  0x08002B6C:  F001 F988    BL         .L236                    ; 0x08003E80
+
.L158:
+  0x08002B70:  0748         LSLS       R0, R1, #29
+  0x08002B72:  D501         BPL        .L159                    ; 0x08002B78
+  0x08002B74:  F001 F961    BL         .L234                    ; 0x08003E3A
+
.L159:
+  0x08002B78:  483B         LDR        R0, =0x50000410          ; [PC, #236] [0x08002C68] 
+  0x08002B7A:  9920         LDR        R1, [SP, #128]
+  0x08002B7C:  6081         STR        R1, [R0, #8]
+  0x08002B7E:  2000         MOVS       R0, #0
+  0x08002B80:  7010         STRB       R0, [R2]
+  0x08002B82:  486B         LDR        R0, =onTimeRT            ; [PC, #0x01AC] [0x08002D30] =0x2000073C 
+  0x08002B84:  7005         STRB       R5, [R0]
+  0x08002B86:  4867         LDR        R0, =offTimeRT           ; [PC, #0x019C] [0x08002D24] =0x20000748 
+  0x08002B88:  7005         STRB       R5, [R0]
+  0x08002B8A:  4865         LDR        R0, =blinkModeRT         ; [PC, #0x0194] [0x08002D20] =0x20000754 
+  0x08002B8C:  7005         STRB       R5, [R0]
+  0x08002B8E:  4866         LDR        R0, =numberOfBlinks      ; [PC, #0x0198] [0x08002D28] =0x200006BC 
+  0x08002B90:  2703         MOVS       R7, #3
+  0x08002B92:  6007         STR        R7, [R0]
+  0x08002B94:  4860         LDR        R0, =blinkCounter        ; [PC, #0x0180] [0x08002D18] =0x200006EC 
+  0x08002B96:  6007         STR        R7, [R0]
+  0x08002B98:  9A10         LDR        R2, [SP, #64]
+  0x08002B9A:  32F4         ADDS       R2, #244
+  0x08002B9C:  4878         LDR        R0, =0x08006910          ; [PC, #0x01E0] [0x08002D80] 
+  0x08002B9E:  495D         LDR        R1, =onTimeCounterRT     ; [PC, #0x0174] [0x08002D14] =0x2000069C 
+  0x08002BA0:  4B62         LDR        R3, =pauseTime           ; [PC, #0x0188] [0x08002D2C] =0x20000734 
+  0x08002BA2:  9E1E         LDR        R6, [SP, #120]
+  0x08002BA4:  F001 F95F    BL         .L235                    ; 0x08003E66
+  0x08002BA8:  2001         MOVS       R0, #1
+  0x08002BAA:  F002 F8AF    BL         MODE_SECONDARYPROTECTION_PLUS_Exec ; 0x08004D0C
+  0x08002BAE:  F001 FAB1    BL         .L252                    ; 0x08004114
+  0x08002BB2:  2000         MOVS       R0, #0
+  0x08002BB4:  F002 F8AA    BL         MODE_SECONDARYPROTECTION_PLUS_Exec ; 0x08004D0C
+  0x08002BB8:  F001 FAAC    BL         .L252                    ; 0x08004114
+  0x08002BBC:  2001         MOVS       R0, #1
+  0x08002BBE:  F001 FD67    BL         MODE_SECONDARYPROTECTION_Exec ; 0x08004690
+  0x08002BC2:  F001 FAA7    BL         .L252                    ; 0x08004114
+  0x08002BC6:  486F         LDR        R0, =smState.145         ; [PC, #0x01BC] [0x08002D84] =0x20000733 
+  0x08002BC8:  7800         LDRB       R0, [R0]
+  0x08002BCA:  0040         LSLS       R0, R0, #1
+  0x08002BCC:  4478         ADD        R0, PC
+  0x08002BCE:  8880         LDRH       R0, [R0, #4]
+  0x08002BD0:  0040         LSLS       R0, R0, #1
+  0x08002BD2:  4487         ADD        PC, R0
+  0x08002BD4:  11           DC.B       0x11                     ; '\x11'
+  0x08002BD5:  00           DC.B       0x00                     ; '\0'
+  0x08002BD6:  29           DC.B       0x29                     ; ')'
+  0x08002BD7:  02           DC.B       0x02                     ; '\x02'
+  0x08002BD8:  0E           DC.B       0x0E                     ; '\x0E'
+  0x08002BD9:  01           DC.B       0x01                     ; '\x01'
+  0x08002BDA:  6F           DC.B       0x6F                     ; 'o'
+  0x08002BDB:  01           DC.B       0x01                     ; '\x01'
+  0x08002BDC:  2000073A     DC.W       buttonState
+  0x08002BE0:  080065AD     DC.W       080065AD               ; R_ARM_ABS32
+  0x08002BE4:  200006A8     DC.W       onTimeCounter
+  0x08002BE8:  50000410     DC.W       0x50000410
+  0x08002BEC:  2000075C     DC.W       alarmMode
+  0x08002BF0:  20000750     DC.W       offTime
+  0x08002BF4:  00001388     DC.W       0x00001388
+  0x08002BF8:  481B         LDR        R0, =0x50000410          ; [PC, #108] [0x08002C68] 
+  0x08002BFA:  6801         LDR        R1, [R0]
+  0x08002BFC:  4C16         LDR        R4, =buttonState         ; [PC, #88] [0x08002C58] =0x2000073A 
+  0x08002BFE:  7820         LDRB       R0, [R4]
+  0x08002C00:  2801         CMP        R0, #1
+  0x08002C02:  D001         BEQ        .L160                    ; 0x08002C08
+  0x08002C04:  F001 F8E1    BL         .L231                    ; 0x08003DCA
+
.L160:
+  0x08002C08:  0748         LSLS       R0, R1, #29
+  0x08002C0A:  D501         BPL        .L161                    ; 0x08002C10
+  0x08002C0C:  F001 F8BA    BL         .L229                    ; 0x08003D84
+
.L161:
+  0x08002C10:  4815         LDR        R0, =0x50000410          ; [PC, #84] [0x08002C68] 
+  0x08002C12:  9920         LDR        R1, [SP, #128]
+  0x08002C14:  6081         STR        R1, [R0, #8]
+  0x08002C16:  2000         MOVS       R0, #0
+  0x08002C18:  7020         STRB       R0, [R4]
+  0x08002C1A:  4845         LDR        R0, =onTimeRT            ; [PC, #0x0114] [0x08002D30] =0x2000073C 
+  0x08002C1C:  7005         STRB       R5, [R0]
+  0x08002C1E:  4841         LDR        R0, =offTimeRT           ; [PC, #0x0104] [0x08002D24] =0x20000748 
+  0x08002C20:  7005         STRB       R5, [R0]
+  0x08002C22:  483F         LDR        R0, =blinkModeRT         ; [PC, #252] [0x08002D20] =0x20000754 
+  0x08002C24:  7005         STRB       R5, [R0]
+  0x08002C26:  4840         LDR        R0, =numberOfBlinks      ; [PC, #0x0100] [0x08002D28] =0x200006BC 
+  0x08002C28:  9F15         LDR        R7, [SP, #84]
+  0x08002C2A:  6007         STR        R7, [R0]
+  0x08002C2C:  483A         LDR        R0, =blinkCounter        ; [PC, #232] [0x08002D18] =0x200006EC 
+  0x08002C2E:  6007         STR        R7, [R0]
+  0x08002C30:  4855         LDR        R0, =0x08006703          ; [PC, #0x0154] [0x08002D88] 
+  0x08002C32:  4938         LDR        R1, =onTimeCounterRT     ; [PC, #224] [0x08002D14] =0x2000069C 
+  0x08002C34:  4B3D         LDR        R3, =pauseTime           ; [PC, #244] [0x08002D2C] =0x20000734 
+  0x08002C36:  9A09         LDR        R2, [SP, #36]
+  0x08002C38:  9E1E         LDR        R6, [SP, #120]
+  0x08002C3A:  F001 F8B9    BL         .L230                    ; 0x08003DB0
+  0x08002C3E:  2000         MOVS       R0, #0
+  0x08002C40:  F001 FD26    BL         MODE_SECONDARYPROTECTION_Exec ; 0x08004690
+  0x08002C44:  F001 FA66    BL         .L252                    ; 0x08004114
+  0x08002C48:  4850         LDR        R0, =smState.122         ; [PC, #0x0140] [0x08002D8C] =0x20000736 
+  0x08002C4A:  7800         LDRB       R0, [R0]
+  0x08002C4C:  A104         ADR        R1, 0x08002C60
+  0x08002C4E:  0040         LSLS       R0, R0, #1
+  0x08002C50:  5A08         LDRH       R0, [R1, R0]
+  0x08002C52:  0040         LSLS       R0, R0, #1
+  0x08002C54:  4487         ADD        PC, R0
+  0x08002C56:  46C0         NOP
+  0x08002C58:  2000073A     DC.W       buttonState
+  0x08002C5C:  200006B8     DC.W       offTimeCounter
+  0x08002C60:  26           DC.B       0x26                     ; '&'
+  0x08002C61:  00           DC.B       0x00                     ; '\0'
+  0x08002C62:  D5           DC.B       0xD5                     ; '\xD5'
+  0x08002C63:  04           DC.B       0x04                     ; '\x04'
+  0x08002C64:  03           DC.B       0x03                     ; '\x03'
+  0x08002C65:  03           DC.B       0x03                     ; '\x03'
+  0x08002C66:  57           DC.B       0x57                     ; 'W'
+  0x08002C67:  04           DC.B       0x04                     ; '\x04'
+  0x08002C68:  50000410     DC.W       0x50000410
+  0x08002C6C:  00001388     DC.W       0x00001388
+  0x08002C70:  20000744     DC.W       onTime
+  0x08002C74:  20000660     DC.W       adcData
+  0x08002C78:  00000CE4     DC.W       0x00000CE4
+  0x08002C7C:  00010063     DC.W       0x00010063
+  0x08002C80:  FFFFFCFF     DC.W       0xFFFFFCFF
+  0x08002C84:  20000694     DC.W       relais_temperature
+  0x08002C88:  20000698     DC.W       onTimeCounterSET
+  0x08002C8C:  200006A0     DC.W       onTimeCounterRESET
+  0x08002C90:  200006A4     DC.W       onTimeCounterGN
+  0x08002C94:  50000818     DC.W       0x50000818
+  0x08002C98:  20000758     DC.W       blinkModeGN
+  0x08002C9C:  2000074C     DC.W       offTimeGN
+  0x08002CA0:  200006B4     DC.W       offTimeCounterGN
+  0x08002CA4:  483A         LDR        R0, =0x50000410          ; [PC, #232] [0x08002D90] 
+  0x08002CA6:  6801         LDR        R1, [R0]
+  0x08002CA8:  4C3A         LDR        R4, =buttonState         ; [PC, #232] [0x08002D94] =0x2000073A 
+  0x08002CAA:  7820         LDRB       R0, [R4]
+  0x08002CAC:  2801         CMP        R0, #1
+  0x08002CAE:  D001         BEQ        .L162                    ; 0x08002CB4
+  0x08002CB0:  F001 F99E    BL         .L244                    ; 0x08003FF0
+
.L162:
+  0x08002CB4:  0748         LSLS       R0, R1, #29
+  0x08002CB6:  D501         BPL        .L163                    ; 0x08002CBC
+  0x08002CB8:  F001 F977    BL         .L242                    ; 0x08003FAA
+
.L163:
+  0x08002CBC:  4834         LDR        R0, =0x50000410          ; [PC, #208] [0x08002D90] 
+  0x08002CBE:  9920         LDR        R1, [SP, #128]
+  0x08002CC0:  6081         STR        R1, [R0, #8]
+  0x08002CC2:  2000         MOVS       R0, #0
+  0x08002CC4:  7020         STRB       R0, [R4]
+  0x08002CC6:  481A         LDR        R0, =onTimeRT            ; [PC, #104] [0x08002D30] =0x2000073C 
+  0x08002CC8:  7005         STRB       R5, [R0]
+  0x08002CCA:  4816         LDR        R0, =offTimeRT           ; [PC, #88] [0x08002D24] =0x20000748 
+  0x08002CCC:  7005         STRB       R5, [R0]
+  0x08002CCE:  4814         LDR        R0, =blinkModeRT         ; [PC, #80] [0x08002D20] =0x20000754 
+  0x08002CD0:  7005         STRB       R5, [R0]
+  0x08002CD2:  4815         LDR        R0, =numberOfBlinks      ; [PC, #84] [0x08002D28] =0x200006BC 
+  0x08002CD4:  2703         MOVS       R7, #3
+  0x08002CD6:  6007         STR        R7, [R0]
+  0x08002CD8:  480F         LDR        R0, =blinkCounter        ; [PC, #60] [0x08002D18] =0x200006EC 
+  0x08002CDA:  6007         STR        R7, [R0]
+  0x08002CDC:  9A10         LDR        R2, [SP, #64]
+  0x08002CDE:  32F4         ADDS       R2, #244
+  0x08002CE0:  482D         LDR        R0, =0x0800667F          ; [PC, #180] [0x08002D98] 
+  0x08002CE2:  490C         LDR        R1, =onTimeCounterRT     ; [PC, #48] [0x08002D14] =0x2000069C 
+  0x08002CE4:  4B11         LDR        R3, =pauseTime           ; [PC, #68] [0x08002D2C] =0x20000734 
+  0x08002CE6:  9E1E         LDR        R6, [SP, #120]
+  0x08002CE8:  F001 F975    BL         .L243                    ; 0x08003FD6
+  0x08002CEC:  482B         LDR        R0, =smState             ; [PC, #172] [0x08002D9C] =0x20000737 
+  0x08002CEE:  7800         LDRB       R0, [R0]
+  0x08002CF0:  A105         ADR        R1, 0x08002D08
+  0x08002CF2:  0040         LSLS       R0, R0, #1
+  0x08002CF4:  5A08         LDRH       R0, [R1, R0]
+  0x08002CF6:  0040         LSLS       R0, R0, #1
+  0x08002CF8:  4487         ADD        PC, R0
+  0x08002CFA:  46C0         NOP
+  0x08002CFC:  200006B4     DC.W       offTimeCounterGN
+  0x08002D00:  20000740     DC.W       onTimeGN
+  0x08002D04:  2000069C     DC.W       onTimeCounterRT
+  0x08002D08:  52           DC.B       0x52                     ; 'R'
+  0x08002D09:  00           DC.B       0x00                     ; '\0'
+  0x08002D0A:  0C           DC.B       0x0C                     ; '\x0C'
+  0x08002D0B:  06           DC.B       0x06                     ; '\x06'
+  0x08002D0C:  D4           DC.B       0xD4                     ; '\xD4'
+  0x08002D0D:  03           DC.B       0x03                     ; '\x03'
+  0x08002D0E:  6C           DC.B       0x6C                     ; 'l'
+  0x08002D0F:  04           DC.B       0x04                     ; '\x04'
+  0x08002D10:  50000818     DC.W       0x50000818
+  0x08002D14:  2000069C     DC.W       onTimeCounterRT
+  0x08002D18:  200006EC     DC.W       blinkCounter
+  0x08002D1C:  200006B0     DC.W       offTimeCounterRT
+  0x08002D20:  20000754     DC.W       blinkModeRT
+  0x08002D24:  20000748     DC.W       offTimeRT
+  0x08002D28:  200006BC     DC.W       numberOfBlinks
+  0x08002D2C:  20000734     DC.W       pauseTime
+  0x08002D30:  2000073C     DC.W       onTimeRT
+  0x08002D34:  20000688     DC.W       voltageUin
+  0x08002D38:  20000684     DC.W       voltageUout
+  0x08002D3C:  20000730     DC.W       relaisState
+  0x08002D40:  200006E4     DC.W       dropLimitCounter
+  0x08002D44:  000003C7     DC.W       0x000003C7
+  0x08002D48:  0800635B     DC.W       0800635B               ; R_ARM_ABS32
+  0x08002D4C:  2000068C     DC.W       uwTick
+  0x08002D50:  200006AC     DC.W       oldTimeMSTick
+  0x08002D54:  200006C0     DC.W       msCounter
+  0x08002D58:  200006E8     DC.W       calTemperatureSensor30Value
+  0x08002D5C:  A3D70A3D     DC.W       0xA3D70A3D
+  0x08002D60:  40043D70     DC.W       0x40043D70
+  0x08002D64:  20000234     DC.W       sys_data
+  0x08002D68:  200005C8     DC.W       htim17
+  0x08002D6C:  200006E0     DC.W       frequency
+  0x08002D70:  20000690     DC.W       temp
+  0x08002D74:  50000010     DC.W       0x50000010
+  0x08002D78:  20000739     DC.W       mode
+  0x08002D7C:  20000735     DC.W       smState.137
+  0x08002D80:  08006910     DC.W       08006910               ; R_ARM_ABS32
+  0x08002D84:  20000733     DC.W       smState.145
+  0x08002D88:  08006703     DC.W       08006703               ; R_ARM_ABS32
+  0x08002D8C:  20000736     DC.W       smState.122
+  0x08002D90:  50000410     DC.W       0x50000410
+  0x08002D94:  2000073A     DC.W       buttonState
+  0x08002D98:  0800667F     DC.W       0800667F               ; R_ARM_ABS32
+  0x08002D9C:  20000737     DC.W       smState
+  0x08002DA0:  4883         LDR        R0, =0x50000410          ; [PC, #0x020C] [0x08002FB0] 
+  0x08002DA2:  6801         LDR        R1, [R0]
+  0x08002DA4:  4C83         LDR        R4, =buttonState         ; [PC, #0x020C] [0x08002FB4] =0x2000073A 
+  0x08002DA6:  7820         LDRB       R0, [R4]
+  0x08002DA8:  2801         CMP        R0, #1
+  0x08002DAA:  D001         BEQ        .L164                    ; 0x08002DB0
+  0x08002DAC:  F001 F97B    BL         .L249                    ; 0x080040A6
+
.L164:
+  0x08002DB0:  0748         LSLS       R0, R1, #29
+  0x08002DB2:  D501         BPL        .L165                    ; 0x08002DB8
+  0x08002DB4:  F001 F954    BL         .L247                    ; 0x08004060
+
.L165:
+  0x08002DB8:  487D         LDR        R0, =0x50000410          ; [PC, #0x01F4] [0x08002FB0] 
+  0x08002DBA:  9920         LDR        R1, [SP, #128]
+  0x08002DBC:  6081         STR        R1, [R0, #8]
+  0x08002DBE:  2000         MOVS       R0, #0
+  0x08002DC0:  7020         STRB       R0, [R4]
+  0x08002DC2:  487D         LDR        R0, =onTimeRT            ; [PC, #0x01F4] [0x08002FB8] =0x2000073C 
+  0x08002DC4:  7005         STRB       R5, [R0]
+  0x08002DC6:  487D         LDR        R0, =offTimeRT           ; [PC, #0x01F4] [0x08002FBC] =0x20000748 
+  0x08002DC8:  7005         STRB       R5, [R0]
+  0x08002DCA:  487D         LDR        R0, =blinkModeRT         ; [PC, #0x01F4] [0x08002FC0] =0x20000754 
+  0x08002DCC:  7005         STRB       R5, [R0]
+  0x08002DCE:  487D         LDR        R0, =numberOfBlinks      ; [PC, #0x01F4] [0x08002FC4] =0x200006BC 
+  0x08002DD0:  2703         MOVS       R7, #3
+  0x08002DD2:  6007         STR        R7, [R0]
+  0x08002DD4:  487C         LDR        R0, =blinkCounter        ; [PC, #0x01F0] [0x08002FC8] =0x200006EC 
+  0x08002DD6:  6007         STR        R7, [R0]
+  0x08002DD8:  9A10         LDR        R2, [SP, #64]
+  0x08002DDA:  32F4         ADDS       R2, #244
+  0x08002DDC:  487B         LDR        R0, =0x0800661B          ; [PC, #0x01EC] [0x08002FCC] 
+  0x08002DDE:  497C         LDR        R1, =onTimeCounterRT     ; [PC, #0x01F0] [0x08002FD0] =0x2000069C 
+  0x08002DE0:  4B7C         LDR        R3, =pauseTime           ; [PC, #0x01F0] [0x08002FD4] =0x20000734 
+  0x08002DE2:  9E1E         LDR        R6, [SP, #120]
+  0x08002DE4:  F001 F952    BL         .L248                    ; 0x0800408C
+
.L166:
+  0x08002DE8:  487B         LDR        R0, =0x080065BE          ; [PC, #0x01EC] [0x08002FD8] 
+  0x08002DEA:  F002 FA03    BL         puts                     ; 0x080051F4
+  0x08002DEE:  F001 F991    BL         .L252                    ; 0x08004114
+  0x08002DF2:  4870         LDR        R0, =buttonState         ; [PC, #0x01C0] [0x08002FB4] =0x2000073A 
+  0x08002DF4:  7800         LDRB       R0, [R0]
+  0x08002DF6:  2800         CMP        R0, #0
+  0x08002DF8:  D001         BEQ        .L167                    ; 0x08002DFE
+  0x08002DFA:  F001 F98B    BL         .L252                    ; 0x08004114
+
.L167:
+  0x08002DFE:  496C         LDR        R1, =0x50000410          ; [PC, #0x01B0] [0x08002FB0] 
+  0x08002E00:  981B         LDR        R0, [SP, #108]
+  0x08002E02:  6188         STR        R0, [R1, #24]
+  0x08002E04:  981A         LDR        R0, [SP, #104]
+  0x08002E06:  6088         STR        R0, [R1, #8]
+  0x08002E08:  4874         LDR        R0, =relaisState         ; [PC, #0x01D0] [0x08002FDC] =0x20000730 
+  0x08002E0A:  2600         MOVS       R6, #0
+  0x08002E0C:  7006         STRB       R6, [R0]
+  0x08002E0E:  4874         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01D0] [0x08002FE0] =0x200006A0 
+  0x08002E10:  9A16         LDR        R2, [SP, #88]
+  0x08002E12:  6002         STR        R2, [R0]
+  0x08002E14:  9820         LDR        R0, [SP, #128]
+  0x08002E16:  6188         STR        R0, [R1, #24]
+  0x08002E18:  4872         LDR        R0, =offTimeCounter      ; [PC, #0x01C8] [0x08002FE4] =0x200006B8 
+  0x08002E1A:  6006         STR        R6, [R0]
+  0x08002E1C:  4872         LDR        R0, =alarmMode           ; [PC, #0x01C8] [0x08002FE8] =0x2000075C 
+  0x08002E1E:  7006         STRB       R6, [R0]
+  0x08002E20:  4872         LDR        R0, =onTimeCounter       ; [PC, #0x01C8] [0x08002FEC] =0x200006A8 
+  0x08002E22:  6006         STR        R6, [R0]
+  0x08002E24:  4972         LDR        R1, =0x50000818          ; [PC, #0x01C8] [0x08002FF0] 
+  0x08002E26:  981F         LDR        R0, [SP, #124]
+  0x08002E28:  6108         STR        R0, [R1, #16]
+  0x08002E2A:  4872         LDR        R0, =offTimeCounterGN    ; [PC, #0x01C8] [0x08002FF4] =0x200006B4 
+  0x08002E2C:  6006         STR        R6, [R0]
+  0x08002E2E:  4872         LDR        R0, =blinkModeGN         ; [PC, #0x01C8] [0x08002FF8] =0x20000758 
+  0x08002E30:  7006         STRB       R6, [R0]
+  0x08002E32:  4872         LDR        R0, =onTimeCounterGN     ; [PC, #0x01C8] [0x08002FFC] =0x200006A4 
+  0x08002E34:  6006         STR        R6, [R0]
+  0x08002E36:  981E         LDR        R0, [SP, #120]
+  0x08002E38:  6108         STR        R0, [R1, #16]
+  0x08002E3A:  4871         LDR        R0, =offTimeCounterRT    ; [PC, #0x01C4] [0x08003000] =0x200006B0 
+  0x08002E3C:  6006         STR        R6, [R0]
+  0x08002E3E:  4860         LDR        R0, =blinkModeRT         ; [PC, #0x0180] [0x08002FC0] =0x20000754 
+  0x08002E40:  7006         STRB       R6, [R0]
+  0x08002E42:  4863         LDR        R0, =onTimeCounterRT     ; [PC, #0x018C] [0x08002FD0] =0x2000069C 
+  0x08002E44:  6006         STR        R6, [R0]
+  0x08002E46:  486F         LDR        R0, =0x080062FA          ; [PC, #0x01BC] [0x08003004] 
+  0x08002E48:  F002 F9D4    BL         puts                     ; 0x080051F4
+  0x08002E4C:  486E         LDR        R0, =smState.145         ; [PC, #0x01B8] [0x08003008] =0x20000733 
+  0x08002E4E:  7006         STRB       R6, [R0]
+  0x08002E50:  F001 F960    BL         .L252                    ; 0x08004114
+  0x08002E54:  4857         LDR        R0, =buttonState         ; [PC, #0x015C] [0x08002FB4] =0x2000073A 
+  0x08002E56:  7800         LDRB       R0, [R0]
+  0x08002E58:  2800         CMP        R0, #0
+  0x08002E5A:  D001         BEQ        .L168                    ; 0x08002E60
+  0x08002E5C:  F001 F95A    BL         .L252                    ; 0x08004114
+
.L168:
+  0x08002E60:  4953         LDR        R1, =0x50000410          ; [PC, #0x014C] [0x08002FB0] 
+  0x08002E62:  981B         LDR        R0, [SP, #108]
+  0x08002E64:  6188         STR        R0, [R1, #24]
+  0x08002E66:  981A         LDR        R0, [SP, #104]
+  0x08002E68:  6088         STR        R0, [R1, #8]
+  0x08002E6A:  485C         LDR        R0, =relaisState         ; [PC, #0x0170] [0x08002FDC] =0x20000730 
+  0x08002E6C:  2600         MOVS       R6, #0
+  0x08002E6E:  7006         STRB       R6, [R0]
+  0x08002E70:  485B         LDR        R0, =onTimeCounterRESET  ; [PC, #0x016C] [0x08002FE0] =0x200006A0 
+  0x08002E72:  9A16         LDR        R2, [SP, #88]
+  0x08002E74:  6002         STR        R2, [R0]
+  0x08002E76:  9820         LDR        R0, [SP, #128]
+  0x08002E78:  6188         STR        R0, [R1, #24]
+  0x08002E7A:  485A         LDR        R0, =offTimeCounter      ; [PC, #0x0168] [0x08002FE4] =0x200006B8 
+  0x08002E7C:  6006         STR        R6, [R0]
+  0x08002E7E:  485A         LDR        R0, =alarmMode           ; [PC, #0x0168] [0x08002FE8] =0x2000075C 
+  0x08002E80:  7006         STRB       R6, [R0]
+  0x08002E82:  485A         LDR        R0, =onTimeCounter       ; [PC, #0x0168] [0x08002FEC] =0x200006A8 
+  0x08002E84:  6006         STR        R6, [R0]
+  0x08002E86:  495A         LDR        R1, =0x50000818          ; [PC, #0x0168] [0x08002FF0] 
+  0x08002E88:  981F         LDR        R0, [SP, #124]
+  0x08002E8A:  6108         STR        R0, [R1, #16]
+  0x08002E8C:  4859         LDR        R0, =offTimeCounterGN    ; [PC, #0x0164] [0x08002FF4] =0x200006B4 
+  0x08002E8E:  6006         STR        R6, [R0]
+  0x08002E90:  4859         LDR        R0, =blinkModeGN         ; [PC, #0x0164] [0x08002FF8] =0x20000758 
+  0x08002E92:  7006         STRB       R6, [R0]
+  0x08002E94:  4859         LDR        R0, =onTimeCounterGN     ; [PC, #0x0164] [0x08002FFC] =0x200006A4 
+  0x08002E96:  6006         STR        R6, [R0]
+  0x08002E98:  981E         LDR        R0, [SP, #120]
+  0x08002E9A:  6108         STR        R0, [R1, #16]
+  0x08002E9C:  4858         LDR        R0, =offTimeCounterRT    ; [PC, #0x0160] [0x08003000] =0x200006B0 
+  0x08002E9E:  6006         STR        R6, [R0]
+  0x08002EA0:  4847         LDR        R0, =blinkModeRT         ; [PC, #0x011C] [0x08002FC0] =0x20000754 
+  0x08002EA2:  7006         STRB       R6, [R0]
+  0x08002EA4:  484A         LDR        R0, =onTimeCounterRT     ; [PC, #0x0128] [0x08002FD0] =0x2000069C 
+  0x08002EA6:  6006         STR        R6, [R0]
+  0x08002EA8:  4858         LDR        R0, =0x080064DD          ; [PC, #0x0160] [0x0800300C] 
+  0x08002EAA:  F002 F9A3    BL         puts                     ; 0x080051F4
+  0x08002EAE:  7026         STRB       R6, [R4]
+  0x08002EB0:  F001 F930    BL         .L252                    ; 0x08004114
+  0x08002EB4:  483E         LDR        R0, =0x50000410          ; [PC, #248] [0x08002FB0] 
+  0x08002EB6:  6801         LDR        R1, [R0]
+  0x08002EB8:  4E3E         LDR        R6, =buttonState         ; [PC, #248] [0x08002FB4] =0x2000073A 
+  0x08002EBA:  7830         LDRB       R0, [R6]
+  0x08002EBC:  2801         CMP        R0, #1
+  0x08002EBE:  D001         BEQ        .L169                    ; 0x08002EC4
+  0x08002EC0:  F000 FED0    BL         .L227                    ; 0x08003C64
+
.L169:
+  0x08002EC4:  0748         LSLS       R0, R1, #29
+  0x08002EC6:  D501         BPL        .L170                    ; 0x08002ECC
+  0x08002EC8:  F000 FEA3    BL         .L226                    ; 0x08003C12
+
.L170:
+  0x08002ECC:  4838         LDR        R0, =0x50000410          ; [PC, #224] [0x08002FB0] 
+  0x08002ECE:  9920         LDR        R1, [SP, #128]
+  0x08002ED0:  6081         STR        R1, [R0, #8]
+  0x08002ED2:  2000         MOVS       R0, #0
+  0x08002ED4:  7030         STRB       R0, [R6]
+  0x08002ED6:  4845         LDR        R0, =onTimeCounter       ; [PC, #0x0114] [0x08002FEC] =0x200006A8 
+  0x08002ED8:  9909         LDR        R1, [SP, #36]
+  0x08002EDA:  6001         STR        R1, [R0]
+  0x08002EDC:  F001 F91A    BL         .L252                    ; 0x08004114
+  0x08002EE0:  4833         LDR        R0, =0x50000410          ; [PC, #204] [0x08002FB0] 
+  0x08002EE2:  6801         LDR        R1, [R0]
+  0x08002EE4:  4E33         LDR        R6, =buttonState         ; [PC, #204] [0x08002FB4] =0x2000073A 
+  0x08002EE6:  7830         LDRB       R0, [R6]
+  0x08002EE8:  2801         CMP        R0, #1
+  0x08002EEA:  D12A         BNE        .L172                    ; 0x08002F42
+  0x08002EEC:  0748         LSLS       R0, R1, #29
+  0x08002EEE:  D400         BMI        .L171                    ; 0x08002EF2
+  0x08002EF0:  E37C         B          .L192                    ; 0x080035EC
+
.L171:
+  0x08002EF2:  492F         LDR        R1, =0x50000410          ; [PC, #188] [0x08002FB0] 
+  0x08002EF4:  981A         LDR        R0, [SP, #104]
+  0x08002EF6:  6188         STR        R0, [R1, #24]
+  0x08002EF8:  981B         LDR        R0, [SP, #108]
+  0x08002EFA:  6088         STR        R0, [R1, #8]
+  0x08002EFC:  4837         LDR        R0, =relaisState         ; [PC, #220] [0x08002FDC] =0x20000730 
+  0x08002EFE:  7005         STRB       R5, [R0]
+  0x08002F00:  4843         LDR        R0, =onTimeCounterSET    ; [PC, #0x010C] [0x08003010] =0x20000698 
+  0x08002F02:  9A16         LDR        R2, [SP, #88]
+  0x08002F04:  6002         STR        R2, [R0]
+  0x08002F06:  9820         LDR        R0, [SP, #128]
+  0x08002F08:  6088         STR        R0, [R1, #8]
+  0x08002F0A:  4842         LDR        R0, =onTimeGN            ; [PC, #0x0108] [0x08003014] =0x20000740 
+  0x08002F0C:  7005         STRB       R5, [R0]
+  0x08002F0E:  4837         LDR        R0, =onTimeCounter       ; [PC, #220] [0x08002FEC] =0x200006A8 
+  0x08002F10:  21C8         MOVS       R1, #200
+  0x08002F12:  6001         STR        R1, [R0]
+  0x08002F14:  4840         LDR        R0, =offTimeGN           ; [PC, #0x0100] [0x08003018] =0x2000074C 
+  0x08002F16:  7005         STRB       R5, [R0]
+  0x08002F18:  4837         LDR        R0, =blinkModeGN         ; [PC, #220] [0x08002FF8] =0x20000758 
+  0x08002F1A:  7005         STRB       R5, [R0]
+  0x08002F1C:  4A34         LDR        R2, =0x50000818          ; [PC, #208] [0x08002FF0] 
+  0x08002F1E:  981F         LDR        R0, [SP, #124]
+  0x08002F20:  6010         STR        R0, [R2]
+  0x08002F22:  4836         LDR        R0, =onTimeCounterGN     ; [PC, #216] [0x08002FFC] =0x200006A4 
+  0x08002F24:  6001         STR        R1, [R0]
+  0x08002F26:  981E         LDR        R0, [SP, #120]
+  0x08002F28:  6110         STR        R0, [R2, #16]
+  0x08002F2A:  4835         LDR        R0, =offTimeCounterRT    ; [PC, #212] [0x08003000] =0x200006B0 
+  0x08002F2C:  2100         MOVS       R1, #0
+  0x08002F2E:  6001         STR        R1, [R0]
+  0x08002F30:  4823         LDR        R0, =blinkModeRT         ; [PC, #140] [0x08002FC0] =0x20000754 
+  0x08002F32:  7001         STRB       R1, [R0]
+  0x08002F34:  4826         LDR        R0, =onTimeCounterRT     ; [PC, #152] [0x08002FD0] =0x2000069C 
+  0x08002F36:  6001         STR        R1, [R0]
+  0x08002F38:  4838         LDR        R0, =0x080066EA          ; [PC, #224] [0x0800301C] 
+  0x08002F3A:  F002 F95B    BL         puts                     ; 0x080051F4
+  0x08002F3E:  7025         STRB       R5, [R4]
+  0x08002F40:  7830         LDRB       R0, [R6]
+
.L172:
+  0x08002F42:  2802         CMP        R0, #2
+  0x08002F44:  D001         BEQ        .L173                    ; 0x08002F4A
+  0x08002F46:  F001 F8E5    BL         .L252                    ; 0x08004114
+
.L173:
+  0x08002F4A:  4919         LDR        R1, =0x50000410          ; [PC, #100] [0x08002FB0] 
+  0x08002F4C:  981A         LDR        R0, [SP, #104]
+  0x08002F4E:  6188         STR        R0, [R1, #24]
+  0x08002F50:  981B         LDR        R0, [SP, #108]
+  0x08002F52:  6088         STR        R0, [R1, #8]
+  0x08002F54:  4821         LDR        R0, =relaisState         ; [PC, #132] [0x08002FDC] =0x20000730 
+  0x08002F56:  7005         STRB       R5, [R0]
+  0x08002F58:  482D         LDR        R0, =onTimeCounterSET    ; [PC, #180] [0x08003010] =0x20000698 
+  0x08002F5A:  9A16         LDR        R2, [SP, #88]
+  0x08002F5C:  6002         STR        R2, [R0]
+  0x08002F5E:  4830         LDR        R0, =onTime              ; [PC, #192] [0x08003020] =0x20000744 
+  0x08002F60:  7005         STRB       R5, [R0]
+  0x08002F62:  4830         LDR        R0, =offTime             ; [PC, #192] [0x08003024] =0x20000750 
+  0x08002F64:  7005         STRB       R5, [R0]
+  0x08002F66:  4820         LDR        R0, =alarmMode           ; [PC, #128] [0x08002FE8] =0x2000075C 
+  0x08002F68:  7005         STRB       R5, [R0]
+  0x08002F6A:  9820         LDR        R0, [SP, #128]
+  0x08002F6C:  6088         STR        R0, [R1, #8]
+  0x08002F6E:  491F         LDR        R1, =onTimeCounter       ; [PC, #124] [0x08002FEC] =0x200006A8 
+  0x08002F70:  20C8         MOVS       R0, #200
+  0x08002F72:  6008         STR        R0, [R1]
+  0x08002F74:  4B1E         LDR        R3, =0x50000818          ; [PC, #120] [0x08002FF0] 
+  0x08002F76:  991F         LDR        R1, [SP, #124]
+  0x08002F78:  6019         STR        R1, [R3]
+  0x08002F7A:  4920         LDR        R1, =onTimeCounterGN     ; [PC, #128] [0x08002FFC] =0x200006A4 
+  0x08002F7C:  2200         MOVS       R2, #0
+  0x08002F7E:  600A         STR        R2, [R1]
+  0x08002F80:  491D         LDR        R1, =blinkModeGN         ; [PC, #116] [0x08002FF8] =0x20000758 
+  0x08002F82:  700A         STRB       R2, [R1]
+  0x08002F84:  491B         LDR        R1, =offTimeCounterGN    ; [PC, #108] [0x08002FF4] =0x200006B4 
+  0x08002F86:  600A         STR        R2, [R1]
+  0x08002F88:  9E1E         LDR        R6, [SP, #120]
+  0x08002F8A:  611E         STR        R6, [R3, #16]
+  0x08002F8C:  490A         LDR        R1, =onTimeRT            ; [PC, #40] [0x08002FB8] =0x2000073C 
+  0x08002F8E:  700D         STRB       R5, [R1]
+  0x08002F90:  491B         LDR        R1, =offTimeCounterRT    ; [PC, #108] [0x08003000] =0x200006B0 
+  0x08002F92:  600A         STR        R2, [R1]
+  0x08002F94:  4909         LDR        R1, =offTimeRT           ; [PC, #36] [0x08002FBC] =0x20000748 
+  0x08002F96:  700D         STRB       R5, [R1]
+  0x08002F98:  4909         LDR        R1, =blinkModeRT         ; [PC, #36] [0x08002FC0] =0x20000754 
+  0x08002F9A:  700D         STRB       R5, [R1]
+  0x08002F9C:  4909         LDR        R1, =numberOfBlinks      ; [PC, #36] [0x08002FC4] =0x200006BC 
+  0x08002F9E:  600D         STR        R5, [R1]
+  0x08002FA0:  4909         LDR        R1, =blinkCounter        ; [PC, #36] [0x08002FC8] =0x200006EC 
+  0x08002FA2:  600D         STR        R5, [R1]
+  0x08002FA4:  490B         LDR        R1, =pauseTime           ; [PC, #44] [0x08002FD4] =0x20000734 
+  0x08002FA6:  700D         STRB       R5, [R1]
+  0x08002FA8:  601E         STR        R6, [R3]
+  0x08002FAA:  F000 FF99    BL         .L238                    ; 0x08003EE0
+  0x08002FAE:  46C0         NOP
+  0x08002FB0:  50000410     DC.W       0x50000410
+  0x08002FB4:  2000073A     DC.W       buttonState
+  0x08002FB8:  2000073C     DC.W       onTimeRT
+  0x08002FBC:  20000748     DC.W       offTimeRT
+  0x08002FC0:  20000754     DC.W       blinkModeRT
+  0x08002FC4:  200006BC     DC.W       numberOfBlinks
+  0x08002FC8:  200006EC     DC.W       blinkCounter
+  0x08002FCC:  0800661B     DC.W       0800661B               ; R_ARM_ABS32
+  0x08002FD0:  2000069C     DC.W       onTimeCounterRT
+  0x08002FD4:  20000734     DC.W       pauseTime
+  0x08002FD8:  080065BE     DC.W       080065BE               ; R_ARM_ABS32
+  0x08002FDC:  20000730     DC.W       relaisState
+  0x08002FE0:  200006A0     DC.W       onTimeCounterRESET
+  0x08002FE4:  200006B8     DC.W       offTimeCounter
+  0x08002FE8:  2000075C     DC.W       alarmMode
+  0x08002FEC:  200006A8     DC.W       onTimeCounter
+  0x08002FF0:  50000818     DC.W       0x50000818
+  0x08002FF4:  200006B4     DC.W       offTimeCounterGN
+  0x08002FF8:  20000758     DC.W       blinkModeGN
+  0x08002FFC:  200006A4     DC.W       onTimeCounterGN
+  0x08003000:  200006B0     DC.W       offTimeCounterRT
+  0x08003004:  080062FA     DC.W       080062FA               ; R_ARM_ABS32
+  0x08003008:  20000733     DC.W       smState.145
+  0x0800300C:  080064DD     DC.W       080064DD               ; R_ARM_ABS32
+  0x08003010:  20000698     DC.W       onTimeCounterSET
+  0x08003014:  20000740     DC.W       onTimeGN
+  0x08003018:  2000074C     DC.W       offTimeGN
+  0x0800301C:  080066EA     DC.W       080066EA               ; R_ARM_ABS32
+  0x08003020:  20000744     DC.W       onTime
+  0x08003024:  20000750     DC.W       offTime
+  0x08003028:  48F3         LDR        R0, =0x50000410          ; [PC, #0x03CC] [0x080033F8] 
+  0x0800302A:  6800         LDR        R0, [R0]
+  0x0800302C:  49F3         LDR        R1, =0x50000010          ; [PC, #0x03CC] [0x080033FC] 
+  0x0800302E:  6809         LDR        R1, [R1]
+  0x08003030:  0789         LSLS       R1, R1, #30
+  0x08003032:  D403         BMI        .L174                    ; 0x0800303C
+  0x08003034:  49F1         LDR        R1, =0x50000010          ; [PC, #0x03C4] [0x080033FC] 
+  0x08003036:  6809         LDR        R1, [R1]
+  0x08003038:  0789         LSLS       R1, R1, #30
+  0x0800303A:  D517         BPL        .L177                    ; 0x0800306C
+
.L174:
+  0x0800303C:  49F0         LDR        R1, =OVP_SM_On.oldtime   ; [PC, #0x03C0] [0x08003400] =0x2000071C 
+  0x0800303E:  680A         LDR        R2, [R1]
+  0x08003040:  4BF0         LDR        R3, =uwTick              ; [PC, #0x03C0] [0x08003404] =0x2000068C 
+  0x08003042:  681B         LDR        R3, [R3]
+  0x08003044:  4293         CMP        R3, R2
+  0x08003046:  D011         BEQ        .L177                    ; 0x0800306C
+  0x08003048:  4AEF         LDR        R2, =OVP_SM_On.ovpTimeCounter ; [PC, #0x03BC] [0x08003408] =0x20000718 
+  0x0800304A:  6813         LDR        R3, [R2]
+  0x0800304C:  4EEF         LDR        R6, =0x00001388          ; [PC, #0x03BC] [0x0800340C] 
+  0x0800304E:  42B3         CMP        R3, R6
+  0x08003050:  DA05         BGE        .L175                    ; 0x0800305E
+  0x08003052:  1C5E         ADDS       R6, R3, #1
+  0x08003054:  6016         STR        R6, [R2]
+  0x08003056:  4EED         LDR        R6, =0x00001388          ; [PC, #0x03B4] [0x0800340C] 
+  0x08003058:  1E76         SUBS       R6, R6, #1
+  0x0800305A:  42B3         CMP        R3, R6
+  0x0800305C:  D103         BNE        .L176                    ; 0x08003066
+
.L175:
+  0x0800305E:  2300         MOVS       R3, #0
+  0x08003060:  6013         STR        R3, [R2]
+  0x08003062:  4AEB         LDR        R2, =OVP_SM_On.ovpInput  ; [PC, #0x03AC] [0x08003410] =0x20000760 
+  0x08003064:  7015         STRB       R5, [R2]
+
.L176:
+  0x08003066:  4AE7         LDR        R2, =uwTick              ; [PC, #0x039C] [0x08003404] =0x2000068C 
+  0x08003068:  6812         LDR        R2, [R2]
+  0x0800306A:  600A         STR        R2, [R1]
+
.L177:
+  0x0800306C:  49E3         LDR        R1, =0x50000010          ; [PC, #0x038C] [0x080033FC] 
+  0x0800306E:  6809         LDR        R1, [R1]
+  0x08003070:  0789         LSLS       R1, R1, #30
+  0x08003072:  D404         BMI        .L178                    ; 0x0800307E
+  0x08003074:  49E4         LDR        R1, =OVP_SM_On.ovpTimeCounter ; [PC, #0x0390] [0x08003408] =0x20000718 
+  0x08003076:  2200         MOVS       R2, #0
+  0x08003078:  600A         STR        R2, [R1]
+  0x0800307A:  49E5         LDR        R1, =OVP_SM_On.ovpInput  ; [PC, #0x0394] [0x08003410] =0x20000760 
+  0x0800307C:  700A         STRB       R2, [R1]
+
.L178:
+  0x0800307E:  990F         LDR        R1, [SP, #60]
+  0x08003080:  4008         ANDS       R0, R1
+  0x08003082:  D134         BNE        .L179                    ; 0x080030EE
+  0x08003084:  4ADC         LDR        R2, =0x50000410          ; [PC, #0x0370] [0x080033F8] 
+  0x08003086:  981B         LDR        R0, [SP, #108]
+  0x08003088:  6190         STR        R0, [R2, #24]
+  0x0800308A:  981A         LDR        R0, [SP, #104]
+  0x0800308C:  6090         STR        R0, [R2, #8]
+  0x0800308E:  49E1         LDR        R1, =relaisState         ; [PC, #0x0384] [0x08003414] =0x20000730 
+  0x08003090:  2000         MOVS       R0, #0
+  0x08003092:  7008         STRB       R0, [R1]
+  0x08003094:  49E0         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0380] [0x08003418] =0x200006A0 
+  0x08003096:  9B16         LDR        R3, [SP, #88]
+  0x08003098:  600B         STR        R3, [R1]
+  0x0800309A:  9920         LDR        R1, [SP, #128]
+  0x0800309C:  6091         STR        R1, [R2, #8]
+  0x0800309E:  49DF         LDR        R1, =onTimeCounter       ; [PC, #0x037C] [0x0800341C] =0x200006A8 
+  0x080030A0:  9A09         LDR        R2, [SP, #36]
+  0x080030A2:  600A         STR        R2, [R1]
+  0x080030A4:  4ADE         LDR        R2, =0x50000818          ; [PC, #0x0378] [0x08003420] 
+  0x080030A6:  991F         LDR        R1, [SP, #124]
+  0x080030A8:  6111         STR        R1, [R2, #16]
+  0x080030AA:  49DE         LDR        R1, =offTimeCounterGN    ; [PC, #0x0378] [0x08003424] =0x200006B4 
+  0x080030AC:  6008         STR        R0, [R1]
+  0x080030AE:  49DE         LDR        R1, =blinkModeGN         ; [PC, #0x0378] [0x08003428] =0x20000758 
+  0x080030B0:  7008         STRB       R0, [R1]
+  0x080030B2:  49DE         LDR        R1, =onTimeCounterGN     ; [PC, #0x0378] [0x0800342C] =0x200006A4 
+  0x080030B4:  6008         STR        R0, [R1]
+  0x080030B6:  49DE         LDR        R1, =onTimeRT            ; [PC, #0x0378] [0x08003430] =0x2000073C 
+  0x080030B8:  700D         STRB       R5, [R1]
+  0x080030BA:  49DE         LDR        R1, =offTimeRT           ; [PC, #0x0378] [0x08003434] =0x20000748 
+  0x080030BC:  700D         STRB       R5, [R1]
+  0x080030BE:  49DE         LDR        R1, =blinkModeRT         ; [PC, #0x0378] [0x08003438] =0x20000754 
+  0x080030C0:  700D         STRB       R5, [R1]
+  0x080030C2:  49DE         LDR        R1, =numberOfBlinks      ; [PC, #0x0378] [0x0800343C] =0x200006BC 
+  0x080030C4:  9E15         LDR        R6, [SP, #84]
+  0x080030C6:  600E         STR        R6, [R1]
+  0x080030C8:  49DD         LDR        R1, =blinkCounter        ; [PC, #0x0374] [0x08003440] =0x200006EC 
+  0x080030CA:  600E         STR        R6, [R1]
+  0x080030CC:  49DD         LDR        R1, =pauseTime           ; [PC, #0x0374] [0x08003444] =0x20000734 
+  0x080030CE:  700D         STRB       R5, [R1]
+  0x080030D0:  991E         LDR        R1, [SP, #120]
+  0x080030D2:  6011         STR        R1, [R2]
+  0x080030D4:  49DC         LDR        R1, =buttonState         ; [PC, #0x0370] [0x08003448] =0x2000073A 
+  0x080030D6:  7008         STRB       R0, [R1]
+  0x080030D8:  48DC         LDR        R0, =onTimeCounterRT     ; [PC, #0x0370] [0x0800344C] =0x2000069C 
+  0x080030DA:  21C8         MOVS       R1, #200
+  0x080030DC:  6001         STR        R1, [R0]
+  0x080030DE:  48DC         LDR        R0, =0x08006990          ; [PC, #0x0370] [0x08003450] 
+  0x080030E0:  F002 F888    BL         puts                     ; 0x080051F4
+  0x080030E4:  48DB         LDR        R0, =0x08006730          ; [PC, #0x036C] [0x08003454] 
+  0x080030E6:  F002 F885    BL         puts                     ; 0x080051F4
+  0x080030EA:  48DB         LDR        R0, =smState.145         ; [PC, #0x036C] [0x08003458] =0x20000733 
+  0x080030EC:  7006         STRB       R6, [R0]
+
.L179:
+  0x080030EE:  48DB         LDR        R0, =temp                ; [PC, #0x036C] [0x0800345C] =0x20000690 
+  0x080030F0:  6800         LDR        R0, [R0]
+  0x080030F2:  2851         CMP        R0, #81
+  0x080030F4:  DB32         BLT        .L180                    ; 0x0800315C
+  0x080030F6:  4AC0         LDR        R2, =0x50000410          ; [PC, #0x0300] [0x080033F8] 
+  0x080030F8:  981B         LDR        R0, [SP, #108]
+  0x080030FA:  6190         STR        R0, [R2, #24]
+  0x080030FC:  981A         LDR        R0, [SP, #104]
+  0x080030FE:  6090         STR        R0, [R2, #8]
+  0x08003100:  49C4         LDR        R1, =relaisState         ; [PC, #0x0310] [0x08003414] =0x20000730 
+  0x08003102:  2000         MOVS       R0, #0
+  0x08003104:  7008         STRB       R0, [R1]
+  0x08003106:  49C4         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0310] [0x08003418] =0x200006A0 
+  0x08003108:  9B16         LDR        R3, [SP, #88]
+  0x0800310A:  600B         STR        R3, [R1]
+  0x0800310C:  9920         LDR        R1, [SP, #128]
+  0x0800310E:  6091         STR        R1, [R2, #8]
+  0x08003110:  49C2         LDR        R1, =onTimeCounter       ; [PC, #0x0308] [0x0800341C] =0x200006A8 
+  0x08003112:  9A09         LDR        R2, [SP, #36]
+  0x08003114:  600A         STR        R2, [R1]
+  0x08003116:  4BC2         LDR        R3, =0x50000818          ; [PC, #0x0308] [0x08003420] 
+  0x08003118:  991F         LDR        R1, [SP, #124]
+  0x0800311A:  6119         STR        R1, [R3, #16]
+  0x0800311C:  49C1         LDR        R1, =offTimeCounterGN    ; [PC, #0x0304] [0x08003424] =0x200006B4 
+  0x0800311E:  6008         STR        R0, [R1]
+  0x08003120:  49C1         LDR        R1, =blinkModeGN         ; [PC, #0x0304] [0x08003428] =0x20000758 
+  0x08003122:  7008         STRB       R0, [R1]
+  0x08003124:  49C1         LDR        R1, =onTimeCounterGN     ; [PC, #0x0304] [0x0800342C] =0x200006A4 
+  0x08003126:  6008         STR        R0, [R1]
+  0x08003128:  49C1         LDR        R1, =onTimeRT            ; [PC, #0x0304] [0x08003430] =0x2000073C 
+  0x0800312A:  700D         STRB       R5, [R1]
+  0x0800312C:  49C1         LDR        R1, =offTimeRT           ; [PC, #0x0304] [0x08003434] =0x20000748 
+  0x0800312E:  700D         STRB       R5, [R1]
+  0x08003130:  49C1         LDR        R1, =blinkModeRT         ; [PC, #0x0304] [0x08003438] =0x20000754 
+  0x08003132:  700D         STRB       R5, [R1]
+  0x08003134:  49C1         LDR        R1, =numberOfBlinks      ; [PC, #0x0304] [0x0800343C] =0x200006BC 
+  0x08003136:  2205         MOVS       R2, #5
+  0x08003138:  600A         STR        R2, [R1]
+  0x0800313A:  49C1         LDR        R1, =blinkCounter        ; [PC, #0x0304] [0x08003440] =0x200006EC 
+  0x0800313C:  600A         STR        R2, [R1]
+  0x0800313E:  49C1         LDR        R1, =pauseTime           ; [PC, #0x0304] [0x08003444] =0x20000734 
+  0x08003140:  700D         STRB       R5, [R1]
+  0x08003142:  991E         LDR        R1, [SP, #120]
+  0x08003144:  6019         STR        R1, [R3]
+  0x08003146:  49C0         LDR        R1, =buttonState         ; [PC, #0x0300] [0x08003448] =0x2000073A 
+  0x08003148:  7008         STRB       R0, [R1]
+  0x0800314A:  48C0         LDR        R0, =onTimeCounterRT     ; [PC, #0x0300] [0x0800344C] =0x2000069C 
+  0x0800314C:  21C8         MOVS       R1, #200
+  0x0800314E:  6001         STR        R1, [R0]
+  0x08003150:  48C3         LDR        R0, =0x08006330          ; [PC, #0x030C] [0x08003460] 
+  0x08003152:  F002 F84F    BL         puts                     ; 0x080051F4
+  0x08003156:  9815         LDR        R0, [SP, #84]
+  0x08003158:  49BF         LDR        R1, =smState.145         ; [PC, #0x02FC] [0x08003458] =0x20000733 
+  0x0800315A:  7008         STRB       R0, [R1]
+
.L180:
+  0x0800315C:  48AC         LDR        R0, =OVP_SM_On.ovpInput  ; [PC, #0x02B0] [0x08003410] =0x20000760 
+  0x0800315E:  4EAD         LDR        R6, =relaisState         ; [PC, #0x02B4] [0x08003414] =0x20000730 
+  0x08003160:  7800         LDRB       R0, [R0]
+  0x08003162:  2801         CMP        R0, #1
+  0x08003164:  7830         LDRB       R0, [R6]
+  0x08003166:  D124         BNE        .L181                    ; 0x080031B2
+  0x08003168:  2800         CMP        R0, #0
+  0x0800316A:  D048         BEQ        .L182                    ; 0x080031FE
+  0x0800316C:  4AA2         LDR        R2, =0x50000410          ; [PC, #0x0288] [0x080033F8] 
+  0x0800316E:  981B         LDR        R0, [SP, #108]
+  0x08003170:  6190         STR        R0, [R2, #24]
+  0x08003172:  981A         LDR        R0, [SP, #104]
+  0x08003174:  6090         STR        R0, [R2, #8]
+  0x08003176:  2000         MOVS       R0, #0
+  0x08003178:  7030         STRB       R0, [R6]
+  0x0800317A:  49A7         LDR        R1, =onTimeCounterRESET  ; [PC, #0x029C] [0x08003418] =0x200006A0 
+  0x0800317C:  9B16         LDR        R3, [SP, #88]
+  0x0800317E:  600B         STR        R3, [R1]
+  0x08003180:  9920         LDR        R1, [SP, #128]
+  0x08003182:  6091         STR        R1, [R2, #8]
+  0x08003184:  49A5         LDR        R1, =onTimeCounter       ; [PC, #0x0294] [0x0800341C] =0x200006A8 
+  0x08003186:  9A09         LDR        R2, [SP, #36]
+  0x08003188:  600A         STR        R2, [R1]
+  0x0800318A:  49A5         LDR        R1, =0x50000818          ; [PC, #0x0294] [0x08003420] 
+  0x0800318C:  9A1F         LDR        R2, [SP, #124]
+  0x0800318E:  610A         STR        R2, [R1, #16]
+  0x08003190:  49A4         LDR        R1, =offTimeCounterGN    ; [PC, #0x0290] [0x08003424] =0x200006B4 
+  0x08003192:  6008         STR        R0, [R1]
+  0x08003194:  49A4         LDR        R1, =blinkModeGN         ; [PC, #0x0290] [0x08003428] =0x20000758 
+  0x08003196:  7008         STRB       R0, [R1]
+  0x08003198:  49A4         LDR        R1, =onTimeCounterGN     ; [PC, #0x0290] [0x0800342C] =0x200006A4 
+  0x0800319A:  6008         STR        R0, [R1]
+  0x0800319C:  48B1         LDR        R0, =0x08006745          ; [PC, #0x02C4] [0x08003464] 
+  0x0800319E:  F002 F829    BL         puts                     ; 0x080051F4
+  0x080031A2:  48B1         LDR        R0, =0x080062D7          ; [PC, #0x02C4] [0x08003468] 
+  0x080031A4:  F002 F826    BL         puts                     ; 0x080051F4
+  0x080031A8:  4899         LDR        R0, =OVP_SM_On.ovpInput  ; [PC, #0x0264] [0x08003410] =0x20000760 
+  0x080031AA:  7800         LDRB       R0, [R0]
+  0x080031AC:  2800         CMP        R0, #0
+  0x080031AE:  D126         BNE        .L182                    ; 0x080031FE
+  0x080031B0:  7830         LDRB       R0, [R6]
+
.L181:
+  0x080031B2:  2800         CMP        R0, #0
+  0x080031B4:  D123         BNE        .L182                    ; 0x080031FE
+  0x080031B6:  4990         LDR        R1, =0x50000410          ; [PC, #0x0240] [0x080033F8] 
+  0x080031B8:  981A         LDR        R0, [SP, #104]
+  0x080031BA:  6188         STR        R0, [R1, #24]
+  0x080031BC:  981B         LDR        R0, [SP, #108]
+  0x080031BE:  6088         STR        R0, [R1, #8]
+  0x080031C0:  7035         STRB       R5, [R6]
+  0x080031C2:  48AA         LDR        R0, =onTimeCounterSET    ; [PC, #0x02A8] [0x0800346C] =0x20000698 
+  0x080031C4:  9A16         LDR        R2, [SP, #88]
+  0x080031C6:  6002         STR        R2, [R0]
+  0x080031C8:  9820         LDR        R0, [SP, #128]
+  0x080031CA:  6088         STR        R0, [R1, #8]
+  0x080031CC:  4893         LDR        R0, =onTimeCounter       ; [PC, #0x024C] [0x0800341C] =0x200006A8 
+  0x080031CE:  21C8         MOVS       R1, #200
+  0x080031D0:  6001         STR        R1, [R0]
+  0x080031D2:  4B93         LDR        R3, =0x50000818          ; [PC, #0x024C] [0x08003420] 
+  0x080031D4:  9F1F         LDR        R7, [SP, #124]
+  0x080031D6:  611F         STR        R7, [R3, #16]
+  0x080031D8:  48A5         LDR        R0, =onTimeGN            ; [PC, #0x0294] [0x08003470] =0x20000740 
+  0x080031DA:  7005         STRB       R5, [R0]
+  0x080031DC:  4891         LDR        R0, =offTimeCounterGN    ; [PC, #0x0244] [0x08003424] =0x200006B4 
+  0x080031DE:  2200         MOVS       R2, #0
+  0x080031E0:  6002         STR        R2, [R0]
+  0x080031E2:  48A4         LDR        R0, =offTimeGN           ; [PC, #0x0290] [0x08003474] =0x2000074C 
+  0x080031E4:  7005         STRB       R5, [R0]
+  0x080031E6:  4890         LDR        R0, =blinkModeGN         ; [PC, #0x0240] [0x08003428] =0x20000758 
+  0x080031E8:  7005         STRB       R5, [R0]
+  0x080031EA:  601F         STR        R7, [R3]
+  0x080031EC:  4627         MOV        R7, R4
+  0x080031EE:  488F         LDR        R0, =onTimeCounterGN     ; [PC, #0x023C] [0x0800342C] =0x200006A4 
+  0x080031F0:  6001         STR        R1, [R0]
+  0x080031F2:  48A1         LDR        R0, =0x0800694C          ; [PC, #0x0284] [0x08003478] 
+  0x080031F4:  F001 FFFE    BL         puts                     ; 0x080051F4
+  0x080031F8:  48A0         LDR        R0, =0x08006515          ; [PC, #0x0280] [0x0800347C] 
+  0x080031FA:  F001 FFFB    BL         puts                     ; 0x080051F4
+
.L182:
+  0x080031FE:  4892         LDR        R0, =buttonState         ; [PC, #0x0248] [0x08003448] =0x2000073A 
+  0x08003200:  7800         LDRB       R0, [R0]
+  0x08003202:  2800         CMP        R0, #0
+  0x08003204:  D001         BEQ        .L183                    ; 0x0800320A
+  0x08003206:  F000 FF85    BL         .L252                    ; 0x08004114
+
.L183:
+  0x0800320A:  497B         LDR        R1, =0x50000410          ; [PC, #0x01EC] [0x080033F8] 
+  0x0800320C:  981B         LDR        R0, [SP, #108]
+  0x0800320E:  6188         STR        R0, [R1, #24]
+  0x08003210:  981A         LDR        R0, [SP, #104]
+  0x08003212:  6088         STR        R0, [R1, #8]
+  0x08003214:  2700         MOVS       R7, #0
+  0x08003216:  7037         STRB       R7, [R6]
+  0x08003218:  487F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01FC] [0x08003418] =0x200006A0 
+  0x0800321A:  9A16         LDR        R2, [SP, #88]
+  0x0800321C:  6002         STR        R2, [R0]
+  0x0800321E:  9820         LDR        R0, [SP, #128]
+  0x08003220:  6088         STR        R0, [R1, #8]
+  0x08003222:  487E         LDR        R0, =onTimeCounter       ; [PC, #0x01F8] [0x0800341C] =0x200006A8 
+  0x08003224:  21C8         MOVS       R1, #200
+  0x08003226:  6001         STR        R1, [R0]
+  0x08003228:  497D         LDR        R1, =0x50000818          ; [PC, #0x01F4] [0x08003420] 
+  0x0800322A:  981F         LDR        R0, [SP, #124]
+  0x0800322C:  6108         STR        R0, [R1, #16]
+  0x0800322E:  487D         LDR        R0, =offTimeCounterGN    ; [PC, #0x01F4] [0x08003424] =0x200006B4 
+  0x08003230:  6007         STR        R7, [R0]
+  0x08003232:  487D         LDR        R0, =blinkModeGN         ; [PC, #0x01F4] [0x08003428] =0x20000758 
+  0x08003234:  7007         STRB       R7, [R0]
+  0x08003236:  487D         LDR        R0, =onTimeCounterGN     ; [PC, #0x01F4] [0x0800342C] =0x200006A4 
+  0x08003238:  6007         STR        R7, [R0]
+  0x0800323A:  981E         LDR        R0, [SP, #120]
+  0x0800323C:  6108         STR        R0, [R1, #16]
+  0x0800323E:  4890         LDR        R0, =offTimeCounterRT    ; [PC, #0x0240] [0x08003480] =0x200006B0 
+  0x08003240:  6007         STR        R7, [R0]
+  0x08003242:  487D         LDR        R0, =blinkModeRT         ; [PC, #0x01F4] [0x08003438] =0x20000754 
+  0x08003244:  7007         STRB       R7, [R0]
+  0x08003246:  4881         LDR        R0, =onTimeCounterRT     ; [PC, #0x0204] [0x0800344C] =0x2000069C 
+  0x08003248:  6007         STR        R7, [R0]
+  0x0800324A:  488E         LDR        R0, =0x080062FA          ; [PC, #0x0238] [0x08003484] 
+  0x0800324C:  F001 FFD2    BL         puts                     ; 0x080051F4
+  0x08003250:  4881         LDR        R0, =smState.145         ; [PC, #0x0204] [0x08003458] =0x20000733 
+  0x08003252:  7007         STRB       R7, [R0]
+  0x08003254:  486C         LDR        R0, =OVP_SM_On.ovpTimeCounter ; [PC, #0x01B0] [0x08003408] =0x20000718 
+  0x08003256:  6007         STR        R7, [R0]
+  0x08003258:  486D         LDR        R0, =OVP_SM_On.ovpInput  ; [PC, #0x01B4] [0x08003410] =0x20000760 
+  0x0800325A:  F000 FC88    BL         .L213                    ; 0x08003B6E
+  0x0800325E:  487A         LDR        R0, =buttonState         ; [PC, #0x01E8] [0x08003448] =0x2000073A 
+  0x08003260:  7800         LDRB       R0, [R0]
+  0x08003262:  2800         CMP        R0, #0
+  0x08003264:  D001         BEQ        .L184                    ; 0x0800326A
+  0x08003266:  F000 FF55    BL         .L252                    ; 0x08004114
+
.L184:
+  0x0800326A:  4963         LDR        R1, =0x50000410          ; [PC, #0x018C] [0x080033F8] 
+  0x0800326C:  981B         LDR        R0, [SP, #108]
+  0x0800326E:  6188         STR        R0, [R1, #24]
+  0x08003270:  981A         LDR        R0, [SP, #104]
+  0x08003272:  6088         STR        R0, [R1, #8]
+  0x08003274:  4867         LDR        R0, =relaisState         ; [PC, #0x019C] [0x08003414] =0x20000730 
+  0x08003276:  2600         MOVS       R6, #0
+  0x08003278:  7006         STRB       R6, [R0]
+  0x0800327A:  4867         LDR        R0, =onTimeCounterRESET  ; [PC, #0x019C] [0x08003418] =0x200006A0 
+  0x0800327C:  9A16         LDR        R2, [SP, #88]
+  0x0800327E:  6002         STR        R2, [R0]
+  0x08003280:  9820         LDR        R0, [SP, #128]
+  0x08003282:  6188         STR        R0, [R1, #24]
+  0x08003284:  4880         LDR        R0, =offTimeCounter      ; [PC, #0x0200] [0x08003488] =0x200006B8 
+  0x08003286:  6006         STR        R6, [R0]
+  0x08003288:  4880         LDR        R0, =alarmMode           ; [PC, #0x0200] [0x0800348C] =0x2000075C 
+  0x0800328A:  7006         STRB       R6, [R0]
+  0x0800328C:  4863         LDR        R0, =onTimeCounter       ; [PC, #0x018C] [0x0800341C] =0x200006A8 
+  0x0800328E:  6006         STR        R6, [R0]
+  0x08003290:  4963         LDR        R1, =0x50000818          ; [PC, #0x018C] [0x08003420] 
+  0x08003292:  981F         LDR        R0, [SP, #124]
+  0x08003294:  6108         STR        R0, [R1, #16]
+  0x08003296:  4863         LDR        R0, =offTimeCounterGN    ; [PC, #0x018C] [0x08003424] =0x200006B4 
+  0x08003298:  6006         STR        R6, [R0]
+  0x0800329A:  4863         LDR        R0, =blinkModeGN         ; [PC, #0x018C] [0x08003428] =0x20000758 
+  0x0800329C:  7006         STRB       R6, [R0]
+  0x0800329E:  4863         LDR        R0, =onTimeCounterGN     ; [PC, #0x018C] [0x0800342C] =0x200006A4 
+  0x080032A0:  6006         STR        R6, [R0]
+  0x080032A2:  981E         LDR        R0, [SP, #120]
+  0x080032A4:  6108         STR        R0, [R1, #16]
+  0x080032A6:  4876         LDR        R0, =offTimeCounterRT    ; [PC, #0x01D8] [0x08003480] =0x200006B0 
+  0x080032A8:  6006         STR        R6, [R0]
+  0x080032AA:  4863         LDR        R0, =blinkModeRT         ; [PC, #0x018C] [0x08003438] =0x20000754 
+  0x080032AC:  7006         STRB       R6, [R0]
+  0x080032AE:  4867         LDR        R0, =onTimeCounterRT     ; [PC, #0x019C] [0x0800344C] =0x2000069C 
+  0x080032B0:  6006         STR        R6, [R0]
+  0x080032B2:  4877         LDR        R0, =0x080062C0          ; [PC, #0x01DC] [0x08003490] 
+  0x080032B4:  F001 FF9E    BL         puts                     ; 0x080051F4
+  0x080032B8:  4876         LDR        R0, =smState.122         ; [PC, #0x01D8] [0x08003494] =0x20000736 
+  0x080032BA:  7006         STRB       R6, [R0]
+  0x080032BC:  F000 FF2A    BL         .L252                    ; 0x08004114
+  0x080032C0:  484D         LDR        R0, =0x50000410          ; [PC, #0x0134] [0x080033F8] 
+  0x080032C2:  6807         LDR        R7, [R0]
+  0x080032C4:  4860         LDR        R0, =buttonState         ; [PC, #0x0180] [0x08003448] =0x2000073A 
+  0x080032C6:  7800         LDRB       R0, [R0]
+  0x080032C8:  2800         CMP        R0, #0
+  0x080032CA:  D124         BNE        .L185                    ; 0x08003316
+  0x080032CC:  494A         LDR        R1, =0x50000410          ; [PC, #0x0128] [0x080033F8] 
+  0x080032CE:  981B         LDR        R0, [SP, #108]
+  0x080032D0:  6188         STR        R0, [R1, #24]
+  0x080032D2:  981A         LDR        R0, [SP, #104]
+  0x080032D4:  6088         STR        R0, [R1, #8]
+  0x080032D6:  484F         LDR        R0, =relaisState         ; [PC, #0x013C] [0x08003414] =0x20000730 
+  0x080032D8:  2600         MOVS       R6, #0
+  0x080032DA:  7006         STRB       R6, [R0]
+  0x080032DC:  484E         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0138] [0x08003418] =0x200006A0 
+  0x080032DE:  9A16         LDR        R2, [SP, #88]
+  0x080032E0:  6002         STR        R2, [R0]
+  0x080032E2:  9820         LDR        R0, [SP, #128]
+  0x080032E4:  6088         STR        R0, [R1, #8]
+  0x080032E6:  484D         LDR        R0, =onTimeCounter       ; [PC, #0x0134] [0x0800341C] =0x200006A8 
+  0x080032E8:  21C8         MOVS       R1, #200
+  0x080032EA:  6001         STR        R1, [R0]
+  0x080032EC:  494C         LDR        R1, =0x50000818          ; [PC, #0x0130] [0x08003420] 
+  0x080032EE:  981F         LDR        R0, [SP, #124]
+  0x080032F0:  6108         STR        R0, [R1, #16]
+  0x080032F2:  484C         LDR        R0, =offTimeCounterGN    ; [PC, #0x0130] [0x08003424] =0x200006B4 
+  0x080032F4:  6006         STR        R6, [R0]
+  0x080032F6:  484C         LDR        R0, =blinkModeGN         ; [PC, #0x0130] [0x08003428] =0x20000758 
+  0x080032F8:  7006         STRB       R6, [R0]
+  0x080032FA:  484C         LDR        R0, =onTimeCounterGN     ; [PC, #0x0130] [0x0800342C] =0x200006A4 
+  0x080032FC:  6006         STR        R6, [R0]
+  0x080032FE:  981E         LDR        R0, [SP, #120]
+  0x08003300:  6108         STR        R0, [R1, #16]
+  0x08003302:  485F         LDR        R0, =offTimeCounterRT    ; [PC, #0x017C] [0x08003480] =0x200006B0 
+  0x08003304:  6006         STR        R6, [R0]
+  0x08003306:  484C         LDR        R0, =blinkModeRT         ; [PC, #0x0130] [0x08003438] =0x20000754 
+  0x08003308:  7006         STRB       R6, [R0]
+  0x0800330A:  4850         LDR        R0, =onTimeCounterRT     ; [PC, #0x0140] [0x0800344C] =0x2000069C 
+  0x0800330C:  6006         STR        R6, [R0]
+  0x0800330E:  4862         LDR        R0, =0x080064DD          ; [PC, #0x0188] [0x08003498] 
+  0x08003310:  F001 FF70    BL         puts                     ; 0x080051F4
+  0x08003314:  7026         STRB       R6, [R4]
+
.L185:
+  0x08003316:  980F         LDR        R0, [SP, #60]
+  0x08003318:  4007         ANDS       R7, R0
+  0x0800331A:  D130         BNE        .L186                    ; 0x0800337E
+  0x0800331C:  4A36         LDR        R2, =0x50000410          ; [PC, #216] [0x080033F8] 
+  0x0800331E:  981B         LDR        R0, [SP, #108]
+  0x08003320:  6190         STR        R0, [R2, #24]
+  0x08003322:  981A         LDR        R0, [SP, #104]
+  0x08003324:  6090         STR        R0, [R2, #8]
+  0x08003326:  493B         LDR        R1, =relaisState         ; [PC, #236] [0x08003414] =0x20000730 
+  0x08003328:  700F         STRB       R7, [R1]
+  0x0800332A:  493B         LDR        R1, =onTimeCounterRESET  ; [PC, #236] [0x08003418] =0x200006A0 
+  0x0800332C:  9B16         LDR        R3, [SP, #88]
+  0x0800332E:  600B         STR        R3, [R1]
+  0x08003330:  9920         LDR        R1, [SP, #128]
+  0x08003332:  6091         STR        R1, [R2, #8]
+  0x08003334:  9910         LDR        R1, [SP, #64]
+  0x08003336:  31F4         ADDS       R1, #244
+  0x08003338:  4A38         LDR        R2, =onTimeCounter       ; [PC, #224] [0x0800341C] =0x200006A8 
+  0x0800333A:  6011         STR        R1, [R2]
+  0x0800333C:  4A38         LDR        R2, =0x50000818          ; [PC, #224] [0x08003420] 
+  0x0800333E:  991F         LDR        R1, [SP, #124]
+  0x08003340:  6111         STR        R1, [R2, #16]
+  0x08003342:  4938         LDR        R1, =offTimeCounterGN    ; [PC, #224] [0x08003424] =0x200006B4 
+  0x08003344:  600F         STR        R7, [R1]
+  0x08003346:  4938         LDR        R1, =blinkModeGN         ; [PC, #224] [0x08003428] =0x20000758 
+  0x08003348:  700F         STRB       R7, [R1]
+  0x0800334A:  4938         LDR        R1, =onTimeCounterGN     ; [PC, #224] [0x0800342C] =0x200006A4 
+  0x0800334C:  600F         STR        R7, [R1]
+  0x0800334E:  4938         LDR        R1, =onTimeRT            ; [PC, #224] [0x08003430] =0x2000073C 
+  0x08003350:  700D         STRB       R5, [R1]
+  0x08003352:  4938         LDR        R1, =offTimeRT           ; [PC, #224] [0x08003434] =0x20000748 
+  0x08003354:  700D         STRB       R5, [R1]
+  0x08003356:  4938         LDR        R1, =blinkModeRT         ; [PC, #224] [0x08003438] =0x20000754 
+  0x08003358:  700D         STRB       R5, [R1]
+  0x0800335A:  4938         LDR        R1, =numberOfBlinks      ; [PC, #224] [0x0800343C] =0x200006BC 
+  0x0800335C:  2603         MOVS       R6, #3
+  0x0800335E:  600E         STR        R6, [R1]
+  0x08003360:  4937         LDR        R1, =blinkCounter        ; [PC, #220] [0x08003440] =0x200006EC 
+  0x08003362:  600E         STR        R6, [R1]
+  0x08003364:  4937         LDR        R1, =pauseTime           ; [PC, #220] [0x08003444] =0x20000734 
+  0x08003366:  700D         STRB       R5, [R1]
+  0x08003368:  991E         LDR        R1, [SP, #120]
+  0x0800336A:  6011         STR        R1, [R2]
+  0x0800336C:  4936         LDR        R1, =buttonState         ; [PC, #216] [0x08003448] =0x2000073A 
+  0x0800336E:  700F         STRB       R7, [R1]
+  0x08003370:  4836         LDR        R0, =onTimeCounterRT     ; [PC, #216] [0x0800344C] =0x2000069C 
+  0x08003372:  21C8         MOVS       R1, #200
+  0x08003374:  6001         STR        R1, [R0]
+  0x08003376:  4849         LDR        R0, =0x08006910          ; [PC, #0x0124] [0x0800349C] 
+  0x08003378:  F001 FF3C    BL         puts                     ; 0x080051F4
+  0x0800337C:  7026         STRB       R6, [R4]
+
.L186:
+  0x0800337E:  4837         LDR        R0, =temp                ; [PC, #220] [0x0800345C] =0x20000690 
+  0x08003380:  6800         LDR        R0, [R0]
+  0x08003382:  2851         CMP        R0, #81
+  0x08003384:  4F46         LDR        R7, =0x000003C7          ; [PC, #0x0118] [0x080034A0] 
+  0x08003386:  DA01         BGE        .L187                    ; 0x0800338C
+  0x08003388:  F000 FEC4    BL         .L252                    ; 0x08004114
+
.L187:
+  0x0800338C:  4A1A         LDR        R2, =0x50000410          ; [PC, #104] [0x080033F8] 
+  0x0800338E:  981B         LDR        R0, [SP, #108]
+  0x08003390:  6190         STR        R0, [R2, #24]
+  0x08003392:  981A         LDR        R0, [SP, #104]
+  0x08003394:  6090         STR        R0, [R2, #8]
+  0x08003396:  491F         LDR        R1, =relaisState         ; [PC, #124] [0x08003414] =0x20000730 
+  0x08003398:  2000         MOVS       R0, #0
+  0x0800339A:  7008         STRB       R0, [R1]
+  0x0800339C:  491E         LDR        R1, =onTimeCounterRESET  ; [PC, #120] [0x08003418] =0x200006A0 
+  0x0800339E:  9B16         LDR        R3, [SP, #88]
+  0x080033A0:  600B         STR        R3, [R1]
+  0x080033A2:  9920         LDR        R1, [SP, #128]
+  0x080033A4:  6091         STR        R1, [R2, #8]
+  0x080033A6:  9910         LDR        R1, [SP, #64]
+  0x080033A8:  31F4         ADDS       R1, #244
+  0x080033AA:  4A1C         LDR        R2, =onTimeCounter       ; [PC, #112] [0x0800341C] =0x200006A8 
+  0x080033AC:  6011         STR        R1, [R2]
+  0x080033AE:  4B1C         LDR        R3, =0x50000818          ; [PC, #112] [0x08003420] 
+  0x080033B0:  991F         LDR        R1, [SP, #124]
+  0x080033B2:  6119         STR        R1, [R3, #16]
+  0x080033B4:  491B         LDR        R1, =offTimeCounterGN    ; [PC, #108] [0x08003424] =0x200006B4 
+  0x080033B6:  6008         STR        R0, [R1]
+  0x080033B8:  491B         LDR        R1, =blinkModeGN         ; [PC, #108] [0x08003428] =0x20000758 
+  0x080033BA:  7008         STRB       R0, [R1]
+  0x080033BC:  491B         LDR        R1, =onTimeCounterGN     ; [PC, #108] [0x0800342C] =0x200006A4 
+  0x080033BE:  6008         STR        R0, [R1]
+  0x080033C0:  491B         LDR        R1, =onTimeRT            ; [PC, #108] [0x08003430] =0x2000073C 
+  0x080033C2:  700D         STRB       R5, [R1]
+  0x080033C4:  491B         LDR        R1, =offTimeRT           ; [PC, #108] [0x08003434] =0x20000748 
+  0x080033C6:  700D         STRB       R5, [R1]
+  0x080033C8:  491B         LDR        R1, =blinkModeRT         ; [PC, #108] [0x08003438] =0x20000754 
+  0x080033CA:  700D         STRB       R5, [R1]
+  0x080033CC:  491B         LDR        R1, =numberOfBlinks      ; [PC, #108] [0x0800343C] =0x200006BC 
+  0x080033CE:  2205         MOVS       R2, #5
+  0x080033D0:  600A         STR        R2, [R1]
+  0x080033D2:  491B         LDR        R1, =blinkCounter        ; [PC, #108] [0x08003440] =0x200006EC 
+  0x080033D4:  600A         STR        R2, [R1]
+  0x080033D6:  491B         LDR        R1, =pauseTime           ; [PC, #108] [0x08003444] =0x20000734 
+  0x080033D8:  700D         STRB       R5, [R1]
+  0x080033DA:  991E         LDR        R1, [SP, #120]
+  0x080033DC:  6019         STR        R1, [R3]
+  0x080033DE:  491A         LDR        R1, =buttonState         ; [PC, #104] [0x08003448] =0x2000073A 
+  0x080033E0:  7008         STRB       R0, [R1]
+  0x080033E2:  481A         LDR        R0, =onTimeCounterRT     ; [PC, #104] [0x0800344C] =0x2000069C 
+  0x080033E4:  21C8         MOVS       R1, #200
+  0x080033E6:  6001         STR        R1, [R0]
+  0x080033E8:  481D         LDR        R0, =0x08006330          ; [PC, #116] [0x08003460] 
+  0x080033EA:  F001 FF03    BL         puts                     ; 0x080051F4
+  0x080033EE:  2003         MOVS       R0, #3
+  0x080033F0:  7020         STRB       R0, [R4]
+  0x080033F2:  F000 FE8F    BL         .L252                    ; 0x08004114
+  0x080033F6:  46C0         NOP
+  0x080033F8:  50000410     DC.W       0x50000410
+  0x080033FC:  50000010     DC.W       0x50000010
+  0x08003400:  2000071C     DC.W       OVP_SM_On.oldtime
+  0x08003404:  2000068C     DC.W       uwTick
+  0x08003408:  20000718     DC.W       OVP_SM_On.ovpTimeCounter
+  0x0800340C:  00001388     DC.W       0x00001388
+  0x08003410:  20000760     DC.W       OVP_SM_On.ovpInput
+  0x08003414:  20000730     DC.W       relaisState
+  0x08003418:  200006A0     DC.W       onTimeCounterRESET
+  0x0800341C:  200006A8     DC.W       onTimeCounter
+  0x08003420:  50000818     DC.W       0x50000818
+  0x08003424:  200006B4     DC.W       offTimeCounterGN
+  0x08003428:  20000758     DC.W       blinkModeGN
+  0x0800342C:  200006A4     DC.W       onTimeCounterGN
+  0x08003430:  2000073C     DC.W       onTimeRT
+  0x08003434:  20000748     DC.W       offTimeRT
+  0x08003438:  20000754     DC.W       blinkModeRT
+  0x0800343C:  200006BC     DC.W       numberOfBlinks
+  0x08003440:  200006EC     DC.W       blinkCounter
+  0x08003444:  20000734     DC.W       pauseTime
+  0x08003448:  2000073A     DC.W       buttonState
+  0x0800344C:  2000069C     DC.W       onTimeCounterRT
+  0x08003450:  08006990     DC.W       08006990               ; R_ARM_ABS32
+  0x08003454:  08006730     DC.W       08006730               ; R_ARM_ABS32
+  0x08003458:  20000733     DC.W       smState.145
+  0x0800345C:  20000690     DC.W       temp
+  0x08003460:  08006330     DC.W       08006330               ; R_ARM_ABS32
+  0x08003464:  08006745     DC.W       08006745               ; R_ARM_ABS32
+  0x08003468:  080062D7     DC.W       080062D7               ; R_ARM_ABS32
+  0x0800346C:  20000698     DC.W       onTimeCounterSET
+  0x08003470:  20000740     DC.W       onTimeGN
+  0x08003474:  2000074C     DC.W       offTimeGN
+  0x08003478:  0800694C     DC.W       0800694C               ; R_ARM_ABS32
+  0x0800347C:  08006515     DC.W       08006515               ; R_ARM_ABS32
+  0x08003480:  200006B0     DC.W       offTimeCounterRT
+  0x08003484:  080062FA     DC.W       080062FA               ; R_ARM_ABS32
+  0x08003488:  200006B8     DC.W       offTimeCounter
+  0x0800348C:  2000075C     DC.W       alarmMode
+  0x08003490:  080062C0     DC.W       080062C0               ; R_ARM_ABS32
+  0x08003494:  20000736     DC.W       smState.122
+  0x08003498:  080064DD     DC.W       080064DD               ; R_ARM_ABS32
+  0x0800349C:  08006910     DC.W       08006910               ; R_ARM_ABS32
+  0x080034A0:  000003C7     DC.W       0x000003C7
+  0x080034A4:  48F0         LDR        R0, =buttonState         ; [PC, #0x03C0] [0x08003868] =0x2000073A 
+  0x080034A6:  7800         LDRB       R0, [R0]
+  0x080034A8:  2800         CMP        R0, #0
+  0x080034AA:  D001         BEQ        .L188                    ; 0x080034B0
+  0x080034AC:  F000 FE32    BL         .L252                    ; 0x08004114
+
.L188:
+  0x080034B0:  49EE         LDR        R1, =0x50000410          ; [PC, #0x03B8] [0x0800386C] 
+  0x080034B2:  981B         LDR        R0, [SP, #108]
+  0x080034B4:  6188         STR        R0, [R1, #24]
+  0x080034B6:  981A         LDR        R0, [SP, #104]
+  0x080034B8:  6088         STR        R0, [R1, #8]
+  0x080034BA:  48ED         LDR        R0, =relaisState         ; [PC, #0x03B4] [0x08003870] =0x20000730 
+  0x080034BC:  2600         MOVS       R6, #0
+  0x080034BE:  7006         STRB       R6, [R0]
+  0x080034C0:  48EC         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03B0] [0x08003874] =0x200006A0 
+  0x080034C2:  9A16         LDR        R2, [SP, #88]
+  0x080034C4:  6002         STR        R2, [R0]
+  0x080034C6:  9820         LDR        R0, [SP, #128]
+  0x080034C8:  6188         STR        R0, [R1, #24]
+  0x080034CA:  48EB         LDR        R0, =offTimeCounter      ; [PC, #0x03AC] [0x08003878] =0x200006B8 
+  0x080034CC:  6006         STR        R6, [R0]
+  0x080034CE:  48EB         LDR        R0, =alarmMode           ; [PC, #0x03AC] [0x0800387C] =0x2000075C 
+  0x080034D0:  7006         STRB       R6, [R0]
+  0x080034D2:  48EB         LDR        R0, =onTimeCounter       ; [PC, #0x03AC] [0x08003880] =0x200006A8 
+  0x080034D4:  6006         STR        R6, [R0]
+  0x080034D6:  49EB         LDR        R1, =0x50000818          ; [PC, #0x03AC] [0x08003884] 
+  0x080034D8:  981F         LDR        R0, [SP, #124]
+  0x080034DA:  6108         STR        R0, [R1, #16]
+  0x080034DC:  48EA         LDR        R0, =offTimeCounterGN    ; [PC, #0x03A8] [0x08003888] =0x200006B4 
+  0x080034DE:  6006         STR        R6, [R0]
+  0x080034E0:  48EA         LDR        R0, =blinkModeGN         ; [PC, #0x03A8] [0x0800388C] =0x20000758 
+  0x080034E2:  7006         STRB       R6, [R0]
+  0x080034E4:  48EA         LDR        R0, =onTimeCounterGN     ; [PC, #0x03A8] [0x08003890] =0x200006A4 
+  0x080034E6:  6006         STR        R6, [R0]
+  0x080034E8:  981E         LDR        R0, [SP, #120]
+  0x080034EA:  6108         STR        R0, [R1, #16]
+  0x080034EC:  48E9         LDR        R0, =offTimeCounterRT    ; [PC, #0x03A4] [0x08003894] =0x200006B0 
+  0x080034EE:  6006         STR        R6, [R0]
+  0x080034F0:  48E9         LDR        R0, =blinkModeRT         ; [PC, #0x03A4] [0x08003898] =0x20000754 
+  0x080034F2:  7006         STRB       R6, [R0]
+  0x080034F4:  48E9         LDR        R0, =onTimeCounterRT     ; [PC, #0x03A4] [0x0800389C] =0x2000069C 
+  0x080034F6:  6006         STR        R6, [R0]
+  0x080034F8:  48E9         LDR        R0, =0x08006286          ; [PC, #0x03A4] [0x080038A0] 
+  0x080034FA:  F001 FE7B    BL         puts                     ; 0x080051F4
+  0x080034FE:  48E9         LDR        R0, =smState             ; [PC, #0x03A4] [0x080038A4] =0x20000737 
+  0x08003500:  7006         STRB       R6, [R0]
+  0x08003502:  F000 FE07    BL         .L252                    ; 0x08004114
+  0x08003506:  48D9         LDR        R0, =0x50000410          ; [PC, #0x0364] [0x0800386C] 
+  0x08003508:  6801         LDR        R1, [R0]
+  0x0800350A:  4ED7         LDR        R6, =buttonState         ; [PC, #0x035C] [0x08003868] =0x2000073A 
+  0x0800350C:  7830         LDRB       R0, [R6]
+  0x0800350E:  2801         CMP        R0, #1
+  0x08003510:  D12A         BNE        .L189                    ; 0x08003568
+  0x08003512:  0748         LSLS       R0, R1, #29
+  0x08003514:  D56A         BPL        .L192                    ; 0x080035EC
+  0x08003516:  49D5         LDR        R1, =0x50000410          ; [PC, #0x0354] [0x0800386C] 
+  0x08003518:  981A         LDR        R0, [SP, #104]
+  0x0800351A:  6188         STR        R0, [R1, #24]
+  0x0800351C:  981B         LDR        R0, [SP, #108]
+  0x0800351E:  6088         STR        R0, [R1, #8]
+  0x08003520:  48D3         LDR        R0, =relaisState         ; [PC, #0x034C] [0x08003870] =0x20000730 
+  0x08003522:  7005         STRB       R5, [R0]
+  0x08003524:  48E0         LDR        R0, =onTimeCounterSET    ; [PC, #0x0380] [0x080038A8] =0x20000698 
+  0x08003526:  9A16         LDR        R2, [SP, #88]
+  0x08003528:  6002         STR        R2, [R0]
+  0x0800352A:  9820         LDR        R0, [SP, #128]
+  0x0800352C:  6088         STR        R0, [R1, #8]
+  0x0800352E:  48DF         LDR        R0, =onTimeGN            ; [PC, #0x037C] [0x080038AC] =0x20000740 
+  0x08003530:  7005         STRB       R5, [R0]
+  0x08003532:  48D3         LDR        R0, =onTimeCounter       ; [PC, #0x034C] [0x08003880] =0x200006A8 
+  0x08003534:  21C8         MOVS       R1, #200
+  0x08003536:  6001         STR        R1, [R0]
+  0x08003538:  48DD         LDR        R0, =offTimeGN           ; [PC, #0x0374] [0x080038B0] =0x2000074C 
+  0x0800353A:  7005         STRB       R5, [R0]
+  0x0800353C:  48D3         LDR        R0, =blinkModeGN         ; [PC, #0x034C] [0x0800388C] =0x20000758 
+  0x0800353E:  7005         STRB       R5, [R0]
+  0x08003540:  4AD0         LDR        R2, =0x50000818          ; [PC, #0x0340] [0x08003884] 
+  0x08003542:  981F         LDR        R0, [SP, #124]
+  0x08003544:  6010         STR        R0, [R2]
+  0x08003546:  48D2         LDR        R0, =onTimeCounterGN     ; [PC, #0x0348] [0x08003890] =0x200006A4 
+  0x08003548:  6001         STR        R1, [R0]
+  0x0800354A:  981E         LDR        R0, [SP, #120]
+  0x0800354C:  6110         STR        R0, [R2, #16]
+  0x0800354E:  48D1         LDR        R0, =offTimeCounterRT    ; [PC, #0x0344] [0x08003894] =0x200006B0 
+  0x08003550:  2100         MOVS       R1, #0
+  0x08003552:  6001         STR        R1, [R0]
+  0x08003554:  48D0         LDR        R0, =blinkModeRT         ; [PC, #0x0340] [0x08003898] =0x20000754 
+  0x08003556:  7001         STRB       R1, [R0]
+  0x08003558:  48D0         LDR        R0, =onTimeCounterRT     ; [PC, #0x0340] [0x0800389C] =0x2000069C 
+  0x0800355A:  6001         STR        R1, [R0]
+  0x0800355C:  48D5         LDR        R0, =0x080064C7          ; [PC, #0x0354] [0x080038B4] 
+  0x0800355E:  F001 FE49    BL         puts                     ; 0x080051F4
+  0x08003562:  48D5         LDR        R0, =smState.122         ; [PC, #0x0354] [0x080038B8] =0x20000736 
+  0x08003564:  7005         STRB       R5, [R0]
+  0x08003566:  7830         LDRB       R0, [R6]
+
.L189:
+  0x08003568:  2802         CMP        R0, #2
+  0x0800356A:  D001         BEQ        .L190                    ; 0x08003570
+  0x0800356C:  F000 FDD2    BL         .L252                    ; 0x08004114
+
.L190:
+  0x08003570:  49BE         LDR        R1, =0x50000410          ; [PC, #0x02F8] [0x0800386C] 
+  0x08003572:  981A         LDR        R0, [SP, #104]
+  0x08003574:  6188         STR        R0, [R1, #24]
+  0x08003576:  981B         LDR        R0, [SP, #108]
+  0x08003578:  6088         STR        R0, [R1, #8]
+  0x0800357A:  48BD         LDR        R0, =relaisState         ; [PC, #0x02F4] [0x08003870] =0x20000730 
+  0x0800357C:  7005         STRB       R5, [R0]
+  0x0800357E:  48CA         LDR        R0, =onTimeCounterSET    ; [PC, #0x0328] [0x080038A8] =0x20000698 
+  0x08003580:  9A16         LDR        R2, [SP, #88]
+  0x08003582:  6002         STR        R2, [R0]
+  0x08003584:  48CD         LDR        R0, =onTime              ; [PC, #0x0334] [0x080038BC] =0x20000744 
+  0x08003586:  7005         STRB       R5, [R0]
+  0x08003588:  48CD         LDR        R0, =offTime             ; [PC, #0x0334] [0x080038C0] =0x20000750 
+  0x0800358A:  7005         STRB       R5, [R0]
+  0x0800358C:  48BB         LDR        R0, =alarmMode           ; [PC, #0x02EC] [0x0800387C] =0x2000075C 
+  0x0800358E:  7005         STRB       R5, [R0]
+  0x08003590:  9820         LDR        R0, [SP, #128]
+  0x08003592:  6088         STR        R0, [R1, #8]
+  0x08003594:  49BA         LDR        R1, =onTimeCounter       ; [PC, #0x02E8] [0x08003880] =0x200006A8 
+  0x08003596:  20C8         MOVS       R0, #200
+  0x08003598:  6008         STR        R0, [R1]
+  0x0800359A:  4BBA         LDR        R3, =0x50000818          ; [PC, #0x02E8] [0x08003884] 
+  0x0800359C:  991F         LDR        R1, [SP, #124]
+  0x0800359E:  6019         STR        R1, [R3]
+  0x080035A0:  49BB         LDR        R1, =onTimeCounterGN     ; [PC, #0x02EC] [0x08003890] =0x200006A4 
+  0x080035A2:  2200         MOVS       R2, #0
+  0x080035A4:  600A         STR        R2, [R1]
+  0x080035A6:  49B9         LDR        R1, =blinkModeGN         ; [PC, #0x02E4] [0x0800388C] =0x20000758 
+  0x080035A8:  700A         STRB       R2, [R1]
+  0x080035AA:  49B7         LDR        R1, =offTimeCounterGN    ; [PC, #0x02DC] [0x08003888] =0x200006B4 
+  0x080035AC:  600A         STR        R2, [R1]
+  0x080035AE:  9E1E         LDR        R6, [SP, #120]
+  0x080035B0:  611E         STR        R6, [R3, #16]
+  0x080035B2:  49C4         LDR        R1, =onTimeRT            ; [PC, #0x0310] [0x080038C4] =0x2000073C 
+  0x080035B4:  700D         STRB       R5, [R1]
+  0x080035B6:  49B7         LDR        R1, =offTimeCounterRT    ; [PC, #0x02DC] [0x08003894] =0x200006B0 
+  0x080035B8:  600A         STR        R2, [R1]
+  0x080035BA:  49C3         LDR        R1, =offTimeRT           ; [PC, #0x030C] [0x080038C8] =0x20000748 
+  0x080035BC:  700D         STRB       R5, [R1]
+  0x080035BE:  49B6         LDR        R1, =blinkModeRT         ; [PC, #0x02D8] [0x08003898] =0x20000754 
+  0x080035C0:  700D         STRB       R5, [R1]
+  0x080035C2:  49C2         LDR        R1, =numberOfBlinks      ; [PC, #0x0308] [0x080038CC] =0x200006BC 
+  0x080035C4:  600D         STR        R5, [R1]
+  0x080035C6:  49C2         LDR        R1, =blinkCounter        ; [PC, #0x0308] [0x080038D0] =0x200006EC 
+  0x080035C8:  600D         STR        R5, [R1]
+  0x080035CA:  49C2         LDR        R1, =pauseTime           ; [PC, #0x0308] [0x080038D4] =0x20000734 
+  0x080035CC:  700D         STRB       R5, [R1]
+  0x080035CE:  601E         STR        R6, [R3]
+  0x080035D0:  F000 FD3E    BL         .L246                    ; 0x08004050
+  0x080035D4:  48A5         LDR        R0, =0x50000410          ; [PC, #0x0294] [0x0800386C] 
+  0x080035D6:  6801         LDR        R1, [R0]
+  0x080035D8:  4EA3         LDR        R6, =buttonState         ; [PC, #0x028C] [0x08003868] =0x2000073A 
+  0x080035DA:  7830         LDRB       R0, [R6]
+  0x080035DC:  2801         CMP        R0, #1
+  0x080035DE:  D001         BEQ        .L191                    ; 0x080035E4
+  0x080035E0:  F000 FCAF    BL         .L240                    ; 0x08003F42
+
.L191:
+  0x080035E4:  0748         LSLS       R0, R1, #29
+  0x080035E6:  D501         BPL        .L192                    ; 0x080035EC
+  0x080035E8:  F000 FC82    BL         .L239                    ; 0x08003EF0
+
.L192:
+  0x080035EC:  489F         LDR        R0, =0x50000410          ; [PC, #0x027C] [0x0800386C] 
+  0x080035EE:  9920         LDR        R1, [SP, #128]
+  0x080035F0:  6081         STR        R1, [R0, #8]
+  0x080035F2:  2000         MOVS       R0, #0
+  0x080035F4:  7030         STRB       R0, [R6]
+  0x080035F6:  9810         LDR        R0, [SP, #64]
+  0x080035F8:  30F4         ADDS       R0, #244
+  0x080035FA:  49A1         LDR        R1, =onTimeCounter       ; [PC, #0x0284] [0x08003880] =0x200006A8 
+  0x080035FC:  6008         STR        R0, [R1]
+  0x080035FE:  F000 FD89    BL         .L252                    ; 0x08004114
+  0x08003602:  489A         LDR        R0, =0x50000410          ; [PC, #0x0268] [0x0800386C] 
+  0x08003604:  6800         LDR        R0, [R0]
+  0x08003606:  49B4         LDR        R1, =0x50000010          ; [PC, #0x02D0] [0x080038D8] 
+  0x08003608:  6809         LDR        R1, [R1]
+  0x0800360A:  07C9         LSLS       R1, R1, #31
+  0x0800360C:  D103         BNE        .L193                    ; 0x08003616
+  0x0800360E:  49B2         LDR        R1, =0x50000010          ; [PC, #0x02C8] [0x080038D8] 
+  0x08003610:  6809         LDR        R1, [R1]
+  0x08003612:  0789         LSLS       R1, R1, #30
+  0x08003614:  D517         BPL        .L196                    ; 0x08003646
+
.L193:
+  0x08003616:  49B1         LDR        R1, =LVP_OVP_SM_On.oldtime ; [PC, #0x02C4] [0x080038DC] =0x20000728 
+  0x08003618:  680A         LDR        R2, [R1]
+  0x0800361A:  4BB1         LDR        R3, =uwTick              ; [PC, #0x02C4] [0x080038E0] =0x2000068C 
+  0x0800361C:  681B         LDR        R3, [R3]
+  0x0800361E:  4293         CMP        R3, R2
+  0x08003620:  D011         BEQ        .L196                    ; 0x08003646
+  0x08003622:  4AB0         LDR        R2, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x02C0] [0x080038E4] =0x2000072C 
+  0x08003624:  6813         LDR        R3, [R2]
+  0x08003626:  4EB0         LDR        R6, =0x00001388          ; [PC, #0x02C0] [0x080038E8] 
+  0x08003628:  42B3         CMP        R3, R6
+  0x0800362A:  DA05         BGE        .L194                    ; 0x08003638
+  0x0800362C:  1C5E         ADDS       R6, R3, #1
+  0x0800362E:  6016         STR        R6, [R2]
+  0x08003630:  4EAD         LDR        R6, =0x00001388          ; [PC, #0x02B4] [0x080038E8] 
+  0x08003632:  1E76         SUBS       R6, R6, #1
+  0x08003634:  42B3         CMP        R3, R6
+  0x08003636:  D103         BNE        .L195                    ; 0x08003640
+
.L194:
+  0x08003638:  2300         MOVS       R3, #0
+  0x0800363A:  6013         STR        R3, [R2]
+  0x0800363C:  4AAB         LDR        R2, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x02AC] [0x080038EC] =0x20000768 
+  0x0800363E:  7015         STRB       R5, [R2]
+
.L195:
+  0x08003640:  4AA7         LDR        R2, =uwTick              ; [PC, #0x029C] [0x080038E0] =0x2000068C 
+  0x08003642:  6812         LDR        R2, [R2]
+  0x08003644:  600A         STR        R2, [R1]
+
.L196:
+  0x08003646:  49A4         LDR        R1, =0x50000010          ; [PC, #0x0290] [0x080038D8] 
+  0x08003648:  6809         LDR        R1, [R1]
+  0x0800364A:  07C9         LSLS       R1, R1, #31
+  0x0800364C:  D108         BNE        .L197                    ; 0x08003660
+  0x0800364E:  49A2         LDR        R1, =0x50000010          ; [PC, #0x0288] [0x080038D8] 
+  0x08003650:  6809         LDR        R1, [R1]
+  0x08003652:  0789         LSLS       R1, R1, #30
+  0x08003654:  D404         BMI        .L197                    ; 0x08003660
+  0x08003656:  49A3         LDR        R1, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x028C] [0x080038E4] =0x2000072C 
+  0x08003658:  2200         MOVS       R2, #0
+  0x0800365A:  600A         STR        R2, [R1]
+  0x0800365C:  49A3         LDR        R1, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x028C] [0x080038EC] =0x20000768 
+  0x0800365E:  700A         STRB       R2, [R1]
+
.L197:
+  0x08003660:  990F         LDR        R1, [SP, #60]
+  0x08003662:  4008         ANDS       R0, R1
+  0x08003664:  D135         BNE        .L198                    ; 0x080036D2
+  0x08003666:  4A81         LDR        R2, =0x50000410          ; [PC, #0x0204] [0x0800386C] 
+  0x08003668:  981B         LDR        R0, [SP, #108]
+  0x0800366A:  6190         STR        R0, [R2, #24]
+  0x0800366C:  981A         LDR        R0, [SP, #104]
+  0x0800366E:  6090         STR        R0, [R2, #8]
+  0x08003670:  497F         LDR        R1, =relaisState         ; [PC, #0x01FC] [0x08003870] =0x20000730 
+  0x08003672:  2000         MOVS       R0, #0
+  0x08003674:  7008         STRB       R0, [R1]
+  0x08003676:  497F         LDR        R1, =onTimeCounterRESET  ; [PC, #0x01FC] [0x08003874] =0x200006A0 
+  0x08003678:  9B16         LDR        R3, [SP, #88]
+  0x0800367A:  600B         STR        R3, [R1]
+  0x0800367C:  9920         LDR        R1, [SP, #128]
+  0x0800367E:  6091         STR        R1, [R2, #8]
+  0x08003680:  9910         LDR        R1, [SP, #64]
+  0x08003682:  31F4         ADDS       R1, #244
+  0x08003684:  4A7E         LDR        R2, =onTimeCounter       ; [PC, #0x01F8] [0x08003880] =0x200006A8 
+  0x08003686:  6011         STR        R1, [R2]
+  0x08003688:  4A7E         LDR        R2, =0x50000818          ; [PC, #0x01F8] [0x08003884] 
+  0x0800368A:  991F         LDR        R1, [SP, #124]
+  0x0800368C:  6111         STR        R1, [R2, #16]
+  0x0800368E:  497E         LDR        R1, =offTimeCounterGN    ; [PC, #0x01F8] [0x08003888] =0x200006B4 
+  0x08003690:  6008         STR        R0, [R1]
+  0x08003692:  497E         LDR        R1, =blinkModeGN         ; [PC, #0x01F8] [0x0800388C] =0x20000758 
+  0x08003694:  7008         STRB       R0, [R1]
+  0x08003696:  497E         LDR        R1, =onTimeCounterGN     ; [PC, #0x01F8] [0x08003890] =0x200006A4 
+  0x08003698:  6008         STR        R0, [R1]
+  0x0800369A:  498A         LDR        R1, =onTimeRT            ; [PC, #0x0228] [0x080038C4] =0x2000073C 
+  0x0800369C:  700D         STRB       R5, [R1]
+  0x0800369E:  498A         LDR        R1, =offTimeRT           ; [PC, #0x0228] [0x080038C8] =0x20000748 
+  0x080036A0:  700D         STRB       R5, [R1]
+  0x080036A2:  497D         LDR        R1, =blinkModeRT         ; [PC, #0x01F4] [0x08003898] =0x20000754 
+  0x080036A4:  700D         STRB       R5, [R1]
+  0x080036A6:  4989         LDR        R1, =numberOfBlinks      ; [PC, #0x0224] [0x080038CC] =0x200006BC 
+  0x080036A8:  2603         MOVS       R6, #3
+  0x080036AA:  600E         STR        R6, [R1]
+  0x080036AC:  4988         LDR        R1, =blinkCounter        ; [PC, #0x0220] [0x080038D0] =0x200006EC 
+  0x080036AE:  600E         STR        R6, [R1]
+  0x080036B0:  4988         LDR        R1, =pauseTime           ; [PC, #0x0220] [0x080038D4] =0x20000734 
+  0x080036B2:  700D         STRB       R5, [R1]
+  0x080036B4:  991E         LDR        R1, [SP, #120]
+  0x080036B6:  6011         STR        R1, [R2]
+  0x080036B8:  496B         LDR        R1, =buttonState         ; [PC, #0x01AC] [0x08003868] =0x2000073A 
+  0x080036BA:  7008         STRB       R0, [R1]
+  0x080036BC:  4877         LDR        R0, =onTimeCounterRT     ; [PC, #0x01DC] [0x0800389C] =0x2000069C 
+  0x080036BE:  21C8         MOVS       R1, #200
+  0x080036C0:  6001         STR        R1, [R0]
+  0x080036C2:  488B         LDR        R0, =0x08006990          ; [PC, #0x022C] [0x080038F0] 
+  0x080036C4:  F001 FD96    BL         puts                     ; 0x080051F4
+  0x080036C8:  488A         LDR        R0, =0x080066B4          ; [PC, #0x0228] [0x080038F4] 
+  0x080036CA:  F001 FD93    BL         puts                     ; 0x080051F4
+  0x080036CE:  487A         LDR        R0, =smState.122         ; [PC, #0x01E8] [0x080038B8] =0x20000736 
+  0x080036D0:  7006         STRB       R6, [R0]
+
.L198:
+  0x080036D2:  4889         LDR        R0, =temp                ; [PC, #0x0224] [0x080038F8] =0x20000690 
+  0x080036D4:  6800         LDR        R0, [R0]
+  0x080036D6:  2851         CMP        R0, #81
+  0x080036D8:  DB33         BLT        .L199                    ; 0x08003742
+  0x080036DA:  4A64         LDR        R2, =0x50000410          ; [PC, #0x0190] [0x0800386C] 
+  0x080036DC:  981B         LDR        R0, [SP, #108]
+  0x080036DE:  6190         STR        R0, [R2, #24]
+  0x080036E0:  981A         LDR        R0, [SP, #104]
+  0x080036E2:  6090         STR        R0, [R2, #8]
+  0x080036E4:  4962         LDR        R1, =relaisState         ; [PC, #0x0188] [0x08003870] =0x20000730 
+  0x080036E6:  2000         MOVS       R0, #0
+  0x080036E8:  7008         STRB       R0, [R1]
+  0x080036EA:  4962         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0188] [0x08003874] =0x200006A0 
+  0x080036EC:  9B16         LDR        R3, [SP, #88]
+  0x080036EE:  600B         STR        R3, [R1]
+  0x080036F0:  9920         LDR        R1, [SP, #128]
+  0x080036F2:  6091         STR        R1, [R2, #8]
+  0x080036F4:  9910         LDR        R1, [SP, #64]
+  0x080036F6:  31F4         ADDS       R1, #244
+  0x080036F8:  4A61         LDR        R2, =onTimeCounter       ; [PC, #0x0184] [0x08003880] =0x200006A8 
+  0x080036FA:  6011         STR        R1, [R2]
+  0x080036FC:  4B61         LDR        R3, =0x50000818          ; [PC, #0x0184] [0x08003884] 
+  0x080036FE:  991F         LDR        R1, [SP, #124]
+  0x08003700:  6119         STR        R1, [R3, #16]
+  0x08003702:  4961         LDR        R1, =offTimeCounterGN    ; [PC, #0x0184] [0x08003888] =0x200006B4 
+  0x08003704:  6008         STR        R0, [R1]
+  0x08003706:  4961         LDR        R1, =blinkModeGN         ; [PC, #0x0184] [0x0800388C] =0x20000758 
+  0x08003708:  7008         STRB       R0, [R1]
+  0x0800370A:  4961         LDR        R1, =onTimeCounterGN     ; [PC, #0x0184] [0x08003890] =0x200006A4 
+  0x0800370C:  6008         STR        R0, [R1]
+  0x0800370E:  496D         LDR        R1, =onTimeRT            ; [PC, #0x01B4] [0x080038C4] =0x2000073C 
+  0x08003710:  700D         STRB       R5, [R1]
+  0x08003712:  496D         LDR        R1, =offTimeRT           ; [PC, #0x01B4] [0x080038C8] =0x20000748 
+  0x08003714:  700D         STRB       R5, [R1]
+  0x08003716:  4960         LDR        R1, =blinkModeRT         ; [PC, #0x0180] [0x08003898] =0x20000754 
+  0x08003718:  700D         STRB       R5, [R1]
+  0x0800371A:  496C         LDR        R1, =numberOfBlinks      ; [PC, #0x01B0] [0x080038CC] =0x200006BC 
+  0x0800371C:  2205         MOVS       R2, #5
+  0x0800371E:  600A         STR        R2, [R1]
+  0x08003720:  496B         LDR        R1, =blinkCounter        ; [PC, #0x01AC] [0x080038D0] =0x200006EC 
+  0x08003722:  600A         STR        R2, [R1]
+  0x08003724:  496B         LDR        R1, =pauseTime           ; [PC, #0x01AC] [0x080038D4] =0x20000734 
+  0x08003726:  700D         STRB       R5, [R1]
+  0x08003728:  991E         LDR        R1, [SP, #120]
+  0x0800372A:  6019         STR        R1, [R3]
+  0x0800372C:  494E         LDR        R1, =buttonState         ; [PC, #0x0138] [0x08003868] =0x2000073A 
+  0x0800372E:  7008         STRB       R0, [R1]
+  0x08003730:  485A         LDR        R0, =onTimeCounterRT     ; [PC, #0x0168] [0x0800389C] =0x2000069C 
+  0x08003732:  21C8         MOVS       R1, #200
+  0x08003734:  6001         STR        R1, [R0]
+  0x08003736:  4871         LDR        R0, =0x08006330          ; [PC, #0x01C4] [0x080038FC] 
+  0x08003738:  F001 FD5C    BL         puts                     ; 0x080051F4
+  0x0800373C:  2003         MOVS       R0, #3
+  0x0800373E:  495E         LDR        R1, =smState.122         ; [PC, #0x0178] [0x080038B8] =0x20000736 
+  0x08003740:  7008         STRB       R0, [R1]
+
.L199:
+  0x08003742:  486A         LDR        R0, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x01A8] [0x080038EC] =0x20000768 
+  0x08003744:  4E4A         LDR        R6, =relaisState         ; [PC, #0x0128] [0x08003870] =0x20000730 
+  0x08003746:  7800         LDRB       R0, [R0]
+  0x08003748:  2801         CMP        R0, #1
+  0x0800374A:  7830         LDRB       R0, [R6]
+  0x0800374C:  D137         BNE        .L200                    ; 0x080037BE
+  0x0800374E:  2800         CMP        R0, #0
+  0x08003750:  D05B         BEQ        .L201                    ; 0x0800380A
+  0x08003752:  4A46         LDR        R2, =0x50000410          ; [PC, #0x0118] [0x0800386C] 
+  0x08003754:  981B         LDR        R0, [SP, #108]
+  0x08003756:  6190         STR        R0, [R2, #24]
+  0x08003758:  981A         LDR        R0, [SP, #104]
+  0x0800375A:  6090         STR        R0, [R2, #8]
+  0x0800375C:  2000         MOVS       R0, #0
+  0x0800375E:  7030         STRB       R0, [R6]
+  0x08003760:  4944         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0110] [0x08003874] =0x200006A0 
+  0x08003762:  9B16         LDR        R3, [SP, #88]
+  0x08003764:  600B         STR        R3, [R1]
+  0x08003766:  9920         LDR        R1, [SP, #128]
+  0x08003768:  6091         STR        R1, [R2, #8]
+  0x0800376A:  9910         LDR        R1, [SP, #64]
+  0x0800376C:  31F4         ADDS       R1, #244
+  0x0800376E:  4A44         LDR        R2, =onTimeCounter       ; [PC, #0x0110] [0x08003880] =0x200006A8 
+  0x08003770:  6011         STR        R1, [R2]
+  0x08003772:  4A44         LDR        R2, =0x50000818          ; [PC, #0x0110] [0x08003884] 
+  0x08003774:  991F         LDR        R1, [SP, #124]
+  0x08003776:  6111         STR        R1, [R2, #16]
+  0x08003778:  4943         LDR        R1, =offTimeCounterGN    ; [PC, #0x010C] [0x08003888] =0x200006B4 
+  0x0800377A:  6008         STR        R0, [R1]
+  0x0800377C:  4943         LDR        R1, =blinkModeGN         ; [PC, #0x010C] [0x0800388C] =0x20000758 
+  0x0800377E:  7008         STRB       R0, [R1]
+  0x08003780:  4943         LDR        R1, =onTimeCounterGN     ; [PC, #0x010C] [0x08003890] =0x200006A4 
+  0x08003782:  6008         STR        R0, [R1]
+  0x08003784:  484F         LDR        R0, =onTimeRT            ; [PC, #0x013C] [0x080038C4] =0x2000073C 
+  0x08003786:  7005         STRB       R5, [R0]
+  0x08003788:  484F         LDR        R0, =offTimeRT           ; [PC, #0x013C] [0x080038C8] =0x20000748 
+  0x0800378A:  7005         STRB       R5, [R0]
+  0x0800378C:  4842         LDR        R0, =blinkModeRT         ; [PC, #0x0108] [0x08003898] =0x20000754 
+  0x0800378E:  7005         STRB       R5, [R0]
+  0x08003790:  484E         LDR        R0, =numberOfBlinks      ; [PC, #0x0138] [0x080038CC] =0x200006BC 
+  0x08003792:  2102         MOVS       R1, #2
+  0x08003794:  6001         STR        R1, [R0]
+  0x08003796:  484E         LDR        R0, =blinkCounter        ; [PC, #0x0138] [0x080038D0] =0x200006EC 
+  0x08003798:  6001         STR        R1, [R0]
+  0x0800379A:  484E         LDR        R0, =pauseTime           ; [PC, #0x0138] [0x080038D4] =0x20000734 
+  0x0800379C:  7005         STRB       R5, [R0]
+  0x0800379E:  981E         LDR        R0, [SP, #120]
+  0x080037A0:  6010         STR        R0, [R2]
+  0x080037A2:  483E         LDR        R0, =onTimeCounterRT     ; [PC, #248] [0x0800389C] =0x2000069C 
+  0x080037A4:  21C8         MOVS       R1, #200
+  0x080037A6:  6001         STR        R1, [R0]
+  0x080037A8:  4855         LDR        R0, =0x080068F0          ; [PC, #0x0154] [0x08003900] 
+  0x080037AA:  F001 FD23    BL         puts                     ; 0x080051F4
+  0x080037AE:  4855         LDR        R0, =0x08006299          ; [PC, #0x0154] [0x08003904] 
+  0x080037B0:  F001 FD20    BL         puts                     ; 0x080051F4
+  0x080037B4:  484D         LDR        R0, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #0x0134] [0x080038EC] =0x20000768 
+  0x080037B6:  7800         LDRB       R0, [R0]
+  0x080037B8:  2800         CMP        R0, #0
+  0x080037BA:  D126         BNE        .L201                    ; 0x0800380A
+  0x080037BC:  7830         LDRB       R0, [R6]
+
.L200:
+  0x080037BE:  2800         CMP        R0, #0
+  0x080037C0:  D123         BNE        .L201                    ; 0x0800380A
+  0x080037C2:  492A         LDR        R1, =0x50000410          ; [PC, #168] [0x0800386C] 
+  0x080037C4:  981A         LDR        R0, [SP, #104]
+  0x080037C6:  6188         STR        R0, [R1, #24]
+  0x080037C8:  981B         LDR        R0, [SP, #108]
+  0x080037CA:  6088         STR        R0, [R1, #8]
+  0x080037CC:  7035         STRB       R5, [R6]
+  0x080037CE:  4836         LDR        R0, =onTimeCounterSET    ; [PC, #216] [0x080038A8] =0x20000698 
+  0x080037D0:  9A16         LDR        R2, [SP, #88]
+  0x080037D2:  6002         STR        R2, [R0]
+  0x080037D4:  9820         LDR        R0, [SP, #128]
+  0x080037D6:  6088         STR        R0, [R1, #8]
+  0x080037D8:  4829         LDR        R0, =onTimeCounter       ; [PC, #164] [0x08003880] =0x200006A8 
+  0x080037DA:  21C8         MOVS       R1, #200
+  0x080037DC:  6001         STR        R1, [R0]
+  0x080037DE:  4B29         LDR        R3, =0x50000818          ; [PC, #164] [0x08003884] 
+  0x080037E0:  9F1F         LDR        R7, [SP, #124]
+  0x080037E2:  611F         STR        R7, [R3, #16]
+  0x080037E4:  4831         LDR        R0, =onTimeGN            ; [PC, #196] [0x080038AC] =0x20000740 
+  0x080037E6:  7005         STRB       R5, [R0]
+  0x080037E8:  4827         LDR        R0, =offTimeCounterGN    ; [PC, #156] [0x08003888] =0x200006B4 
+  0x080037EA:  2200         MOVS       R2, #0
+  0x080037EC:  6002         STR        R2, [R0]
+  0x080037EE:  4830         LDR        R0, =offTimeGN           ; [PC, #192] [0x080038B0] =0x2000074C 
+  0x080037F0:  7005         STRB       R5, [R0]
+  0x080037F2:  4826         LDR        R0, =blinkModeGN         ; [PC, #152] [0x0800388C] =0x20000758 
+  0x080037F4:  7005         STRB       R5, [R0]
+  0x080037F6:  601F         STR        R7, [R3]
+  0x080037F8:  4627         MOV        R7, R4
+  0x080037FA:  4825         LDR        R0, =onTimeCounterGN     ; [PC, #148] [0x08003890] =0x200006A4 
+  0x080037FC:  6001         STR        R1, [R0]
+  0x080037FE:  4842         LDR        R0, =0x08006900          ; [PC, #0x0108] [0x08003908] 
+  0x08003800:  F001 FCF8    BL         puts                     ; 0x080051F4
+  0x08003804:  4841         LDR        R0, =0x080064A1          ; [PC, #0x0104] [0x0800390C] 
+  0x08003806:  F001 FCF5    BL         puts                     ; 0x080051F4
+
.L201:
+  0x0800380A:  4817         LDR        R0, =buttonState         ; [PC, #92] [0x08003868] =0x2000073A 
+  0x0800380C:  7800         LDRB       R0, [R0]
+  0x0800380E:  2800         CMP        R0, #0
+  0x08003810:  D001         BEQ        .L202                    ; 0x08003816
+  0x08003812:  F000 FC7F    BL         .L252                    ; 0x08004114
+
.L202:
+  0x08003816:  4915         LDR        R1, =0x50000410          ; [PC, #84] [0x0800386C] 
+  0x08003818:  981B         LDR        R0, [SP, #108]
+  0x0800381A:  6188         STR        R0, [R1, #24]
+  0x0800381C:  981A         LDR        R0, [SP, #104]
+  0x0800381E:  6088         STR        R0, [R1, #8]
+  0x08003820:  2700         MOVS       R7, #0
+  0x08003822:  7037         STRB       R7, [R6]
+  0x08003824:  4813         LDR        R0, =onTimeCounterRESET  ; [PC, #76] [0x08003874] =0x200006A0 
+  0x08003826:  9A16         LDR        R2, [SP, #88]
+  0x08003828:  6002         STR        R2, [R0]
+  0x0800382A:  9820         LDR        R0, [SP, #128]
+  0x0800382C:  6088         STR        R0, [R1, #8]
+  0x0800382E:  4814         LDR        R0, =onTimeCounter       ; [PC, #80] [0x08003880] =0x200006A8 
+  0x08003830:  21C8         MOVS       R1, #200
+  0x08003832:  6001         STR        R1, [R0]
+  0x08003834:  4913         LDR        R1, =0x50000818          ; [PC, #76] [0x08003884] 
+  0x08003836:  981F         LDR        R0, [SP, #124]
+  0x08003838:  6108         STR        R0, [R1, #16]
+  0x0800383A:  4813         LDR        R0, =offTimeCounterGN    ; [PC, #76] [0x08003888] =0x200006B4 
+  0x0800383C:  6007         STR        R7, [R0]
+  0x0800383E:  4813         LDR        R0, =blinkModeGN         ; [PC, #76] [0x0800388C] =0x20000758 
+  0x08003840:  7007         STRB       R7, [R0]
+  0x08003842:  4813         LDR        R0, =onTimeCounterGN     ; [PC, #76] [0x08003890] =0x200006A4 
+  0x08003844:  6007         STR        R7, [R0]
+  0x08003846:  981E         LDR        R0, [SP, #120]
+  0x08003848:  6108         STR        R0, [R1, #16]
+  0x0800384A:  4812         LDR        R0, =offTimeCounterRT    ; [PC, #72] [0x08003894] =0x200006B0 
+  0x0800384C:  6007         STR        R7, [R0]
+  0x0800384E:  4812         LDR        R0, =blinkModeRT         ; [PC, #72] [0x08003898] =0x20000754 
+  0x08003850:  7007         STRB       R7, [R0]
+  0x08003852:  4812         LDR        R0, =onTimeCounterRT     ; [PC, #72] [0x0800389C] =0x2000069C 
+  0x08003854:  6007         STR        R7, [R0]
+  0x08003856:  482E         LDR        R0, =0x080062C0          ; [PC, #184] [0x08003910] 
+  0x08003858:  F001 FCCC    BL         puts                     ; 0x080051F4
+  0x0800385C:  4816         LDR        R0, =smState.122         ; [PC, #88] [0x080038B8] =0x20000736 
+  0x0800385E:  7007         STRB       R7, [R0]
+  0x08003860:  4820         LDR        R0, =LVP_OVP_SM_On.lvpAndOvpInputTimeCounter ; [PC, #128] [0x080038E4] =0x2000072C 
+  0x08003862:  6007         STR        R7, [R0]
+  0x08003864:  4821         LDR        R0, =LVP_OVP_SM_On.lvpOROvpInput ; [PC, #132] [0x080038EC] =0x20000768 
+  0x08003866:  E182         B          .L213                    ; 0x08003B6E
+  0x08003868:  2000073A     DC.W       buttonState
+  0x0800386C:  50000410     DC.W       0x50000410
+  0x08003870:  20000730     DC.W       relaisState
+  0x08003874:  200006A0     DC.W       onTimeCounterRESET
+  0x08003878:  200006B8     DC.W       offTimeCounter
+  0x0800387C:  2000075C     DC.W       alarmMode
+  0x08003880:  200006A8     DC.W       onTimeCounter
+  0x08003884:  50000818     DC.W       0x50000818
+  0x08003888:  200006B4     DC.W       offTimeCounterGN
+  0x0800388C:  20000758     DC.W       blinkModeGN
+  0x08003890:  200006A4     DC.W       onTimeCounterGN
+  0x08003894:  200006B0     DC.W       offTimeCounterRT
+  0x08003898:  20000754     DC.W       blinkModeRT
+  0x0800389C:  2000069C     DC.W       onTimeCounterRT
+  0x080038A0:  08006286     DC.W       08006286               ; R_ARM_ABS32
+  0x080038A4:  20000737     DC.W       smState
+  0x080038A8:  20000698     DC.W       onTimeCounterSET
+  0x080038AC:  20000740     DC.W       onTimeGN
+  0x080038B0:  2000074C     DC.W       offTimeGN
+  0x080038B4:  080064C7     DC.W       080064C7               ; R_ARM_ABS32
+  0x080038B8:  20000736     DC.W       smState.122
+  0x080038BC:  20000744     DC.W       onTime
+  0x080038C0:  20000750     DC.W       offTime
+  0x080038C4:  2000073C     DC.W       onTimeRT
+  0x080038C8:  20000748     DC.W       offTimeRT
+  0x080038CC:  200006BC     DC.W       numberOfBlinks
+  0x080038D0:  200006EC     DC.W       blinkCounter
+  0x080038D4:  20000734     DC.W       pauseTime
+  0x080038D8:  50000010     DC.W       0x50000010
+  0x080038DC:  20000728     DC.W       LVP_OVP_SM_On.oldtime
+  0x080038E0:  2000068C     DC.W       uwTick
+  0x080038E4:  2000072C     DC.W       LVP_OVP_SM_On.lvpAndOvpInputTimeCounter
+  0x080038E8:  00001388     DC.W       0x00001388
+  0x080038EC:  20000768     DC.W       LVP_OVP_SM_On.lvpOROvpInput
+  0x080038F0:  08006990     DC.W       08006990               ; R_ARM_ABS32
+  0x080038F4:  080066B4     DC.W       080066B4               ; R_ARM_ABS32
+  0x080038F8:  20000690     DC.W       temp
+  0x080038FC:  08006330     DC.W       08006330               ; R_ARM_ABS32
+  0x08003900:  080068F0     DC.W       080068F0               ; R_ARM_ABS32
+  0x08003904:  08006299     DC.W       08006299               ; R_ARM_ABS32
+  0x08003908:  08006900     DC.W       08006900               ; R_ARM_ABS32
+  0x0800390C:  080064A1     DC.W       080064A1               ; R_ARM_ABS32
+  0x08003910:  080062C0     DC.W       080062C0               ; R_ARM_ABS32
+  0x08003914:  48ED         LDR        R0, =0x50000410          ; [PC, #0x03B4] [0x08003CCC] 
+  0x08003916:  6800         LDR        R0, [R0]
+  0x08003918:  49ED         LDR        R1, =0x50000010          ; [PC, #0x03B4] [0x08003CD0] 
+  0x0800391A:  6809         LDR        R1, [R1]
+  0x0800391C:  07C9         LSLS       R1, R1, #31
+  0x0800391E:  D103         BNE        .L203                    ; 0x08003928
+  0x08003920:  49EB         LDR        R1, =0x50000010          ; [PC, #0x03AC] [0x08003CD0] 
+  0x08003922:  6809         LDR        R1, [R1]
+  0x08003924:  0789         LSLS       R1, R1, #30
+  0x08003926:  D517         BPL        .L206                    ; 0x08003958
+
.L203:
+  0x08003928:  49EA         LDR        R1, =LVP_SM_On.oldtime   ; [PC, #0x03A8] [0x08003CD4] =0x20000720 
+  0x0800392A:  680A         LDR        R2, [R1]
+  0x0800392C:  4BEA         LDR        R3, =uwTick              ; [PC, #0x03A8] [0x08003CD8] =0x2000068C 
+  0x0800392E:  681B         LDR        R3, [R3]
+  0x08003930:  4293         CMP        R3, R2
+  0x08003932:  D011         BEQ        .L206                    ; 0x08003958
+  0x08003934:  4AE9         LDR        R2, =LVP_SM_On.lvpTimeCounter ; [PC, #0x03A4] [0x08003CDC] =0x20000724 
+  0x08003936:  6813         LDR        R3, [R2]
+  0x08003938:  4EE9         LDR        R6, =0x00001388          ; [PC, #0x03A4] [0x08003CE0] 
+  0x0800393A:  42B3         CMP        R3, R6
+  0x0800393C:  DA05         BGE        .L204                    ; 0x0800394A
+  0x0800393E:  1C5E         ADDS       R6, R3, #1
+  0x08003940:  6016         STR        R6, [R2]
+  0x08003942:  4EE7         LDR        R6, =0x00001388          ; [PC, #0x039C] [0x08003CE0] 
+  0x08003944:  1E76         SUBS       R6, R6, #1
+  0x08003946:  42B3         CMP        R3, R6
+  0x08003948:  D103         BNE        .L205                    ; 0x08003952
+
.L204:
+  0x0800394A:  2300         MOVS       R3, #0
+  0x0800394C:  6013         STR        R3, [R2]
+  0x0800394E:  4AE5         LDR        R2, =LVP_SM_On.lvpInput  ; [PC, #0x0394] [0x08003CE4] =0x20000764 
+  0x08003950:  7015         STRB       R5, [R2]
+
.L205:
+  0x08003952:  4AE1         LDR        R2, =uwTick              ; [PC, #0x0384] [0x08003CD8] =0x2000068C 
+  0x08003954:  6812         LDR        R2, [R2]
+  0x08003956:  600A         STR        R2, [R1]
+
.L206:
+  0x08003958:  49DD         LDR        R1, =0x50000010          ; [PC, #0x0374] [0x08003CD0] 
+  0x0800395A:  6809         LDR        R1, [R1]
+  0x0800395C:  07C9         LSLS       R1, R1, #31
+  0x0800395E:  D104         BNE        .L207                    ; 0x0800396A
+  0x08003960:  49DE         LDR        R1, =LVP_SM_On.lvpTimeCounter ; [PC, #0x0378] [0x08003CDC] =0x20000724 
+  0x08003962:  2200         MOVS       R2, #0
+  0x08003964:  600A         STR        R2, [R1]
+  0x08003966:  49DF         LDR        R1, =LVP_SM_On.lvpInput  ; [PC, #0x037C] [0x08003CE4] =0x20000764 
+  0x08003968:  700A         STRB       R2, [R1]
+
.L207:
+  0x0800396A:  990F         LDR        R1, [SP, #60]
+  0x0800396C:  4008         ANDS       R0, R1
+  0x0800396E:  D135         BNE        .L208                    ; 0x080039DC
+  0x08003970:  4AD6         LDR        R2, =0x50000410          ; [PC, #0x0358] [0x08003CCC] 
+  0x08003972:  981B         LDR        R0, [SP, #108]
+  0x08003974:  6190         STR        R0, [R2, #24]
+  0x08003976:  981A         LDR        R0, [SP, #104]
+  0x08003978:  6090         STR        R0, [R2, #8]
+  0x0800397A:  49DB         LDR        R1, =relaisState         ; [PC, #0x036C] [0x08003CE8] =0x20000730 
+  0x0800397C:  2000         MOVS       R0, #0
+  0x0800397E:  7008         STRB       R0, [R1]
+  0x08003980:  49DA         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0368] [0x08003CEC] =0x200006A0 
+  0x08003982:  9B16         LDR        R3, [SP, #88]
+  0x08003984:  600B         STR        R3, [R1]
+  0x08003986:  9920         LDR        R1, [SP, #128]
+  0x08003988:  6091         STR        R1, [R2, #8]
+  0x0800398A:  9910         LDR        R1, [SP, #64]
+  0x0800398C:  31F4         ADDS       R1, #244
+  0x0800398E:  4AD8         LDR        R2, =onTimeCounter       ; [PC, #0x0360] [0x08003CF0] =0x200006A8 
+  0x08003990:  6011         STR        R1, [R2]
+  0x08003992:  4AD8         LDR        R2, =0x50000818          ; [PC, #0x0360] [0x08003CF4] 
+  0x08003994:  991F         LDR        R1, [SP, #124]
+  0x08003996:  6111         STR        R1, [R2, #16]
+  0x08003998:  49D7         LDR        R1, =offTimeCounterGN    ; [PC, #0x035C] [0x08003CF8] =0x200006B4 
+  0x0800399A:  6008         STR        R0, [R1]
+  0x0800399C:  49D7         LDR        R1, =blinkModeGN         ; [PC, #0x035C] [0x08003CFC] =0x20000758 
+  0x0800399E:  7008         STRB       R0, [R1]
+  0x080039A0:  49D7         LDR        R1, =onTimeCounterGN     ; [PC, #0x035C] [0x08003D00] =0x200006A4 
+  0x080039A2:  6008         STR        R0, [R1]
+  0x080039A4:  49D7         LDR        R1, =onTimeRT            ; [PC, #0x035C] [0x08003D04] =0x2000073C 
+  0x080039A6:  700D         STRB       R5, [R1]
+  0x080039A8:  49D7         LDR        R1, =offTimeRT           ; [PC, #0x035C] [0x08003D08] =0x20000748 
+  0x080039AA:  700D         STRB       R5, [R1]
+  0x080039AC:  49D7         LDR        R1, =blinkModeRT         ; [PC, #0x035C] [0x08003D0C] =0x20000754 
+  0x080039AE:  700D         STRB       R5, [R1]
+  0x080039B0:  49D7         LDR        R1, =numberOfBlinks      ; [PC, #0x035C] [0x08003D10] =0x200006BC 
+  0x080039B2:  2603         MOVS       R6, #3
+  0x080039B4:  600E         STR        R6, [R1]
+  0x080039B6:  49D7         LDR        R1, =blinkCounter        ; [PC, #0x035C] [0x08003D14] =0x200006EC 
+  0x080039B8:  600E         STR        R6, [R1]
+  0x080039BA:  49D7         LDR        R1, =pauseTime           ; [PC, #0x035C] [0x08003D18] =0x20000734 
+  0x080039BC:  700D         STRB       R5, [R1]
+  0x080039BE:  991E         LDR        R1, [SP, #120]
+  0x080039C0:  6011         STR        R1, [R2]
+  0x080039C2:  49D6         LDR        R1, =buttonState         ; [PC, #0x0358] [0x08003D1C] =0x2000073A 
+  0x080039C4:  7008         STRB       R0, [R1]
+  0x080039C6:  48D6         LDR        R0, =onTimeCounterRT     ; [PC, #0x0358] [0x08003D20] =0x2000069C 
+  0x080039C8:  21C8         MOVS       R1, #200
+  0x080039CA:  6001         STR        R1, [R0]
+  0x080039CC:  48D5         LDR        R0, =0x08006990          ; [PC, #0x0354] [0x08003D24] 
+  0x080039CE:  F001 FC11    BL         puts                     ; 0x080051F4
+  0x080039D2:  48D5         LDR        R0, =0x08006648          ; [PC, #0x0354] [0x08003D28] 
+  0x080039D4:  F001 FC0E    BL         puts                     ; 0x080051F4
+  0x080039D8:  48D4         LDR        R0, =smState             ; [PC, #0x0350] [0x08003D2C] =0x20000737 
+  0x080039DA:  7006         STRB       R6, [R0]
+
.L208:
+  0x080039DC:  48D4         LDR        R0, =temp                ; [PC, #0x0350] [0x08003D30] =0x20000690 
+  0x080039DE:  6800         LDR        R0, [R0]
+  0x080039E0:  2851         CMP        R0, #81
+  0x080039E2:  DB33         BLT        .L209                    ; 0x08003A4C
+  0x080039E4:  4AB9         LDR        R2, =0x50000410          ; [PC, #0x02E4] [0x08003CCC] 
+  0x080039E6:  981B         LDR        R0, [SP, #108]
+  0x080039E8:  6190         STR        R0, [R2, #24]
+  0x080039EA:  981A         LDR        R0, [SP, #104]
+  0x080039EC:  6090         STR        R0, [R2, #8]
+  0x080039EE:  49BE         LDR        R1, =relaisState         ; [PC, #0x02F8] [0x08003CE8] =0x20000730 
+  0x080039F0:  2000         MOVS       R0, #0
+  0x080039F2:  7008         STRB       R0, [R1]
+  0x080039F4:  49BD         LDR        R1, =onTimeCounterRESET  ; [PC, #0x02F4] [0x08003CEC] =0x200006A0 
+  0x080039F6:  9B16         LDR        R3, [SP, #88]
+  0x080039F8:  600B         STR        R3, [R1]
+  0x080039FA:  9920         LDR        R1, [SP, #128]
+  0x080039FC:  6091         STR        R1, [R2, #8]
+  0x080039FE:  9910         LDR        R1, [SP, #64]
+  0x08003A00:  31F4         ADDS       R1, #244
+  0x08003A02:  4ABB         LDR        R2, =onTimeCounter       ; [PC, #0x02EC] [0x08003CF0] =0x200006A8 
+  0x08003A04:  6011         STR        R1, [R2]
+  0x08003A06:  4BBB         LDR        R3, =0x50000818          ; [PC, #0x02EC] [0x08003CF4] 
+  0x08003A08:  991F         LDR        R1, [SP, #124]
+  0x08003A0A:  6119         STR        R1, [R3, #16]
+  0x08003A0C:  49BA         LDR        R1, =offTimeCounterGN    ; [PC, #0x02E8] [0x08003CF8] =0x200006B4 
+  0x08003A0E:  6008         STR        R0, [R1]
+  0x08003A10:  49BA         LDR        R1, =blinkModeGN         ; [PC, #0x02E8] [0x08003CFC] =0x20000758 
+  0x08003A12:  7008         STRB       R0, [R1]
+  0x08003A14:  49BA         LDR        R1, =onTimeCounterGN     ; [PC, #0x02E8] [0x08003D00] =0x200006A4 
+  0x08003A16:  6008         STR        R0, [R1]
+  0x08003A18:  49BA         LDR        R1, =onTimeRT            ; [PC, #0x02E8] [0x08003D04] =0x2000073C 
+  0x08003A1A:  700D         STRB       R5, [R1]
+  0x08003A1C:  49BA         LDR        R1, =offTimeRT           ; [PC, #0x02E8] [0x08003D08] =0x20000748 
+  0x08003A1E:  700D         STRB       R5, [R1]
+  0x08003A20:  49BA         LDR        R1, =blinkModeRT         ; [PC, #0x02E8] [0x08003D0C] =0x20000754 
+  0x08003A22:  700D         STRB       R5, [R1]
+  0x08003A24:  49BA         LDR        R1, =numberOfBlinks      ; [PC, #0x02E8] [0x08003D10] =0x200006BC 
+  0x08003A26:  2205         MOVS       R2, #5
+  0x08003A28:  600A         STR        R2, [R1]
+  0x08003A2A:  49BA         LDR        R1, =blinkCounter        ; [PC, #0x02E8] [0x08003D14] =0x200006EC 
+  0x08003A2C:  600A         STR        R2, [R1]
+  0x08003A2E:  49BA         LDR        R1, =pauseTime           ; [PC, #0x02E8] [0x08003D18] =0x20000734 
+  0x08003A30:  700D         STRB       R5, [R1]
+  0x08003A32:  991E         LDR        R1, [SP, #120]
+  0x08003A34:  6019         STR        R1, [R3]
+  0x08003A36:  49B9         LDR        R1, =buttonState         ; [PC, #0x02E4] [0x08003D1C] =0x2000073A 
+  0x08003A38:  7008         STRB       R0, [R1]
+  0x08003A3A:  48B9         LDR        R0, =onTimeCounterRT     ; [PC, #0x02E4] [0x08003D20] =0x2000069C 
+  0x08003A3C:  21C8         MOVS       R1, #200
+  0x08003A3E:  6001         STR        R1, [R0]
+  0x08003A40:  48BC         LDR        R0, =0x08006330          ; [PC, #0x02F0] [0x08003D34] 
+  0x08003A42:  F001 FBD7    BL         puts                     ; 0x080051F4
+  0x08003A46:  2003         MOVS       R0, #3
+  0x08003A48:  49B8         LDR        R1, =smState             ; [PC, #0x02E0] [0x08003D2C] =0x20000737 
+  0x08003A4A:  7008         STRB       R0, [R1]
+
.L209:
+  0x08003A4C:  48A5         LDR        R0, =LVP_SM_On.lvpInput  ; [PC, #0x0294] [0x08003CE4] =0x20000764 
+  0x08003A4E:  4EA6         LDR        R6, =relaisState         ; [PC, #0x0298] [0x08003CE8] =0x20000730 
+  0x08003A50:  7800         LDRB       R0, [R0]
+  0x08003A52:  2801         CMP        R0, #1
+  0x08003A54:  7830         LDRB       R0, [R6]
+  0x08003A56:  D137         BNE        .L210                    ; 0x08003AC8
+  0x08003A58:  2800         CMP        R0, #0
+  0x08003A5A:  D05B         BEQ        .L211                    ; 0x08003B14
+  0x08003A5C:  4A9B         LDR        R2, =0x50000410          ; [PC, #0x026C] [0x08003CCC] 
+  0x08003A5E:  981B         LDR        R0, [SP, #108]
+  0x08003A60:  6190         STR        R0, [R2, #24]
+  0x08003A62:  981A         LDR        R0, [SP, #104]
+  0x08003A64:  6090         STR        R0, [R2, #8]
+  0x08003A66:  2000         MOVS       R0, #0
+  0x08003A68:  7030         STRB       R0, [R6]
+  0x08003A6A:  49A0         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0280] [0x08003CEC] =0x200006A0 
+  0x08003A6C:  9B16         LDR        R3, [SP, #88]
+  0x08003A6E:  600B         STR        R3, [R1]
+  0x08003A70:  9920         LDR        R1, [SP, #128]
+  0x08003A72:  6091         STR        R1, [R2, #8]
+  0x08003A74:  9910         LDR        R1, [SP, #64]
+  0x08003A76:  31F4         ADDS       R1, #244
+  0x08003A78:  4A9D         LDR        R2, =onTimeCounter       ; [PC, #0x0274] [0x08003CF0] =0x200006A8 
+  0x08003A7A:  6011         STR        R1, [R2]
+  0x08003A7C:  4A9D         LDR        R2, =0x50000818          ; [PC, #0x0274] [0x08003CF4] 
+  0x08003A7E:  991F         LDR        R1, [SP, #124]
+  0x08003A80:  6111         STR        R1, [R2, #16]
+  0x08003A82:  499D         LDR        R1, =offTimeCounterGN    ; [PC, #0x0274] [0x08003CF8] =0x200006B4 
+  0x08003A84:  6008         STR        R0, [R1]
+  0x08003A86:  499D         LDR        R1, =blinkModeGN         ; [PC, #0x0274] [0x08003CFC] =0x20000758 
+  0x08003A88:  7008         STRB       R0, [R1]
+  0x08003A8A:  499D         LDR        R1, =onTimeCounterGN     ; [PC, #0x0274] [0x08003D00] =0x200006A4 
+  0x08003A8C:  6008         STR        R0, [R1]
+  0x08003A8E:  489D         LDR        R0, =onTimeRT            ; [PC, #0x0274] [0x08003D04] =0x2000073C 
+  0x08003A90:  7005         STRB       R5, [R0]
+  0x08003A92:  489D         LDR        R0, =offTimeRT           ; [PC, #0x0274] [0x08003D08] =0x20000748 
+  0x08003A94:  7005         STRB       R5, [R0]
+  0x08003A96:  489D         LDR        R0, =blinkModeRT         ; [PC, #0x0274] [0x08003D0C] =0x20000754 
+  0x08003A98:  7005         STRB       R5, [R0]
+  0x08003A9A:  489D         LDR        R0, =numberOfBlinks      ; [PC, #0x0274] [0x08003D10] =0x200006BC 
+  0x08003A9C:  2102         MOVS       R1, #2
+  0x08003A9E:  6001         STR        R1, [R0]
+  0x08003AA0:  489C         LDR        R0, =blinkCounter        ; [PC, #0x0270] [0x08003D14] =0x200006EC 
+  0x08003AA2:  6001         STR        R1, [R0]
+  0x08003AA4:  489C         LDR        R0, =pauseTime           ; [PC, #0x0270] [0x08003D18] =0x20000734 
+  0x08003AA6:  7005         STRB       R5, [R0]
+  0x08003AA8:  981E         LDR        R0, [SP, #120]
+  0x08003AAA:  6010         STR        R0, [R2]
+  0x08003AAC:  489C         LDR        R0, =onTimeCounterRT     ; [PC, #0x0270] [0x08003D20] =0x2000069C 
+  0x08003AAE:  21C8         MOVS       R1, #200
+  0x08003AB0:  6001         STR        R1, [R0]
+  0x08003AB2:  48A1         LDR        R0, =0x0800665D          ; [PC, #0x0284] [0x08003D38] 
+  0x08003AB4:  F001 FB9E    BL         puts                     ; 0x080051F4
+  0x08003AB8:  48A0         LDR        R0, =0x08006263          ; [PC, #0x0280] [0x08003D3C] 
+  0x08003ABA:  F001 FB9B    BL         puts                     ; 0x080051F4
+  0x08003ABE:  4889         LDR        R0, =LVP_SM_On.lvpInput  ; [PC, #0x0224] [0x08003CE4] =0x20000764 
+  0x08003AC0:  7800         LDRB       R0, [R0]
+  0x08003AC2:  2800         CMP        R0, #0
+  0x08003AC4:  D126         BNE        .L211                    ; 0x08003B14
+  0x08003AC6:  7830         LDRB       R0, [R6]
+
.L210:
+  0x08003AC8:  2800         CMP        R0, #0
+  0x08003ACA:  D123         BNE        .L211                    ; 0x08003B14
+  0x08003ACC:  497F         LDR        R1, =0x50000410          ; [PC, #0x01FC] [0x08003CCC] 
+  0x08003ACE:  981A         LDR        R0, [SP, #104]
+  0x08003AD0:  6188         STR        R0, [R1, #24]
+  0x08003AD2:  981B         LDR        R0, [SP, #108]
+  0x08003AD4:  6088         STR        R0, [R1, #8]
+  0x08003AD6:  7035         STRB       R5, [R6]
+  0x08003AD8:  4899         LDR        R0, =onTimeCounterSET    ; [PC, #0x0264] [0x08003D40] =0x20000698 
+  0x08003ADA:  9A16         LDR        R2, [SP, #88]
+  0x08003ADC:  6002         STR        R2, [R0]
+  0x08003ADE:  9820         LDR        R0, [SP, #128]
+  0x08003AE0:  6088         STR        R0, [R1, #8]
+  0x08003AE2:  4883         LDR        R0, =onTimeCounter       ; [PC, #0x020C] [0x08003CF0] =0x200006A8 
+  0x08003AE4:  21C8         MOVS       R1, #200
+  0x08003AE6:  6001         STR        R1, [R0]
+  0x08003AE8:  4B82         LDR        R3, =0x50000818          ; [PC, #0x0208] [0x08003CF4] 
+  0x08003AEA:  9F1F         LDR        R7, [SP, #124]
+  0x08003AEC:  611F         STR        R7, [R3, #16]
+  0x08003AEE:  4895         LDR        R0, =onTimeGN            ; [PC, #0x0254] [0x08003D44] =0x20000740 
+  0x08003AF0:  7005         STRB       R5, [R0]
+  0x08003AF2:  4881         LDR        R0, =offTimeCounterGN    ; [PC, #0x0204] [0x08003CF8] =0x200006B4 
+  0x08003AF4:  2200         MOVS       R2, #0
+  0x08003AF6:  6002         STR        R2, [R0]
+  0x08003AF8:  4893         LDR        R0, =offTimeGN           ; [PC, #0x024C] [0x08003D48] =0x2000074C 
+  0x08003AFA:  7005         STRB       R5, [R0]
+  0x08003AFC:  487F         LDR        R0, =blinkModeGN         ; [PC, #0x01FC] [0x08003CFC] =0x20000758 
+  0x08003AFE:  7005         STRB       R5, [R0]
+  0x08003B00:  601F         STR        R7, [R3]
+  0x08003B02:  4627         MOV        R7, R4
+  0x08003B04:  487E         LDR        R0, =onTimeCounterGN     ; [PC, #0x01F8] [0x08003D00] =0x200006A4 
+  0x08003B06:  6001         STR        R1, [R0]
+  0x08003B08:  4890         LDR        R0, =0x080068E8          ; [PC, #0x0240] [0x08003D4C] 
+  0x08003B0A:  F001 FB73    BL         puts                     ; 0x080051F4
+  0x08003B0E:  4890         LDR        R0, =0x080064A1          ; [PC, #0x0240] [0x08003D50] 
+  0x08003B10:  F001 FB70    BL         puts                     ; 0x080051F4
+
.L211:
+  0x08003B14:  4881         LDR        R0, =buttonState         ; [PC, #0x0204] [0x08003D1C] =0x2000073A 
+  0x08003B16:  7800         LDRB       R0, [R0]
+  0x08003B18:  2800         CMP        R0, #0
+  0x08003B1A:  D000         BEQ        .L212                    ; 0x08003B1E
+  0x08003B1C:  E2FA         B          .L252                    ; 0x08004114
+
.L212:
+  0x08003B1E:  496B         LDR        R1, =0x50000410          ; [PC, #0x01AC] [0x08003CCC] 
+  0x08003B20:  981B         LDR        R0, [SP, #108]
+  0x08003B22:  6188         STR        R0, [R1, #24]
+  0x08003B24:  981A         LDR        R0, [SP, #104]
+  0x08003B26:  6088         STR        R0, [R1, #8]
+  0x08003B28:  2700         MOVS       R7, #0
+  0x08003B2A:  7037         STRB       R7, [R6]
+  0x08003B2C:  486F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01BC] [0x08003CEC] =0x200006A0 
+  0x08003B2E:  9A16         LDR        R2, [SP, #88]
+  0x08003B30:  6002         STR        R2, [R0]
+  0x08003B32:  9820         LDR        R0, [SP, #128]
+  0x08003B34:  6088         STR        R0, [R1, #8]
+  0x08003B36:  486E         LDR        R0, =onTimeCounter       ; [PC, #0x01B8] [0x08003CF0] =0x200006A8 
+  0x08003B38:  21C8         MOVS       R1, #200
+  0x08003B3A:  6001         STR        R1, [R0]
+  0x08003B3C:  496D         LDR        R1, =0x50000818          ; [PC, #0x01B4] [0x08003CF4] 
+  0x08003B3E:  981F         LDR        R0, [SP, #124]
+  0x08003B40:  6108         STR        R0, [R1, #16]
+  0x08003B42:  486D         LDR        R0, =offTimeCounterGN    ; [PC, #0x01B4] [0x08003CF8] =0x200006B4 
+  0x08003B44:  6007         STR        R7, [R0]
+  0x08003B46:  486D         LDR        R0, =blinkModeGN         ; [PC, #0x01B4] [0x08003CFC] =0x20000758 
+  0x08003B48:  7007         STRB       R7, [R0]
+  0x08003B4A:  486D         LDR        R0, =onTimeCounterGN     ; [PC, #0x01B4] [0x08003D00] =0x200006A4 
+  0x08003B4C:  6007         STR        R7, [R0]
+  0x08003B4E:  981E         LDR        R0, [SP, #120]
+  0x08003B50:  6108         STR        R0, [R1, #16]
+  0x08003B52:  4880         LDR        R0, =offTimeCounterRT    ; [PC, #0x0200] [0x08003D54] =0x200006B0 
+  0x08003B54:  6007         STR        R7, [R0]
+  0x08003B56:  486D         LDR        R0, =blinkModeRT         ; [PC, #0x01B4] [0x08003D0C] =0x20000754 
+  0x08003B58:  7007         STRB       R7, [R0]
+  0x08003B5A:  4871         LDR        R0, =onTimeCounterRT     ; [PC, #0x01C4] [0x08003D20] =0x2000069C 
+  0x08003B5C:  6007         STR        R7, [R0]
+  0x08003B5E:  487E         LDR        R0, =0x08006286          ; [PC, #0x01F8] [0x08003D58] 
+  0x08003B60:  F001 FB48    BL         puts                     ; 0x080051F4
+  0x08003B64:  4871         LDR        R0, =smState             ; [PC, #0x01C4] [0x08003D2C] =0x20000737 
+  0x08003B66:  7007         STRB       R7, [R0]
+  0x08003B68:  485C         LDR        R0, =LVP_SM_On.lvpTimeCounter ; [PC, #0x0170] [0x08003CDC] =0x20000724 
+  0x08003B6A:  6007         STR        R7, [R0]
+  0x08003B6C:  485D         LDR        R0, =LVP_SM_On.lvpInput  ; [PC, #0x0174] [0x08003CE4] =0x20000764 
+
.L213:
+  0x08003B6E:  7007         STRB       R7, [R0]
+  0x08003B70:  4F7A         LDR        R7, =0x000003C7          ; [PC, #0x01E8] [0x08003D5C] 
+  0x08003B72:  E2CF         B          .L252                    ; 0x08004114
+
.L214:
+  0x08003B74:  497A         LDR        R1, =sys_data            ; [PC, #0x01E8] [0x08003D60] =0x20000234 
+  0x08003B76:  8B09         LDRH       R1, [R1, #24]
+  0x08003B78:  2B00         CMP        R3, #0
+  0x08003B7A:  D001         BEQ        .L215                    ; 0x08003B80
+  0x08003B7C:  4299         CMP        R1, R3
+  0x08003B7E:  D112         BNE        .L218                    ; 0x08003BA6
+
.L215:
+  0x08003B80:  212A         MOVS       R1, #42
+  0x08003B82:  5C62         LDRB       R2, [R4, R1]
+  0x08003B84:  2129         MOVS       R1, #41
+  0x08003B86:  5C61         LDRB       R1, [R4, R1]
+  0x08003B88:  0209         LSLS       R1, R1, #8
+  0x08003B8A:  1889         ADDS       R1, R1, R2
+  0x08003B8C:  2970         CMP        R1, #112
+  0x08003B8E:  D200         BCS        .L216                    ; 0x08003B92
+  0x08003B90:  E343         B          .L260                    ; 0x0800421A
+
.L216:
+  0x08003B92:  2125         MOVS       R1, #37
+  0x08003B94:  00C9         LSLS       R1, R1, #3
+  0x08003B96:  4A73         LDR        R2, =0x00000286          ; [PC, #0x01CC] [0x08003D64] 
+  0x08003B98:  E022         B          .L222                    ; 0x08003BE0
+
.L217:
+  0x08003B9A:  4971         LDR        R1, =sys_data            ; [PC, #0x01C4] [0x08003D60] =0x20000234 
+  0x08003B9C:  8B09         LDRH       R1, [R1, #24]
+  0x08003B9E:  2B00         CMP        R3, #0
+  0x08003BA0:  D010         BEQ        .L220                    ; 0x08003BC4
+  0x08003BA2:  4299         CMP        R1, R3
+  0x08003BA4:  D00E         BEQ        .L220                    ; 0x08003BC4
+
.L218:
+  0x08003BA6:  2125         MOVS       R1, #37
+  0x08003BA8:  00C9         LSLS       R1, R1, #3
+  0x08003BAA:  4A6F         LDR        R2, =0x00000B86          ; [PC, #0x01BC] [0x08003D68] 
+  0x08003BAC:  E018         B          .L222                    ; 0x08003BE0
+
.L219:
+  0x08003BAE:  9913         LDR        R1, [SP, #76]
+  0x08003BB0:  312A         ADDS       R1, #42
+  0x08003BB2:  2301         MOVS       R3, #1
+  0x08003BB4:  5463         STRB       R3, [R4, R1]
+  0x08003BB6:  990A         LDR        R1, [SP, #40]
+  0x08003BB8:  404A         EORS       R2, R1
+  0x08003BBA:  2125         MOVS       R1, #37
+  0x08003BBC:  00C9         LSLS       R1, R1, #3
+  0x08003BBE:  5462         STRB       R2, [R4, R1]
+  0x08003BC0:  2603         MOVS       R6, #3
+  0x08003BC2:  E3BC         B          .L270                    ; 0x0800433E
+
.L220:
+  0x08003BC4:  9908         LDR        R1, [SP, #32]
+  0x08003BC6:  5C60         LDRB       R0, [R4, R1]
+  0x08003BC8:  222B         MOVS       R2, #43
+  0x08003BCA:  5CA2         LDRB       R2, [R4, R2]
+  0x08003BCC:  0212         LSLS       R2, R2, #8
+  0x08003BCE:  1816         ADDS       R6, R2, R0
+  0x08003BD0:  D002         BEQ        .L221                    ; 0x08003BD8
+  0x08003BD2:  2E7C         CMP        R6, #124
+  0x08003BD4:  D200         BCS        .L221                    ; 0x08003BD8
+  0x08003BD6:  E339         B          .L261                    ; 0x0800424C
+
.L221:
+  0x08003BD8:  2125         MOVS       R1, #37
+  0x08003BDA:  00C9         LSLS       R1, R1, #3
+  0x08003BDC:  2239         MOVS       R2, #57
+  0x08003BDE:  0112         LSLS       R2, R2, #4
+
.L222:
+  0x08003BE0:  5262         STRH       R2, [R4, R1]
+  0x08003BE2:  2603         MOVS       R6, #3
+  0x08003BE4:  E3AB         B          .L270                    ; 0x0800433E
+
.L223:
+  0x08003BE6:  9A08         LDR        R2, [SP, #32]
+  0x08003BE8:  5CA0         LDRB       R0, [R4, R2]
+  0x08003BEA:  222B         MOVS       R2, #43
+  0x08003BEC:  5CA2         LDRB       R2, [R4, R2]
+  0x08003BEE:  0212         LSLS       R2, R2, #8
+  0x08003BF0:  1814         ADDS       R4, R2, R0
+  0x08003BF2:  2203         MOVS       R2, #3
+  0x08003BF4:  2383         MOVS       R3, #131
+  0x08003BF6:  2C00         CMP        R4, #0
+  0x08003BF8:  D002         BEQ        .L224                    ; 0x08003C00
+  0x08003BFA:  2C7D         CMP        R4, #125
+  0x08003BFC:  D800         BHI        .L224                    ; 0x08003C00
+  0x08003BFE:  E33A         B          .L262                    ; 0x08004276
+
.L224:
+  0x08003C00:  4C5A         LDR        R4, =modbusData          ; [PC, #0x0168] [0x08003D6C] =0x20000000 
+
.L225:
+  0x08003C02:  9913         LDR        R1, [SP, #76]
+  0x08003C04:  312A         ADDS       R1, #42
+  0x08003C06:  5462         STRB       R2, [R4, R1]
+  0x08003C08:  2125         MOVS       R1, #37
+  0x08003C0A:  00C9         LSLS       R1, R1, #3
+  0x08003C0C:  5463         STRB       R3, [R4, R1]
+  0x08003C0E:  2603         MOVS       R6, #3
+  0x08003C10:  E395         B          .L270                    ; 0x0800433E
+
.L226:
+  0x08003C12:  492E         LDR        R1, =0x50000410          ; [PC, #184] [0x08003CCC] 
+  0x08003C14:  981A         LDR        R0, [SP, #104]
+  0x08003C16:  6188         STR        R0, [R1, #24]
+  0x08003C18:  981B         LDR        R0, [SP, #108]
+  0x08003C1A:  6088         STR        R0, [R1, #8]
+  0x08003C1C:  4832         LDR        R0, =relaisState         ; [PC, #200] [0x08003CE8] =0x20000730 
+  0x08003C1E:  7005         STRB       R5, [R0]
+  0x08003C20:  4847         LDR        R0, =onTimeCounterSET    ; [PC, #0x011C] [0x08003D40] =0x20000698 
+  0x08003C22:  9A16         LDR        R2, [SP, #88]
+  0x08003C24:  6002         STR        R2, [R0]
+  0x08003C26:  9820         LDR        R0, [SP, #128]
+  0x08003C28:  6088         STR        R0, [R1, #8]
+  0x08003C2A:  4846         LDR        R0, =onTimeGN            ; [PC, #0x0118] [0x08003D44] =0x20000740 
+  0x08003C2C:  7005         STRB       R5, [R0]
+  0x08003C2E:  4830         LDR        R0, =onTimeCounter       ; [PC, #192] [0x08003CF0] =0x200006A8 
+  0x08003C30:  21C8         MOVS       R1, #200
+  0x08003C32:  6001         STR        R1, [R0]
+  0x08003C34:  4844         LDR        R0, =offTimeGN           ; [PC, #0x0110] [0x08003D48] =0x2000074C 
+  0x08003C36:  7005         STRB       R5, [R0]
+  0x08003C38:  4830         LDR        R0, =blinkModeGN         ; [PC, #192] [0x08003CFC] =0x20000758 
+  0x08003C3A:  7005         STRB       R5, [R0]
+  0x08003C3C:  4A2D         LDR        R2, =0x50000818          ; [PC, #180] [0x08003CF4] 
+  0x08003C3E:  981F         LDR        R0, [SP, #124]
+  0x08003C40:  6010         STR        R0, [R2]
+  0x08003C42:  482F         LDR        R0, =onTimeCounterGN     ; [PC, #188] [0x08003D00] =0x200006A4 
+  0x08003C44:  6001         STR        R1, [R0]
+  0x08003C46:  981E         LDR        R0, [SP, #120]
+  0x08003C48:  6110         STR        R0, [R2, #16]
+  0x08003C4A:  4842         LDR        R0, =offTimeCounterRT    ; [PC, #0x0108] [0x08003D54] =0x200006B0 
+  0x08003C4C:  2100         MOVS       R1, #0
+  0x08003C4E:  6001         STR        R1, [R0]
+  0x08003C50:  482E         LDR        R0, =blinkModeRT         ; [PC, #184] [0x08003D0C] =0x20000754 
+  0x08003C52:  7001         STRB       R1, [R0]
+  0x08003C54:  4832         LDR        R0, =onTimeCounterRT     ; [PC, #200] [0x08003D20] =0x2000069C 
+  0x08003C56:  6001         STR        R1, [R0]
+  0x08003C58:  4845         LDR        R0, =0x0800653B          ; [PC, #0x0114] [0x08003D70] 
+  0x08003C5A:  F001 FACB    BL         puts                     ; 0x080051F4
+  0x08003C5E:  4845         LDR        R0, =smState.145         ; [PC, #0x0114] [0x08003D74] =0x20000733 
+  0x08003C60:  7005         STRB       R5, [R0]
+  0x08003C62:  7830         LDRB       R0, [R6]
+
.L227:
+  0x08003C64:  2802         CMP        R0, #2
+  0x08003C66:  D000         BEQ        .L228                    ; 0x08003C6A
+  0x08003C68:  E254         B          .L252                    ; 0x08004114
+
.L228:
+  0x08003C6A:  4918         LDR        R1, =0x50000410          ; [PC, #96] [0x08003CCC] 
+  0x08003C6C:  981A         LDR        R0, [SP, #104]
+  0x08003C6E:  6188         STR        R0, [R1, #24]
+  0x08003C70:  981B         LDR        R0, [SP, #108]
+  0x08003C72:  6088         STR        R0, [R1, #8]
+  0x08003C74:  481C         LDR        R0, =relaisState         ; [PC, #112] [0x08003CE8] =0x20000730 
+  0x08003C76:  7005         STRB       R5, [R0]
+  0x08003C78:  4831         LDR        R0, =onTimeCounterSET    ; [PC, #196] [0x08003D40] =0x20000698 
+  0x08003C7A:  9A16         LDR        R2, [SP, #88]
+  0x08003C7C:  6002         STR        R2, [R0]
+  0x08003C7E:  483E         LDR        R0, =onTime              ; [PC, #248] [0x08003D78] =0x20000744 
+  0x08003C80:  7005         STRB       R5, [R0]
+  0x08003C82:  483E         LDR        R0, =offTime             ; [PC, #248] [0x08003D7C] =0x20000750 
+  0x08003C84:  7005         STRB       R5, [R0]
+  0x08003C86:  483E         LDR        R0, =alarmMode           ; [PC, #248] [0x08003D80] =0x2000075C 
+  0x08003C88:  7005         STRB       R5, [R0]
+  0x08003C8A:  9820         LDR        R0, [SP, #128]
+  0x08003C8C:  6088         STR        R0, [R1, #8]
+  0x08003C8E:  4918         LDR        R1, =onTimeCounter       ; [PC, #96] [0x08003CF0] =0x200006A8 
+  0x08003C90:  20C8         MOVS       R0, #200
+  0x08003C92:  6008         STR        R0, [R1]
+  0x08003C94:  4B17         LDR        R3, =0x50000818          ; [PC, #92] [0x08003CF4] 
+  0x08003C96:  991F         LDR        R1, [SP, #124]
+  0x08003C98:  6019         STR        R1, [R3]
+  0x08003C9A:  4919         LDR        R1, =onTimeCounterGN     ; [PC, #100] [0x08003D00] =0x200006A4 
+  0x08003C9C:  2200         MOVS       R2, #0
+  0x08003C9E:  600A         STR        R2, [R1]
+  0x08003CA0:  4916         LDR        R1, =blinkModeGN         ; [PC, #88] [0x08003CFC] =0x20000758 
+  0x08003CA2:  700A         STRB       R2, [R1]
+  0x08003CA4:  4914         LDR        R1, =offTimeCounterGN    ; [PC, #80] [0x08003CF8] =0x200006B4 
+  0x08003CA6:  600A         STR        R2, [R1]
+  0x08003CA8:  9E1E         LDR        R6, [SP, #120]
+  0x08003CAA:  611E         STR        R6, [R3, #16]
+  0x08003CAC:  4915         LDR        R1, =onTimeRT            ; [PC, #84] [0x08003D04] =0x2000073C 
+  0x08003CAE:  700D         STRB       R5, [R1]
+  0x08003CB0:  4928         LDR        R1, =offTimeCounterRT    ; [PC, #160] [0x08003D54] =0x200006B0 
+  0x08003CB2:  600A         STR        R2, [R1]
+  0x08003CB4:  4914         LDR        R1, =offTimeRT           ; [PC, #80] [0x08003D08] =0x20000748 
+  0x08003CB6:  700D         STRB       R5, [R1]
+  0x08003CB8:  4914         LDR        R1, =blinkModeRT         ; [PC, #80] [0x08003D0C] =0x20000754 
+  0x08003CBA:  700D         STRB       R5, [R1]
+  0x08003CBC:  4914         LDR        R1, =numberOfBlinks      ; [PC, #80] [0x08003D10] =0x200006BC 
+  0x08003CBE:  600D         STR        R5, [R1]
+  0x08003CC0:  4914         LDR        R1, =blinkCounter        ; [PC, #80] [0x08003D14] =0x200006EC 
+  0x08003CC2:  600D         STR        R5, [R1]
+  0x08003CC4:  4914         LDR        R1, =pauseTime           ; [PC, #80] [0x08003D18] =0x20000734 
+  0x08003CC6:  700D         STRB       R5, [R1]
+  0x08003CC8:  601E         STR        R6, [R3]
+  0x08003CCA:  E0AE         B          .L233                    ; 0x08003E2A
+  0x08003CCC:  50000410     DC.W       0x50000410
+  0x08003CD0:  50000010     DC.W       0x50000010
+  0x08003CD4:  20000720     DC.W       LVP_SM_On.oldtime
+  0x08003CD8:  2000068C     DC.W       uwTick
+  0x08003CDC:  20000724     DC.W       LVP_SM_On.lvpTimeCounter
+  0x08003CE0:  00001388     DC.W       0x00001388
+  0x08003CE4:  20000764     DC.W       LVP_SM_On.lvpInput
+  0x08003CE8:  20000730     DC.W       relaisState
+  0x08003CEC:  200006A0     DC.W       onTimeCounterRESET
+  0x08003CF0:  200006A8     DC.W       onTimeCounter
+  0x08003CF4:  50000818     DC.W       0x50000818
+  0x08003CF8:  200006B4     DC.W       offTimeCounterGN
+  0x08003CFC:  20000758     DC.W       blinkModeGN
+  0x08003D00:  200006A4     DC.W       onTimeCounterGN
+  0x08003D04:  2000073C     DC.W       onTimeRT
+  0x08003D08:  20000748     DC.W       offTimeRT
+  0x08003D0C:  20000754     DC.W       blinkModeRT
+  0x08003D10:  200006BC     DC.W       numberOfBlinks
+  0x08003D14:  200006EC     DC.W       blinkCounter
+  0x08003D18:  20000734     DC.W       pauseTime
+  0x08003D1C:  2000073A     DC.W       buttonState
+  0x08003D20:  2000069C     DC.W       onTimeCounterRT
+  0x08003D24:  08006990     DC.W       08006990               ; R_ARM_ABS32
+  0x08003D28:  08006648     DC.W       08006648               ; R_ARM_ABS32
+  0x08003D2C:  20000737     DC.W       smState
+  0x08003D30:  20000690     DC.W       temp
+  0x08003D34:  08006330     DC.W       08006330               ; R_ARM_ABS32
+  0x08003D38:  0800665D     DC.W       0800665D               ; R_ARM_ABS32
+  0x08003D3C:  08006263     DC.W       08006263               ; R_ARM_ABS32
+  0x08003D40:  20000698     DC.W       onTimeCounterSET
+  0x08003D44:  20000740     DC.W       onTimeGN
+  0x08003D48:  2000074C     DC.W       offTimeGN
+  0x08003D4C:  080068E8     DC.W       080068E8               ; R_ARM_ABS32
+  0x08003D50:  080064A1     DC.W       080064A1               ; R_ARM_ABS32
+  0x08003D54:  200006B0     DC.W       offTimeCounterRT
+  0x08003D58:  08006286     DC.W       08006286               ; R_ARM_ABS32
+  0x08003D5C:  000003C7     DC.W       0x000003C7
+  0x08003D60:  20000234     DC.W       sys_data
+  0x08003D64:  00000286     DC.W       0x00000286
+  0x08003D68:  00000B86     DC.W       0x00000B86
+  0x08003D6C:  20000000     DC.W       modbusData
+  0x08003D70:  0800653B     DC.W       0800653B               ; R_ARM_ABS32
+  0x08003D74:  20000733     DC.W       smState.145
+  0x08003D78:  20000744     DC.W       onTime
+  0x08003D7C:  20000750     DC.W       offTime
+  0x08003D80:  2000075C     DC.W       alarmMode
+
.L229:
+  0x08003D84:  49F2         LDR        R1, =0x50000410          ; [PC, #0x03C8] [0x08004150] 
+  0x08003D86:  981A         LDR        R0, [SP, #104]
+  0x08003D88:  6188         STR        R0, [R1, #24]
+  0x08003D8A:  981B         LDR        R0, [SP, #108]
+  0x08003D8C:  6088         STR        R0, [R1, #8]
+  0x08003D8E:  48F1         LDR        R0, =relaisState         ; [PC, #0x03C4] [0x08004154] =0x20000730 
+  0x08003D90:  7005         STRB       R5, [R0]
+  0x08003D92:  48F1         LDR        R0, =onTimeCounterSET    ; [PC, #0x03C4] [0x08004158] =0x20000698 
+  0x08003D94:  9A16         LDR        R2, [SP, #88]
+  0x08003D96:  6002         STR        R2, [R0]
+  0x08003D98:  9820         LDR        R0, [SP, #128]
+  0x08003D9A:  6088         STR        R0, [R1, #8]
+  0x08003D9C:  48EF         LDR        R0, =offTimeGN           ; [PC, #0x03BC] [0x0800415C] =0x2000074C 
+  0x08003D9E:  7005         STRB       R5, [R0]
+  0x08003DA0:  48EF         LDR        R0, =onTimeGN            ; [PC, #0x03BC] [0x08004160] =0x20000740 
+  0x08003DA2:  7005         STRB       R5, [R0]
+  0x08003DA4:  48EF         LDR        R0, =0x080064F7          ; [PC, #0x03BC] [0x08004164] 
+  0x08003DA6:  49F0         LDR        R1, =onTimeCounterGN     ; [PC, #0x03C0] [0x08004168] =0x200006A4 
+  0x08003DA8:  4BF0         LDR        R3, =blinkModeGN         ; [PC, #0x03C0] [0x0800416C] =0x20000758 
+  0x08003DAA:  22C8         MOVS       R2, #200
+  0x08003DAC:  9E1F         LDR        R6, [SP, #124]
+  0x08003DAE:  462F         MOV        R7, R5
+
.L230:
+  0x08003DB0:  701D         STRB       R5, [R3]
+  0x08003DB2:  4BEF         LDR        R3, =onTimeCounter       ; [PC, #0x03BC] [0x08004170] =0x200006A8 
+  0x08003DB4:  601A         STR        R2, [R3]
+  0x08003DB6:  4AEF         LDR        R2, =0x50000818          ; [PC, #0x03BC] [0x08004174] 
+  0x08003DB8:  6016         STR        R6, [R2]
+  0x08003DBA:  22C8         MOVS       R2, #200
+  0x08003DBC:  600A         STR        R2, [R1]
+  0x08003DBE:  F001 FA19    BL         puts                     ; 0x080051F4
+  0x08003DC2:  48ED         LDR        R0, =smState.145         ; [PC, #0x03B4] [0x08004178] =0x20000733 
+  0x08003DC4:  7007         STRB       R7, [R0]
+  0x08003DC6:  7820         LDRB       R0, [R4]
+  0x08003DC8:  4FEC         LDR        R7, =0x000003C7          ; [PC, #0x03B0] [0x0800417C] 
+
.L231:
+  0x08003DCA:  2802         CMP        R0, #2
+  0x08003DCC:  D000         BEQ        .L232                    ; 0x08003DD0
+  0x08003DCE:  E1A1         B          .L252                    ; 0x08004114
+
.L232:
+  0x08003DD0:  49DF         LDR        R1, =0x50000410          ; [PC, #0x037C] [0x08004150] 
+  0x08003DD2:  981A         LDR        R0, [SP, #104]
+  0x08003DD4:  6188         STR        R0, [R1, #24]
+  0x08003DD6:  981B         LDR        R0, [SP, #108]
+  0x08003DD8:  6088         STR        R0, [R1, #8]
+  0x08003DDA:  48DE         LDR        R0, =relaisState         ; [PC, #0x0378] [0x08004154] =0x20000730 
+  0x08003DDC:  7005         STRB       R5, [R0]
+  0x08003DDE:  48DE         LDR        R0, =onTimeCounterSET    ; [PC, #0x0378] [0x08004158] =0x20000698 
+  0x08003DE0:  9A16         LDR        R2, [SP, #88]
+  0x08003DE2:  6002         STR        R2, [R0]
+  0x08003DE4:  48E6         LDR        R0, =onTime              ; [PC, #0x0398] [0x08004180] =0x20000744 
+  0x08003DE6:  7005         STRB       R5, [R0]
+  0x08003DE8:  48E6         LDR        R0, =offTime             ; [PC, #0x0398] [0x08004184] =0x20000750 
+  0x08003DEA:  7005         STRB       R5, [R0]
+  0x08003DEC:  48E6         LDR        R0, =alarmMode           ; [PC, #0x0398] [0x08004188] =0x2000075C 
+  0x08003DEE:  7005         STRB       R5, [R0]
+  0x08003DF0:  9820         LDR        R0, [SP, #128]
+  0x08003DF2:  6088         STR        R0, [R1, #8]
+  0x08003DF4:  49DE         LDR        R1, =onTimeCounter       ; [PC, #0x0378] [0x08004170] =0x200006A8 
+  0x08003DF6:  20C8         MOVS       R0, #200
+  0x08003DF8:  6008         STR        R0, [R1]
+  0x08003DFA:  4BDE         LDR        R3, =0x50000818          ; [PC, #0x0378] [0x08004174] 
+  0x08003DFC:  991F         LDR        R1, [SP, #124]
+  0x08003DFE:  6019         STR        R1, [R3]
+  0x08003E00:  49D9         LDR        R1, =onTimeCounterGN     ; [PC, #0x0364] [0x08004168] =0x200006A4 
+  0x08003E02:  2200         MOVS       R2, #0
+  0x08003E04:  600A         STR        R2, [R1]
+  0x08003E06:  49D9         LDR        R1, =blinkModeGN         ; [PC, #0x0364] [0x0800416C] =0x20000758 
+  0x08003E08:  700A         STRB       R2, [R1]
+  0x08003E0A:  49E0         LDR        R1, =offTimeCounterGN    ; [PC, #0x0380] [0x0800418C] =0x200006B4 
+  0x08003E0C:  600A         STR        R2, [R1]
+  0x08003E0E:  49E0         LDR        R1, =onTimeRT            ; [PC, #0x0380] [0x08004190] =0x2000073C 
+  0x08003E10:  700D         STRB       R5, [R1]
+  0x08003E12:  49E0         LDR        R1, =offTimeRT           ; [PC, #0x0380] [0x08004194] =0x20000748 
+  0x08003E14:  700D         STRB       R5, [R1]
+  0x08003E16:  49E0         LDR        R1, =blinkModeRT         ; [PC, #0x0380] [0x08004198] =0x20000754 
+  0x08003E18:  700D         STRB       R5, [R1]
+  0x08003E1A:  49E0         LDR        R1, =numberOfBlinks      ; [PC, #0x0380] [0x0800419C] =0x200006BC 
+  0x08003E1C:  600D         STR        R5, [R1]
+  0x08003E1E:  49E0         LDR        R1, =blinkCounter        ; [PC, #0x0380] [0x080041A0] =0x200006EC 
+  0x08003E20:  600D         STR        R5, [R1]
+  0x08003E22:  49E0         LDR        R1, =pauseTime           ; [PC, #0x0380] [0x080041A4] =0x20000734 
+  0x08003E24:  700D         STRB       R5, [R1]
+  0x08003E26:  991E         LDR        R1, [SP, #120]
+  0x08003E28:  6019         STR        R1, [R3]
+
.L233:
+  0x08003E2A:  49DF         LDR        R1, =onTimeCounterRT     ; [PC, #0x037C] [0x080041A8] =0x2000069C 
+  0x08003E2C:  6008         STR        R0, [R1]
+  0x08003E2E:  48DF         LDR        R0, =0x0800674E          ; [PC, #0x037C] [0x080041AC] 
+  0x08003E30:  F001 F9E0    BL         puts                     ; 0x080051F4
+  0x08003E34:  2002         MOVS       R0, #2
+  0x08003E36:  49D0         LDR        R1, =smState.145         ; [PC, #0x0340] [0x08004178] =0x20000733 
+  0x08003E38:  E16B         B          .L251                    ; 0x08004112
+
.L234:
+  0x08003E3A:  49C5         LDR        R1, =0x50000410          ; [PC, #0x0314] [0x08004150] 
+  0x08003E3C:  981A         LDR        R0, [SP, #104]
+  0x08003E3E:  6188         STR        R0, [R1, #24]
+  0x08003E40:  981B         LDR        R0, [SP, #108]
+  0x08003E42:  6088         STR        R0, [R1, #8]
+  0x08003E44:  48C3         LDR        R0, =relaisState         ; [PC, #0x030C] [0x08004154] =0x20000730 
+  0x08003E46:  7005         STRB       R5, [R0]
+  0x08003E48:  48C3         LDR        R0, =onTimeCounterSET    ; [PC, #0x030C] [0x08004158] =0x20000698 
+  0x08003E4A:  9A16         LDR        R2, [SP, #88]
+  0x08003E4C:  6002         STR        R2, [R0]
+  0x08003E4E:  9820         LDR        R0, [SP, #128]
+  0x08003E50:  6088         STR        R0, [R1, #8]
+  0x08003E52:  48C2         LDR        R0, =offTimeGN           ; [PC, #0x0308] [0x0800415C] =0x2000074C 
+  0x08003E54:  7005         STRB       R5, [R0]
+  0x08003E56:  48C2         LDR        R0, =onTimeGN            ; [PC, #0x0308] [0x08004160] =0x20000740 
+  0x08003E58:  7005         STRB       R5, [R0]
+  0x08003E5A:  48D5         LDR        R0, =0x080066EA          ; [PC, #0x0354] [0x080041B0] 
+  0x08003E5C:  49C2         LDR        R1, =onTimeCounterGN     ; [PC, #0x0308] [0x08004168] =0x200006A4 
+  0x08003E5E:  4BC3         LDR        R3, =blinkModeGN         ; [PC, #0x030C] [0x0800416C] =0x20000758 
+  0x08003E60:  22C8         MOVS       R2, #200
+  0x08003E62:  9E1F         LDR        R6, [SP, #124]
+  0x08003E64:  462F         MOV        R7, R5
+
.L235:
+  0x08003E66:  701D         STRB       R5, [R3]
+  0x08003E68:  4BC1         LDR        R3, =onTimeCounter       ; [PC, #0x0304] [0x08004170] =0x200006A8 
+  0x08003E6A:  601A         STR        R2, [R3]
+  0x08003E6C:  4AC1         LDR        R2, =0x50000818          ; [PC, #0x0304] [0x08004174] 
+  0x08003E6E:  6016         STR        R6, [R2]
+  0x08003E70:  22C8         MOVS       R2, #200
+  0x08003E72:  600A         STR        R2, [R1]
+  0x08003E74:  F001 F9BE    BL         puts                     ; 0x080051F4
+  0x08003E78:  7027         STRB       R7, [R4]
+  0x08003E7A:  48CE         LDR        R0, =buttonState         ; [PC, #0x0338] [0x080041B4] =0x2000073A 
+  0x08003E7C:  7800         LDRB       R0, [R0]
+  0x08003E7E:  4FBF         LDR        R7, =0x000003C7          ; [PC, #0x02FC] [0x0800417C] 
+
.L236:
+  0x08003E80:  2802         CMP        R0, #2
+  0x08003E82:  D000         BEQ        .L237                    ; 0x08003E86
+  0x08003E84:  E146         B          .L252                    ; 0x08004114
+
.L237:
+  0x08003E86:  49B2         LDR        R1, =0x50000410          ; [PC, #0x02C8] [0x08004150] 
+  0x08003E88:  981A         LDR        R0, [SP, #104]
+  0x08003E8A:  6188         STR        R0, [R1, #24]
+  0x08003E8C:  981B         LDR        R0, [SP, #108]
+  0x08003E8E:  6088         STR        R0, [R1, #8]
+  0x08003E90:  48B0         LDR        R0, =relaisState         ; [PC, #0x02C0] [0x08004154] =0x20000730 
+  0x08003E92:  7005         STRB       R5, [R0]
+  0x08003E94:  48B0         LDR        R0, =onTimeCounterSET    ; [PC, #0x02C0] [0x08004158] =0x20000698 
+  0x08003E96:  9A16         LDR        R2, [SP, #88]
+  0x08003E98:  6002         STR        R2, [R0]
+  0x08003E9A:  48B9         LDR        R0, =onTime              ; [PC, #0x02E4] [0x08004180] =0x20000744 
+  0x08003E9C:  7005         STRB       R5, [R0]
+  0x08003E9E:  48B9         LDR        R0, =offTime             ; [PC, #0x02E4] [0x08004184] =0x20000750 
+  0x08003EA0:  7005         STRB       R5, [R0]
+  0x08003EA2:  48B9         LDR        R0, =alarmMode           ; [PC, #0x02E4] [0x08004188] =0x2000075C 
+  0x08003EA4:  7005         STRB       R5, [R0]
+  0x08003EA6:  9820         LDR        R0, [SP, #128]
+  0x08003EA8:  6088         STR        R0, [R1, #8]
+  0x08003EAA:  49B1         LDR        R1, =onTimeCounter       ; [PC, #0x02C4] [0x08004170] =0x200006A8 
+  0x08003EAC:  20C8         MOVS       R0, #200
+  0x08003EAE:  6008         STR        R0, [R1]
+  0x08003EB0:  4BB0         LDR        R3, =0x50000818          ; [PC, #0x02C0] [0x08004174] 
+  0x08003EB2:  991F         LDR        R1, [SP, #124]
+  0x08003EB4:  6019         STR        R1, [R3]
+  0x08003EB6:  49AC         LDR        R1, =onTimeCounterGN     ; [PC, #0x02B0] [0x08004168] =0x200006A4 
+  0x08003EB8:  2200         MOVS       R2, #0
+  0x08003EBA:  600A         STR        R2, [R1]
+  0x08003EBC:  49AB         LDR        R1, =blinkModeGN         ; [PC, #0x02AC] [0x0800416C] =0x20000758 
+  0x08003EBE:  700A         STRB       R2, [R1]
+  0x08003EC0:  49B2         LDR        R1, =offTimeCounterGN    ; [PC, #0x02C8] [0x0800418C] =0x200006B4 
+  0x08003EC2:  600A         STR        R2, [R1]
+  0x08003EC4:  49B2         LDR        R1, =onTimeRT            ; [PC, #0x02C8] [0x08004190] =0x2000073C 
+  0x08003EC6:  700D         STRB       R5, [R1]
+  0x08003EC8:  49B2         LDR        R1, =offTimeRT           ; [PC, #0x02C8] [0x08004194] =0x20000748 
+  0x08003ECA:  700D         STRB       R5, [R1]
+  0x08003ECC:  49B2         LDR        R1, =blinkModeRT         ; [PC, #0x02C8] [0x08004198] =0x20000754 
+  0x08003ECE:  700D         STRB       R5, [R1]
+  0x08003ED0:  49B2         LDR        R1, =numberOfBlinks      ; [PC, #0x02C8] [0x0800419C] =0x200006BC 
+  0x08003ED2:  600D         STR        R5, [R1]
+  0x08003ED4:  49B2         LDR        R1, =blinkCounter        ; [PC, #0x02C8] [0x080041A0] =0x200006EC 
+  0x08003ED6:  600D         STR        R5, [R1]
+  0x08003ED8:  49B2         LDR        R1, =pauseTime           ; [PC, #0x02C8] [0x080041A4] =0x20000734 
+  0x08003EDA:  700D         STRB       R5, [R1]
+  0x08003EDC:  991E         LDR        R1, [SP, #120]
+  0x08003EDE:  6019         STR        R1, [R3]
+
.L238:
+  0x08003EE0:  49B1         LDR        R1, =onTimeCounterRT     ; [PC, #0x02C4] [0x080041A8] =0x2000069C 
+  0x08003EE2:  6008         STR        R0, [R1]
+  0x08003EE4:  48B4         LDR        R0, =0x0800692C          ; [PC, #0x02D0] [0x080041B8] 
+  0x08003EE6:  F001 F985    BL         puts                     ; 0x080051F4
+  0x08003EEA:  2002         MOVS       R0, #2
+  0x08003EEC:  7020         STRB       R0, [R4]
+  0x08003EEE:  E111         B          .L252                    ; 0x08004114
+
.L239:
+  0x08003EF0:  4997         LDR        R1, =0x50000410          ; [PC, #0x025C] [0x08004150] 
+  0x08003EF2:  981A         LDR        R0, [SP, #104]
+  0x08003EF4:  6188         STR        R0, [R1, #24]
+  0x08003EF6:  981B         LDR        R0, [SP, #108]
+  0x08003EF8:  6088         STR        R0, [R1, #8]
+  0x08003EFA:  4896         LDR        R0, =relaisState         ; [PC, #0x0258] [0x08004154] =0x20000730 
+  0x08003EFC:  7005         STRB       R5, [R0]
+  0x08003EFE:  4896         LDR        R0, =onTimeCounterSET    ; [PC, #0x0258] [0x08004158] =0x20000698 
+  0x08003F00:  9A16         LDR        R2, [SP, #88]
+  0x08003F02:  6002         STR        R2, [R0]
+  0x08003F04:  9820         LDR        R0, [SP, #128]
+  0x08003F06:  6088         STR        R0, [R1, #8]
+  0x08003F08:  4895         LDR        R0, =onTimeGN            ; [PC, #0x0254] [0x08004160] =0x20000740 
+  0x08003F0A:  7005         STRB       R5, [R0]
+  0x08003F0C:  4898         LDR        R0, =onTimeCounter       ; [PC, #0x0260] [0x08004170] =0x200006A8 
+  0x08003F0E:  21C8         MOVS       R1, #200
+  0x08003F10:  6001         STR        R1, [R0]
+  0x08003F12:  4892         LDR        R0, =offTimeGN           ; [PC, #0x0248] [0x0800415C] =0x2000074C 
+  0x08003F14:  7005         STRB       R5, [R0]
+  0x08003F16:  4895         LDR        R0, =blinkModeGN         ; [PC, #0x0254] [0x0800416C] =0x20000758 
+  0x08003F18:  7005         STRB       R5, [R0]
+  0x08003F1A:  4A96         LDR        R2, =0x50000818          ; [PC, #0x0258] [0x08004174] 
+  0x08003F1C:  981F         LDR        R0, [SP, #124]
+  0x08003F1E:  6010         STR        R0, [R2]
+  0x08003F20:  4891         LDR        R0, =onTimeCounterGN     ; [PC, #0x0244] [0x08004168] =0x200006A4 
+  0x08003F22:  6001         STR        R1, [R0]
+  0x08003F24:  981E         LDR        R0, [SP, #120]
+  0x08003F26:  6110         STR        R0, [R2, #16]
+  0x08003F28:  48A4         LDR        R0, =offTimeCounterRT    ; [PC, #0x0290] [0x080041BC] =0x200006B0 
+  0x08003F2A:  2100         MOVS       R1, #0
+  0x08003F2C:  6001         STR        R1, [R0]
+  0x08003F2E:  489A         LDR        R0, =blinkModeRT         ; [PC, #0x0268] [0x08004198] =0x20000754 
+  0x08003F30:  7001         STRB       R1, [R0]
+  0x08003F32:  489D         LDR        R0, =onTimeCounterRT     ; [PC, #0x0274] [0x080041A8] =0x2000069C 
+  0x08003F34:  6001         STR        R1, [R0]
+  0x08003F36:  48A2         LDR        R0, =0x08006469          ; [PC, #0x0288] [0x080041C0] 
+  0x08003F38:  F001 F95C    BL         puts                     ; 0x080051F4
+  0x08003F3C:  48A1         LDR        R0, =smState             ; [PC, #0x0284] [0x080041C4] =0x20000737 
+  0x08003F3E:  7005         STRB       R5, [R0]
+  0x08003F40:  7830         LDRB       R0, [R6]
+
.L240:
+  0x08003F42:  2802         CMP        R0, #2
+  0x08003F44:  D000         BEQ        .L241                    ; 0x08003F48
+  0x08003F46:  E0E5         B          .L252                    ; 0x08004114
+
.L241:
+  0x08003F48:  4981         LDR        R1, =0x50000410          ; [PC, #0x0204] [0x08004150] 
+  0x08003F4A:  981A         LDR        R0, [SP, #104]
+  0x08003F4C:  6188         STR        R0, [R1, #24]
+  0x08003F4E:  981B         LDR        R0, [SP, #108]
+  0x08003F50:  6088         STR        R0, [R1, #8]
+  0x08003F52:  4880         LDR        R0, =relaisState         ; [PC, #0x0200] [0x08004154] =0x20000730 
+  0x08003F54:  7005         STRB       R5, [R0]
+  0x08003F56:  4880         LDR        R0, =onTimeCounterSET    ; [PC, #0x0200] [0x08004158] =0x20000698 
+  0x08003F58:  9A16         LDR        R2, [SP, #88]
+  0x08003F5A:  6002         STR        R2, [R0]
+  0x08003F5C:  4888         LDR        R0, =onTime              ; [PC, #0x0220] [0x08004180] =0x20000744 
+  0x08003F5E:  7005         STRB       R5, [R0]
+  0x08003F60:  4888         LDR        R0, =offTime             ; [PC, #0x0220] [0x08004184] =0x20000750 
+  0x08003F62:  7005         STRB       R5, [R0]
+  0x08003F64:  4888         LDR        R0, =alarmMode           ; [PC, #0x0220] [0x08004188] =0x2000075C 
+  0x08003F66:  7005         STRB       R5, [R0]
+  0x08003F68:  9820         LDR        R0, [SP, #128]
+  0x08003F6A:  6088         STR        R0, [R1, #8]
+  0x08003F6C:  4980         LDR        R1, =onTimeCounter       ; [PC, #0x0200] [0x08004170] =0x200006A8 
+  0x08003F6E:  20C8         MOVS       R0, #200
+  0x08003F70:  6008         STR        R0, [R1]
+  0x08003F72:  4B80         LDR        R3, =0x50000818          ; [PC, #0x0200] [0x08004174] 
+  0x08003F74:  991F         LDR        R1, [SP, #124]
+  0x08003F76:  6019         STR        R1, [R3]
+  0x08003F78:  497B         LDR        R1, =onTimeCounterGN     ; [PC, #0x01EC] [0x08004168] =0x200006A4 
+  0x08003F7A:  2200         MOVS       R2, #0
+  0x08003F7C:  600A         STR        R2, [R1]
+  0x08003F7E:  497B         LDR        R1, =blinkModeGN         ; [PC, #0x01EC] [0x0800416C] =0x20000758 
+  0x08003F80:  700A         STRB       R2, [R1]
+  0x08003F82:  4982         LDR        R1, =offTimeCounterGN    ; [PC, #0x0208] [0x0800418C] =0x200006B4 
+  0x08003F84:  600A         STR        R2, [R1]
+  0x08003F86:  9E1E         LDR        R6, [SP, #120]
+  0x08003F88:  611E         STR        R6, [R3, #16]
+  0x08003F8A:  4981         LDR        R1, =onTimeRT            ; [PC, #0x0204] [0x08004190] =0x2000073C 
+  0x08003F8C:  700D         STRB       R5, [R1]
+  0x08003F8E:  498B         LDR        R1, =offTimeCounterRT    ; [PC, #0x022C] [0x080041BC] =0x200006B0 
+  0x08003F90:  600A         STR        R2, [R1]
+  0x08003F92:  4980         LDR        R1, =offTimeRT           ; [PC, #0x0200] [0x08004194] =0x20000748 
+  0x08003F94:  700D         STRB       R5, [R1]
+  0x08003F96:  4980         LDR        R1, =blinkModeRT         ; [PC, #0x0200] [0x08004198] =0x20000754 
+  0x08003F98:  700D         STRB       R5, [R1]
+  0x08003F9A:  4980         LDR        R1, =numberOfBlinks      ; [PC, #0x0200] [0x0800419C] =0x200006BC 
+  0x08003F9C:  600D         STR        R5, [R1]
+  0x08003F9E:  4980         LDR        R1, =blinkCounter        ; [PC, #0x0200] [0x080041A0] =0x200006EC 
+  0x08003FA0:  600D         STR        R5, [R1]
+  0x08003FA2:  4980         LDR        R1, =pauseTime           ; [PC, #0x0200] [0x080041A4] =0x20000734 
+  0x08003FA4:  700D         STRB       R5, [R1]
+  0x08003FA6:  601E         STR        R6, [R3]
+  0x08003FA8:  E0AC         B          .L250                    ; 0x08004104
+
.L242:
+  0x08003FAA:  4969         LDR        R1, =0x50000410          ; [PC, #0x01A4] [0x08004150] 
+  0x08003FAC:  981A         LDR        R0, [SP, #104]
+  0x08003FAE:  6188         STR        R0, [R1, #24]
+  0x08003FB0:  981B         LDR        R0, [SP, #108]
+  0x08003FB2:  6088         STR        R0, [R1, #8]
+  0x08003FB4:  4867         LDR        R0, =relaisState         ; [PC, #0x019C] [0x08004154] =0x20000730 
+  0x08003FB6:  7005         STRB       R5, [R0]
+  0x08003FB8:  4867         LDR        R0, =onTimeCounterSET    ; [PC, #0x019C] [0x08004158] =0x20000698 
+  0x08003FBA:  9A16         LDR        R2, [SP, #88]
+  0x08003FBC:  6002         STR        R2, [R0]
+  0x08003FBE:  9820         LDR        R0, [SP, #128]
+  0x08003FC0:  6088         STR        R0, [R1, #8]
+  0x08003FC2:  4866         LDR        R0, =offTimeGN           ; [PC, #0x0198] [0x0800415C] =0x2000074C 
+  0x08003FC4:  7005         STRB       R5, [R0]
+  0x08003FC6:  4866         LDR        R0, =onTimeGN            ; [PC, #0x0198] [0x08004160] =0x20000740 
+  0x08003FC8:  7005         STRB       R5, [R0]
+  0x08003FCA:  487F         LDR        R0, =0x0800647B          ; [PC, #0x01FC] [0x080041C8] 
+  0x08003FCC:  4966         LDR        R1, =onTimeCounterGN     ; [PC, #0x0198] [0x08004168] =0x200006A4 
+  0x08003FCE:  4B67         LDR        R3, =blinkModeGN         ; [PC, #0x019C] [0x0800416C] =0x20000758 
+  0x08003FD0:  22C8         MOVS       R2, #200
+  0x08003FD2:  9E1F         LDR        R6, [SP, #124]
+  0x08003FD4:  462F         MOV        R7, R5
+
.L243:
+  0x08003FD6:  701D         STRB       R5, [R3]
+  0x08003FD8:  4B65         LDR        R3, =onTimeCounter       ; [PC, #0x0194] [0x08004170] =0x200006A8 
+  0x08003FDA:  601A         STR        R2, [R3]
+  0x08003FDC:  4A65         LDR        R2, =0x50000818          ; [PC, #0x0194] [0x08004174] 
+  0x08003FDE:  6016         STR        R6, [R2]
+  0x08003FE0:  22C8         MOVS       R2, #200
+  0x08003FE2:  600A         STR        R2, [R1]
+  0x08003FE4:  F001 F906    BL         puts                     ; 0x080051F4
+  0x08003FE8:  4878         LDR        R0, =smState.122         ; [PC, #0x01E0] [0x080041CC] =0x20000736 
+  0x08003FEA:  7007         STRB       R7, [R0]
+  0x08003FEC:  7820         LDRB       R0, [R4]
+  0x08003FEE:  4F63         LDR        R7, =0x000003C7          ; [PC, #0x018C] [0x0800417C] 
+
.L244:
+  0x08003FF0:  2802         CMP        R0, #2
+  0x08003FF2:  D000         BEQ        .L245                    ; 0x08003FF6
+  0x08003FF4:  E08E         B          .L252                    ; 0x08004114
+
.L245:
+  0x08003FF6:  4956         LDR        R1, =0x50000410          ; [PC, #0x0158] [0x08004150] 
+  0x08003FF8:  981A         LDR        R0, [SP, #104]
+  0x08003FFA:  6188         STR        R0, [R1, #24]
+  0x08003FFC:  981B         LDR        R0, [SP, #108]
+  0x08003FFE:  6088         STR        R0, [R1, #8]
+  0x08004000:  4854         LDR        R0, =relaisState         ; [PC, #0x0150] [0x08004154] =0x20000730 
+  0x08004002:  7005         STRB       R5, [R0]
+  0x08004004:  4854         LDR        R0, =onTimeCounterSET    ; [PC, #0x0150] [0x08004158] =0x20000698 
+  0x08004006:  9A16         LDR        R2, [SP, #88]
+  0x08004008:  6002         STR        R2, [R0]
+  0x0800400A:  485D         LDR        R0, =onTime              ; [PC, #0x0174] [0x08004180] =0x20000744 
+  0x0800400C:  7005         STRB       R5, [R0]
+  0x0800400E:  485D         LDR        R0, =offTime             ; [PC, #0x0174] [0x08004184] =0x20000750 
+  0x08004010:  7005         STRB       R5, [R0]
+  0x08004012:  485D         LDR        R0, =alarmMode           ; [PC, #0x0174] [0x08004188] =0x2000075C 
+  0x08004014:  7005         STRB       R5, [R0]
+  0x08004016:  9820         LDR        R0, [SP, #128]
+  0x08004018:  6088         STR        R0, [R1, #8]
+  0x0800401A:  4955         LDR        R1, =onTimeCounter       ; [PC, #0x0154] [0x08004170] =0x200006A8 
+  0x0800401C:  20C8         MOVS       R0, #200
+  0x0800401E:  6008         STR        R0, [R1]
+  0x08004020:  4B54         LDR        R3, =0x50000818          ; [PC, #0x0150] [0x08004174] 
+  0x08004022:  991F         LDR        R1, [SP, #124]
+  0x08004024:  6019         STR        R1, [R3]
+  0x08004026:  4950         LDR        R1, =onTimeCounterGN     ; [PC, #0x0140] [0x08004168] =0x200006A4 
+  0x08004028:  2200         MOVS       R2, #0
+  0x0800402A:  600A         STR        R2, [R1]
+  0x0800402C:  494F         LDR        R1, =blinkModeGN         ; [PC, #0x013C] [0x0800416C] =0x20000758 
+  0x0800402E:  700A         STRB       R2, [R1]
+  0x08004030:  4956         LDR        R1, =offTimeCounterGN    ; [PC, #0x0158] [0x0800418C] =0x200006B4 
+  0x08004032:  600A         STR        R2, [R1]
+  0x08004034:  4956         LDR        R1, =onTimeRT            ; [PC, #0x0158] [0x08004190] =0x2000073C 
+  0x08004036:  700D         STRB       R5, [R1]
+  0x08004038:  4956         LDR        R1, =offTimeRT           ; [PC, #0x0158] [0x08004194] =0x20000748 
+  0x0800403A:  700D         STRB       R5, [R1]
+  0x0800403C:  4956         LDR        R1, =blinkModeRT         ; [PC, #0x0158] [0x08004198] =0x20000754 
+  0x0800403E:  700D         STRB       R5, [R1]
+  0x08004040:  4956         LDR        R1, =numberOfBlinks      ; [PC, #0x0158] [0x0800419C] =0x200006BC 
+  0x08004042:  600D         STR        R5, [R1]
+  0x08004044:  4956         LDR        R1, =blinkCounter        ; [PC, #0x0158] [0x080041A0] =0x200006EC 
+  0x08004046:  600D         STR        R5, [R1]
+  0x08004048:  4956         LDR        R1, =pauseTime           ; [PC, #0x0158] [0x080041A4] =0x20000734 
+  0x0800404A:  700D         STRB       R5, [R1]
+  0x0800404C:  991E         LDR        R1, [SP, #120]
+  0x0800404E:  6019         STR        R1, [R3]
+
.L246:
+  0x08004050:  4955         LDR        R1, =onTimeCounterRT     ; [PC, #0x0154] [0x080041A8] =0x2000069C 
+  0x08004052:  6008         STR        R0, [R1]
+  0x08004054:  485E         LDR        R0, =0x080066CD          ; [PC, #0x0178] [0x080041D0] 
+  0x08004056:  F001 F8CD    BL         puts                     ; 0x080051F4
+  0x0800405A:  2002         MOVS       R0, #2
+  0x0800405C:  495B         LDR        R1, =smState.122         ; [PC, #0x016C] [0x080041CC] =0x20000736 
+  0x0800405E:  E058         B          .L251                    ; 0x08004112
+
.L247:
+  0x08004060:  493B         LDR        R1, =0x50000410          ; [PC, #236] [0x08004150] 
+  0x08004062:  981A         LDR        R0, [SP, #104]
+  0x08004064:  6188         STR        R0, [R1, #24]
+  0x08004066:  981B         LDR        R0, [SP, #108]
+  0x08004068:  6088         STR        R0, [R1, #8]
+  0x0800406A:  483A         LDR        R0, =relaisState         ; [PC, #232] [0x08004154] =0x20000730 
+  0x0800406C:  7005         STRB       R5, [R0]
+  0x0800406E:  483A         LDR        R0, =onTimeCounterSET    ; [PC, #232] [0x08004158] =0x20000698 
+  0x08004070:  9A16         LDR        R2, [SP, #88]
+  0x08004072:  6002         STR        R2, [R0]
+  0x08004074:  9820         LDR        R0, [SP, #128]
+  0x08004076:  6088         STR        R0, [R1, #8]
+  0x08004078:  4838         LDR        R0, =offTimeGN           ; [PC, #224] [0x0800415C] =0x2000074C 
+  0x0800407A:  7005         STRB       R5, [R0]
+  0x0800407C:  4838         LDR        R0, =onTimeGN            ; [PC, #224] [0x08004160] =0x20000740 
+  0x0800407E:  7005         STRB       R5, [R0]
+  0x08004080:  4854         LDR        R0, =0x0800644B          ; [PC, #0x0150] [0x080041D4] 
+  0x08004082:  4939         LDR        R1, =onTimeCounterGN     ; [PC, #228] [0x08004168] =0x200006A4 
+  0x08004084:  4B39         LDR        R3, =blinkModeGN         ; [PC, #228] [0x0800416C] =0x20000758 
+  0x08004086:  22C8         MOVS       R2, #200
+  0x08004088:  9E1F         LDR        R6, [SP, #124]
+  0x0800408A:  462F         MOV        R7, R5
+
.L248:
+  0x0800408C:  701D         STRB       R5, [R3]
+  0x0800408E:  4B38         LDR        R3, =onTimeCounter       ; [PC, #224] [0x08004170] =0x200006A8 
+  0x08004090:  601A         STR        R2, [R3]
+  0x08004092:  4A38         LDR        R2, =0x50000818          ; [PC, #224] [0x08004174] 
+  0x08004094:  6016         STR        R6, [R2]
+  0x08004096:  22C8         MOVS       R2, #200
+  0x08004098:  600A         STR        R2, [R1]
+  0x0800409A:  F001 F8AB    BL         puts                     ; 0x080051F4
+  0x0800409E:  4849         LDR        R0, =smState             ; [PC, #0x0124] [0x080041C4] =0x20000737 
+  0x080040A0:  7007         STRB       R7, [R0]
+  0x080040A2:  7820         LDRB       R0, [R4]
+  0x080040A4:  4F35         LDR        R7, =0x000003C7          ; [PC, #212] [0x0800417C] 
+
.L249:
+  0x080040A6:  2802         CMP        R0, #2
+  0x080040A8:  D134         BNE        .L252                    ; 0x08004114
+  0x080040AA:  4929         LDR        R1, =0x50000410          ; [PC, #164] [0x08004150] 
+  0x080040AC:  981A         LDR        R0, [SP, #104]
+  0x080040AE:  6188         STR        R0, [R1, #24]
+  0x080040B0:  981B         LDR        R0, [SP, #108]
+  0x080040B2:  6088         STR        R0, [R1, #8]
+  0x080040B4:  4827         LDR        R0, =relaisState         ; [PC, #156] [0x08004154] =0x20000730 
+  0x080040B6:  7005         STRB       R5, [R0]
+  0x080040B8:  4827         LDR        R0, =onTimeCounterSET    ; [PC, #156] [0x08004158] =0x20000698 
+  0x080040BA:  9A16         LDR        R2, [SP, #88]
+  0x080040BC:  6002         STR        R2, [R0]
+  0x080040BE:  4830         LDR        R0, =onTime              ; [PC, #192] [0x08004180] =0x20000744 
+  0x080040C0:  7005         STRB       R5, [R0]
+  0x080040C2:  4830         LDR        R0, =offTime             ; [PC, #192] [0x08004184] =0x20000750 
+  0x080040C4:  7005         STRB       R5, [R0]
+  0x080040C6:  4830         LDR        R0, =alarmMode           ; [PC, #192] [0x08004188] =0x2000075C 
+  0x080040C8:  7005         STRB       R5, [R0]
+  0x080040CA:  9820         LDR        R0, [SP, #128]
+  0x080040CC:  6088         STR        R0, [R1, #8]
+  0x080040CE:  4928         LDR        R1, =onTimeCounter       ; [PC, #160] [0x08004170] =0x200006A8 
+  0x080040D0:  20C8         MOVS       R0, #200
+  0x080040D2:  6008         STR        R0, [R1]
+  0x080040D4:  4B27         LDR        R3, =0x50000818          ; [PC, #156] [0x08004174] 
+  0x080040D6:  991F         LDR        R1, [SP, #124]
+  0x080040D8:  6019         STR        R1, [R3]
+  0x080040DA:  4923         LDR        R1, =onTimeCounterGN     ; [PC, #140] [0x08004168] =0x200006A4 
+  0x080040DC:  2200         MOVS       R2, #0
+  0x080040DE:  600A         STR        R2, [R1]
+  0x080040E0:  4922         LDR        R1, =blinkModeGN         ; [PC, #136] [0x0800416C] =0x20000758 
+  0x080040E2:  700A         STRB       R2, [R1]
+  0x080040E4:  4929         LDR        R1, =offTimeCounterGN    ; [PC, #164] [0x0800418C] =0x200006B4 
+  0x080040E6:  600A         STR        R2, [R1]
+  0x080040E8:  4929         LDR        R1, =onTimeRT            ; [PC, #164] [0x08004190] =0x2000073C 
+  0x080040EA:  700D         STRB       R5, [R1]
+  0x080040EC:  4929         LDR        R1, =offTimeRT           ; [PC, #164] [0x08004194] =0x20000748 
+  0x080040EE:  700D         STRB       R5, [R1]
+  0x080040F0:  4929         LDR        R1, =blinkModeRT         ; [PC, #164] [0x08004198] =0x20000754 
+  0x080040F2:  700D         STRB       R5, [R1]
+  0x080040F4:  4929         LDR        R1, =numberOfBlinks      ; [PC, #164] [0x0800419C] =0x200006BC 
+  0x080040F6:  600D         STR        R5, [R1]
+  0x080040F8:  4929         LDR        R1, =blinkCounter        ; [PC, #164] [0x080041A0] =0x200006EC 
+  0x080040FA:  600D         STR        R5, [R1]
+  0x080040FC:  4929         LDR        R1, =pauseTime           ; [PC, #164] [0x080041A4] =0x20000734 
+  0x080040FE:  700D         STRB       R5, [R1]
+  0x08004100:  991E         LDR        R1, [SP, #120]
+  0x08004102:  6019         STR        R1, [R3]
+
.L250:
+  0x08004104:  4928         LDR        R1, =onTimeCounterRT     ; [PC, #160] [0x080041A8] =0x2000069C 
+  0x08004106:  6008         STR        R0, [R1]
+  0x08004108:  4833         LDR        R0, =0x08006666          ; [PC, #204] [0x080041D8] 
+  0x0800410A:  F001 F873    BL         puts                     ; 0x080051F4
+  0x0800410E:  2002         MOVS       R0, #2
+  0x08004110:  492C         LDR        R1, =smState             ; [PC, #176] [0x080041C4] =0x20000737 
+
.L251:
+  0x08004112:  7008         STRB       R0, [R1]
+
.L252:
+  0x08004114:  4C31         LDR        R4, =modbusData          ; [PC, #196] [0x080041DC] =0x20000000 
+  0x08004116:  9822         LDR        R0, [SP, #136]
+  0x08004118:  5C20         LDRB       R0, [R4, R0]
+  0x0800411A:  4931         LDR        R1, =sys_data            ; [PC, #196] [0x080041E0] =0x20000234 
+  0x0800411C:  8B49         LDRH       R1, [R1, #26]
+  0x0800411E:  2900         CMP        R1, #0
+  0x08004120:  D101         BNE        .L253                    ; 0x08004126
+  0x08004122:  F7FE FAB6    BL         .L107                    ; 0x08002692
+
.L253:
+  0x08004126:  2800         CMP        R0, #0
+  0x08004128:  D001         BEQ        .L254                    ; 0x0800412E
+  0x0800412A:  F7FE FAB2    BL         .L107                    ; 0x08002692
+
.L254:
+  0x0800412E:  48F8         LDR        R0, =sys_data            ; [PC, #0x03E0] [0x08004510] =0x20000234 
+  0x08004130:  8B40         LDRH       R0, [R0, #26]
+  0x08004132:  1E41         SUBS       R1, R0, #1
+  0x08004134:  2905         CMP        R1, #5
+  0x08004136:  D858         BHI        .L255                    ; 0x080041EA
+  0x08004138:  0049         LSLS       R1, R1, #1
+  0x0800413A:  46C0         NOP
+  0x0800413C:  4479         ADD        R1, PC
+  0x0800413E:  8889         LDRH       R1, [R1, #4]
+  0x08004140:  0049         LSLS       R1, R1, #1
+  0x08004142:  448F         ADD        PC, R1
+  0x08004144:  5D           DC.B       0x5D                     ; ']'
+  0x08004145:  00           DC.B       0x00                     ; '\0'
+  0x08004146:  4F           DC.B       0x4F                     ; 'O'
+  0x08004147:  00           DC.B       0x00                     ; '\0'
+  0x08004148:  4F           DC.B       0x4F                     ; 'O'
+  0x08004149:  00           DC.B       0x00                     ; '\0'
+  0x0800414A:  5F           DC.B       0x5F                     ; '_'
+  0x0800414B:  00           DC.B       0x00                     ; '\0'
+  0x0800414C:  59           DC.B       0x59                     ; 'Y'
+  0x0800414D:  00           DC.B       0x00                     ; '\0'
+  0x0800414E:  53           DC.B       0x53                     ; 'S'
+  0x0800414F:  01           DC.B       0x01                     ; '\x01'
+  0x08004150:  50000410     DC.W       0x50000410
+  0x08004154:  20000730     DC.W       relaisState
+  0x08004158:  20000698     DC.W       onTimeCounterSET
+  0x0800415C:  2000074C     DC.W       offTimeGN
+  0x08004160:  20000740     DC.W       onTimeGN
+  0x08004164:  080064F7     DC.W       080064F7               ; R_ARM_ABS32
+  0x08004168:  200006A4     DC.W       onTimeCounterGN
+  0x0800416C:  20000758     DC.W       blinkModeGN
+  0x08004170:  200006A8     DC.W       onTimeCounter
+  0x08004174:  50000818     DC.W       0x50000818
+  0x08004178:  20000733     DC.W       smState.145
+  0x0800417C:  000003C7     DC.W       0x000003C7
+  0x08004180:  20000744     DC.W       onTime
+  0x08004184:  20000750     DC.W       offTime
+  0x08004188:  2000075C     DC.W       alarmMode
+  0x0800418C:  200006B4     DC.W       offTimeCounterGN
+  0x08004190:  2000073C     DC.W       onTimeRT
+  0x08004194:  20000748     DC.W       offTimeRT
+  0x08004198:  20000754     DC.W       blinkModeRT
+  0x0800419C:  200006BC     DC.W       numberOfBlinks
+  0x080041A0:  200006EC     DC.W       blinkCounter
+  0x080041A4:  20000734     DC.W       pauseTime
+  0x080041A8:  2000069C     DC.W       onTimeCounterRT
+  0x080041AC:  0800674E     DC.W       0800674E               ; R_ARM_ABS32
+  0x080041B0:  080066EA     DC.W       080066EA               ; R_ARM_ABS32
+  0x080041B4:  2000073A     DC.W       buttonState
+  0x080041B8:  0800692C     DC.W       0800692C               ; R_ARM_ABS32
+  0x080041BC:  200006B0     DC.W       offTimeCounterRT
+  0x080041C0:  08006469     DC.W       08006469               ; R_ARM_ABS32
+  0x080041C4:  20000737     DC.W       smState
+  0x080041C8:  0800647B     DC.W       0800647B               ; R_ARM_ABS32
+  0x080041CC:  20000736     DC.W       smState.122
+  0x080041D0:  080066CD     DC.W       080066CD               ; R_ARM_ABS32
+  0x080041D4:  0800644B     DC.W       0800644B               ; R_ARM_ABS32
+  0x080041D8:  08006666     DC.W       08006666               ; R_ARM_ABS32
+  0x080041DC:  20000000     DC.W       modbusData
+  0x080041E0:  20000234     DC.W       sys_data
+  0x080041E4:  F7FD FAE6    BL         EEPROM_WriteDefaults     ; 0x080017B4
+  0x080041E8:  E012         B          .L259                    ; 0x08004210
+
.L255:
+  0x080041EA:  49D7         LDR        R1, =0x000004D2          ; [PC, #0x035C] [0x08004548] 
+  0x080041EC:  4288         CMP        R0, R1
+  0x080041EE:  D00C         BEQ        .L257                    ; 0x0800420A
+  0x080041F0:  49D6         LDR        R1, =0x00001552          ; [PC, #0x0358] [0x0800454C] 
+  0x080041F2:  4288         CMP        R0, R1
+  0x080041F4:  D100         BNE        .L256                    ; 0x080041F8
+  0x080041F6:  E174         B          .L288                    ; 0x080044E2
+
.L256:
+  0x080041F8:  48D5         LDR        R0, =0x080068A8          ; [PC, #0x0354] [0x08004550] 
+  0x080041FA:  F000 FFFB    BL         puts                     ; 0x080051F4
+  0x080041FE:  E007         B          .L259                    ; 0x08004210
+  0x08004200:  2000         MOVS       R0, #0
+  0x08004202:  E003         B          .L258                    ; 0x0800420C
+  0x08004204:  F7FD FAEE    BL         EEPROM_ReadDeviceParameter ; 0x080017E4
+  0x08004208:  E002         B          .L259                    ; 0x08004210
+
.L257:
+  0x0800420A:  4628         MOV        R0, R5
+
.L258:
+  0x0800420C:  F7FD FAFC    BL         EEPROM_StoreConfig       ; 0x08001808
+
.L259:
+  0x08004210:  2000         MOVS       R0, #0
+  0x08004212:  49C7         LDR        R1, =sys_data            ; [PC, #0x031C] [0x08004530] =0x20000234 
+  0x08004214:  8348         STRH       R0, [R1, #26]
+  0x08004216:  F7FE FA3C    BL         .L107                    ; 0x08002692
+
.L260:
+  0x0800421A:  9B08         LDR        R3, [SP, #32]
+  0x0800421C:  5CE3         LDRB       R3, [R4, R3]
+  0x0800421E:  9C05         LDR        R4, [SP, #20]
+  0x08004220:  00A4         LSLS       R4, R4, #2
+  0x08004222:  48C4         LDR        R0, =modbusData          ; [PC, #0x0310] [0x08004534] =0x20000000 
+  0x08004224:  5503         STRB       R3, [R0, R4]
+  0x08004226:  242B         MOVS       R4, #43
+  0x08004228:  5D04         LDRB       R4, [R0, R4]
+  0x0800422A:  9E13         LDR        R6, [SP, #76]
+  0x0800422C:  362C         ADDS       R6, #44
+  0x0800422E:  5584         STRB       R4, [R0, R6]
+  0x08004230:  2695         MOVS       R6, #149
+  0x08004232:  0076         LSLS       R6, R6, #1
+  0x08004234:  5582         STRB       R2, [R0, R6]
+  0x08004236:  2225         MOVS       R2, #37
+  0x08004238:  00D2         LSLS       R2, R2, #3
+  0x0800423A:  2606         MOVS       R6, #6
+  0x0800423C:  5286         STRH       R6, [R0, R2]
+  0x0800423E:  0049         LSLS       R1, R1, #1
+  0x08004240:  48BB         LDR        R0, =sys_data            ; [PC, #0x02EC] [0x08004530] =0x20000234 
+  0x08004242:  1842         ADDS       R2, R0, R1
+  0x08004244:  7054         STRB       R4, [R2, #1]
+  0x08004246:  4CBB         LDR        R4, =modbusData          ; [PC, #0x02EC] [0x08004534] =0x20000000 
+  0x08004248:  5443         STRB       R3, [R0, R1]
+  0x0800424A:  E078         B          .L270                    ; 0x0800433E
+
.L261:
+  0x0800424C:  901C         STR        R0, [SP, #112]
+  0x0800424E:  222A         MOVS       R2, #42
+  0x08004250:  5CA0         LDRB       R0, [R4, R2]
+  0x08004252:  2229         MOVS       R2, #41
+  0x08004254:  5CA1         LDRB       R1, [R4, R2]
+  0x08004256:  020C         LSLS       R4, R1, #8
+  0x08004258:  1824         ADDS       R4, R4, R0
+  0x0800425A:  1936         ADDS       R6, R6, R4
+  0x0800425C:  4637         MOV        R7, R6
+  0x0800425E:  3F71         SUBS       R7, #113
+  0x08004260:  236F         MOVS       R3, #111
+  0x08004262:  43DB         MVNS       R3, R3
+  0x08004264:  429F         CMP        R7, R3
+  0x08004266:  D21A         BCS        .L263                    ; 0x0800429E
+  0x08004268:  2125         MOVS       R1, #37
+  0x0800426A:  00C9         LSLS       R1, R1, #3
+  0x0800426C:  0112         LSLS       R2, R2, #4
+  0x0800426E:  4CB1         LDR        R4, =modbusData          ; [PC, #0x02C4] [0x08004534] =0x20000000 
+  0x08004270:  5262         STRH       R2, [R4, R1]
+  0x08004272:  2603         MOVS       R6, #3
+  0x08004274:  E062         B          .L269                    ; 0x0800433C
+
.L262:
+  0x08004276:  9004         STR        R0, [SP, #16]
+  0x08004278:  222A         MOVS       R2, #42
+  0x0800427A:  48AE         LDR        R0, =modbusData          ; [PC, #0x02B8] [0x08004534] =0x20000000 
+  0x0800427C:  5C86         LDRB       R6, [R0, R2]
+  0x0800427E:  2229         MOVS       R2, #41
+  0x08004280:  5C82         LDRB       R2, [R0, R2]
+  0x08004282:  9202         STR        R2, [SP, #8]
+  0x08004284:  0212         LSLS       R2, R2, #8
+  0x08004286:  9603         STR        R6, [SP, #12]
+  0x08004288:  1992         ADDS       R2, R2, R6
+  0x0800428A:  18A4         ADDS       R4, R4, R2
+  0x0800428C:  941C         STR        R4, [SP, #112]
+  0x0800428E:  3C71         SUBS       R4, #113
+  0x08004290:  266F         MOVS       R6, #111
+  0x08004292:  43F6         MVNS       R6, R6
+  0x08004294:  42B4         CMP        R4, R6
+  0x08004296:  D22E         BCS        .L266                    ; 0x080042F6
+  0x08004298:  2202         MOVS       R2, #2
+  0x0800429A:  4604         MOV        R4, R0
+  0x0800429C:  E4B1         B          .L225                    ; 0x08003C02
+
.L263:
+  0x0800429E:  9003         STR        R0, [SP, #12]
+  0x080042A0:  0042         LSLS       R2, R0, #1
+  0x080042A2:  9104         STR        R1, [SP, #16]
+  0x080042A4:  024B         LSLS       R3, R1, #9
+  0x080042A6:  189A         ADDS       R2, R3, R2
+  0x080042A8:  4BA1         LDR        R3, =sys_data            ; [PC, #0x0284] [0x08004530] =0x20000234 
+  0x080042AA:  189F         ADDS       R7, R3, R2
+  0x080042AC:  4AA1         LDR        R2, =modbusData          ; [PC, #0x0284] [0x08004534] =0x20000000 
+  0x080042AE:  322F         ADDS       R2, #47
+  0x080042B0:  981C         LDR        R0, [SP, #112]
+
.L264:
+  0x080042B2:  42B4         CMP        R4, R6
+  0x080042B4:  D208         BCS        .L265                    ; 0x080042C8
+  0x080042B6:  1E53         SUBS       R3, R2, #1
+  0x080042B8:  781B         LDRB       R3, [R3]
+  0x080042BA:  707B         STRB       R3, [R7, #1]
+  0x080042BC:  7813         LDRB       R3, [R2]
+  0x080042BE:  703B         STRB       R3, [R7]
+  0x080042C0:  1C92         ADDS       R2, R2, #2
+  0x080042C2:  1CBF         ADDS       R7, R7, #2
+  0x080042C4:  1C64         ADDS       R4, R4, #1
+  0x080042C6:  E7F4         B          .L264                    ; 0x080042B2
+
.L265:
+  0x080042C8:  9A05         LDR        R2, [SP, #20]
+  0x080042CA:  0092         LSLS       R2, R2, #2
+  0x080042CC:  4C99         LDR        R4, =modbusData          ; [PC, #0x0264] [0x08004534] =0x20000000 
+  0x080042CE:  54A0         STRB       R0, [R4, R2]
+  0x080042D0:  9B13         LDR        R3, [SP, #76]
+  0x080042D2:  4619         MOV        R1, R3
+  0x080042D4:  312C         ADDS       R1, #44
+  0x080042D6:  2200         MOVS       R2, #0
+  0x080042D8:  5462         STRB       R2, [R4, R1]
+  0x080042DA:  2195         MOVS       R1, #149
+  0x080042DC:  0049         LSLS       R1, R1, #1
+  0x080042DE:  9803         LDR        R0, [SP, #12]
+  0x080042E0:  5460         STRB       R0, [R4, R1]
+  0x080042E2:  4619         MOV        R1, R3
+  0x080042E4:  312A         ADDS       R1, #42
+  0x080042E6:  9804         LDR        R0, [SP, #16]
+  0x080042E8:  5460         STRB       R0, [R4, R1]
+  0x080042EA:  2125         MOVS       R1, #37
+  0x080042EC:  00C9         LSLS       R1, R1, #3
+  0x080042EE:  981A         LDR        R0, [SP, #104]
+  0x080042F0:  5460         STRB       R0, [R4, R1]
+  0x080042F2:  2606         MOVS       R6, #6
+  0x080042F4:  E022         B          .L269                    ; 0x0800433C
+
.L266:
+  0x080042F6:  9B13         LDR        R3, [SP, #76]
+  0x080042F8:  332A         ADDS       R3, #42
+  0x080042FA:  9C04         LDR        R4, [SP, #16]
+  0x080042FC:  0064         LSLS       R4, R4, #1
+  0x080042FE:  54C4         STRB       R4, [R0, R3]
+  0x08004300:  2325         MOVS       R3, #37
+  0x08004302:  00DB         LSLS       R3, R3, #3
+  0x08004304:  2403         MOVS       R4, #3
+  0x08004306:  54C4         STRB       R4, [R0, R3]
+  0x08004308:  9803         LDR        R0, [SP, #12]
+  0x0800430A:  0043         LSLS       R3, R0, #1
+  0x0800430C:  9802         LDR        R0, [SP, #8]
+  0x0800430E:  0244         LSLS       R4, R0, #9
+  0x08004310:  18E3         ADDS       R3, R4, R3
+  0x08004312:  4C87         LDR        R4, =sys_data            ; [PC, #0x021C] [0x08004530] =0x20000234 
+  0x08004314:  18E3         ADDS       R3, R4, R3
+
.L267:
+  0x08004316:  981C         LDR        R0, [SP, #112]
+  0x08004318:  4282         CMP        R2, R0
+  0x0800431A:  D20D         BCS        .L268                    ; 0x08004338
+  0x0800431C:  4885         LDR        R0, =modbusData          ; [PC, #0x0214] [0x08004534] =0x20000000 
+  0x0800431E:  1844         ADDS       R4, R0, R1
+  0x08004320:  185E         ADDS       R6, R3, R1
+  0x08004322:  7876         LDRB       R6, [R6, #1]
+  0x08004324:  2795         MOVS       R7, #149
+  0x08004326:  007F         LSLS       R7, R7, #1
+  0x08004328:  55E6         STRB       R6, [R4, R7]
+  0x0800432A:  5C5E         LDRB       R6, [R3, R1]
+  0x0800432C:  9F13         LDR        R7, [SP, #76]
+  0x0800432E:  372C         ADDS       R7, #44
+  0x08004330:  55E6         STRB       R6, [R4, R7]
+  0x08004332:  1C89         ADDS       R1, R1, #2
+  0x08004334:  1C52         ADDS       R2, R2, #1
+  0x08004336:  E7EE         B          .L267                    ; 0x08004316
+
.L268:
+  0x08004338:  1CCE         ADDS       R6, R1, #3
+  0x0800433A:  4C7E         LDR        R4, =modbusData          ; [PC, #0x01F8] [0x08004534] =0x20000000 
+
.L269:
+  0x0800433C:  9F0C         LDR        R7, [SP, #48]
+
.L270:
+  0x0800433E:  19E7         ADDS       R7, R4, R7
+  0x08004340:  4638         MOV        R0, R7
+  0x08004342:  4631         MOV        R1, R6
+  0x08004344:  F000 F988    BL         mbCrc16                  ; 0x08004658
+  0x08004348:  55B8         STRB       R0, [R7, R6]
+  0x0800434A:  990E         LDR        R1, [SP, #56]
+  0x0800434C:  9A22         LDR        R2, [SP, #136]
+  0x0800434E:  54A1         STRB       R1, [R4, R2]
+  0x08004350:  19B9         ADDS       R1, R7, R6
+  0x08004352:  0A00         LSRS       R0, R0, #8
+  0x08004354:  7048         STRB       R0, [R1, #1]
+  0x08004356:  1CB0         ADDS       R0, R6, #2
+  0x08004358:  9911         LDR        R1, [SP, #68]
+  0x0800435A:  5060         STR        R0, [R4, R1]
+  0x0800435C:  6826         LDR        R6, [R4]
+  0x0800435E:  990D         LDR        R1, [SP, #52]
+  0x08004360:  5871         LDR        R1, [R6, R1]
+  0x08004362:  2920         CMP        R1, #32
+  0x08004364:  D13B         BNE        .L273                    ; 0x080043DE
+  0x08004366:  B283         UXTH       R3, R0
+  0x08004368:  2B00         CMP        R3, #0
+  0x0800436A:  D038         BEQ        .L273                    ; 0x080043DE
+  0x0800436C:  68B1         LDR        R1, [R6, #8]
+  0x0800436E:  9A14         LDR        R2, [SP, #80]
+  0x08004370:  4291         CMP        R1, R2
+  0x08004372:  D102         BNE        .L271                    ; 0x0800437A
+  0x08004374:  6931         LDR        R1, [R6, #16]
+  0x08004376:  2900         CMP        R1, #0
+  0x08004378:  D031         BEQ        .L273                    ; 0x080043DE
+
.L271:
+  0x0800437A:  4632         MOV        R2, R6
+  0x0800437C:  3254         ADDS       R2, #84
+  0x0800437E:  4634         MOV        R4, R6
+  0x08004380:  3488         ADDS       R4, #136
+  0x08004382:  8050         STRH       R0, [R2, #2]
+  0x08004384:  2100         MOVS       R1, #0
+  0x08004386:  60A1         STR        R1, [R4, #8]
+  0x08004388:  8010         STRH       R0, [R2]
+  0x0800438A:  6537         STR        R7, [R6, #80]
+  0x0800438C:  2021         MOVS       R0, #33
+  0x0800438E:  6020         STR        R0, [R4]
+  0x08004390:  6FF0         LDR        R0, [R6, #124]
+  0x08004392:  2800         CMP        R0, #0
+  0x08004394:  D014         BEQ        .L272                    ; 0x080043C0
+  0x08004396:  931C         STR        R3, [SP, #112]
+  0x08004398:  4B69         LDR        R3, =UART_DMATxHalfCplt  ; [PC, #0x01A4] [0x08004540] =0x08005813 
+  0x0800439A:  4A6A         LDR        R2, =UART_DMATransmitCplt ; [PC, #0x01A8] [0x08004544] =0x08001501 
+  0x0800439C:  62C2         STR        R2, [R0, #44]
+  0x0800439E:  6303         STR        R3, [R0, #48]
+  0x080043A0:  4A66         LDR        R2, =UART_DMAError       ; [PC, #0x0198] [0x0800453C] =0x08005815 
+  0x080043A2:  6342         STR        R2, [R0, #52]
+  0x080043A4:  6381         STR        R1, [R0, #56]
+  0x080043A6:  6832         LDR        R2, [R6]
+  0x080043A8:  3228         ADDS       R2, #40
+  0x080043AA:  4639         MOV        R1, R7
+  0x080043AC:  9B1C         LDR        R3, [SP, #112]
+  0x080043AE:  F7FC FB39    BL         HAL_DMA_Start_IT         ; 0x08000A24
+  0x080043B2:  2800         CMP        R0, #0
+  0x080043B4:  D004         BEQ        .L272                    ; 0x080043C0
+  0x080043B6:  981A         LDR        R0, [SP, #104]
+  0x080043B8:  60A0         STR        R0, [R4, #8]
+  0x080043BA:  9820         LDR        R0, [SP, #128]
+  0x080043BC:  6020         STR        R0, [R4]
+  0x080043BE:  E00E         B          .L273                    ; 0x080043DE
+
.L272:
+  0x080043C0:  6830         LDR        R0, [R6]
+  0x080043C2:  9907         LDR        R1, [SP, #28]
+  0x080043C4:  6201         STR        R1, [R0, #32]
+  0x080043C6:  F3EF 8010    MRS        R0, PRIMASK
+  0x080043CA:  2101         MOVS       R1, #1
+  0x080043CC:  F381 8810    MSR        PRIMASK, R1
+  0x080043D0:  6831         LDR        R1, [R6]
+  0x080043D2:  688A         LDR        R2, [R1, #8]
+  0x080043D4:  9B0A         LDR        R3, [SP, #40]
+  0x080043D6:  431A         ORRS       R2, R3
+  0x080043D8:  608A         STR        R2, [R1, #8]
+  0x080043DA:  F380 8810    MSR        PRIMASK, R0
+
.L273:
+  0x080043DE:  2000         MOVS       R0, #0
+  0x080043E0:  4954         LDR        R1, =modbusData          ; [PC, #0x0150] [0x08004534] =0x20000000 
+  0x080043E2:  9A21         LDR        R2, [SP, #132]
+  0x080043E4:  5088         STR        R0, [R1, R2]
+  0x080043E6:  7508         STRB       R0, [R1, #20]
+  0x080043E8:  F7FE F967    BL         .L109                    ; 0x080026BA
+
.L274:
+  0x080043EC:  E7FE         B          .L274                    ; 0x080043EC
+
.L275:
+  0x080043EE:  484C         LDR        R0, =SystemCoreClock     ; [PC, #0x0130] [0x08004520] =0x20000BA4 
+  0x080043F0:  6800         LDR        R0, [R0]
+  0x080043F2:  494D         LDR        R1, =0x00030D40          ; [PC, #0x0134] [0x08004528] 
+  0x080043F4:  F001 FE47    BL         __aeabi_uidiv            ; 0x08006086
+  0x080043F8:  9A03         LDR        R2, [SP, #12]
+  0x080043FA:  9B21         LDR        R3, [SP, #132]
+  0x080043FC:  1C40         ADDS       R0, R0, #1
+
.L276:
+  0x080043FE:  9029         STR        R0, [SP, #164]
+  0x08004400:  9829         LDR        R0, [SP, #164]
+  0x08004402:  2800         CMP        R0, #0
+  0x08004404:  D101         BNE        .L277                    ; 0x0800440A
+  0x08004406:  F7FE F8CE    BL         .L98                     ; 0x080025A6
+
.L277:
+  0x0800440A:  9829         LDR        R0, [SP, #164]
+  0x0800440C:  1E40         SUBS       R0, R0, #1
+  0x0800440E:  E7F6         B          .L276                    ; 0x080043FE
+
.L278:
+  0x08004410:  4842         LDR        R0, =uwTick              ; [PC, #0x0108] [0x0800451C] =0x2000068C 
+  0x08004412:  6800         LDR        R0, [R0]
+
.L279:
+  0x08004414:  6821         LDR        R1, [R4]
+  0x08004416:  07C9         LSLS       R1, R1, #31
+  0x08004418:  D001         BEQ        .L280                    ; 0x0800441E
+  0x0800441A:  F7FE F8C9    BL         .L99                     ; 0x080025B0
+
.L280:
+  0x0800441E:  68A1         LDR        R1, [R4, #8]
+  0x08004420:  07C9         LSLS       R1, R1, #31
+  0x08004422:  D105         BNE        .L281                    ; 0x08004430
+  0x08004424:  68A1         LDR        R1, [R4, #8]
+  0x08004426:  4A3F         LDR        R2, =0x7FFFFFE8          ; [PC, #252] [0x08004524] 
+  0x08004428:  4011         ANDS       R1, R2
+  0x0800442A:  9A03         LDR        R2, [SP, #12]
+  0x0800442C:  4311         ORRS       R1, R2
+  0x0800442E:  60A1         STR        R1, [R4, #8]
+
.L281:
+  0x08004430:  493A         LDR        R1, =uwTick              ; [PC, #232] [0x0800451C] =0x2000068C 
+  0x08004432:  6809         LDR        R1, [R1]
+  0x08004434:  1A09         SUBS       R1, R1, R0
+  0x08004436:  2903         CMP        R1, #3
+  0x08004438:  D3EC         BCC        .L279                    ; 0x08004414
+  0x0800443A:  F7FE F8A0    BL         .L96                     ; 0x0800257E
+
.L282:
+  0x0800443E:  4001         ANDS       R1, R0
+  0x08004440:  9802         LDR        R0, [SP, #8]
+  0x08004442:  4301         ORRS       R1, R0
+  0x08004444:  60A1         STR        R1, [R4, #8]
+  0x08004446:  1D18         ADDS       R0, R3, #4
+  0x08004448:  08C3         LSRS       R3, R0, #3
+  0x0800444A:  6920         LDR        R0, [R4, #16]
+  0x0800444C:  0F80         LSRS       R0, R0, #30
+  0x0800444E:  4F32         LDR        R7, =0x000003C7          ; [PC, #200] [0x08004518] 
+  0x08004450:  D114         BNE        .L284                    ; 0x0800447C
+  0x08004452:  9803         LDR        R0, [SP, #12]
+  0x08004454:  0480         LSLS       R0, R0, #18
+  0x08004456:  4935         LDR        R1, =0x40012708          ; [PC, #212] [0x0800452C] 
+  0x08004458:  6809         LDR        R1, [R1]
+  0x0800445A:  4001         ANDS       R1, R0
+  0x0800445C:  0C89         LSRS       R1, R1, #18
+  0x0800445E:  2907         CMP        R1, #7
+  0x08004460:  D30C         BCC        .L284                    ; 0x0800447C
+  0x08004462:  1EC8         SUBS       R0, R1, #3
+  0x08004464:  9902         LDR        R1, [SP, #8]
+  0x08004466:  4081         LSLS       R1, R0
+  0x08004468:  9130         STR        R1, [SP, #192]
+  0x0800446A:  9830         LDR        R0, [SP, #192]
+  0x0800446C:  0841         LSRS       R1, R0, #1
+
.L283:
+  0x0800446E:  9130         STR        R1, [SP, #192]
+  0x08004470:  9830         LDR        R0, [SP, #192]
+  0x08004472:  2800         CMP        R0, #0
+  0x08004474:  D002         BEQ        .L284                    ; 0x0800447C
+  0x08004476:  9830         LDR        R0, [SP, #192]
+  0x08004478:  1E41         SUBS       R1, R0, #1
+  0x0800447A:  E7F8         B          .L283                    ; 0x0800446E
+
.L284:
+  0x0800447C:  6810         LDR        R0, [R2]
+  0x0800447E:  217F         MOVS       R1, #127
+  0x08004480:  4388         BICS       R0, R1
+  0x08004482:  4318         ORRS       R0, R3
+  0x08004484:  6010         STR        R0, [R2]
+  0x08004486:  68A0         LDR        R0, [R4, #8]
+  0x08004488:  4926         LDR        R1, =0x7FFFFFE8          ; [PC, #152] [0x08004524] 
+  0x0800448A:  4008         ANDS       R0, R1
+  0x0800448C:  9912         LDR        R1, [SP, #72]
+  0x0800448E:  4308         ORRS       R0, R1
+  0x08004490:  60A0         STR        R0, [R4, #8]
+  0x08004492:  4822         LDR        R0, =uwTick              ; [PC, #136] [0x0800451C] =0x2000068C 
+  0x08004494:  6802         LDR        R2, [R0]
+  0x08004496:  9B21         LDR        R3, [SP, #132]
+
.L285:
+  0x08004498:  68A0         LDR        R0, [R4, #8]
+  0x0800449A:  07C0         LSLS       R0, R0, #31
+  0x0800449C:  D012         BEQ        .L286                    ; 0x080044C4
+  0x0800449E:  481F         LDR        R0, =uwTick              ; [PC, #124] [0x0800451C] =0x2000068C 
+  0x080044A0:  6800         LDR        R0, [R0]
+  0x080044A2:  1A80         SUBS       R0, R0, R2
+  0x080044A4:  2803         CMP        R0, #3
+  0x080044A6:  D3F7         BCC        .L285                    ; 0x08004498
+  0x080044A8:  68A0         LDR        R0, [R4, #8]
+  0x080044AA:  07C0         LSLS       R0, R0, #31
+  0x080044AC:  D0F4         BEQ        .L285                    ; 0x08004498
+  0x080044AE:  6DB0         LDR        R0, [R6, #88]
+  0x080044B0:  991A         LDR        R1, [SP, #104]
+  0x080044B2:  4308         ORRS       R0, R1
+  0x080044B4:  65B0         STR        R0, [R6, #88]
+  0x080044B6:  6DF0         LDR        R0, [R6, #92]
+  0x080044B8:  9902         LDR        R1, [SP, #8]
+  0x080044BA:  4308         ORRS       R0, R1
+  0x080044BC:  65F0         STR        R0, [R6, #92]
+  0x080044BE:  4628         MOV        R0, R5
+  0x080044C0:  F7FE F83C    BL         .L93                     ; 0x0800253C
+
.L286:
+  0x080044C4:  68E0         LDR        R0, [R4, #12]
+  0x080044C6:  9901         LDR        R1, [SP, #4]
+  0x080044C8:  4308         ORRS       R0, R1
+  0x080044CA:  60E0         STR        R0, [R4, #12]
+  0x080044CC:  6DB1         LDR        R1, [R6, #88]
+  0x080044CE:  9802         LDR        R0, [SP, #8]
+  0x080044D0:  4301         ORRS       R1, R0
+  0x080044D2:  9812         LDR        R0, [SP, #72]
+  0x080044D4:  4381         BICS       R1, R0
+  0x080044D6:  F7FE F823    BL         .L91                     ; 0x08002520
+
.L287:
+  0x080044DA:  2000         MOVS       R0, #0
+  0x080044DC:  7008         STRB       R0, [R1]
+  0x080044DE:  F000 F839    BL         JumpToBootloader         ; 0x08004554
+
.L288:
+  0x080044E2:  480C         LDR        R0, =bootLoaderMark      ; [PC, #48] [0x08004514] =0x20000B7C 
+  0x080044E4:  7005         STRB       R5, [R0]
+  0x080044E6:  F001 FC90    BL         HAL_NVIC_SystemReset     ; 0x08005E0A
+
.L289:
+  0x080044EA:  3658         ADDS       R6, #88
+  0x080044EC:  E007         B          .L291                    ; 0x080044FE
+
.L290:
+  0x080044EE:  6DB0         LDR        R0, [R6, #88]
+  0x080044F0:  2110         MOVS       R1, #16
+  0x080044F2:  4301         ORRS       R1, R0
+  0x080044F4:  43B9         BICS       R1, R7
+  0x080044F6:  65B1         STR        R1, [R6, #88]
+  0x080044F8:  6DF0         LDR        R0, [R6, #92]
+  0x080044FA:  365C         ADDS       R6, #92
+  0x080044FC:  4629         MOV        R1, R5
+
.L291:
+  0x080044FE:  4301         ORRS       R1, R0
+  0x08004500:  6031         STR        R1, [R6]
+  0x08004502:  F7FD FE18    BL         .L61                     ; 0x08002136
+
.L292:
+  0x08004506:  480C         LDR        R0, =0x0800660A          ; [PC, #48] [0x08004538] 
+  0x08004508:  F000 FE74    BL         puts                     ; 0x080051F4
+  0x0800450C:  F001 FCED    BL         Error_Handler            ; 0x08005EEA
+  0x08004510:  20000234     DC.W       sys_data
+  0x08004514:  20000B7C     DC.W       bootLoaderMark
+  0x08004518:  000003C7     DC.W       0x000003C7
+  0x0800451C:  2000068C     DC.W       uwTick
+  0x08004520:  20000BA4     DC.W       SystemCoreClock
+  0x08004524:  7FFFFFE8     DC.W       0x7FFFFFE8
+  0x08004528:  00030D40     DC.W       0x00030D40
+  0x0800452C:  40012708     DC.W       0x40012708
+  0x08004530:  20000234     DC.W       sys_data
+  0x08004534:  20000000     DC.W       modbusData
+  0x08004538:  0800660A     DC.W       0800660A               ; R_ARM_ABS32
+  0x0800453C:  08005815     DC.W       UART_DMAError
+  0x08004540:  08005813     DC.W       UART_DMATxHalfCplt
+  0x08004544:  08001501     DC.W       UART_DMATransmitCplt
+  0x08004548:  000004D2     DC.W       0x000004D2
+  0x0800454C:  00001552     DC.W       0x00001552
+  0x08004550:  080068A8     DC.W       080068A8               ; R_ARM_ABS32
+
+

Section .text.JumpToBootloader from PowerPro_lto.o, size=92, align=4

+
+
JumpToBootloader:
+  0x08004554:  B082         SUB        SP, SP, #8
+  0x08004556:  B672         CPSID      i
+  0x08004558:  2000         MOVS       R0, #0
+  0x0800455A:  43C0         MVNS       R0, R0
+  0x0800455C:  490E         LDR        R1, =0xE000E180          ; [PC, #56] [0x08004598] 
+  0x0800455E:  6008         STR        R0, [R1]
+  0x08004560:  490E         LDR        R1, =0xE000E280          ; [PC, #56] [0x0800459C] 
+  0x08004562:  6008         STR        R0, [R1]
+  0x08004564:  480E         LDR        R0, =0x1FFF0000          ; [PC, #56] [0x080045A0] 
+  0x08004566:  6801         LDR        R1, [R0]
+  0x08004568:  6840         LDR        R0, [R0, #4]
+  0x0800456A:  F381 8808    MSR        MSP, R1
+  0x0800456E:  490D         LDR        R1, =0x40021040          ; [PC, #52] [0x080045A4] 
+  0x08004570:  680A         LDR        R2, [R1]
+  0x08004572:  2301         MOVS       R3, #1
+  0x08004574:  431A         ORRS       R2, R3
+  0x08004576:  600A         STR        R2, [R1]
+  0x08004578:  6809         LDR        R1, [R1]
+  0x0800457A:  4019         ANDS       R1, R3
+  0x0800457C:  9101         STR        R1, [SP, #4]
+  0x0800457E:  9901         LDR        R1, [SP, #4]
+  0x08004580:  4909         LDR        R1, =0x40010000          ; [PC, #36] [0x080045A8] 
+  0x08004582:  680A         LDR        R2, [R1]
+  0x08004584:  431A         ORRS       R2, R3
+  0x08004586:  2302         MOVS       R3, #2
+  0x08004588:  439A         BICS       R2, R3
+  0x0800458A:  600A         STR        R2, [R1]
+  0x0800458C:  B662         CPSIE      i
+  0x0800458E:  4780         BLX        R0
+
.L1:
+  0x08004590:  4806         LDR        R0, =0x080065D7          ; [PC, #24] [0x080045AC] 
+  0x08004592:  F000 FE2F    BL         puts                     ; 0x080051F4
+  0x08004596:  E7FB         B          .L1                      ; 0x08004590
+  0x08004598:  E000E180     DC.W       0xE000E180
+  0x0800459C:  E000E280     DC.W       0xE000E280
+  0x080045A0:  1FFF0000     DC.W       0x1FFF0000
+  0x080045A4:  40021040     DC.W       0x40021040
+  0x080045A8:  40010000     DC.W       0x40010000
+  0x080045AC:  080065D7     DC.W       080065D7               ; R_ARM_ABS32
+
+

Section .text.HAL_UART_ErrorCallback from PowerPro_lto.o, size=168, align=4

+
+
HAL_UART_ErrorCallback:
+  0x080045B0:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080045B2:  4604         MOV        R4, R0
+  0x080045B4:  4820         LDR        R0, =modbusData          ; [PC, #128] [0x08004638] =0x20000000 
+  0x080045B6:  2101         MOVS       R1, #1
+  0x080045B8:  7501         STRB       R1, [R0, #20]
+  0x080045BA:  4920         LDR        R1, =0x00000231          ; [PC, #128] [0x0800463C] 
+  0x080045BC:  2200         MOVS       R2, #0
+  0x080045BE:  5442         STRB       R2, [R0, R1]
+  0x080045C0:  215C         MOVS       R1, #92
+  0x080045C2:  5A61         LDRH       R1, [R4, R1]
+  0x080045C4:  2280         MOVS       R2, #128
+  0x080045C6:  58A2         LDR        R2, [R4, R2]
+  0x080045C8:  6812         LDR        R2, [R2]
+  0x080045CA:  6852         LDR        R2, [R2, #4]
+  0x080045CC:  1A89         SUBS       R1, R1, R2
+  0x080045CE:  2245         MOVS       R2, #69
+  0x080045D0:  00D2         LSLS       R2, R2, #3
+  0x080045D2:  5081         STR        R1, [R0, R2]
+  0x080045D4:  4625         MOV        R5, R4
+  0x080045D6:  3580         ADDS       R5, #128
+  0x080045D8:  6928         LDR        R0, [R5, #16]
+  0x080045DA:  6928         LDR        R0, [R5, #16]
+  0x080045DC:  2804         CMP        R0, #4
+  0x080045DE:  D102         BNE        .L1                      ; 0x080045E6
+  0x080045E0:  4817         LDR        R0, =0x080068B8          ; [PC, #92] [0x08004640] 
+  0x080045E2:  F000 FE61    BL         printf                   ; 0x080052A8
+
.L1:
+  0x080045E6:  6928         LDR        R0, [R5, #16]
+  0x080045E8:  2801         CMP        R0, #1
+  0x080045EA:  D102         BNE        .L2                      ; 0x080045F2
+  0x080045EC:  4815         LDR        R0, =0x080068C8          ; [PC, #84] [0x08004644] 
+  0x080045EE:  F000 FE5B    BL         printf                   ; 0x080052A8
+
.L2:
+  0x080045F2:  6928         LDR        R0, [R5, #16]
+  0x080045F4:  2802         CMP        R0, #2
+  0x080045F6:  D102         BNE        .L3                      ; 0x080045FE
+  0x080045F8:  4813         LDR        R0, =0x080068D8          ; [PC, #76] [0x08004648] 
+  0x080045FA:  F000 FE55    BL         printf                   ; 0x080052A8
+
.L3:
+  0x080045FE:  6928         LDR        R0, [R5, #16]
+  0x08004600:  2810         CMP        R0, #16
+  0x08004602:  D102         BNE        .L4                      ; 0x0800460A
+  0x08004604:  4811         LDR        R0, =0x080065E8          ; [PC, #68] [0x0800464C] 
+  0x08004606:  F000 FE4F    BL         printf                   ; 0x080052A8
+
.L4:
+  0x0800460A:  6928         LDR        R0, [R5, #16]
+  0x0800460C:  2810         CMP        R0, #16
+  0x0800460E:  D102         BNE        .L5                      ; 0x08004616
+  0x08004610:  480E         LDR        R0, =0x080065E8          ; [PC, #56] [0x0800464C] 
+  0x08004612:  F000 FE49    BL         printf                   ; 0x080052A8
+
.L5:
+  0x08004616:  6928         LDR        R0, [R5, #16]
+  0x08004618:  2808         CMP        R0, #8
+  0x0800461A:  D102         BNE        .L6                      ; 0x08004622
+  0x0800461C:  480C         LDR        R0, =0x080065F9          ; [PC, #48] [0x08004650] 
+  0x0800461E:  F000 FE43    BL         printf                   ; 0x080052A8
+
.L6:
+  0x08004622:  6DA1         LDR        R1, [R4, #88]
+  0x08004624:  4620         MOV        R0, R4
+  0x08004626:  F7FC FF93    BL         HAL_UART_Receive_DMA     ; 0x08001550
+  0x0800462A:  2800         CMP        R0, #0
+  0x0800462C:  D002         BEQ        .L7                      ; 0x08004634
+  0x0800462E:  4809         LDR        R0, =0x0800623C          ; [PC, #36] [0x08004654] 
+  0x08004630:  F000 FE3A    BL         printf                   ; 0x080052A8
+
.L7:
+  0x08004634:  BDB0         POP        {R4-R5, R7, PC}
+  0x08004636:  46C0         NOP
+  0x08004638:  20000000     DC.W       modbusData
+  0x0800463C:  00000231     DC.W       0x00000231
+  0x08004640:  080068B8     DC.W       080068B8               ; R_ARM_ABS32
+  0x08004644:  080068C8     DC.W       080068C8               ; R_ARM_ABS32
+  0x08004648:  080068D8     DC.W       080068D8               ; R_ARM_ABS32
+  0x0800464C:  080065E8     DC.W       080065E8               ; R_ARM_ABS32
+  0x08004650:  080065F9     DC.W       080065F9               ; R_ARM_ABS32
+  0x08004654:  0800623C     DC.W       0800623C               ; R_ARM_ABS32
+
+

Section .text.mbCrc16 from PowerPro_lto.o, size=56, align=4

+
+
mbCrc16:
+  0x08004658:  B530         PUSH       {R4-R5, LR}
+  0x0800465A:  2200         MOVS       R2, #0
+  0x0800465C:  4B0A         LDR        R3, =0x0000FFFF          ; [PC, #40] [0x08004688] 
+
.L1:
+  0x0800465E:  428A         CMP        R2, R1
+  0x08004660:  D00F         BEQ        .L5                      ; 0x08004682
+  0x08004662:  5C84         LDRB       R4, [R0, R2]
+  0x08004664:  4063         EORS       R3, R4
+  0x08004666:  2407         MOVS       R4, #7
+  0x08004668:  43E4         MVNS       R4, R4
+
.L2:
+  0x0800466A:  2C00         CMP        R4, #0
+  0x0800466C:  D007         BEQ        .L4                      ; 0x0800467E
+  0x0800466E:  085D         LSRS       R5, R3, #1
+  0x08004670:  07DB         LSLS       R3, R3, #31
+  0x08004672:  D001         BEQ        .L3                      ; 0x08004678
+  0x08004674:  4B05         LDR        R3, =0x0000A001          ; [PC, #20] [0x0800468C] 
+  0x08004676:  405D         EORS       R5, R3
+
.L3:
+  0x08004678:  462B         MOV        R3, R5
+  0x0800467A:  1C64         ADDS       R4, R4, #1
+  0x0800467C:  E7F5         B          .L2                      ; 0x0800466A
+
.L4:
+  0x0800467E:  1C52         ADDS       R2, R2, #1
+  0x08004680:  E7ED         B          .L1                      ; 0x0800465E
+
.L5:
+  0x08004682:  B298         UXTH       R0, R3
+  0x08004684:  BD30         POP        {R4-R5, PC}
+  0x08004686:  46C0         NOP
+  0x08004688:  0000FFFF     DC.W       0x0000FFFF
+  0x0800468C:  0000A001     DC.W       0x0000A001
+
+

Section .text.MODE_SECONDARYPROTECTION_Exec from PowerPro_lto.o, size=1660, align=4

+
+
MODE_SECONDARYPROTECTION_Exec:
+  0x08004690:  B5F0         PUSH       {R4-R7, LR}
+  0x08004692:  B085         SUB        SP, SP, #20
+  0x08004694:  4F07         LDR        R7, =autoRetryMode       ; [PC, #28] [0x080046B4] =0x200006F4 
+  0x08004696:  6038         STR        R0, [R7]
+  0x08004698:  4D07         LDR        R5, =0x50000418          ; [PC, #28] [0x080046B8] 
+  0x0800469A:  4628         MOV        R0, R5
+  0x0800469C:  3808         SUBS       R0, #8
+  0x0800469E:  6800         LDR        R0, [R0]
+  0x080046A0:  0740         LSLS       R0, R0, #29
+  0x080046A2:  0FC0         LSRS       R0, R0, #31
+  0x080046A4:  4C05         LDR        R4, =smState.160         ; [PC, #20] [0x080046BC] =0x20000732 
+  0x080046A6:  7821         LDRB       R1, [R4]
+  0x080046A8:  4479         ADD        R1, PC
+  0x080046AA:  7909         LDRB       R1, [R1, #4]
+  0x080046AC:  0049         LSLS       R1, R1, #1
+  0x080046AE:  448F         ADD        PC, R1
+  0x080046B0:  07           DC.B       0x07                     ; '\x07'
+  0x080046B1:  A2           DC.B       0xA2                     ; '\xA2'
+  0x080046B2:  2C           DC.B       0x2C                     ; ','
+  0x080046B3:  91           DC.B       0x91                     ; '\x91'
+  0x080046B4:  200006F4     DC.W       autoRetryMode
+  0x080046B8:  50000418     DC.W       0x50000418
+  0x080046BC:  20000732     DC.W       smState.160
+  0x080046C0:  49DA         LDR        R1, =0x50000010          ; [PC, #0x0368] [0x08004A2C] 
+  0x080046C2:  680A         LDR        R2, [R1]
+  0x080046C4:  07D2         LSLS       R2, R2, #31
+  0x080046C6:  D000         BEQ        .L1                      ; 0x080046CA
+  0x080046C8:  6809         LDR        R1, [R1]
+
.L1:
+  0x080046CA:  4AD9         LDR        R2, =buttonState         ; [PC, #0x0364] [0x08004A30] =0x2000073A 
+  0x080046CC:  7811         LDRB       R1, [R2]
+  0x080046CE:  2901         CMP        R1, #1
+  0x080046D0:  D000         BEQ        .L2                      ; 0x080046D4
+  0x080046D2:  E27C         B          .L23                     ; 0x08004BCE
+
.L2:
+  0x080046D4:  2800         CMP        R0, #0
+  0x080046D6:  D000         BEQ        .L3                      ; 0x080046DA
+  0x080046D8:  E258         B          .L21                     ; 0x08004B8C
+
.L3:
+  0x080046DA:  2020         MOVS       R0, #32
+  0x080046DC:  6028         STR        R0, [R5]
+  0x080046DE:  2000         MOVS       R0, #0
+  0x080046E0:  7010         STRB       R0, [R2]
+  0x080046E2:  207D         MOVS       R0, #125
+  0x080046E4:  0080         LSLS       R0, R0, #2
+  0x080046E6:  4AD3         LDR        R2, =onTimeCounter       ; [PC, #0x034C] [0x08004A34] =0x200006A8 
+  0x080046E8:  6010         STR        R0, [R2]
+  0x080046EA:  48D3         LDR        R0, =onTimeRT            ; [PC, #0x034C] [0x08004A38] =0x2000073C 
+  0x080046EC:  7001         STRB       R1, [R0]
+  0x080046EE:  48D3         LDR        R0, =offTimeRT           ; [PC, #0x034C] [0x08004A3C] =0x20000748 
+  0x080046F0:  7001         STRB       R1, [R0]
+  0x080046F2:  48D3         LDR        R0, =blinkModeRT         ; [PC, #0x034C] [0x08004A40] =0x20000754 
+  0x080046F4:  7001         STRB       R1, [R0]
+  0x080046F6:  48D3         LDR        R0, =numberOfBlinks      ; [PC, #0x034C] [0x08004A44] =0x200006BC 
+  0x080046F8:  2703         MOVS       R7, #3
+  0x080046FA:  6007         STR        R7, [R0]
+  0x080046FC:  48D2         LDR        R0, =blinkCounter        ; [PC, #0x0348] [0x08004A48] =0x200006EC 
+  0x080046FE:  6007         STR        R7, [R0]
+  0x08004700:  03CA         LSLS       R2, R1, #15
+  0x08004702:  48D2         LDR        R0, =0x080067AD          ; [PC, #0x0348] [0x08004A4C] 
+  0x08004704:  4BD2         LDR        R3, =onTimeCounterRT     ; [PC, #0x0348] [0x08004A50] =0x2000069C 
+  0x08004706:  4ED3         LDR        R6, =pauseTime           ; [PC, #0x034C] [0x08004A54] =0x20000734 
+  0x08004708:  E257         B          .L22                     ; 0x08004BBA
+  0x0800470A:  2800         CMP        R0, #0
+  0x0800470C:  D134         BNE        .L4                      ; 0x08004778
+  0x0800470E:  2008         MOVS       R0, #8
+  0x08004710:  6128         STR        R0, [R5, #16]
+  0x08004712:  2010         MOVS       R0, #16
+  0x08004714:  6028         STR        R0, [R5]
+  0x08004716:  49D0         LDR        R1, =relaisState         ; [PC, #0x0340] [0x08004A58] =0x20000730 
+  0x08004718:  2000         MOVS       R0, #0
+  0x0800471A:  7008         STRB       R0, [R1]
+  0x0800471C:  49CF         LDR        R1, =onTimeCounterRESET  ; [PC, #0x033C] [0x08004A5C] =0x200006A0 
+  0x0800471E:  2232         MOVS       R2, #50
+  0x08004720:  600A         STR        R2, [R1]
+  0x08004722:  2120         MOVS       R1, #32
+  0x08004724:  6029         STR        R1, [R5]
+  0x08004726:  217D         MOVS       R1, #125
+  0x08004728:  0089         LSLS       R1, R1, #2
+  0x0800472A:  4AC2         LDR        R2, =onTimeCounter       ; [PC, #0x0308] [0x08004A34] =0x200006A8 
+  0x0800472C:  6011         STR        R1, [R2]
+  0x0800472E:  2101         MOVS       R1, #1
+  0x08004730:  038B         LSLS       R3, R1, #14
+  0x08004732:  4ACB         LDR        R2, =0x50000818          ; [PC, #0x032C] [0x08004A60] 
+  0x08004734:  6113         STR        R3, [R2, #16]
+  0x08004736:  4BCB         LDR        R3, =offTimeCounterGN    ; [PC, #0x032C] [0x08004A64] =0x200006B4 
+  0x08004738:  6018         STR        R0, [R3]
+  0x0800473A:  4BCB         LDR        R3, =blinkModeGN         ; [PC, #0x032C] [0x08004A68] =0x20000758 
+  0x0800473C:  7018         STRB       R0, [R3]
+  0x0800473E:  4BCB         LDR        R3, =onTimeCounterGN     ; [PC, #0x032C] [0x08004A6C] =0x200006A4 
+  0x08004740:  6018         STR        R0, [R3]
+  0x08004742:  4BBD         LDR        R3, =onTimeRT            ; [PC, #0x02F4] [0x08004A38] =0x2000073C 
+  0x08004744:  7019         STRB       R1, [R3]
+  0x08004746:  4BBD         LDR        R3, =offTimeRT           ; [PC, #0x02F4] [0x08004A3C] =0x20000748 
+  0x08004748:  7019         STRB       R1, [R3]
+  0x0800474A:  4BBD         LDR        R3, =blinkModeRT         ; [PC, #0x02F4] [0x08004A40] =0x20000754 
+  0x0800474C:  7019         STRB       R1, [R3]
+  0x0800474E:  4BBD         LDR        R3, =numberOfBlinks      ; [PC, #0x02F4] [0x08004A44] =0x200006BC 
+  0x08004750:  2603         MOVS       R6, #3
+  0x08004752:  601E         STR        R6, [R3]
+  0x08004754:  4BBC         LDR        R3, =blinkCounter        ; [PC, #0x02F0] [0x08004A48] =0x200006EC 
+  0x08004756:  601E         STR        R6, [R3]
+  0x08004758:  4BBE         LDR        R3, =pauseTime           ; [PC, #0x02F8] [0x08004A54] =0x20000734 
+  0x0800475A:  7019         STRB       R1, [R3]
+  0x0800475C:  03C9         LSLS       R1, R1, #15
+  0x0800475E:  6011         STR        R1, [R2]
+  0x08004760:  49B3         LDR        R1, =buttonState         ; [PC, #0x02CC] [0x08004A30] =0x2000073A 
+  0x08004762:  7008         STRB       R0, [R1]
+  0x08004764:  48BA         LDR        R0, =onTimeCounterRT     ; [PC, #0x02E8] [0x08004A50] =0x2000069C 
+  0x08004766:  21C8         MOVS       R1, #200
+  0x08004768:  6001         STR        R1, [R0]
+  0x0800476A:  48C1         LDR        R0, =0x08006990          ; [PC, #0x0304] [0x08004A70] 
+  0x0800476C:  F000 FD42    BL         puts                     ; 0x080051F4
+  0x08004770:  48B6         LDR        R0, =0x080067AD          ; [PC, #0x02D8] [0x08004A4C] 
+  0x08004772:  F000 FD3F    BL         puts                     ; 0x080051F4
+  0x08004776:  7026         STRB       R6, [R4]
+
.L4:
+  0x08004778:  48AD         LDR        R0, =buttonState         ; [PC, #0x02B4] [0x08004A30] =0x2000073A 
+  0x0800477A:  7800         LDRB       R0, [R0]
+  0x0800477C:  2800         CMP        R0, #0
+  0x0800477E:  D000         BEQ        .L5                      ; 0x08004782
+  0x08004780:  E25B         B          .L25                     ; 0x08004C3A
+
.L5:
+  0x08004782:  2008         MOVS       R0, #8
+  0x08004784:  6128         STR        R0, [R5, #16]
+  0x08004786:  2010         MOVS       R0, #16
+  0x08004788:  6028         STR        R0, [R5]
+  0x0800478A:  48B3         LDR        R0, =relaisState         ; [PC, #0x02CC] [0x08004A58] =0x20000730 
+  0x0800478C:  2600         MOVS       R6, #0
+  0x0800478E:  7006         STRB       R6, [R0]
+  0x08004790:  48B2         LDR        R0, =onTimeCounterRESET  ; [PC, #0x02C8] [0x08004A5C] =0x200006A0 
+  0x08004792:  2132         MOVS       R1, #50
+  0x08004794:  6001         STR        R1, [R0]
+  0x08004796:  2020         MOVS       R0, #32
+  0x08004798:  6128         STR        R0, [R5, #16]
+  0x0800479A:  48B6         LDR        R0, =offTimeCounter      ; [PC, #0x02D8] [0x08004A74] =0x200006B8 
+  0x0800479C:  6006         STR        R6, [R0]
+  0x0800479E:  48B6         LDR        R0, =alarmMode           ; [PC, #0x02D8] [0x08004A78] =0x2000075C 
+  0x080047A0:  7006         STRB       R6, [R0]
+  0x080047A2:  48A4         LDR        R0, =onTimeCounter       ; [PC, #0x0290] [0x08004A34] =0x200006A8 
+  0x080047A4:  6006         STR        R6, [R0]
+  0x080047A6:  2001         MOVS       R0, #1
+  0x080047A8:  0381         LSLS       R1, R0, #14
+  0x080047AA:  4AAD         LDR        R2, =0x50000818          ; [PC, #0x02B4] [0x08004A60] 
+  0x080047AC:  6111         STR        R1, [R2, #16]
+  0x080047AE:  49AD         LDR        R1, =offTimeCounterGN    ; [PC, #0x02B4] [0x08004A64] =0x200006B4 
+  0x080047B0:  600E         STR        R6, [R1]
+  0x080047B2:  49AD         LDR        R1, =blinkModeGN         ; [PC, #0x02B4] [0x08004A68] =0x20000758 
+  0x080047B4:  700E         STRB       R6, [R1]
+  0x080047B6:  49AD         LDR        R1, =onTimeCounterGN     ; [PC, #0x02B4] [0x08004A6C] =0x200006A4 
+  0x080047B8:  600E         STR        R6, [R1]
+  0x080047BA:  03C0         LSLS       R0, R0, #15
+  0x080047BC:  6110         STR        R0, [R2, #16]
+  0x080047BE:  48AF         LDR        R0, =offTimeCounterRT    ; [PC, #0x02BC] [0x08004A7C] =0x200006B0 
+  0x080047C0:  6006         STR        R6, [R0]
+  0x080047C2:  489F         LDR        R0, =blinkModeRT         ; [PC, #0x027C] [0x08004A40] =0x20000754 
+  0x080047C4:  7006         STRB       R6, [R0]
+  0x080047C6:  48A2         LDR        R0, =onTimeCounterRT     ; [PC, #0x0288] [0x08004A50] =0x2000069C 
+  0x080047C8:  6006         STR        R6, [R0]
+  0x080047CA:  48AD         LDR        R0, =0x0800630D          ; [PC, #0x02B4] [0x08004A80] 
+  0x080047CC:  F000 FD12    BL         puts                     ; 0x080051F4
+  0x080047D0:  7026         STRB       R6, [R4]
+  0x080047D2:  E232         B          .L25                     ; 0x08004C3A
+  0x080047D4:  4E96         LDR        R6, =buttonState         ; [PC, #0x0258] [0x08004A30] =0x2000073A 
+  0x080047D6:  7831         LDRB       R1, [R6]
+  0x080047D8:  2901         CMP        R1, #1
+  0x080047DA:  D000         BEQ        .L6                      ; 0x080047DE
+  0x080047DC:  E181         B          .L17                     ; 0x08004AE2
+
.L6:
+  0x080047DE:  2800         CMP        R0, #0
+  0x080047E0:  D000         BEQ        .L7                      ; 0x080047E4
+  0x080047E2:  E155         B          .L16                     ; 0x08004A90
+
.L7:
+  0x080047E4:  2020         MOVS       R0, #32
+  0x080047E6:  6028         STR        R0, [R5]
+  0x080047E8:  2000         MOVS       R0, #0
+  0x080047EA:  7030         STRB       R0, [R6]
+  0x080047EC:  207D         MOVS       R0, #125
+  0x080047EE:  0080         LSLS       R0, R0, #2
+  0x080047F0:  4990         LDR        R1, =onTimeCounter       ; [PC, #0x0240] [0x08004A34] =0x200006A8 
+  0x080047F2:  6008         STR        R0, [R1]
+  0x080047F4:  E1AF         B          .L18                     ; 0x08004B56
+  0x080047F6:  217D         MOVS       R1, #125
+  0x080047F8:  008B         LSLS       R3, R1, #2
+  0x080047FA:  2701         MOVS       R7, #1
+  0x080047FC:  03BA         LSLS       R2, R7, #14
+  0x080047FE:  03FE         LSLS       R6, R7, #15
+  0x08004800:  9604         STR        R6, [SP, #16]
+  0x08004802:  2800         CMP        R0, #0
+  0x08004804:  4E96         LDR        R6, =0x50000818          ; [PC, #0x0258] [0x08004A60] 
+  0x08004806:  D12F         BNE        .L8                      ; 0x08004868
+  0x08004808:  2008         MOVS       R0, #8
+  0x0800480A:  6128         STR        R0, [R5, #16]
+  0x0800480C:  2010         MOVS       R0, #16
+  0x0800480E:  6028         STR        R0, [R5]
+  0x08004810:  4991         LDR        R1, =relaisState         ; [PC, #0x0244] [0x08004A58] =0x20000730 
+  0x08004812:  2000         MOVS       R0, #0
+  0x08004814:  7008         STRB       R0, [R1]
+  0x08004816:  4991         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0244] [0x08004A5C] =0x200006A0 
+  0x08004818:  4614         MOV        R4, R2
+  0x0800481A:  2232         MOVS       R2, #50
+  0x0800481C:  600A         STR        R2, [R1]
+  0x0800481E:  2120         MOVS       R1, #32
+  0x08004820:  6029         STR        R1, [R5]
+  0x08004822:  4984         LDR        R1, =onTimeCounter       ; [PC, #0x0210] [0x08004A34] =0x200006A8 
+  0x08004824:  600B         STR        R3, [R1]
+  0x08004826:  6134         STR        R4, [R6, #16]
+  0x08004828:  4C96         LDR        R4, =smState.160         ; [PC, #0x0258] [0x08004A84] =0x20000732 
+  0x0800482A:  498E         LDR        R1, =offTimeCounterGN    ; [PC, #0x0238] [0x08004A64] =0x200006B4 
+  0x0800482C:  6008         STR        R0, [R1]
+  0x0800482E:  498E         LDR        R1, =blinkModeGN         ; [PC, #0x0238] [0x08004A68] =0x20000758 
+  0x08004830:  7008         STRB       R0, [R1]
+  0x08004832:  498E         LDR        R1, =onTimeCounterGN     ; [PC, #0x0238] [0x08004A6C] =0x200006A4 
+  0x08004834:  6008         STR        R0, [R1]
+  0x08004836:  4980         LDR        R1, =onTimeRT            ; [PC, #0x0200] [0x08004A38] =0x2000073C 
+  0x08004838:  700F         STRB       R7, [R1]
+  0x0800483A:  4980         LDR        R1, =offTimeRT           ; [PC, #0x0200] [0x08004A3C] =0x20000748 
+  0x0800483C:  700F         STRB       R7, [R1]
+  0x0800483E:  4980         LDR        R1, =blinkModeRT         ; [PC, #0x0200] [0x08004A40] =0x20000754 
+  0x08004840:  700F         STRB       R7, [R1]
+  0x08004842:  4980         LDR        R1, =numberOfBlinks      ; [PC, #0x0200] [0x08004A44] =0x200006BC 
+  0x08004844:  2203         MOVS       R2, #3
+  0x08004846:  600A         STR        R2, [R1]
+  0x08004848:  497F         LDR        R1, =blinkCounter        ; [PC, #0x01FC] [0x08004A48] =0x200006EC 
+  0x0800484A:  600A         STR        R2, [R1]
+  0x0800484C:  4981         LDR        R1, =pauseTime           ; [PC, #0x0204] [0x08004A54] =0x20000734 
+  0x0800484E:  700F         STRB       R7, [R1]
+  0x08004850:  9904         LDR        R1, [SP, #16]
+  0x08004852:  6031         STR        R1, [R6]
+  0x08004854:  4976         LDR        R1, =buttonState         ; [PC, #0x01D8] [0x08004A30] =0x2000073A 
+  0x08004856:  7008         STRB       R0, [R1]
+  0x08004858:  487D         LDR        R0, =onTimeCounterRT     ; [PC, #0x01F4] [0x08004A50] =0x2000069C 
+  0x0800485A:  21C8         MOVS       R1, #200
+  0x0800485C:  6001         STR        R1, [R0]
+  0x0800485E:  4884         LDR        R0, =0x08006990          ; [PC, #0x0210] [0x08004A70] 
+  0x08004860:  F000 FCC8    BL         puts                     ; 0x080051F4
+  0x08004864:  4879         LDR        R0, =0x080067AD          ; [PC, #0x01E4] [0x08004A4C] 
+  0x08004866:  E0DC         B          .L15                     ; 0x08004A22
+
.L8:
+  0x08004868:  9100         STR        R1, [SP, #0]
+  0x0800486A:  9302         STR        R3, [SP, #8]
+  0x0800486C:  486F         LDR        R0, =0x50000010          ; [PC, #0x01BC] [0x08004A2C] 
+  0x0800486E:  6801         LDR        R1, [R0]
+  0x08004870:  07C9         LSLS       R1, R1, #31
+  0x08004872:  9203         STR        R2, [SP, #12]
+  0x08004874:  9B04         LDR        R3, [SP, #16]
+  0x08004876:  D003         BEQ        .L9                      ; 0x08004880
+  0x08004878:  6800         LDR        R0, [R0]
+  0x0800487A:  0780         LSLS       R0, R0, #30
+  0x0800487C:  D500         BPL        .L9                      ; 0x08004880
+  0x0800487E:  E1DE         B          .L26                     ; 0x08004C3E
+
.L9:
+  0x08004880:  4881         LDR        R0, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter ; [PC, #0x0204] [0x08004A88] =0x20000704 
+  0x08004882:  2100         MOVS       R1, #0
+  0x08004884:  6001         STR        R1, [R0]
+
.L10:
+  0x08004886:  9101         STR        R1, [SP, #4]
+  0x08004888:  48FB         LDR        R0, =buttonState         ; [PC, #0x03EC] [0x08004C78] =0x2000073A 
+  0x0800488A:  7800         LDRB       R0, [R0]
+  0x0800488C:  2800         CMP        R0, #0
+  0x0800488E:  D125         BNE        .L11                     ; 0x080048DC
+  0x08004890:  2008         MOVS       R0, #8
+  0x08004892:  6128         STR        R0, [R5, #16]
+  0x08004894:  2010         MOVS       R0, #16
+  0x08004896:  6028         STR        R0, [R5]
+  0x08004898:  48F8         LDR        R0, =relaisState         ; [PC, #0x03E0] [0x08004C7C] =0x20000730 
+  0x0800489A:  2600         MOVS       R6, #0
+  0x0800489C:  7006         STRB       R6, [R0]
+  0x0800489E:  486F         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01BC] [0x08004A5C] =0x200006A0 
+  0x080048A0:  2132         MOVS       R1, #50
+  0x080048A2:  6001         STR        R1, [R0]
+  0x080048A4:  2020         MOVS       R0, #32
+  0x080048A6:  6028         STR        R0, [R5]
+  0x080048A8:  48F7         LDR        R0, =onTimeCounter       ; [PC, #0x03DC] [0x08004C88] =0x200006A8 
+  0x080048AA:  21C8         MOVS       R1, #200
+  0x080048AC:  6001         STR        R1, [R0]
+  0x080048AE:  48F9         LDR        R0, =0x50000818          ; [PC, #0x03E4] [0x08004C94] 
+  0x080048B0:  6102         STR        R2, [R0, #16]
+  0x080048B2:  486C         LDR        R0, =offTimeCounterGN    ; [PC, #0x01B0] [0x08004A64] =0x200006B4 
+  0x080048B4:  6006         STR        R6, [R0]
+  0x080048B6:  48F6         LDR        R0, =blinkModeGN         ; [PC, #0x03D8] [0x08004C90] =0x20000758 
+  0x080048B8:  7006         STRB       R6, [R0]
+  0x080048BA:  48F7         LDR        R0, =onTimeCounterGN     ; [PC, #0x03DC] [0x08004C98] =0x200006A4 
+  0x080048BC:  6006         STR        R6, [R0]
+  0x080048BE:  48F5         LDR        R0, =0x50000818          ; [PC, #0x03D4] [0x08004C94] 
+  0x080048C0:  6103         STR        R3, [R0, #16]
+  0x080048C2:  48F6         LDR        R0, =offTimeCounterRT    ; [PC, #0x03D8] [0x08004C9C] =0x200006B0 
+  0x080048C4:  6006         STR        R6, [R0]
+  0x080048C6:  48F6         LDR        R0, =blinkModeRT         ; [PC, #0x03D8] [0x08004CA0] =0x20000754 
+  0x080048C8:  7006         STRB       R6, [R0]
+  0x080048CA:  48F6         LDR        R0, =onTimeCounterRT     ; [PC, #0x03D8] [0x08004CA4] =0x2000069C 
+  0x080048CC:  6006         STR        R6, [R0]
+  0x080048CE:  486C         LDR        R0, =0x0800630D          ; [PC, #0x01B0] [0x08004A80] 
+  0x080048D0:  F000 FC90    BL         puts                     ; 0x080051F4
+  0x080048D4:  9A03         LDR        R2, [SP, #12]
+  0x080048D6:  9B04         LDR        R3, [SP, #16]
+  0x080048D8:  7026         STRB       R6, [R4]
+  0x080048DA:  4EEE         LDR        R6, =0x50000818          ; [PC, #0x03B8] [0x08004C94] 
+
.L11:
+  0x080048DC:  9800         LDR        R0, [SP, #0]
+  0x080048DE:  00C0         LSLS       R0, R0, #3
+  0x080048E0:  496A         LDR        R1, =dropLimitCounter    ; [PC, #0x01A8] [0x08004A8C] =0x200006E4 
+  0x080048E2:  6809         LDR        R1, [R1]
+  0x080048E4:  4281         CMP        R1, R0
+  0x080048E6:  D136         BNE        .L12                     ; 0x08004956
+  0x080048E8:  2008         MOVS       R0, #8
+  0x080048EA:  6128         STR        R0, [R5, #16]
+  0x080048EC:  2010         MOVS       R0, #16
+  0x080048EE:  6028         STR        R0, [R5]
+  0x080048F0:  48E2         LDR        R0, =relaisState         ; [PC, #0x0388] [0x08004C7C] =0x20000730 
+  0x080048F2:  2600         MOVS       R6, #0
+  0x080048F4:  7006         STRB       R6, [R0]
+  0x080048F6:  48FB         LDR        R0, =onTimeCounterRESET  ; [PC, #0x03EC] [0x08004CE4] =0x200006A0 
+  0x080048F8:  2132         MOVS       R1, #50
+  0x080048FA:  6001         STR        R1, [R0]
+  0x080048FC:  2020         MOVS       R0, #32
+  0x080048FE:  6028         STR        R0, [R5]
+  0x08004900:  48E1         LDR        R0, =onTimeCounter       ; [PC, #0x0384] [0x08004C88] =0x200006A8 
+  0x08004902:  9902         LDR        R1, [SP, #8]
+  0x08004904:  6001         STR        R1, [R0]
+  0x08004906:  48E3         LDR        R0, =0x50000818          ; [PC, #0x038C] [0x08004C94] 
+  0x08004908:  6102         STR        R2, [R0, #16]
+  0x0800490A:  48EB         LDR        R0, =offTimeCounterGN    ; [PC, #0x03AC] [0x08004CB8] =0x200006B4 
+  0x0800490C:  6006         STR        R6, [R0]
+  0x0800490E:  48E0         LDR        R0, =blinkModeGN         ; [PC, #0x0380] [0x08004C90] =0x20000758 
+  0x08004910:  7006         STRB       R6, [R0]
+  0x08004912:  48E1         LDR        R0, =onTimeCounterGN     ; [PC, #0x0384] [0x08004C98] =0x200006A4 
+  0x08004914:  6006         STR        R6, [R0]
+  0x08004916:  48E9         LDR        R0, =onTimeRT            ; [PC, #0x03A4] [0x08004CBC] =0x2000073C 
+  0x08004918:  7007         STRB       R7, [R0]
+  0x0800491A:  48E9         LDR        R0, =offTimeRT           ; [PC, #0x03A4] [0x08004CC0] =0x20000748 
+  0x0800491C:  7007         STRB       R7, [R0]
+  0x0800491E:  48E0         LDR        R0, =blinkModeRT         ; [PC, #0x0380] [0x08004CA0] =0x20000754 
+  0x08004920:  7007         STRB       R7, [R0]
+  0x08004922:  48E8         LDR        R0, =numberOfBlinks      ; [PC, #0x03A0] [0x08004CC4] =0x200006BC 
+  0x08004924:  2104         MOVS       R1, #4
+  0x08004926:  6001         STR        R1, [R0]
+  0x08004928:  48E7         LDR        R0, =blinkCounter        ; [PC, #0x039C] [0x08004CC8] =0x200006EC 
+  0x0800492A:  6001         STR        R1, [R0]
+  0x0800492C:  48E7         LDR        R0, =pauseTime           ; [PC, #0x039C] [0x08004CCC] =0x20000734 
+  0x0800492E:  7007         STRB       R7, [R0]
+  0x08004930:  48D8         LDR        R0, =0x50000818          ; [PC, #0x0360] [0x08004C94] 
+  0x08004932:  6003         STR        R3, [R0]
+  0x08004934:  48D0         LDR        R0, =buttonState         ; [PC, #0x0340] [0x08004C78] =0x2000073A 
+  0x08004936:  7006         STRB       R6, [R0]
+  0x08004938:  48DA         LDR        R0, =onTimeCounterRT     ; [PC, #0x0368] [0x08004CA4] =0x2000069C 
+  0x0800493A:  21C8         MOVS       R1, #200
+  0x0800493C:  6001         STR        R1, [R0]
+  0x0800493E:  48EF         LDR        R0, =0x08006790          ; [PC, #0x03BC] [0x08004CFC] 
+  0x08004940:  F000 FC58    BL         puts                     ; 0x080051F4
+  0x08004944:  48E8         LDR        R0, =0x080067AD          ; [PC, #0x03A0] [0x08004CE8] 
+  0x08004946:  F000 FC55    BL         puts                     ; 0x080051F4
+  0x0800494A:  9B04         LDR        R3, [SP, #16]
+  0x0800494C:  2003         MOVS       R0, #3
+  0x0800494E:  7020         STRB       R0, [R4]
+  0x08004950:  48E9         LDR        R0, =dropLimitCounter    ; [PC, #0x03A4] [0x08004CF8] =0x200006E4 
+  0x08004952:  6006         STR        R6, [R0]
+  0x08004954:  4ECF         LDR        R6, =0x50000818          ; [PC, #0x033C] [0x08004C94] 
+
.L12:
+  0x08004956:  9801         LDR        R0, [SP, #4]
+  0x08004958:  2800         CMP        R0, #0
+  0x0800495A:  D032         BEQ        .L13                     ; 0x080049C2
+  0x0800495C:  2008         MOVS       R0, #8
+  0x0800495E:  6128         STR        R0, [R5, #16]
+  0x08004960:  2010         MOVS       R0, #16
+  0x08004962:  6028         STR        R0, [R5]
+  0x08004964:  49C5         LDR        R1, =relaisState         ; [PC, #0x0314] [0x08004C7C] =0x20000730 
+  0x08004966:  2000         MOVS       R0, #0
+  0x08004968:  7008         STRB       R0, [R1]
+  0x0800496A:  49DE         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0378] [0x08004CE4] =0x200006A0 
+  0x0800496C:  2232         MOVS       R2, #50
+  0x0800496E:  600A         STR        R2, [R1]
+  0x08004970:  2120         MOVS       R1, #32
+  0x08004972:  6029         STR        R1, [R5]
+  0x08004974:  49C4         LDR        R1, =onTimeCounter       ; [PC, #0x0310] [0x08004C88] =0x200006A8 
+  0x08004976:  9A02         LDR        R2, [SP, #8]
+  0x08004978:  600A         STR        R2, [R1]
+  0x0800497A:  9903         LDR        R1, [SP, #12]
+  0x0800497C:  6131         STR        R1, [R6, #16]
+  0x0800497E:  49CE         LDR        R1, =offTimeCounterGN    ; [PC, #0x0338] [0x08004CB8] =0x200006B4 
+  0x08004980:  6008         STR        R0, [R1]
+  0x08004982:  49C3         LDR        R1, =blinkModeGN         ; [PC, #0x030C] [0x08004C90] =0x20000758 
+  0x08004984:  7008         STRB       R0, [R1]
+  0x08004986:  49C4         LDR        R1, =onTimeCounterGN     ; [PC, #0x0310] [0x08004C98] =0x200006A4 
+  0x08004988:  6008         STR        R0, [R1]
+  0x0800498A:  49CC         LDR        R1, =onTimeRT            ; [PC, #0x0330] [0x08004CBC] =0x2000073C 
+  0x0800498C:  700F         STRB       R7, [R1]
+  0x0800498E:  49CC         LDR        R1, =offTimeRT           ; [PC, #0x0330] [0x08004CC0] =0x20000748 
+  0x08004990:  700F         STRB       R7, [R1]
+  0x08004992:  49C3         LDR        R1, =blinkModeRT         ; [PC, #0x030C] [0x08004CA0] =0x20000754 
+  0x08004994:  700F         STRB       R7, [R1]
+  0x08004996:  49CB         LDR        R1, =numberOfBlinks      ; [PC, #0x032C] [0x08004CC4] =0x200006BC 
+  0x08004998:  2202         MOVS       R2, #2
+  0x0800499A:  600A         STR        R2, [R1]
+  0x0800499C:  49CA         LDR        R1, =blinkCounter        ; [PC, #0x0328] [0x08004CC8] =0x200006EC 
+  0x0800499E:  600A         STR        R2, [R1]
+  0x080049A0:  49CA         LDR        R1, =pauseTime           ; [PC, #0x0328] [0x08004CCC] =0x20000734 
+  0x080049A2:  700F         STRB       R7, [R1]
+  0x080049A4:  6033         STR        R3, [R6]
+  0x080049A6:  49B4         LDR        R1, =buttonState         ; [PC, #0x02D0] [0x08004C78] =0x2000073A 
+  0x080049A8:  7008         STRB       R0, [R1]
+  0x080049AA:  48BE         LDR        R0, =onTimeCounterRT     ; [PC, #0x02F8] [0x08004CA4] =0x2000069C 
+  0x080049AC:  21C8         MOVS       R1, #200
+  0x080049AE:  6001         STR        R1, [R0]
+  0x080049B0:  48D3         LDR        R0, =0x08006954          ; [PC, #0x034C] [0x08004D00] 
+  0x080049B2:  F000 FC1F    BL         puts                     ; 0x080051F4
+  0x080049B6:  48CC         LDR        R0, =0x080067AD          ; [PC, #0x0330] [0x08004CE8] 
+  0x080049B8:  F000 FC1C    BL         puts                     ; 0x080051F4
+  0x080049BC:  9B04         LDR        R3, [SP, #16]
+  0x080049BE:  2003         MOVS       R0, #3
+  0x080049C0:  7020         STRB       R0, [R4]
+
.L13:
+  0x080049C2:  48D0         LDR        R0, =temp                ; [PC, #0x0340] [0x08004D04] =0x20000690 
+  0x080049C4:  6800         LDR        R0, [R0]
+  0x080049C6:  2851         CMP        R0, #81
+  0x080049C8:  DA00         BGE        .L14                     ; 0x080049CC
+  0x080049CA:  E136         B          .L25                     ; 0x08004C3A
+
.L14:
+  0x080049CC:  2008         MOVS       R0, #8
+  0x080049CE:  6128         STR        R0, [R5, #16]
+  0x080049D0:  2010         MOVS       R0, #16
+  0x080049D2:  6028         STR        R0, [R5]
+  0x080049D4:  49A9         LDR        R1, =relaisState         ; [PC, #0x02A4] [0x08004C7C] =0x20000730 
+  0x080049D6:  2000         MOVS       R0, #0
+  0x080049D8:  7008         STRB       R0, [R1]
+  0x080049DA:  49C2         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0308] [0x08004CE4] =0x200006A0 
+  0x080049DC:  2232         MOVS       R2, #50
+  0x080049DE:  600A         STR        R2, [R1]
+  0x080049E0:  2120         MOVS       R1, #32
+  0x080049E2:  6029         STR        R1, [R5]
+  0x080049E4:  49A8         LDR        R1, =onTimeCounter       ; [PC, #0x02A0] [0x08004C88] =0x200006A8 
+  0x080049E6:  9A02         LDR        R2, [SP, #8]
+  0x080049E8:  600A         STR        R2, [R1]
+  0x080049EA:  9903         LDR        R1, [SP, #12]
+  0x080049EC:  6131         STR        R1, [R6, #16]
+  0x080049EE:  49B2         LDR        R1, =offTimeCounterGN    ; [PC, #0x02C8] [0x08004CB8] =0x200006B4 
+  0x080049F0:  6008         STR        R0, [R1]
+  0x080049F2:  49A7         LDR        R1, =blinkModeGN         ; [PC, #0x029C] [0x08004C90] =0x20000758 
+  0x080049F4:  7008         STRB       R0, [R1]
+  0x080049F6:  49A8         LDR        R1, =onTimeCounterGN     ; [PC, #0x02A0] [0x08004C98] =0x200006A4 
+  0x080049F8:  6008         STR        R0, [R1]
+  0x080049FA:  49B0         LDR        R1, =onTimeRT            ; [PC, #0x02C0] [0x08004CBC] =0x2000073C 
+  0x080049FC:  700F         STRB       R7, [R1]
+  0x080049FE:  49B0         LDR        R1, =offTimeRT           ; [PC, #0x02C0] [0x08004CC0] =0x20000748 
+  0x08004A00:  700F         STRB       R7, [R1]
+  0x08004A02:  49A7         LDR        R1, =blinkModeRT         ; [PC, #0x029C] [0x08004CA0] =0x20000754 
+  0x08004A04:  700F         STRB       R7, [R1]
+  0x08004A06:  49AF         LDR        R1, =numberOfBlinks      ; [PC, #0x02BC] [0x08004CC4] =0x200006BC 
+  0x08004A08:  2205         MOVS       R2, #5
+  0x08004A0A:  600A         STR        R2, [R1]
+  0x08004A0C:  49AE         LDR        R1, =blinkCounter        ; [PC, #0x02B8] [0x08004CC8] =0x200006EC 
+  0x08004A0E:  600A         STR        R2, [R1]
+  0x08004A10:  49AE         LDR        R1, =pauseTime           ; [PC, #0x02B8] [0x08004CCC] =0x20000734 
+  0x08004A12:  700F         STRB       R7, [R1]
+  0x08004A14:  6033         STR        R3, [R6]
+  0x08004A16:  4998         LDR        R1, =buttonState         ; [PC, #0x0260] [0x08004C78] =0x2000073A 
+  0x08004A18:  7008         STRB       R0, [R1]
+  0x08004A1A:  48A2         LDR        R0, =onTimeCounterRT     ; [PC, #0x0288] [0x08004CA4] =0x2000069C 
+  0x08004A1C:  21C8         MOVS       R1, #200
+  0x08004A1E:  6001         STR        R1, [R0]
+  0x08004A20:  48B9         LDR        R0, =0x08006330          ; [PC, #0x02E4] [0x08004D08] 
+
.L15:
+  0x08004A22:  F000 FBE7    BL         puts                     ; 0x080051F4
+  0x08004A26:  2003         MOVS       R0, #3
+  0x08004A28:  E106         B          .L24                     ; 0x08004C38
+  0x08004A2A:  46C0         NOP
+  0x08004A2C:  50000010     DC.W       0x50000010
+  0x08004A30:  2000073A     DC.W       buttonState
+  0x08004A34:  200006A8     DC.W       onTimeCounter
+  0x08004A38:  2000073C     DC.W       onTimeRT
+  0x08004A3C:  20000748     DC.W       offTimeRT
+  0x08004A40:  20000754     DC.W       blinkModeRT
+  0x08004A44:  200006BC     DC.W       numberOfBlinks
+  0x08004A48:  200006EC     DC.W       blinkCounter
+  0x08004A4C:  080067AD     DC.W       080067AD               ; R_ARM_ABS32
+  0x08004A50:  2000069C     DC.W       onTimeCounterRT
+  0x08004A54:  20000734     DC.W       pauseTime
+  0x08004A58:  20000730     DC.W       relaisState
+  0x08004A5C:  200006A0     DC.W       onTimeCounterRESET
+  0x08004A60:  50000818     DC.W       0x50000818
+  0x08004A64:  200006B4     DC.W       offTimeCounterGN
+  0x08004A68:  20000758     DC.W       blinkModeGN
+  0x08004A6C:  200006A4     DC.W       onTimeCounterGN
+  0x08004A70:  08006990     DC.W       08006990               ; R_ARM_ABS32
+  0x08004A74:  200006B8     DC.W       offTimeCounter
+  0x08004A78:  2000075C     DC.W       alarmMode
+  0x08004A7C:  200006B0     DC.W       offTimeCounterRT
+  0x08004A80:  0800630D     DC.W       0800630D               ; R_ARM_ABS32
+  0x08004A84:  20000732     DC.W       smState.160
+  0x08004A88:  20000704     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
+  0x08004A8C:  200006E4     DC.W       dropLimitCounter
+
.L16:
+  0x08004A90:  2010         MOVS       R0, #16
+  0x08004A92:  6128         STR        R0, [R5, #16]
+  0x08004A94:  2008         MOVS       R0, #8
+  0x08004A96:  6028         STR        R0, [R5]
+  0x08004A98:  4878         LDR        R0, =relaisState         ; [PC, #0x01E0] [0x08004C7C] =0x20000730 
+  0x08004A9A:  2601         MOVS       R6, #1
+  0x08004A9C:  7006         STRB       R6, [R0]
+  0x08004A9E:  4878         LDR        R0, =onTimeCounterSET    ; [PC, #0x01E0] [0x08004C80] =0x20000698 
+  0x08004AA0:  2132         MOVS       R1, #50
+  0x08004AA2:  6001         STR        R1, [R0]
+  0x08004AA4:  2020         MOVS       R0, #32
+  0x08004AA6:  6028         STR        R0, [R5]
+  0x08004AA8:  4876         LDR        R0, =onTimeGN            ; [PC, #0x01D8] [0x08004C84] =0x20000740 
+  0x08004AAA:  7006         STRB       R6, [R0]
+  0x08004AAC:  4876         LDR        R0, =onTimeCounter       ; [PC, #0x01D8] [0x08004C88] =0x200006A8 
+  0x08004AAE:  21C8         MOVS       R1, #200
+  0x08004AB0:  6001         STR        R1, [R0]
+  0x08004AB2:  4876         LDR        R0, =offTimeGN           ; [PC, #0x01D8] [0x08004C8C] =0x2000074C 
+  0x08004AB4:  7006         STRB       R6, [R0]
+  0x08004AB6:  4876         LDR        R0, =blinkModeGN         ; [PC, #0x01D8] [0x08004C90] =0x20000758 
+  0x08004AB8:  7006         STRB       R6, [R0]
+  0x08004ABA:  03B0         LSLS       R0, R6, #14
+  0x08004ABC:  4A75         LDR        R2, =0x50000818          ; [PC, #0x01D4] [0x08004C94] 
+  0x08004ABE:  6010         STR        R0, [R2]
+  0x08004AC0:  4875         LDR        R0, =onTimeCounterGN     ; [PC, #0x01D4] [0x08004C98] =0x200006A4 
+  0x08004AC2:  6001         STR        R1, [R0]
+  0x08004AC4:  03F0         LSLS       R0, R6, #15
+  0x08004AC6:  6110         STR        R0, [R2, #16]
+  0x08004AC8:  4874         LDR        R0, =offTimeCounterRT    ; [PC, #0x01D0] [0x08004C9C] =0x200006B0 
+  0x08004ACA:  2100         MOVS       R1, #0
+  0x08004ACC:  6001         STR        R1, [R0]
+  0x08004ACE:  4874         LDR        R0, =blinkModeRT         ; [PC, #0x01D0] [0x08004CA0] =0x20000754 
+  0x08004AD0:  7001         STRB       R1, [R0]
+  0x08004AD2:  4874         LDR        R0, =onTimeCounterRT     ; [PC, #0x01D0] [0x08004CA4] =0x2000069C 
+  0x08004AD4:  6001         STR        R1, [R0]
+  0x08004AD6:  4874         LDR        R0, =0x0800654D          ; [PC, #0x01D0] [0x08004CA8] 
+  0x08004AD8:  F000 FB8C    BL         puts                     ; 0x080051F4
+  0x08004ADC:  7026         STRB       R6, [R4]
+  0x08004ADE:  4E66         LDR        R6, =buttonState         ; [PC, #0x0198] [0x08004C78] =0x2000073A 
+  0x08004AE0:  7831         LDRB       R1, [R6]
+
.L17:
+  0x08004AE2:  2902         CMP        R1, #2
+  0x08004AE4:  D137         BNE        .L18                     ; 0x08004B56
+  0x08004AE6:  2010         MOVS       R0, #16
+  0x08004AE8:  6128         STR        R0, [R5, #16]
+  0x08004AEA:  2008         MOVS       R0, #8
+  0x08004AEC:  6028         STR        R0, [R5]
+  0x08004AEE:  4963         LDR        R1, =relaisState         ; [PC, #0x018C] [0x08004C7C] =0x20000730 
+  0x08004AF0:  2001         MOVS       R0, #1
+  0x08004AF2:  7008         STRB       R0, [R1]
+  0x08004AF4:  4962         LDR        R1, =onTimeCounterSET    ; [PC, #0x0188] [0x08004C80] =0x20000698 
+  0x08004AF6:  2232         MOVS       R2, #50
+  0x08004AF8:  600A         STR        R2, [R1]
+  0x08004AFA:  496C         LDR        R1, =onTime              ; [PC, #0x01B0] [0x08004CAC] =0x20000744 
+  0x08004AFC:  7008         STRB       R0, [R1]
+  0x08004AFE:  496C         LDR        R1, =offTime             ; [PC, #0x01B0] [0x08004CB0] =0x20000750 
+  0x08004B00:  7008         STRB       R0, [R1]
+  0x08004B02:  496C         LDR        R1, =alarmMode           ; [PC, #0x01B0] [0x08004CB4] =0x2000075C 
+  0x08004B04:  7008         STRB       R0, [R1]
+  0x08004B06:  2120         MOVS       R1, #32
+  0x08004B08:  6029         STR        R1, [R5]
+  0x08004B0A:  4A5F         LDR        R2, =onTimeCounter       ; [PC, #0x017C] [0x08004C88] =0x200006A8 
+  0x08004B0C:  21C8         MOVS       R1, #200
+  0x08004B0E:  6011         STR        R1, [R2]
+  0x08004B10:  0383         LSLS       R3, R0, #14
+  0x08004B12:  4A60         LDR        R2, =0x50000818          ; [PC, #0x0180] [0x08004C94] 
+  0x08004B14:  6013         STR        R3, [R2]
+  0x08004B16:  4B60         LDR        R3, =onTimeCounterGN     ; [PC, #0x0180] [0x08004C98] =0x200006A4 
+  0x08004B18:  2500         MOVS       R5, #0
+  0x08004B1A:  601D         STR        R5, [R3]
+  0x08004B1C:  4B5C         LDR        R3, =blinkModeGN         ; [PC, #0x0170] [0x08004C90] =0x20000758 
+  0x08004B1E:  701D         STRB       R5, [R3]
+  0x08004B20:  4B65         LDR        R3, =offTimeCounterGN    ; [PC, #0x0194] [0x08004CB8] =0x200006B4 
+  0x08004B22:  601D         STR        R5, [R3]
+  0x08004B24:  03C3         LSLS       R3, R0, #15
+  0x08004B26:  6113         STR        R3, [R2, #16]
+  0x08004B28:  4E64         LDR        R6, =onTimeRT            ; [PC, #0x0190] [0x08004CBC] =0x2000073C 
+  0x08004B2A:  7030         STRB       R0, [R6]
+  0x08004B2C:  4E5B         LDR        R6, =offTimeCounterRT    ; [PC, #0x016C] [0x08004C9C] =0x200006B0 
+  0x08004B2E:  6035         STR        R5, [R6]
+  0x08004B30:  4E51         LDR        R6, =buttonState         ; [PC, #0x0144] [0x08004C78] =0x2000073A 
+  0x08004B32:  4D63         LDR        R5, =offTimeRT           ; [PC, #0x018C] [0x08004CC0] =0x20000748 
+  0x08004B34:  7028         STRB       R0, [R5]
+  0x08004B36:  4D5A         LDR        R5, =blinkModeRT         ; [PC, #0x0168] [0x08004CA0] =0x20000754 
+  0x08004B38:  7028         STRB       R0, [R5]
+  0x08004B3A:  4D62         LDR        R5, =numberOfBlinks      ; [PC, #0x0188] [0x08004CC4] =0x200006BC 
+  0x08004B3C:  6028         STR        R0, [R5]
+  0x08004B3E:  4D62         LDR        R5, =blinkCounter        ; [PC, #0x0188] [0x08004CC8] =0x200006EC 
+  0x08004B40:  6028         STR        R0, [R5]
+  0x08004B42:  4D62         LDR        R5, =pauseTime           ; [PC, #0x0188] [0x08004CCC] =0x20000734 
+  0x08004B44:  7028         STRB       R0, [R5]
+  0x08004B46:  6013         STR        R3, [R2]
+  0x08004B48:  4856         LDR        R0, =onTimeCounterRT     ; [PC, #0x0158] [0x08004CA4] =0x2000069C 
+  0x08004B4A:  6001         STR        R1, [R0]
+  0x08004B4C:  4860         LDR        R0, =0x08006767          ; [PC, #0x0180] [0x08004CD0] 
+  0x08004B4E:  F000 FB51    BL         puts                     ; 0x080051F4
+  0x08004B52:  2002         MOVS       R0, #2
+  0x08004B54:  7020         STRB       R0, [R4]
+
.L18:
+  0x08004B56:  6838         LDR        R0, [R7]
+  0x08004B58:  2801         CMP        R0, #1
+  0x08004B5A:  D16E         BNE        .L25                     ; 0x08004C3A
+  0x08004B5C:  485D         LDR        R0, =uwTick              ; [PC, #0x0174] [0x08004CD4] =0x2000068C 
+  0x08004B5E:  6802         LDR        R2, [R0]
+  0x08004B60:  495D         LDR        R1, =SECONDARYPROTECTION_SM_Error.oldTimeMSTick ; [PC, #0x0174] [0x08004CD8] =0x20000714 
+  0x08004B62:  680B         LDR        R3, [R1]
+  0x08004B64:  4293         CMP        R3, R2
+  0x08004B66:  D102         BNE        .L19                     ; 0x08004B6E
+  0x08004B68:  485C         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0170] [0x08004CDC] =0x2000070C 
+  0x08004B6A:  6800         LDR        R0, [R0]
+  0x08004B6C:  E005         B          .L20                     ; 0x08004B7A
+
.L19:
+  0x08004B6E:  6800         LDR        R0, [R0]
+  0x08004B70:  6008         STR        R0, [R1]
+  0x08004B72:  495A         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0168] [0x08004CDC] =0x2000070C 
+  0x08004B74:  6808         LDR        R0, [R1]
+  0x08004B76:  1C40         ADDS       R0, R0, #1
+  0x08004B78:  6008         STR        R0, [R1]
+
.L20:
+  0x08004B7A:  4959         LDR        R1, =0x0036EE81          ; [PC, #0x0164] [0x08004CE0] 
+  0x08004B7C:  4288         CMP        R0, R1
+  0x08004B7E:  D35C         BCC        .L25                     ; 0x08004C3A
+  0x08004B80:  4856         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter ; [PC, #0x0158] [0x08004CDC] =0x2000070C 
+  0x08004B82:  2100         MOVS       R1, #0
+  0x08004B84:  6001         STR        R1, [R0]
+  0x08004B86:  2001         MOVS       R0, #1
+  0x08004B88:  7030         STRB       R0, [R6]
+  0x08004B8A:  E056         B          .L25                     ; 0x08004C3A
+
.L21:
+  0x08004B8C:  2010         MOVS       R0, #16
+  0x08004B8E:  6128         STR        R0, [R5, #16]
+  0x08004B90:  2008         MOVS       R0, #8
+  0x08004B92:  6028         STR        R0, [R5]
+  0x08004B94:  4839         LDR        R0, =relaisState         ; [PC, #228] [0x08004C7C] =0x20000730 
+  0x08004B96:  7001         STRB       R1, [R0]
+  0x08004B98:  4839         LDR        R0, =onTimeCounterSET    ; [PC, #228] [0x08004C80] =0x20000698 
+  0x08004B9A:  2232         MOVS       R2, #50
+  0x08004B9C:  6002         STR        R2, [R0]
+  0x08004B9E:  2020         MOVS       R0, #32
+  0x08004BA0:  6028         STR        R0, [R5]
+  0x08004BA2:  4838         LDR        R0, =onTimeGN            ; [PC, #224] [0x08004C84] =0x20000740 
+  0x08004BA4:  7001         STRB       R1, [R0]
+  0x08004BA6:  4838         LDR        R0, =onTimeCounter       ; [PC, #224] [0x08004C88] =0x200006A8 
+  0x08004BA8:  22C8         MOVS       R2, #200
+  0x08004BAA:  6002         STR        R2, [R0]
+  0x08004BAC:  4837         LDR        R0, =offTimeGN           ; [PC, #220] [0x08004C8C] =0x2000074C 
+  0x08004BAE:  7001         STRB       R1, [R0]
+  0x08004BB0:  038A         LSLS       R2, R1, #14
+  0x08004BB2:  483D         LDR        R0, =0x0800654D          ; [PC, #244] [0x08004CA8] 
+  0x08004BB4:  4B38         LDR        R3, =onTimeCounterGN     ; [PC, #224] [0x08004C98] =0x200006A4 
+  0x08004BB6:  4E36         LDR        R6, =blinkModeGN         ; [PC, #216] [0x08004C90] =0x20000758 
+  0x08004BB8:  460F         MOV        R7, R1
+
.L22:
+  0x08004BBA:  7031         STRB       R1, [R6]
+  0x08004BBC:  4935         LDR        R1, =0x50000818          ; [PC, #212] [0x08004C94] 
+  0x08004BBE:  600A         STR        R2, [R1]
+  0x08004BC0:  21C8         MOVS       R1, #200
+  0x08004BC2:  6019         STR        R1, [R3]
+  0x08004BC4:  F000 FB16    BL         puts                     ; 0x080051F4
+  0x08004BC8:  7027         STRB       R7, [R4]
+  0x08004BCA:  482B         LDR        R0, =buttonState         ; [PC, #172] [0x08004C78] =0x2000073A 
+  0x08004BCC:  7801         LDRB       R1, [R0]
+
.L23:
+  0x08004BCE:  2902         CMP        R1, #2
+  0x08004BD0:  D133         BNE        .L25                     ; 0x08004C3A
+  0x08004BD2:  2010         MOVS       R0, #16
+  0x08004BD4:  6128         STR        R0, [R5, #16]
+  0x08004BD6:  2008         MOVS       R0, #8
+  0x08004BD8:  6028         STR        R0, [R5]
+  0x08004BDA:  4928         LDR        R1, =relaisState         ; [PC, #160] [0x08004C7C] =0x20000730 
+  0x08004BDC:  2001         MOVS       R0, #1
+  0x08004BDE:  7008         STRB       R0, [R1]
+  0x08004BE0:  4927         LDR        R1, =onTimeCounterSET    ; [PC, #156] [0x08004C80] =0x20000698 
+  0x08004BE2:  2232         MOVS       R2, #50
+  0x08004BE4:  600A         STR        R2, [R1]
+  0x08004BE6:  4931         LDR        R1, =onTime              ; [PC, #196] [0x08004CAC] =0x20000744 
+  0x08004BE8:  7008         STRB       R0, [R1]
+  0x08004BEA:  4931         LDR        R1, =offTime             ; [PC, #196] [0x08004CB0] =0x20000750 
+  0x08004BEC:  7008         STRB       R0, [R1]
+  0x08004BEE:  4931         LDR        R1, =alarmMode           ; [PC, #196] [0x08004CB4] =0x2000075C 
+  0x08004BF0:  7008         STRB       R0, [R1]
+  0x08004BF2:  2120         MOVS       R1, #32
+  0x08004BF4:  6029         STR        R1, [R5]
+  0x08004BF6:  4A24         LDR        R2, =onTimeCounter       ; [PC, #144] [0x08004C88] =0x200006A8 
+  0x08004BF8:  21C8         MOVS       R1, #200
+  0x08004BFA:  6011         STR        R1, [R2]
+  0x08004BFC:  0383         LSLS       R3, R0, #14
+  0x08004BFE:  4A25         LDR        R2, =0x50000818          ; [PC, #148] [0x08004C94] 
+  0x08004C00:  6013         STR        R3, [R2]
+  0x08004C02:  4B25         LDR        R3, =onTimeCounterGN     ; [PC, #148] [0x08004C98] =0x200006A4 
+  0x08004C04:  2500         MOVS       R5, #0
+  0x08004C06:  601D         STR        R5, [R3]
+  0x08004C08:  4B21         LDR        R3, =blinkModeGN         ; [PC, #132] [0x08004C90] =0x20000758 
+  0x08004C0A:  701D         STRB       R5, [R3]
+  0x08004C0C:  4B2A         LDR        R3, =offTimeCounterGN    ; [PC, #168] [0x08004CB8] =0x200006B4 
+  0x08004C0E:  601D         STR        R5, [R3]
+  0x08004C10:  4B2A         LDR        R3, =onTimeRT            ; [PC, #168] [0x08004CBC] =0x2000073C 
+  0x08004C12:  7018         STRB       R0, [R3]
+  0x08004C14:  4B2A         LDR        R3, =offTimeRT           ; [PC, #168] [0x08004CC0] =0x20000748 
+  0x08004C16:  7018         STRB       R0, [R3]
+  0x08004C18:  4B21         LDR        R3, =blinkModeRT         ; [PC, #132] [0x08004CA0] =0x20000754 
+  0x08004C1A:  7018         STRB       R0, [R3]
+  0x08004C1C:  4B29         LDR        R3, =numberOfBlinks      ; [PC, #164] [0x08004CC4] =0x200006BC 
+  0x08004C1E:  6018         STR        R0, [R3]
+  0x08004C20:  4B29         LDR        R3, =blinkCounter        ; [PC, #164] [0x08004CC8] =0x200006EC 
+  0x08004C22:  6018         STR        R0, [R3]
+  0x08004C24:  4B29         LDR        R3, =pauseTime           ; [PC, #164] [0x08004CCC] =0x20000734 
+  0x08004C26:  7018         STRB       R0, [R3]
+  0x08004C28:  03C0         LSLS       R0, R0, #15
+  0x08004C2A:  6010         STR        R0, [R2]
+  0x08004C2C:  481D         LDR        R0, =onTimeCounterRT     ; [PC, #116] [0x08004CA4] =0x2000069C 
+  0x08004C2E:  6001         STR        R1, [R0]
+  0x08004C30:  4827         LDR        R0, =0x08006767          ; [PC, #156] [0x08004CD0] 
+  0x08004C32:  F000 FADF    BL         puts                     ; 0x080051F4
+  0x08004C36:  2002         MOVS       R0, #2
+
.L24:
+  0x08004C38:  7020         STRB       R0, [R4]
+
.L25:
+  0x08004C3A:  B005         ADD        SP, SP, #20
+  0x08004C3C:  BDF0         POP        {R4-R7, PC}
+
.L26:
+  0x08004C3E:  482B         LDR        R0, =SECONDARYPROTECTION_SM_On.oldtime ; [PC, #172] [0x08004CEC] =0x200006FC 
+  0x08004C40:  6802         LDR        R2, [R0]
+  0x08004C42:  4924         LDR        R1, =uwTick              ; [PC, #144] [0x08004CD4] =0x2000068C 
+  0x08004C44:  680B         LDR        R3, [R1]
+  0x08004C46:  4293         CMP        R3, R2
+  0x08004C48:  D103         BNE        .L27                     ; 0x08004C52
+  0x08004C4A:  2100         MOVS       R1, #0
+  0x08004C4C:  9B04         LDR        R3, [SP, #16]
+  0x08004C4E:  9A03         LDR        R2, [SP, #12]
+  0x08004C50:  E619         B          .L10                     ; 0x08004886
+
.L27:
+  0x08004C52:  6809         LDR        R1, [R1]
+  0x08004C54:  6001         STR        R1, [R0]
+  0x08004C56:  4926         LDR        R1, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter ; [PC, #152] [0x08004CF0] =0x20000704 
+  0x08004C58:  680B         LDR        R3, [R1]
+  0x08004C5A:  1C5A         ADDS       R2, R3, #1
+  0x08004C5C:  2000         MOVS       R0, #0
+  0x08004C5E:  4E25         LDR        R6, =0x0000752F          ; [PC, #148] [0x08004CF4] 
+  0x08004C60:  42B3         CMP        R3, R6
+  0x08004C62:  4603         MOV        R3, R0
+  0x08004C64:  DC00         BGT        .L28                     ; 0x08004C68
+  0x08004C66:  4613         MOV        R3, R2
+
.L28:
+  0x08004C68:  600B         STR        R3, [R1]
+  0x08004C6A:  4639         MOV        R1, R7
+  0x08004C6C:  DC00         BGT        .L29                     ; 0x08004C70
+  0x08004C6E:  2100         MOVS       R1, #0
+
.L29:
+  0x08004C70:  9B04         LDR        R3, [SP, #16]
+  0x08004C72:  4E08         LDR        R6, =0x50000818          ; [PC, #32] [0x08004C94] 
+  0x08004C74:  9A03         LDR        R2, [SP, #12]
+  0x08004C76:  E606         B          .L10                     ; 0x08004886
+  0x08004C78:  2000073A     DC.W       buttonState
+  0x08004C7C:  20000730     DC.W       relaisState
+  0x08004C80:  20000698     DC.W       onTimeCounterSET
+  0x08004C84:  20000740     DC.W       onTimeGN
+  0x08004C88:  200006A8     DC.W       onTimeCounter
+  0x08004C8C:  2000074C     DC.W       offTimeGN
+  0x08004C90:  20000758     DC.W       blinkModeGN
+  0x08004C94:  50000818     DC.W       0x50000818
+  0x08004C98:  200006A4     DC.W       onTimeCounterGN
+  0x08004C9C:  200006B0     DC.W       offTimeCounterRT
+  0x08004CA0:  20000754     DC.W       blinkModeRT
+  0x08004CA4:  2000069C     DC.W       onTimeCounterRT
+  0x08004CA8:  0800654D     DC.W       0800654D               ; R_ARM_ABS32
+  0x08004CAC:  20000744     DC.W       onTime
+  0x08004CB0:  20000750     DC.W       offTime
+  0x08004CB4:  2000075C     DC.W       alarmMode
+  0x08004CB8:  200006B4     DC.W       offTimeCounterGN
+  0x08004CBC:  2000073C     DC.W       onTimeRT
+  0x08004CC0:  20000748     DC.W       offTimeRT
+  0x08004CC4:  200006BC     DC.W       numberOfBlinks
+  0x08004CC8:  200006EC     DC.W       blinkCounter
+  0x08004CCC:  20000734     DC.W       pauseTime
+  0x08004CD0:  08006767     DC.W       08006767               ; R_ARM_ABS32
+  0x08004CD4:  2000068C     DC.W       uwTick
+  0x08004CD8:  20000714     DC.W       SECONDARYPROTECTION_SM_Error.oldTimeMSTick
+  0x08004CDC:  2000070C     DC.W       SECONDARYPROTECTION_SM_Error.retry_counter
+  0x08004CE0:  0036EE81     DC.W       0x0036EE81
+  0x08004CE4:  200006A0     DC.W       onTimeCounterRESET
+  0x08004CE8:  080067AD     DC.W       080067AD               ; R_ARM_ABS32
+  0x08004CEC:  200006FC     DC.W       SECONDARYPROTECTION_SM_On.oldtime
+  0x08004CF0:  20000704     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter
+  0x08004CF4:  0000752F     DC.W       0x0000752F
+  0x08004CF8:  200006E4     DC.W       dropLimitCounter
+  0x08004CFC:  08006790     DC.W       08006790               ; R_ARM_ABS32
+  0x08004D00:  08006954     DC.W       08006954               ; R_ARM_ABS32
+  0x08004D04:  20000690     DC.W       temp
+  0x08004D08:  08006330     DC.W       08006330               ; R_ARM_ABS32
+
+

Section .text.MODE_SECONDARYPROTECTION_PLUS_Exec from PowerPro_lto.o, size=1108, align=4

+
+
MODE_SECONDARYPROTECTION_PLUS_Exec:
+  0x08004D0C:  B5F0         PUSH       {R4-R7, LR}
+  0x08004D0E:  B085         SUB        SP, SP, #20
+  0x08004D10:  4EEC         LDR        R6, =autoRetryMode.170   ; [PC, #0x03B0] [0x080050C4] =0x200006F0 
+  0x08004D12:  6030         STR        R0, [R6]
+  0x08004D14:  4DEC         LDR        R5, =0x50000418          ; [PC, #0x03B0] [0x080050C8] 
+  0x08004D16:  4628         MOV        R0, R5
+  0x08004D18:  3808         SUBS       R0, #8
+  0x08004D1A:  6800         LDR        R0, [R0]
+  0x08004D1C:  0740         LSLS       R0, R0, #29
+  0x08004D1E:  0FC0         LSRS       R0, R0, #31
+  0x08004D20:  4BEA         LDR        R3, =smState.171         ; [PC, #0x03A8] [0x080050CC] =0x20000731 
+  0x08004D22:  7819         LDRB       R1, [R3]
+  0x08004D24:  2902         CMP        R1, #2
+  0x08004D26:  D038         BEQ        .L1                      ; 0x08004D9A
+  0x08004D28:  2901         CMP        R1, #1
+  0x08004D2A:  D145         BNE        .L2                      ; 0x08004DB8
+  0x08004D2C:  217D         MOVS       R1, #125
+  0x08004D2E:  008A         LSLS       R2, R1, #2
+  0x08004D30:  2701         MOVS       R7, #1
+  0x08004D32:  03BC         LSLS       R4, R7, #14
+  0x08004D34:  03FB         LSLS       R3, R7, #15
+  0x08004D36:  2800         CMP        R0, #0
+  0x08004D38:  4EED         LDR        R6, =0x50000818          ; [PC, #0x03B4] [0x080050F0] 
+  0x08004D3A:  D162         BNE        .L5                      ; 0x08004E02
+  0x08004D3C:  2008         MOVS       R0, #8
+  0x08004D3E:  6128         STR        R0, [R5, #16]
+  0x08004D40:  2010         MOVS       R0, #16
+  0x08004D42:  6028         STR        R0, [R5]
+  0x08004D44:  49E4         LDR        R1, =relaisState         ; [PC, #0x0390] [0x080050D8] =0x20000730 
+  0x08004D46:  2000         MOVS       R0, #0
+  0x08004D48:  7008         STRB       R0, [R1]
+  0x08004D4A:  49F6         LDR        R1, =onTimeCounterRESET  ; [PC, #0x03D8] [0x08005124] =0x200006A0 
+  0x08004D4C:  4616         MOV        R6, R2
+  0x08004D4E:  2232         MOVS       R2, #50
+  0x08004D50:  600A         STR        R2, [R1]
+  0x08004D52:  2120         MOVS       R1, #32
+  0x08004D54:  6029         STR        R1, [R5]
+  0x08004D56:  49E3         LDR        R1, =onTimeCounter       ; [PC, #0x038C] [0x080050E4] =0x200006A8 
+  0x08004D58:  600E         STR        R6, [R1]
+  0x08004D5A:  4DE5         LDR        R5, =0x50000818          ; [PC, #0x0394] [0x080050F0] 
+  0x08004D5C:  612C         STR        R4, [R5, #16]
+  0x08004D5E:  49F2         LDR        R1, =offTimeCounterGN    ; [PC, #0x03C8] [0x08005128] =0x200006B4 
+  0x08004D60:  6008         STR        R0, [R1]
+  0x08004D62:  49E2         LDR        R1, =blinkModeGN         ; [PC, #0x0388] [0x080050EC] =0x20000758 
+  0x08004D64:  7008         STRB       R0, [R1]
+  0x08004D66:  49E3         LDR        R1, =onTimeCounterGN     ; [PC, #0x038C] [0x080050F4] =0x200006A4 
+  0x08004D68:  6008         STR        R0, [R1]
+  0x08004D6A:  49F2         LDR        R1, =onTimeRT            ; [PC, #0x03C8] [0x08005134] =0x2000073C 
+  0x08004D6C:  700F         STRB       R7, [R1]
+  0x08004D6E:  49F2         LDR        R1, =offTimeRT           ; [PC, #0x03C8] [0x08005138] =0x20000748 
+  0x08004D70:  700F         STRB       R7, [R1]
+  0x08004D72:  49E2         LDR        R1, =blinkModeRT         ; [PC, #0x0388] [0x080050FC] =0x20000754 
+  0x08004D74:  700F         STRB       R7, [R1]
+  0x08004D76:  49F1         LDR        R1, =numberOfBlinks      ; [PC, #0x03C4] [0x0800513C] =0x200006BC 
+  0x08004D78:  2203         MOVS       R2, #3
+  0x08004D7A:  600A         STR        R2, [R1]
+  0x08004D7C:  49F0         LDR        R1, =blinkCounter        ; [PC, #0x03C0] [0x08005140] =0x200006EC 
+  0x08004D7E:  600A         STR        R2, [R1]
+  0x08004D80:  49F0         LDR        R1, =pauseTime           ; [PC, #0x03C0] [0x08005144] =0x20000734 
+  0x08004D82:  700F         STRB       R7, [R1]
+  0x08004D84:  602B         STR        R3, [R5]
+  0x08004D86:  49D2         LDR        R1, =buttonState         ; [PC, #0x0348] [0x080050D0] =0x2000073A 
+  0x08004D88:  7008         STRB       R0, [R1]
+  0x08004D8A:  48DD         LDR        R0, =onTimeCounterRT     ; [PC, #0x0374] [0x08005100] =0x2000069C 
+  0x08004D8C:  21C8         MOVS       R1, #200
+  0x08004D8E:  6001         STR        R1, [R0]
+  0x08004D90:  48F2         LDR        R0, =0x08006990          ; [PC, #0x03C8] [0x0800515C] 
+  0x08004D92:  F000 FA2F    BL         puts                     ; 0x080051F4
+  0x08004D96:  48ED         LDR        R0, =0x080067AD          ; [PC, #0x03B4] [0x0800514C] 
+  0x08004D98:  E18C         B          .L23                     ; 0x080050B4
+
.L1:
+  0x08004D9A:  4CCD         LDR        R4, =buttonState         ; [PC, #0x0334] [0x080050D0] =0x2000073A 
+  0x08004D9C:  7821         LDRB       R1, [R4]
+  0x08004D9E:  2901         CMP        R1, #1
+  0x08004DA0:  D168         BNE        .L8                      ; 0x08004E74
+  0x08004DA2:  2800         CMP        R0, #0
+  0x08004DA4:  D13C         BNE        .L7                      ; 0x08004E20
+  0x08004DA6:  2020         MOVS       R0, #32
+  0x08004DA8:  6028         STR        R0, [R5]
+  0x08004DAA:  2000         MOVS       R0, #0
+  0x08004DAC:  7020         STRB       R0, [R4]
+  0x08004DAE:  207D         MOVS       R0, #125
+  0x08004DB0:  0080         LSLS       R0, R0, #2
+  0x08004DB2:  49CC         LDR        R1, =onTimeCounter       ; [PC, #0x0330] [0x080050E4] =0x200006A8 
+  0x08004DB4:  6008         STR        R0, [R1]
+  0x08004DB6:  E05D         B          .L8                      ; 0x08004E74
+
.L2:
+  0x08004DB8:  49D6         LDR        R1, =0x50000010          ; [PC, #0x0358] [0x08005114] 
+  0x08004DBA:  680A         LDR        R2, [R1]
+  0x08004DBC:  07D2         LSLS       R2, R2, #31
+  0x08004DBE:  D000         BEQ        .L3                      ; 0x08004DC2
+  0x08004DC0:  6809         LDR        R1, [R1]
+
.L3:
+  0x08004DC2:  4AC3         LDR        R2, =buttonState         ; [PC, #0x030C] [0x080050D0] =0x2000073A 
+  0x08004DC4:  7811         LDRB       R1, [R2]
+  0x08004DC6:  2901         CMP        R1, #1
+  0x08004DC8:  D000         BEQ        .L4                      ; 0x08004DCC
+  0x08004DCA:  E178         B          .L24                     ; 0x080050BE
+
.L4:
+  0x08004DCC:  2800         CMP        R0, #0
+  0x08004DCE:  D16E         BNE        .L13                     ; 0x08004EAE
+  0x08004DD0:  2020         MOVS       R0, #32
+  0x08004DD2:  6028         STR        R0, [R5]
+  0x08004DD4:  2000         MOVS       R0, #0
+  0x08004DD6:  7010         STRB       R0, [R2]
+  0x08004DD8:  207D         MOVS       R0, #125
+  0x08004DDA:  0080         LSLS       R0, R0, #2
+  0x08004DDC:  4AC1         LDR        R2, =onTimeCounter       ; [PC, #0x0304] [0x080050E4] =0x200006A8 
+  0x08004DDE:  6010         STR        R0, [R2]
+  0x08004DE0:  48D4         LDR        R0, =onTimeRT            ; [PC, #0x0350] [0x08005134] =0x2000073C 
+  0x08004DE2:  7001         STRB       R1, [R0]
+  0x08004DE4:  48D4         LDR        R0, =offTimeRT           ; [PC, #0x0350] [0x08005138] =0x20000748 
+  0x08004DE6:  7001         STRB       R1, [R0]
+  0x08004DE8:  48C4         LDR        R0, =blinkModeRT         ; [PC, #0x0310] [0x080050FC] =0x20000754 
+  0x08004DEA:  7001         STRB       R1, [R0]
+  0x08004DEC:  48D3         LDR        R0, =numberOfBlinks      ; [PC, #0x034C] [0x0800513C] =0x200006BC 
+  0x08004DEE:  2203         MOVS       R2, #3
+  0x08004DF0:  6002         STR        R2, [R0]
+  0x08004DF2:  48D3         LDR        R0, =blinkCounter        ; [PC, #0x034C] [0x08005140] =0x200006EC 
+  0x08004DF4:  6002         STR        R2, [R0]
+  0x08004DF6:  03CA         LSLS       R2, R1, #15
+  0x08004DF8:  2402         MOVS       R4, #2
+  0x08004DFA:  48D4         LDR        R0, =0x080067AD          ; [PC, #0x0350] [0x0800514C] 
+  0x08004DFC:  4BC0         LDR        R3, =onTimeCounterRT     ; [PC, #0x0300] [0x08005100] =0x2000069C 
+  0x08004DFE:  4DD1         LDR        R5, =pauseTime           ; [PC, #0x0344] [0x08005144] =0x20000734 
+  0x08004E00:  E06C         B          .L14                     ; 0x08004EDC
+
.L5:
+  0x08004E02:  9101         STR        R1, [SP, #4]
+  0x08004E04:  48C3         LDR        R0, =0x50000010          ; [PC, #0x030C] [0x08005114] 
+  0x08004E06:  6801         LDR        R1, [R0]
+  0x08004E08:  07C9         LSLS       R1, R1, #31
+  0x08004E0A:  9303         STR        R3, [SP, #12]
+  0x08004E0C:  9404         STR        R4, [SP, #16]
+  0x08004E0E:  9202         STR        R2, [SP, #8]
+  0x08004E10:  D002         BEQ        .L6                      ; 0x08004E18
+  0x08004E12:  6800         LDR        R0, [R0]
+  0x08004E14:  0780         LSLS       R0, R0, #30
+  0x08004E16:  D46B         BMI        .L15                     ; 0x08004EF0
+
.L6:
+  0x08004E18:  48C0         LDR        R0, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 ; [PC, #0x0300] [0x0800511C] =0x20000700 
+  0x08004E1A:  2400         MOVS       R4, #0
+  0x08004E1C:  6004         STR        R4, [R0]
+  0x08004E1E:  E07E         B          .L19                     ; 0x08004F1E
+
.L7:
+  0x08004E20:  49AC         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x02B0] [0x080050D4] =0x20000708 
+  0x08004E22:  2000         MOVS       R0, #0
+  0x08004E24:  6008         STR        R0, [R1]
+  0x08004E26:  2110         MOVS       R1, #16
+  0x08004E28:  6129         STR        R1, [R5, #16]
+  0x08004E2A:  2108         MOVS       R1, #8
+  0x08004E2C:  6029         STR        R1, [R5]
+  0x08004E2E:  49AA         LDR        R1, =relaisState         ; [PC, #0x02A8] [0x080050D8] =0x20000730 
+  0x08004E30:  2701         MOVS       R7, #1
+  0x08004E32:  700F         STRB       R7, [R1]
+  0x08004E34:  49A9         LDR        R1, =onTimeCounterSET    ; [PC, #0x02A4] [0x080050DC] =0x20000698 
+  0x08004E36:  2232         MOVS       R2, #50
+  0x08004E38:  600A         STR        R2, [R1]
+  0x08004E3A:  2120         MOVS       R1, #32
+  0x08004E3C:  6029         STR        R1, [R5]
+  0x08004E3E:  49A8         LDR        R1, =onTimeGN            ; [PC, #0x02A0] [0x080050E0] =0x20000740 
+  0x08004E40:  700F         STRB       R7, [R1]
+  0x08004E42:  49A8         LDR        R1, =onTimeCounter       ; [PC, #0x02A0] [0x080050E4] =0x200006A8 
+  0x08004E44:  22C8         MOVS       R2, #200
+  0x08004E46:  600A         STR        R2, [R1]
+  0x08004E48:  49A7         LDR        R1, =offTimeGN           ; [PC, #0x029C] [0x080050E8] =0x2000074C 
+  0x08004E4A:  700F         STRB       R7, [R1]
+  0x08004E4C:  49A7         LDR        R1, =blinkModeGN         ; [PC, #0x029C] [0x080050EC] =0x20000758 
+  0x08004E4E:  700F         STRB       R7, [R1]
+  0x08004E50:  03B9         LSLS       R1, R7, #14
+  0x08004E52:  461D         MOV        R5, R3
+  0x08004E54:  4BA6         LDR        R3, =0x50000818          ; [PC, #0x0298] [0x080050F0] 
+  0x08004E56:  6019         STR        R1, [R3]
+  0x08004E58:  49A6         LDR        R1, =onTimeCounterGN     ; [PC, #0x0298] [0x080050F4] =0x200006A4 
+  0x08004E5A:  600A         STR        R2, [R1]
+  0x08004E5C:  03F9         LSLS       R1, R7, #15
+  0x08004E5E:  6119         STR        R1, [R3, #16]
+  0x08004E60:  49A5         LDR        R1, =offTimeCounterRT    ; [PC, #0x0294] [0x080050F8] =0x200006B0 
+  0x08004E62:  6008         STR        R0, [R1]
+  0x08004E64:  49A5         LDR        R1, =blinkModeRT         ; [PC, #0x0294] [0x080050FC] =0x20000754 
+  0x08004E66:  7008         STRB       R0, [R1]
+  0x08004E68:  49A5         LDR        R1, =onTimeCounterRT     ; [PC, #0x0294] [0x08005100] =0x2000069C 
+  0x08004E6A:  6008         STR        R0, [R1]
+  0x08004E6C:  48A5         LDR        R0, =0x0800654D          ; [PC, #0x0294] [0x08005104] 
+  0x08004E6E:  F000 F9C1    BL         puts                     ; 0x080051F4
+  0x08004E72:  702F         STRB       R7, [R5]
+
.L8:
+  0x08004E74:  6830         LDR        R0, [R6]
+  0x08004E76:  2801         CMP        R0, #1
+  0x08004E78:  D000         BEQ        .L9                      ; 0x08004E7C
+  0x08004E7A:  E120         B          .L24                     ; 0x080050BE
+
.L9:
+  0x08004E7C:  48A2         LDR        R0, =uwTick              ; [PC, #0x0288] [0x08005108] =0x2000068C 
+  0x08004E7E:  6802         LDR        R2, [R0]
+  0x08004E80:  49A2         LDR        R1, =SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182 ; [PC, #0x0288] [0x0800510C] =0x20000710 
+  0x08004E82:  680B         LDR        R3, [R1]
+  0x08004E84:  4293         CMP        R3, R2
+  0x08004E86:  D102         BNE        .L10                     ; 0x08004E8E
+  0x08004E88:  4892         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0248] [0x080050D4] =0x20000708 
+  0x08004E8A:  6800         LDR        R0, [R0]
+  0x08004E8C:  E005         B          .L11                     ; 0x08004E9A
+
.L10:
+  0x08004E8E:  6800         LDR        R0, [R0]
+  0x08004E90:  6008         STR        R0, [R1]
+  0x08004E92:  4990         LDR        R1, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0240] [0x080050D4] =0x20000708 
+  0x08004E94:  6808         LDR        R0, [R1]
+  0x08004E96:  1C40         ADDS       R0, R0, #1
+  0x08004E98:  6008         STR        R0, [R1]
+
.L11:
+  0x08004E9A:  499D         LDR        R1, =0x0036EE81          ; [PC, #0x0274] [0x08005110] 
+  0x08004E9C:  4288         CMP        R0, R1
+  0x08004E9E:  D200         BCS        .L12                     ; 0x08004EA2
+  0x08004EA0:  E10D         B          .L24                     ; 0x080050BE
+
.L12:
+  0x08004EA2:  488C         LDR        R0, =SECONDARYPROTECTION_SM_Error.retry_counter.181 ; [PC, #0x0230] [0x080050D4] =0x20000708 
+  0x08004EA4:  2100         MOVS       R1, #0
+  0x08004EA6:  6001         STR        R1, [R0]
+  0x08004EA8:  2001         MOVS       R0, #1
+  0x08004EAA:  7020         STRB       R0, [R4]
+  0x08004EAC:  E107         B          .L24                     ; 0x080050BE
+
.L13:
+  0x08004EAE:  2010         MOVS       R0, #16
+  0x08004EB0:  6128         STR        R0, [R5, #16]
+  0x08004EB2:  2008         MOVS       R0, #8
+  0x08004EB4:  6028         STR        R0, [R5]
+  0x08004EB6:  4888         LDR        R0, =relaisState         ; [PC, #0x0220] [0x080050D8] =0x20000730 
+  0x08004EB8:  7001         STRB       R1, [R0]
+  0x08004EBA:  4888         LDR        R0, =onTimeCounterSET    ; [PC, #0x0220] [0x080050DC] =0x20000698 
+  0x08004EBC:  2232         MOVS       R2, #50
+  0x08004EBE:  6002         STR        R2, [R0]
+  0x08004EC0:  2020         MOVS       R0, #32
+  0x08004EC2:  6028         STR        R0, [R5]
+  0x08004EC4:  4886         LDR        R0, =onTimeGN            ; [PC, #0x0218] [0x080050E0] =0x20000740 
+  0x08004EC6:  7001         STRB       R1, [R0]
+  0x08004EC8:  4886         LDR        R0, =onTimeCounter       ; [PC, #0x0218] [0x080050E4] =0x200006A8 
+  0x08004ECA:  22C8         MOVS       R2, #200
+  0x08004ECC:  6002         STR        R2, [R0]
+  0x08004ECE:  4886         LDR        R0, =offTimeGN           ; [PC, #0x0218] [0x080050E8] =0x2000074C 
+  0x08004ED0:  7001         STRB       R1, [R0]
+  0x08004ED2:  038A         LSLS       R2, R1, #14
+  0x08004ED4:  488B         LDR        R0, =0x0800654D          ; [PC, #0x022C] [0x08005104] 
+  0x08004ED6:  4B87         LDR        R3, =onTimeCounterGN     ; [PC, #0x021C] [0x080050F4] =0x200006A4 
+  0x08004ED8:  4D84         LDR        R5, =blinkModeGN         ; [PC, #0x0210] [0x080050EC] =0x20000758 
+  0x08004EDA:  460C         MOV        R4, R1
+
.L14:
+  0x08004EDC:  7029         STRB       R1, [R5]
+  0x08004EDE:  4984         LDR        R1, =0x50000818          ; [PC, #0x0210] [0x080050F0] 
+  0x08004EE0:  600A         STR        R2, [R1]
+  0x08004EE2:  21C8         MOVS       R1, #200
+  0x08004EE4:  6019         STR        R1, [R3]
+  0x08004EE6:  F000 F985    BL         puts                     ; 0x080051F4
+  0x08004EEA:  4878         LDR        R0, =smState.171         ; [PC, #0x01E0] [0x080050CC] =0x20000731 
+  0x08004EEC:  7004         STRB       R4, [R0]
+  0x08004EEE:  E0E6         B          .L24                     ; 0x080050BE
+
.L15:
+  0x08004EF0:  4889         LDR        R0, =SECONDARYPROTECTION_SM_On.oldtime.175 ; [PC, #0x0224] [0x08005118] =0x200006F8 
+  0x08004EF2:  6802         LDR        R2, [R0]
+  0x08004EF4:  4984         LDR        R1, =uwTick              ; [PC, #0x0210] [0x08005108] =0x2000068C 
+  0x08004EF6:  680B         LDR        R3, [R1]
+  0x08004EF8:  4293         CMP        R3, R2
+  0x08004EFA:  D00D         BEQ        .L17                     ; 0x08004F18
+  0x08004EFC:  6809         LDR        R1, [R1]
+  0x08004EFE:  6001         STR        R1, [R0]
+  0x08004F00:  4986         LDR        R1, =SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 ; [PC, #0x0218] [0x0800511C] =0x20000700 
+  0x08004F02:  680B         LDR        R3, [R1]
+  0x08004F04:  1C5A         ADDS       R2, R3, #1
+  0x08004F06:  2000         MOVS       R0, #0
+  0x08004F08:  4C85         LDR        R4, =0x0000752F          ; [PC, #0x0214] [0x08005120] 
+  0x08004F0A:  42A3         CMP        R3, R4
+  0x08004F0C:  4603         MOV        R3, R0
+  0x08004F0E:  DC00         BGT        .L16                     ; 0x08004F12
+  0x08004F10:  4613         MOV        R3, R2
+
.L16:
+  0x08004F12:  600B         STR        R3, [R1]
+  0x08004F14:  463C         MOV        R4, R7
+  0x08004F16:  DC00         BGT        .L18                     ; 0x08004F1A
+
.L17:
+  0x08004F18:  2400         MOVS       R4, #0
+
.L18:
+  0x08004F1A:  9B03         LDR        R3, [SP, #12]
+  0x08004F1C:  9A02         LDR        R2, [SP, #8]
+
.L19:
+  0x08004F1E:  9901         LDR        R1, [SP, #4]
+  0x08004F20:  486B         LDR        R0, =buttonState         ; [PC, #0x01AC] [0x080050D0] =0x2000073A 
+  0x08004F22:  7800         LDRB       R0, [R0]
+  0x08004F24:  2800         CMP        R0, #0
+  0x08004F26:  9400         STR        R4, [SP, #0]
+  0x08004F28:  D125         BNE        .L20                     ; 0x08004F76
+  0x08004F2A:  2008         MOVS       R0, #8
+  0x08004F2C:  6128         STR        R0, [R5, #16]
+  0x08004F2E:  2010         MOVS       R0, #16
+  0x08004F30:  6028         STR        R0, [R5]
+  0x08004F32:  4869         LDR        R0, =relaisState         ; [PC, #0x01A4] [0x080050D8] =0x20000730 
+  0x08004F34:  2400         MOVS       R4, #0
+  0x08004F36:  7004         STRB       R4, [R0]
+  0x08004F38:  487A         LDR        R0, =onTimeCounterRESET  ; [PC, #0x01E8] [0x08005124] =0x200006A0 
+  0x08004F3A:  2132         MOVS       R1, #50
+  0x08004F3C:  6001         STR        R1, [R0]
+  0x08004F3E:  2020         MOVS       R0, #32
+  0x08004F40:  6028         STR        R0, [R5]
+  0x08004F42:  4868         LDR        R0, =onTimeCounter       ; [PC, #0x01A0] [0x080050E4] =0x200006A8 
+  0x08004F44:  21C8         MOVS       R1, #200
+  0x08004F46:  6001         STR        R1, [R0]
+  0x08004F48:  9804         LDR        R0, [SP, #16]
+  0x08004F4A:  6130         STR        R0, [R6, #16]
+  0x08004F4C:  4876         LDR        R0, =offTimeCounterGN    ; [PC, #0x01D8] [0x08005128] =0x200006B4 
+  0x08004F4E:  6004         STR        R4, [R0]
+  0x08004F50:  4866         LDR        R0, =blinkModeGN         ; [PC, #0x0198] [0x080050EC] =0x20000758 
+  0x08004F52:  7004         STRB       R4, [R0]
+  0x08004F54:  4867         LDR        R0, =onTimeCounterGN     ; [PC, #0x019C] [0x080050F4] =0x200006A4 
+  0x08004F56:  6004         STR        R4, [R0]
+  0x08004F58:  6133         STR        R3, [R6, #16]
+  0x08004F5A:  4867         LDR        R0, =offTimeCounterRT    ; [PC, #0x019C] [0x080050F8] =0x200006B0 
+  0x08004F5C:  6004         STR        R4, [R0]
+  0x08004F5E:  4867         LDR        R0, =blinkModeRT         ; [PC, #0x019C] [0x080050FC] =0x20000754 
+  0x08004F60:  7004         STRB       R4, [R0]
+  0x08004F62:  4867         LDR        R0, =onTimeCounterRT     ; [PC, #0x019C] [0x08005100] =0x2000069C 
+  0x08004F64:  6004         STR        R4, [R0]
+  0x08004F66:  4871         LDR        R0, =0x0800630D          ; [PC, #0x01C4] [0x0800512C] 
+  0x08004F68:  F000 F944    BL         puts                     ; 0x080051F4
+  0x08004F6C:  A901         ADD        R1, SP, #4
+  0x08004F6E:  C90E         LDM        R1, {R1-R3}
+  0x08004F70:  4856         LDR        R0, =smState.171         ; [PC, #0x0158] [0x080050CC] =0x20000731 
+  0x08004F72:  7004         STRB       R4, [R0]
+  0x08004F74:  9C00         LDR        R4, [SP, #0]
+
.L20:
+  0x08004F76:  00C8         LSLS       R0, R1, #3
+  0x08004F78:  496D         LDR        R1, =dropLimitCounter    ; [PC, #0x01B4] [0x08005130] =0x200006E4 
+  0x08004F7A:  6809         LDR        R1, [R1]
+  0x08004F7C:  4281         CMP        R1, R0
+  0x08004F7E:  D135         BNE        .L21                     ; 0x08004FEC
+  0x08004F80:  2008         MOVS       R0, #8
+  0x08004F82:  6128         STR        R0, [R5, #16]
+  0x08004F84:  2010         MOVS       R0, #16
+  0x08004F86:  6028         STR        R0, [R5]
+  0x08004F88:  4853         LDR        R0, =relaisState         ; [PC, #0x014C] [0x080050D8] =0x20000730 
+  0x08004F8A:  2400         MOVS       R4, #0
+  0x08004F8C:  7004         STRB       R4, [R0]
+  0x08004F8E:  4865         LDR        R0, =onTimeCounterRESET  ; [PC, #0x0194] [0x08005124] =0x200006A0 
+  0x08004F90:  2132         MOVS       R1, #50
+  0x08004F92:  6001         STR        R1, [R0]
+  0x08004F94:  2020         MOVS       R0, #32
+  0x08004F96:  6028         STR        R0, [R5]
+  0x08004F98:  4852         LDR        R0, =onTimeCounter       ; [PC, #0x0148] [0x080050E4] =0x200006A8 
+  0x08004F9A:  6002         STR        R2, [R0]
+  0x08004F9C:  9804         LDR        R0, [SP, #16]
+  0x08004F9E:  6130         STR        R0, [R6, #16]
+  0x08004FA0:  4861         LDR        R0, =offTimeCounterGN    ; [PC, #0x0184] [0x08005128] =0x200006B4 
+  0x08004FA2:  6004         STR        R4, [R0]
+  0x08004FA4:  4851         LDR        R0, =blinkModeGN         ; [PC, #0x0144] [0x080050EC] =0x20000758 
+  0x08004FA6:  7004         STRB       R4, [R0]
+  0x08004FA8:  4852         LDR        R0, =onTimeCounterGN     ; [PC, #0x0148] [0x080050F4] =0x200006A4 
+  0x08004FAA:  6004         STR        R4, [R0]
+  0x08004FAC:  4861         LDR        R0, =onTimeRT            ; [PC, #0x0184] [0x08005134] =0x2000073C 
+  0x08004FAE:  7007         STRB       R7, [R0]
+  0x08004FB0:  4861         LDR        R0, =offTimeRT           ; [PC, #0x0184] [0x08005138] =0x20000748 
+  0x08004FB2:  7007         STRB       R7, [R0]
+  0x08004FB4:  4851         LDR        R0, =blinkModeRT         ; [PC, #0x0144] [0x080050FC] =0x20000754 
+  0x08004FB6:  7007         STRB       R7, [R0]
+  0x08004FB8:  4860         LDR        R0, =numberOfBlinks      ; [PC, #0x0180] [0x0800513C] =0x200006BC 
+  0x08004FBA:  2104         MOVS       R1, #4
+  0x08004FBC:  6001         STR        R1, [R0]
+  0x08004FBE:  4860         LDR        R0, =blinkCounter        ; [PC, #0x0180] [0x08005140] =0x200006EC 
+  0x08004FC0:  6001         STR        R1, [R0]
+  0x08004FC2:  4860         LDR        R0, =pauseTime           ; [PC, #0x0180] [0x08005144] =0x20000734 
+  0x08004FC4:  7007         STRB       R7, [R0]
+  0x08004FC6:  6033         STR        R3, [R6]
+  0x08004FC8:  4841         LDR        R0, =buttonState         ; [PC, #0x0104] [0x080050D0] =0x2000073A 
+  0x08004FCA:  7004         STRB       R4, [R0]
+  0x08004FCC:  484C         LDR        R0, =onTimeCounterRT     ; [PC, #0x0130] [0x08005100] =0x2000069C 
+  0x08004FCE:  21C8         MOVS       R1, #200
+  0x08004FD0:  6001         STR        R1, [R0]
+  0x08004FD2:  485D         LDR        R0, =0x08006790          ; [PC, #0x0174] [0x08005148] 
+  0x08004FD4:  F000 F90E    BL         puts                     ; 0x080051F4
+  0x08004FD8:  485C         LDR        R0, =0x080067AD          ; [PC, #0x0170] [0x0800514C] 
+  0x08004FDA:  F000 F90B    BL         puts                     ; 0x080051F4
+  0x08004FDE:  9B03         LDR        R3, [SP, #12]
+  0x08004FE0:  2002         MOVS       R0, #2
+  0x08004FE2:  493A         LDR        R1, =smState.171         ; [PC, #232] [0x080050CC] =0x20000731 
+  0x08004FE4:  7008         STRB       R0, [R1]
+  0x08004FE6:  4852         LDR        R0, =dropLimitCounter    ; [PC, #0x0148] [0x08005130] =0x200006E4 
+  0x08004FE8:  6004         STR        R4, [R0]
+  0x08004FEA:  9C00         LDR        R4, [SP, #0]
+
.L21:
+  0x08004FEC:  2C00         CMP        R4, #0
+  0x08004FEE:  D032         BEQ        .L22                     ; 0x08005056
+  0x08004FF0:  2008         MOVS       R0, #8
+  0x08004FF2:  6128         STR        R0, [R5, #16]
+  0x08004FF4:  2010         MOVS       R0, #16
+  0x08004FF6:  6028         STR        R0, [R5]
+  0x08004FF8:  4937         LDR        R1, =relaisState         ; [PC, #220] [0x080050D8] =0x20000730 
+  0x08004FFA:  2000         MOVS       R0, #0
+  0x08004FFC:  7008         STRB       R0, [R1]
+  0x08004FFE:  4949         LDR        R1, =onTimeCounterRESET  ; [PC, #0x0124] [0x08005124] =0x200006A0 
+  0x08005000:  2232         MOVS       R2, #50
+  0x08005002:  600A         STR        R2, [R1]
+  0x08005004:  2120         MOVS       R1, #32
+  0x08005006:  6029         STR        R1, [R5]
+  0x08005008:  4936         LDR        R1, =onTimeCounter       ; [PC, #216] [0x080050E4] =0x200006A8 
+  0x0800500A:  9A02         LDR        R2, [SP, #8]
+  0x0800500C:  600A         STR        R2, [R1]
+  0x0800500E:  9904         LDR        R1, [SP, #16]
+  0x08005010:  6131         STR        R1, [R6, #16]
+  0x08005012:  4945         LDR        R1, =offTimeCounterGN    ; [PC, #0x0114] [0x08005128] =0x200006B4 
+  0x08005014:  6008         STR        R0, [R1]
+  0x08005016:  4935         LDR        R1, =blinkModeGN         ; [PC, #212] [0x080050EC] =0x20000758 
+  0x08005018:  7008         STRB       R0, [R1]
+  0x0800501A:  4936         LDR        R1, =onTimeCounterGN     ; [PC, #216] [0x080050F4] =0x200006A4 
+  0x0800501C:  6008         STR        R0, [R1]
+  0x0800501E:  4945         LDR        R1, =onTimeRT            ; [PC, #0x0114] [0x08005134] =0x2000073C 
+  0x08005020:  700F         STRB       R7, [R1]
+  0x08005022:  4945         LDR        R1, =offTimeRT           ; [PC, #0x0114] [0x08005138] =0x20000748 
+  0x08005024:  700F         STRB       R7, [R1]
+  0x08005026:  4935         LDR        R1, =blinkModeRT         ; [PC, #212] [0x080050FC] =0x20000754 
+  0x08005028:  700F         STRB       R7, [R1]
+  0x0800502A:  4944         LDR        R1, =numberOfBlinks      ; [PC, #0x0110] [0x0800513C] =0x200006BC 
+  0x0800502C:  2402         MOVS       R4, #2
+  0x0800502E:  600C         STR        R4, [R1]
+  0x08005030:  4943         LDR        R1, =blinkCounter        ; [PC, #0x010C] [0x08005140] =0x200006EC 
+  0x08005032:  600C         STR        R4, [R1]
+  0x08005034:  4943         LDR        R1, =pauseTime           ; [PC, #0x010C] [0x08005144] =0x20000734 
+  0x08005036:  700F         STRB       R7, [R1]
+  0x08005038:  6033         STR        R3, [R6]
+  0x0800503A:  4925         LDR        R1, =buttonState         ; [PC, #148] [0x080050D0] =0x2000073A 
+  0x0800503C:  7008         STRB       R0, [R1]
+  0x0800503E:  4830         LDR        R0, =onTimeCounterRT     ; [PC, #192] [0x08005100] =0x2000069C 
+  0x08005040:  21C8         MOVS       R1, #200
+  0x08005042:  6001         STR        R1, [R0]
+  0x08005044:  4842         LDR        R0, =0x08006954          ; [PC, #0x0108] [0x08005150] 
+  0x08005046:  F000 F8D5    BL         puts                     ; 0x080051F4
+  0x0800504A:  4840         LDR        R0, =0x080067AD          ; [PC, #0x0100] [0x0800514C] 
+  0x0800504C:  F000 F8D2    BL         puts                     ; 0x080051F4
+  0x08005050:  9B03         LDR        R3, [SP, #12]
+  0x08005052:  481E         LDR        R0, =smState.171         ; [PC, #120] [0x080050CC] =0x20000731 
+  0x08005054:  7004         STRB       R4, [R0]
+
.L22:
+  0x08005056:  483F         LDR        R0, =temp                ; [PC, #252] [0x08005154] =0x20000690 
+  0x08005058:  6800         LDR        R0, [R0]
+  0x0800505A:  2851         CMP        R0, #81
+  0x0800505C:  9C04         LDR        R4, [SP, #16]
+  0x0800505E:  DB2E         BLT        .L24                     ; 0x080050BE
+  0x08005060:  2008         MOVS       R0, #8
+  0x08005062:  6128         STR        R0, [R5, #16]
+  0x08005064:  2010         MOVS       R0, #16
+  0x08005066:  6028         STR        R0, [R5]
+  0x08005068:  491B         LDR        R1, =relaisState         ; [PC, #108] [0x080050D8] =0x20000730 
+  0x0800506A:  2000         MOVS       R0, #0
+  0x0800506C:  7008         STRB       R0, [R1]
+  0x0800506E:  492D         LDR        R1, =onTimeCounterRESET  ; [PC, #180] [0x08005124] =0x200006A0 
+  0x08005070:  2232         MOVS       R2, #50
+  0x08005072:  600A         STR        R2, [R1]
+  0x08005074:  2120         MOVS       R1, #32
+  0x08005076:  6029         STR        R1, [R5]
+  0x08005078:  491A         LDR        R1, =onTimeCounter       ; [PC, #104] [0x080050E4] =0x200006A8 
+  0x0800507A:  9A02         LDR        R2, [SP, #8]
+  0x0800507C:  600A         STR        R2, [R1]
+  0x0800507E:  6134         STR        R4, [R6, #16]
+  0x08005080:  4929         LDR        R1, =offTimeCounterGN    ; [PC, #164] [0x08005128] =0x200006B4 
+  0x08005082:  6008         STR        R0, [R1]
+  0x08005084:  4919         LDR        R1, =blinkModeGN         ; [PC, #100] [0x080050EC] =0x20000758 
+  0x08005086:  7008         STRB       R0, [R1]
+  0x08005088:  491A         LDR        R1, =onTimeCounterGN     ; [PC, #104] [0x080050F4] =0x200006A4 
+  0x0800508A:  6008         STR        R0, [R1]
+  0x0800508C:  4929         LDR        R1, =onTimeRT            ; [PC, #164] [0x08005134] =0x2000073C 
+  0x0800508E:  700F         STRB       R7, [R1]
+  0x08005090:  4929         LDR        R1, =offTimeRT           ; [PC, #164] [0x08005138] =0x20000748 
+  0x08005092:  700F         STRB       R7, [R1]
+  0x08005094:  4919         LDR        R1, =blinkModeRT         ; [PC, #100] [0x080050FC] =0x20000754 
+  0x08005096:  700F         STRB       R7, [R1]
+  0x08005098:  4928         LDR        R1, =numberOfBlinks      ; [PC, #160] [0x0800513C] =0x200006BC 
+  0x0800509A:  2205         MOVS       R2, #5
+  0x0800509C:  600A         STR        R2, [R1]
+  0x0800509E:  4928         LDR        R1, =blinkCounter        ; [PC, #160] [0x08005140] =0x200006EC 
+  0x080050A0:  600A         STR        R2, [R1]
+  0x080050A2:  4928         LDR        R1, =pauseTime           ; [PC, #160] [0x08005144] =0x20000734 
+  0x080050A4:  700F         STRB       R7, [R1]
+  0x080050A6:  6033         STR        R3, [R6]
+  0x080050A8:  4909         LDR        R1, =buttonState         ; [PC, #36] [0x080050D0] =0x2000073A 
+  0x080050AA:  7008         STRB       R0, [R1]
+  0x080050AC:  4814         LDR        R0, =onTimeCounterRT     ; [PC, #80] [0x08005100] =0x2000069C 
+  0x080050AE:  21C8         MOVS       R1, #200
+  0x080050B0:  6001         STR        R1, [R0]
+  0x080050B2:  4829         LDR        R0, =0x08006330          ; [PC, #164] [0x08005158] 
+
.L23:
+  0x080050B4:  F000 F89E    BL         puts                     ; 0x080051F4
+  0x080050B8:  2002         MOVS       R0, #2
+  0x080050BA:  4904         LDR        R1, =smState.171         ; [PC, #16] [0x080050CC] =0x20000731 
+  0x080050BC:  7008         STRB       R0, [R1]
+
.L24:
+  0x080050BE:  B005         ADD        SP, SP, #20
+  0x080050C0:  BDF0         POP        {R4-R7, PC}
+  0x080050C2:  46C0         NOP
+  0x080050C4:  200006F0     DC.W       autoRetryMode.170
+  0x080050C8:  50000418     DC.W       0x50000418
+  0x080050CC:  20000731     DC.W       smState.171
+  0x080050D0:  2000073A     DC.W       buttonState
+  0x080050D4:  20000708     DC.W       SECONDARYPROTECTION_SM_Error.retry_counter.181
+  0x080050D8:  20000730     DC.W       relaisState
+  0x080050DC:  20000698     DC.W       onTimeCounterSET
+  0x080050E0:  20000740     DC.W       onTimeGN
+  0x080050E4:  200006A8     DC.W       onTimeCounter
+  0x080050E8:  2000074C     DC.W       offTimeGN
+  0x080050EC:  20000758     DC.W       blinkModeGN
+  0x080050F0:  50000818     DC.W       0x50000818
+  0x080050F4:  200006A4     DC.W       onTimeCounterGN
+  0x080050F8:  200006B0     DC.W       offTimeCounterRT
+  0x080050FC:  20000754     DC.W       blinkModeRT
+  0x08005100:  2000069C     DC.W       onTimeCounterRT
+  0x08005104:  0800654D     DC.W       0800654D               ; R_ARM_ABS32
+  0x08005108:  2000068C     DC.W       uwTick
+  0x0800510C:  20000710     DC.W       SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182
+  0x08005110:  0036EE81     DC.W       0x0036EE81
+  0x08005114:  50000010     DC.W       0x50000010
+  0x08005118:  200006F8     DC.W       SECONDARYPROTECTION_SM_On.oldtime.175
+  0x0800511C:  20000700     DC.W       SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176
+  0x08005120:  0000752F     DC.W       0x0000752F
+  0x08005124:  200006A0     DC.W       onTimeCounterRESET
+  0x08005128:  200006B4     DC.W       offTimeCounterGN
+  0x0800512C:  0800630D     DC.W       0800630D               ; R_ARM_ABS32
+  0x08005130:  200006E4     DC.W       dropLimitCounter
+  0x08005134:  2000073C     DC.W       onTimeRT
+  0x08005138:  20000748     DC.W       offTimeRT
+  0x0800513C:  200006BC     DC.W       numberOfBlinks
+  0x08005140:  200006EC     DC.W       blinkCounter
+  0x08005144:  20000734     DC.W       pauseTime
+  0x08005148:  08006790     DC.W       08006790               ; R_ARM_ABS32
+  0x0800514C:  080067AD     DC.W       080067AD               ; R_ARM_ABS32
+  0x08005150:  08006954     DC.W       08006954               ; R_ARM_ABS32
+  0x08005154:  20000690     DC.W       temp
+  0x08005158:  08006330     DC.W       08006330               ; R_ARM_ABS32
+  0x0800515C:  08006990     DC.W       08006990               ; R_ARM_ABS32
+
+

Section .rodata.AHBPrescTable from PowerPro_lto.o, size=64, align=4

+
+
AHBPrescTable:
+  0x08005160:  00           DC.B       0x00                     ; '\0'
+  0x08005161:  00           DC.B       0x00                     ; '\0'
+  0x08005162:  00           DC.B       0x00                     ; '\0'
+  0x08005163:  00           DC.B       0x00                     ; '\0'
+  0x08005164:  00           DC.B       0x00                     ; '\0'
+  0x08005165:  00           DC.B       0x00                     ; '\0'
+  0x08005166:  00           DC.B       0x00                     ; '\0'
+  0x08005167:  00           DC.B       0x00                     ; '\0'
+  0x08005168:  00           DC.B       0x00                     ; '\0'
+  0x08005169:  00           DC.B       0x00                     ; '\0'
+  0x0800516A:  00           DC.B       0x00                     ; '\0'
+  0x0800516B:  00           DC.B       0x00                     ; '\0'
+  0x0800516C:  00           DC.B       0x00                     ; '\0'
+  0x0800516D:  00           DC.B       0x00                     ; '\0'
+  0x0800516E:  00           DC.B       0x00                     ; '\0'
+  0x0800516F:  00           DC.B       0x00                     ; '\0'
+  0x08005170:  00           DC.B       0x00                     ; '\0'
+  0x08005171:  00           DC.B       0x00                     ; '\0'
+  0x08005172:  00           DC.B       0x00                     ; '\0'
+  0x08005173:  00           DC.B       0x00                     ; '\0'
+  0x08005174:  00           DC.B       0x00                     ; '\0'
+  0x08005175:  00           DC.B       0x00                     ; '\0'
+  0x08005176:  00           DC.B       0x00                     ; '\0'
+  0x08005177:  00           DC.B       0x00                     ; '\0'
+  0x08005178:  00           DC.B       0x00                     ; '\0'
+  0x08005179:  00           DC.B       0x00                     ; '\0'
+  0x0800517A:  00           DC.B       0x00                     ; '\0'
+  0x0800517B:  00           DC.B       0x00                     ; '\0'
+  0x0800517C:  00           DC.B       0x00                     ; '\0'
+  0x0800517D:  00           DC.B       0x00                     ; '\0'
+  0x0800517E:  00           DC.B       0x00                     ; '\0'
+  0x0800517F:  00           DC.B       0x00                     ; '\0'
+  0x08005180:  01           DC.B       0x01                     ; '\x01'
+  0x08005181:  00           DC.B       0x00                     ; '\0'
+  0x08005182:  00           DC.B       0x00                     ; '\0'
+  0x08005183:  00           DC.B       0x00                     ; '\0'
+  0x08005184:  02           DC.B       0x02                     ; '\x02'
+  0x08005185:  00           DC.B       0x00                     ; '\0'
+  0x08005186:  00           DC.B       0x00                     ; '\0'
+  0x08005187:  00           DC.B       0x00                     ; '\0'
+  0x08005188:  03           DC.B       0x03                     ; '\x03'
+  0x08005189:  00           DC.B       0x00                     ; '\0'
+  0x0800518A:  00           DC.B       0x00                     ; '\0'
+  0x0800518B:  00           DC.B       0x00                     ; '\0'
+  0x0800518C:  04           DC.B       0x04                     ; '\x04'
+  0x0800518D:  00           DC.B       0x00                     ; '\0'
+  0x0800518E:  00           DC.B       0x00                     ; '\0'
+  0x0800518F:  00           DC.B       0x00                     ; '\0'
+  0x08005190:  06           DC.B       0x06                     ; '\x06'
+  0x08005191:  00           DC.B       0x00                     ; '\0'
+  0x08005192:  00           DC.B       0x00                     ; '\0'
+  0x08005193:  00           DC.B       0x00                     ; '\0'
+  0x08005194:  07           DC.B       0x07                     ; '\x07'
+  0x08005195:  00           DC.B       0x00                     ; '\0'
+  0x08005196:  00           DC.B       0x00                     ; '\0'
+  0x08005197:  00           DC.B       0x00                     ; '\0'
+  0x08005198:  08           DC.B       0x08                     ; '\b'
+  0x08005199:  00           DC.B       0x00                     ; '\0'
+  0x0800519A:  00           DC.B       0x00                     ; '\0'
+  0x0800519B:  00           DC.B       0x00                     ; '\0'
+  0x0800519C:  09           DC.B       0x09                     ; '\t'
+  0x0800519D:  00           DC.B       0x00                     ; '\0'
+  0x0800519E:  00           DC.B       0x00                     ; '\0'
+  0x0800519F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.APBPrescTable from PowerPro_lto.o, size=32, align=4

+
+
APBPrescTable:
+  0x080051A0:  00           DC.B       0x00                     ; '\0'
+  0x080051A1:  00           DC.B       0x00                     ; '\0'
+  0x080051A2:  00           DC.B       0x00                     ; '\0'
+  0x080051A3:  00           DC.B       0x00                     ; '\0'
+  0x080051A4:  00           DC.B       0x00                     ; '\0'
+  0x080051A5:  00           DC.B       0x00                     ; '\0'
+  0x080051A6:  00           DC.B       0x00                     ; '\0'
+  0x080051A7:  00           DC.B       0x00                     ; '\0'
+  0x080051A8:  00           DC.B       0x00                     ; '\0'
+  0x080051A9:  00           DC.B       0x00                     ; '\0'
+  0x080051AA:  00           DC.B       0x00                     ; '\0'
+  0x080051AB:  00           DC.B       0x00                     ; '\0'
+  0x080051AC:  00           DC.B       0x00                     ; '\0'
+  0x080051AD:  00           DC.B       0x00                     ; '\0'
+  0x080051AE:  00           DC.B       0x00                     ; '\0'
+  0x080051AF:  00           DC.B       0x00                     ; '\0'
+  0x080051B0:  01           DC.B       0x01                     ; '\x01'
+  0x080051B1:  00           DC.B       0x00                     ; '\0'
+  0x080051B2:  00           DC.B       0x00                     ; '\0'
+  0x080051B3:  00           DC.B       0x00                     ; '\0'
+  0x080051B4:  02           DC.B       0x02                     ; '\x02'
+  0x080051B5:  00           DC.B       0x00                     ; '\0'
+  0x080051B6:  00           DC.B       0x00                     ; '\0'
+  0x080051B7:  00           DC.B       0x00                     ; '\0'
+  0x080051B8:  03           DC.B       0x03                     ; '\x03'
+  0x080051B9:  00           DC.B       0x00                     ; '\0'
+  0x080051BA:  00           DC.B       0x00                     ; '\0'
+  0x080051BB:  00           DC.B       0x00                     ; '\0'
+  0x080051BC:  04           DC.B       0x04                     ; '\x04'
+  0x080051BD:  00           DC.B       0x00                     ; '\0'
+  0x080051BE:  00           DC.B       0x00                     ; '\0'
+  0x080051BF:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lswitch.table.UART_SetConfig from PowerPro_lto.o, size=16, align=4

+
+  0x080051C0:  00           DC.B       0x00                     ; '\0'
+  0x080051C1:  00           DC.B       0x00                     ; '\0'
+  0x080051C2:  00           DC.B       0x00                     ; '\0'
+  0x080051C3:  00           DC.B       0x00                     ; '\0'
+  0x080051C4:  04           DC.B       0x04                     ; '\x04'
+  0x080051C5:  00           DC.B       0x00                     ; '\0'
+  0x080051C6:  00           DC.B       0x00                     ; '\0'
+  0x080051C7:  00           DC.B       0x00                     ; '\0'
+  0x080051C8:  02           DC.B       0x02                     ; '\x02'
+  0x080051C9:  00           DC.B       0x00                     ; '\0'
+  0x080051CA:  00           DC.B       0x00                     ; '\0'
+  0x080051CB:  00           DC.B       0x00                     ; '\0'
+  0x080051CC:  08           DC.B       0x08                     ; '\b'
+  0x080051CD:  00           DC.B       0x00                     ; '\0'
+  0x080051CE:  00           DC.B       0x00                     ; '\0'
+  0x080051CF:  00           DC.B       0x00                     ; '\0'
+
+

Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

+
+
_start:
+  0x080051D0:  4C03         LDR        R4, =0x08006A70          ; [PC, #12] [0x080051E0] 
+
.L1:
+  0x080051D2:  6820         LDR        R0, [R4]
+  0x080051D4:  3404         ADDS       R4, #4
+  0x080051D6:  4780         BLX        R0
+  0x080051D8:  E7FB         B          .L1                      ; 0x080051D2
+
__SEGGER_init_done:
+__startup_complete:
+  0x080051DA:  F7FC FB33    BL         main                     ; 0x08001844
+
exit:
+  0x080051DE:  E7FE         B          exit                     ; 0x080051DE
+  0x080051E0:  08006A70     DC.W       08006A70               ; R_ARM_ABS32
+
+

Section .text.libc.putchar from fileops.o (libc_v6m_t_le_eabi_small.a), size=16, align=4

+
+
putchar:
+  0x080051E4:  B580         PUSH       {R7, LR}
+  0x080051E6:  4902         LDR        R1, =stdout              ; [PC, #8] [0x080051F0] =0x20000B98 
+  0x080051E8:  6809         LDR        R1, [R1]
+  0x080051EA:  F000 FB69    BL         fputc                    ; 0x080058C0
+  0x080051EE:  BD80         POP        {R7, PC}
+  0x080051F0:  20000B98     DC.W       stdout
+
+

Section .text.libc.puts from fileops.o (libc_v6m_t_le_eabi_small.a), size=44, align=4

+
+
puts:
+  0x080051F4:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x080051F6:  4604         MOV        R4, R0
+  0x080051F8:  4808         LDR        R0, =stdout              ; [PC, #32] [0x0800521C] =0x20000B98 
+  0x080051FA:  6805         LDR        R5, [R0]
+  0x080051FC:  4620         MOV        R0, R4
+  0x080051FE:  F000 FD95    BL         strlen                   ; 0x08005D2C
+  0x08005202:  4602         MOV        R2, R0
+  0x08005204:  4628         MOV        R0, R5
+  0x08005206:  4621         MOV        R1, R4
+  0x08005208:  F000 FD4C    BL         __SEGGER_RTL_X_file_write ; 0x08005CA4
+  0x0800520C:  1C40         ADDS       R0, R0, #1
+  0x0800520E:  D003         BEQ        .L1                      ; 0x08005218
+  0x08005210:  200A         MOVS       R0, #10
+  0x08005212:  F7FF FFE7    BL         putchar                  ; 0x080051E4
+  0x08005216:  BDB0         POP        {R4-R5, R7, PC}
+
.L1:
+  0x08005218:  43C0         MVNS       R0, R0
+  0x0800521A:  BDB0         POP        {R4-R5, R7, PC}
+  0x0800521C:  20000B98     DC.W       stdout
+
+

Section .text.libc.__aeabi_i2d from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__aeabi_i2d:
+  0x08005220:  4B05         LDR        R3, =__aeabi_ui2d        ; [PC, #20] [0x08005238] =0x0800602B 
+  0x08005222:  4200         TST        R0, R0
+  0x08005224:  D506         BPL        .L1                      ; 0x08005234
+  0x08005226:  4240         RSBS       R0, R0, #0
+  0x08005228:  B500         PUSH       {LR}
+  0x0800522A:  4798         BLX        R3
+  0x0800522C:  BC08         POP        {R3}
+  0x0800522E:  2201         MOVS       R2, #1
+  0x08005230:  07D2         LSLS       R2, R2, #31
+  0x08005232:  4311         ORRS       R1, R2
+
.L1:
+  0x08005234:  4718         BX         R3
+  0x08005236:  0000         NOP
+  0x08005238:  0800602B     DC.W       __aeabi_ui2d
+
+

Section .text.libc.vfprintf_l from prinops.o (libc_v6m_t_le_eabi_small.a), size=108, align=4

+
+
vfprintf_l:
+  0x0800523C:  B5F0         PUSH       {R4-R7, LR}
+  0x0800523E:  AF03         ADD        R7, SP, #12
+  0x08005240:  B091         SUB        SP, SP, #68
+  0x08005242:  466E         MOV        R6, SP
+  0x08005244:  1DF5         ADDS       R5, R6, #7
+  0x08005246:  3519         ADDS       R5, #25
+  0x08005248:  61B3         STR        R3, [R6, #24]
+  0x0800524A:  6172         STR        R2, [R6, #20]
+  0x0800524C:  6071         STR        R1, [R6, #4]
+  0x0800524E:  60F0         STR        R0, [R6, #12]
+  0x08005250:  F000 FF81    BL         __SEGGER_RTL_X_file_bufsize ; 0x08006156
+  0x08005254:  60B0         STR        R0, [R6, #8]
+  0x08005256:  1DC2         ADDS       R2, R0, #7
+  0x08005258:  2107         MOVS       R1, #7
+  0x0800525A:  438A         BICS       R2, R1
+  0x0800525C:  4669         MOV        R1, SP
+  0x0800525E:  6131         STR        R1, [R6, #16]
+  0x08005260:  4669         MOV        R1, SP
+  0x08005262:  1A88         SUBS       R0, R1, R2
+  0x08005264:  6030         STR        R0, [R6]
+  0x08005266:  4685         MOV        SP, R0
+  0x08005268:  1DF4         ADDS       R4, R6, #7
+  0x0800526A:  3415         ADDS       R4, #21
+  0x0800526C:  4620         MOV        R0, R4
+  0x0800526E:  6871         LDR        R1, [R6, #4]
+  0x08005270:  F000 FD02    BL         __SEGGER_RTL_init_prin_l ; 0x08005C78
+  0x08005274:  480A         LDR        R0, =__SEGGER_RTL_stream_write ; [PC, #40] [0x080052A0] =0x08006147 
+  0x08005276:  63F0         STR        R0, [R6, #60]
+  0x08005278:  480A         LDR        R0, =0x7FFFFFFF          ; [PC, #40] [0x080052A4] 
+  0x0800527A:  6028         STR        R0, [R5]
+  0x0800527C:  68F0         LDR        R0, [R6, #12]
+  0x0800527E:  6228         STR        R0, [R5, #32]
+  0x08005280:  68B0         LDR        R0, [R6, #8]
+  0x08005282:  6168         STR        R0, [R5, #20]
+  0x08005284:  6830         LDR        R0, [R6]
+  0x08005286:  60E8         STR        R0, [R5, #12]
+  0x08005288:  4620         MOV        R0, R4
+  0x0800528A:  6971         LDR        R1, [R6, #20]
+  0x0800528C:  69B2         LDR        R2, [R6, #24]
+  0x0800528E:  F000 F81F    BL         __SEGGER_RTL_vfprintf_int_nwp ; 0x080052D0
+  0x08005292:  6931         LDR        R1, [R6, #16]
+  0x08005294:  468D         MOV        SP, R1
+  0x08005296:  1FFE         SUBS       R6, R7, #7
+  0x08005298:  3E05         SUBS       R6, #5
+  0x0800529A:  46B5         MOV        SP, R6
+  0x0800529C:  BDF0         POP        {R4-R7, PC}
+  0x0800529E:  46C0         NOP
+  0x080052A0:  08006147     DC.W       __SEGGER_RTL_stream_write
+  0x080052A4:  7FFFFFFF     DC.W       0x7FFFFFFF
+
+

Section .text.libc.printf from prinops.o (libc_v6m_t_le_eabi_small.a), size=40, align=4

+
+
printf:
+  0x080052A8:  B083         SUB        SP, SP, #12
+  0x080052AA:  B510         PUSH       {R4, LR}
+  0x080052AC:  B081         SUB        SP, SP, #4
+  0x080052AE:  4604         MOV        R4, R0
+  0x080052B0:  A803         ADD        R0, SP, #12
+  0x080052B2:  C00E         STM        R0!, {R1-R3}
+  0x080052B4:  4805         LDR        R0, =stdout              ; [PC, #20] [0x080052CC] =0x20000B98 
+  0x080052B6:  6800         LDR        R0, [R0]
+  0x080052B8:  AA03         ADD        R2, SP, #12
+  0x080052BA:  9200         STR        R2, [SP, #0]
+  0x080052BC:  4621         MOV        R1, R4
+  0x080052BE:  F000 FCE4    BL         vfprintf                 ; 0x08005C8A
+  0x080052C2:  B001         ADD        SP, SP, #4
+  0x080052C4:  BC10         POP        {R4}
+  0x080052C6:  BC02         POP        {R1}
+  0x080052C8:  B003         ADD        SP, SP, #12
+  0x080052CA:  4708         BX         R1
+  0x080052CC:  20000B98     DC.W       stdout
+
+

Section .text.libc.__SEGGER_RTL_vfprintf_int_nwp from __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_small.a), size=840, align=4

+
+
__SEGGER_RTL_vfprintf_int_nwp:
+__SEGGER_RTL_vfprintf:
+  0x080052D0:  B5F0         PUSH       {R4-R7, LR}
+  0x080052D2:  B093         SUB        SP, SP, #76
+  0x080052D4:  9208         STR        R2, [SP, #32]
+  0x080052D6:  9109         STR        R1, [SP, #36]
+  0x080052D8:  4605         MOV        R5, R0
+  0x080052DA:  2000         MOVS       R0, #0
+  0x080052DC:  9006         STR        R0, [SP, #24]
+  0x080052DE:  6028         STR        R0, [R5]
+  0x080052E0:  2001         MOVS       R0, #1
+  0x080052E2:  0341         LSLS       R1, R0, #13
+  0x080052E4:  9102         STR        R1, [SP, #8]
+  0x080052E6:  0381         LSLS       R1, R0, #14
+  0x080052E8:  9105         STR        R1, [SP, #20]
+  0x080052EA:  9001         STR        R0, [SP, #4]
+  0x080052EC:  03C0         LSLS       R0, R0, #15
+  0x080052EE:  9003         STR        R0, [SP, #12]
+  0x080052F0:  9504         STR        R5, [SP, #16]
+
.L1:
+  0x080052F2:  9809         LDR        R0, [SP, #36]
+  0x080052F4:  1C44         ADDS       R4, R0, #1
+  0x080052F6:  7801         LDRB       R1, [R0]
+  0x080052F8:  2925         CMP        R1, #37
+  0x080052FA:  D007         BEQ        .L3                      ; 0x0800530C
+  0x080052FC:  2900         CMP        R1, #0
+  0x080052FE:  D100         BNE        .L2                      ; 0x08005302
+  0x08005300:  E16E         B          .L63                     ; 0x080055E0
+
.L2:
+  0x08005302:  4628         MOV        R0, R5
+  0x08005304:  F000 FC66    BL         __SEGGER_RTL_putc        ; 0x08005BD4
+  0x08005308:  9409         STR        R4, [SP, #36]
+  0x0800530A:  E7F2         B          .L1                      ; 0x080052F2
+
.L3:
+  0x0800530C:  9F06         LDR        R7, [SP, #24]
+
.L4:
+  0x0800530E:  1C61         ADDS       R1, R4, #1
+  0x08005310:  7820         LDRB       R0, [R4]
+  0x08005312:  285E         CMP        R0, #94
+  0x08005314:  460C         MOV        R4, R1
+  0x08005316:  D0FA         BEQ        .L4                      ; 0x0800530E
+  0x08005318:  287A         CMP        R0, #122
+  0x0800531A:  D01A         BEQ        .L10                     ; 0x08005352
+  0x0800531C:  2823         CMP        R0, #35
+  0x0800531E:  D013         BEQ        .L7                      ; 0x08005348
+  0x08005320:  2827         CMP        R0, #39
+  0x08005322:  D00D         BEQ        .L5                      ; 0x08005340
+  0x08005324:  282B         CMP        R0, #43
+  0x08005326:  D00D         BEQ        .L6                      ; 0x08005344
+  0x08005328:  2868         CMP        R0, #104
+  0x0800532A:  D015         BEQ        .L12                     ; 0x08005358
+  0x0800532C:  286A         CMP        R0, #106
+  0x0800532E:  D00E         BEQ        .L9                      ; 0x0800534E
+  0x08005330:  286C         CMP        R0, #108
+  0x08005332:  D016         BEQ        .L13                     ; 0x08005362
+  0x08005334:  2874         CMP        R0, #116
+  0x08005336:  D00C         BEQ        .L10                     ; 0x08005352
+  0x08005338:  2820         CMP        R0, #32
+  0x0800533A:  D119         BNE        .L15                     ; 0x08005370
+  0x0800533C:  2040         MOVS       R0, #64
+  0x0800533E:  E004         B          .L8                      ; 0x0800534A
+
.L5:
+  0x08005340:  9803         LDR        R0, [SP, #12]
+  0x08005342:  E002         B          .L8                      ; 0x0800534A
+
.L6:
+  0x08005344:  2020         MOVS       R0, #32
+  0x08005346:  E000         B          .L8                      ; 0x0800534A
+
.L7:
+  0x08005348:  2080         MOVS       R0, #128
+
.L8:
+  0x0800534A:  4307         ORRS       R7, R0
+  0x0800534C:  E7DF         B          .L4                      ; 0x0800530E
+
.L9:
+  0x0800534E:  2002         MOVS       R0, #2
+  0x08005350:  4307         ORRS       R7, R0
+
.L10:
+  0x08005352:  7808         LDRB       R0, [R1]
+
.L11:
+  0x08005354:  1C49         ADDS       R1, R1, #1
+  0x08005356:  E00B         B          .L15                     ; 0x08005370
+
.L12:
+  0x08005358:  7808         LDRB       R0, [R1]
+  0x0800535A:  2868         CMP        R0, #104
+  0x0800535C:  D15A         BNE        .L23                     ; 0x08005414
+  0x0800535E:  2008         MOVS       R0, #8
+  0x08005360:  E003         B          .L14                     ; 0x0800536A
+
.L13:
+  0x08005362:  7808         LDRB       R0, [R1]
+  0x08005364:  286C         CMP        R0, #108
+  0x08005366:  D1F5         BNE        .L11                     ; 0x08005354
+  0x08005368:  2002         MOVS       R0, #2
+
.L14:
+  0x0800536A:  4307         ORRS       R7, R0
+  0x0800536C:  7848         LDRB       R0, [R1, #1]
+  0x0800536E:  1C89         ADDS       R1, R1, #2
+
.L15:
+  0x08005370:  9109         STR        R1, [SP, #36]
+
.L16:
+  0x08005372:  4601         MOV        R1, R0
+  0x08005374:  3963         SUBS       R1, #99
+  0x08005376:  2300         MOVS       R3, #0
+  0x08005378:  2915         CMP        R1, #21
+  0x0800537A:  D812         BHI        .L17                     ; 0x080053A2
+  0x0800537C:  4479         ADD        R1, PC
+  0x0800537E:  7909         LDRB       R1, [R1, #4]
+  0x08005380:  0049         LSLS       R1, R1, #1
+  0x08005382:  448F         ADD        PC, R1
+  0x08005384:  16           DC.B       0x16                     ; '\x16'
+  0x08005385:  0B           DC.B       0x0B                     ; '\v'
+  0x08005386:  0A           DC.B       0x0A                     ; '\n'
+  0x08005387:  0A           DC.B       0x0A                     ; '\n'
+  0x08005388:  0A           DC.B       0x0A                     ; '\n'
+  0x08005389:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538A:  0B           DC.B       0x0B                     ; '\v'
+  0x0800538B:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538C:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538D:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538E:  0A           DC.B       0x0A                     ; '\n'
+  0x0800538F:  28           DC.B       0x28                     ; '('
+  0x08005390:  35           DC.B       0x35                     ; '5'
+  0x08005391:  1E           DC.B       0x1E                     ; '\x1E'
+  0x08005392:  0A           DC.B       0x0A                     ; '\n'
+  0x08005393:  0A           DC.B       0x0A                     ; '\n'
+  0x08005394:  3A           DC.B       0x3A                     ; ':'
+  0x08005395:  0A           DC.B       0x0A                     ; '\n'
+  0x08005396:  59           DC.B       0x59                     ; 'Y'
+  0x08005397:  0A           DC.B       0x0A                     ; '\n'
+  0x08005398:  0A           DC.B       0x0A                     ; '\n'
+  0x08005399:  53           DC.B       0x53                     ; 'S'
+  0x0800539A:  E7AA         B          .L1                      ; 0x080052F2
+  0x0800539C:  9905         LDR        R1, [SP, #20]
+  0x0800539E:  430F         ORRS       R7, R1
+  0x080053A0:  E04A         B          .L26                     ; 0x08005438
+
.L17:
+  0x080053A2:  2825         CMP        R0, #37
+  0x080053A4:  D03B         BEQ        .L24                     ; 0x0800541E
+  0x080053A6:  2858         CMP        R0, #88
+  0x080053A8:  D03E         BEQ        .L25                     ; 0x08005428
+  0x080053AA:  2800         CMP        R0, #0
+  0x080053AC:  D000         BEQ        .L18                     ; 0x080053B0
+  0x080053AE:  E7A0         B          .L1                      ; 0x080052F2
+
.L18:
+  0x080053B0:  E125         B          .L66                     ; 0x080055FE
+  0x080053B2:  9C08         LDR        R4, [SP, #32]
+  0x080053B4:  7821         LDRB       R1, [R4]
+  0x080053B6:  4628         MOV        R0, R5
+  0x080053B8:  F000 FC0C    BL         __SEGGER_RTL_putc        ; 0x08005BD4
+  0x080053BC:  1D24         ADDS       R4, R4, #4
+  0x080053BE:  9408         STR        R4, [SP, #32]
+  0x080053C0:  E797         B          .L1                      ; 0x080052F2
+  0x080053C2:  0638         LSLS       R0, R7, #24
+  0x080053C4:  17C0         ASRS       R0, R0, #31
+  0x080053C6:  2123         MOVS       R1, #35
+  0x080053C8:  4001         ANDS       R1, R0
+  0x080053CA:  9107         STR        R1, [SP, #28]
+  0x080053CC:  9808         LDR        R0, [SP, #32]
+  0x080053CE:  C820         LDM        R0!, {R5}
+  0x080053D0:  9008         STR        R0, [SP, #32]
+  0x080053D2:  2400         MOVS       R4, #0
+  0x080053D4:  E0A1         B          .L46                     ; 0x0800551A
+  0x080053D6:  9B08         LDR        R3, [SP, #32]
+  0x080053D8:  6818         LDR        R0, [R3]
+  0x080053DA:  0739         LSLS       R1, R7, #28
+  0x080053DC:  6829         LDR        R1, [R5]
+  0x080053DE:  D500         BPL        .L19                     ; 0x080053E2
+  0x080053E0:  E0F0         B          .L58                     ; 0x080055C4
+
.L19:
+  0x080053E2:  07BA         LSLS       R2, R7, #30
+  0x080053E4:  6001         STR        R1, [R0]
+  0x080053E6:  D400         BMI        .L20                     ; 0x080053EA
+  0x080053E8:  E0ED         B          .L59                     ; 0x080055C6
+
.L20:
+  0x080053EA:  2100         MOVS       R1, #0
+  0x080053EC:  6041         STR        R1, [R0, #4]
+  0x080053EE:  E0EA         B          .L59                     ; 0x080055C6
+  0x080053F0:  0639         LSLS       R1, R7, #24
+  0x080053F2:  17C9         ASRS       R1, R1, #31
+  0x080053F4:  2330         MOVS       R3, #48
+  0x080053F6:  400B         ANDS       R3, R1
+  0x080053F8:  E01E         B          .L26                     ; 0x08005438
+  0x080053FA:  9E08         LDR        R6, [SP, #32]
+  0x080053FC:  6834         LDR        R4, [R6]
+
.L21:
+  0x080053FE:  7821         LDRB       R1, [R4]
+  0x08005400:  2900         CMP        R1, #0
+  0x08005402:  D004         BEQ        .L22                     ; 0x0800540E
+  0x08005404:  4628         MOV        R0, R5
+  0x08005406:  F000 FBE5    BL         __SEGGER_RTL_putc        ; 0x08005BD4
+  0x0800540A:  1C64         ADDS       R4, R4, #1
+  0x0800540C:  E7F7         B          .L21                     ; 0x080053FE
+
.L22:
+  0x0800540E:  1D36         ADDS       R6, R6, #4
+  0x08005410:  9608         STR        R6, [SP, #32]
+  0x08005412:  E76E         B          .L1                      ; 0x080052F2
+
.L23:
+  0x08005414:  1C49         ADDS       R1, R1, #1
+  0x08005416:  9109         STR        R1, [SP, #36]
+  0x08005418:  2104         MOVS       R1, #4
+  0x0800541A:  430F         ORRS       R7, R1
+  0x0800541C:  E7A9         B          .L16                     ; 0x08005372
+
.L24:
+  0x0800541E:  2125         MOVS       R1, #37
+  0x08005420:  4628         MOV        R0, R5
+  0x08005422:  F000 FBD7    BL         __SEGGER_RTL_putc        ; 0x08005BD4
+  0x08005426:  E764         B          .L1                      ; 0x080052F2
+
.L25:
+  0x08005428:  9902         LDR        R1, [SP, #8]
+  0x0800542A:  430F         ORRS       R7, R1
+  0x0800542C:  0639         LSLS       R1, R7, #24
+  0x0800542E:  D503         BPL        .L26                     ; 0x08005438
+  0x08005430:  4B76         LDR        R3, =0x00003058          ; [PC, #0x01D8] [0x0800560C] 
+  0x08005432:  2878         CMP        R0, #120
+  0x08005434:  D100         BNE        .L26                     ; 0x08005438
+  0x08005436:  3320         ADDS       R3, #32
+
.L26:
+  0x08005438:  9307         STR        R3, [SP, #28]
+  0x0800543A:  2102         MOVS       R1, #2
+  0x0800543C:  4039         ANDS       R1, R7
+  0x0800543E:  9A05         LDR        R2, [SP, #20]
+  0x08005440:  4217         TST        R7, R2
+  0x08005442:  D105         BNE        .L27                     ; 0x08005450
+  0x08005444:  2900         CMP        R1, #0
+  0x08005446:  9A08         LDR        R2, [SP, #32]
+  0x08005448:  D108         BNE        .L28                     ; 0x0800545C
+  0x0800544A:  1D11         ADDS       R1, R2, #4
+  0x0800544C:  2400         MOVS       R4, #0
+  0x0800544E:  E00B         B          .L29                     ; 0x08005468
+
.L27:
+  0x08005450:  2900         CMP        R1, #0
+  0x08005452:  9B08         LDR        R3, [SP, #32]
+  0x08005454:  D10F         BNE        .L30                     ; 0x08005476
+  0x08005456:  CB02         LDM        R3!, {R1}
+  0x08005458:  17CC         ASRS       R4, R1, #31
+  0x0800545A:  E011         B          .L31                     ; 0x08005480
+
.L28:
+  0x0800545C:  1DD2         ADDS       R2, R2, #7
+  0x0800545E:  2107         MOVS       R1, #7
+  0x08005460:  438A         BICS       R2, R1
+  0x08005462:  6854         LDR        R4, [R2, #4]
+  0x08005464:  4611         MOV        R1, R2
+  0x08005466:  3108         ADDS       R1, #8
+
.L29:
+  0x08005468:  6815         LDR        R5, [R2]
+  0x0800546A:  077A         LSLS       R2, R7, #29
+  0x0800546C:  D40E         BMI        .L32                     ; 0x0800548C
+  0x0800546E:  073A         LSLS       R2, R7, #28
+  0x08005470:  D50E         BPL        .L34                     ; 0x08005490
+  0x08005472:  B2ED         UXTB       R5, R5
+  0x08005474:  E00B         B          .L33                     ; 0x0800548E
+
.L30:
+  0x08005476:  1DDB         ADDS       R3, R3, #7
+  0x08005478:  2107         MOVS       R1, #7
+  0x0800547A:  438B         BICS       R3, R1
+  0x0800547C:  CB12         LDM        R3!, {R1, R4}
+  0x0800547E:  3300         ADDS       R3, #0
+
.L31:
+  0x08005480:  077A         LSLS       R2, R7, #29
+  0x08005482:  D407         BMI        .L35                     ; 0x08005494
+  0x08005484:  073A         LSLS       R2, R7, #28
+  0x08005486:  D408         BMI        .L36                     ; 0x0800549A
+  0x08005488:  460D         MOV        R5, R1
+  0x0800548A:  E009         B          .L38                     ; 0x080054A0
+
.L32:
+  0x0800548C:  B2AD         UXTH       R5, R5
+
.L33:
+  0x0800548E:  2400         MOVS       R4, #0
+
.L34:
+  0x08005490:  9108         STR        R1, [SP, #32]
+  0x08005492:  E017         B          .L42                     ; 0x080054C4
+
.L35:
+  0x08005494:  B20D         SXTH       R5, R1
+  0x08005496:  0409         LSLS       R1, R1, #16
+  0x08005498:  E001         B          .L37                     ; 0x0800549E
+
.L36:
+  0x0800549A:  B24D         SXTB       R5, R1
+  0x0800549C:  0609         LSLS       R1, R1, #24
+
.L37:
+  0x0800549E:  17CC         ASRS       R4, R1, #31
+
.L38:
+  0x080054A0:  2C00         CMP        R4, #0
+  0x080054A2:  9308         STR        R3, [SP, #32]
+  0x080054A4:  D405         BMI        .L39                     ; 0x080054B2
+  0x080054A6:  06B9         LSLS       R1, R7, #26
+  0x080054A8:  D40A         BMI        .L40                     ; 0x080054C0
+  0x080054AA:  0679         LSLS       R1, R7, #25
+  0x080054AC:  D50A         BPL        .L42                     ; 0x080054C4
+  0x080054AE:  2120         MOVS       R1, #32
+  0x080054B0:  E007         B          .L41                     ; 0x080054C2
+
.L39:
+  0x080054B2:  2100         MOVS       R1, #0
+  0x080054B4:  426D         RSBS       R5, R5, #0
+  0x080054B6:  41A1         SBCS       R1, R4
+  0x080054B8:  222D         MOVS       R2, #45
+  0x080054BA:  9207         STR        R2, [SP, #28]
+  0x080054BC:  460C         MOV        R4, R1
+  0x080054BE:  E001         B          .L42                     ; 0x080054C4
+
.L40:
+  0x080054C0:  212B         MOVS       R1, #43
+
.L41:
+  0x080054C2:  9107         STR        R1, [SP, #28]
+
.L42:
+  0x080054C4:  4601         MOV        R1, R0
+  0x080054C6:  396F         SUBS       R1, #111
+  0x080054C8:  2600         MOVS       R6, #0
+  0x080054CA:  2909         CMP        R1, #9
+  0x080054CC:  D81F         BHI        .L45                     ; 0x0800550E
+  0x080054CE:  46C0         NOP
+  0x080054D0:  4479         ADD        R1, PC
+  0x080054D2:  7909         LDRB       R1, [R1, #4]
+  0x080054D4:  0049         LSLS       R1, R1, #1
+  0x080054D6:  448F         ADD        PC, R1
+  0x080054D8:  04           DC.B       0x04                     ; '\x04'
+  0x080054D9:  20           DC.B       0x20                     ; ' '
+  0x080054DA:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DB:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DC:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DD:  6A           DC.B       0x6A                     ; 'j'
+  0x080054DE:  25           DC.B       0x25                     ; '%'
+  0x080054DF:  6A           DC.B       0x6A                     ; 'j'
+  0x080054E0:  6A           DC.B       0x6A                     ; 'j'
+  0x080054E1:  20           DC.B       0x20                     ; ' '
+  0x080054E2:  4628         MOV        R0, R5
+  0x080054E4:  4320         ORRS       R0, R4
+  0x080054E6:  D10E         BNE        .L44                     ; 0x08005506
+  0x080054E8:  A80D         ADD        R0, SP, #52
+  0x080054EA:  2130         MOVS       R1, #48
+  0x080054EC:  7001         STRB       R1, [R0]
+  0x080054EE:  2601         MOVS       R6, #1
+  0x080054F0:  E009         B          .L44                     ; 0x08005506
+
.L43:
+  0x080054F2:  2007         MOVS       R0, #7
+  0x080054F4:  4028         ANDS       R0, R5
+  0x080054F6:  3030         ADDS       R0, #48
+  0x080054F8:  A90D         ADD        R1, SP, #52
+  0x080054FA:  5588         STRB       R0, [R1, R6]
+  0x080054FC:  08E8         LSRS       R0, R5, #3
+  0x080054FE:  0761         LSLS       R1, R4, #29
+  0x08005500:  1845         ADDS       R5, R0, R1
+  0x08005502:  08E4         LSRS       R4, R4, #3
+  0x08005504:  1C76         ADDS       R6, R6, #1
+
.L44:
+  0x08005506:  4628         MOV        R0, R5
+  0x08005508:  4320         ORRS       R0, R4
+  0x0800550A:  D050         BEQ        .L56                     ; 0x080055AE
+  0x0800550C:  E7F1         B          .L43                     ; 0x080054F2
+
.L45:
+  0x0800550E:  2869         CMP        R0, #105
+  0x08005510:  D008         BEQ        .L47                     ; 0x08005524
+  0x08005512:  2864         CMP        R0, #100
+  0x08005514:  D006         BEQ        .L47                     ; 0x08005524
+  0x08005516:  2858         CMP        R0, #88
+  0x08005518:  D149         BNE        .L56                     ; 0x080055AE
+
.L46:
+  0x0800551A:  4628         MOV        R0, R5
+  0x0800551C:  4320         ORRS       R0, R4
+  0x0800551E:  D02E         BEQ        .L51                     ; 0x0800557E
+  0x08005520:  2600         MOVS       R6, #0
+  0x08005522:  E030         B          .L52                     ; 0x08005586
+
.L47:
+  0x08005524:  4628         MOV        R0, R5
+  0x08005526:  4320         ORRS       R0, R4
+  0x08005528:  D103         BNE        .L48                     ; 0x08005532
+  0x0800552A:  A80D         ADD        R0, SP, #52
+  0x0800552C:  2130         MOVS       R1, #48
+  0x0800552E:  7001         STRB       R1, [R0]
+  0x08005530:  2601         MOVS       R6, #1
+
.L48:
+  0x08005532:  9803         LDR        R0, [SP, #12]
+  0x08005534:  4007         ANDS       R7, R0
+  0x08005536:  970A         STR        R7, [SP, #40]
+
.L49:
+  0x08005538:  4628         MOV        R0, R5
+  0x0800553A:  4320         ORRS       R0, R4
+  0x0800553C:  D037         BEQ        .L56                     ; 0x080055AE
+  0x0800553E:  2F00         CMP        R7, #0
+  0x08005540:  D007         BEQ        .L50                     ; 0x08005552
+  0x08005542:  2003         MOVS       R0, #3
+  0x08005544:  4030         ANDS       R0, R6
+  0x08005546:  2803         CMP        R0, #3
+  0x08005548:  D103         BNE        .L50                     ; 0x08005552
+  0x0800554A:  A80D         ADD        R0, SP, #52
+  0x0800554C:  212C         MOVS       R1, #44
+  0x0800554E:  5581         STRB       R1, [R0, R6]
+  0x08005550:  1C76         ADDS       R6, R6, #1
+
.L50:
+  0x08005552:  220A         MOVS       R2, #10
+  0x08005554:  920B         STR        R2, [SP, #44]
+  0x08005556:  2300         MOVS       R3, #0
+  0x08005558:  4628         MOV        R0, R5
+  0x0800555A:  4621         MOV        R1, R4
+  0x0800555C:  F000 FDAF    BL         __aeabi_uldivmod         ; 0x080060BE
+  0x08005560:  900C         STR        R0, [SP, #48]
+  0x08005562:  460C         MOV        R4, R1
+  0x08005564:  9A0B         LDR        R2, [SP, #44]
+  0x08005566:  2300         MOVS       R3, #0
+  0x08005568:  F000 FB1A    BL         __aeabi_lmul             ; 0x08005BA0
+  0x0800556C:  1A28         SUBS       R0, R5, R0
+  0x0800556E:  2130         MOVS       R1, #48
+  0x08005570:  4301         ORRS       R1, R0
+  0x08005572:  A80D         ADD        R0, SP, #52
+  0x08005574:  5581         STRB       R1, [R0, R6]
+  0x08005576:  1C76         ADDS       R6, R6, #1
+  0x08005578:  9D0C         LDR        R5, [SP, #48]
+  0x0800557A:  9F0A         LDR        R7, [SP, #40]
+  0x0800557C:  E7DC         B          .L49                     ; 0x08005538
+
.L51:
+  0x0800557E:  A80D         ADD        R0, SP, #52
+  0x08005580:  2130         MOVS       R1, #48
+  0x08005582:  7001         STRB       R1, [R0]
+  0x08005584:  9E01         LDR        R6, [SP, #4]
+
.L52:
+  0x08005586:  9802         LDR        R0, [SP, #8]
+  0x08005588:  4207         TST        R7, R0
+  0x0800558A:  D001         BEQ        .L53                     ; 0x08005590
+  0x0800558C:  4821         LDR        R0, =__SEGGER_RTL_hex_uc ; [PC, #132] [0x08005614] =0x080069AC 
+  0x0800558E:  E00B         B          .L55                     ; 0x080055A8
+
.L53:
+  0x08005590:  481F         LDR        R0, =__SEGGER_RTL_hex_lc ; [PC, #124] [0x08005610] =0x080069BC 
+  0x08005592:  E009         B          .L55                     ; 0x080055A8
+
.L54:
+  0x08005594:  210F         MOVS       R1, #15
+  0x08005596:  4029         ANDS       R1, R5
+  0x08005598:  5C41         LDRB       R1, [R0, R1]
+  0x0800559A:  AA0D         ADD        R2, SP, #52
+  0x0800559C:  5591         STRB       R1, [R2, R6]
+  0x0800559E:  0929         LSRS       R1, R5, #4
+  0x080055A0:  0722         LSLS       R2, R4, #28
+  0x080055A2:  188D         ADDS       R5, R1, R2
+  0x080055A4:  0924         LSRS       R4, R4, #4
+  0x080055A6:  1C76         ADDS       R6, R6, #1
+
.L55:
+  0x080055A8:  4629         MOV        R1, R5
+  0x080055AA:  4321         ORRS       R1, R4
+  0x080055AC:  D1F2         BNE        .L54                     ; 0x08005594
+
.L56:
+  0x080055AE:  9C07         LDR        R4, [SP, #28]
+  0x080055B0:  0A21         LSRS       R1, R4, #8
+  0x080055B2:  9D04         LDR        R5, [SP, #16]
+  0x080055B4:  D003         BEQ        .L57                     ; 0x080055BE
+  0x080055B6:  4628         MOV        R0, R5
+  0x080055B8:  F000 FB0C    BL         __SEGGER_RTL_putc        ; 0x08005BD4
+  0x080055BC:  E006         B          .L60                     ; 0x080055CC
+
.L57:
+  0x080055BE:  2C00         CMP        R4, #0
+  0x080055C0:  D008         BEQ        .L61                     ; 0x080055D4
+  0x080055C2:  E003         B          .L60                     ; 0x080055CC
+
.L58:
+  0x080055C4:  7001         STRB       R1, [R0]
+
.L59:
+  0x080055C6:  1D1B         ADDS       R3, R3, #4
+  0x080055C8:  9308         STR        R3, [SP, #32]
+  0x080055CA:  E692         B          .L1                      ; 0x080052F2
+
.L60:
+  0x080055CC:  4628         MOV        R0, R5
+  0x080055CE:  4621         MOV        R1, R4
+  0x080055D0:  F000 FB00    BL         __SEGGER_RTL_putc        ; 0x08005BD4
+
.L61:
+  0x080055D4:  1E76         SUBS       R6, R6, #1
+  0x080055D6:  DA00         BGE        .L62                     ; 0x080055DA
+  0x080055D8:  E68B         B          .L1                      ; 0x080052F2
+
.L62:
+  0x080055DA:  A80D         ADD        R0, SP, #52
+  0x080055DC:  5D84         LDRB       R4, [R0, R6]
+  0x080055DE:  E7F5         B          .L60                     ; 0x080055CC
+
.L63:
+  0x080055E0:  68E8         LDR        R0, [R5, #12]
+  0x080055E2:  2800         CMP        R0, #0
+  0x080055E4:  D005         BEQ        .L64                     ; 0x080055F2
+  0x080055E6:  CD06         LDM        R5!, {R1-R2}
+  0x080055E8:  3D08         SUBS       R5, #8
+  0x080055EA:  4291         CMP        R1, R2
+  0x080055EC:  D201         BCS        .L64                     ; 0x080055F2
+  0x080055EE:  9A06         LDR        R2, [SP, #24]
+  0x080055F0:  5442         STRB       R2, [R0, R1]
+
.L64:
+  0x080055F2:  4628         MOV        R0, R5
+  0x080055F4:  F000 FB33    BL         __SEGGER_RTL_prin_flush  ; 0x08005C5E
+  0x080055F8:  6828         LDR        R0, [R5]
+
.L65:
+  0x080055FA:  B013         ADD        SP, SP, #76
+  0x080055FC:  BDF0         POP        {R4-R7, PC}
+
.L66:
+  0x080055FE:  4628         MOV        R0, R5
+  0x08005600:  F000 FB2D    BL         __SEGGER_RTL_prin_flush  ; 0x08005C5E
+  0x08005604:  2000         MOVS       R0, #0
+  0x08005606:  43C0         MVNS       R0, R0
+  0x08005608:  E7F7         B          .L65                     ; 0x080055FA
+  0x0800560A:  46C0         NOP
+  0x0800560C:  00003058     DC.W       0x00003058
+  0x08005610:  080069BC     DC.W       __SEGGER_RTL_hex_lc
+  0x08005614:  080069AC     DC.W       __SEGGER_RTL_hex_uc
+
+

Section .text.libc.__SEGGER_RTL_X_file_stat from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=44, align=4

+
+
__SEGGER_RTL_X_file_stat:
+  0x08005618:  4601         MOV        R1, R0
+  0x0800561A:  4807         LDR        R0, =stdin               ; [PC, #28] [0x08005638] =0x20000B9C 
+  0x0800561C:  6802         LDR        R2, [R0]
+  0x0800561E:  2000         MOVS       R0, #0
+  0x08005620:  4291         CMP        R1, R2
+  0x08005622:  D008         BEQ        .L1                      ; 0x08005636
+  0x08005624:  4A05         LDR        R2, =stdout              ; [PC, #20] [0x0800563C] =0x20000B98 
+  0x08005626:  6812         LDR        R2, [R2]
+  0x08005628:  4291         CMP        R1, R2
+  0x0800562A:  D004         BEQ        .L1                      ; 0x08005636
+  0x0800562C:  4A04         LDR        R2, =stderr              ; [PC, #16] [0x08005640] =0x20000BA0 
+  0x0800562E:  6812         LDR        R2, [R2]
+  0x08005630:  4291         CMP        R1, R2
+  0x08005632:  D000         BEQ        .L1                      ; 0x08005636
+  0x08005634:  43C0         MVNS       R0, R0
+
.L1:
+  0x08005636:  4770         BX         LR
+  0x08005638:  20000B9C     DC.W       stdin
+  0x0800563C:  20000B98     DC.W       stdout
+  0x08005640:  20000BA0     DC.W       stderr
+
+

Section .text.libc._DoInit from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=84, align=4

+
+
_DoInit:
+  0x08005644:  480F         LDR        R0, =_SEGGER_RTT         ; [PC, #60] [0x08005684] =0x20000314 
+  0x08005646:  2103         MOVS       R1, #3
+  0x08005648:  6101         STR        R1, [R0, #16]
+  0x0800564A:  6141         STR        R1, [R0, #20]
+  0x0800564C:  4A0E         LDR        R2, =0x080067EC          ; [PC, #56] [0x08005688] 
+  0x0800564E:  6182         STR        R2, [R0, #24]
+  0x08005650:  490E         LDR        R1, =_acUpBuffer         ; [PC, #56] [0x0800568C] =0x20000769 
+  0x08005652:  61C1         STR        R1, [R0, #28]
+  0x08005654:  2101         MOVS       R1, #1
+  0x08005656:  0289         LSLS       R1, R1, #10
+  0x08005658:  6201         STR        R1, [R0, #32]
+  0x0800565A:  2100         MOVS       R1, #0
+  0x0800565C:  6281         STR        R1, [R0, #40]
+  0x0800565E:  6241         STR        R1, [R0, #36]
+  0x08005660:  62C1         STR        R1, [R0, #44]
+  0x08005662:  6602         STR        R2, [R0, #96]
+  0x08005664:  4A0A         LDR        R2, =_acDownBuffer       ; [PC, #40] [0x08005690] =0x20000B69 
+  0x08005666:  6642         STR        R2, [R0, #100]
+  0x08005668:  2210         MOVS       R2, #16
+  0x0800566A:  6682         STR        R2, [R0, #104]
+  0x0800566C:  6701         STR        R1, [R0, #112]
+  0x0800566E:  66C1         STR        R1, [R0, #108]
+  0x08005670:  6741         STR        R1, [R0, #116]
+  0x08005672:  4A08         LDR        R2, =0x080067EA          ; [PC, #32] [0x08005694] 
+
.L1:
+  0x08005674:  2910         CMP        R1, #16
+  0x08005676:  D004         BEQ        .L2                      ; 0x08005682
+  0x08005678:  7813         LDRB       R3, [R2]
+  0x0800567A:  5443         STRB       R3, [R0, R1]
+  0x0800567C:  1E52         SUBS       R2, R2, #1
+  0x0800567E:  1C49         ADDS       R1, R1, #1
+  0x08005680:  E7F8         B          .L1                      ; 0x08005674
+
.L2:
+  0x08005682:  4770         BX         LR
+  0x08005684:  20000314     DC.W       _SEGGER_RTT
+  0x08005688:  080067EC     DC.W       080067EC               ; R_ARM_ABS32
+  0x0800568C:  20000769     DC.W       _acUpBuffer
+  0x08005690:  20000B69     DC.W       _acDownBuffer
+  0x08005694:  080067EA     DC.W       080067EA               ; R_ARM_ABS32
+
+

Section .text.libc.SEGGER_RTT_WriteNoLock from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=104, align=4

+
+
SEGGER_RTT_WriteNoLock:
+  0x08005698:  B5F0         PUSH       {R4-R7, LR}
+  0x0800569A:  B081         SUB        SP, SP, #4
+  0x0800569C:  460D         MOV        R5, R1
+  0x0800569E:  2118         MOVS       R1, #24
+  0x080056A0:  4341         MULS       R1, R0, R1
+  0x080056A2:  4816         LDR        R0, =_SEGGER_RTT         ; [PC, #88] [0x080056FC] =0x20000314 
+  0x080056A4:  1846         ADDS       R6, R0, R1
+  0x080056A6:  6AF0         LDR        R0, [R6, #44]
+  0x080056A8:  3618         ADDS       R6, #24
+  0x080056AA:  2802         CMP        R0, #2
+  0x080056AC:  D01E         BEQ        .L3                      ; 0x080056EC
+  0x080056AE:  4614         MOV        R4, R2
+  0x080056B0:  2801         CMP        R0, #1
+  0x080056B2:  D00E         BEQ        .L1                      ; 0x080056D2
+  0x080056B4:  2700         MOVS       R7, #0
+  0x080056B6:  2800         CMP        R0, #0
+  0x080056B8:  D11D         BNE        .L4                      ; 0x080056F6
+  0x080056BA:  4630         MOV        R0, R6
+  0x080056BC:  F000 FAF7    BL         _GetAvailWriteSpace      ; 0x08005CAE
+  0x080056C0:  42A0         CMP        R0, R4
+  0x080056C2:  D318         BCC        .L4                      ; 0x080056F6
+  0x080056C4:  4630         MOV        R0, R6
+  0x080056C6:  4629         MOV        R1, R5
+  0x080056C8:  4622         MOV        R2, R4
+  0x080056CA:  F000 FAFB    BL         _WriteNoCheck            ; 0x08005CC4
+  0x080056CE:  4627         MOV        R7, R4
+  0x080056D0:  E011         B          .L4                      ; 0x080056F6
+
.L1:
+  0x080056D2:  4630         MOV        R0, R6
+  0x080056D4:  F000 FAEB    BL         _GetAvailWriteSpace      ; 0x08005CAE
+  0x080056D8:  4607         MOV        R7, R0
+  0x080056DA:  42A0         CMP        R0, R4
+  0x080056DC:  D300         BCC        .L2                      ; 0x080056E0
+  0x080056DE:  4627         MOV        R7, R4
+
.L2:
+  0x080056E0:  4630         MOV        R0, R6
+  0x080056E2:  4629         MOV        R1, R5
+  0x080056E4:  463A         MOV        R2, R7
+  0x080056E6:  F000 FAED    BL         _WriteNoCheck            ; 0x08005CC4
+  0x080056EA:  E004         B          .L4                      ; 0x080056F6
+
.L3:
+  0x080056EC:  4630         MOV        R0, R6
+  0x080056EE:  4629         MOV        R1, R5
+  0x080056F0:  F000 FD33    BL         _WriteBlocking           ; 0x0800615A
+  0x080056F4:  4607         MOV        R7, R0
+
.L4:
+  0x080056F6:  4638         MOV        R0, R7
+  0x080056F8:  B001         ADD        SP, SP, #4
+  0x080056FA:  BDF0         POP        {R4-R7, PC}
+  0x080056FC:  20000314     DC.W       _SEGGER_RTT
+
+

Section .text.libc.SEGGER_RTT_Write from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=56, align=4

+
+
SEGGER_RTT_Write:
+  0x08005700:  B5F0         PUSH       {R4-R7, LR}
+  0x08005702:  B081         SUB        SP, SP, #4
+  0x08005704:  4614         MOV        R4, R2
+  0x08005706:  460D         MOV        R5, R1
+  0x08005708:  4606         MOV        R6, R0
+  0x0800570A:  480A         LDR        R0, =_SEGGER_RTT         ; [PC, #40] [0x08005734] =0x20000314 
+  0x0800570C:  7800         LDRB       R0, [R0]
+  0x0800570E:  2800         CMP        R0, #0
+  0x08005710:  D101         BNE        .L1                      ; 0x08005716
+  0x08005712:  F7FF FF97    BL         _DoInit                  ; 0x08005644
+
.L1:
+  0x08005716:  F3EF 8710    MRS        R7, PRIMASK
+  0x0800571A:  2101         MOVS       R1, #1
+  0x0800571C:  F381 8810    MSR        PRIMASK, R1
+  0x08005720:  4630         MOV        R0, R6
+  0x08005722:  4629         MOV        R1, R5
+  0x08005724:  4622         MOV        R2, R4
+  0x08005726:  F7FF FFB7    BL         SEGGER_RTT_WriteNoLock   ; 0x08005698
+  0x0800572A:  F387 8810    MSR        PRIMASK, R7
+  0x0800572E:  B001         ADD        SP, SP, #4
+  0x08005730:  BDF0         POP        {R4-R7, PC}
+  0x08005732:  46C0         NOP
+  0x08005734:  20000314     DC.W       _SEGGER_RTT
+
+

Section .text.libc.__SEGGER_RTL_current_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=20, align=4

+
+
__SEGGER_RTL_current_locale:
+  0x08005738:  4802         LDR        R0, =__SEGGER_RTL_locale_ptr ; [PC, #8] [0x08005744] =0x200006D8 
+  0x0800573A:  6800         LDR        R0, [R0]
+  0x0800573C:  2800         CMP        R0, #0
+  0x0800573E:  D100         BNE        .L1                      ; 0x08005742
+  0x08005740:  4801         LDR        R0, =__SEGGER_RTL_global_locale ; [PC, #4] [0x08005748] =0x20000B80 
+
.L1:
+  0x08005742:  4770         BX         LR
+  0x08005744:  200006D8     DC.W       __SEGGER_RTL_locale_ptr
+  0x08005748:  20000B80     DC.W       __SEGGER_RTL_global_locale
+
+

Section .text.libc.__SEGGER_RTL_ascii_isctype from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__SEGGER_RTL_ascii_isctype:
+  0x0800574C:  287F         CMP        R0, #127
+  0x0800574E:  D805         BHI        .L1                      ; 0x0800575C
+  0x08005750:  4A03         LDR        R2, =__SEGGER_RTL_ascii_ctype_map ; [PC, #12] [0x08005760] =0x080069CC 
+  0x08005752:  5C12         LDRB       R2, [R2, R0]
+  0x08005754:  4803         LDR        R0, =__SEGGER_RTL_ascii_ctype_mask ; [PC, #12] [0x08005764] =0x08006856 
+  0x08005756:  5C40         LDRB       R0, [R0, R1]
+  0x08005758:  4010         ANDS       R0, R2
+  0x0800575A:  4770         BX         LR
+
.L1:
+  0x0800575C:  2000         MOVS       R0, #0
+  0x0800575E:  4770         BX         LR
+  0x08005760:  080069CC     DC.W       __SEGGER_RTL_ascii_ctype_map
+  0x08005764:  08006856     DC.W       __SEGGER_RTL_ascii_ctype_mask
+
+

Section .text.libc.__SEGGER_RTL_ascii_iswctype from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=28, align=4

+
+
__SEGGER_RTL_ascii_iswctype:
+  0x08005768:  287F         CMP        R0, #127
+  0x0800576A:  D805         BHI        .L1                      ; 0x08005778
+  0x0800576C:  4A03         LDR        R2, =__SEGGER_RTL_ascii_ctype_map ; [PC, #12] [0x0800577C] =0x080069CC 
+  0x0800576E:  5C12         LDRB       R2, [R2, R0]
+  0x08005770:  4803         LDR        R0, =__SEGGER_RTL_ascii_ctype_mask ; [PC, #12] [0x08005780] =0x08006856 
+  0x08005772:  5C40         LDRB       R0, [R0, R1]
+  0x08005774:  4010         ANDS       R0, R2
+  0x08005776:  4770         BX         LR
+
.L1:
+  0x08005778:  2000         MOVS       R0, #0
+  0x0800577A:  4770         BX         LR
+  0x0800577C:  080069CC     DC.W       __SEGGER_RTL_ascii_ctype_map
+  0x08005780:  08006856     DC.W       __SEGGER_RTL_ascii_ctype_mask
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=4

+
+
__SEGGER_RTL_c_locale:
+  0x08005784:  080065A9     DC.W       080065A9               ; R_ARM_ABS32
+  0x08005788:  080057B0     DC.W       __SEGGER_RTL_c_locale_data
+  0x0800578C:  08005790     DC.W       __SEGGER_RTL_codeset_ascii
+
+

Section .rodata.libc.__SEGGER_RTL_codeset_ascii from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=32, align=4

+
+
__SEGGER_RTL_codeset_ascii:
+  0x08005790:  0800574D     DC.W       __SEGGER_RTL_ascii_isctype
+  0x08005794:  080061D7     DC.W       __SEGGER_RTL_ascii_toupper
+  0x08005798:  08005D77     DC.W       __SEGGER_RTL_ascii_tolower
+  0x0800579C:  08005769     DC.W       __SEGGER_RTL_ascii_iswctype
+  0x080057A0:  080061E3     DC.W       __SEGGER_RTL_ascii_towupper
+  0x080057A4:  08005D85     DC.W       __SEGGER_RTL_ascii_towlower
+  0x080057A8:  080061C7     DC.W       __SEGGER_RTL_ascii_wctomb
+  0x080057AC:  08005D49     DC.W       __SEGGER_RTL_ascii_mbtowc
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_data from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=88, align=4

+
+
__SEGGER_RTL_c_locale_data:
+  0x080057B0:  080065AB     DC.W       __SEGGER_RTL_data_utf8_period
+  0x080057B4:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057B8:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057BC:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057C0:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057C4:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057C8:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057CC:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057D0:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057D4:  08006855     DC.W       __SEGGER_RTL_data_empty_string
+  0x080057D8:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057D9:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DA:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DB:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DC:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DD:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DE:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057DF:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E0:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E1:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E2:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E3:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E4:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E5:  FF           DC.B       0xFF                     ; '\xFF'
+  0x080057E6:  00           DC.B       0x00                     ; '\0'
+  0x080057E7:  00           DC.B       0x00                     ; '\0'
+  0x080057E8:  0800656F     DC.W       __SEGGER_RTL_c_locale_day_names
+  0x080057EC:  08006807     DC.W       __SEGGER_RTL_c_locale_abbrev_day_names
+  0x080057F0:  0800637E     DC.W       __SEGGER_RTL_c_locale_month_names
+  0x080057F4:  08006824     DC.W       __SEGGER_RTL_c_locale_abbrev_month_names
+  0x080057F8:  080063D5     DC.W       __SEGGER_RTL_c_locale_am_pm_indicator
+  0x080057FC:  080067F5     DC.W       __SEGGER_RTL_c_locale_date_format
+  0x08005800:  080067FE     DC.W       __SEGGER_RTL_c_locale_time_format
+  0x08005804:  080063DC     DC.W       __SEGGER_RTL_c_locale_date_time_format
+
+

Section .text.NMI_Handler from PowerPro_lto.o, size=2, align=2

+
+
NMI_Handler:
+  0x08005808:  E7FE         B          NMI_Handler              ; 0x08005808
+
+

Section .text.HardFault_Handler from PowerPro_lto.o, size=2, align=2

+
+
HardFault_Handler:
+  0x0800580A:  E7FE         B          HardFault_Handler        ; 0x0800580A
+
+

Section .text.SVC_Handler from PowerPro_lto.o, size=2, align=2

+
+
SVC_Handler:
+  0x0800580C:  4770         BX         LR
+
+

Section .text.PendSV_Handler from PowerPro_lto.o, size=2, align=2

+
+
PendSV_Handler:
+  0x0800580E:  4770         BX         LR
+
+

Section .text.ADC_DMAHalfConvCplt from PowerPro_lto.o, size=2, align=2

+
+
ADC_DMAHalfConvCplt:
+  0x08005810:  4770         BX         LR
+
+

Section .text.UART_DMATxHalfCplt from PowerPro_lto.o, size=2, align=2

+
+
UART_DMATxHalfCplt:
+  0x08005812:  4770         BX         LR
+
+

Section .text.UART_DMAError from PowerPro_lto.o, size=138, align=2

+
+
UART_DMAError:
+  0x08005814:  B5F0         PUSH       {R4-R7, LR}
+  0x08005816:  B081         SUB        SP, SP, #4
+  0x08005818:  6A84         LDR        R4, [R0, #40]
+  0x0800581A:  2088         MOVS       R0, #136
+  0x0800581C:  5823         LDR        R3, [R4, R0]
+  0x0800581E:  4625         MOV        R5, R4
+  0x08005820:  3588         ADDS       R5, #136
+  0x08005822:  686F         LDR        R7, [R5, #4]
+  0x08005824:  4620         MOV        R0, R4
+  0x08005826:  3056         ADDS       R0, #86
+  0x08005828:  6822         LDR        R2, [R4]
+  0x0800582A:  6896         LDR        R6, [R2, #8]
+  0x0800582C:  0636         LSLS       R6, R6, #24
+  0x0800582E:  D523         BPL        .L1                      ; 0x08005878
+  0x08005830:  2B21         CMP        R3, #33
+  0x08005832:  D121         BNE        .L1                      ; 0x08005878
+  0x08005834:  2200         MOVS       R2, #0
+  0x08005836:  8002         STRH       R2, [R0]
+  0x08005838:  F3EF 8110    MRS        R1, PRIMASK
+  0x0800583C:  9100         STR        R1, [SP, #0]
+  0x0800583E:  2301         MOVS       R3, #1
+  0x08005840:  F383 8810    MSR        PRIMASK, R3
+  0x08005844:  6826         LDR        R6, [R4]
+  0x08005846:  4602         MOV        R2, R0
+  0x08005848:  4638         MOV        R0, R7
+  0x0800584A:  6837         LDR        R7, [R6]
+  0x0800584C:  21C0         MOVS       R1, #192
+  0x0800584E:  438F         BICS       R7, R1
+  0x08005850:  6037         STR        R7, [R6]
+  0x08005852:  4607         MOV        R7, R0
+  0x08005854:  4610         MOV        R0, R2
+  0x08005856:  9900         LDR        R1, [SP, #0]
+  0x08005858:  F381 8810    MSR        PRIMASK, R1
+  0x0800585C:  F3EF 8110    MRS        R1, PRIMASK
+  0x08005860:  F383 8810    MSR        PRIMASK, R3
+  0x08005864:  05DA         LSLS       R2, R3, #23
+  0x08005866:  6823         LDR        R3, [R4]
+  0x08005868:  689E         LDR        R6, [R3, #8]
+  0x0800586A:  4396         BICS       R6, R2
+  0x0800586C:  609E         STR        R6, [R3, #8]
+  0x0800586E:  F381 8810    MSR        PRIMASK, R1
+  0x08005872:  2120         MOVS       R1, #32
+  0x08005874:  6029         STR        R1, [R5]
+  0x08005876:  6822         LDR        R2, [R4]
+
.L1:
+  0x08005878:  6891         LDR        R1, [R2, #8]
+  0x0800587A:  0649         LSLS       R1, R1, #25
+  0x0800587C:  D506         BPL        .L2                      ; 0x0800588C
+  0x0800587E:  2F22         CMP        R7, #34
+  0x08005880:  D104         BNE        .L2                      ; 0x0800588C
+  0x08005882:  2100         MOVS       R1, #0
+  0x08005884:  8101         STRH       R1, [R0, #8]
+  0x08005886:  4620         MOV        R0, R4
+  0x08005888:  F7FB FE0A    BL         UART_EndRxTransfer       ; 0x080014A0
+
.L2:
+  0x0800588C:  68A8         LDR        R0, [R5, #8]
+  0x0800588E:  2110         MOVS       R1, #16
+  0x08005890:  4301         ORRS       R1, R0
+  0x08005892:  60A9         STR        R1, [R5, #8]
+  0x08005894:  4620         MOV        R0, R4
+  0x08005896:  F7FE FE8B    BL         HAL_UART_ErrorCallback   ; 0x080045B0
+  0x0800589A:  B001         ADD        SP, SP, #4
+  0x0800589C:  BDF0         POP        {R4-R7, PC}
+
+

Section .init.WWDG_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
WWDG_IRQHandler:
+  0x0800589E:  E7FE         B          WWDG_IRQHandler          ; 0x0800589E
+
+

Section .init.RTC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
RTC_IRQHandler:
+  0x080058A0:  E7FE         B          RTC_IRQHandler           ; 0x080058A0
+
+

Section .init.FLASH_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
FLASH_IRQHandler:
+  0x080058A2:  E7FE         B          FLASH_IRQHandler         ; 0x080058A2
+
+

Section .init.RCC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
RCC_IRQHandler:
+  0x080058A4:  E7FE         B          RCC_IRQHandler           ; 0x080058A4
+
+

Section .init.EXTI0_1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI0_1_IRQHandler:
+  0x080058A6:  E7FE         B          EXTI0_1_IRQHandler       ; 0x080058A6
+
+

Section .init.EXTI2_3_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI2_3_IRQHandler:
+  0x080058A8:  E7FE         B          EXTI2_3_IRQHandler       ; 0x080058A8
+
+

Section .init.EXTI4_15_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
EXTI4_15_IRQHandler:
+  0x080058AA:  E7FE         B          EXTI4_15_IRQHandler      ; 0x080058AA
+
+

Section .init.DMAMUX1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
DMAMUX1_IRQHandler:
+  0x080058AC:  E7FE         B          DMAMUX1_IRQHandler       ; 0x080058AC
+
+

Section .init.ADC1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
ADC1_IRQHandler:
+  0x080058AE:  E7FE         B          ADC1_IRQHandler          ; 0x080058AE
+
+

Section .init.TIM1_BRK_UP_TRG_COM_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM1_BRK_UP_TRG_COM_IRQHandler:
+  0x080058B0:  E7FE         B          TIM1_BRK_UP_TRG_COM_IRQHandler ; 0x080058B0
+
+

Section .init.TIM1_CC_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM1_CC_IRQHandler:
+  0x080058B2:  E7FE         B          TIM1_CC_IRQHandler       ; 0x080058B2
+
+

Section .init.TIM3_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM3_IRQHandler:
+  0x080058B4:  E7FE         B          TIM3_IRQHandler          ; 0x080058B4
+
+

Section .init.TIM14_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM14_IRQHandler:
+  0x080058B6:  E7FE         B          TIM14_IRQHandler         ; 0x080058B6
+
+

Section .init.TIM17_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
TIM17_IRQHandler:
+  0x080058B8:  E7FE         B          TIM17_IRQHandler         ; 0x080058B8
+
+

Section .init.I2C1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
I2C1_IRQHandler:
+  0x080058BA:  E7FE         B          I2C1_IRQHandler          ; 0x080058BA
+
+

Section .init.SPI1_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
SPI1_IRQHandler:
+  0x080058BC:  E7FE         B          SPI1_IRQHandler          ; 0x080058BC
+
+

Section .init.USART2_IRQHandler from stm32c031xx_Vectors.o, size=2, align=2

+
+
USART2_IRQHandler:
+  0x080058BE:  E7FE         B          USART2_IRQHandler        ; 0x080058BE
+
+

Section .text.libc.fputc from fileops.o (libc_v6m_t_le_eabi_small.a), size=34, align=2

+
+
fputc:
+  0x080058C0:  B510         PUSH       {R4, LR}
+  0x080058C2:  B082         SUB        SP, SP, #8
+  0x080058C4:  460B         MOV        R3, R1
+  0x080058C6:  AC01         ADD        R4, SP, #4
+  0x080058C8:  7020         STRB       R0, [R4]
+  0x080058CA:  2101         MOVS       R1, #1
+  0x080058CC:  4620         MOV        R0, R4
+  0x080058CE:  460A         MOV        R2, R1
+  0x080058D0:  F000 F807    BL         fwrite                   ; 0x080058E2
+  0x080058D4:  2800         CMP        R0, #0
+  0x080058D6:  D001         BEQ        .L1                      ; 0x080058DC
+  0x080058D8:  7820         LDRB       R0, [R4]
+  0x080058DA:  E000         B          .L2                      ; 0x080058DE
+
.L1:
+  0x080058DC:  43C0         MVNS       R0, R0
+
.L2:
+  0x080058DE:  B002         ADD        SP, SP, #8
+  0x080058E0:  BD10         POP        {R4, PC}
+
+

Section .text.libc.fwrite from fileops.o (libc_v6m_t_le_eabi_small.a), size=50, align=2

+
+
fwrite:
+  0x080058E2:  B5F0         PUSH       {R4-R7, LR}
+  0x080058E4:  B081         SUB        SP, SP, #4
+  0x080058E6:  B40E         PUSH       {R1-R3}
+  0x080058E8:  BC70         POP        {R4-R6}
+  0x080058EA:  4607         MOV        R7, R0
+  0x080058EC:  4618         MOV        R0, R3
+  0x080058EE:  F7FF FE93    BL         __SEGGER_RTL_X_file_stat ; 0x08005618
+  0x080058F2:  4601         MOV        R1, R0
+  0x080058F4:  2000         MOVS       R0, #0
+  0x080058F6:  2900         CMP        R1, #0
+  0x080058F8:  D40A         BMI        .L1                      ; 0x08005910
+  0x080058FA:  4365         MULS       R5, R4, R5
+  0x080058FC:  42A5         CMP        R5, R4
+  0x080058FE:  D307         BCC        .L1                      ; 0x08005910
+  0x08005900:  4630         MOV        R0, R6
+  0x08005902:  4639         MOV        R1, R7
+  0x08005904:  462A         MOV        R2, R5
+  0x08005906:  F000 F9CD    BL         __SEGGER_RTL_X_file_write ; 0x08005CA4
+  0x0800590A:  4621         MOV        R1, R4
+  0x0800590C:  F000 FBBB    BL         __aeabi_uidiv            ; 0x08006086
+
.L1:
+  0x08005910:  B001         ADD        SP, SP, #4
+  0x08005912:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.__aeabi_fmul from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=182, align=2

+
+
__aeabi_fmul:
+  0x08005914:  B430         PUSH       {R4-R5}
+  0x08005916:  0005         MOVS       R5, R0
+  0x08005918:  404D         EORS       R5, R1
+  0x0800591A:  2401         MOVS       R4, #1
+  0x0800591C:  07E4         LSLS       R4, R4, #31
+  0x0800591E:  4025         ANDS       R5, R4
+  0x08005920:  0042         LSLS       R2, R0, #1
+  0x08005922:  004B         LSLS       R3, R1, #1
+  0x08005924:  0E12         LSRS       R2, R2, #24
+  0x08005926:  D032         BEQ        .L6                      ; 0x0800598E
+  0x08005928:  0E1B         LSRS       R3, R3, #24
+  0x0800592A:  D03C         BEQ        .L9                      ; 0x080059A6
+  0x0800592C:  2AFF         CMP        R2, #255
+  0x0800592E:  D033         BEQ        .L8                      ; 0x08005998
+  0x08005930:  2BFF         CMP        R3, #255
+  0x08005932:  D03F         BEQ        .L11                     ; 0x080059B4
+  0x08005934:  18D2         ADDS       R2, R2, R3
+  0x08005936:  0200         LSLS       R0, R0, #8
+  0x08005938:  4320         ORRS       R0, R4
+  0x0800593A:  0A00         LSRS       R0, R0, #8
+  0x0800593C:  0209         LSLS       R1, R1, #8
+  0x0800593E:  4321         ORRS       R1, R4
+  0x08005940:  0A09         LSRS       R1, R1, #8
+  0x08005942:  B2C4         UXTB       R4, R0
+  0x08005944:  434C         MULS       R4, R1, R4
+  0x08005946:  0A00         LSRS       R0, R0, #8
+  0x08005948:  B2C3         UXTB       R3, R0
+  0x0800594A:  434B         MULS       R3, R1, R3
+  0x0800594C:  0A00         LSRS       R0, R0, #8
+  0x0800594E:  4348         MULS       R0, R1, R0
+  0x08005950:  0A21         LSRS       R1, R4, #8
+  0x08005952:  185B         ADDS       R3, R3, R1
+  0x08005954:  0A19         LSRS       R1, R3, #8
+  0x08005956:  1809         ADDS       R1, R1, R0
+  0x08005958:  D401         BMI        .L1                      ; 0x0800595E
+  0x0800595A:  0049         LSLS       R1, R1, #1
+  0x0800595C:  1E52         SUBS       R2, R2, #1
+
.L1:
+  0x0800595E:  0A08         LSRS       R0, R1, #8
+  0x08005960:  3A7F         SUBS       R2, #127
+  0x08005962:  DB2A         BLT        .L12                     ; 0x080059BA
+  0x08005964:  2AFE         CMP        R2, #254
+  0x08005966:  D20F         BCS        .L5                      ; 0x08005988
+  0x08005968:  05D2         LSLS       R2, R2, #23
+  0x0800596A:  431C         ORRS       R4, R3
+  0x0800596C:  0624         LSLS       R4, R4, #24
+  0x0800596E:  D001         BEQ        .L2                      ; 0x08005974
+  0x08005970:  2401         MOVS       R4, #1
+  0x08005972:  4321         ORRS       R1, R4
+
.L2:
+  0x08005974:  B2C9         UXTB       R1, R1
+  0x08005976:  2980         CMP        R1, #128
+  0x08005978:  4150         ADCS       R0, R2
+  0x0800597A:  2980         CMP        R1, #128
+  0x0800597C:  D101         BNE        .L3                      ; 0x08005982
+  0x0800597E:  0840         LSRS       R0, R0, #1
+  0x08005980:  0040         LSLS       R0, R0, #1
+
.L3:
+  0x08005982:  4328         ORRS       R0, R5
+
.L4:
+  0x08005984:  BC30         POP        {R4-R5}
+  0x08005986:  4770         BX         LR
+
.L5:
+  0x08005988:  20FF         MOVS       R0, #255
+  0x0800598A:  05C0         LSLS       R0, R0, #23
+  0x0800598C:  E7F9         B          .L3                      ; 0x08005982
+
.L6:
+  0x0800598E:  0E1B         LSRS       R3, R3, #24
+  0x08005990:  2BFF         CMP        R3, #255
+  0x08005992:  D00A         BEQ        .L10                     ; 0x080059AA
+
.L7:
+  0x08005994:  0028         MOVS       R0, R5
+  0x08005996:  E7F5         B          .L4                      ; 0x08005984
+
.L8:
+  0x08005998:  0240         LSLS       R0, R0, #9
+  0x0800599A:  D106         BNE        .L10                     ; 0x080059AA
+  0x0800599C:  2BFF         CMP        R3, #255
+  0x0800599E:  D1F3         BNE        .L5                      ; 0x08005988
+  0x080059A0:  0249         LSLS       R1, R1, #9
+  0x080059A2:  D102         BNE        .L10                     ; 0x080059AA
+  0x080059A4:  E7F0         B          .L5                      ; 0x08005988
+
.L9:
+  0x080059A6:  2AFF         CMP        R2, #255
+  0x080059A8:  D1F4         BNE        .L7                      ; 0x08005994
+
.L10:
+  0x080059AA:  207F         MOVS       R0, #127
+  0x080059AC:  0100         LSLS       R0, R0, #4
+  0x080059AE:  300C         ADDS       R0, #12
+  0x080059B0:  0500         LSLS       R0, R0, #20
+  0x080059B2:  E7E7         B          .L4                      ; 0x08005984
+
.L11:
+  0x080059B4:  0249         LSLS       R1, R1, #9
+  0x080059B6:  D1F8         BNE        .L10                     ; 0x080059AA
+  0x080059B8:  E7E6         B          .L5                      ; 0x08005988
+
.L12:
+  0x080059BA:  0243         LSLS       R3, R0, #9
+  0x080059BC:  1C52         ADDS       R2, R2, #1
+  0x080059BE:  D1E9         BNE        .L7                      ; 0x08005994
+  0x080059C0:  125B         ASRS       R3, R3, #9
+  0x080059C2:  1C9B         ADDS       R3, R3, #2
+  0x080059C4:  D9E6         BLS        .L7                      ; 0x08005994
+  0x080059C6:  05D8         LSLS       R0, R3, #23
+  0x080059C8:  E7E4         B          .L7                      ; 0x08005994
+
+

Section .text.libc.__aeabi_dmul_aux from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=394, align=2

+
+
__aeabi_dmul_aux:
+  0x080059CA:  D108         BNE        .L2                      ; 0x080059DE
+  0x080059CC:  2800         CMP        R0, #0
+  0x080059CE:  D106         BNE        .L2                      ; 0x080059DE
+  0x080059D0:  42F5         CMN        R5, R6
+  0x080059D2:  D804         BHI        .L2                      ; 0x080059DE
+  0x080059D4:  D301         BCC        .L1                      ; 0x080059DA
+  0x080059D6:  2A00         CMP        R2, #0
+  0x080059D8:  D101         BNE        .L2                      ; 0x080059DE
+
.L1:
+  0x080059DA:  0D6D         LSRS       R5, R5, #21
+  0x080059DC:  D109         BNE        .L4                      ; 0x080059F2
+
.L2:
+  0x080059DE:  2000         MOVS       R0, #0
+  0x080059E0:  43C1         MVNS       R1, R0
+  0x080059E2:  0D09         LSRS       R1, R1, #20
+  0x080059E4:  04C9         LSLS       R1, R1, #19
+  0x080059E6:  BDF0         POP        {R4-R7, PC}
+
.L3:
+  0x080059E8:  D1F9         BNE        .L2                      ; 0x080059DE
+  0x080059EA:  4212         TST        R2, R2
+  0x080059EC:  D1F7         BNE        .L2                      ; 0x080059DE
+  0x080059EE:  0D64         LSRS       R4, R4, #21
+  0x080059F0:  D0F5         BEQ        .L2                      ; 0x080059DE
+
.L4:
+  0x080059F2:  2000         MOVS       R0, #0
+  0x080059F4:  43C1         MVNS       R1, R0
+  0x080059F6:  0549         LSLS       R1, R1, #21
+  0x080059F8:  0849         LSRS       R1, R1, #1
+  0x080059FA:  E0A6         B          .L7                      ; 0x08005B4A
+
.L5:
+  0x080059FC:  2000         MOVS       R0, #0
+  0x080059FE:  4661         MOV        R1, R12
+  0x08005A00:  BDF0         POP        {R4-R7, PC}
+
__aeabi_dmul:
+  0x08005A02:  B5F0         PUSH       {R4-R7, LR}
+  0x08005A04:  2701         MOVS       R7, #1
+  0x08005A06:  07FF         LSLS       R7, R7, #31
+  0x08005A08:  000E         MOVS       R6, R1
+  0x08005A0A:  405E         EORS       R6, R3
+  0x08005A0C:  403E         ANDS       R6, R7
+  0x08005A0E:  46B4         MOV        R12, R6
+  0x08005A10:  0ABE         LSRS       R6, R7, #10
+  0x08005A12:  184C         ADDS       R4, R1, R1
+  0x08005A14:  18DD         ADDS       R5, R3, R3
+  0x08005A16:  42F4         CMN        R4, R6
+  0x08005A18:  D2D7         BCS        __aeabi_dmul_aux         ; 0x080059CA
+  0x08005A1A:  42F5         CMN        R5, R6
+  0x08005A1C:  D2E4         BCS        .L3                      ; 0x080059E8
+  0x08005A1E:  0D64         LSRS       R4, R4, #21
+  0x08005A20:  D0EC         BEQ        .L5                      ; 0x080059FC
+  0x08005A22:  0D6D         LSRS       R5, R5, #21
+  0x08005A24:  D0EA         BEQ        .L5                      ; 0x080059FC
+  0x08005A26:  1964         ADDS       R4, R4, R5
+  0x08005A28:  02C9         LSLS       R1, R1, #11
+  0x08005A2A:  4339         ORRS       R1, R7
+  0x08005A2C:  0D46         LSRS       R6, R0, #21
+  0x08005A2E:  02C0         LSLS       R0, R0, #11
+  0x08005A30:  4331         ORRS       R1, R6
+  0x08005A32:  02DB         LSLS       R3, R3, #11
+  0x08005A34:  433B         ORRS       R3, R7
+  0x08005A36:  0ADB         LSRS       R3, R3, #11
+  0x08005A38:  B410         PUSH       {R4}
+  0x08005A3A:  468E         MOV        LR, R1
+  0x08005A3C:  B285         UXTH       R5, R0
+  0x08005A3E:  B297         UXTH       R7, R2
+  0x08005A40:  436F         MULS       R7, R5, R7
+  0x08005A42:  0C14         LSRS       R4, R2, #16
+  0x08005A44:  436C         MULS       R4, R5, R4
+  0x08005A46:  0C3E         LSRS       R6, R7, #16
+  0x08005A48:  19A4         ADDS       R4, R4, R6
+  0x08005A4A:  0C26         LSRS       R6, R4, #16
+  0x08005A4C:  0424         LSLS       R4, R4, #16
+  0x08005A4E:  B2BF         UXTH       R7, R7
+  0x08005A50:  4327         ORRS       R7, R4
+  0x08005A52:  B29C         UXTH       R4, R3
+  0x08005A54:  436C         MULS       R4, R5, R4
+  0x08005A56:  19A4         ADDS       R4, R4, R6
+  0x08005A58:  0C19         LSRS       R1, R3, #16
+  0x08005A5A:  4369         MULS       R1, R5, R1
+  0x08005A5C:  0C25         LSRS       R5, R4, #16
+  0x08005A5E:  B2A4         UXTH       R4, R4
+  0x08005A60:  1949         ADDS       R1, R1, R5
+  0x08005A62:  040D         LSLS       R5, R1, #16
+  0x08005A64:  0C09         LSRS       R1, R1, #16
+  0x08005A66:  1964         ADDS       R4, R4, R5
+  0x08005A68:  0C00         LSRS       R0, R0, #16
+  0x08005A6A:  B295         UXTH       R5, R2
+  0x08005A6C:  4345         MULS       R5, R0, R5
+  0x08005A6E:  0C3E         LSRS       R6, R7, #16
+  0x08005A70:  1976         ADDS       R6, R6, R5
+  0x08005A72:  4337         ORRS       R7, R6
+  0x08005A74:  B2BF         UXTH       R7, R7
+  0x08005A76:  0C36         LSRS       R6, R6, #16
+  0x08005A78:  0C15         LSRS       R5, R2, #16
+  0x08005A7A:  4345         MULS       R5, R0, R5
+  0x08005A7C:  19AD         ADDS       R5, R5, R6
+  0x08005A7E:  B2A6         UXTH       R6, R4
+  0x08005A80:  0C24         LSRS       R4, R4, #16
+  0x08005A82:  19AD         ADDS       R5, R5, R6
+  0x08005A84:  042E         LSLS       R6, R5, #16
+  0x08005A86:  4337         ORRS       R7, R6
+  0x08005A88:  0C2E         LSRS       R6, R5, #16
+  0x08005A8A:  1936         ADDS       R6, R6, R4
+  0x08005A8C:  B29D         UXTH       R5, R3
+  0x08005A8E:  4345         MULS       R5, R0, R5
+  0x08005A90:  19AD         ADDS       R5, R5, R6
+  0x08005A92:  B2AC         UXTH       R4, R5
+  0x08005A94:  0C2E         LSRS       R6, R5, #16
+  0x08005A96:  1989         ADDS       R1, R1, R6
+  0x08005A98:  0C1D         LSRS       R5, R3, #16
+  0x08005A9A:  4345         MULS       R5, R0, R5
+  0x08005A9C:  186D         ADDS       R5, R5, R1
+  0x08005A9E:  042E         LSLS       R6, R5, #16
+  0x08005AA0:  0C29         LSRS       R1, R5, #16
+  0x08005AA2:  4334         ORRS       R4, R6
+  0x08005AA4:  4670         MOV        R0, LR
+  0x08005AA6:  B280         UXTH       R0, R0
+  0x08005AA8:  B295         UXTH       R5, R2
+  0x08005AAA:  4345         MULS       R5, R0, R5
+  0x08005AAC:  0C3E         LSRS       R6, R7, #16
+  0x08005AAE:  1976         ADDS       R6, R6, R5
+  0x08005AB0:  4337         ORRS       R7, R6
+  0x08005AB2:  B2BF         UXTH       R7, R7
+  0x08005AB4:  0C36         LSRS       R6, R6, #16
+  0x08005AB6:  0C15         LSRS       R5, R2, #16
+  0x08005AB8:  4345         MULS       R5, R0, R5
+  0x08005ABA:  19AD         ADDS       R5, R5, R6
+  0x08005ABC:  B2A6         UXTH       R6, R4
+  0x08005ABE:  19AD         ADDS       R5, R5, R6
+  0x08005AC0:  0C24         LSRS       R4, R4, #16
+  0x08005AC2:  042E         LSLS       R6, R5, #16
+  0x08005AC4:  4337         ORRS       R7, R6
+  0x08005AC6:  0C2E         LSRS       R6, R5, #16
+  0x08005AC8:  1936         ADDS       R6, R6, R4
+  0x08005ACA:  B29D         UXTH       R5, R3
+  0x08005ACC:  4345         MULS       R5, R0, R5
+  0x08005ACE:  19AD         ADDS       R5, R5, R6
+  0x08005AD0:  B2AC         UXTH       R4, R5
+  0x08005AD2:  0C2E         LSRS       R6, R5, #16
+  0x08005AD4:  1989         ADDS       R1, R1, R6
+  0x08005AD6:  0C1D         LSRS       R5, R3, #16
+  0x08005AD8:  4345         MULS       R5, R0, R5
+  0x08005ADA:  186D         ADDS       R5, R5, R1
+  0x08005ADC:  042E         LSLS       R6, R5, #16
+  0x08005ADE:  4334         ORRS       R4, R6
+  0x08005AE0:  0C29         LSRS       R1, R5, #16
+  0x08005AE2:  4675         MOV        R5, LR
+  0x08005AE4:  0C2D         LSRS       R5, R5, #16
+  0x08005AE6:  B290         UXTH       R0, R2
+  0x08005AE8:  4368         MULS       R0, R5, R0
+  0x08005AEA:  0C3E         LSRS       R6, R7, #16
+  0x08005AEC:  1980         ADDS       R0, R0, R6
+  0x08005AEE:  0406         LSLS       R6, R0, #16
+  0x08005AF0:  B2BF         UXTH       R7, R7
+  0x08005AF2:  433E         ORRS       R6, R7
+  0x08005AF4:  0C07         LSRS       R7, R0, #16
+  0x08005AF6:  B2A0         UXTH       R0, R4
+  0x08005AF8:  183F         ADDS       R7, R7, R0
+  0x08005AFA:  0C12         LSRS       R2, R2, #16
+  0x08005AFC:  436A         MULS       R2, R5, R2
+  0x08005AFE:  19D0         ADDS       R0, R2, R7
+  0x08005B00:  0C02         LSRS       R2, R0, #16
+  0x08005B02:  B280         UXTH       R0, R0
+  0x08005B04:  0C24         LSRS       R4, R4, #16
+  0x08005B06:  18A4         ADDS       R4, R4, R2
+  0x08005B08:  B29A         UXTH       R2, R3
+  0x08005B0A:  436A         MULS       R2, R5, R2
+  0x08005B0C:  1912         ADDS       R2, R2, R4
+  0x08005B0E:  0414         LSLS       R4, R2, #16
+  0x08005B10:  4320         ORRS       R0, R4
+  0x08005B12:  0C12         LSRS       R2, R2, #16
+  0x08005B14:  1889         ADDS       R1, R1, R2
+  0x08005B16:  0C1B         LSRS       R3, R3, #16
+  0x08005B18:  436B         MULS       R3, R5, R3
+  0x08005B1A:  18C9         ADDS       R1, R1, R3
+  0x08005B1C:  BC10         POP        {R4}
+  0x08005B1E:  2701         MOVS       R7, #1
+  0x08005B20:  053D         LSLS       R5, R7, #20
+  0x08005B22:  4229         TST        R1, R5
+  0x08005B24:  D103         BNE        .L6                      ; 0x08005B2E
+  0x08005B26:  19B6         ADDS       R6, R6, R6
+  0x08005B28:  4140         ADCS       R0, R0
+  0x08005B2A:  4149         ADCS       R1, R1
+  0x08005B2C:  1E64         SUBS       R4, R4, #1
+
.L6:
+  0x08005B2E:  07FF         LSLS       R7, R7, #31
+  0x08005B30:  0D7D         LSRS       R5, R7, #21
+  0x08005B32:  1E6D         SUBS       R5, R5, #1
+  0x08005B34:  1B64         SUBS       R4, R4, R5
+  0x08005B36:  DB0B         BLT        .L8                      ; 0x08005B50
+  0x08005B38:  006D         LSLS       R5, R5, #1
+  0x08005B3A:  42AC         CMP        R4, R5
+  0x08005B3C:  DA09         BGE        .L9                      ; 0x08005B52
+  0x08005B3E:  0524         LSLS       R4, R4, #20
+  0x08005B40:  2500         MOVS       R5, #0
+  0x08005B42:  0842         LSRS       R2, R0, #1
+  0x08005B44:  41BE         SBCS       R6, R7
+  0x08005B46:  4168         ADCS       R0, R5
+  0x08005B48:  4161         ADCS       R1, R4
+
.L7:
+  0x08005B4A:  4666         MOV        R6, R12
+  0x08005B4C:  4331         ORRS       R1, R6
+  0x08005B4E:  BDF0         POP        {R4-R7, PC}
+
.L8:
+  0x08005B50:  E754         B          .L5                      ; 0x080059FC
+
.L9:
+  0x08005B52:  E74E         B          .L4                      ; 0x080059F2
+
+

Section .text.libc.__aeabi_d2uiz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__aeabi_d2uiz:
+  0x08005B54:  004A         LSLS       R2, R1, #1
+  0x08005B56:  D210         BCS        .L1                      ; 0x08005B7A
+  0x08005B58:  0D52         LSRS       R2, R2, #21
+  0x08005B5A:  2303         MOVS       R3, #3
+  0x08005B5C:  021B         LSLS       R3, R3, #8
+  0x08005B5E:  33FF         ADDS       R3, #255
+  0x08005B60:  1AD2         SUBS       R2, R2, R3
+  0x08005B62:  D40A         BMI        .L1                      ; 0x08005B7A
+  0x08005B64:  4252         RSBS       R2, R2, #0
+  0x08005B66:  321F         ADDS       R2, #31
+  0x08005B68:  D409         BMI        .L2                      ; 0x08005B7E
+  0x08005B6A:  0D40         LSRS       R0, R0, #21
+  0x08005B6C:  02C9         LSLS       R1, R1, #11
+  0x08005B6E:  4308         ORRS       R0, R1
+  0x08005B70:  2301         MOVS       R3, #1
+  0x08005B72:  07DB         LSLS       R3, R3, #31
+  0x08005B74:  4318         ORRS       R0, R3
+  0x08005B76:  40D0         LSRS       R0, R2
+  0x08005B78:  4770         BX         LR
+
.L1:
+  0x08005B7A:  2000         MOVS       R0, #0
+  0x08005B7C:  4770         BX         LR
+
.L2:
+  0x08005B7E:  17D0         ASRS       R0, R2, #31
+  0x08005B80:  4770         BX         LR
+
+

Section .text.libc.__aeabi_ui2f from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=30, align=2

+
+
__aeabi_ui2f:
+  0x08005B82:  229D         MOVS       R2, #157
+  0x08005B84:  0001         MOVS       R1, R0
+  0x08005B86:  D00A         BEQ        .L4                      ; 0x08005B9E
+  0x08005B88:  D402         BMI        .L2                      ; 0x08005B90
+
.L1:
+  0x08005B8A:  1E52         SUBS       R2, R2, #1
+  0x08005B8C:  0049         LSLS       R1, R1, #1
+  0x08005B8E:  D5FC         BPL        .L1                      ; 0x08005B8A
+
.L2:
+  0x08005B90:  05D2         LSLS       R2, R2, #23
+  0x08005B92:  0A08         LSRS       R0, R1, #8
+  0x08005B94:  0609         LSLS       R1, R1, #24
+  0x08005B96:  4149         ADCS       R1, R1
+  0x08005B98:  D300         BCC        .L3                      ; 0x08005B9C
+  0x08005B9A:  2901         CMP        R1, #1
+
.L3:
+  0x08005B9C:  4150         ADCS       R0, R2
+
.L4:
+  0x08005B9E:  4770         BX         LR
+
+

Section .text.libc.__aeabi_lmul from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__aeabi_lmul:
+  0x08005BA0:  B530         PUSH       {R4-R5, LR}
+  0x08005BA2:  4351         MULS       R1, R2, R1
+  0x08005BA4:  4343         MULS       R3, R0, R3
+  0x08005BA6:  185C         ADDS       R4, R3, R1
+  0x08005BA8:  0C01         LSRS       R1, R0, #16
+  0x08005BAA:  0C13         LSRS       R3, R2, #16
+  0x08005BAC:  000D         MOVS       R5, R1
+  0x08005BAE:  435D         MULS       R5, R3, R5
+  0x08005BB0:  1964         ADDS       R4, R4, R5
+  0x08005BB2:  B292         UXTH       R2, R2
+  0x08005BB4:  4351         MULS       R1, R2, R1
+  0x08005BB6:  B280         UXTH       R0, R0
+  0x08005BB8:  4342         MULS       R2, R0, R2
+  0x08005BBA:  0C0D         LSRS       R5, R1, #16
+  0x08005BBC:  0409         LSLS       R1, R1, #16
+  0x08005BBE:  1852         ADDS       R2, R2, R1
+  0x08005BC0:  4165         ADCS       R5, R4
+  0x08005BC2:  4358         MULS       R0, R3, R0
+  0x08005BC4:  0C01         LSRS       R1, R0, #16
+  0x08005BC6:  0400         LSLS       R0, R0, #16
+  0x08005BC8:  1880         ADDS       R0, R0, R2
+  0x08005BCA:  4169         ADCS       R1, R5
+  0x08005BCC:  BD30         POP        {R4-R5, PC}
+
+

Section .text.libc.__aeabi_idiv0 from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=6, align=2

+
+
__aeabi_idiv0:
+  0x08005BCE:  2000         MOVS       R0, #0
+  0x08005BD0:  2100         MOVS       R1, #0
+  0x08005BD2:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_putc from prinops.o (libc_v6m_t_le_eabi_small.a), size=138, align=2

+
+
__SEGGER_RTL_putc:
+  0x08005BD4:  B530         PUSH       {R4-R5, LR}
+  0x08005BD6:  B081         SUB        SP, SP, #4
+  0x08005BD8:  4604         MOV        R4, R0
+  0x08005BDA:  4668         MOV        R0, SP
+  0x08005BDC:  7001         STRB       R1, [R0]
+  0x08005BDE:  6920         LDR        R0, [R4, #16]
+  0x08005BE0:  2800         CMP        R0, #0
+  0x08005BE2:  D00F         BEQ        .L1                      ; 0x08005C04
+  0x08005BE4:  CC0C         LDM        R4!, {R2-R3}
+  0x08005BE6:  3C08         SUBS       R4, #8
+  0x08005BE8:  429A         CMP        R2, R3
+  0x08005BEA:  D233         BCS        .L7                      ; 0x08005C54
+  0x08005BEC:  6962         LDR        R2, [R4, #20]
+  0x08005BEE:  1C53         ADDS       R3, R2, #1
+  0x08005BF0:  6163         STR        R3, [R4, #20]
+  0x08005BF2:  5481         STRB       R1, [R0, R2]
+  0x08005BF4:  69A0         LDR        R0, [R4, #24]
+  0x08005BF6:  6961         LDR        R1, [R4, #20]
+  0x08005BF8:  4281         CMP        R1, R0
+  0x08005BFA:  D12B         BNE        .L7                      ; 0x08005C54
+  0x08005BFC:  4620         MOV        R0, R4
+  0x08005BFE:  F000 F82E    BL         __SEGGER_RTL_prin_flush  ; 0x08005C5E
+  0x08005C02:  E027         B          .L7                      ; 0x08005C54
+
.L1:
+  0x08005C04:  68E0         LDR        R0, [R4, #12]
+  0x08005C06:  2800         CMP        R0, #0
+  0x08005C08:  D009         BEQ        .L3                      ; 0x08005C1E
+  0x08005C0A:  CC0C         LDM        R4!, {R2-R3}
+  0x08005C0C:  3C08         SUBS       R4, #8
+  0x08005C0E:  429A         CMP        R2, R3
+  0x08005C10:  D220         BCS        .L7                      ; 0x08005C54
+  0x08005C12:  1C55         ADDS       R5, R2, #1
+  0x08005C14:  429D         CMP        R5, R3
+  0x08005C16:  D100         BNE        .L2                      ; 0x08005C1A
+  0x08005C18:  2100         MOVS       R1, #0
+
.L2:
+  0x08005C1A:  5481         STRB       R1, [R0, R2]
+  0x08005C1C:  E01A         B          .L7                      ; 0x08005C54
+
.L3:
+  0x08005C1E:  68A0         LDR        R0, [R4, #8]
+  0x08005C20:  2800         CMP        R0, #0
+  0x08005C22:  D008         BEQ        .L4                      ; 0x08005C36
+  0x08005C24:  CC0C         LDM        R4!, {R2-R3}
+  0x08005C26:  3C08         SUBS       R4, #8
+  0x08005C28:  429A         CMP        R2, R3
+  0x08005C2A:  D213         BCS        .L7                      ; 0x08005C54
+  0x08005C2C:  1C55         ADDS       R5, R2, #1
+  0x08005C2E:  429D         CMP        R5, R3
+  0x08005C30:  D00D         BEQ        .L5                      ; 0x08005C4E
+  0x08005C32:  B2C9         UXTB       R1, R1
+  0x08005C34:  E00C         B          .L6                      ; 0x08005C50
+
.L4:
+  0x08005C36:  6A23         LDR        R3, [R4, #32]
+  0x08005C38:  2B00         CMP        R3, #0
+  0x08005C3A:  D00B         BEQ        .L7                      ; 0x08005C54
+  0x08005C3C:  CC03         LDM        R4!, {R0-R1}
+  0x08005C3E:  3C08         SUBS       R4, #8
+  0x08005C40:  4288         CMP        R0, R1
+  0x08005C42:  D207         BCS        .L7                      ; 0x08005C54
+  0x08005C44:  4669         MOV        R1, SP
+  0x08005C46:  2201         MOVS       R2, #1
+  0x08005C48:  4620         MOV        R0, R4
+  0x08005C4A:  4798         BLX        R3
+  0x08005C4C:  E002         B          .L7                      ; 0x08005C54
+
.L5:
+  0x08005C4E:  2100         MOVS       R1, #0
+
.L6:
+  0x08005C50:  0092         LSLS       R2, R2, #2
+  0x08005C52:  5081         STR        R1, [R0, R2]
+
.L7:
+  0x08005C54:  6820         LDR        R0, [R4]
+  0x08005C56:  1C40         ADDS       R0, R0, #1
+  0x08005C58:  6020         STR        R0, [R4]
+  0x08005C5A:  B001         ADD        SP, SP, #4
+  0x08005C5C:  BD30         POP        {R4-R5, PC}
+
+

Section .text.libc.__SEGGER_RTL_prin_flush from prinops.o (libc_v6m_t_le_eabi_small.a), size=26, align=2

+
+
__SEGGER_RTL_prin_flush:
+  0x08005C5E:  B510         PUSH       {R4, LR}
+  0x08005C60:  6942         LDR        R2, [R0, #20]
+  0x08005C62:  2A00         CMP        R2, #0
+  0x08005C64:  D007         BEQ        .L2                      ; 0x08005C76
+  0x08005C66:  4604         MOV        R4, R0
+  0x08005C68:  6A03         LDR        R3, [R0, #32]
+  0x08005C6A:  2B00         CMP        R3, #0
+  0x08005C6C:  D001         BEQ        .L1                      ; 0x08005C72
+  0x08005C6E:  6921         LDR        R1, [R4, #16]
+  0x08005C70:  4798         BLX        R3
+
.L1:
+  0x08005C72:  2000         MOVS       R0, #0
+  0x08005C74:  6160         STR        R0, [R4, #20]
+
.L2:
+  0x08005C76:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_init_prin_l from prinops.o (libc_v6m_t_le_eabi_small.a), size=18, align=2

+
+
__SEGGER_RTL_init_prin_l:
+  0x08005C78:  B5B0         PUSH       {R4-R5, R7, LR}
+  0x08005C7A:  460C         MOV        R4, R1
+  0x08005C7C:  4605         MOV        R5, R0
+  0x08005C7E:  2100         MOVS       R1, #0
+  0x08005C80:  2224         MOVS       R2, #36
+  0x08005C82:  F000 FA9A    BL         memset                   ; 0x080061BA
+  0x08005C86:  61EC         STR        R4, [R5, #28]
+  0x08005C88:  BDB0         POP        {R4-R5, R7, PC}
+
+

Section .text.libc.vfprintf from prinops.o (libc_v6m_t_le_eabi_small.a), size=26, align=2

+
+
vfprintf:
+  0x08005C8A:  B570         PUSH       {R4-R6, LR}
+  0x08005C8C:  4614         MOV        R4, R2
+  0x08005C8E:  460D         MOV        R5, R1
+  0x08005C90:  4606         MOV        R6, R0
+  0x08005C92:  F7FF FD51    BL         __SEGGER_RTL_current_locale ; 0x08005738
+  0x08005C96:  4601         MOV        R1, R0
+  0x08005C98:  4630         MOV        R0, R6
+  0x08005C9A:  462A         MOV        R2, R5
+  0x08005C9C:  4623         MOV        R3, R4
+  0x08005C9E:  F7FF FACD    BL         vfprintf_l               ; 0x0800523C
+  0x08005CA2:  BD70         POP        {R4-R6, PC}
+
+

Section .text.libc.__SEGGER_RTL_X_file_write from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=10, align=2

+
+
__SEGGER_RTL_X_file_write:
+  0x08005CA4:  B580         PUSH       {R7, LR}
+  0x08005CA6:  6800         LDR        R0, [R0]
+  0x08005CA8:  F7FF FD2A    BL         SEGGER_RTT_Write         ; 0x08005700
+  0x08005CAC:  BD80         POP        {R7, PC}
+
+

Section .text.libc._GetAvailWriteSpace from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=22, align=2

+
+
_GetAvailWriteSpace:
+  0x08005CAE:  68C2         LDR        R2, [R0, #12]
+  0x08005CB0:  6901         LDR        R1, [R0, #16]
+  0x08005CB2:  4291         CMP        R1, R2
+  0x08005CB4:  D901         BLS        .L1                      ; 0x08005CBA
+  0x08005CB6:  43D0         MVNS       R0, R2
+  0x08005CB8:  E002         B          .L2                      ; 0x08005CC0
+
.L1:
+  0x08005CBA:  43D2         MVNS       R2, R2
+  0x08005CBC:  1889         ADDS       R1, R1, R2
+  0x08005CBE:  6880         LDR        R0, [R0, #8]
+
.L2:
+  0x08005CC0:  1808         ADDS       R0, R1, R0
+  0x08005CC2:  4770         BX         LR
+
+

Section .text.libc._WriteNoCheck from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=58, align=2

+
+
_WriteNoCheck:
+  0x08005CC4:  B5F0         PUSH       {R4-R7, LR}
+  0x08005CC6:  B081         SUB        SP, SP, #4
+  0x08005CC8:  4615         MOV        R5, R2
+  0x08005CCA:  4604         MOV        R4, R0
+  0x08005CCC:  6840         LDR        R0, [R0, #4]
+  0x08005CCE:  68A2         LDR        R2, [R4, #8]
+  0x08005CD0:  68E6         LDR        R6, [R4, #12]
+  0x08005CD2:  1980         ADDS       R0, R0, R6
+  0x08005CD4:  1B97         SUBS       R7, R2, R6
+  0x08005CD6:  42BD         CMP        R5, R7
+  0x08005CD8:  D204         BCS        .L1                      ; 0x08005CE4
+  0x08005CDA:  462A         MOV        R2, R5
+  0x08005CDC:  F000 F82D    BL         memcpy                   ; 0x08005D3A
+  0x08005CE0:  1975         ADDS       R5, R6, R5
+  0x08005CE2:  E009         B          .L2                      ; 0x08005CF8
+
.L1:
+  0x08005CE4:  460E         MOV        R6, R1
+  0x08005CE6:  463A         MOV        R2, R7
+  0x08005CE8:  F000 F827    BL         memcpy                   ; 0x08005D3A
+  0x08005CEC:  19F1         ADDS       R1, R6, R7
+  0x08005CEE:  1BED         SUBS       R5, R5, R7
+  0x08005CF0:  6860         LDR        R0, [R4, #4]
+  0x08005CF2:  462A         MOV        R2, R5
+  0x08005CF4:  F000 F821    BL         memcpy                   ; 0x08005D3A
+
.L2:
+  0x08005CF8:  60E5         STR        R5, [R4, #12]
+  0x08005CFA:  B001         ADD        SP, SP, #4
+  0x08005CFC:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.memcmp from strops.o (strops_v6m_t_le_eabi_small.a), size=46, align=2

+
+
memcmp:
+  0x08005CFE:  B5F0         PUSH       {R4-R7, LR}
+  0x08005D00:  2A00         CMP        R2, #0
+  0x08005D02:  D00D         BEQ        .L2                      ; 0x08005D20
+  0x08005D04:  1E52         SUBS       R2, R2, #1
+  0x08005D06:  4613         MOV        R3, R2
+  0x08005D08:  4604         MOV        R4, R0
+  0x08005D0A:  460D         MOV        R5, R1
+
.L1:
+  0x08005D0C:  2B00         CMP        R3, #0
+  0x08005D0E:  D009         BEQ        .L3                      ; 0x08005D24
+  0x08005D10:  782E         LDRB       R6, [R5]
+  0x08005D12:  7827         LDRB       R7, [R4]
+  0x08005D14:  42B7         CMP        R7, R6
+  0x08005D16:  D107         BNE        .L4                      ; 0x08005D28
+  0x08005D18:  1E5B         SUBS       R3, R3, #1
+  0x08005D1A:  1C6D         ADDS       R5, R5, #1
+  0x08005D1C:  1C64         ADDS       R4, R4, #1
+  0x08005D1E:  E7F5         B          .L1                      ; 0x08005D0C
+
.L2:
+  0x08005D20:  2000         MOVS       R0, #0
+  0x08005D22:  BDF0         POP        {R4-R7, PC}
+
.L3:
+  0x08005D24:  5C8E         LDRB       R6, [R1, R2]
+  0x08005D26:  5C87         LDRB       R7, [R0, R2]
+
.L4:
+  0x08005D28:  1BB8         SUBS       R0, R7, R6
+  0x08005D2A:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.strlen from strops.o (strops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
strlen:
+  0x08005D2C:  2100         MOVS       R1, #0
+
.L1:
+  0x08005D2E:  5C42         LDRB       R2, [R0, R1]
+  0x08005D30:  1C49         ADDS       R1, R1, #1
+  0x08005D32:  2A00         CMP        R2, #0
+  0x08005D34:  D1FB         BNE        .L1                      ; 0x08005D2E
+  0x08005D36:  1E48         SUBS       R0, R1, #1
+  0x08005D38:  4770         BX         LR
+
+

Section .text.libc.memcpy from strasmops_arm.o (strops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
memcpy:
+__aeabi_memcpy:
+__aeabi_memcpy4:
+__aeabi_memcpy8:
+  0x08005D3A:  2A00         CMP        R2, #0
+  0x08005D3C:  D003         BEQ        .L2                      ; 0x08005D46
+
.L1:
+  0x08005D3E:  1E52         SUBS       R2, R2, #1
+  0x08005D40:  5C8B         LDRB       R3, [R1, R2]
+  0x08005D42:  5483         STRB       R3, [R0, R2]
+  0x08005D44:  D1FB         BNE        .L1                      ; 0x08005D3E
+
.L2:
+  0x08005D46:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_mbtowc from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=46, align=2

+
+
__SEGGER_RTL_ascii_mbtowc:
+  0x08005D48:  B510         PUSH       {R4, LR}
+  0x08005D4A:  4604         MOV        R4, R0
+  0x08005D4C:  2000         MOVS       R0, #0
+  0x08005D4E:  2900         CMP        R1, #0
+  0x08005D50:  D010         BEQ        .L3                      ; 0x08005D74
+  0x08005D52:  2A00         CMP        R2, #0
+  0x08005D54:  D00E         BEQ        .L3                      ; 0x08005D74
+  0x08005D56:  7809         LDRB       R1, [R1]
+  0x08005D58:  B248         SXTB       R0, R1
+  0x08005D5A:  2800         CMP        R0, #0
+  0x08005D5C:  D408         BMI        .L2                      ; 0x08005D70
+  0x08005D5E:  2C00         CMP        R4, #0
+  0x08005D60:  D000         BEQ        .L1                      ; 0x08005D64
+  0x08005D62:  6021         STR        R1, [R4]
+
.L1:
+  0x08005D64:  2100         MOVS       R1, #0
+  0x08005D66:  6019         STR        R1, [R3]
+  0x08005D68:  6059         STR        R1, [R3, #4]
+  0x08005D6A:  1E41         SUBS       R1, R0, #1
+  0x08005D6C:  4188         SBCS       R0, R1
+  0x08005D6E:  BD10         POP        {R4, PC}
+
.L2:
+  0x08005D70:  2001         MOVS       R0, #1
+  0x08005D72:  43C0         MVNS       R0, R0
+
.L3:
+  0x08005D74:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_ascii_tolower from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
__SEGGER_RTL_ascii_tolower:
+  0x08005D76:  4601         MOV        R1, R0
+  0x08005D78:  3941         SUBS       R1, #65
+  0x08005D7A:  291A         CMP        R1, #26
+  0x08005D7C:  D201         BCS        .L1                      ; 0x08005D82
+  0x08005D7E:  2120         MOVS       R1, #32
+  0x08005D80:  4308         ORRS       R0, R1
+
.L1:
+  0x08005D82:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_towlower from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=14, align=2

+
+
__SEGGER_RTL_ascii_towlower:
+  0x08005D84:  4601         MOV        R1, R0
+  0x08005D86:  3941         SUBS       R1, #65
+  0x08005D88:  291A         CMP        R1, #26
+  0x08005D8A:  D201         BCS        .L1                      ; 0x08005D90
+  0x08005D8C:  2120         MOVS       R1, #32
+  0x08005D8E:  4308         ORRS       R0, R1
+
.L1:
+  0x08005D90:  4770         BX         LR
+
+

Section .text.ADC_DMAConvCplt from PowerPro_lto.o, size=100, align=2

+
+
ADC_DMAConvCplt:
+  0x08005D92:  B580         PUSH       {R7, LR}
+  0x08005D94:  6A81         LDR        R1, [R0, #40]
+  0x08005D96:  6D8A         LDR        R2, [R1, #88]
+  0x08005D98:  2350         MOVS       R3, #80
+  0x08005D9A:  421A         TST        R2, R3
+  0x08005D9C:  6D8A         LDR        R2, [R1, #88]
+  0x08005D9E:  D005         BEQ        .L1                      ; 0x08005DAC
+  0x08005DA0:  06D2         LSLS       R2, R2, #27
+  0x08005DA2:  D427         BMI        .L3                      ; 0x08005DF4
+  0x08005DA4:  6D09         LDR        R1, [R1, #80]
+  0x08005DA6:  6B49         LDR        R1, [R1, #52]
+  0x08005DA8:  4788         BLX        R1
+  0x08005DAA:  BD80         POP        {R7, PC}
+
.L1:
+  0x08005DAC:  2001         MOVS       R0, #1
+  0x08005DAE:  0243         LSLS       R3, R0, #9
+  0x08005DB0:  431A         ORRS       R2, R3
+  0x08005DB2:  658A         STR        R2, [R1, #88]
+  0x08005DB4:  680A         LDR        R2, [R1]
+  0x08005DB6:  68D3         LDR        R3, [R2, #12]
+  0x08005DB8:  051B         LSLS       R3, R3, #20
+  0x08005DBA:  0F9B         LSRS       R3, R3, #30
+  0x08005DBC:  D11A         BNE        .L3                      ; 0x08005DF4
+  0x08005DBE:  7E8B         LDRB       R3, [R1, #26]
+  0x08005DC0:  2B00         CMP        R3, #0
+  0x08005DC2:  D117         BNE        .L3                      ; 0x08005DF4
+  0x08005DC4:  6813         LDR        R3, [R2]
+  0x08005DC6:  071B         LSLS       R3, R3, #28
+  0x08005DC8:  D514         BPL        .L3                      ; 0x08005DF4
+  0x08005DCA:  6893         LDR        R3, [R2, #8]
+  0x08005DCC:  075B         LSLS       R3, R3, #29
+  0x08005DCE:  D40A         BMI        .L2                      ; 0x08005DE6
+  0x08005DD0:  6850         LDR        R0, [R2, #4]
+  0x08005DD2:  230C         MOVS       R3, #12
+  0x08005DD4:  4398         BICS       R0, R3
+  0x08005DD6:  6050         STR        R0, [R2, #4]
+  0x08005DD8:  20FF         MOVS       R0, #255
+  0x08005DDA:  3002         ADDS       R0, #2
+  0x08005DDC:  6D8A         LDR        R2, [R1, #88]
+  0x08005DDE:  4382         BICS       R2, R0
+  0x08005DE0:  1C50         ADDS       R0, R2, #1
+  0x08005DE2:  6588         STR        R0, [R1, #88]
+  0x08005DE4:  BD80         POP        {R7, PC}
+
.L2:
+  0x08005DE6:  6D8A         LDR        R2, [R1, #88]
+  0x08005DE8:  2320         MOVS       R3, #32
+  0x08005DEA:  4313         ORRS       R3, R2
+  0x08005DEC:  658B         STR        R3, [R1, #88]
+  0x08005DEE:  6DCA         LDR        R2, [R1, #92]
+  0x08005DF0:  4302         ORRS       R2, R0
+  0x08005DF2:  65CA         STR        R2, [R1, #92]
+
.L3:
+  0x08005DF4:  BD80         POP        {R7, PC}
+
+

Section .text.ADC_DMAError from PowerPro_lto.o, size=20, align=2

+
+
ADC_DMAError:
+  0x08005DF6:  6A80         LDR        R0, [R0, #40]
+  0x08005DF8:  6D81         LDR        R1, [R0, #88]
+  0x08005DFA:  2240         MOVS       R2, #64
+  0x08005DFC:  430A         ORRS       R2, R1
+  0x08005DFE:  6582         STR        R2, [R0, #88]
+  0x08005E00:  6DC1         LDR        R1, [R0, #92]
+  0x08005E02:  2204         MOVS       R2, #4
+  0x08005E04:  430A         ORRS       R2, R1
+  0x08005E06:  65C2         STR        R2, [R0, #92]
+  0x08005E08:  4770         BX         LR
+
+

Section .text.HAL_NVIC_SystemReset from PowerPro_lto.o, size=4, align=2

+
+
HAL_NVIC_SystemReset:
+  0x08005E0A:  F7FA FD8D    BL         __NVIC_SystemReset       ; 0x08000928
+
+

Section .text.UART_DMAReceiveCplt from PowerPro_lto.o, size=168, align=2

+
+
UART_DMAReceiveCplt:
+  0x08005E0E:  B5F0         PUSH       {R4-R7, LR}
+  0x08005E10:  B082         SUB        SP, SP, #8
+  0x08005E12:  6A82         LDR        R2, [R0, #40]
+  0x08005E14:  4611         MOV        R1, R2
+  0x08005E16:  315C         ADDS       R1, #92
+  0x08005E18:  6803         LDR        R3, [R0]
+  0x08005E1A:  681B         LDR        R3, [R3]
+  0x08005E1C:  069B         LSLS       R3, R3, #26
+  0x08005E1E:  D43A         BMI        .L1                      ; 0x08005E96
+  0x08005E20:  4614         MOV        R4, R2
+  0x08005E22:  348C         ADDS       R4, #140
+  0x08005E24:  2300         MOVS       R3, #0
+  0x08005E26:  804B         STRH       R3, [R1, #2]
+  0x08005E28:  F3EF 8310    MRS        R3, PRIMASK
+  0x08005E2C:  9300         STR        R3, [SP, #0]
+  0x08005E2E:  2301         MOVS       R3, #1
+  0x08005E30:  F383 8810    MSR        PRIMASK, R3
+  0x08005E34:  9001         STR        R0, [SP, #4]
+  0x08005E36:  021E         LSLS       R6, R3, #8
+  0x08005E38:  6817         LDR        R7, [R2]
+  0x08005E3A:  683D         LDR        R5, [R7]
+  0x08005E3C:  43B5         BICS       R5, R6
+  0x08005E3E:  603D         STR        R5, [R7]
+  0x08005E40:  9800         LDR        R0, [SP, #0]
+  0x08005E42:  F380 8810    MSR        PRIMASK, R0
+  0x08005E46:  F3EF 8010    MRS        R0, PRIMASK
+  0x08005E4A:  F383 8810    MSR        PRIMASK, R3
+  0x08005E4E:  6815         LDR        R5, [R2]
+  0x08005E50:  68AE         LDR        R6, [R5, #8]
+  0x08005E52:  439E         BICS       R6, R3
+  0x08005E54:  60AE         STR        R6, [R5, #8]
+  0x08005E56:  F380 8810    MSR        PRIMASK, R0
+  0x08005E5A:  F3EF 8010    MRS        R0, PRIMASK
+  0x08005E5E:  9000         STR        R0, [SP, #0]
+  0x08005E60:  F383 8810    MSR        PRIMASK, R3
+  0x08005E64:  6815         LDR        R5, [R2]
+  0x08005E66:  68AE         LDR        R6, [R5, #8]
+  0x08005E68:  2740         MOVS       R7, #64
+  0x08005E6A:  43BE         BICS       R6, R7
+  0x08005E6C:  60AE         STR        R6, [R5, #8]
+  0x08005E6E:  9801         LDR        R0, [SP, #4]
+  0x08005E70:  9D00         LDR        R5, [SP, #0]
+  0x08005E72:  F385 8810    MSR        PRIMASK, R5
+  0x08005E76:  2520         MOVS       R5, #32
+  0x08005E78:  6025         STR        R5, [R4]
+  0x08005E7A:  6ED4         LDR        R4, [R2, #108]
+  0x08005E7C:  2C01         CMP        R4, #1
+  0x08005E7E:  D10A         BNE        .L1                      ; 0x08005E96
+  0x08005E80:  F3EF 8610    MRS        R6, PRIMASK
+  0x08005E84:  F383 8810    MSR        PRIMASK, R3
+  0x08005E88:  6813         LDR        R3, [R2]
+  0x08005E8A:  681C         LDR        R4, [R3]
+  0x08005E8C:  2510         MOVS       R5, #16
+  0x08005E8E:  43AC         BICS       R4, R5
+  0x08005E90:  601C         STR        R4, [R3]
+  0x08005E92:  F386 8810    MSR        PRIMASK, R6
+
.L1:
+  0x08005E96:  2300         MOVS       R3, #0
+  0x08005E98:  6713         STR        R3, [R2, #112]
+  0x08005E9A:  6ED2         LDR        R2, [R2, #108]
+  0x08005E9C:  2A01         CMP        R2, #1
+  0x08005E9E:  D108         BNE        .L3                      ; 0x08005EB2
+  0x08005EA0:  804B         STRH       R3, [R1, #2]
+  0x08005EA2:  880A         LDRH       R2, [R1]
+  0x08005EA4:  6800         LDR        R0, [R0]
+  0x08005EA6:  6840         LDR        R0, [R0, #4]
+  0x08005EA8:  B283         UXTH       R3, R0
+  0x08005EAA:  4293         CMP        R3, R2
+  0x08005EAC:  D200         BCS        .L2                      ; 0x08005EB0
+  0x08005EAE:  8048         STRH       R0, [R1, #2]
+
.L2:
+  0x08005EB0:  8848         LDRH       R0, [R1, #2]
+
.L3:
+  0x08005EB2:  B002         ADD        SP, SP, #8
+  0x08005EB4:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.UART_DMARxHalfCplt from PowerPro_lto.o, size=36, align=2

+
+
UART_DMARxHalfCplt:
+  0x08005EB6:  6A81         LDR        R1, [R0, #40]
+  0x08005EB8:  2201         MOVS       R2, #1
+  0x08005EBA:  670A         STR        R2, [R1, #112]
+  0x08005EBC:  6ECA         LDR        R2, [R1, #108]
+  0x08005EBE:  2A01         CMP        R2, #1
+  0x08005EC0:  D10A         BNE        .L2                      ; 0x08005ED8
+  0x08005EC2:  315C         ADDS       R1, #92
+  0x08005EC4:  880A         LDRH       R2, [R1]
+  0x08005EC6:  0853         LSRS       R3, R2, #1
+  0x08005EC8:  804B         STRH       R3, [R1, #2]
+  0x08005ECA:  6800         LDR        R0, [R0]
+  0x08005ECC:  6840         LDR        R0, [R0, #4]
+  0x08005ECE:  B283         UXTH       R3, R0
+  0x08005ED0:  4293         CMP        R3, R2
+  0x08005ED2:  D800         BHI        .L1                      ; 0x08005ED6
+  0x08005ED4:  8048         STRH       R0, [R1, #2]
+
.L1:
+  0x08005ED6:  8848         LDRH       R0, [R1, #2]
+
.L2:
+  0x08005ED8:  4770         BX         LR
+
+

Section .text.UART_DMAAbortOnError from PowerPro_lto.o, size=16, align=2

+
+
UART_DMAAbortOnError:
+  0x08005EDA:  B580         PUSH       {R7, LR}
+  0x08005EDC:  6A80         LDR        R0, [R0, #40]
+  0x08005EDE:  215E         MOVS       R1, #94
+  0x08005EE0:  2200         MOVS       R2, #0
+  0x08005EE2:  5242         STRH       R2, [R0, R1]
+  0x08005EE4:  F7FE FB64    BL         HAL_UART_ErrorCallback   ; 0x080045B0
+  0x08005EE8:  BD80         POP        {R7, PC}
+
+

Section .text.Error_Handler from PowerPro_lto.o, size=4, align=2

+
+
Error_Handler:
+  0x08005EEA:  B672         CPSID      i
+
.L1:
+  0x08005EEC:  E7FE         B          .L1                      ; 0x08005EEC
+
+

Section .rodata.UARTPrescTable from PowerPro_lto.o, size=24, align=2

+
+
UARTPrescTable:
+  0x08005EEE:  01           DC.B       0x01                     ; '\x01'
+  0x08005EEF:  00           DC.B       0x00                     ; '\0'
+  0x08005EF0:  02           DC.B       0x02                     ; '\x02'
+  0x08005EF1:  00           DC.B       0x00                     ; '\0'
+  0x08005EF2:  04           DC.B       0x04                     ; '\x04'
+  0x08005EF3:  00           DC.B       0x00                     ; '\0'
+  0x08005EF4:  06           DC.B       0x06                     ; '\x06'
+  0x08005EF5:  00           DC.B       0x00                     ; '\0'
+  0x08005EF6:  08           DC.B       0x08                     ; '\b'
+  0x08005EF7:  00           DC.B       0x00                     ; '\0'
+  0x08005EF8:  0A           DC.B       0x0A                     ; '\n'
+  0x08005EF9:  00           DC.B       0x00                     ; '\0'
+  0x08005EFA:  0C           DC.B       0x0C                     ; '\x0C'
+  0x08005EFB:  00           DC.B       0x00                     ; '\0'
+  0x08005EFC:  10           DC.B       0x10                     ; '\x10'
+  0x08005EFD:  00           DC.B       0x00                     ; '\0'
+  0x08005EFE:  20           DC.B       0x20                     ; ' '
+  0x08005EFF:  00           DC.B       0x00                     ; '\0'
+  0x08005F00:  40           DC.B       0x40                     ; '@'
+  0x08005F01:  00           DC.B       0x00                     ; '\0'
+  0x08005F02:  80           DC.B       0x80                     ; '\x80'
+  0x08005F03:  00           DC.B       0x00                     ; '\0'
+  0x08005F04:  00           DC.B       0x00                     ; '\0'
+  0x08005F05:  01           DC.B       0x01                     ; '\x01'
+
+

Section .init.Reset_Handler from STM32C0xx_Startup.o, size=8, align=2

+
+
reset_handler:
+Reset_Handler:
+  0x08005F06:  F7FA FB75    BL         SystemInit               ; 0x080005F4
+  0x08005F0A:  F7FF F961    BL         _start                   ; 0x080051D0
+
+

Section .text.libc.__aeabi_ddiv from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=196, align=2

+
+
__aeabi_ddiv:
+  0x08005F0E:  B4F0         PUSH       {R4-R7}
+  0x08005F10:  2501         MOVS       R5, #1
+  0x08005F12:  07ED         LSLS       R5, R5, #31
+  0x08005F14:  000C         MOVS       R4, R1
+  0x08005F16:  405C         EORS       R4, R3
+  0x08005F18:  402C         ANDS       R4, R5
+  0x08005F1A:  46A4         MOV        R12, R4
+  0x08005F1C:  0AAE         LSRS       R6, R5, #10
+  0x08005F1E:  184C         ADDS       R4, R1, R1
+  0x08005F20:  18DF         ADDS       R7, R3, R3
+  0x08005F22:  42F4         CMN        R4, R6
+  0x08005F24:  D23D         BCS        .L8                      ; 0x08005FA2
+  0x08005F26:  42F7         CMN        R7, R6
+  0x08005F28:  D245         BCS        .L10                     ; 0x08005FB6
+  0x08005F2A:  0D64         LSRS       R4, R4, #21
+  0x08005F2C:  D04C         BEQ        .L12                     ; 0x08005FC8
+  0x08005F2E:  0D7F         LSRS       R7, R7, #21
+  0x08005F30:  D03C         BEQ        .L9                      ; 0x08005FAC
+  0x08005F32:  1BE4         SUBS       R4, R4, R7
+  0x08005F34:  02C9         LSLS       R1, R1, #11
+  0x08005F36:  4329         ORRS       R1, R5
+  0x08005F38:  0ACF         LSRS       R7, R1, #11
+  0x08005F3A:  02DB         LSLS       R3, R3, #11
+  0x08005F3C:  432B         ORRS       R3, R5
+  0x08005F3E:  0ADB         LSRS       R3, R3, #11
+  0x08005F40:  0006         MOVS       R6, R0
+  0x08005F42:  1AB6         SUBS       R6, R6, R2
+  0x08005F44:  419F         SBCS       R7, R3
+  0x08005F46:  D204         BCS        .L1                      ; 0x08005F52
+  0x08005F48:  1E64         SUBS       R4, R4, #1
+  0x08005F4A:  19B6         ADDS       R6, R6, R6
+  0x08005F4C:  417F         ADCS       R7, R7
+  0x08005F4E:  18B6         ADDS       R6, R6, R2
+  0x08005F50:  415F         ADCS       R7, R3
+
.L1:
+  0x08005F52:  1268         ASRS       R0, R5, #9
+  0x08005F54:  0D80         LSRS       R0, R0, #22
+  0x08005F56:  1824         ADDS       R4, R4, R0
+  0x08005F58:  DD38         BLE        .L13                     ; 0x08005FCC
+  0x08005F5A:  1800         ADDS       R0, R0, R0
+  0x08005F5C:  4284         CMP        R4, R0
+  0x08005F5E:  D825         BHI        .L9                      ; 0x08005FAC
+  0x08005F60:  0CE8         LSRS       R0, R5, #19
+  0x08005F62:  2100         MOVS       R1, #0
+
.L2:
+  0x08005F64:  19B6         ADDS       R6, R6, R6
+  0x08005F66:  417F         ADCS       R7, R7
+  0x08005F68:  1AB6         SUBS       R6, R6, R2
+  0x08005F6A:  419F         SBCS       R7, R3
+  0x08005F6C:  D303         BCC        .L3                      ; 0x08005F76
+  0x08005F6E:  4140         ADCS       R0, R0
+  0x08005F70:  4149         ADCS       R1, R1
+  0x08005F72:  D3F7         BCC        .L2                      ; 0x08005F64
+  0x08005F74:  E004         B          .L4                      ; 0x08005F80
+
.L3:
+  0x08005F76:  18B6         ADDS       R6, R6, R2
+  0x08005F78:  415F         ADCS       R7, R3
+  0x08005F7A:  1800         ADDS       R0, R0, R0
+  0x08005F7C:  4149         ADCS       R1, R1
+  0x08005F7E:  D3F1         BCC        .L2                      ; 0x08005F64
+
.L4:
+  0x08005F80:  0524         LSLS       R4, R4, #20
+  0x08005F82:  19B6         ADDS       R6, R6, R6
+  0x08005F84:  417F         ADCS       R7, R7
+  0x08005F86:  1AB6         SUBS       R6, R6, R2
+  0x08005F88:  419F         SBCS       R7, R3
+  0x08005F8A:  D305         BCC        .L5                      ; 0x08005F98
+  0x08005F8C:  4337         ORRS       R7, R6
+  0x08005F8E:  07C2         LSLS       R2, R0, #31
+  0x08005F90:  4317         ORRS       R7, R2
+  0x08005F92:  2200         MOVS       R2, #0
+  0x08005F94:  2F01         CMP        R7, #1
+  0x08005F96:  4150         ADCS       R0, R2
+
.L5:
+  0x08005F98:  4161         ADCS       R1, R4
+
.L6:
+  0x08005F9A:  4662         MOV        R2, R12
+  0x08005F9C:  4311         ORRS       R1, R2
+
.L7:
+  0x08005F9E:  BCF0         POP        {R4-R7}
+  0x08005FA0:  4770         BX         LR
+
.L8:
+  0x08005FA2:  D10C         BNE        .L11                     ; 0x08005FBE
+  0x08005FA4:  2800         CMP        R0, #0
+  0x08005FA6:  D10A         BNE        .L11                     ; 0x08005FBE
+  0x08005FA8:  42F7         CMN        R7, R6
+  0x08005FAA:  D208         BCS        .L11                     ; 0x08005FBE
+
.L9:
+  0x08005FAC:  2000         MOVS       R0, #0
+  0x08005FAE:  43C1         MVNS       R1, R0
+  0x08005FB0:  0D49         LSRS       R1, R1, #21
+  0x08005FB2:  0509         LSLS       R1, R1, #20
+  0x08005FB4:  E7F1         B          .L6                      ; 0x08005F9A
+
.L10:
+  0x08005FB6:  2A00         CMP        R2, #0
+  0x08005FB8:  D101         BNE        .L11                     ; 0x08005FBE
+  0x08005FBA:  42F7         CMN        R7, R6
+  0x08005FBC:  D006         BEQ        .L13                     ; 0x08005FCC
+
.L11:
+  0x08005FBE:  2000         MOVS       R0, #0
+  0x08005FC0:  43C1         MVNS       R1, R0
+  0x08005FC2:  0D09         LSRS       R1, R1, #20
+  0x08005FC4:  04C9         LSLS       R1, R1, #19
+  0x08005FC6:  E7EA         B          .L7                      ; 0x08005F9E
+
.L12:
+  0x08005FC8:  0D7F         LSRS       R7, R7, #21
+  0x08005FCA:  D0F8         BEQ        .L11                     ; 0x08005FBE
+
.L13:
+  0x08005FCC:  2000         MOVS       R0, #0
+  0x08005FCE:  4661         MOV        R1, R12
+  0x08005FD0:  E7E5         B          .L7                      ; 0x08005F9E
+
+

Section .text.libc.__aeabi_d2iz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=52, align=2

+
+
__aeabi_d2iz:
+  0x08005FD2:  46F4         MOV        R12, LR
+  0x08005FD4:  184A         ADDS       R2, R1, R1
+  0x08005FD6:  D205         BCS        .L2                      ; 0x08005FE4
+  0x08005FD8:  F7FF FDBE    BL         0x08005B58               ; 0x08005B59 = .text.libc.__aeabi_d2uiz+5
+  0x08005FDC:  D501         BPL        .L1                      ; 0x08005FE2
+  0x08005FDE:  17C0         ASRS       R0, R0, #31
+  0x08005FE0:  0840         LSRS       R0, R0, #1
+
.L1:
+  0x08005FE2:  4760         BX         R12
+
.L2:
+  0x08005FE4:  2301         MOVS       R3, #1
+  0x08005FE6:  055B         LSLS       R3, R3, #21
+  0x08005FE8:  42D3         CMN        R3, R2
+  0x08005FEA:  D206         BCS        .L5                      ; 0x08005FFA
+
.L3:
+  0x08005FEC:  F7FF FDB4    BL         0x08005B58               ; 0x08005B59 = .text.libc.__aeabi_d2uiz+5
+  0x08005FF0:  D501         BPL        .L4                      ; 0x08005FF6
+  0x08005FF2:  2001         MOVS       R0, #1
+  0x08005FF4:  07C0         LSLS       R0, R0, #31
+
.L4:
+  0x08005FF6:  4240         RSBS       R0, R0, #0
+  0x08005FF8:  4760         BX         R12
+
.L5:
+  0x08005FFA:  D101         BNE        .L6                      ; 0x08006000
+  0x08005FFC:  4200         TST        R0, R0
+  0x08005FFE:  D0F5         BEQ        .L3                      ; 0x08005FEC
+
.L6:
+  0x08006000:  17D0         ASRS       R0, R2, #31
+  0x08006002:  0840         LSRS       R0, R0, #1
+  0x08006004:  4770         BX         LR
+
+

Section .text.libc.__aeabi_f2uiz from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=36, align=2

+
+
__aeabi_f2uiz:
+  0x08006006:  0041         LSLS       R1, R0, #1
+  0x08006008:  D20D         BCS        .L2                      ; 0x08006026
+  0x0800600A:  0E09         LSRS       R1, R1, #24
+  0x0800600C:  397F         SUBS       R1, #127
+  0x0800600E:  D40A         BMI        .L2                      ; 0x08006026
+  0x08006010:  4249         RSBS       R1, R1, #0
+  0x08006012:  311F         ADDS       R1, #31
+  0x08006014:  D405         BMI        .L1                      ; 0x08006022
+  0x08006016:  0200         LSLS       R0, R0, #8
+  0x08006018:  2201         MOVS       R2, #1
+  0x0800601A:  07D2         LSLS       R2, R2, #31
+  0x0800601C:  4310         ORRS       R0, R2
+  0x0800601E:  40C8         LSRS       R0, R1
+  0x08006020:  4770         BX         LR
+
.L1:
+  0x08006022:  17C8         ASRS       R0, R1, #31
+  0x08006024:  4770         BX         LR
+
.L2:
+  0x08006026:  2000         MOVS       R0, #0
+  0x08006028:  4770         BX         LR
+
+

Section .text.libc.__aeabi_ui2d from floatasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=28, align=2

+
+
__aeabi_ui2d:
+  0x0800602A:  2242         MOVS       R2, #66
+  0x0800602C:  0112         LSLS       R2, R2, #4
+  0x0800602E:  1ED2         SUBS       R2, R2, #3
+  0x08006030:  0001         MOVS       R1, R0
+  0x08006032:  D007         BEQ        .L3                      ; 0x08006044
+  0x08006034:  D402         BMI        .L2                      ; 0x0800603C
+
.L1:
+  0x08006036:  1E52         SUBS       R2, R2, #1
+  0x08006038:  1800         ADDS       R0, R0, R0
+  0x0800603A:  D5FC         BPL        .L1                      ; 0x08006036
+
.L2:
+  0x0800603C:  0512         LSLS       R2, R2, #20
+  0x0800603E:  0AC3         LSRS       R3, R0, #11
+  0x08006040:  0540         LSLS       R0, R0, #21
+  0x08006042:  1899         ADDS       R1, R3, R2
+
.L3:
+  0x08006044:  4770         BX         LR
+
+

Section .text.libc.__aeabi_idiv from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=64, align=2

+
+
__aeabi_idiv:
+  0x08006046:  17CA         ASRS       R2, R1, #31
+  0x08006048:  4051         EORS       R1, R2
+  0x0800604A:  1A8B         SUBS       R3, R1, R2
+  0x0800604C:  D017         BEQ        .L6                      ; 0x0800607E
+  0x0800604E:  17C1         ASRS       R1, R0, #31
+  0x08006050:  404A         EORS       R2, R1
+  0x08006052:  4694         MOV        R12, R2
+  0x08006054:  4048         EORS       R0, R1
+  0x08006056:  1A41         SUBS       R1, R0, R1
+  0x08006058:  0848         LSRS       R0, R1, #1
+  0x0800605A:  001A         MOVS       R2, R3
+  0x0800605C:  E000         B          .L2                      ; 0x08006060
+
.L1:
+  0x0800605E:  0052         LSLS       R2, R2, #1
+
.L2:
+  0x08006060:  4282         CMP        R2, R0
+  0x08006062:  D9FC         BLS        .L1                      ; 0x0800605E
+  0x08006064:  2000         MOVS       R0, #0
+  0x08006066:  E000         B          .L4                      ; 0x0800606A
+
.L3:
+  0x08006068:  0852         LSRS       R2, R2, #1
+
.L4:
+  0x0800606A:  4291         CMP        R1, R2
+  0x0800606C:  D300         BCC        .L5                      ; 0x08006070
+  0x0800606E:  1A89         SUBS       R1, R1, R2
+
.L5:
+  0x08006070:  4140         ADCS       R0, R0
+  0x08006072:  429A         CMP        R2, R3
+  0x08006074:  D1F8         BNE        .L3                      ; 0x08006068
+  0x08006076:  4662         MOV        R2, R12
+  0x08006078:  4050         EORS       R0, R2
+  0x0800607A:  1A80         SUBS       R0, R0, R2
+  0x0800607C:  4770         BX         LR
+
.L6:
+  0x0800607E:  B510         PUSH       {R4, LR}
+  0x08006080:  F7FF FDA5    BL         __aeabi_idiv0            ; 0x08005BCE
+  0x08006084:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__aeabi_uidiv from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=56, align=2

+
+
__aeabi_uidiv:
+  0x08006086:  000A         MOVS       R2, R1
+  0x08006088:  D015         BEQ        .L8                      ; 0x080060B6
+  0x0800608A:  0003         MOVS       R3, R0
+  0x0800608C:  0840         LSRS       R0, R0, #1
+  0x0800608E:  E000         B          .L2                      ; 0x08006092
+
.L1:
+  0x08006090:  0052         LSLS       R2, R2, #1
+
.L2:
+  0x08006092:  4282         CMP        R2, R0
+  0x08006094:  D9FC         BLS        .L1                      ; 0x08006090
+  0x08006096:  2000         MOVS       R0, #0
+  0x08006098:  E000         B          .L4                      ; 0x0800609C
+
.L3:
+  0x0800609A:  0852         LSRS       R2, R2, #1
+
.L4:
+  0x0800609C:  1A9B         SUBS       R3, R3, R2
+  0x0800609E:  D306         BCC        .L7                      ; 0x080060AE
+
.L5:
+  0x080060A0:  4140         ADCS       R0, R0
+  0x080060A2:  428A         CMP        R2, R1
+  0x080060A4:  D1F9         BNE        .L3                      ; 0x0800609A
+  0x080060A6:  4770         BX         LR
+
.L6:
+  0x080060A8:  0852         LSRS       R2, R2, #1
+  0x080060AA:  189B         ADDS       R3, R3, R2
+  0x080060AC:  D2F8         BCS        .L5                      ; 0x080060A0
+
.L7:
+  0x080060AE:  1800         ADDS       R0, R0, R0
+  0x080060B0:  428A         CMP        R2, R1
+  0x080060B2:  D1F9         BNE        .L6                      ; 0x080060A8
+  0x080060B4:  4770         BX         LR
+
.L8:
+  0x080060B6:  B510         PUSH       {R4, LR}
+  0x080060B8:  F7FF FD89    BL         __aeabi_idiv0            ; 0x08005BCE
+  0x080060BC:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__aeabi_uldivmod from intasmops_arm.o (libc_v6m_t_le_eabi_small.a), size=136, align=2

+
+
__aeabi_uldivmod:
+  0x080060BE:  B470         PUSH       {R4-R6}
+  0x080060C0:  2400         MOVS       R4, #0
+  0x080060C2:  2501         MOVS       R5, #1
+  0x080060C4:  07ED         LSLS       R5, R5, #31
+  0x080060C6:  2B00         CMP        R3, #0
+  0x080060C8:  D107         BNE        .L1                      ; 0x080060DA
+  0x080060CA:  2900         CMP        R1, #0
+  0x080060CC:  D005         BEQ        .L1                      ; 0x080060DA
+  0x080060CE:  4283         CMP        R3, R0
+  0x080060D0:  D203         BCS        .L1                      ; 0x080060DA
+  0x080060D2:  0013         MOVS       R3, R2
+  0x080060D4:  2200         MOVS       R2, #0
+  0x080060D6:  002C         MOVS       R4, R5
+  0x080060D8:  2500         MOVS       R5, #0
+
.L1:
+  0x080060DA:  2600         MOVS       R6, #0
+
.L2:
+  0x080060DC:  19A4         ADDS       R4, R4, R6
+  0x080060DE:  4299         CMP        R1, R3
+  0x080060E0:  D100         BNE        .L3                      ; 0x080060E4
+  0x080060E2:  4290         CMP        R0, R2
+
.L3:
+  0x080060E4:  D912         BLS        .L6                      ; 0x0800610C
+  0x080060E6:  1892         ADDS       R2, R2, R2
+  0x080060E8:  415B         ADCS       R3, R3
+  0x080060EA:  D203         BCS        .L4                      ; 0x080060F4
+  0x080060EC:  07EE         LSLS       R6, R5, #31
+  0x080060EE:  086D         LSRS       R5, R5, #1
+  0x080060F0:  0864         LSRS       R4, R4, #1
+  0x080060F2:  E7F3         B          .L2                      ; 0x080060DC
+
.L4:
+  0x080060F4:  07DE         LSLS       R6, R3, #31
+  0x080060F6:  085B         LSRS       R3, R3, #1
+  0x080060F8:  0852         LSRS       R2, R2, #1
+  0x080060FA:  1992         ADDS       R2, R2, R6
+  0x080060FC:  2601         MOVS       R6, #1
+  0x080060FE:  07F6         LSLS       R6, R6, #31
+  0x08006100:  199B         ADDS       R3, R3, R6
+  0x08006102:  E003         B          .L6                      ; 0x0800610C
+
.L5:
+  0x08006104:  07DE         LSLS       R6, R3, #31
+  0x08006106:  085B         LSRS       R3, R3, #1
+  0x08006108:  0852         LSRS       R2, R2, #1
+  0x0800610A:  1992         ADDS       R2, R2, R6
+
.L6:
+  0x0800610C:  1A80         SUBS       R0, R0, R2
+  0x0800610E:  4199         SBCS       R1, R3
+  0x08006110:  D303         BCC        .L7                      ; 0x0800611A
+  0x08006112:  4164         ADCS       R4, R4
+  0x08006114:  416D         ADCS       R5, R5
+  0x08006116:  D3F5         BCC        .L5                      ; 0x08006104
+  0x08006118:  E00F         B          .L9                      ; 0x0800613A
+
.L7:
+  0x0800611A:  1924         ADDS       R4, R4, R4
+  0x0800611C:  416D         ADCS       R5, R5
+  0x0800611E:  D20A         BCS        .L8                      ; 0x08006136
+  0x08006120:  07DE         LSLS       R6, R3, #31
+  0x08006122:  085B         LSRS       R3, R3, #1
+  0x08006124:  0852         LSRS       R2, R2, #1
+  0x08006126:  1992         ADDS       R2, R2, R6
+  0x08006128:  1880         ADDS       R0, R0, R2
+  0x0800612A:  4159         ADCS       R1, R3
+  0x0800612C:  D3F5         BCC        .L7                      ; 0x0800611A
+  0x0800612E:  4164         ADCS       R4, R4
+  0x08006130:  416D         ADCS       R5, R5
+  0x08006132:  D3E7         BCC        .L5                      ; 0x08006104
+  0x08006134:  E001         B          .L9                      ; 0x0800613A
+
.L8:
+  0x08006136:  1880         ADDS       R0, R0, R2
+  0x08006138:  4159         ADCS       R1, R3
+
.L9:
+  0x0800613A:  0002         MOVS       R2, R0
+  0x0800613C:  000B         MOVS       R3, R1
+  0x0800613E:  0020         MOVS       R0, R4
+  0x08006140:  0029         MOVS       R1, R5
+  0x08006142:  BC70         POP        {R4-R6}
+  0x08006144:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_stream_write from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=2

+
+
__SEGGER_RTL_stream_write:
+  0x08006146:  B510         PUSH       {R4, LR}
+  0x08006148:  460C         MOV        R4, R1
+  0x0800614A:  6A43         LDR        R3, [R0, #36]
+  0x0800614C:  2101         MOVS       R1, #1
+  0x0800614E:  4620         MOV        R0, R4
+  0x08006150:  F7FF FBC7    BL         fwrite                   ; 0x080058E2
+  0x08006154:  BD10         POP        {R4, PC}
+
+

Section .text.libc.__SEGGER_RTL_X_file_bufsize from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=2

+
+
__SEGGER_RTL_X_file_bufsize:
+  0x08006156:  2040         MOVS       R0, #64
+  0x08006158:  4770         BX         LR
+
+

Section .text.libc._WriteBlocking from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=88, align=2

+
+
_WriteBlocking:
+  0x0800615A:  B5F0         PUSH       {R4-R7, LR}
+  0x0800615C:  B083         SUB        SP, SP, #12
+  0x0800615E:  4617         MOV        R7, R2
+  0x08006160:  4606         MOV        R6, R0
+  0x08006162:  68C5         LDR        R5, [R0, #12]
+  0x08006164:  2000         MOVS       R0, #0
+
.L1:
+  0x08006166:  9001         STR        R0, [SP, #4]
+  0x08006168:  6933         LDR        R3, [R6, #16]
+  0x0800616A:  42AB         CMP        R3, R5
+  0x0800616C:  68B0         LDR        R0, [R6, #8]
+  0x0800616E:  D902         BLS        .L2                      ; 0x08006176
+  0x08006170:  43EA         MVNS       R2, R5
+  0x08006172:  189C         ADDS       R4, R3, R2
+  0x08006174:  E002         B          .L3                      ; 0x0800617C
+
.L2:
+  0x08006176:  43EA         MVNS       R2, R5
+  0x08006178:  189A         ADDS       R2, R3, R2
+  0x0800617A:  1814         ADDS       R4, R2, R0
+
.L3:
+  0x0800617C:  1B40         SUBS       R0, R0, R5
+  0x0800617E:  4284         CMP        R4, R0
+  0x08006180:  D300         BCC        .L4                      ; 0x08006184
+  0x08006182:  4604         MOV        R4, R0
+
.L4:
+  0x08006184:  42BC         CMP        R4, R7
+  0x08006186:  D300         BCC        .L5                      ; 0x0800618A
+  0x08006188:  463C         MOV        R4, R7
+
.L5:
+  0x0800618A:  6870         LDR        R0, [R6, #4]
+  0x0800618C:  1940         ADDS       R0, R0, R5
+  0x0800618E:  9102         STR        R1, [SP, #8]
+  0x08006190:  4622         MOV        R2, R4
+  0x08006192:  F7FF FDD2    BL         memcpy                   ; 0x08005D3A
+  0x08006196:  1965         ADDS       R5, R4, R5
+  0x08006198:  68B0         LDR        R0, [R6, #8]
+  0x0800619A:  4285         CMP        R5, R0
+  0x0800619C:  D100         BNE        .L6                      ; 0x080061A0
+  0x0800619E:  2500         MOVS       R5, #0
+
.L6:
+  0x080061A0:  9801         LDR        R0, [SP, #4]
+  0x080061A2:  60F5         STR        R5, [R6, #12]
+  0x080061A4:  9902         LDR        R1, [SP, #8]
+  0x080061A6:  1909         ADDS       R1, R1, R4
+  0x080061A8:  1820         ADDS       R0, R4, R0
+  0x080061AA:  1B3F         SUBS       R7, R7, R4
+  0x080061AC:  D1DB         BNE        .L1                      ; 0x08006166
+  0x080061AE:  B003         ADD        SP, SP, #12
+  0x080061B0:  BDF0         POP        {R4-R7, PC}
+
+

Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_v6m_t_le_eabi_small.a), size=20, align=2

+
+
__aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x080061B2:  2200         MOVS       R2, #0
+
__aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x080061B4:  000B         MOVS       R3, R1
+  0x080061B6:  0011         MOVS       R1, R2
+  0x080061B8:  001A         MOVS       R2, R3
+
memset:
+  0x080061BA:  2A00         CMP        R2, #0
+  0x080061BC:  D002         BEQ        .L2                      ; 0x080061C4
+
.L1:
+  0x080061BE:  1E52         SUBS       R2, R2, #1
+  0x080061C0:  5481         STRB       R1, [R0, R2]
+  0x080061C2:  D1FC         BNE        .L1                      ; 0x080061BE
+
.L2:
+  0x080061C4:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_wctomb from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=16, align=2

+
+
__SEGGER_RTL_ascii_wctomb:
+  0x080061C6:  4602         MOV        R2, R0
+  0x080061C8:  2001         MOVS       R0, #1
+  0x080061CA:  297F         CMP        R1, #127
+  0x080061CC:  D901         BLS        .L1                      ; 0x080061D2
+  0x080061CE:  43C0         MVNS       R0, R0
+  0x080061D0:  4770         BX         LR
+
.L1:
+  0x080061D2:  7011         STRB       R1, [R2]
+  0x080061D4:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_toupper from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=2

+
+
__SEGGER_RTL_ascii_toupper:
+  0x080061D6:  4601         MOV        R1, R0
+  0x080061D8:  3961         SUBS       R1, #97
+  0x080061DA:  291A         CMP        R1, #26
+  0x080061DC:  D200         BCS        .L1                      ; 0x080061E0
+  0x080061DE:  3820         SUBS       R0, #32
+
.L1:
+  0x080061E0:  4770         BX         LR
+
+

Section .text.libc.__SEGGER_RTL_ascii_towupper from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=12, align=2

+
+
__SEGGER_RTL_ascii_towupper:
+  0x080061E2:  4601         MOV        R1, R0
+  0x080061E4:  3961         SUBS       R1, #97
+  0x080061E6:  291A         CMP        R1, #26
+  0x080061E8:  D200         BCS        .L1                      ; 0x080061EC
+  0x080061EA:  3820         SUBS       R0, #32
+
.L1:
+  0x080061EC:  4770         BX         LR
+
+

Section .rodata..Lstr.99 from PowerPro_lto.o, size=19, align=1

+
+  0x080061EE:  73           DC.B       0x73                     ; 's'
+  0x080061EF:  65           DC.B       0x65                     ; 'e'
+  0x080061F0:  74           DC.B       0x74                     ; 't'
+  0x080061F1:  7A           DC.B       0x7A                     ; 'z'
+  0x080061F2:  65           DC.B       0x65                     ; 'e'
+  0x080061F3:  20           DC.B       0x20                     ; ' '
+  0x080061F4:  6F           DC.B       0x6F                     ; 'o'
+  0x080061F5:  70           DC.B       0x70                     ; 'p'
+  0x080061F6:  74           DC.B       0x74                     ; 't'
+  0x080061F7:  69           DC.B       0x69                     ; 'i'
+  0x080061F8:  6F           DC.B       0x6F                     ; 'o'
+  0x080061F9:  6E           DC.B       0x6E                     ; 'n'
+  0x080061FA:  20           DC.B       0x20                     ; ' '
+  0x080061FB:  62           DC.B       0x62                     ; 'b'
+  0x080061FC:  79           DC.B       0x79                     ; 'y'
+  0x080061FD:  74           DC.B       0x74                     ; 't'
+  0x080061FE:  65           DC.B       0x65                     ; 'e'
+  0x080061FF:  0D           DC.B       0x0D                     ; '\r'
+  0x08006200:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.9 from PowerPro_lto.o, size=59, align=1

+
+  0x08006201:  4E           DC.B       0x4E                     ; 'N'
+  0x08006202:  65           DC.B       0x65                     ; 'e'
+  0x08006203:  75           DC.B       0x75                     ; 'u'
+  0x08006204:  65           DC.B       0x65                     ; 'e'
+  0x08006205:  20           DC.B       0x20                     ; ' '
+  0x08006206:  56           DC.B       0x56                     ; 'V'
+  0x08006207:  65           DC.B       0x65                     ; 'e'
+  0x08006208:  72           DC.B       0x72                     ; 'r'
+  0x08006209:  73           DC.B       0x73                     ; 's'
+  0x0800620A:  69           DC.B       0x69                     ; 'i'
+  0x0800620B:  6F           DC.B       0x6F                     ; 'o'
+  0x0800620C:  6E           DC.B       0x6E                     ; 'n'
+  0x0800620D:  20           DC.B       0x20                     ; ' '
+  0x0800620E:  50           DC.B       0x50                     ; 'P'
+  0x0800620F:  61           DC.B       0x61                     ; 'a'
+  0x08006210:  72           DC.B       0x72                     ; 'r'
+  0x08006211:  61           DC.B       0x61                     ; 'a'
+  0x08006212:  6D           DC.B       0x6D                     ; 'm'
+  0x08006213:  65           DC.B       0x65                     ; 'e'
+  0x08006214:  74           DC.B       0x74                     ; 't'
+  0x08006215:  65           DC.B       0x65                     ; 'e'
+  0x08006216:  72           DC.B       0x72                     ; 'r'
+  0x08006217:  20           DC.B       0x20                     ; ' '
+  0x08006218:  65           DC.B       0x65                     ; 'e'
+  0x08006219:  72           DC.B       0x72                     ; 'r'
+  0x0800621A:  6B           DC.B       0x6B                     ; 'k'
+  0x0800621B:  61           DC.B       0x61                     ; 'a'
+  0x0800621C:  6E           DC.B       0x6E                     ; 'n'
+  0x0800621D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800621E:  74           DC.B       0x74                     ; 't'
+  0x0800621F:  2C           DC.B       0x2C                     ; ','
+  0x08006220:  20           DC.B       0x20                     ; ' '
+  0x08006221:  73           DC.B       0x73                     ; 's'
+  0x08006222:  63           DC.B       0x63                     ; 'c'
+  0x08006223:  68           DC.B       0x68                     ; 'h'
+  0x08006224:  72           DC.B       0x72                     ; 'r'
+  0x08006225:  65           DC.B       0x65                     ; 'e'
+  0x08006226:  69           DC.B       0x69                     ; 'i'
+  0x08006227:  62           DC.B       0x62                     ; 'b'
+  0x08006228:  65           DC.B       0x65                     ; 'e'
+  0x08006229:  20           DC.B       0x20                     ; ' '
+  0x0800622A:  57           DC.B       0x57                     ; 'W'
+  0x0800622B:  65           DC.B       0x65                     ; 'e'
+  0x0800622C:  72           DC.B       0x72                     ; 'r'
+  0x0800622D:  6B           DC.B       0x6B                     ; 'k'
+  0x0800622E:  73           DC.B       0x73                     ; 's'
+  0x0800622F:  65           DC.B       0x65                     ; 'e'
+  0x08006230:  69           DC.B       0x69                     ; 'i'
+  0x08006231:  6E           DC.B       0x6E                     ; 'n'
+  0x08006232:  73           DC.B       0x73                     ; 's'
+  0x08006233:  74           DC.B       0x74                     ; 't'
+  0x08006234:  65           DC.B       0x65                     ; 'e'
+  0x08006235:  6C           DC.B       0x6C                     ; 'l'
+  0x08006236:  6C           DC.B       0x6C                     ; 'l'
+  0x08006237:  75           DC.B       0x75                     ; 'u'
+  0x08006238:  6E           DC.B       0x6E                     ; 'n'
+  0x08006239:  67           DC.B       0x67                     ; 'g'
+  0x0800623A:  0D           DC.B       0x0D                     ; '\r'
+  0x0800623B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.7 from PowerPro_lto.o, size=39, align=1

+
+  0x0800623C:  55           DC.B       0x55                     ; 'U'
+  0x0800623D:  61           DC.B       0x61                     ; 'a'
+  0x0800623E:  72           DC.B       0x72                     ; 'r'
+  0x0800623F:  74           DC.B       0x74                     ; 't'
+  0x08006240:  20           DC.B       0x20                     ; ' '
+  0x08006241:  45           DC.B       0x45                     ; 'E'
+  0x08006242:  72           DC.B       0x72                     ; 'r'
+  0x08006243:  72           DC.B       0x72                     ; 'r'
+  0x08006244:  6F           DC.B       0x6F                     ; 'o'
+  0x08006245:  72           DC.B       0x72                     ; 'r'
+  0x08006246:  20           DC.B       0x20                     ; ' '
+  0x08006247:  62           DC.B       0x62                     ; 'b'
+  0x08006248:  65           DC.B       0x65                     ; 'e'
+  0x08006249:  69           DC.B       0x69                     ; 'i'
+  0x0800624A:  20           DC.B       0x20                     ; ' '
+  0x0800624B:  6E           DC.B       0x6E                     ; 'n'
+  0x0800624C:  65           DC.B       0x65                     ; 'e'
+  0x0800624D:  75           DC.B       0x75                     ; 'u'
+  0x0800624E:  73           DC.B       0x73                     ; 's'
+  0x0800624F:  74           DC.B       0x74                     ; 't'
+  0x08006250:  61           DC.B       0x61                     ; 'a'
+  0x08006251:  72           DC.B       0x72                     ; 'r'
+  0x08006252:  74           DC.B       0x74                     ; 't'
+  0x08006253:  20           DC.B       0x20                     ; ' '
+  0x08006254:  6E           DC.B       0x6E                     ; 'n'
+  0x08006255:  61           DC.B       0x61                     ; 'a'
+  0x08006256:  63           DC.B       0x63                     ; 'c'
+  0x08006257:  68           DC.B       0x68                     ; 'h'
+  0x08006258:  20           DC.B       0x20                     ; ' '
+  0x08006259:  46           DC.B       0x46                     ; 'F'
+  0x0800625A:  65           DC.B       0x65                     ; 'e'
+  0x0800625B:  68           DC.B       0x68                     ; 'h'
+  0x0800625C:  6C           DC.B       0x6C                     ; 'l'
+  0x0800625D:  65           DC.B       0x65                     ; 'e'
+  0x0800625E:  72           DC.B       0x72                     ; 'r'
+  0x0800625F:  20           DC.B       0x20                     ; ' '
+  0x08006260:  0A           DC.B       0x0A                     ; '\n'
+  0x08006261:  0D           DC.B       0x0D                     ; '\r'
+  0x08006262:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18 from PowerPro_lto.o, size=35, align=1

+
+  0x08006263:  4E           DC.B       0x4E                     ; 'N'
+  0x08006264:  45           DC.B       0x45                     ; 'E'
+  0x08006265:  57           DC.B       0x57                     ; 'W'
+  0x08006266:  5F           DC.B       0x5F                     ; '_'
+  0x08006267:  53           DC.B       0x53                     ; 'S'
+  0x08006268:  54           DC.B       0x54                     ; 'T'
+  0x08006269:  41           DC.B       0x41                     ; 'A'
+  0x0800626A:  54           DC.B       0x54                     ; 'T'
+  0x0800626B:  45           DC.B       0x45                     ; 'E'
+  0x0800626C:  3A           DC.B       0x3A                     ; ':'
+  0x0800626D:  20           DC.B       0x20                     ; ' '
+  0x0800626E:  4C           DC.B       0x4C                     ; 'L'
+  0x0800626F:  56           DC.B       0x56                     ; 'V'
+  0x08006270:  50           DC.B       0x50                     ; 'P'
+  0x08006271:  5F           DC.B       0x5F                     ; '_'
+  0x08006272:  41           DC.B       0x41                     ; 'A'
+  0x08006273:  75           DC.B       0x75                     ; 'u'
+  0x08006274:  74           DC.B       0x74                     ; 't'
+  0x08006275:  6F           DC.B       0x6F                     ; 'o'
+  0x08006276:  20           DC.B       0x20                     ; ' '
+  0x08006277:  4F           DC.B       0x4F                     ; 'O'
+  0x08006278:  6E           DC.B       0x6E                     ; 'n'
+  0x08006279:  2C           DC.B       0x2C                     ; ','
+  0x0800627A:  20           DC.B       0x20                     ; ' '
+  0x0800627B:  52           DC.B       0x52                     ; 'R'
+  0x0800627C:  65           DC.B       0x65                     ; 'e'
+  0x0800627D:  6C           DC.B       0x6C                     ; 'l'
+  0x0800627E:  61           DC.B       0x61                     ; 'a'
+  0x0800627F:  69           DC.B       0x69                     ; 'i'
+  0x08006280:  73           DC.B       0x73                     ; 's'
+  0x08006281:  20           DC.B       0x20                     ; ' '
+  0x08006282:  6F           DC.B       0x6F                     ; 'o'
+  0x08006283:  66           DC.B       0x66                     ; 'f'
+  0x08006284:  66           DC.B       0x66                     ; 'f'
+  0x08006285:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22 from PowerPro_lto.o, size=19, align=1

+
+  0x08006286:  4E           DC.B       0x4E                     ; 'N'
+  0x08006287:  45           DC.B       0x45                     ; 'E'
+  0x08006288:  57           DC.B       0x57                     ; 'W'
+  0x08006289:  5F           DC.B       0x5F                     ; '_'
+  0x0800628A:  53           DC.B       0x53                     ; 'S'
+  0x0800628B:  54           DC.B       0x54                     ; 'T'
+  0x0800628C:  41           DC.B       0x41                     ; 'A'
+  0x0800628D:  54           DC.B       0x54                     ; 'T'
+  0x0800628E:  45           DC.B       0x45                     ; 'E'
+  0x0800628F:  3A           DC.B       0x3A                     ; ':'
+  0x08006290:  20           DC.B       0x20                     ; ' '
+  0x08006291:  4C           DC.B       0x4C                     ; 'L'
+  0x08006292:  56           DC.B       0x56                     ; 'V'
+  0x08006293:  50           DC.B       0x50                     ; 'P'
+  0x08006294:  5F           DC.B       0x5F                     ; '_'
+  0x08006295:  4F           DC.B       0x4F                     ; 'O'
+  0x08006296:  46           DC.B       0x46                     ; 'F'
+  0x08006297:  46           DC.B       0x46                     ; 'F'
+  0x08006298:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18.130 from PowerPro_lto.o, size=39, align=1

+
+  0x08006299:  4E           DC.B       0x4E                     ; 'N'
+  0x0800629A:  45           DC.B       0x45                     ; 'E'
+  0x0800629B:  57           DC.B       0x57                     ; 'W'
+  0x0800629C:  5F           DC.B       0x5F                     ; '_'
+  0x0800629D:  53           DC.B       0x53                     ; 'S'
+  0x0800629E:  54           DC.B       0x54                     ; 'T'
+  0x0800629F:  41           DC.B       0x41                     ; 'A'
+  0x080062A0:  54           DC.B       0x54                     ; 'T'
+  0x080062A1:  45           DC.B       0x45                     ; 'E'
+  0x080062A2:  3A           DC.B       0x3A                     ; ':'
+  0x080062A3:  20           DC.B       0x20                     ; ' '
+  0x080062A4:  4C           DC.B       0x4C                     ; 'L'
+  0x080062A5:  56           DC.B       0x56                     ; 'V'
+  0x080062A6:  50           DC.B       0x50                     ; 'P'
+  0x080062A7:  5F           DC.B       0x5F                     ; '_'
+  0x080062A8:  4F           DC.B       0x4F                     ; 'O'
+  0x080062A9:  56           DC.B       0x56                     ; 'V'
+  0x080062AA:  50           DC.B       0x50                     ; 'P'
+  0x080062AB:  5F           DC.B       0x5F                     ; '_'
+  0x080062AC:  41           DC.B       0x41                     ; 'A'
+  0x080062AD:  75           DC.B       0x75                     ; 'u'
+  0x080062AE:  74           DC.B       0x74                     ; 't'
+  0x080062AF:  6F           DC.B       0x6F                     ; 'o'
+  0x080062B0:  20           DC.B       0x20                     ; ' '
+  0x080062B1:  4F           DC.B       0x4F                     ; 'O'
+  0x080062B2:  6E           DC.B       0x6E                     ; 'n'
+  0x080062B3:  2C           DC.B       0x2C                     ; ','
+  0x080062B4:  20           DC.B       0x20                     ; ' '
+  0x080062B5:  52           DC.B       0x52                     ; 'R'
+  0x080062B6:  65           DC.B       0x65                     ; 'e'
+  0x080062B7:  6C           DC.B       0x6C                     ; 'l'
+  0x080062B8:  61           DC.B       0x61                     ; 'a'
+  0x080062B9:  69           DC.B       0x69                     ; 'i'
+  0x080062BA:  73           DC.B       0x73                     ; 's'
+  0x080062BB:  20           DC.B       0x20                     ; ' '
+  0x080062BC:  6F           DC.B       0x6F                     ; 'o'
+  0x080062BD:  66           DC.B       0x66                     ; 'f'
+  0x080062BE:  66           DC.B       0x66                     ; 'f'
+  0x080062BF:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.133 from PowerPro_lto.o, size=23, align=1

+
+  0x080062C0:  4E           DC.B       0x4E                     ; 'N'
+  0x080062C1:  45           DC.B       0x45                     ; 'E'
+  0x080062C2:  57           DC.B       0x57                     ; 'W'
+  0x080062C3:  5F           DC.B       0x5F                     ; '_'
+  0x080062C4:  53           DC.B       0x53                     ; 'S'
+  0x080062C5:  54           DC.B       0x54                     ; 'T'
+  0x080062C6:  41           DC.B       0x41                     ; 'A'
+  0x080062C7:  54           DC.B       0x54                     ; 'T'
+  0x080062C8:  45           DC.B       0x45                     ; 'E'
+  0x080062C9:  3A           DC.B       0x3A                     ; ':'
+  0x080062CA:  20           DC.B       0x20                     ; ' '
+  0x080062CB:  4C           DC.B       0x4C                     ; 'L'
+  0x080062CC:  56           DC.B       0x56                     ; 'V'
+  0x080062CD:  50           DC.B       0x50                     ; 'P'
+  0x080062CE:  5F           DC.B       0x5F                     ; '_'
+  0x080062CF:  4F           DC.B       0x4F                     ; 'O'
+  0x080062D0:  56           DC.B       0x56                     ; 'V'
+  0x080062D1:  50           DC.B       0x50                     ; 'P'
+  0x080062D2:  5F           DC.B       0x5F                     ; '_'
+  0x080062D3:  4F           DC.B       0x4F                     ; 'O'
+  0x080062D4:  46           DC.B       0x46                     ; 'F'
+  0x080062D5:  46           DC.B       0x46                     ; 'F'
+  0x080062D6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.18.153 from PowerPro_lto.o, size=35, align=1

+
+  0x080062D7:  4E           DC.B       0x4E                     ; 'N'
+  0x080062D8:  45           DC.B       0x45                     ; 'E'
+  0x080062D9:  57           DC.B       0x57                     ; 'W'
+  0x080062DA:  5F           DC.B       0x5F                     ; '_'
+  0x080062DB:  53           DC.B       0x53                     ; 'S'
+  0x080062DC:  54           DC.B       0x54                     ; 'T'
+  0x080062DD:  41           DC.B       0x41                     ; 'A'
+  0x080062DE:  54           DC.B       0x54                     ; 'T'
+  0x080062DF:  45           DC.B       0x45                     ; 'E'
+  0x080062E0:  3A           DC.B       0x3A                     ; ':'
+  0x080062E1:  20           DC.B       0x20                     ; ' '
+  0x080062E2:  4F           DC.B       0x4F                     ; 'O'
+  0x080062E3:  56           DC.B       0x56                     ; 'V'
+  0x080062E4:  50           DC.B       0x50                     ; 'P'
+  0x080062E5:  5F           DC.B       0x5F                     ; '_'
+  0x080062E6:  41           DC.B       0x41                     ; 'A'
+  0x080062E7:  75           DC.B       0x75                     ; 'u'
+  0x080062E8:  74           DC.B       0x74                     ; 't'
+  0x080062E9:  6F           DC.B       0x6F                     ; 'o'
+  0x080062EA:  20           DC.B       0x20                     ; ' '
+  0x080062EB:  4F           DC.B       0x4F                     ; 'O'
+  0x080062EC:  6E           DC.B       0x6E                     ; 'n'
+  0x080062ED:  2C           DC.B       0x2C                     ; ','
+  0x080062EE:  20           DC.B       0x20                     ; ' '
+  0x080062EF:  52           DC.B       0x52                     ; 'R'
+  0x080062F0:  65           DC.B       0x65                     ; 'e'
+  0x080062F1:  6C           DC.B       0x6C                     ; 'l'
+  0x080062F2:  61           DC.B       0x61                     ; 'a'
+  0x080062F3:  69           DC.B       0x69                     ; 'i'
+  0x080062F4:  73           DC.B       0x73                     ; 's'
+  0x080062F5:  20           DC.B       0x20                     ; ' '
+  0x080062F6:  6F           DC.B       0x6F                     ; 'o'
+  0x080062F7:  66           DC.B       0x66                     ; 'f'
+  0x080062F8:  66           DC.B       0x66                     ; 'f'
+  0x080062F9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.156 from PowerPro_lto.o, size=19, align=1

+
+  0x080062FA:  4E           DC.B       0x4E                     ; 'N'
+  0x080062FB:  45           DC.B       0x45                     ; 'E'
+  0x080062FC:  57           DC.B       0x57                     ; 'W'
+  0x080062FD:  5F           DC.B       0x5F                     ; '_'
+  0x080062FE:  53           DC.B       0x53                     ; 'S'
+  0x080062FF:  54           DC.B       0x54                     ; 'T'
+  0x08006300:  41           DC.B       0x41                     ; 'A'
+  0x08006301:  54           DC.B       0x54                     ; 'T'
+  0x08006302:  45           DC.B       0x45                     ; 'E'
+  0x08006303:  3A           DC.B       0x3A                     ; ':'
+  0x08006304:  20           DC.B       0x20                     ; ' '
+  0x08006305:  4F           DC.B       0x4F                     ; 'O'
+  0x08006306:  56           DC.B       0x56                     ; 'V'
+  0x08006307:  50           DC.B       0x50                     ; 'P'
+  0x08006308:  5F           DC.B       0x5F                     ; '_'
+  0x08006309:  4F           DC.B       0x4F                     ; 'O'
+  0x0800630A:  46           DC.B       0x46                     ; 'F'
+  0x0800630B:  46           DC.B       0x46                     ; 'F'
+  0x0800630C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8.177 from PowerPro_lto.o, size=35, align=1

+
+  0x0800630D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800630E:  45           DC.B       0x45                     ; 'E'
+  0x0800630F:  57           DC.B       0x57                     ; 'W'
+  0x08006310:  5F           DC.B       0x5F                     ; '_'
+  0x08006311:  53           DC.B       0x53                     ; 'S'
+  0x08006312:  54           DC.B       0x54                     ; 'T'
+  0x08006313:  41           DC.B       0x41                     ; 'A'
+  0x08006314:  54           DC.B       0x54                     ; 'T'
+  0x08006315:  45           DC.B       0x45                     ; 'E'
+  0x08006316:  3A           DC.B       0x3A                     ; ':'
+  0x08006317:  20           DC.B       0x20                     ; ' '
+  0x08006318:  53           DC.B       0x53                     ; 'S'
+  0x08006319:  45           DC.B       0x45                     ; 'E'
+  0x0800631A:  43           DC.B       0x43                     ; 'C'
+  0x0800631B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800631C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800631D:  44           DC.B       0x44                     ; 'D'
+  0x0800631E:  41           DC.B       0x41                     ; 'A'
+  0x0800631F:  52           DC.B       0x52                     ; 'R'
+  0x08006320:  59           DC.B       0x59                     ; 'Y'
+  0x08006321:  50           DC.B       0x50                     ; 'P'
+  0x08006322:  52           DC.B       0x52                     ; 'R'
+  0x08006323:  4F           DC.B       0x4F                     ; 'O'
+  0x08006324:  54           DC.B       0x54                     ; 'T'
+  0x08006325:  45           DC.B       0x45                     ; 'E'
+  0x08006326:  43           DC.B       0x43                     ; 'C'
+  0x08006327:  54           DC.B       0x54                     ; 'T'
+  0x08006328:  49           DC.B       0x49                     ; 'I'
+  0x08006329:  4F           DC.B       0x4F                     ; 'O'
+  0x0800632A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800632B:  5F           DC.B       0x5F                     ; '_'
+  0x0800632C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800632D:  46           DC.B       0x46                     ; 'F'
+  0x0800632E:  46           DC.B       0x46                     ; 'F'
+  0x0800632F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.13.180 from PowerPro_lto.o, size=43, align=1

+
+  0x08006330:  4E           DC.B       0x4E                     ; 'N'
+  0x08006331:  45           DC.B       0x45                     ; 'E'
+  0x08006332:  57           DC.B       0x57                     ; 'W'
+  0x08006333:  5F           DC.B       0x5F                     ; '_'
+  0x08006334:  53           DC.B       0x53                     ; 'S'
+  0x08006335:  54           DC.B       0x54                     ; 'T'
+  0x08006336:  41           DC.B       0x41                     ; 'A'
+  0x08006337:  54           DC.B       0x54                     ; 'T'
+  0x08006338:  45           DC.B       0x45                     ; 'E'
+  0x08006339:  3A           DC.B       0x3A                     ; ':'
+  0x0800633A:  20           DC.B       0x20                     ; ' '
+  0x0800633B:  4D           DC.B       0x4D                     ; 'M'
+  0x0800633C:  41           DC.B       0x41                     ; 'A'
+  0x0800633D:  49           DC.B       0x49                     ; 'I'
+  0x0800633E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800633F:  53           DC.B       0x53                     ; 'S'
+  0x08006340:  57           DC.B       0x57                     ; 'W'
+  0x08006341:  49           DC.B       0x49                     ; 'I'
+  0x08006342:  54           DC.B       0x54                     ; 'T'
+  0x08006343:  43           DC.B       0x43                     ; 'C'
+  0x08006344:  48           DC.B       0x48                     ; 'H'
+  0x08006345:  5F           DC.B       0x5F                     ; '_'
+  0x08006346:  45           DC.B       0x45                     ; 'E'
+  0x08006347:  52           DC.B       0x52                     ; 'R'
+  0x08006348:  52           DC.B       0x52                     ; 'R'
+  0x08006349:  4F           DC.B       0x4F                     ; 'O'
+  0x0800634A:  52           DC.B       0x52                     ; 'R'
+  0x0800634B:  2C           DC.B       0x2C                     ; ','
+  0x0800634C:  20           DC.B       0x20                     ; ' '
+  0x0800634D:  54           DC.B       0x54                     ; 'T'
+  0x0800634E:  65           DC.B       0x65                     ; 'e'
+  0x0800634F:  6D           DC.B       0x6D                     ; 'm'
+  0x08006350:  70           DC.B       0x70                     ; 'p'
+  0x08006351:  20           DC.B       0x20                     ; ' '
+  0x08006352:  74           DC.B       0x74                     ; 't'
+  0x08006353:  6F           DC.B       0x6F                     ; 'o'
+  0x08006354:  6F           DC.B       0x6F                     ; 'o'
+  0x08006355:  20           DC.B       0x20                     ; ' '
+  0x08006356:  68           DC.B       0x68                     ; 'h'
+  0x08006357:  69           DC.B       0x69                     ; 'i'
+  0x08006358:  67           DC.B       0x67                     ; 'g'
+  0x08006359:  68           DC.B       0x68                     ; 'h'
+  0x0800635A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.203 from PowerPro_lto.o, size=35, align=1

+
+  0x0800635B:  76           DC.B       0x76                     ; 'v'
+  0x0800635C:  6F           DC.B       0x6F                     ; 'o'
+  0x0800635D:  6C           DC.B       0x6C                     ; 'l'
+  0x0800635E:  74           DC.B       0x74                     ; 't'
+  0x0800635F:  61           DC.B       0x61                     ; 'a'
+  0x08006360:  67           DC.B       0x67                     ; 'g'
+  0x08006361:  65           DC.B       0x65                     ; 'e'
+  0x08006362:  20           DC.B       0x20                     ; ' '
+  0x08006363:  69           DC.B       0x69                     ; 'i'
+  0x08006364:  6E           DC.B       0x6E                     ; 'n'
+  0x08006365:  3D           DC.B       0x3D                     ; '='
+  0x08006366:  20           DC.B       0x20                     ; ' '
+  0x08006367:  25           DC.B       0x25                     ; '%'
+  0x08006368:  64           DC.B       0x64                     ; 'd'
+  0x08006369:  2C           DC.B       0x2C                     ; ','
+  0x0800636A:  20           DC.B       0x20                     ; ' '
+  0x0800636B:  6F           DC.B       0x6F                     ; 'o'
+  0x0800636C:  75           DC.B       0x75                     ; 'u'
+  0x0800636D:  74           DC.B       0x74                     ; 't'
+  0x0800636E:  3D           DC.B       0x3D                     ; '='
+  0x0800636F:  20           DC.B       0x20                     ; ' '
+  0x08006370:  25           DC.B       0x25                     ; '%'
+  0x08006371:  64           DC.B       0x64                     ; 'd'
+  0x08006372:  2C           DC.B       0x2C                     ; ','
+  0x08006373:  20           DC.B       0x20                     ; ' '
+  0x08006374:  64           DC.B       0x64                     ; 'd'
+  0x08006375:  72           DC.B       0x72                     ; 'r'
+  0x08006376:  6F           DC.B       0x6F                     ; 'o'
+  0x08006377:  70           DC.B       0x70                     ; 'p'
+  0x08006378:  20           DC.B       0x20                     ; ' '
+  0x08006379:  25           DC.B       0x25                     ; '%'
+  0x0800637A:  64           DC.B       0x64                     ; 'd'
+  0x0800637B:  0D           DC.B       0x0D                     ; '\r'
+  0x0800637C:  0A           DC.B       0x0A                     ; '\n'
+  0x0800637D:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_month_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=87, align=1

+
+
__SEGGER_RTL_c_locale_month_names:
+  0x0800637E:  4A           DC.B       0x4A                     ; 'J'
+  0x0800637F:  61           DC.B       0x61                     ; 'a'
+  0x08006380:  6E           DC.B       0x6E                     ; 'n'
+  0x08006381:  75           DC.B       0x75                     ; 'u'
+  0x08006382:  61           DC.B       0x61                     ; 'a'
+  0x08006383:  72           DC.B       0x72                     ; 'r'
+  0x08006384:  79           DC.B       0x79                     ; 'y'
+  0x08006385:  00           DC.B       0x00                     ; '\0'
+  0x08006386:  46           DC.B       0x46                     ; 'F'
+  0x08006387:  65           DC.B       0x65                     ; 'e'
+  0x08006388:  62           DC.B       0x62                     ; 'b'
+  0x08006389:  72           DC.B       0x72                     ; 'r'
+  0x0800638A:  75           DC.B       0x75                     ; 'u'
+  0x0800638B:  61           DC.B       0x61                     ; 'a'
+  0x0800638C:  72           DC.B       0x72                     ; 'r'
+  0x0800638D:  79           DC.B       0x79                     ; 'y'
+  0x0800638E:  00           DC.B       0x00                     ; '\0'
+  0x0800638F:  4D           DC.B       0x4D                     ; 'M'
+  0x08006390:  61           DC.B       0x61                     ; 'a'
+  0x08006391:  72           DC.B       0x72                     ; 'r'
+  0x08006392:  63           DC.B       0x63                     ; 'c'
+  0x08006393:  68           DC.B       0x68                     ; 'h'
+  0x08006394:  00           DC.B       0x00                     ; '\0'
+  0x08006395:  41           DC.B       0x41                     ; 'A'
+  0x08006396:  70           DC.B       0x70                     ; 'p'
+  0x08006397:  72           DC.B       0x72                     ; 'r'
+  0x08006398:  69           DC.B       0x69                     ; 'i'
+  0x08006399:  6C           DC.B       0x6C                     ; 'l'
+  0x0800639A:  00           DC.B       0x00                     ; '\0'
+  0x0800639B:  4D           DC.B       0x4D                     ; 'M'
+  0x0800639C:  61           DC.B       0x61                     ; 'a'
+  0x0800639D:  79           DC.B       0x79                     ; 'y'
+  0x0800639E:  00           DC.B       0x00                     ; '\0'
+  0x0800639F:  4A           DC.B       0x4A                     ; 'J'
+  0x080063A0:  75           DC.B       0x75                     ; 'u'
+  0x080063A1:  6E           DC.B       0x6E                     ; 'n'
+  0x080063A2:  65           DC.B       0x65                     ; 'e'
+  0x080063A3:  00           DC.B       0x00                     ; '\0'
+  0x080063A4:  4A           DC.B       0x4A                     ; 'J'
+  0x080063A5:  75           DC.B       0x75                     ; 'u'
+  0x080063A6:  6C           DC.B       0x6C                     ; 'l'
+  0x080063A7:  79           DC.B       0x79                     ; 'y'
+  0x080063A8:  00           DC.B       0x00                     ; '\0'
+  0x080063A9:  41           DC.B       0x41                     ; 'A'
+  0x080063AA:  75           DC.B       0x75                     ; 'u'
+  0x080063AB:  67           DC.B       0x67                     ; 'g'
+  0x080063AC:  75           DC.B       0x75                     ; 'u'
+  0x080063AD:  73           DC.B       0x73                     ; 's'
+  0x080063AE:  74           DC.B       0x74                     ; 't'
+  0x080063AF:  00           DC.B       0x00                     ; '\0'
+  0x080063B0:  53           DC.B       0x53                     ; 'S'
+  0x080063B1:  65           DC.B       0x65                     ; 'e'
+  0x080063B2:  70           DC.B       0x70                     ; 'p'
+  0x080063B3:  74           DC.B       0x74                     ; 't'
+  0x080063B4:  65           DC.B       0x65                     ; 'e'
+  0x080063B5:  6D           DC.B       0x6D                     ; 'm'
+  0x080063B6:  62           DC.B       0x62                     ; 'b'
+  0x080063B7:  65           DC.B       0x65                     ; 'e'
+  0x080063B8:  72           DC.B       0x72                     ; 'r'
+  0x080063B9:  00           DC.B       0x00                     ; '\0'
+  0x080063BA:  4F           DC.B       0x4F                     ; 'O'
+  0x080063BB:  63           DC.B       0x63                     ; 'c'
+  0x080063BC:  74           DC.B       0x74                     ; 't'
+  0x080063BD:  6F           DC.B       0x6F                     ; 'o'
+  0x080063BE:  62           DC.B       0x62                     ; 'b'
+  0x080063BF:  65           DC.B       0x65                     ; 'e'
+  0x080063C0:  72           DC.B       0x72                     ; 'r'
+  0x080063C1:  00           DC.B       0x00                     ; '\0'
+  0x080063C2:  4E           DC.B       0x4E                     ; 'N'
+  0x080063C3:  6F           DC.B       0x6F                     ; 'o'
+  0x080063C4:  76           DC.B       0x76                     ; 'v'
+  0x080063C5:  65           DC.B       0x65                     ; 'e'
+  0x080063C6:  6D           DC.B       0x6D                     ; 'm'
+  0x080063C7:  62           DC.B       0x62                     ; 'b'
+  0x080063C8:  65           DC.B       0x65                     ; 'e'
+  0x080063C9:  72           DC.B       0x72                     ; 'r'
+  0x080063CA:  00           DC.B       0x00                     ; '\0'
+  0x080063CB:  44           DC.B       0x44                     ; 'D'
+  0x080063CC:  65           DC.B       0x65                     ; 'e'
+  0x080063CD:  63           DC.B       0x63                     ; 'c'
+  0x080063CE:  65           DC.B       0x65                     ; 'e'
+  0x080063CF:  6D           DC.B       0x6D                     ; 'm'
+  0x080063D0:  62           DC.B       0x62                     ; 'b'
+  0x080063D1:  65           DC.B       0x65                     ; 'e'
+  0x080063D2:  72           DC.B       0x72                     ; 'r'
+  0x080063D3:  00           DC.B       0x00                     ; '\0'
+  0x080063D4:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_am_pm_indicator from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=7, align=1

+
+
__SEGGER_RTL_c_locale_am_pm_indicator:
+  0x080063D5:  41           DC.B       0x41                     ; 'A'
+  0x080063D6:  4D           DC.B       0x4D                     ; 'M'
+  0x080063D7:  00           DC.B       0x00                     ; '\0'
+  0x080063D8:  50           DC.B       0x50                     ; 'P'
+  0x080063D9:  4D           DC.B       0x4D                     ; 'M'
+  0x080063DA:  00           DC.B       0x00                     ; '\0'
+  0x080063DB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_date_time_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=15, align=1

+
+
__SEGGER_RTL_c_locale_date_time_format:
+  0x080063DC:  25           DC.B       0x25                     ; '%'
+  0x080063DD:  61           DC.B       0x61                     ; 'a'
+  0x080063DE:  20           DC.B       0x20                     ; ' '
+  0x080063DF:  25           DC.B       0x25                     ; '%'
+  0x080063E0:  62           DC.B       0x62                     ; 'b'
+  0x080063E1:  20           DC.B       0x20                     ; ' '
+  0x080063E2:  25           DC.B       0x25                     ; '%'
+  0x080063E3:  65           DC.B       0x65                     ; 'e'
+  0x080063E4:  20           DC.B       0x20                     ; ' '
+  0x080063E5:  25           DC.B       0x25                     ; '%'
+  0x080063E6:  54           DC.B       0x54                     ; 'T'
+  0x080063E7:  20           DC.B       0x20                     ; ' '
+  0x080063E8:  25           DC.B       0x25                     ; '%'
+  0x080063E9:  59           DC.B       0x59                     ; 'Y'
+  0x080063EA:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr from PowerPro_lto.o, size=18, align=1

+
+  0x080063EB:  42           DC.B       0x42                     ; 'B'
+  0x080063EC:  55           DC.B       0x55                     ; 'U'
+  0x080063ED:  54           DC.B       0x54                     ; 'T'
+  0x080063EE:  54           DC.B       0x54                     ; 'T'
+  0x080063EF:  4F           DC.B       0x4F                     ; 'O'
+  0x080063F0:  4E           DC.B       0x4E                     ; 'N'
+  0x080063F1:  3A           DC.B       0x3A                     ; ':'
+  0x080063F2:  20           DC.B       0x20                     ; ' '
+  0x080063F3:  41           DC.B       0x41                     ; 'A'
+  0x080063F4:  75           DC.B       0x75                     ; 'u'
+  0x080063F5:  74           DC.B       0x74                     ; 't'
+  0x080063F6:  6F           DC.B       0x6F                     ; 'o'
+  0x080063F7:  20           DC.B       0x20                     ; ' '
+  0x080063F8:  4D           DC.B       0x4D                     ; 'M'
+  0x080063F9:  6F           DC.B       0x6F                     ; 'o'
+  0x080063FA:  64           DC.B       0x64                     ; 'd'
+  0x080063FB:  65           DC.B       0x65                     ; 'e'
+  0x080063FC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8 from PowerPro_lto.o, size=18, align=1

+
+  0x080063FD:  4B           DC.B       0x4B                     ; 'K'
+  0x080063FE:  6F           DC.B       0x6F                     ; 'o'
+  0x080063FF:  6E           DC.B       0x6E                     ; 'n'
+  0x08006400:  66           DC.B       0x66                     ; 'f'
+  0x08006401:  69           DC.B       0x69                     ; 'i'
+  0x08006402:  67           DC.B       0x67                     ; 'g'
+  0x08006403:  20           DC.B       0x20                     ; ' '
+  0x08006404:  76           DC.B       0x76                     ; 'v'
+  0x08006405:  6F           DC.B       0x6F                     ; 'o'
+  0x08006406:  72           DC.B       0x72                     ; 'r'
+  0x08006407:  68           DC.B       0x68                     ; 'h'
+  0x08006408:  61           DC.B       0x61                     ; 'a'
+  0x08006409:  6E           DC.B       0x6E                     ; 'n'
+  0x0800640A:  64           DC.B       0x64                     ; 'd'
+  0x0800640B:  65           DC.B       0x65                     ; 'e'
+  0x0800640C:  6E           DC.B       0x6E                     ; 'n'
+  0x0800640D:  0D           DC.B       0x0D                     ; '\r'
+  0x0800640E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.10 from PowerPro_lto.o, size=46, align=1

+
+  0x0800640F:  45           DC.B       0x45                     ; 'E'
+  0x08006410:  72           DC.B       0x72                     ; 'r'
+  0x08006411:  73           DC.B       0x73                     ; 's'
+  0x08006412:  74           DC.B       0x74                     ; 't'
+  0x08006413:  73           DC.B       0x73                     ; 's'
+  0x08006414:  74           DC.B       0x74                     ; 't'
+  0x08006415:  61           DC.B       0x61                     ; 'a'
+  0x08006416:  72           DC.B       0x72                     ; 'r'
+  0x08006417:  74           DC.B       0x74                     ; 't'
+  0x08006418:  20           DC.B       0x20                     ; ' '
+  0x08006419:  65           DC.B       0x65                     ; 'e'
+  0x0800641A:  72           DC.B       0x72                     ; 'r'
+  0x0800641B:  6B           DC.B       0x6B                     ; 'k'
+  0x0800641C:  61           DC.B       0x61                     ; 'a'
+  0x0800641D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800641E:  6E           DC.B       0x6E                     ; 'n'
+  0x0800641F:  74           DC.B       0x74                     ; 't'
+  0x08006420:  2C           DC.B       0x2C                     ; ','
+  0x08006421:  20           DC.B       0x20                     ; ' '
+  0x08006422:  73           DC.B       0x73                     ; 's'
+  0x08006423:  63           DC.B       0x63                     ; 'c'
+  0x08006424:  68           DC.B       0x68                     ; 'h'
+  0x08006425:  72           DC.B       0x72                     ; 'r'
+  0x08006426:  65           DC.B       0x65                     ; 'e'
+  0x08006427:  69           DC.B       0x69                     ; 'i'
+  0x08006428:  62           DC.B       0x62                     ; 'b'
+  0x08006429:  65           DC.B       0x65                     ; 'e'
+  0x0800642A:  20           DC.B       0x20                     ; ' '
+  0x0800642B:  57           DC.B       0x57                     ; 'W'
+  0x0800642C:  65           DC.B       0x65                     ; 'e'
+  0x0800642D:  72           DC.B       0x72                     ; 'r'
+  0x0800642E:  6B           DC.B       0x6B                     ; 'k'
+  0x0800642F:  73           DC.B       0x73                     ; 's'
+  0x08006430:  65           DC.B       0x65                     ; 'e'
+  0x08006431:  69           DC.B       0x69                     ; 'i'
+  0x08006432:  6E           DC.B       0x6E                     ; 'n'
+  0x08006433:  73           DC.B       0x73                     ; 's'
+  0x08006434:  74           DC.B       0x74                     ; 't'
+  0x08006435:  65           DC.B       0x65                     ; 'e'
+  0x08006436:  6C           DC.B       0x6C                     ; 'l'
+  0x08006437:  6C           DC.B       0x6C                     ; 'l'
+  0x08006438:  75           DC.B       0x75                     ; 'u'
+  0x08006439:  6E           DC.B       0x6E                     ; 'n'
+  0x0800643A:  67           DC.B       0x67                     ; 'g'
+  0x0800643B:  0D           DC.B       0x0D                     ; '\r'
+  0x0800643C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.1 from PowerPro_lto.o, size=14, align=1

+
+  0x0800643D:  75           DC.B       0x75                     ; 'u'
+  0x0800643E:  61           DC.B       0x61                     ; 'a'
+  0x0800643F:  72           DC.B       0x72                     ; 'r'
+  0x08006440:  74           DC.B       0x74                     ; 't'
+  0x08006441:  20           DC.B       0x20                     ; ' '
+  0x08006442:  65           DC.B       0x65                     ; 'e'
+  0x08006443:  72           DC.B       0x72                     ; 'r'
+  0x08006444:  72           DC.B       0x72                     ; 'r'
+  0x08006445:  6F           DC.B       0x6F                     ; 'o'
+  0x08006446:  72           DC.B       0x72                     ; 'r'
+  0x08006447:  20           DC.B       0x20                     ; ' '
+  0x08006448:  0A           DC.B       0x0A                     ; '\n'
+  0x08006449:  0D           DC.B       0x0D                     ; '\r'
+  0x0800644A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.117 from PowerPro_lto.o, size=30, align=1

+
+  0x0800644B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800644C:  56           DC.B       0x56                     ; 'V'
+  0x0800644D:  50           DC.B       0x50                     ; 'P'
+  0x0800644E:  5F           DC.B       0x5F                     ; '_'
+  0x0800644F:  53           DC.B       0x53                     ; 'S'
+  0x08006450:  4D           DC.B       0x4D                     ; 'M'
+  0x08006451:  5F           DC.B       0x5F                     ; '_'
+  0x08006452:  4F           DC.B       0x4F                     ; 'O'
+  0x08006453:  66           DC.B       0x66                     ; 'f'
+  0x08006454:  66           DC.B       0x66                     ; 'f'
+  0x08006455:  3A           DC.B       0x3A                     ; ':'
+  0x08006456:  20           DC.B       0x20                     ; ' '
+  0x08006457:  4E           DC.B       0x4E                     ; 'N'
+  0x08006458:  45           DC.B       0x45                     ; 'E'
+  0x08006459:  57           DC.B       0x57                     ; 'W'
+  0x0800645A:  5F           DC.B       0x5F                     ; '_'
+  0x0800645B:  53           DC.B       0x53                     ; 'S'
+  0x0800645C:  54           DC.B       0x54                     ; 'T'
+  0x0800645D:  41           DC.B       0x41                     ; 'A'
+  0x0800645E:  54           DC.B       0x54                     ; 'T'
+  0x0800645F:  45           DC.B       0x45                     ; 'E'
+  0x08006460:  3A           DC.B       0x3A                     ; ':'
+  0x08006461:  20           DC.B       0x20                     ; ' '
+  0x08006462:  4C           DC.B       0x4C                     ; 'L'
+  0x08006463:  56           DC.B       0x56                     ; 'V'
+  0x08006464:  50           DC.B       0x50                     ; 'P'
+  0x08006465:  5F           DC.B       0x5F                     ; '_'
+  0x08006466:  4F           DC.B       0x4F                     ; 'O'
+  0x08006467:  4E           DC.B       0x4E                     ; 'N'
+  0x08006468:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23 from PowerPro_lto.o, size=18, align=1

+
+  0x08006469:  4E           DC.B       0x4E                     ; 'N'
+  0x0800646A:  45           DC.B       0x45                     ; 'E'
+  0x0800646B:  57           DC.B       0x57                     ; 'W'
+  0x0800646C:  5F           DC.B       0x5F                     ; '_'
+  0x0800646D:  53           DC.B       0x53                     ; 'S'
+  0x0800646E:  54           DC.B       0x54                     ; 'T'
+  0x0800646F:  41           DC.B       0x41                     ; 'A'
+  0x08006470:  54           DC.B       0x54                     ; 'T'
+  0x08006471:  45           DC.B       0x45                     ; 'E'
+  0x08006472:  3A           DC.B       0x3A                     ; ':'
+  0x08006473:  20           DC.B       0x20                     ; ' '
+  0x08006474:  4C           DC.B       0x4C                     ; 'L'
+  0x08006475:  56           DC.B       0x56                     ; 'V'
+  0x08006476:  50           DC.B       0x50                     ; 'P'
+  0x08006477:  5F           DC.B       0x5F                     ; '_'
+  0x08006478:  4F           DC.B       0x4F                     ; 'O'
+  0x08006479:  4E           DC.B       0x4E                     ; 'N'
+  0x0800647A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.123 from PowerPro_lto.o, size=38, align=1

+
+  0x0800647B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800647C:  56           DC.B       0x56                     ; 'V'
+  0x0800647D:  50           DC.B       0x50                     ; 'P'
+  0x0800647E:  5F           DC.B       0x5F                     ; '_'
+  0x0800647F:  4F           DC.B       0x4F                     ; 'O'
+  0x08006480:  56           DC.B       0x56                     ; 'V'
+  0x08006481:  50           DC.B       0x50                     ; 'P'
+  0x08006482:  5F           DC.B       0x5F                     ; '_'
+  0x08006483:  53           DC.B       0x53                     ; 'S'
+  0x08006484:  4D           DC.B       0x4D                     ; 'M'
+  0x08006485:  5F           DC.B       0x5F                     ; '_'
+  0x08006486:  4F           DC.B       0x4F                     ; 'O'
+  0x08006487:  66           DC.B       0x66                     ; 'f'
+  0x08006488:  66           DC.B       0x66                     ; 'f'
+  0x08006489:  3A           DC.B       0x3A                     ; ':'
+  0x0800648A:  20           DC.B       0x20                     ; ' '
+  0x0800648B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800648C:  45           DC.B       0x45                     ; 'E'
+  0x0800648D:  57           DC.B       0x57                     ; 'W'
+  0x0800648E:  5F           DC.B       0x5F                     ; '_'
+  0x0800648F:  53           DC.B       0x53                     ; 'S'
+  0x08006490:  54           DC.B       0x54                     ; 'T'
+  0x08006491:  41           DC.B       0x41                     ; 'A'
+  0x08006492:  54           DC.B       0x54                     ; 'T'
+  0x08006493:  45           DC.B       0x45                     ; 'E'
+  0x08006494:  3A           DC.B       0x3A                     ; ':'
+  0x08006495:  20           DC.B       0x20                     ; ' '
+  0x08006496:  4C           DC.B       0x4C                     ; 'L'
+  0x08006497:  56           DC.B       0x56                     ; 'V'
+  0x08006498:  50           DC.B       0x50                     ; 'P'
+  0x08006499:  5F           DC.B       0x5F                     ; '_'
+  0x0800649A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800649B:  56           DC.B       0x56                     ; 'V'
+  0x0800649C:  50           DC.B       0x50                     ; 'P'
+  0x0800649D:  5F           DC.B       0x5F                     ; '_'
+  0x0800649E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800649F:  4E           DC.B       0x4E                     ; 'N'
+  0x080064A0:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.20.132 from PowerPro_lto.o, size=38, align=1

+
+  0x080064A1:  4E           DC.B       0x4E                     ; 'N'
+  0x080064A2:  45           DC.B       0x45                     ; 'E'
+  0x080064A3:  57           DC.B       0x57                     ; 'W'
+  0x080064A4:  5F           DC.B       0x5F                     ; '_'
+  0x080064A5:  53           DC.B       0x53                     ; 'S'
+  0x080064A6:  54           DC.B       0x54                     ; 'T'
+  0x080064A7:  41           DC.B       0x41                     ; 'A'
+  0x080064A8:  54           DC.B       0x54                     ; 'T'
+  0x080064A9:  45           DC.B       0x45                     ; 'E'
+  0x080064AA:  3A           DC.B       0x3A                     ; ':'
+  0x080064AB:  20           DC.B       0x20                     ; ' '
+  0x080064AC:  4C           DC.B       0x4C                     ; 'L'
+  0x080064AD:  56           DC.B       0x56                     ; 'V'
+  0x080064AE:  50           DC.B       0x50                     ; 'P'
+  0x080064AF:  5F           DC.B       0x5F                     ; '_'
+  0x080064B0:  4F           DC.B       0x4F                     ; 'O'
+  0x080064B1:  56           DC.B       0x56                     ; 'V'
+  0x080064B2:  50           DC.B       0x50                     ; 'P'
+  0x080064B3:  5F           DC.B       0x5F                     ; '_'
+  0x080064B4:  41           DC.B       0x41                     ; 'A'
+  0x080064B5:  75           DC.B       0x75                     ; 'u'
+  0x080064B6:  74           DC.B       0x74                     ; 't'
+  0x080064B7:  6F           DC.B       0x6F                     ; 'o'
+  0x080064B8:  20           DC.B       0x20                     ; ' '
+  0x080064B9:  4F           DC.B       0x4F                     ; 'O'
+  0x080064BA:  6E           DC.B       0x6E                     ; 'n'
+  0x080064BB:  2C           DC.B       0x2C                     ; ','
+  0x080064BC:  20           DC.B       0x20                     ; ' '
+  0x080064BD:  52           DC.B       0x52                     ; 'R'
+  0x080064BE:  65           DC.B       0x65                     ; 'e'
+  0x080064BF:  6C           DC.B       0x6C                     ; 'l'
+  0x080064C0:  61           DC.B       0x61                     ; 'a'
+  0x080064C1:  69           DC.B       0x69                     ; 'i'
+  0x080064C2:  73           DC.B       0x73                     ; 's'
+  0x080064C3:  20           DC.B       0x20                     ; ' '
+  0x080064C4:  6F           DC.B       0x6F                     ; 'o'
+  0x080064C5:  6E           DC.B       0x6E                     ; 'n'
+  0x080064C6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23.134 from PowerPro_lto.o, size=22, align=1

+
+  0x080064C7:  4E           DC.B       0x4E                     ; 'N'
+  0x080064C8:  45           DC.B       0x45                     ; 'E'
+  0x080064C9:  57           DC.B       0x57                     ; 'W'
+  0x080064CA:  5F           DC.B       0x5F                     ; '_'
+  0x080064CB:  53           DC.B       0x53                     ; 'S'
+  0x080064CC:  54           DC.B       0x54                     ; 'T'
+  0x080064CD:  41           DC.B       0x41                     ; 'A'
+  0x080064CE:  54           DC.B       0x54                     ; 'T'
+  0x080064CF:  45           DC.B       0x45                     ; 'E'
+  0x080064D0:  3A           DC.B       0x3A                     ; ':'
+  0x080064D1:  20           DC.B       0x20                     ; ' '
+  0x080064D2:  4C           DC.B       0x4C                     ; 'L'
+  0x080064D3:  56           DC.B       0x56                     ; 'V'
+  0x080064D4:  50           DC.B       0x50                     ; 'P'
+  0x080064D5:  5F           DC.B       0x5F                     ; '_'
+  0x080064D6:  4F           DC.B       0x4F                     ; 'O'
+  0x080064D7:  56           DC.B       0x56                     ; 'V'
+  0x080064D8:  50           DC.B       0x50                     ; 'P'
+  0x080064D9:  5F           DC.B       0x5F                     ; '_'
+  0x080064DA:  4F           DC.B       0x4F                     ; 'O'
+  0x080064DB:  4E           DC.B       0x4E                     ; 'N'
+  0x080064DC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.10.139 from PowerPro_lto.o, size=26, align=1

+
+  0x080064DD:  4E           DC.B       0x4E                     ; 'N'
+  0x080064DE:  45           DC.B       0x45                     ; 'E'
+  0x080064DF:  57           DC.B       0x57                     ; 'W'
+  0x080064E0:  5F           DC.B       0x5F                     ; '_'
+  0x080064E1:  53           DC.B       0x53                     ; 'S'
+  0x080064E2:  54           DC.B       0x54                     ; 'T'
+  0x080064E3:  41           DC.B       0x41                     ; 'A'
+  0x080064E4:  54           DC.B       0x54                     ; 'T'
+  0x080064E5:  45           DC.B       0x45                     ; 'E'
+  0x080064E6:  3A           DC.B       0x3A                     ; ':'
+  0x080064E7:  20           DC.B       0x20                     ; ' '
+  0x080064E8:  4D           DC.B       0x4D                     ; 'M'
+  0x080064E9:  41           DC.B       0x41                     ; 'A'
+  0x080064EA:  49           DC.B       0x49                     ; 'I'
+  0x080064EB:  4E           DC.B       0x4E                     ; 'N'
+  0x080064EC:  53           DC.B       0x53                     ; 'S'
+  0x080064ED:  57           DC.B       0x57                     ; 'W'
+  0x080064EE:  49           DC.B       0x49                     ; 'I'
+  0x080064EF:  54           DC.B       0x54                     ; 'T'
+  0x080064F0:  43           DC.B       0x43                     ; 'C'
+  0x080064F1:  48           DC.B       0x48                     ; 'H'
+  0x080064F2:  5F           DC.B       0x5F                     ; '_'
+  0x080064F3:  4F           DC.B       0x4F                     ; 'O'
+  0x080064F4:  46           DC.B       0x46                     ; 'F'
+  0x080064F5:  46           DC.B       0x46                     ; 'F'
+  0x080064F6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.146 from PowerPro_lto.o, size=30, align=1

+
+  0x080064F7:  4F           DC.B       0x4F                     ; 'O'
+  0x080064F8:  56           DC.B       0x56                     ; 'V'
+  0x080064F9:  50           DC.B       0x50                     ; 'P'
+  0x080064FA:  5F           DC.B       0x5F                     ; '_'
+  0x080064FB:  53           DC.B       0x53                     ; 'S'
+  0x080064FC:  4D           DC.B       0x4D                     ; 'M'
+  0x080064FD:  5F           DC.B       0x5F                     ; '_'
+  0x080064FE:  4F           DC.B       0x4F                     ; 'O'
+  0x080064FF:  66           DC.B       0x66                     ; 'f'
+  0x08006500:  66           DC.B       0x66                     ; 'f'
+  0x08006501:  3A           DC.B       0x3A                     ; ':'
+  0x08006502:  20           DC.B       0x20                     ; ' '
+  0x08006503:  4E           DC.B       0x4E                     ; 'N'
+  0x08006504:  45           DC.B       0x45                     ; 'E'
+  0x08006505:  57           DC.B       0x57                     ; 'W'
+  0x08006506:  5F           DC.B       0x5F                     ; '_'
+  0x08006507:  53           DC.B       0x53                     ; 'S'
+  0x08006508:  54           DC.B       0x54                     ; 'T'
+  0x08006509:  41           DC.B       0x41                     ; 'A'
+  0x0800650A:  54           DC.B       0x54                     ; 'T'
+  0x0800650B:  45           DC.B       0x45                     ; 'E'
+  0x0800650C:  3A           DC.B       0x3A                     ; ':'
+  0x0800650D:  20           DC.B       0x20                     ; ' '
+  0x0800650E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800650F:  56           DC.B       0x56                     ; 'V'
+  0x08006510:  50           DC.B       0x50                     ; 'P'
+  0x08006511:  5F           DC.B       0x5F                     ; '_'
+  0x08006512:  4F           DC.B       0x4F                     ; 'O'
+  0x08006513:  4E           DC.B       0x4E                     ; 'N'
+  0x08006514:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.20.155 from PowerPro_lto.o, size=38, align=1

+
+  0x08006515:  4E           DC.B       0x4E                     ; 'N'
+  0x08006516:  45           DC.B       0x45                     ; 'E'
+  0x08006517:  57           DC.B       0x57                     ; 'W'
+  0x08006518:  5F           DC.B       0x5F                     ; '_'
+  0x08006519:  53           DC.B       0x53                     ; 'S'
+  0x0800651A:  54           DC.B       0x54                     ; 'T'
+  0x0800651B:  41           DC.B       0x41                     ; 'A'
+  0x0800651C:  54           DC.B       0x54                     ; 'T'
+  0x0800651D:  45           DC.B       0x45                     ; 'E'
+  0x0800651E:  3A           DC.B       0x3A                     ; ':'
+  0x0800651F:  20           DC.B       0x20                     ; ' '
+  0x08006520:  4F           DC.B       0x4F                     ; 'O'
+  0x08006521:  56           DC.B       0x56                     ; 'V'
+  0x08006522:  50           DC.B       0x50                     ; 'P'
+  0x08006523:  5F           DC.B       0x5F                     ; '_'
+  0x08006524:  4F           DC.B       0x4F                     ; 'O'
+  0x08006525:  56           DC.B       0x56                     ; 'V'
+  0x08006526:  50           DC.B       0x50                     ; 'P'
+  0x08006527:  5F           DC.B       0x5F                     ; '_'
+  0x08006528:  41           DC.B       0x41                     ; 'A'
+  0x08006529:  75           DC.B       0x75                     ; 'u'
+  0x0800652A:  74           DC.B       0x74                     ; 't'
+  0x0800652B:  6F           DC.B       0x6F                     ; 'o'
+  0x0800652C:  20           DC.B       0x20                     ; ' '
+  0x0800652D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800652E:  6E           DC.B       0x6E                     ; 'n'
+  0x0800652F:  2C           DC.B       0x2C                     ; ','
+  0x08006530:  20           DC.B       0x20                     ; ' '
+  0x08006531:  52           DC.B       0x52                     ; 'R'
+  0x08006532:  65           DC.B       0x65                     ; 'e'
+  0x08006533:  6C           DC.B       0x6C                     ; 'l'
+  0x08006534:  61           DC.B       0x61                     ; 'a'
+  0x08006535:  69           DC.B       0x69                     ; 'i'
+  0x08006536:  73           DC.B       0x73                     ; 's'
+  0x08006537:  20           DC.B       0x20                     ; ' '
+  0x08006538:  6F           DC.B       0x6F                     ; 'o'
+  0x08006539:  6E           DC.B       0x6E                     ; 'n'
+  0x0800653A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.23.157 from PowerPro_lto.o, size=18, align=1

+
+  0x0800653B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800653C:  45           DC.B       0x45                     ; 'E'
+  0x0800653D:  57           DC.B       0x57                     ; 'W'
+  0x0800653E:  5F           DC.B       0x5F                     ; '_'
+  0x0800653F:  53           DC.B       0x53                     ; 'S'
+  0x08006540:  54           DC.B       0x54                     ; 'T'
+  0x08006541:  41           DC.B       0x41                     ; 'A'
+  0x08006542:  54           DC.B       0x54                     ; 'T'
+  0x08006543:  45           DC.B       0x45                     ; 'E'
+  0x08006544:  3A           DC.B       0x3A                     ; ':'
+  0x08006545:  20           DC.B       0x20                     ; ' '
+  0x08006546:  4F           DC.B       0x4F                     ; 'O'
+  0x08006547:  56           DC.B       0x56                     ; 'V'
+  0x08006548:  50           DC.B       0x50                     ; 'P'
+  0x08006549:  5F           DC.B       0x5F                     ; '_'
+  0x0800654A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800654B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800654C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.16.172 from PowerPro_lto.o, size=34, align=1

+
+  0x0800654D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800654E:  45           DC.B       0x45                     ; 'E'
+  0x0800654F:  57           DC.B       0x57                     ; 'W'
+  0x08006550:  5F           DC.B       0x5F                     ; '_'
+  0x08006551:  53           DC.B       0x53                     ; 'S'
+  0x08006552:  54           DC.B       0x54                     ; 'T'
+  0x08006553:  41           DC.B       0x41                     ; 'A'
+  0x08006554:  54           DC.B       0x54                     ; 'T'
+  0x08006555:  45           DC.B       0x45                     ; 'E'
+  0x08006556:  3A           DC.B       0x3A                     ; ':'
+  0x08006557:  20           DC.B       0x20                     ; ' '
+  0x08006558:  53           DC.B       0x53                     ; 'S'
+  0x08006559:  45           DC.B       0x45                     ; 'E'
+  0x0800655A:  43           DC.B       0x43                     ; 'C'
+  0x0800655B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800655C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800655D:  44           DC.B       0x44                     ; 'D'
+  0x0800655E:  41           DC.B       0x41                     ; 'A'
+  0x0800655F:  52           DC.B       0x52                     ; 'R'
+  0x08006560:  59           DC.B       0x59                     ; 'Y'
+  0x08006561:  50           DC.B       0x50                     ; 'P'
+  0x08006562:  52           DC.B       0x52                     ; 'R'
+  0x08006563:  4F           DC.B       0x4F                     ; 'O'
+  0x08006564:  54           DC.B       0x54                     ; 'T'
+  0x08006565:  45           DC.B       0x45                     ; 'E'
+  0x08006566:  43           DC.B       0x43                     ; 'C'
+  0x08006567:  54           DC.B       0x54                     ; 'T'
+  0x08006568:  49           DC.B       0x49                     ; 'I'
+  0x08006569:  4F           DC.B       0x4F                     ; 'O'
+  0x0800656A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800656B:  5F           DC.B       0x5F                     ; '_'
+  0x0800656C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800656D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800656E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_day_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=58, align=1

+
+
__SEGGER_RTL_c_locale_day_names:
+  0x0800656F:  53           DC.B       0x53                     ; 'S'
+  0x08006570:  75           DC.B       0x75                     ; 'u'
+  0x08006571:  6E           DC.B       0x6E                     ; 'n'
+  0x08006572:  64           DC.B       0x64                     ; 'd'
+  0x08006573:  61           DC.B       0x61                     ; 'a'
+  0x08006574:  79           DC.B       0x79                     ; 'y'
+  0x08006575:  00           DC.B       0x00                     ; '\0'
+  0x08006576:  4D           DC.B       0x4D                     ; 'M'
+  0x08006577:  6F           DC.B       0x6F                     ; 'o'
+  0x08006578:  6E           DC.B       0x6E                     ; 'n'
+  0x08006579:  64           DC.B       0x64                     ; 'd'
+  0x0800657A:  61           DC.B       0x61                     ; 'a'
+  0x0800657B:  79           DC.B       0x79                     ; 'y'
+  0x0800657C:  00           DC.B       0x00                     ; '\0'
+  0x0800657D:  54           DC.B       0x54                     ; 'T'
+  0x0800657E:  75           DC.B       0x75                     ; 'u'
+  0x0800657F:  65           DC.B       0x65                     ; 'e'
+  0x08006580:  73           DC.B       0x73                     ; 's'
+  0x08006581:  64           DC.B       0x64                     ; 'd'
+  0x08006582:  61           DC.B       0x61                     ; 'a'
+  0x08006583:  79           DC.B       0x79                     ; 'y'
+  0x08006584:  00           DC.B       0x00                     ; '\0'
+  0x08006585:  57           DC.B       0x57                     ; 'W'
+  0x08006586:  65           DC.B       0x65                     ; 'e'
+  0x08006587:  64           DC.B       0x64                     ; 'd'
+  0x08006588:  6E           DC.B       0x6E                     ; 'n'
+  0x08006589:  65           DC.B       0x65                     ; 'e'
+  0x0800658A:  73           DC.B       0x73                     ; 's'
+  0x0800658B:  64           DC.B       0x64                     ; 'd'
+  0x0800658C:  61           DC.B       0x61                     ; 'a'
+  0x0800658D:  79           DC.B       0x79                     ; 'y'
+  0x0800658E:  00           DC.B       0x00                     ; '\0'
+  0x0800658F:  54           DC.B       0x54                     ; 'T'
+  0x08006590:  68           DC.B       0x68                     ; 'h'
+  0x08006591:  75           DC.B       0x75                     ; 'u'
+  0x08006592:  72           DC.B       0x72                     ; 'r'
+  0x08006593:  73           DC.B       0x73                     ; 's'
+  0x08006594:  64           DC.B       0x64                     ; 'd'
+  0x08006595:  61           DC.B       0x61                     ; 'a'
+  0x08006596:  79           DC.B       0x79                     ; 'y'
+  0x08006597:  00           DC.B       0x00                     ; '\0'
+  0x08006598:  46           DC.B       0x46                     ; 'F'
+  0x08006599:  72           DC.B       0x72                     ; 'r'
+  0x0800659A:  69           DC.B       0x69                     ; 'i'
+  0x0800659B:  64           DC.B       0x64                     ; 'd'
+  0x0800659C:  61           DC.B       0x61                     ; 'a'
+  0x0800659D:  79           DC.B       0x79                     ; 'y'
+  0x0800659E:  00           DC.B       0x00                     ; '\0'
+  0x0800659F:  53           DC.B       0x53                     ; 'S'
+  0x080065A0:  61           DC.B       0x61                     ; 'a'
+  0x080065A1:  74           DC.B       0x74                     ; 't'
+  0x080065A2:  75           DC.B       0x75                     ; 'u'
+  0x080065A3:  72           DC.B       0x72                     ; 'r'
+  0x080065A4:  64           DC.B       0x64                     ; 'd'
+  0x080065A5:  61           DC.B       0x61                     ; 'a'
+  0x080065A6:  79           DC.B       0x79                     ; 'y'
+  0x080065A7:  00           DC.B       0x00                     ; '\0'
+  0x080065A8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc..L.str from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=2, align=1

+
+  0x080065A9:  43           DC.B       0x43                     ; 'C'
+  0x080065AA:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_data_utf8_period from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=2, align=1

+
+
__SEGGER_RTL_data_utf8_period:
+  0x080065AB:  2E           DC.B       0x2E                     ; '.'
+  0x080065AC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.4 from PowerPro_lto.o, size=17, align=1

+
+  0x080065AD:  42           DC.B       0x42                     ; 'B'
+  0x080065AE:  55           DC.B       0x55                     ; 'U'
+  0x080065AF:  54           DC.B       0x54                     ; 'T'
+  0x080065B0:  54           DC.B       0x54                     ; 'T'
+  0x080065B1:  4F           DC.B       0x4F                     ; 'O'
+  0x080065B2:  4E           DC.B       0x4E                     ; 'N'
+  0x080065B3:  3A           DC.B       0x3A                     ; ':'
+  0x080065B4:  20           DC.B       0x20                     ; ' '
+  0x080065B5:  4F           DC.B       0x4F                     ; 'O'
+  0x080065B6:  66           DC.B       0x66                     ; 'f'
+  0x080065B7:  66           DC.B       0x66                     ; 'f'
+  0x080065B8:  20           DC.B       0x20                     ; ' '
+  0x080065B9:  4D           DC.B       0x4D                     ; 'M'
+  0x080065BA:  6F           DC.B       0x6F                     ; 'o'
+  0x080065BB:  64           DC.B       0x64                     ; 'd'
+  0x080065BC:  65           DC.B       0x65                     ; 'e'
+  0x080065BD:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12 from PowerPro_lto.o, size=25, align=1

+
+  0x080065BE:  6D           DC.B       0x6D                     ; 'm'
+  0x080065BF:  6F           DC.B       0x6F                     ; 'o'
+  0x080065C0:  64           DC.B       0x64                     ; 'd'
+  0x080065C1:  65           DC.B       0x65                     ; 'e'
+  0x080065C2:  20           DC.B       0x20                     ; ' '
+  0x080065C3:  6E           DC.B       0x6E                     ; 'n'
+  0x080065C4:  6F           DC.B       0x6F                     ; 'o'
+  0x080065C5:  74           DC.B       0x74                     ; 't'
+  0x080065C6:  20           DC.B       0x20                     ; ' '
+  0x080065C7:  79           DC.B       0x79                     ; 'y'
+  0x080065C8:  65           DC.B       0x65                     ; 'e'
+  0x080065C9:  74           DC.B       0x74                     ; 't'
+  0x080065CA:  20           DC.B       0x20                     ; ' '
+  0x080065CB:  69           DC.B       0x69                     ; 'i'
+  0x080065CC:  6D           DC.B       0x6D                     ; 'm'
+  0x080065CD:  70           DC.B       0x70                     ; 'p'
+  0x080065CE:  6C           DC.B       0x6C                     ; 'l'
+  0x080065CF:  65           DC.B       0x65                     ; 'e'
+  0x080065D0:  6D           DC.B       0x6D                     ; 'm'
+  0x080065D1:  65           DC.B       0x65                     ; 'e'
+  0x080065D2:  6E           DC.B       0x6E                     ; 'n'
+  0x080065D3:  74           DC.B       0x74                     ; 't'
+  0x080065D4:  65           DC.B       0x65                     ; 'e'
+  0x080065D5:  64           DC.B       0x64                     ; 'd'
+  0x080065D6:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.14 from PowerPro_lto.o, size=17, align=1

+
+  0x080065D7:  4A           DC.B       0x4A                     ; 'J'
+  0x080065D8:  75           DC.B       0x75                     ; 'u'
+  0x080065D9:  6D           DC.B       0x6D                     ; 'm'
+  0x080065DA:  70           DC.B       0x70                     ; 'p'
+  0x080065DB:  20           DC.B       0x20                     ; ' '
+  0x080065DC:  68           DC.B       0x68                     ; 'h'
+  0x080065DD:  61           DC.B       0x61                     ; 'a'
+  0x080065DE:  73           DC.B       0x73                     ; 's'
+  0x080065DF:  20           DC.B       0x20                     ; ' '
+  0x080065E0:  66           DC.B       0x66                     ; 'f'
+  0x080065E1:  61           DC.B       0x61                     ; 'a'
+  0x080065E2:  69           DC.B       0x69                     ; 'i'
+  0x080065E3:  6C           DC.B       0x6C                     ; 'l'
+  0x080065E4:  65           DC.B       0x65                     ; 'e'
+  0x080065E5:  64           DC.B       0x64                     ; 'd'
+  0x080065E6:  21           DC.B       0x21                     ; '!'
+  0x080065E7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.5 from PowerPro_lto.o, size=17, align=1

+
+  0x080065E8:  4D           DC.B       0x4D                     ; 'M'
+  0x080065E9:  42           DC.B       0x42                     ; 'B'
+  0x080065EA:  20           DC.B       0x20                     ; ' '
+  0x080065EB:  44           DC.B       0x44                     ; 'D'
+  0x080065EC:  4D           DC.B       0x4D                     ; 'M'
+  0x080065ED:  41           DC.B       0x41                     ; 'A'
+  0x080065EE:  20           DC.B       0x20                     ; ' '
+  0x080065EF:  45           DC.B       0x45                     ; 'E'
+  0x080065F0:  72           DC.B       0x72                     ; 'r'
+  0x080065F1:  72           DC.B       0x72                     ; 'r'
+  0x080065F2:  6F           DC.B       0x6F                     ; 'o'
+  0x080065F3:  72           DC.B       0x72                     ; 'r'
+  0x080065F4:  21           DC.B       0x21                     ; '!'
+  0x080065F5:  20           DC.B       0x20                     ; ' '
+  0x080065F6:  0A           DC.B       0x0A                     ; '\n'
+  0x080065F7:  0D           DC.B       0x0D                     ; '\r'
+  0x080065F8:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.6 from PowerPro_lto.o, size=17, align=1

+
+  0x080065F9:  4D           DC.B       0x4D                     ; 'M'
+  0x080065FA:  42           DC.B       0x42                     ; 'B'
+  0x080065FB:  20           DC.B       0x20                     ; ' '
+  0x080065FC:  4F           DC.B       0x4F                     ; 'O'
+  0x080065FD:  52           DC.B       0x52                     ; 'R'
+  0x080065FE:  45           DC.B       0x45                     ; 'E'
+  0x080065FF:  20           DC.B       0x20                     ; ' '
+  0x08006600:  45           DC.B       0x45                     ; 'E'
+  0x08006601:  72           DC.B       0x72                     ; 'r'
+  0x08006602:  72           DC.B       0x72                     ; 'r'
+  0x08006603:  6F           DC.B       0x6F                     ; 'o'
+  0x08006604:  72           DC.B       0x72                     ; 'r'
+  0x08006605:  21           DC.B       0x21                     ; '!'
+  0x08006606:  20           DC.B       0x20                     ; ' '
+  0x08006607:  0A           DC.B       0x0A                     ; '\n'
+  0x08006608:  0D           DC.B       0x0D                     ; '\r'
+  0x08006609:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.104 from PowerPro_lto.o, size=17, align=1

+
+  0x0800660A:  45           DC.B       0x45                     ; 'E'
+  0x0800660B:  52           DC.B       0x52                     ; 'R'
+  0x0800660C:  52           DC.B       0x52                     ; 'R'
+  0x0800660D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800660E:  52           DC.B       0x52                     ; 'R'
+  0x0800660F:  20           DC.B       0x20                     ; ' '
+  0x08006610:  55           DC.B       0x55                     ; 'U'
+  0x08006611:  61           DC.B       0x61                     ; 'a'
+  0x08006612:  72           DC.B       0x72                     ; 'r'
+  0x08006613:  74           DC.B       0x74                     ; 't'
+  0x08006614:  20           DC.B       0x20                     ; ' '
+  0x08006615:  49           DC.B       0x49                     ; 'I'
+  0x08006616:  4E           DC.B       0x4E                     ; 'N'
+  0x08006617:  49           DC.B       0x49                     ; 'I'
+  0x08006618:  54           DC.B       0x54                     ; 'T'
+  0x08006619:  0D           DC.B       0x0D                     ; '\r'
+  0x0800661A:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.118 from PowerPro_lto.o, size=45, align=1

+
+  0x0800661B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800661C:  56           DC.B       0x56                     ; 'V'
+  0x0800661D:  50           DC.B       0x50                     ; 'P'
+  0x0800661E:  5F           DC.B       0x5F                     ; '_'
+  0x0800661F:  53           DC.B       0x53                     ; 'S'
+  0x08006620:  4D           DC.B       0x4D                     ; 'M'
+  0x08006621:  5F           DC.B       0x5F                     ; '_'
+  0x08006622:  4F           DC.B       0x4F                     ; 'O'
+  0x08006623:  66           DC.B       0x66                     ; 'f'
+  0x08006624:  66           DC.B       0x66                     ; 'f'
+  0x08006625:  3A           DC.B       0x3A                     ; ':'
+  0x08006626:  20           DC.B       0x20                     ; ' '
+  0x08006627:  4E           DC.B       0x4E                     ; 'N'
+  0x08006628:  45           DC.B       0x45                     ; 'E'
+  0x08006629:  57           DC.B       0x57                     ; 'W'
+  0x0800662A:  5F           DC.B       0x5F                     ; '_'
+  0x0800662B:  53           DC.B       0x53                     ; 'S'
+  0x0800662C:  54           DC.B       0x54                     ; 'T'
+  0x0800662D:  41           DC.B       0x41                     ; 'A'
+  0x0800662E:  54           DC.B       0x54                     ; 'T'
+  0x0800662F:  45           DC.B       0x45                     ; 'E'
+  0x08006630:  3A           DC.B       0x3A                     ; ':'
+  0x08006631:  20           DC.B       0x20                     ; ' '
+  0x08006632:  4C           DC.B       0x4C                     ; 'L'
+  0x08006633:  56           DC.B       0x56                     ; 'V'
+  0x08006634:  50           DC.B       0x50                     ; 'P'
+  0x08006635:  5F           DC.B       0x5F                     ; '_'
+  0x08006636:  45           DC.B       0x45                     ; 'E'
+  0x08006637:  52           DC.B       0x52                     ; 'R'
+  0x08006638:  52           DC.B       0x52                     ; 'R'
+  0x08006639:  4F           DC.B       0x4F                     ; 'O'
+  0x0800663A:  52           DC.B       0x52                     ; 'R'
+  0x0800663B:  5F           DC.B       0x5F                     ; '_'
+  0x0800663C:  46           DC.B       0x46                     ; 'F'
+  0x0800663D:  41           DC.B       0x41                     ; 'A'
+  0x0800663E:  55           DC.B       0x55                     ; 'U'
+  0x0800663F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006640:  54           DC.B       0x54                     ; 'T'
+  0x08006641:  5F           DC.B       0x5F                     ; '_'
+  0x08006642:  49           DC.B       0x49                     ; 'I'
+  0x08006643:  4E           DC.B       0x4E                     ; 'N'
+  0x08006644:  50           DC.B       0x50                     ; 'P'
+  0x08006645:  55           DC.B       0x55                     ; 'U'
+  0x08006646:  54           DC.B       0x54                     ; 'T'
+  0x08006647:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15 from PowerPro_lto.o, size=21, align=1

+
+  0x08006648:  4E           DC.B       0x4E                     ; 'N'
+  0x08006649:  45           DC.B       0x45                     ; 'E'
+  0x0800664A:  57           DC.B       0x57                     ; 'W'
+  0x0800664B:  5F           DC.B       0x5F                     ; '_'
+  0x0800664C:  53           DC.B       0x53                     ; 'S'
+  0x0800664D:  54           DC.B       0x54                     ; 'T'
+  0x0800664E:  41           DC.B       0x41                     ; 'A'
+  0x0800664F:  54           DC.B       0x54                     ; 'T'
+  0x08006650:  45           DC.B       0x45                     ; 'E'
+  0x08006651:  3A           DC.B       0x3A                     ; ':'
+  0x08006652:  20           DC.B       0x20                     ; ' '
+  0x08006653:  4C           DC.B       0x4C                     ; 'L'
+  0x08006654:  56           DC.B       0x56                     ; 'V'
+  0x08006655:  50           DC.B       0x50                     ; 'P'
+  0x08006656:  5F           DC.B       0x5F                     ; '_'
+  0x08006657:  45           DC.B       0x45                     ; 'E'
+  0x08006658:  52           DC.B       0x52                     ; 'R'
+  0x08006659:  52           DC.B       0x52                     ; 'R'
+  0x0800665A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800665B:  52           DC.B       0x52                     ; 'R'
+  0x0800665C:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17 from PowerPro_lto.o, size=9, align=1

+
+  0x0800665D:  4C           DC.B       0x4C                     ; 'L'
+  0x0800665E:  56           DC.B       0x56                     ; 'V'
+  0x0800665F:  50           DC.B       0x50                     ; 'P'
+  0x08006660:  20           DC.B       0x20                     ; ' '
+  0x08006661:  4F           DC.B       0x4F                     ; 'O'
+  0x08006662:  46           DC.B       0x46                     ; 'F'
+  0x08006663:  46           DC.B       0x46                     ; 'F'
+  0x08006664:  21           DC.B       0x21                     ; '!'
+  0x08006665:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24 from PowerPro_lto.o, size=25, align=1

+
+  0x08006666:  4E           DC.B       0x4E                     ; 'N'
+  0x08006667:  45           DC.B       0x45                     ; 'E'
+  0x08006668:  57           DC.B       0x57                     ; 'W'
+  0x08006669:  5F           DC.B       0x5F                     ; '_'
+  0x0800666A:  53           DC.B       0x53                     ; 'S'
+  0x0800666B:  54           DC.B       0x54                     ; 'T'
+  0x0800666C:  41           DC.B       0x41                     ; 'A'
+  0x0800666D:  54           DC.B       0x54                     ; 'T'
+  0x0800666E:  45           DC.B       0x45                     ; 'E'
+  0x0800666F:  3A           DC.B       0x3A                     ; ':'
+  0x08006670:  20           DC.B       0x20                     ; ' '
+  0x08006671:  4C           DC.B       0x4C                     ; 'L'
+  0x08006672:  56           DC.B       0x56                     ; 'V'
+  0x08006673:  50           DC.B       0x50                     ; 'P'
+  0x08006674:  5F           DC.B       0x5F                     ; '_'
+  0x08006675:  4D           DC.B       0x4D                     ; 'M'
+  0x08006676:  41           DC.B       0x41                     ; 'A'
+  0x08006677:  4E           DC.B       0x4E                     ; 'N'
+  0x08006678:  55           DC.B       0x55                     ; 'U'
+  0x08006679:  41           DC.B       0x41                     ; 'A'
+  0x0800667A:  4C           DC.B       0x4C                     ; 'L'
+  0x0800667B:  5F           DC.B       0x5F                     ; '_'
+  0x0800667C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800667D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800667E:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.124 from PowerPro_lto.o, size=53, align=1

+
+  0x0800667F:  4C           DC.B       0x4C                     ; 'L'
+  0x08006680:  56           DC.B       0x56                     ; 'V'
+  0x08006681:  50           DC.B       0x50                     ; 'P'
+  0x08006682:  5F           DC.B       0x5F                     ; '_'
+  0x08006683:  4F           DC.B       0x4F                     ; 'O'
+  0x08006684:  56           DC.B       0x56                     ; 'V'
+  0x08006685:  50           DC.B       0x50                     ; 'P'
+  0x08006686:  5F           DC.B       0x5F                     ; '_'
+  0x08006687:  53           DC.B       0x53                     ; 'S'
+  0x08006688:  4D           DC.B       0x4D                     ; 'M'
+  0x08006689:  5F           DC.B       0x5F                     ; '_'
+  0x0800668A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800668B:  66           DC.B       0x66                     ; 'f'
+  0x0800668C:  66           DC.B       0x66                     ; 'f'
+  0x0800668D:  3A           DC.B       0x3A                     ; ':'
+  0x0800668E:  20           DC.B       0x20                     ; ' '
+  0x0800668F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006690:  45           DC.B       0x45                     ; 'E'
+  0x08006691:  57           DC.B       0x57                     ; 'W'
+  0x08006692:  5F           DC.B       0x5F                     ; '_'
+  0x08006693:  53           DC.B       0x53                     ; 'S'
+  0x08006694:  54           DC.B       0x54                     ; 'T'
+  0x08006695:  41           DC.B       0x41                     ; 'A'
+  0x08006696:  54           DC.B       0x54                     ; 'T'
+  0x08006697:  45           DC.B       0x45                     ; 'E'
+  0x08006698:  3A           DC.B       0x3A                     ; ':'
+  0x08006699:  20           DC.B       0x20                     ; ' '
+  0x0800669A:  4C           DC.B       0x4C                     ; 'L'
+  0x0800669B:  56           DC.B       0x56                     ; 'V'
+  0x0800669C:  50           DC.B       0x50                     ; 'P'
+  0x0800669D:  5F           DC.B       0x5F                     ; '_'
+  0x0800669E:  4F           DC.B       0x4F                     ; 'O'
+  0x0800669F:  56           DC.B       0x56                     ; 'V'
+  0x080066A0:  50           DC.B       0x50                     ; 'P'
+  0x080066A1:  5F           DC.B       0x5F                     ; '_'
+  0x080066A2:  45           DC.B       0x45                     ; 'E'
+  0x080066A3:  52           DC.B       0x52                     ; 'R'
+  0x080066A4:  52           DC.B       0x52                     ; 'R'
+  0x080066A5:  4F           DC.B       0x4F                     ; 'O'
+  0x080066A6:  52           DC.B       0x52                     ; 'R'
+  0x080066A7:  5F           DC.B       0x5F                     ; '_'
+  0x080066A8:  46           DC.B       0x46                     ; 'F'
+  0x080066A9:  41           DC.B       0x41                     ; 'A'
+  0x080066AA:  55           DC.B       0x55                     ; 'U'
+  0x080066AB:  4C           DC.B       0x4C                     ; 'L'
+  0x080066AC:  54           DC.B       0x54                     ; 'T'
+  0x080066AD:  5F           DC.B       0x5F                     ; '_'
+  0x080066AE:  49           DC.B       0x49                     ; 'I'
+  0x080066AF:  4E           DC.B       0x4E                     ; 'N'
+  0x080066B0:  50           DC.B       0x50                     ; 'P'
+  0x080066B1:  55           DC.B       0x55                     ; 'U'
+  0x080066B2:  54           DC.B       0x54                     ; 'T'
+  0x080066B3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.127 from PowerPro_lto.o, size=25, align=1

+
+  0x080066B4:  4E           DC.B       0x4E                     ; 'N'
+  0x080066B5:  45           DC.B       0x45                     ; 'E'
+  0x080066B6:  57           DC.B       0x57                     ; 'W'
+  0x080066B7:  5F           DC.B       0x5F                     ; '_'
+  0x080066B8:  53           DC.B       0x53                     ; 'S'
+  0x080066B9:  54           DC.B       0x54                     ; 'T'
+  0x080066BA:  41           DC.B       0x41                     ; 'A'
+  0x080066BB:  54           DC.B       0x54                     ; 'T'
+  0x080066BC:  45           DC.B       0x45                     ; 'E'
+  0x080066BD:  3A           DC.B       0x3A                     ; ':'
+  0x080066BE:  20           DC.B       0x20                     ; ' '
+  0x080066BF:  4C           DC.B       0x4C                     ; 'L'
+  0x080066C0:  56           DC.B       0x56                     ; 'V'
+  0x080066C1:  50           DC.B       0x50                     ; 'P'
+  0x080066C2:  5F           DC.B       0x5F                     ; '_'
+  0x080066C3:  4F           DC.B       0x4F                     ; 'O'
+  0x080066C4:  56           DC.B       0x56                     ; 'V'
+  0x080066C5:  50           DC.B       0x50                     ; 'P'
+  0x080066C6:  5F           DC.B       0x5F                     ; '_'
+  0x080066C7:  45           DC.B       0x45                     ; 'E'
+  0x080066C8:  52           DC.B       0x52                     ; 'R'
+  0x080066C9:  52           DC.B       0x52                     ; 'R'
+  0x080066CA:  4F           DC.B       0x4F                     ; 'O'
+  0x080066CB:  52           DC.B       0x52                     ; 'R'
+  0x080066CC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24.125 from PowerPro_lto.o, size=29, align=1

+
+  0x080066CD:  4E           DC.B       0x4E                     ; 'N'
+  0x080066CE:  45           DC.B       0x45                     ; 'E'
+  0x080066CF:  57           DC.B       0x57                     ; 'W'
+  0x080066D0:  5F           DC.B       0x5F                     ; '_'
+  0x080066D1:  53           DC.B       0x53                     ; 'S'
+  0x080066D2:  54           DC.B       0x54                     ; 'T'
+  0x080066D3:  41           DC.B       0x41                     ; 'A'
+  0x080066D4:  54           DC.B       0x54                     ; 'T'
+  0x080066D5:  45           DC.B       0x45                     ; 'E'
+  0x080066D6:  3A           DC.B       0x3A                     ; ':'
+  0x080066D7:  20           DC.B       0x20                     ; ' '
+  0x080066D8:  4C           DC.B       0x4C                     ; 'L'
+  0x080066D9:  56           DC.B       0x56                     ; 'V'
+  0x080066DA:  50           DC.B       0x50                     ; 'P'
+  0x080066DB:  5F           DC.B       0x5F                     ; '_'
+  0x080066DC:  4F           DC.B       0x4F                     ; 'O'
+  0x080066DD:  56           DC.B       0x56                     ; 'V'
+  0x080066DE:  50           DC.B       0x50                     ; 'P'
+  0x080066DF:  5F           DC.B       0x5F                     ; '_'
+  0x080066E0:  4D           DC.B       0x4D                     ; 'M'
+  0x080066E1:  41           DC.B       0x41                     ; 'A'
+  0x080066E2:  4E           DC.B       0x4E                     ; 'N'
+  0x080066E3:  55           DC.B       0x55                     ; 'U'
+  0x080066E4:  41           DC.B       0x41                     ; 'A'
+  0x080066E5:  4C           DC.B       0x4C                     ; 'L'
+  0x080066E6:  5F           DC.B       0x5F                     ; '_'
+  0x080066E7:  4F           DC.B       0x4F                     ; 'O'
+  0x080066E8:  4E           DC.B       0x4E                     ; 'N'
+  0x080066E9:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11.135 from PowerPro_lto.o, size=25, align=1

+
+  0x080066EA:  4E           DC.B       0x4E                     ; 'N'
+  0x080066EB:  45           DC.B       0x45                     ; 'E'
+  0x080066EC:  57           DC.B       0x57                     ; 'W'
+  0x080066ED:  5F           DC.B       0x5F                     ; '_'
+  0x080066EE:  53           DC.B       0x53                     ; 'S'
+  0x080066EF:  54           DC.B       0x54                     ; 'T'
+  0x080066F0:  41           DC.B       0x41                     ; 'A'
+  0x080066F1:  54           DC.B       0x54                     ; 'T'
+  0x080066F2:  45           DC.B       0x45                     ; 'E'
+  0x080066F3:  3A           DC.B       0x3A                     ; ':'
+  0x080066F4:  20           DC.B       0x20                     ; ' '
+  0x080066F5:  4D           DC.B       0x4D                     ; 'M'
+  0x080066F6:  41           DC.B       0x41                     ; 'A'
+  0x080066F7:  49           DC.B       0x49                     ; 'I'
+  0x080066F8:  4E           DC.B       0x4E                     ; 'N'
+  0x080066F9:  53           DC.B       0x53                     ; 'S'
+  0x080066FA:  57           DC.B       0x57                     ; 'W'
+  0x080066FB:  49           DC.B       0x49                     ; 'I'
+  0x080066FC:  54           DC.B       0x54                     ; 'T'
+  0x080066FD:  43           DC.B       0x43                     ; 'C'
+  0x080066FE:  48           DC.B       0x48                     ; 'H'
+  0x080066FF:  5F           DC.B       0x5F                     ; '_'
+  0x08006700:  4F           DC.B       0x4F                     ; 'O'
+  0x08006701:  4E           DC.B       0x4E                     ; 'N'
+  0x08006702:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.147 from PowerPro_lto.o, size=45, align=1

+
+  0x08006703:  4F           DC.B       0x4F                     ; 'O'
+  0x08006704:  56           DC.B       0x56                     ; 'V'
+  0x08006705:  50           DC.B       0x50                     ; 'P'
+  0x08006706:  5F           DC.B       0x5F                     ; '_'
+  0x08006707:  53           DC.B       0x53                     ; 'S'
+  0x08006708:  4D           DC.B       0x4D                     ; 'M'
+  0x08006709:  5F           DC.B       0x5F                     ; '_'
+  0x0800670A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800670B:  66           DC.B       0x66                     ; 'f'
+  0x0800670C:  66           DC.B       0x66                     ; 'f'
+  0x0800670D:  3A           DC.B       0x3A                     ; ':'
+  0x0800670E:  20           DC.B       0x20                     ; ' '
+  0x0800670F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006710:  45           DC.B       0x45                     ; 'E'
+  0x08006711:  57           DC.B       0x57                     ; 'W'
+  0x08006712:  5F           DC.B       0x5F                     ; '_'
+  0x08006713:  53           DC.B       0x53                     ; 'S'
+  0x08006714:  54           DC.B       0x54                     ; 'T'
+  0x08006715:  41           DC.B       0x41                     ; 'A'
+  0x08006716:  54           DC.B       0x54                     ; 'T'
+  0x08006717:  45           DC.B       0x45                     ; 'E'
+  0x08006718:  3A           DC.B       0x3A                     ; ':'
+  0x08006719:  20           DC.B       0x20                     ; ' '
+  0x0800671A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800671B:  56           DC.B       0x56                     ; 'V'
+  0x0800671C:  50           DC.B       0x50                     ; 'P'
+  0x0800671D:  5F           DC.B       0x5F                     ; '_'
+  0x0800671E:  45           DC.B       0x45                     ; 'E'
+  0x0800671F:  52           DC.B       0x52                     ; 'R'
+  0x08006720:  52           DC.B       0x52                     ; 'R'
+  0x08006721:  4F           DC.B       0x4F                     ; 'O'
+  0x08006722:  52           DC.B       0x52                     ; 'R'
+  0x08006723:  5F           DC.B       0x5F                     ; '_'
+  0x08006724:  46           DC.B       0x46                     ; 'F'
+  0x08006725:  41           DC.B       0x41                     ; 'A'
+  0x08006726:  55           DC.B       0x55                     ; 'U'
+  0x08006727:  4C           DC.B       0x4C                     ; 'L'
+  0x08006728:  54           DC.B       0x54                     ; 'T'
+  0x08006729:  5F           DC.B       0x5F                     ; '_'
+  0x0800672A:  49           DC.B       0x49                     ; 'I'
+  0x0800672B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800672C:  50           DC.B       0x50                     ; 'P'
+  0x0800672D:  55           DC.B       0x55                     ; 'U'
+  0x0800672E:  54           DC.B       0x54                     ; 'T'
+  0x0800672F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.150 from PowerPro_lto.o, size=21, align=1

+
+  0x08006730:  4E           DC.B       0x4E                     ; 'N'
+  0x08006731:  45           DC.B       0x45                     ; 'E'
+  0x08006732:  57           DC.B       0x57                     ; 'W'
+  0x08006733:  5F           DC.B       0x5F                     ; '_'
+  0x08006734:  53           DC.B       0x53                     ; 'S'
+  0x08006735:  54           DC.B       0x54                     ; 'T'
+  0x08006736:  41           DC.B       0x41                     ; 'A'
+  0x08006737:  54           DC.B       0x54                     ; 'T'
+  0x08006738:  45           DC.B       0x45                     ; 'E'
+  0x08006739:  3A           DC.B       0x3A                     ; ':'
+  0x0800673A:  20           DC.B       0x20                     ; ' '
+  0x0800673B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800673C:  56           DC.B       0x56                     ; 'V'
+  0x0800673D:  50           DC.B       0x50                     ; 'P'
+  0x0800673E:  5F           DC.B       0x5F                     ; '_'
+  0x0800673F:  45           DC.B       0x45                     ; 'E'
+  0x08006740:  52           DC.B       0x52                     ; 'R'
+  0x08006741:  52           DC.B       0x52                     ; 'R'
+  0x08006742:  4F           DC.B       0x4F                     ; 'O'
+  0x08006743:  52           DC.B       0x52                     ; 'R'
+  0x08006744:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17.152 from PowerPro_lto.o, size=9, align=1

+
+  0x08006745:  4F           DC.B       0x4F                     ; 'O'
+  0x08006746:  56           DC.B       0x56                     ; 'V'
+  0x08006747:  50           DC.B       0x50                     ; 'P'
+  0x08006748:  20           DC.B       0x20                     ; ' '
+  0x08006749:  4F           DC.B       0x4F                     ; 'O'
+  0x0800674A:  46           DC.B       0x46                     ; 'F'
+  0x0800674B:  46           DC.B       0x46                     ; 'F'
+  0x0800674C:  21           DC.B       0x21                     ; '!'
+  0x0800674D:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.24.148 from PowerPro_lto.o, size=25, align=1

+
+  0x0800674E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800674F:  45           DC.B       0x45                     ; 'E'
+  0x08006750:  57           DC.B       0x57                     ; 'W'
+  0x08006751:  5F           DC.B       0x5F                     ; '_'
+  0x08006752:  53           DC.B       0x53                     ; 'S'
+  0x08006753:  54           DC.B       0x54                     ; 'T'
+  0x08006754:  41           DC.B       0x41                     ; 'A'
+  0x08006755:  54           DC.B       0x54                     ; 'T'
+  0x08006756:  45           DC.B       0x45                     ; 'E'
+  0x08006757:  3A           DC.B       0x3A                     ; ':'
+  0x08006758:  20           DC.B       0x20                     ; ' '
+  0x08006759:  4F           DC.B       0x4F                     ; 'O'
+  0x0800675A:  56           DC.B       0x56                     ; 'V'
+  0x0800675B:  50           DC.B       0x50                     ; 'P'
+  0x0800675C:  5F           DC.B       0x5F                     ; '_'
+  0x0800675D:  4D           DC.B       0x4D                     ; 'M'
+  0x0800675E:  41           DC.B       0x41                     ; 'A'
+  0x0800675F:  4E           DC.B       0x4E                     ; 'N'
+  0x08006760:  55           DC.B       0x55                     ; 'U'
+  0x08006761:  41           DC.B       0x41                     ; 'A'
+  0x08006762:  4C           DC.B       0x4C                     ; 'L'
+  0x08006763:  5F           DC.B       0x5F                     ; '_'
+  0x08006764:  4F           DC.B       0x4F                     ; 'O'
+  0x08006765:  4E           DC.B       0x4E                     ; 'N'
+  0x08006766:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.22.162 from PowerPro_lto.o, size=41, align=1

+
+  0x08006767:  4E           DC.B       0x4E                     ; 'N'
+  0x08006768:  45           DC.B       0x45                     ; 'E'
+  0x08006769:  57           DC.B       0x57                     ; 'W'
+  0x0800676A:  5F           DC.B       0x5F                     ; '_'
+  0x0800676B:  53           DC.B       0x53                     ; 'S'
+  0x0800676C:  54           DC.B       0x54                     ; 'T'
+  0x0800676D:  41           DC.B       0x41                     ; 'A'
+  0x0800676E:  54           DC.B       0x54                     ; 'T'
+  0x0800676F:  45           DC.B       0x45                     ; 'E'
+  0x08006770:  3A           DC.B       0x3A                     ; ':'
+  0x08006771:  20           DC.B       0x20                     ; ' '
+  0x08006772:  53           DC.B       0x53                     ; 'S'
+  0x08006773:  45           DC.B       0x45                     ; 'E'
+  0x08006774:  43           DC.B       0x43                     ; 'C'
+  0x08006775:  4F           DC.B       0x4F                     ; 'O'
+  0x08006776:  4E           DC.B       0x4E                     ; 'N'
+  0x08006777:  44           DC.B       0x44                     ; 'D'
+  0x08006778:  41           DC.B       0x41                     ; 'A'
+  0x08006779:  52           DC.B       0x52                     ; 'R'
+  0x0800677A:  59           DC.B       0x59                     ; 'Y'
+  0x0800677B:  50           DC.B       0x50                     ; 'P'
+  0x0800677C:  52           DC.B       0x52                     ; 'R'
+  0x0800677D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800677E:  54           DC.B       0x54                     ; 'T'
+  0x0800677F:  45           DC.B       0x45                     ; 'E'
+  0x08006780:  43           DC.B       0x43                     ; 'C'
+  0x08006781:  54           DC.B       0x54                     ; 'T'
+  0x08006782:  49           DC.B       0x49                     ; 'I'
+  0x08006783:  4F           DC.B       0x4F                     ; 'O'
+  0x08006784:  4E           DC.B       0x4E                     ; 'N'
+  0x08006785:  5F           DC.B       0x5F                     ; '_'
+  0x08006786:  4D           DC.B       0x4D                     ; 'M'
+  0x08006787:  41           DC.B       0x41                     ; 'A'
+  0x08006788:  4E           DC.B       0x4E                     ; 'N'
+  0x08006789:  55           DC.B       0x55                     ; 'U'
+  0x0800678A:  41           DC.B       0x41                     ; 'A'
+  0x0800678B:  4C           DC.B       0x4C                     ; 'L'
+  0x0800678C:  5F           DC.B       0x5F                     ; '_'
+  0x0800678D:  4F           DC.B       0x4F                     ; 'O'
+  0x0800678E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800678F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.9.178 from PowerPro_lto.o, size=29, align=1

+
+  0x08006790:  46           DC.B       0x46                     ; 'F'
+  0x08006791:  41           DC.B       0x41                     ; 'A'
+  0x08006792:  55           DC.B       0x55                     ; 'U'
+  0x08006793:  4C           DC.B       0x4C                     ; 'L'
+  0x08006794:  54           DC.B       0x54                     ; 'T'
+  0x08006795:  20           DC.B       0x20                     ; ' '
+  0x08006796:  56           DC.B       0x56                     ; 'V'
+  0x08006797:  4F           DC.B       0x4F                     ; 'O'
+  0x08006798:  4C           DC.B       0x4C                     ; 'L'
+  0x08006799:  54           DC.B       0x54                     ; 'T'
+  0x0800679A:  41           DC.B       0x41                     ; 'A'
+  0x0800679B:  47           DC.B       0x47                     ; 'G'
+  0x0800679C:  45           DC.B       0x45                     ; 'E'
+  0x0800679D:  20           DC.B       0x20                     ; ' '
+  0x0800679E:  44           DC.B       0x44                     ; 'D'
+  0x0800679F:  52           DC.B       0x52                     ; 'R'
+  0x080067A0:  4F           DC.B       0x4F                     ; 'O'
+  0x080067A1:  50           DC.B       0x50                     ; 'P'
+  0x080067A2:  20           DC.B       0x20                     ; ' '
+  0x080067A3:  44           DC.B       0x44                     ; 'D'
+  0x080067A4:  45           DC.B       0x45                     ; 'E'
+  0x080067A5:  54           DC.B       0x54                     ; 'T'
+  0x080067A6:  45           DC.B       0x45                     ; 'E'
+  0x080067A7:  43           DC.B       0x43                     ; 'C'
+  0x080067A8:  54           DC.B       0x54                     ; 'T'
+  0x080067A9:  45           DC.B       0x45                     ; 'E'
+  0x080067AA:  44           DC.B       0x44                     ; 'D'
+  0x080067AB:  21           DC.B       0x21                     ; '!'
+  0x080067AC:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.15.173 from PowerPro_lto.o, size=37, align=1

+
+  0x080067AD:  4E           DC.B       0x4E                     ; 'N'
+  0x080067AE:  45           DC.B       0x45                     ; 'E'
+  0x080067AF:  57           DC.B       0x57                     ; 'W'
+  0x080067B0:  5F           DC.B       0x5F                     ; '_'
+  0x080067B1:  53           DC.B       0x53                     ; 'S'
+  0x080067B2:  54           DC.B       0x54                     ; 'T'
+  0x080067B3:  41           DC.B       0x41                     ; 'A'
+  0x080067B4:  54           DC.B       0x54                     ; 'T'
+  0x080067B5:  45           DC.B       0x45                     ; 'E'
+  0x080067B6:  3A           DC.B       0x3A                     ; ':'
+  0x080067B7:  20           DC.B       0x20                     ; ' '
+  0x080067B8:  53           DC.B       0x53                     ; 'S'
+  0x080067B9:  45           DC.B       0x45                     ; 'E'
+  0x080067BA:  43           DC.B       0x43                     ; 'C'
+  0x080067BB:  4F           DC.B       0x4F                     ; 'O'
+  0x080067BC:  4E           DC.B       0x4E                     ; 'N'
+  0x080067BD:  44           DC.B       0x44                     ; 'D'
+  0x080067BE:  41           DC.B       0x41                     ; 'A'
+  0x080067BF:  52           DC.B       0x52                     ; 'R'
+  0x080067C0:  59           DC.B       0x59                     ; 'Y'
+  0x080067C1:  50           DC.B       0x50                     ; 'P'
+  0x080067C2:  52           DC.B       0x52                     ; 'R'
+  0x080067C3:  4F           DC.B       0x4F                     ; 'O'
+  0x080067C4:  54           DC.B       0x54                     ; 'T'
+  0x080067C5:  45           DC.B       0x45                     ; 'E'
+  0x080067C6:  43           DC.B       0x43                     ; 'C'
+  0x080067C7:  54           DC.B       0x54                     ; 'T'
+  0x080067C8:  49           DC.B       0x49                     ; 'I'
+  0x080067C9:  4F           DC.B       0x4F                     ; 'O'
+  0x080067CA:  4E           DC.B       0x4E                     ; 'N'
+  0x080067CB:  5F           DC.B       0x5F                     ; '_'
+  0x080067CC:  45           DC.B       0x45                     ; 'E'
+  0x080067CD:  52           DC.B       0x52                     ; 'R'
+  0x080067CE:  52           DC.B       0x52                     ; 'R'
+  0x080067CF:  4F           DC.B       0x4F                     ; 'O'
+  0x080067D0:  52           DC.B       0x52                     ; 'R'
+  0x080067D1:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str from PowerPro_lto.o, size=9, align=1

+
+  0x080067D2:  6D           DC.B       0x6D                     ; 'm'
+  0x080067D3:  6F           DC.B       0x6F                     ; 'o'
+  0x080067D4:  64           DC.B       0x64                     ; 'd'
+  0x080067D5:  65           DC.B       0x65                     ; 'e'
+  0x080067D6:  3D           DC.B       0x3D                     ; '='
+  0x080067D7:  25           DC.B       0x25                     ; '%'
+  0x080067D8:  69           DC.B       0x69                     ; 'i'
+  0x080067D9:  0A           DC.B       0x0A                     ; '\n'
+  0x080067DA:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc._DoInit._aInitStr from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=17, align=1

+
+
_DoInit._aInitStr:
+  0x080067DB:  00           DC.B       0x00                     ; '\0'
+  0x080067DC:  00           DC.B       0x00                     ; '\0'
+  0x080067DD:  00           DC.B       0x00                     ; '\0'
+  0x080067DE:  00           DC.B       0x00                     ; '\0'
+  0x080067DF:  00           DC.B       0x00                     ; '\0'
+  0x080067E0:  00           DC.B       0x00                     ; '\0'
+  0x080067E1:  54           DC.B       0x54                     ; 'T'
+  0x080067E2:  54           DC.B       0x54                     ; 'T'
+  0x080067E3:  52           DC.B       0x52                     ; 'R'
+  0x080067E4:  20           DC.B       0x20                     ; ' '
+  0x080067E5:  52           DC.B       0x52                     ; 'R'
+  0x080067E6:  45           DC.B       0x45                     ; 'E'
+  0x080067E7:  47           DC.B       0x47                     ; 'G'
+  0x080067E8:  47           DC.B       0x47                     ; 'G'
+  0x080067E9:  45           DC.B       0x45                     ; 'E'
+  0x080067EA:  53           DC.B       0x53                     ; 'S'
+  0x080067EB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc..L.str from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=9, align=1

+
+  0x080067EC:  54           DC.B       0x54                     ; 'T'
+  0x080067ED:  65           DC.B       0x65                     ; 'e'
+  0x080067EE:  72           DC.B       0x72                     ; 'r'
+  0x080067EF:  6D           DC.B       0x6D                     ; 'm'
+  0x080067F0:  69           DC.B       0x69                     ; 'i'
+  0x080067F1:  6E           DC.B       0x6E                     ; 'n'
+  0x080067F2:  61           DC.B       0x61                     ; 'a'
+  0x080067F3:  6C           DC.B       0x6C                     ; 'l'
+  0x080067F4:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_date_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=9, align=1

+
+
__SEGGER_RTL_c_locale_date_format:
+  0x080067F5:  25           DC.B       0x25                     ; '%'
+  0x080067F6:  6D           DC.B       0x6D                     ; 'm'
+  0x080067F7:  2F           DC.B       0x2F                     ; '/'
+  0x080067F8:  25           DC.B       0x25                     ; '%'
+  0x080067F9:  64           DC.B       0x64                     ; 'd'
+  0x080067FA:  2F           DC.B       0x2F                     ; '/'
+  0x080067FB:  25           DC.B       0x25                     ; '%'
+  0x080067FC:  79           DC.B       0x79                     ; 'y'
+  0x080067FD:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_time_format from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=9, align=1

+
+
__SEGGER_RTL_c_locale_time_format:
+  0x080067FE:  25           DC.B       0x25                     ; '%'
+  0x080067FF:  48           DC.B       0x48                     ; 'H'
+  0x08006800:  3A           DC.B       0x3A                     ; ':'
+  0x08006801:  25           DC.B       0x25                     ; '%'
+  0x08006802:  4D           DC.B       0x4D                     ; 'M'
+  0x08006803:  3A           DC.B       0x3A                     ; ':'
+  0x08006804:  25           DC.B       0x25                     ; '%'
+  0x08006805:  53           DC.B       0x53                     ; 'S'
+  0x08006806:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_abbrev_day_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=29, align=1

+
+
__SEGGER_RTL_c_locale_abbrev_day_names:
+  0x08006807:  53           DC.B       0x53                     ; 'S'
+  0x08006808:  75           DC.B       0x75                     ; 'u'
+  0x08006809:  6E           DC.B       0x6E                     ; 'n'
+  0x0800680A:  00           DC.B       0x00                     ; '\0'
+  0x0800680B:  4D           DC.B       0x4D                     ; 'M'
+  0x0800680C:  6F           DC.B       0x6F                     ; 'o'
+  0x0800680D:  6E           DC.B       0x6E                     ; 'n'
+  0x0800680E:  00           DC.B       0x00                     ; '\0'
+  0x0800680F:  54           DC.B       0x54                     ; 'T'
+  0x08006810:  75           DC.B       0x75                     ; 'u'
+  0x08006811:  65           DC.B       0x65                     ; 'e'
+  0x08006812:  00           DC.B       0x00                     ; '\0'
+  0x08006813:  57           DC.B       0x57                     ; 'W'
+  0x08006814:  65           DC.B       0x65                     ; 'e'
+  0x08006815:  64           DC.B       0x64                     ; 'd'
+  0x08006816:  00           DC.B       0x00                     ; '\0'
+  0x08006817:  54           DC.B       0x54                     ; 'T'
+  0x08006818:  68           DC.B       0x68                     ; 'h'
+  0x08006819:  75           DC.B       0x75                     ; 'u'
+  0x0800681A:  00           DC.B       0x00                     ; '\0'
+  0x0800681B:  46           DC.B       0x46                     ; 'F'
+  0x0800681C:  72           DC.B       0x72                     ; 'r'
+  0x0800681D:  69           DC.B       0x69                     ; 'i'
+  0x0800681E:  00           DC.B       0x00                     ; '\0'
+  0x0800681F:  53           DC.B       0x53                     ; 'S'
+  0x08006820:  61           DC.B       0x61                     ; 'a'
+  0x08006821:  74           DC.B       0x74                     ; 't'
+  0x08006822:  00           DC.B       0x00                     ; '\0'
+  0x08006823:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_c_locale_abbrev_month_names from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=49, align=1

+
+
__SEGGER_RTL_c_locale_abbrev_month_names:
+  0x08006824:  4A           DC.B       0x4A                     ; 'J'
+  0x08006825:  61           DC.B       0x61                     ; 'a'
+  0x08006826:  6E           DC.B       0x6E                     ; 'n'
+  0x08006827:  00           DC.B       0x00                     ; '\0'
+  0x08006828:  46           DC.B       0x46                     ; 'F'
+  0x08006829:  65           DC.B       0x65                     ; 'e'
+  0x0800682A:  62           DC.B       0x62                     ; 'b'
+  0x0800682B:  00           DC.B       0x00                     ; '\0'
+  0x0800682C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800682D:  61           DC.B       0x61                     ; 'a'
+  0x0800682E:  72           DC.B       0x72                     ; 'r'
+  0x0800682F:  00           DC.B       0x00                     ; '\0'
+  0x08006830:  41           DC.B       0x41                     ; 'A'
+  0x08006831:  70           DC.B       0x70                     ; 'p'
+  0x08006832:  72           DC.B       0x72                     ; 'r'
+  0x08006833:  00           DC.B       0x00                     ; '\0'
+  0x08006834:  4D           DC.B       0x4D                     ; 'M'
+  0x08006835:  61           DC.B       0x61                     ; 'a'
+  0x08006836:  79           DC.B       0x79                     ; 'y'
+  0x08006837:  00           DC.B       0x00                     ; '\0'
+  0x08006838:  4A           DC.B       0x4A                     ; 'J'
+  0x08006839:  75           DC.B       0x75                     ; 'u'
+  0x0800683A:  6E           DC.B       0x6E                     ; 'n'
+  0x0800683B:  00           DC.B       0x00                     ; '\0'
+  0x0800683C:  4A           DC.B       0x4A                     ; 'J'
+  0x0800683D:  75           DC.B       0x75                     ; 'u'
+  0x0800683E:  6C           DC.B       0x6C                     ; 'l'
+  0x0800683F:  00           DC.B       0x00                     ; '\0'
+  0x08006840:  41           DC.B       0x41                     ; 'A'
+  0x08006841:  75           DC.B       0x75                     ; 'u'
+  0x08006842:  67           DC.B       0x67                     ; 'g'
+  0x08006843:  00           DC.B       0x00                     ; '\0'
+  0x08006844:  53           DC.B       0x53                     ; 'S'
+  0x08006845:  65           DC.B       0x65                     ; 'e'
+  0x08006846:  70           DC.B       0x70                     ; 'p'
+  0x08006847:  00           DC.B       0x00                     ; '\0'
+  0x08006848:  4F           DC.B       0x4F                     ; 'O'
+  0x08006849:  63           DC.B       0x63                     ; 'c'
+  0x0800684A:  74           DC.B       0x74                     ; 't'
+  0x0800684B:  00           DC.B       0x00                     ; '\0'
+  0x0800684C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800684D:  6F           DC.B       0x6F                     ; 'o'
+  0x0800684E:  76           DC.B       0x76                     ; 'v'
+  0x0800684F:  00           DC.B       0x00                     ; '\0'
+  0x08006850:  44           DC.B       0x44                     ; 'D'
+  0x08006851:  65           DC.B       0x65                     ; 'e'
+  0x08006852:  63           DC.B       0x63                     ; 'c'
+  0x08006853:  00           DC.B       0x00                     ; '\0'
+  0x08006854:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_data_empty_string from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=1, align=1

+
+
__SEGGER_RTL_data_empty_string:
+  0x08006855:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_ascii_ctype_mask from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=13, align=1

+
+
__SEGGER_RTL_ascii_ctype_mask:
+  0x08006856:  00           DC.B       0x00                     ; '\0'
+  0x08006857:  07           DC.B       0x07                     ; '\x07'
+  0x08006858:  03           DC.B       0x03                     ; '\x03'
+  0x08006859:  20           DC.B       0x20                     ; ' '
+  0x0800685A:  04           DC.B       0x04                     ; '\x04'
+  0x0800685B:  17           DC.B       0x17                     ; '\x17'
+  0x0800685C:  02           DC.B       0x02                     ; '\x02'
+  0x0800685D:  01           DC.B       0x01                     ; '\x01'
+  0x0800685E:  08           DC.B       0x08                     ; '\b'
+  0x0800685F:  57           DC.B       0x57                     ; 'W'
+  0x08006860:  10           DC.B       0x10                     ; '\x10'
+  0x08006861:  40           DC.B       0x40                     ; '@'
+  0x08006862:  80           DC.B       0x80                     ; '\x80'
+
+

Section .init_array from STM32C0xx_Startup.o, size=4, align=4

+
+  0x08006864:  08000605     DC.W       SystemCoreClockUpdate
+
+

Section .rodata.UARTEx_SetNbDataToProcess.numerator from PowerPro_lto.o, size=8, align=1

+
+
UARTEx_SetNbDataToProcess.numerator:
+  0x08006868:  01           DC.B       0x01                     ; '\x01'
+  0x08006869:  01           DC.B       0x01                     ; '\x01'
+  0x0800686A:  01           DC.B       0x01                     ; '\x01'
+  0x0800686B:  03           DC.B       0x03                     ; '\x03'
+  0x0800686C:  07           DC.B       0x07                     ; '\x07'
+  0x0800686D:  01           DC.B       0x01                     ; '\x01'
+  0x0800686E:  00           DC.B       0x00                     ; '\0'
+  0x0800686F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.UARTEx_SetNbDataToProcess.denominator from PowerPro_lto.o, size=8, align=1

+
+
UARTEx_SetNbDataToProcess.denominator:
+  0x08006870:  08           DC.B       0x08                     ; '\b'
+  0x08006871:  04           DC.B       0x04                     ; '\x04'
+  0x08006872:  02           DC.B       0x02                     ; '\x02'
+  0x08006873:  04           DC.B       0x04                     ; '\x04'
+  0x08006874:  08           DC.B       0x08                     ; '\b'
+  0x08006875:  01           DC.B       0x01                     ; '\x01'
+  0x08006876:  01           DC.B       0x01                     ; '\x01'
+  0x08006877:  01           DC.B       0x01                     ; '\x01'
+
+

Section .rodata..Lstr.3 from PowerPro_lto.o, size=28, align=1

+
+  0x08006878:  42           DC.B       0x42                     ; 'B'
+  0x08006879:  55           DC.B       0x55                     ; 'U'
+  0x0800687A:  54           DC.B       0x54                     ; 'T'
+  0x0800687B:  54           DC.B       0x54                     ; 'T'
+  0x0800687C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800687D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800687E:  3A           DC.B       0x3A                     ; ':'
+  0x0800687F:  20           DC.B       0x20                     ; ' '
+  0x08006880:  41           DC.B       0x41                     ; 'A'
+  0x08006881:  75           DC.B       0x75                     ; 'u'
+  0x08006882:  74           DC.B       0x74                     ; 't'
+  0x08006883:  6F           DC.B       0x6F                     ; 'o'
+  0x08006884:  20           DC.B       0x20                     ; ' '
+  0x08006885:  4D           DC.B       0x4D                     ; 'M'
+  0x08006886:  6F           DC.B       0x6F                     ; 'o'
+  0x08006887:  64           DC.B       0x64                     ; 'd'
+  0x08006888:  65           DC.B       0x65                     ; 'e'
+  0x08006889:  20           DC.B       0x20                     ; ' '
+  0x0800688A:  4D           DC.B       0x4D                     ; 'M'
+  0x0800688B:  61           DC.B       0x61                     ; 'a'
+  0x0800688C:  6E           DC.B       0x6E                     ; 'n'
+  0x0800688D:  75           DC.B       0x75                     ; 'u'
+  0x0800688E:  61           DC.B       0x61                     ; 'a'
+  0x0800688F:  6C           DC.B       0x6C                     ; 'l'
+  0x08006890:  20           DC.B       0x20                     ; ' '
+  0x08006891:  4F           DC.B       0x4F                     ; 'O'
+  0x08006892:  6E           DC.B       0x6E                     ; 'n'
+  0x08006893:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11 from PowerPro_lto.o, size=20, align=1

+
+  0x08006894:  64           DC.B       0x64                     ; 'd'
+  0x08006895:  65           DC.B       0x65                     ; 'e'
+  0x08006896:  62           DC.B       0x62                     ; 'b'
+  0x08006897:  75           DC.B       0x75                     ; 'u'
+  0x08006898:  67           DC.B       0x67                     ; 'g'
+  0x08006899:  20           DC.B       0x20                     ; ' '
+  0x0800689A:  69           DC.B       0x69                     ; 'i'
+  0x0800689B:  6F           DC.B       0x6F                     ; 'o'
+  0x0800689C:  20           DC.B       0x20                     ; ' '
+  0x0800689D:  74           DC.B       0x74                     ; 't'
+  0x0800689E:  65           DC.B       0x65                     ; 'e'
+  0x0800689F:  73           DC.B       0x73                     ; 's'
+  0x080068A0:  74           DC.B       0x74                     ; 't'
+  0x080068A1:  2E           DC.B       0x2E                     ; '.'
+  0x080068A2:  2E           DC.B       0x2E                     ; '.'
+  0x080068A3:  2E           DC.B       0x2E                     ; '.'
+  0x080068A4:  6F           DC.B       0x6F                     ; 'o'
+  0x080068A5:  6B           DC.B       0x6B                     ; 'k'
+  0x080068A6:  0D           DC.B       0x0D                     ; '\r'
+  0x080068A7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.13 from PowerPro_lto.o, size=16, align=1

+
+  0x080068A8:  55           DC.B       0x55                     ; 'U'
+  0x080068A9:  4E           DC.B       0x4E                     ; 'N'
+  0x080068AA:  4B           DC.B       0x4B                     ; 'K'
+  0x080068AB:  4E           DC.B       0x4E                     ; 'N'
+  0x080068AC:  4F           DC.B       0x4F                     ; 'O'
+  0x080068AD:  57           DC.B       0x57                     ; 'W'
+  0x080068AE:  4E           DC.B       0x4E                     ; 'N'
+  0x080068AF:  20           DC.B       0x20                     ; ' '
+  0x080068B0:  43           DC.B       0x43                     ; 'C'
+  0x080068B1:  4F           DC.B       0x4F                     ; 'O'
+  0x080068B2:  4D           DC.B       0x4D                     ; 'M'
+  0x080068B3:  4D           DC.B       0x4D                     ; 'M'
+  0x080068B4:  41           DC.B       0x41                     ; 'A'
+  0x080068B5:  4E           DC.B       0x4E                     ; 'N'
+  0x080068B6:  44           DC.B       0x44                     ; 'D'
+  0x080068B7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.2 from PowerPro_lto.o, size=16, align=1

+
+  0x080068B8:  4D           DC.B       0x4D                     ; 'M'
+  0x080068B9:  42           DC.B       0x42                     ; 'B'
+  0x080068BA:  20           DC.B       0x20                     ; ' '
+  0x080068BB:  46           DC.B       0x46                     ; 'F'
+  0x080068BC:  45           DC.B       0x45                     ; 'E'
+  0x080068BD:  20           DC.B       0x20                     ; ' '
+  0x080068BE:  45           DC.B       0x45                     ; 'E'
+  0x080068BF:  72           DC.B       0x72                     ; 'r'
+  0x080068C0:  72           DC.B       0x72                     ; 'r'
+  0x080068C1:  6F           DC.B       0x6F                     ; 'o'
+  0x080068C2:  72           DC.B       0x72                     ; 'r'
+  0x080068C3:  21           DC.B       0x21                     ; '!'
+  0x080068C4:  20           DC.B       0x20                     ; ' '
+  0x080068C5:  0A           DC.B       0x0A                     ; '\n'
+  0x080068C6:  0D           DC.B       0x0D                     ; '\r'
+  0x080068C7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.3 from PowerPro_lto.o, size=16, align=1

+
+  0x080068C8:  4D           DC.B       0x4D                     ; 'M'
+  0x080068C9:  42           DC.B       0x42                     ; 'B'
+  0x080068CA:  20           DC.B       0x20                     ; ' '
+  0x080068CB:  50           DC.B       0x50                     ; 'P'
+  0x080068CC:  45           DC.B       0x45                     ; 'E'
+  0x080068CD:  20           DC.B       0x20                     ; ' '
+  0x080068CE:  45           DC.B       0x45                     ; 'E'
+  0x080068CF:  72           DC.B       0x72                     ; 'r'
+  0x080068D0:  72           DC.B       0x72                     ; 'r'
+  0x080068D1:  6F           DC.B       0x6F                     ; 'o'
+  0x080068D2:  72           DC.B       0x72                     ; 'r'
+  0x080068D3:  21           DC.B       0x21                     ; '!'
+  0x080068D4:  20           DC.B       0x20                     ; ' '
+  0x080068D5:  0A           DC.B       0x0A                     ; '\n'
+  0x080068D6:  0D           DC.B       0x0D                     ; '\r'
+  0x080068D7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.4 from PowerPro_lto.o, size=16, align=1

+
+  0x080068D8:  4D           DC.B       0x4D                     ; 'M'
+  0x080068D9:  42           DC.B       0x42                     ; 'B'
+  0x080068DA:  20           DC.B       0x20                     ; ' '
+  0x080068DB:  4E           DC.B       0x4E                     ; 'N'
+  0x080068DC:  45           DC.B       0x45                     ; 'E'
+  0x080068DD:  20           DC.B       0x20                     ; ' '
+  0x080068DE:  45           DC.B       0x45                     ; 'E'
+  0x080068DF:  72           DC.B       0x72                     ; 'r'
+  0x080068E0:  72           DC.B       0x72                     ; 'r'
+  0x080068E1:  6F           DC.B       0x6F                     ; 'o'
+  0x080068E2:  72           DC.B       0x72                     ; 'r'
+  0x080068E3:  21           DC.B       0x21                     ; '!'
+  0x080068E4:  20           DC.B       0x20                     ; ' '
+  0x080068E5:  0A           DC.B       0x0A                     ; '\n'
+  0x080068E6:  0D           DC.B       0x0D                     ; '\r'
+  0x080068E7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19 from PowerPro_lto.o, size=8, align=1

+
+  0x080068E8:  4C           DC.B       0x4C                     ; 'L'
+  0x080068E9:  56           DC.B       0x56                     ; 'V'
+  0x080068EA:  50           DC.B       0x50                     ; 'P'
+  0x080068EB:  20           DC.B       0x20                     ; ' '
+  0x080068EC:  4F           DC.B       0x4F                     ; 'O'
+  0x080068ED:  4E           DC.B       0x4E                     ; 'N'
+  0x080068EE:  21           DC.B       0x21                     ; '!'
+  0x080068EF:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.17.129 from PowerPro_lto.o, size=16, align=1

+
+  0x080068F0:  4C           DC.B       0x4C                     ; 'L'
+  0x080068F1:  56           DC.B       0x56                     ; 'V'
+  0x080068F2:  50           DC.B       0x50                     ; 'P'
+  0x080068F3:  20           DC.B       0x20                     ; ' '
+  0x080068F4:  4F           DC.B       0x4F                     ; 'O'
+  0x080068F5:  52           DC.B       0x52                     ; 'R'
+  0x080068F6:  20           DC.B       0x20                     ; ' '
+  0x080068F7:  4F           DC.B       0x4F                     ; 'O'
+  0x080068F8:  56           DC.B       0x56                     ; 'V'
+  0x080068F9:  50           DC.B       0x50                     ; 'P'
+  0x080068FA:  20           DC.B       0x20                     ; ' '
+  0x080068FB:  4F           DC.B       0x4F                     ; 'O'
+  0x080068FC:  46           DC.B       0x46                     ; 'F'
+  0x080068FD:  46           DC.B       0x46                     ; 'F'
+  0x080068FE:  21           DC.B       0x21                     ; '!'
+  0x080068FF:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19.131 from PowerPro_lto.o, size=16, align=1

+
+  0x08006900:  4C           DC.B       0x4C                     ; 'L'
+  0x08006901:  56           DC.B       0x56                     ; 'V'
+  0x08006902:  50           DC.B       0x50                     ; 'P'
+  0x08006903:  20           DC.B       0x20                     ; ' '
+  0x08006904:  41           DC.B       0x41                     ; 'A'
+  0x08006905:  4E           DC.B       0x4E                     ; 'N'
+  0x08006906:  44           DC.B       0x44                     ; 'D'
+  0x08006907:  20           DC.B       0x20                     ; ' '
+  0x08006908:  4F           DC.B       0x4F                     ; 'O'
+  0x08006909:  56           DC.B       0x56                     ; 'V'
+  0x0800690A:  50           DC.B       0x50                     ; 'P'
+  0x0800690B:  20           DC.B       0x20                     ; ' '
+  0x0800690C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800690D:  4E           DC.B       0x4E                     ; 'N'
+  0x0800690E:  21           DC.B       0x21                     ; '!'
+  0x0800690F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.8.136 from PowerPro_lto.o, size=28, align=1

+
+  0x08006910:  4E           DC.B       0x4E                     ; 'N'
+  0x08006911:  45           DC.B       0x45                     ; 'E'
+  0x08006912:  57           DC.B       0x57                     ; 'W'
+  0x08006913:  5F           DC.B       0x5F                     ; '_'
+  0x08006914:  53           DC.B       0x53                     ; 'S'
+  0x08006915:  54           DC.B       0x54                     ; 'T'
+  0x08006916:  41           DC.B       0x41                     ; 'A'
+  0x08006917:  54           DC.B       0x54                     ; 'T'
+  0x08006918:  45           DC.B       0x45                     ; 'E'
+  0x08006919:  3A           DC.B       0x3A                     ; ':'
+  0x0800691A:  20           DC.B       0x20                     ; ' '
+  0x0800691B:  4D           DC.B       0x4D                     ; 'M'
+  0x0800691C:  41           DC.B       0x41                     ; 'A'
+  0x0800691D:  49           DC.B       0x49                     ; 'I'
+  0x0800691E:  4E           DC.B       0x4E                     ; 'N'
+  0x0800691F:  53           DC.B       0x53                     ; 'S'
+  0x08006920:  57           DC.B       0x57                     ; 'W'
+  0x08006921:  49           DC.B       0x49                     ; 'I'
+  0x08006922:  54           DC.B       0x54                     ; 'T'
+  0x08006923:  43           DC.B       0x43                     ; 'C'
+  0x08006924:  48           DC.B       0x48                     ; 'H'
+  0x08006925:  5F           DC.B       0x5F                     ; '_'
+  0x08006926:  45           DC.B       0x45                     ; 'E'
+  0x08006927:  52           DC.B       0x52                     ; 'R'
+  0x08006928:  52           DC.B       0x52                     ; 'R'
+  0x08006929:  4F           DC.B       0x4F                     ; 'O'
+  0x0800692A:  52           DC.B       0x52                     ; 'R'
+  0x0800692B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.12.138 from PowerPro_lto.o, size=32, align=1

+
+  0x0800692C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800692D:  45           DC.B       0x45                     ; 'E'
+  0x0800692E:  57           DC.B       0x57                     ; 'W'
+  0x0800692F:  5F           DC.B       0x5F                     ; '_'
+  0x08006930:  53           DC.B       0x53                     ; 'S'
+  0x08006931:  54           DC.B       0x54                     ; 'T'
+  0x08006932:  41           DC.B       0x41                     ; 'A'
+  0x08006933:  54           DC.B       0x54                     ; 'T'
+  0x08006934:  45           DC.B       0x45                     ; 'E'
+  0x08006935:  3A           DC.B       0x3A                     ; ':'
+  0x08006936:  20           DC.B       0x20                     ; ' '
+  0x08006937:  4D           DC.B       0x4D                     ; 'M'
+  0x08006938:  41           DC.B       0x41                     ; 'A'
+  0x08006939:  49           DC.B       0x49                     ; 'I'
+  0x0800693A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800693B:  53           DC.B       0x53                     ; 'S'
+  0x0800693C:  57           DC.B       0x57                     ; 'W'
+  0x0800693D:  49           DC.B       0x49                     ; 'I'
+  0x0800693E:  54           DC.B       0x54                     ; 'T'
+  0x0800693F:  43           DC.B       0x43                     ; 'C'
+  0x08006940:  48           DC.B       0x48                     ; 'H'
+  0x08006941:  5F           DC.B       0x5F                     ; '_'
+  0x08006942:  4D           DC.B       0x4D                     ; 'M'
+  0x08006943:  41           DC.B       0x41                     ; 'A'
+  0x08006944:  4E           DC.B       0x4E                     ; 'N'
+  0x08006945:  55           DC.B       0x55                     ; 'U'
+  0x08006946:  41           DC.B       0x41                     ; 'A'
+  0x08006947:  4C           DC.B       0x4C                     ; 'L'
+  0x08006948:  5F           DC.B       0x5F                     ; '_'
+  0x08006949:  4F           DC.B       0x4F                     ; 'O'
+  0x0800694A:  4E           DC.B       0x4E                     ; 'N'
+  0x0800694B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.19.154 from PowerPro_lto.o, size=8, align=1

+
+  0x0800694C:  4F           DC.B       0x4F                     ; 'O'
+  0x0800694D:  56           DC.B       0x56                     ; 'V'
+  0x0800694E:  50           DC.B       0x50                     ; 'P'
+  0x0800694F:  20           DC.B       0x20                     ; ' '
+  0x08006950:  4F           DC.B       0x4F                     ; 'O'
+  0x08006951:  4E           DC.B       0x4E                     ; 'N'
+  0x08006952:  21           DC.B       0x21                     ; '!'
+  0x08006953:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.11.179 from PowerPro_lto.o, size=60, align=1

+
+  0x08006954:  42           DC.B       0x42                     ; 'B'
+  0x08006955:  4D           DC.B       0x4D                     ; 'M'
+  0x08006956:  53           DC.B       0x53                     ; 'S'
+  0x08006957:  20           DC.B       0x20                     ; ' '
+  0x08006958:  53           DC.B       0x53                     ; 'S'
+  0x08006959:  45           DC.B       0x45                     ; 'E'
+  0x0800695A:  43           DC.B       0x43                     ; 'C'
+  0x0800695B:  4F           DC.B       0x4F                     ; 'O'
+  0x0800695C:  4E           DC.B       0x4E                     ; 'N'
+  0x0800695D:  44           DC.B       0x44                     ; 'D'
+  0x0800695E:  41           DC.B       0x41                     ; 'A'
+  0x0800695F:  52           DC.B       0x52                     ; 'R'
+  0x08006960:  59           DC.B       0x59                     ; 'Y'
+  0x08006961:  20           DC.B       0x20                     ; ' '
+  0x08006962:  50           DC.B       0x50                     ; 'P'
+  0x08006963:  52           DC.B       0x52                     ; 'R'
+  0x08006964:  4F           DC.B       0x4F                     ; 'O'
+  0x08006965:  54           DC.B       0x54                     ; 'T'
+  0x08006966:  45           DC.B       0x45                     ; 'E'
+  0x08006967:  43           DC.B       0x43                     ; 'C'
+  0x08006968:  54           DC.B       0x54                     ; 'T'
+  0x08006969:  49           DC.B       0x49                     ; 'I'
+  0x0800696A:  4F           DC.B       0x4F                     ; 'O'
+  0x0800696B:  4E           DC.B       0x4E                     ; 'N'
+  0x0800696C:  20           DC.B       0x20                     ; ' '
+  0x0800696D:  46           DC.B       0x46                     ; 'F'
+  0x0800696E:  41           DC.B       0x41                     ; 'A'
+  0x0800696F:  55           DC.B       0x55                     ; 'U'
+  0x08006970:  4C           DC.B       0x4C                     ; 'L'
+  0x08006971:  54           DC.B       0x54                     ; 'T'
+  0x08006972:  20           DC.B       0x20                     ; ' '
+  0x08006973:  45           DC.B       0x45                     ; 'E'
+  0x08006974:  56           DC.B       0x56                     ; 'V'
+  0x08006975:  45           DC.B       0x45                     ; 'E'
+  0x08006976:  4E           DC.B       0x4E                     ; 'N'
+  0x08006977:  54           DC.B       0x54                     ; 'T'
+  0x08006978:  20           DC.B       0x20                     ; ' '
+  0x08006979:  44           DC.B       0x44                     ; 'D'
+  0x0800697A:  45           DC.B       0x45                     ; 'E'
+  0x0800697B:  54           DC.B       0x54                     ; 'T'
+  0x0800697C:  45           DC.B       0x45                     ; 'E'
+  0x0800697D:  43           DC.B       0x43                     ; 'C'
+  0x0800697E:  54           DC.B       0x54                     ; 'T'
+  0x0800697F:  45           DC.B       0x45                     ; 'E'
+  0x08006980:  44           DC.B       0x44                     ; 'D'
+  0x08006981:  20           DC.B       0x20                     ; ' '
+  0x08006982:  28           DC.B       0x28                     ; '('
+  0x08006983:  4C           DC.B       0x4C                     ; 'L'
+  0x08006984:  56           DC.B       0x56                     ; 'V'
+  0x08006985:  50           DC.B       0x50                     ; 'P'
+  0x08006986:  20           DC.B       0x20                     ; ' '
+  0x08006987:  26           DC.B       0x26                     ; '&'
+  0x08006988:  20           DC.B       0x20                     ; ' '
+  0x08006989:  4F           DC.B       0x4F                     ; 'O'
+  0x0800698A:  56           DC.B       0x56                     ; 'V'
+  0x0800698B:  50           DC.B       0x50                     ; 'P'
+  0x0800698C:  20           DC.B       0x20                     ; ' '
+  0x0800698D:  29           DC.B       0x29                     ; ')'
+  0x0800698E:  21           DC.B       0x21                     ; '!'
+  0x0800698F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lstr.14.174 from PowerPro_lto.o, size=28, align=1

+
+  0x08006990:  46           DC.B       0x46                     ; 'F'
+  0x08006991:  41           DC.B       0x41                     ; 'A'
+  0x08006992:  55           DC.B       0x55                     ; 'U'
+  0x08006993:  4C           DC.B       0x4C                     ; 'L'
+  0x08006994:  54           DC.B       0x54                     ; 'T'
+  0x08006995:  20           DC.B       0x20                     ; ' '
+  0x08006996:  49           DC.B       0x49                     ; 'I'
+  0x08006997:  4E           DC.B       0x4E                     ; 'N'
+  0x08006998:  50           DC.B       0x50                     ; 'P'
+  0x08006999:  55           DC.B       0x55                     ; 'U'
+  0x0800699A:  54           DC.B       0x54                     ; 'T'
+  0x0800699B:  20           DC.B       0x20                     ; ' '
+  0x0800699C:  45           DC.B       0x45                     ; 'E'
+  0x0800699D:  56           DC.B       0x56                     ; 'V'
+  0x0800699E:  45           DC.B       0x45                     ; 'E'
+  0x0800699F:  4E           DC.B       0x4E                     ; 'N'
+  0x080069A0:  54           DC.B       0x54                     ; 'T'
+  0x080069A1:  20           DC.B       0x20                     ; ' '
+  0x080069A2:  44           DC.B       0x44                     ; 'D'
+  0x080069A3:  45           DC.B       0x45                     ; 'E'
+  0x080069A4:  54           DC.B       0x54                     ; 'T'
+  0x080069A5:  45           DC.B       0x45                     ; 'E'
+  0x080069A6:  43           DC.B       0x43                     ; 'C'
+  0x080069A7:  54           DC.B       0x54                     ; 'T'
+  0x080069A8:  45           DC.B       0x45                     ; 'E'
+  0x080069A9:  44           DC.B       0x44                     ; 'D'
+  0x080069AA:  21           DC.B       0x21                     ; '!'
+  0x080069AB:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata.libc.__SEGGER_RTL_hex_uc from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=1

+
+
__SEGGER_RTL_hex_uc:
+  0x080069AC:  30           DC.B       0x30                     ; '0'
+  0x080069AD:  31           DC.B       0x31                     ; '1'
+  0x080069AE:  32           DC.B       0x32                     ; '2'
+  0x080069AF:  33           DC.B       0x33                     ; '3'
+  0x080069B0:  34           DC.B       0x34                     ; '4'
+  0x080069B1:  35           DC.B       0x35                     ; '5'
+  0x080069B2:  36           DC.B       0x36                     ; '6'
+  0x080069B3:  37           DC.B       0x37                     ; '7'
+  0x080069B4:  38           DC.B       0x38                     ; '8'
+  0x080069B5:  39           DC.B       0x39                     ; '9'
+  0x080069B6:  41           DC.B       0x41                     ; 'A'
+  0x080069B7:  42           DC.B       0x42                     ; 'B'
+  0x080069B8:  43           DC.B       0x43                     ; 'C'
+  0x080069B9:  44           DC.B       0x44                     ; 'D'
+  0x080069BA:  45           DC.B       0x45                     ; 'E'
+  0x080069BB:  46           DC.B       0x46                     ; 'F'
+
+

Section .rodata.libc.__SEGGER_RTL_hex_lc from prinops.o (libc_v6m_t_le_eabi_small.a), size=16, align=1

+
+
__SEGGER_RTL_hex_lc:
+  0x080069BC:  30           DC.B       0x30                     ; '0'
+  0x080069BD:  31           DC.B       0x31                     ; '1'
+  0x080069BE:  32           DC.B       0x32                     ; '2'
+  0x080069BF:  33           DC.B       0x33                     ; '3'
+  0x080069C0:  34           DC.B       0x34                     ; '4'
+  0x080069C1:  35           DC.B       0x35                     ; '5'
+  0x080069C2:  36           DC.B       0x36                     ; '6'
+  0x080069C3:  37           DC.B       0x37                     ; '7'
+  0x080069C4:  38           DC.B       0x38                     ; '8'
+  0x080069C5:  39           DC.B       0x39                     ; '9'
+  0x080069C6:  61           DC.B       0x61                     ; 'a'
+  0x080069C7:  62           DC.B       0x62                     ; 'b'
+  0x080069C8:  63           DC.B       0x63                     ; 'c'
+  0x080069C9:  64           DC.B       0x64                     ; 'd'
+  0x080069CA:  65           DC.B       0x65                     ; 'e'
+  0x080069CB:  66           DC.B       0x66                     ; 'f'
+
+

Section .rodata.libc.__SEGGER_RTL_ascii_ctype_map from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=128, align=1

+
+
__SEGGER_RTL_ascii_ctype_map:
+  0x080069CC:  20           DC.B       0x20                     ; ' '
+  0x080069CD:  20           DC.B       0x20                     ; ' '
+  0x080069CE:  20           DC.B       0x20                     ; ' '
+  0x080069CF:  20           DC.B       0x20                     ; ' '
+  0x080069D0:  20           DC.B       0x20                     ; ' '
+  0x080069D1:  20           DC.B       0x20                     ; ' '
+  0x080069D2:  20           DC.B       0x20                     ; ' '
+  0x080069D3:  20           DC.B       0x20                     ; ' '
+  0x080069D4:  20           DC.B       0x20                     ; ' '
+  0x080069D5:  68           DC.B       0x68                     ; 'h'
+  0x080069D6:  28           DC.B       0x28                     ; '('
+  0x080069D7:  28           DC.B       0x28                     ; '('
+  0x080069D8:  28           DC.B       0x28                     ; '('
+  0x080069D9:  28           DC.B       0x28                     ; '('
+  0x080069DA:  20           DC.B       0x20                     ; ' '
+  0x080069DB:  20           DC.B       0x20                     ; ' '
+  0x080069DC:  20           DC.B       0x20                     ; ' '
+  0x080069DD:  20           DC.B       0x20                     ; ' '
+  0x080069DE:  20           DC.B       0x20                     ; ' '
+  0x080069DF:  20           DC.B       0x20                     ; ' '
+  0x080069E0:  20           DC.B       0x20                     ; ' '
+  0x080069E1:  20           DC.B       0x20                     ; ' '
+  0x080069E2:  20           DC.B       0x20                     ; ' '
+  0x080069E3:  20           DC.B       0x20                     ; ' '
+  0x080069E4:  20           DC.B       0x20                     ; ' '
+  0x080069E5:  20           DC.B       0x20                     ; ' '
+  0x080069E6:  20           DC.B       0x20                     ; ' '
+  0x080069E7:  20           DC.B       0x20                     ; ' '
+  0x080069E8:  20           DC.B       0x20                     ; ' '
+  0x080069E9:  20           DC.B       0x20                     ; ' '
+  0x080069EA:  20           DC.B       0x20                     ; ' '
+  0x080069EB:  20           DC.B       0x20                     ; ' '
+  0x080069EC:  48           DC.B       0x48                     ; 'H'
+  0x080069ED:  10           DC.B       0x10                     ; '\x10'
+  0x080069EE:  10           DC.B       0x10                     ; '\x10'
+  0x080069EF:  10           DC.B       0x10                     ; '\x10'
+  0x080069F0:  10           DC.B       0x10                     ; '\x10'
+  0x080069F1:  10           DC.B       0x10                     ; '\x10'
+  0x080069F2:  10           DC.B       0x10                     ; '\x10'
+  0x080069F3:  10           DC.B       0x10                     ; '\x10'
+  0x080069F4:  10           DC.B       0x10                     ; '\x10'
+  0x080069F5:  10           DC.B       0x10                     ; '\x10'
+  0x080069F6:  10           DC.B       0x10                     ; '\x10'
+  0x080069F7:  10           DC.B       0x10                     ; '\x10'
+  0x080069F8:  10           DC.B       0x10                     ; '\x10'
+  0x080069F9:  10           DC.B       0x10                     ; '\x10'
+  0x080069FA:  10           DC.B       0x10                     ; '\x10'
+  0x080069FB:  10           DC.B       0x10                     ; '\x10'
+  0x080069FC:  84           DC.B       0x84                     ; '\x84'
+  0x080069FD:  84           DC.B       0x84                     ; '\x84'
+  0x080069FE:  84           DC.B       0x84                     ; '\x84'
+  0x080069FF:  84           DC.B       0x84                     ; '\x84'
+  0x08006A00:  84           DC.B       0x84                     ; '\x84'
+  0x08006A01:  84           DC.B       0x84                     ; '\x84'
+  0x08006A02:  84           DC.B       0x84                     ; '\x84'
+  0x08006A03:  84           DC.B       0x84                     ; '\x84'
+  0x08006A04:  84           DC.B       0x84                     ; '\x84'
+  0x08006A05:  84           DC.B       0x84                     ; '\x84'
+  0x08006A06:  10           DC.B       0x10                     ; '\x10'
+  0x08006A07:  10           DC.B       0x10                     ; '\x10'
+  0x08006A08:  10           DC.B       0x10                     ; '\x10'
+  0x08006A09:  10           DC.B       0x10                     ; '\x10'
+  0x08006A0A:  10           DC.B       0x10                     ; '\x10'
+  0x08006A0B:  10           DC.B       0x10                     ; '\x10'
+  0x08006A0C:  10           DC.B       0x10                     ; '\x10'
+  0x08006A0D:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0E:  81           DC.B       0x81                     ; '\x81'
+  0x08006A0F:  81           DC.B       0x81                     ; '\x81'
+  0x08006A10:  81           DC.B       0x81                     ; '\x81'
+  0x08006A11:  81           DC.B       0x81                     ; '\x81'
+  0x08006A12:  81           DC.B       0x81                     ; '\x81'
+  0x08006A13:  01           DC.B       0x01                     ; '\x01'
+  0x08006A14:  01           DC.B       0x01                     ; '\x01'
+  0x08006A15:  01           DC.B       0x01                     ; '\x01'
+  0x08006A16:  01           DC.B       0x01                     ; '\x01'
+  0x08006A17:  01           DC.B       0x01                     ; '\x01'
+  0x08006A18:  01           DC.B       0x01                     ; '\x01'
+  0x08006A19:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1A:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1B:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1C:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1D:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1E:  01           DC.B       0x01                     ; '\x01'
+  0x08006A1F:  01           DC.B       0x01                     ; '\x01'
+  0x08006A20:  01           DC.B       0x01                     ; '\x01'
+  0x08006A21:  01           DC.B       0x01                     ; '\x01'
+  0x08006A22:  01           DC.B       0x01                     ; '\x01'
+  0x08006A23:  01           DC.B       0x01                     ; '\x01'
+  0x08006A24:  01           DC.B       0x01                     ; '\x01'
+  0x08006A25:  01           DC.B       0x01                     ; '\x01'
+  0x08006A26:  01           DC.B       0x01                     ; '\x01'
+  0x08006A27:  10           DC.B       0x10                     ; '\x10'
+  0x08006A28:  10           DC.B       0x10                     ; '\x10'
+  0x08006A29:  10           DC.B       0x10                     ; '\x10'
+  0x08006A2A:  10           DC.B       0x10                     ; '\x10'
+  0x08006A2B:  10           DC.B       0x10                     ; '\x10'
+  0x08006A2C:  10           DC.B       0x10                     ; '\x10'
+  0x08006A2D:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2E:  82           DC.B       0x82                     ; '\x82'
+  0x08006A2F:  82           DC.B       0x82                     ; '\x82'
+  0x08006A30:  82           DC.B       0x82                     ; '\x82'
+  0x08006A31:  82           DC.B       0x82                     ; '\x82'
+  0x08006A32:  82           DC.B       0x82                     ; '\x82'
+  0x08006A33:  02           DC.B       0x02                     ; '\x02'
+  0x08006A34:  02           DC.B       0x02                     ; '\x02'
+  0x08006A35:  02           DC.B       0x02                     ; '\x02'
+  0x08006A36:  02           DC.B       0x02                     ; '\x02'
+  0x08006A37:  02           DC.B       0x02                     ; '\x02'
+  0x08006A38:  02           DC.B       0x02                     ; '\x02'
+  0x08006A39:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3A:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3B:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3C:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3D:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3E:  02           DC.B       0x02                     ; '\x02'
+  0x08006A3F:  02           DC.B       0x02                     ; '\x02'
+  0x08006A40:  02           DC.B       0x02                     ; '\x02'
+  0x08006A41:  02           DC.B       0x02                     ; '\x02'
+  0x08006A42:  02           DC.B       0x02                     ; '\x02'
+  0x08006A43:  02           DC.B       0x02                     ; '\x02'
+  0x08006A44:  02           DC.B       0x02                     ; '\x02'
+  0x08006A45:  02           DC.B       0x02                     ; '\x02'
+  0x08006A46:  02           DC.B       0x02                     ; '\x02'
+  0x08006A47:  10           DC.B       0x10                     ; '\x10'
+  0x08006A48:  10           DC.B       0x10                     ; '\x10'
+  0x08006A49:  10           DC.B       0x10                     ; '\x10'
+  0x08006A4A:  10           DC.B       0x10                     ; '\x10'
+  0x08006A4B:  20           DC.B       0x20                     ; ' '
+
+

Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=36, align=4

+
+
__SEGGER_init_ctors:
+  0x08006A4C:  B500         PUSH       {LR}
+  0x08006A4E:  4806         LDR        R0, =0x08006864          ; [PC, #24] [0x08006A68] 
+  0x08006A50:  4906         LDR        R1, =UARTEx_SetNbDataToProcess.numerator ; [PC, #24] [0x08006A6C] =0x08006868 
+
.L1:
+  0x08006A52:  4288         CMP        R0, R1
+  0x08006A54:  D005         BEQ        .L2                      ; 0x08006A62
+  0x08006A56:  6802         LDR        R2, [R0]
+  0x08006A58:  3004         ADDS       R0, #4
+  0x08006A5A:  B403         PUSH       {R0-R1}
+  0x08006A5C:  4790         BLX        R2
+  0x08006A5E:  BC03         POP        {R0-R1}
+  0x08006A60:  E7F7         B          .L1                      ; 0x08006A52
+
.L2:
+  0x08006A62:  BC08         POP        {R3}
+  0x08006A64:  4718         BX         R3
+  0x08006A66:  0000         NOP
+  0x08006A68:  08006864     DC.W       08006864               ; R_ARM_ABS32
+  0x08006A6C:  08006868     DC.W       UARTEx_SetNbDataToProcess.numerator
+
+

Section .segger.init.table from [ Linker created ], size=180, align=4

+
+  0x08006A70:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006A74:  00           DC.B       0x00                     ; '\0'
+  0x08006A75:  00           DC.B       0x00                     ; '\0'
+  0x08006A76:  00           DC.B       0x00                     ; '\0'
+  0x08006A77:  20           DC.B       0x20                     ; ' '
+  0x08006A78:  3B           DC.B       0x3B                     ; ';'
+  0x08006A79:  07           DC.B       0x07                     ; '\x07'
+  0x08006A7A:  00           DC.B       0x00                     ; '\0'
+  0x08006A7B:  00           DC.B       0x00                     ; '\0'
+  0x08006A7C:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006A80:  3C           DC.B       0x3C                     ; '<'
+  0x08006A81:  07           DC.B       0x07                     ; '\x07'
+  0x08006A82:  00           DC.B       0x00                     ; '\0'
+  0x08006A83:  20           DC.B       0x20                     ; ' '
+  0x08006A84:  01           DC.B       0x01                     ; '\x01'
+  0x08006A85:  00           DC.B       0x00                     ; '\0'
+  0x08006A86:  00           DC.B       0x00                     ; '\0'
+  0x08006A87:  00           DC.B       0x00                     ; '\0'
+  0x08006A88:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006A8C:  40           DC.B       0x40                     ; '@'
+  0x08006A8D:  07           DC.B       0x07                     ; '\x07'
+  0x08006A8E:  00           DC.B       0x00                     ; '\0'
+  0x08006A8F:  20           DC.B       0x20                     ; ' '
+  0x08006A90:  01           DC.B       0x01                     ; '\x01'
+  0x08006A91:  00           DC.B       0x00                     ; '\0'
+  0x08006A92:  00           DC.B       0x00                     ; '\0'
+  0x08006A93:  00           DC.B       0x00                     ; '\0'
+  0x08006A94:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006A98:  44           DC.B       0x44                     ; 'D'
+  0x08006A99:  07           DC.B       0x07                     ; '\x07'
+  0x08006A9A:  00           DC.B       0x00                     ; '\0'
+  0x08006A9B:  20           DC.B       0x20                     ; ' '
+  0x08006A9C:  01           DC.B       0x01                     ; '\x01'
+  0x08006A9D:  00           DC.B       0x00                     ; '\0'
+  0x08006A9E:  00           DC.B       0x00                     ; '\0'
+  0x08006A9F:  00           DC.B       0x00                     ; '\0'
+  0x08006AA0:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AA4:  48           DC.B       0x48                     ; 'H'
+  0x08006AA5:  07           DC.B       0x07                     ; '\x07'
+  0x08006AA6:  00           DC.B       0x00                     ; '\0'
+  0x08006AA7:  20           DC.B       0x20                     ; ' '
+  0x08006AA8:  01           DC.B       0x01                     ; '\x01'
+  0x08006AA9:  00           DC.B       0x00                     ; '\0'
+  0x08006AAA:  00           DC.B       0x00                     ; '\0'
+  0x08006AAB:  00           DC.B       0x00                     ; '\0'
+  0x08006AAC:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AB0:  4C           DC.B       0x4C                     ; 'L'
+  0x08006AB1:  07           DC.B       0x07                     ; '\x07'
+  0x08006AB2:  00           DC.B       0x00                     ; '\0'
+  0x08006AB3:  20           DC.B       0x20                     ; ' '
+  0x08006AB4:  01           DC.B       0x01                     ; '\x01'
+  0x08006AB5:  00           DC.B       0x00                     ; '\0'
+  0x08006AB6:  00           DC.B       0x00                     ; '\0'
+  0x08006AB7:  00           DC.B       0x00                     ; '\0'
+  0x08006AB8:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006ABC:  50           DC.B       0x50                     ; 'P'
+  0x08006ABD:  07           DC.B       0x07                     ; '\x07'
+  0x08006ABE:  00           DC.B       0x00                     ; '\0'
+  0x08006ABF:  20           DC.B       0x20                     ; ' '
+  0x08006AC0:  01           DC.B       0x01                     ; '\x01'
+  0x08006AC1:  00           DC.B       0x00                     ; '\0'
+  0x08006AC2:  00           DC.B       0x00                     ; '\0'
+  0x08006AC3:  00           DC.B       0x00                     ; '\0'
+  0x08006AC4:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AC8:  54           DC.B       0x54                     ; 'T'
+  0x08006AC9:  07           DC.B       0x07                     ; '\x07'
+  0x08006ACA:  00           DC.B       0x00                     ; '\0'
+  0x08006ACB:  20           DC.B       0x20                     ; ' '
+  0x08006ACC:  01           DC.B       0x01                     ; '\x01'
+  0x08006ACD:  00           DC.B       0x00                     ; '\0'
+  0x08006ACE:  00           DC.B       0x00                     ; '\0'
+  0x08006ACF:  00           DC.B       0x00                     ; '\0'
+  0x08006AD0:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AD4:  58           DC.B       0x58                     ; 'X'
+  0x08006AD5:  07           DC.B       0x07                     ; '\x07'
+  0x08006AD6:  00           DC.B       0x00                     ; '\0'
+  0x08006AD7:  20           DC.B       0x20                     ; ' '
+  0x08006AD8:  01           DC.B       0x01                     ; '\x01'
+  0x08006AD9:  00           DC.B       0x00                     ; '\0'
+  0x08006ADA:  00           DC.B       0x00                     ; '\0'
+  0x08006ADB:  00           DC.B       0x00                     ; '\0'
+  0x08006ADC:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AE0:  5C           DC.B       0x5C                     ; '\\'
+  0x08006AE1:  07           DC.B       0x07                     ; '\x07'
+  0x08006AE2:  00           DC.B       0x00                     ; '\0'
+  0x08006AE3:  20           DC.B       0x20                     ; ' '
+  0x08006AE4:  01           DC.B       0x01                     ; '\x01'
+  0x08006AE5:  00           DC.B       0x00                     ; '\0'
+  0x08006AE6:  00           DC.B       0x00                     ; '\0'
+  0x08006AE7:  00           DC.B       0x00                     ; '\0'
+  0x08006AE8:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AEC:  60           DC.B       0x60                     ; '`'
+  0x08006AED:  07           DC.B       0x07                     ; '\x07'
+  0x08006AEE:  00           DC.B       0x00                     ; '\0'
+  0x08006AEF:  20           DC.B       0x20                     ; ' '
+  0x08006AF0:  01           DC.B       0x01                     ; '\x01'
+  0x08006AF1:  00           DC.B       0x00                     ; '\0'
+  0x08006AF2:  00           DC.B       0x00                     ; '\0'
+  0x08006AF3:  00           DC.B       0x00                     ; '\0'
+  0x08006AF4:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006AF8:  64           DC.B       0x64                     ; 'd'
+  0x08006AF9:  07           DC.B       0x07                     ; '\x07'
+  0x08006AFA:  00           DC.B       0x00                     ; '\0'
+  0x08006AFB:  20           DC.B       0x20                     ; ' '
+  0x08006AFC:  01           DC.B       0x01                     ; '\x01'
+  0x08006AFD:  00           DC.B       0x00                     ; '\0'
+  0x08006AFE:  00           DC.B       0x00                     ; '\0'
+  0x08006AFF:  00           DC.B       0x00                     ; '\0'
+  0x08006B00:  08006B4D     DC.W       __SEGGER_init_zero
+  0x08006B04:  68           DC.B       0x68                     ; 'h'
+  0x08006B05:  07           DC.B       0x07                     ; '\x07'
+  0x08006B06:  00           DC.B       0x00                     ; '\0'
+  0x08006B07:  20           DC.B       0x20                     ; ' '
+  0x08006B08:  11           DC.B       0x11                     ; '\x11'
+  0x08006B09:  04           DC.B       0x04                     ; '\x04'
+  0x08006B0A:  00           DC.B       0x00                     ; '\0'
+  0x08006B0B:  00           DC.B       0x00                     ; '\0'
+  0x08006B0C:  08006B5F     DC.W       __SEGGER_init_copy
+  0x08006B10:  80           DC.B       0x80                     ; '\x80'
+  0x08006B11:  0B           DC.B       0x0B                     ; '\v'
+  0x08006B12:  00           DC.B       0x00                     ; '\0'
+  0x08006B13:  20           DC.B       0x20                     ; ' '
+  0x08006B14:  08006B24     DC.W       08006B24               ; R_ARM_ABS32
+  0x08006B18:  28           DC.B       0x28                     ; '('
+  0x08006B19:  00           DC.B       0x00                     ; '\0'
+  0x08006B1A:  00           DC.B       0x00                     ; '\0'
+  0x08006B1B:  00           DC.B       0x00                     ; '\0'
+  0x08006B1C:  08006A4D     DC.W       __SEGGER_init_ctors
+  0x08006B20:  080051DB     DC.W       __SEGGER_init_done
+
+

Section .segger.init.data from [ Linker created ], size=40, align=4

+
+  0x08006B24:  84           DC.B       0x84                     ; '\x84'
+  0x08006B25:  57           DC.B       0x57                     ; 'W'
+  0x08006B26:  00           DC.B       0x00                     ; '\0'
+  0x08006B27:  08           DC.B       0x08                     ; '\b'
+  0x08006B28:  84           DC.B       0x84                     ; '\x84'
+  0x08006B29:  57           DC.B       0x57                     ; 'W'
+  0x08006B2A:  00           DC.B       0x00                     ; '\0'
+  0x08006B2B:  08           DC.B       0x08                     ; '\b'
+  0x08006B2C:  84           DC.B       0x84                     ; '\x84'
+  0x08006B2D:  57           DC.B       0x57                     ; 'W'
+  0x08006B2E:  00           DC.B       0x00                     ; '\0'
+  0x08006B2F:  08           DC.B       0x08                     ; '\b'
+  0x08006B30:  84           DC.B       0x84                     ; '\x84'
+  0x08006B31:  57           DC.B       0x57                     ; 'W'
+  0x08006B32:  00           DC.B       0x00                     ; '\0'
+  0x08006B33:  08           DC.B       0x08                     ; '\b'
+  0x08006B34:  84           DC.B       0x84                     ; '\x84'
+  0x08006B35:  57           DC.B       0x57                     ; 'W'
+  0x08006B36:  00           DC.B       0x00                     ; '\0'
+  0x08006B37:  08           DC.B       0x08                     ; '\b'
+  0x08006B38:  04           DC.B       0x04                     ; '\x04'
+  0x08006B39:  00           DC.B       0x00                     ; '\0'
+  0x08006B3A:  00           DC.B       0x00                     ; '\0'
+  0x08006B3B:  00           DC.B       0x00                     ; '\0'
+  0x08006B3C:  CC           DC.B       0xCC                     ; '\xCC'
+  0x08006B3D:  06           DC.B       0x06                     ; '\x06'
+  0x08006B3E:  00           DC.B       0x00                     ; '\0'
+  0x08006B3F:  20           DC.B       0x20                     ; ' '
+  0x08006B40:  D0           DC.B       0xD0                     ; '\xD0'
+  0x08006B41:  06           DC.B       0x06                     ; '\x06'
+  0x08006B42:  00           DC.B       0x00                     ; '\0'
+  0x08006B43:  20           DC.B       0x20                     ; ' '
+  0x08006B44:  D4           DC.B       0xD4                     ; '\xD4'
+  0x08006B45:  06           DC.B       0x06                     ; '\x06'
+  0x08006B46:  00           DC.B       0x00                     ; '\0'
+  0x08006B47:  20           DC.B       0x20                     ; ' '
+  0x08006B48:  00           DC.B       0x00                     ; '\0'
+  0x08006B49:  1B           DC.B       0x1B                     ; '\x1B'
+  0x08006B4A:  B7           DC.B       0xB7                     ; '\xB7'
+  0x08006B4B:  00           DC.B       0x00                     ; '\0'
+
+

Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=18, align=2

+
+
__SEGGER_init_zero:
+  0x08006B4C:  6820         LDR        R0, [R4]
+  0x08006B4E:  6861         LDR        R1, [R4, #4]
+  0x08006B50:  3408         ADDS       R4, #8
+  0x08006B52:  2200         MOVS       R2, #0
+  0x08006B54:  E000         B          .L2                      ; 0x08006B58
+
.L1:
+  0x08006B56:  5442         STRB       R2, [R0, R1]
+
.L2:
+  0x08006B58:  1E49         SUBS       R1, R1, #1
+  0x08006B5A:  D5FC         BPL        .L1                      ; 0x08006B56
+  0x08006B5C:  4770         BX         LR
+
+

Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_small.a), size=20, align=2

+
+
__SEGGER_init_copy:
+  0x08006B5E:  6820         LDR        R0, [R4]
+  0x08006B60:  6861         LDR        R1, [R4, #4]
+  0x08006B62:  68A2         LDR        R2, [R4, #8]
+  0x08006B64:  340C         ADDS       R4, #12
+  0x08006B66:  E001         B          .L2                      ; 0x08006B6C
+
.L1:
+  0x08006B68:  5C8B         LDRB       R3, [R1, R2]
+  0x08006B6A:  5483         STRB       R3, [R0, R2]
+
.L2:
+  0x08006B6C:  1E52         SUBS       R2, R2, #1
+  0x08006B6E:  D5FB         BPL        .L1                      ; 0x08006B68
+  0x08006B70:  4770         BX         LR
+
+

Section .RAM1 from PowerPro_lto.o, size=564, align=4

+
+
modbusData:
+  0x20000000:  00           DC.B       0x00                     ; '\0'
+  0x20000001:  00           DC.B       0x00                     ; '\0'
+  0x20000002:  00           DC.B       0x00                     ; '\0'
+  0x20000003:  00           DC.B       0x00                     ; '\0'
+  0x20000004:  00           DC.B       0x00                     ; '\0'
+  0x20000005:  00           DC.B       0x00                     ; '\0'
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+  0x20000146:  00           DC.B       0x00                     ; '\0'
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+  0x20000148:  00           DC.B       0x00                     ; '\0'
+  0x20000149:  00           DC.B       0x00                     ; '\0'
+  0x2000014A:  00           DC.B       0x00                     ; '\0'
+  0x2000014B:  00           DC.B       0x00                     ; '\0'
+  0x2000014C:  00           DC.B       0x00                     ; '\0'
+  0x2000014D:  00           DC.B       0x00                     ; '\0'
+  0x2000014E:  00           DC.B       0x00                     ; '\0'
+  0x2000014F:  00           DC.B       0x00                     ; '\0'
+  0x20000150:  00           DC.B       0x00                     ; '\0'
+  0x20000151:  00           DC.B       0x00                     ; '\0'
+  0x20000152:  00           DC.B       0x00                     ; '\0'
+  0x20000153:  00           DC.B       0x00                     ; '\0'
+  0x20000154:  00           DC.B       0x00                     ; '\0'
+  0x20000155:  00           DC.B       0x00                     ; '\0'
+  0x20000156:  00           DC.B       0x00                     ; '\0'
+  0x20000157:  00           DC.B       0x00                     ; '\0'
+  0x20000158:  00           DC.B       0x00                     ; '\0'
+  0x20000159:  00           DC.B       0x00                     ; '\0'
+  0x2000015A:  00           DC.B       0x00                     ; '\0'
+  0x2000015B:  00           DC.B       0x00                     ; '\0'
+  0x2000015C:  00           DC.B       0x00                     ; '\0'
+  0x2000015D:  00           DC.B       0x00                     ; '\0'
+  0x2000015E:  00           DC.B       0x00                     ; '\0'
+  0x2000015F:  00           DC.B       0x00                     ; '\0'
+  0x20000160:  00           DC.B       0x00                     ; '\0'
+  0x20000161:  00           DC.B       0x00                     ; '\0'
+  0x20000162:  00           DC.B       0x00                     ; '\0'
+  0x20000163:  00           DC.B       0x00                     ; '\0'
+  0x20000164:  00           DC.B       0x00                     ; '\0'
+  0x20000165:  00           DC.B       0x00                     ; '\0'
+  0x20000166:  00           DC.B       0x00                     ; '\0'
+  0x20000167:  00           DC.B       0x00                     ; '\0'
+  0x20000168:  00           DC.B       0x00                     ; '\0'
+  0x20000169:  00           DC.B       0x00                     ; '\0'
+  0x2000016A:  00           DC.B       0x00                     ; '\0'
+  0x2000016B:  00           DC.B       0x00                     ; '\0'
+  0x2000016C:  00           DC.B       0x00                     ; '\0'
+  0x2000016D:  00           DC.B       0x00                     ; '\0'
+  0x2000016E:  00           DC.B       0x00                     ; '\0'
+  0x2000016F:  00           DC.B       0x00                     ; '\0'
+  0x20000170:  00           DC.B       0x00                     ; '\0'
+  0x20000171:  00           DC.B       0x00                     ; '\0'
+  0x20000172:  00           DC.B       0x00                     ; '\0'
+  0x20000173:  00           DC.B       0x00                     ; '\0'
+  0x20000174:  00           DC.B       0x00                     ; '\0'
+  0x20000175:  00           DC.B       0x00                     ; '\0'
+  0x20000176:  00           DC.B       0x00                     ; '\0'
+  0x20000177:  00           DC.B       0x00                     ; '\0'
+  0x20000178:  00           DC.B       0x00                     ; '\0'
+  0x20000179:  00           DC.B       0x00                     ; '\0'
+  0x2000017A:  00           DC.B       0x00                     ; '\0'
+  0x2000017B:  00           DC.B       0x00                     ; '\0'
+  0x2000017C:  00           DC.B       0x00                     ; '\0'
+  0x2000017D:  00           DC.B       0x00                     ; '\0'
+  0x2000017E:  00           DC.B       0x00                     ; '\0'
+  0x2000017F:  00           DC.B       0x00                     ; '\0'
+  0x20000180:  00           DC.B       0x00                     ; '\0'
+  0x20000181:  00           DC.B       0x00                     ; '\0'
+  0x20000182:  00           DC.B       0x00                     ; '\0'
+  0x20000183:  00           DC.B       0x00                     ; '\0'
+  0x20000184:  00           DC.B       0x00                     ; '\0'
+  0x20000185:  00           DC.B       0x00                     ; '\0'
+  0x20000186:  00           DC.B       0x00                     ; '\0'
+  0x20000187:  00           DC.B       0x00                     ; '\0'
+  0x20000188:  00           DC.B       0x00                     ; '\0'
+  0x20000189:  00           DC.B       0x00                     ; '\0'
+  0x2000018A:  00           DC.B       0x00                     ; '\0'
+  0x2000018B:  00           DC.B       0x00                     ; '\0'
+  0x2000018C:  00           DC.B       0x00                     ; '\0'
+  0x2000018D:  00           DC.B       0x00                     ; '\0'
+  0x2000018E:  00           DC.B       0x00                     ; '\0'
+  0x2000018F:  00           DC.B       0x00                     ; '\0'
+  0x20000190:  00           DC.B       0x00                     ; '\0'
+  0x20000191:  00           DC.B       0x00                     ; '\0'
+  0x20000192:  00           DC.B       0x00                     ; '\0'
+  0x20000193:  00           DC.B       0x00                     ; '\0'
+  0x20000194:  00           DC.B       0x00                     ; '\0'
+  0x20000195:  00           DC.B       0x00                     ; '\0'
+  0x20000196:  00           DC.B       0x00                     ; '\0'
+  0x20000197:  00           DC.B       0x00                     ; '\0'
+  0x20000198:  00           DC.B       0x00                     ; '\0'
+  0x20000199:  00           DC.B       0x00                     ; '\0'
+  0x2000019A:  00           DC.B       0x00                     ; '\0'
+  0x2000019B:  00           DC.B       0x00                     ; '\0'
+  0x2000019C:  00           DC.B       0x00                     ; '\0'
+  0x2000019D:  00           DC.B       0x00                     ; '\0'
+  0x2000019E:  00           DC.B       0x00                     ; '\0'
+  0x2000019F:  00           DC.B       0x00                     ; '\0'
+  0x200001A0:  00           DC.B       0x00                     ; '\0'
+  0x200001A1:  00           DC.B       0x00                     ; '\0'
+  0x200001A2:  00           DC.B       0x00                     ; '\0'
+  0x200001A3:  00           DC.B       0x00                     ; '\0'
+  0x200001A4:  00           DC.B       0x00                     ; '\0'
+  0x200001A5:  00           DC.B       0x00                     ; '\0'
+  0x200001A6:  00           DC.B       0x00                     ; '\0'
+  0x200001A7:  00           DC.B       0x00                     ; '\0'
+  0x200001A8:  00           DC.B       0x00                     ; '\0'
+  0x200001A9:  00           DC.B       0x00                     ; '\0'
+  0x200001AA:  00           DC.B       0x00                     ; '\0'
+  0x200001AB:  00           DC.B       0x00                     ; '\0'
+  0x200001AC:  00           DC.B       0x00                     ; '\0'
+  0x200001AD:  00           DC.B       0x00                     ; '\0'
+  0x200001AE:  00           DC.B       0x00                     ; '\0'
+  0x200001AF:  00           DC.B       0x00                     ; '\0'
+  0x200001B0:  00           DC.B       0x00                     ; '\0'
+  0x200001B1:  00           DC.B       0x00                     ; '\0'
+  0x200001B2:  00           DC.B       0x00                     ; '\0'
+  0x200001B3:  00           DC.B       0x00                     ; '\0'
+  0x200001B4:  00           DC.B       0x00                     ; '\0'
+  0x200001B5:  00           DC.B       0x00                     ; '\0'
+  0x200001B6:  00           DC.B       0x00                     ; '\0'
+  0x200001B7:  00           DC.B       0x00                     ; '\0'
+  0x200001B8:  00           DC.B       0x00                     ; '\0'
+  0x200001B9:  00           DC.B       0x00                     ; '\0'
+  0x200001BA:  00           DC.B       0x00                     ; '\0'
+  0x200001BB:  00           DC.B       0x00                     ; '\0'
+  0x200001BC:  00           DC.B       0x00                     ; '\0'
+  0x200001BD:  00           DC.B       0x00                     ; '\0'
+  0x200001BE:  00           DC.B       0x00                     ; '\0'
+  0x200001BF:  00           DC.B       0x00                     ; '\0'
+  0x200001C0:  00           DC.B       0x00                     ; '\0'
+  0x200001C1:  00           DC.B       0x00                     ; '\0'
+  0x200001C2:  00           DC.B       0x00                     ; '\0'
+  0x200001C3:  00           DC.B       0x00                     ; '\0'
+  0x200001C4:  00           DC.B       0x00                     ; '\0'
+  0x200001C5:  00           DC.B       0x00                     ; '\0'
+  0x200001C6:  00           DC.B       0x00                     ; '\0'
+  0x200001C7:  00           DC.B       0x00                     ; '\0'
+  0x200001C8:  00           DC.B       0x00                     ; '\0'
+  0x200001C9:  00           DC.B       0x00                     ; '\0'
+  0x200001CA:  00           DC.B       0x00                     ; '\0'
+  0x200001CB:  00           DC.B       0x00                     ; '\0'
+  0x200001CC:  00           DC.B       0x00                     ; '\0'
+  0x200001CD:  00           DC.B       0x00                     ; '\0'
+  0x200001CE:  00           DC.B       0x00                     ; '\0'
+  0x200001CF:  00           DC.B       0x00                     ; '\0'
+  0x200001D0:  00           DC.B       0x00                     ; '\0'
+  0x200001D1:  00           DC.B       0x00                     ; '\0'
+  0x200001D2:  00           DC.B       0x00                     ; '\0'
+  0x200001D3:  00           DC.B       0x00                     ; '\0'
+  0x200001D4:  00           DC.B       0x00                     ; '\0'
+  0x200001D5:  00           DC.B       0x00                     ; '\0'
+  0x200001D6:  00           DC.B       0x00                     ; '\0'
+  0x200001D7:  00           DC.B       0x00                     ; '\0'
+  0x200001D8:  00           DC.B       0x00                     ; '\0'
+  0x200001D9:  00           DC.B       0x00                     ; '\0'
+  0x200001DA:  00           DC.B       0x00                     ; '\0'
+  0x200001DB:  00           DC.B       0x00                     ; '\0'
+  0x200001DC:  00           DC.B       0x00                     ; '\0'
+  0x200001DD:  00           DC.B       0x00                     ; '\0'
+  0x200001DE:  00           DC.B       0x00                     ; '\0'
+  0x200001DF:  00           DC.B       0x00                     ; '\0'
+  0x200001E0:  00           DC.B       0x00                     ; '\0'
+  0x200001E1:  00           DC.B       0x00                     ; '\0'
+  0x200001E2:  00           DC.B       0x00                     ; '\0'
+  0x200001E3:  00           DC.B       0x00                     ; '\0'
+  0x200001E4:  00           DC.B       0x00                     ; '\0'
+  0x200001E5:  00           DC.B       0x00                     ; '\0'
+  0x200001E6:  00           DC.B       0x00                     ; '\0'
+  0x200001E7:  00           DC.B       0x00                     ; '\0'
+  0x200001E8:  00           DC.B       0x00                     ; '\0'
+  0x200001E9:  00           DC.B       0x00                     ; '\0'
+  0x200001EA:  00           DC.B       0x00                     ; '\0'
+  0x200001EB:  00           DC.B       0x00                     ; '\0'
+  0x200001EC:  00           DC.B       0x00                     ; '\0'
+  0x200001ED:  00           DC.B       0x00                     ; '\0'
+  0x200001EE:  00           DC.B       0x00                     ; '\0'
+  0x200001EF:  00           DC.B       0x00                     ; '\0'
+  0x200001F0:  00           DC.B       0x00                     ; '\0'
+  0x200001F1:  00           DC.B       0x00                     ; '\0'
+  0x200001F2:  00           DC.B       0x00                     ; '\0'
+  0x200001F3:  00           DC.B       0x00                     ; '\0'
+  0x200001F4:  00           DC.B       0x00                     ; '\0'
+  0x200001F5:  00           DC.B       0x00                     ; '\0'
+  0x200001F6:  00           DC.B       0x00                     ; '\0'
+  0x200001F7:  00           DC.B       0x00                     ; '\0'
+  0x200001F8:  00           DC.B       0x00                     ; '\0'
+  0x200001F9:  00           DC.B       0x00                     ; '\0'
+  0x200001FA:  00           DC.B       0x00                     ; '\0'
+  0x200001FB:  00           DC.B       0x00                     ; '\0'
+  0x200001FC:  00           DC.B       0x00                     ; '\0'
+  0x200001FD:  00           DC.B       0x00                     ; '\0'
+  0x200001FE:  00           DC.B       0x00                     ; '\0'
+  0x200001FF:  00           DC.B       0x00                     ; '\0'
+  0x20000200:  00           DC.B       0x00                     ; '\0'
+  0x20000201:  00           DC.B       0x00                     ; '\0'
+  0x20000202:  00           DC.B       0x00                     ; '\0'
+  0x20000203:  00           DC.B       0x00                     ; '\0'
+  0x20000204:  00           DC.B       0x00                     ; '\0'
+  0x20000205:  00           DC.B       0x00                     ; '\0'
+  0x20000206:  00           DC.B       0x00                     ; '\0'
+  0x20000207:  00           DC.B       0x00                     ; '\0'
+  0x20000208:  00           DC.B       0x00                     ; '\0'
+  0x20000209:  00           DC.B       0x00                     ; '\0'
+  0x2000020A:  00           DC.B       0x00                     ; '\0'
+  0x2000020B:  00           DC.B       0x00                     ; '\0'
+  0x2000020C:  00           DC.B       0x00                     ; '\0'
+  0x2000020D:  00           DC.B       0x00                     ; '\0'
+  0x2000020E:  00           DC.B       0x00                     ; '\0'
+  0x2000020F:  00           DC.B       0x00                     ; '\0'
+  0x20000210:  00           DC.B       0x00                     ; '\0'
+  0x20000211:  00           DC.B       0x00                     ; '\0'
+  0x20000212:  00           DC.B       0x00                     ; '\0'
+  0x20000213:  00           DC.B       0x00                     ; '\0'
+  0x20000214:  00           DC.B       0x00                     ; '\0'
+  0x20000215:  00           DC.B       0x00                     ; '\0'
+  0x20000216:  00           DC.B       0x00                     ; '\0'
+  0x20000217:  00           DC.B       0x00                     ; '\0'
+  0x20000218:  00           DC.B       0x00                     ; '\0'
+  0x20000219:  00           DC.B       0x00                     ; '\0'
+  0x2000021A:  00           DC.B       0x00                     ; '\0'
+  0x2000021B:  00           DC.B       0x00                     ; '\0'
+  0x2000021C:  00           DC.B       0x00                     ; '\0'
+  0x2000021D:  00           DC.B       0x00                     ; '\0'
+  0x2000021E:  00           DC.B       0x00                     ; '\0'
+  0x2000021F:  00           DC.B       0x00                     ; '\0'
+  0x20000220:  00           DC.B       0x00                     ; '\0'
+  0x20000221:  00           DC.B       0x00                     ; '\0'
+  0x20000222:  00           DC.B       0x00                     ; '\0'
+  0x20000223:  00           DC.B       0x00                     ; '\0'
+  0x20000224:  00           DC.B       0x00                     ; '\0'
+  0x20000225:  00           DC.B       0x00                     ; '\0'
+  0x20000226:  00           DC.B       0x00                     ; '\0'
+  0x20000227:  00           DC.B       0x00                     ; '\0'
+  0x20000228:  00           DC.B       0x00                     ; '\0'
+  0x20000229:  00           DC.B       0x00                     ; '\0'
+  0x2000022A:  00           DC.B       0x00                     ; '\0'
+  0x2000022B:  00           DC.B       0x00                     ; '\0'
+  0x2000022C:  00           DC.B       0x00                     ; '\0'
+  0x2000022D:  00           DC.B       0x00                     ; '\0'
+  0x2000022E:  00           DC.B       0x00                     ; '\0'
+  0x2000022F:  00           DC.B       0x00                     ; '\0'
+  0x20000230:  00           DC.B       0x00                     ; '\0'
+  0x20000231:  00           DC.B       0x00                     ; '\0'
+  0x20000232:  00           DC.B       0x00                     ; '\0'
+  0x20000233:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.sys_data from PowerPro_lto.o, size=224, align=4

+
+
sys_data:
+  0x20000234:  76           DC.B       0x76                     ; 'v'
+  0x20000235:  6F           DC.B       0x6F                     ; 'o'
+  0x20000236:  6C           DC.B       0x6C                     ; 'l'
+  0x20000237:  74           DC.B       0x74                     ; 't'
+  0x20000238:  61           DC.B       0x61                     ; 'a'
+  0x20000239:  67           DC.B       0x67                     ; 'g'
+  0x2000023A:  65           DC.B       0x65                     ; 'e'
+  0x2000023B:  20           DC.B       0x20                     ; ' '
+  0x2000023C:  69           DC.B       0x69                     ; 'i'
+  0x2000023D:  6E           DC.B       0x6E                     ; 'n'
+  0x2000023E:  3D           DC.B       0x3D                     ; '='
+  0x2000023F:  20           DC.B       0x20                     ; ' '
+  0x20000240:  25           DC.B       0x25                     ; '%'
+  0x20000241:  64           DC.B       0x64                     ; 'd'
+  0x20000242:  2C           DC.B       0x2C                     ; ','
+  0x20000243:  20           DC.B       0x20                     ; ' '
+  0x20000244:  6F           DC.B       0x6F                     ; 'o'
+  0x20000245:  75           DC.B       0x75                     ; 'u'
+  0x20000246:  74           DC.B       0x74                     ; 't'
+  0x20000247:  3D           DC.B       0x3D                     ; '='
+  0x20000248:  20           DC.B       0x20                     ; ' '
+  0x20000249:  25           DC.B       0x25                     ; '%'
+  0x2000024A:  64           DC.B       0x64                     ; 'd'
+  0x2000024B:  2C           DC.B       0x2C                     ; ','
+  0x2000024C:  20           DC.B       0x20                     ; ' '
+  0x2000024D:  64           DC.B       0x64                     ; 'd'
+  0x2000024E:  72           DC.B       0x72                     ; 'r'
+  0x2000024F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000250:  70           DC.B       0x70                     ; 'p'
+  0x20000251:  20           DC.B       0x20                     ; ' '
+  0x20000252:  25           DC.B       0x25                     ; '%'
+  0x20000253:  64           DC.B       0x64                     ; 'd'
+  0x20000254:  0D           DC.B       0x0D                     ; '\r'
+  0x20000255:  0A           DC.B       0x0A                     ; '\n'
+  0x20000256:  00           DC.B       0x00                     ; '\0'
+  0x20000257:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000258:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000259:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000025A:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000025B:  EC           DC.B       0xEC                     ; '\xEC'
+  0x2000025C:  00           DC.B       0x00                     ; '\0'
+  0x2000025D:  00           DC.B       0x00                     ; '\0'
+  0x2000025E:  08           DC.B       0x08                     ; '\b'
+  0x2000025F:  06           DC.B       0x06                     ; '\x06'
+  0x20000260:  00           DC.B       0x00                     ; '\0'
+  0x20000261:  00           DC.B       0x00                     ; '\0'
+  0x20000262:  00           DC.B       0x00                     ; '\0'
+  0x20000263:  02           DC.B       0x02                     ; '\x02'
+  0x20000264:  01           DC.B       0x01                     ; '\x01'
+  0x20000265:  00           DC.B       0x00                     ; '\0'
+  0x20000266:  00           DC.B       0x00                     ; '\0'
+  0x20000267:  01           DC.B       0x01                     ; '\x01'
+  0x20000268:  00           DC.B       0x00                     ; '\0'
+  0x20000269:  54           DC.B       0x54                     ; 'T'
+  0x2000026A:  00           DC.B       0x00                     ; '\0'
+  0x2000026B:  00           DC.B       0x00                     ; '\0'
+  0x2000026C:  00           DC.B       0x00                     ; '\0'
+  0x2000026D:  00           DC.B       0x00                     ; '\0'
+  0x2000026E:  00           DC.B       0x00                     ; '\0'
+  0x2000026F:  00           DC.B       0x00                     ; '\0'
+  0x20000270:  00           DC.B       0x00                     ; '\0'
+  0x20000271:  00           DC.B       0x00                     ; '\0'
+  0x20000272:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000273:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000274:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000275:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000276:  EC           DC.B       0xEC                     ; '\xEC'
+  0x20000277:  00           DC.B       0x00                     ; '\0'
+  0x20000278:  00           DC.B       0x00                     ; '\0'
+  0x20000279:  08           DC.B       0x08                     ; '\b'
+  0x2000027A:  0A           DC.B       0x0A                     ; '\n'
+  0x2000027B:  00           DC.B       0x00                     ; '\0'
+  0x2000027C:  00           DC.B       0x00                     ; '\0'
+  0x2000027D:  00           DC.B       0x00                     ; '\0'
+  0x2000027E:  02           DC.B       0x02                     ; '\x02'
+  0x2000027F:  01           DC.B       0x01                     ; '\x01'
+  0x20000280:  00           DC.B       0x00                     ; '\0'
+  0x20000281:  00           DC.B       0x00                     ; '\0'
+  0x20000282:  01           DC.B       0x01                     ; '\x01'
+  0x20000283:  00           DC.B       0x00                     ; '\0'
+  0x20000284:  56           DC.B       0x56                     ; 'V'
+  0x20000285:  00           DC.B       0x00                     ; '\0'
+  0x20000286:  00           DC.B       0x00                     ; '\0'
+  0x20000287:  00           DC.B       0x00                     ; '\0'
+  0x20000288:  00           DC.B       0x00                     ; '\0'
+  0x20000289:  00           DC.B       0x00                     ; '\0'
+  0x2000028A:  00           DC.B       0x00                     ; '\0'
+  0x2000028B:  00           DC.B       0x00                     ; '\0'
+  0x2000028C:  00           DC.B       0x00                     ; '\0'
+  0x2000028D:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000028E:  FF           DC.B       0xFF                     ; '\xFF'
+  0x2000028F:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000290:  FF           DC.B       0xFF                     ; '\xFF'
+  0x20000291:  EC           DC.B       0xEC                     ; '\xEC'
+  0x20000292:  00           DC.B       0x00                     ; '\0'
+  0x20000293:  00           DC.B       0x00                     ; '\0'
+  0x20000294:  08           DC.B       0x08                     ; '\b'
+  0x20000295:  0C           DC.B       0x0C                     ; '\x0C'
+  0x20000296:  00           DC.B       0x00                     ; '\0'
+  0x20000297:  00           DC.B       0x00                     ; '\0'
+  0x20000298:  00           DC.B       0x00                     ; '\0'
+  0x20000299:  02           DC.B       0x02                     ; '\x02'
+  0x2000029A:  01           DC.B       0x01                     ; '\x01'
+  0x2000029B:  00           DC.B       0x00                     ; '\0'
+  0x2000029C:  00           DC.B       0x00                     ; '\0'
+  0x2000029D:  01           DC.B       0x01                     ; '\x01'
+  0x2000029E:  00           DC.B       0x00                     ; '\0'
+  0x2000029F:  57           DC.B       0x57                     ; 'W'
+  0x200002A0:  00           DC.B       0x00                     ; '\0'
+  0x200002A1:  00           DC.B       0x00                     ; '\0'
+  0x200002A2:  00           DC.B       0x00                     ; '\0'
+  0x200002A3:  00           DC.B       0x00                     ; '\0'
+  0x200002A4:  00           DC.B       0x00                     ; '\0'
+  0x200002A5:  00           DC.B       0x00                     ; '\0'
+  0x200002A6:  00           DC.B       0x00                     ; '\0'
+  0x200002A7:  00           DC.B       0x00                     ; '\0'
+  0x200002A8:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002A9:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002AA:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002AB:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002AC:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200002AD:  02           DC.B       0x02                     ; '\x02'
+  0x200002AE:  00           DC.B       0x00                     ; '\0'
+  0x200002AF:  08           DC.B       0x08                     ; '\b'
+  0x200002B0:  06           DC.B       0x06                     ; '\x06'
+  0x200002B1:  00           DC.B       0x00                     ; '\0'
+  0x200002B2:  00           DC.B       0x00                     ; '\0'
+  0x200002B3:  00           DC.B       0x00                     ; '\0'
+  0x200002B4:  80           DC.B       0x80                     ; '\x80'
+  0x200002B5:  01           DC.B       0x01                     ; '\x01'
+  0x200002B6:  00           DC.B       0x00                     ; '\0'
+  0x200002B7:  00           DC.B       0x00                     ; '\0'
+  0x200002B8:  01           DC.B       0x01                     ; '\x01'
+  0x200002B9:  00           DC.B       0x00                     ; '\0'
+  0x200002BA:  54           DC.B       0x54                     ; 'T'
+  0x200002BB:  84           DC.B       0x84                     ; '\x84'
+  0x200002BC:  01           DC.B       0x01                     ; '\x01'
+  0x200002BD:  00           DC.B       0x00                     ; '\0'
+  0x200002BE:  00           DC.B       0x00                     ; '\0'
+  0x200002BF:  32           DC.B       0x32                     ; '2'
+  0x200002C0:  02           DC.B       0x02                     ; '\x02'
+  0x200002C1:  00           DC.B       0x00                     ; '\0'
+  0x200002C2:  00           DC.B       0x00                     ; '\0'
+  0x200002C3:  01           DC.B       0x01                     ; '\x01'
+  0x200002C4:  00           DC.B       0x00                     ; '\0'
+  0x200002C5:  54           DC.B       0x54                     ; 'T'
+  0x200002C6:  7E           DC.B       0x7E                     ; '~'
+  0x200002C7:  02           DC.B       0x02                     ; '\x02'
+  0x200002C8:  00           DC.B       0x00                     ; '\0'
+  0x200002C9:  00           DC.B       0x00                     ; '\0'
+  0x200002CA:  70           DC.B       0x70                     ; 'p'
+  0x200002CB:  03           DC.B       0x03                     ; '\x03'
+  0x200002CC:  00           DC.B       0x00                     ; '\0'
+  0x200002CD:  00           DC.B       0x00                     ; '\0'
+  0x200002CE:  01           DC.B       0x01                     ; '\x01'
+  0x200002CF:  00           DC.B       0x00                     ; '\0'
+  0x200002D0:  54           DC.B       0x54                     ; 'T'
+  0x200002D1:  72           DC.B       0x72                     ; 'r'
+  0x200002D2:  03           DC.B       0x03                     ; '\x03'
+  0x200002D3:  00           DC.B       0x00                     ; '\0'
+  0x200002D4:  00           DC.B       0x00                     ; '\0'
+  0x200002D5:  92           DC.B       0x92                     ; '\x92'
+  0x200002D6:  03           DC.B       0x03                     ; '\x03'
+  0x200002D7:  00           DC.B       0x00                     ; '\0'
+  0x200002D8:  00           DC.B       0x00                     ; '\0'
+  0x200002D9:  01           DC.B       0x01                     ; '\x01'
+  0x200002DA:  00           DC.B       0x00                     ; '\0'
+  0x200002DB:  54           DC.B       0x54                     ; 'T'
+  0x200002DC:  00           DC.B       0x00                     ; '\0'
+  0x200002DD:  00           DC.B       0x00                     ; '\0'
+  0x200002DE:  00           DC.B       0x00                     ; '\0'
+  0x200002DF:  00           DC.B       0x00                     ; '\0'
+  0x200002E0:  00           DC.B       0x00                     ; '\0'
+  0x200002E1:  00           DC.B       0x00                     ; '\0'
+  0x200002E2:  00           DC.B       0x00                     ; '\0'
+  0x200002E3:  00           DC.B       0x00                     ; '\0'
+  0x200002E4:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E5:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E6:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E7:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200002E8:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200002E9:  02           DC.B       0x02                     ; '\x02'
+  0x200002EA:  00           DC.B       0x00                     ; '\0'
+  0x200002EB:  08           DC.B       0x08                     ; '\b'
+  0x200002EC:  10           DC.B       0x10                     ; '\x10'
+  0x200002ED:  00           DC.B       0x00                     ; '\0'
+  0x200002EE:  00           DC.B       0x00                     ; '\0'
+  0x200002EF:  00           DC.B       0x00                     ; '\0'
+  0x200002F0:  B6           DC.B       0xB6                     ; '\xB6'
+  0x200002F1:  00           DC.B       0x00                     ; '\0'
+  0x200002F2:  00           DC.B       0x00                     ; '\0'
+  0x200002F3:  00           DC.B       0x00                     ; '\0'
+  0x200002F4:  01           DC.B       0x01                     ; '\x01'
+  0x200002F5:  00           DC.B       0x00                     ; '\0'
+  0x200002F6:  53           DC.B       0x53                     ; 'S'
+  0x200002F7:  EC           DC.B       0xEC                     ; '\xEC'
+  0x200002F8:  00           DC.B       0x00                     ; '\0'
+  0x200002F9:  00           DC.B       0x00                     ; '\0'
+  0x200002FA:  00           DC.B       0x00                     ; '\0'
+  0x200002FB:  3E           DC.B       0x3E                     ; '>'
+  0x200002FC:  01           DC.B       0x01                     ; '\x01'
+  0x200002FD:  00           DC.B       0x00                     ; '\0'
+  0x200002FE:  00           DC.B       0x00                     ; '\0'
+  0x200002FF:  01           DC.B       0x01                     ; '\x01'
+  0x20000300:  00           DC.B       0x00                     ; '\0'
+  0x20000301:  53           DC.B       0x53                     ; 'S'
+  0x20000302:  56           DC.B       0x56                     ; 'V'
+  0x20000303:  01           DC.B       0x01                     ; '\x01'
+  0x20000304:  00           DC.B       0x00                     ; '\0'
+  0x20000305:  00           DC.B       0x00                     ; '\0'
+  0x20000306:  5E           DC.B       0x5E                     ; '^'
+  0x20000307:  01           DC.B       0x01                     ; '\x01'
+  0x20000308:  00           DC.B       0x00                     ; '\0'
+  0x20000309:  00           DC.B       0x00                     ; '\0'
+  0x2000030A:  01           DC.B       0x01                     ; '\x01'
+  0x2000030B:  00           DC.B       0x00                     ; '\0'
+  0x2000030C:  53           DC.B       0x53                     ; 'S'
+  0x2000030D:  72           DC.B       0x72                     ; 'r'
+  0x2000030E:  01           DC.B       0x01                     ; '\x01'
+  0x2000030F:  00           DC.B       0x00                     ; '\0'
+  0x20000310:  00           DC.B       0x00                     ; '\0'
+  0x20000311:  80           DC.B       0x80                     ; '\x80'
+  0x20000312:  01           DC.B       0x01                     ; '\x01'
+  0x20000313:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc._SEGGER_RTT from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=168, align=4

+
+
_SEGGER_RTT:
+  0x20000314:  30           DC.B       0x30                     ; '0'
+  0x20000315:  31           DC.B       0x31                     ; '1'
+  0x20000316:  32           DC.B       0x32                     ; '2'
+  0x20000317:  33           DC.B       0x33                     ; '3'
+  0x20000318:  34           DC.B       0x34                     ; '4'
+  0x20000319:  35           DC.B       0x35                     ; '5'
+  0x2000031A:  36           DC.B       0x36                     ; '6'
+  0x2000031B:  37           DC.B       0x37                     ; '7'
+  0x2000031C:  38           DC.B       0x38                     ; '8'
+  0x2000031D:  39           DC.B       0x39                     ; '9'
+  0x2000031E:  41           DC.B       0x41                     ; 'A'
+  0x2000031F:  42           DC.B       0x42                     ; 'B'
+  0x20000320:  43           DC.B       0x43                     ; 'C'
+  0x20000321:  44           DC.B       0x44                     ; 'D'
+  0x20000322:  45           DC.B       0x45                     ; 'E'
+  0x20000323:  46           DC.B       0x46                     ; 'F'
+  0x20000324:  00           DC.B       0x00                     ; '\0'
+  0x20000325:  00           DC.B       0x00                     ; '\0'
+  0x20000326:  00           DC.B       0x00                     ; '\0'
+  0x20000327:  00           DC.B       0x00                     ; '\0'
+  0x20000328:  00           DC.B       0x00                     ; '\0'
+  0x20000329:  00           DC.B       0x00                     ; '\0'
+  0x2000032A:  54           DC.B       0x54                     ; 'T'
+  0x2000032B:  54           DC.B       0x54                     ; 'T'
+  0x2000032C:  52           DC.B       0x52                     ; 'R'
+  0x2000032D:  20           DC.B       0x20                     ; ' '
+  0x2000032E:  52           DC.B       0x52                     ; 'R'
+  0x2000032F:  45           DC.B       0x45                     ; 'E'
+  0x20000330:  47           DC.B       0x47                     ; 'G'
+  0x20000331:  47           DC.B       0x47                     ; 'G'
+  0x20000332:  45           DC.B       0x45                     ; 'E'
+  0x20000333:  53           DC.B       0x53                     ; 'S'
+  0x20000334:  00           DC.B       0x00                     ; '\0'
+  0x20000335:  54           DC.B       0x54                     ; 'T'
+  0x20000336:  65           DC.B       0x65                     ; 'e'
+  0x20000337:  72           DC.B       0x72                     ; 'r'
+  0x20000338:  6D           DC.B       0x6D                     ; 'm'
+  0x20000339:  69           DC.B       0x69                     ; 'i'
+  0x2000033A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000033B:  61           DC.B       0x61                     ; 'a'
+  0x2000033C:  6C           DC.B       0x6C                     ; 'l'
+  0x2000033D:  00           DC.B       0x00                     ; '\0'
+  0x2000033E:  00           DC.B       0x00                     ; '\0'
+  0x2000033F:  53           DC.B       0x53                     ; 'S'
+  0x20000340:  45           DC.B       0x45                     ; 'E'
+  0x20000341:  47           DC.B       0x47                     ; 'G'
+  0x20000342:  47           DC.B       0x47                     ; 'G'
+  0x20000343:  45           DC.B       0x45                     ; 'E'
+  0x20000344:  52           DC.B       0x52                     ; 'R'
+  0x20000345:  20           DC.B       0x20                     ; ' '
+  0x20000346:  43           DC.B       0x43                     ; 'C'
+  0x20000347:  2F           DC.B       0x2F                     ; '/'
+  0x20000348:  43           DC.B       0x43                     ; 'C'
+  0x20000349:  2B           DC.B       0x2B                     ; '+'
+  0x2000034A:  2B           DC.B       0x2B                     ; '+'
+  0x2000034B:  20           DC.B       0x20                     ; ' '
+  0x2000034C:  63           DC.B       0x63                     ; 'c'
+  0x2000034D:  6F           DC.B       0x6F                     ; 'o'
+  0x2000034E:  6D           DC.B       0x6D                     ; 'm'
+  0x2000034F:  70           DC.B       0x70                     ; 'p'
+  0x20000350:  69           DC.B       0x69                     ; 'i'
+  0x20000351:  6C           DC.B       0x6C                     ; 'l'
+  0x20000352:  65           DC.B       0x65                     ; 'e'
+  0x20000353:  72           DC.B       0x72                     ; 'r'
+  0x20000354:  20           DC.B       0x20                     ; ' '
+  0x20000355:  76           DC.B       0x76                     ; 'v'
+  0x20000356:  65           DC.B       0x65                     ; 'e'
+  0x20000357:  72           DC.B       0x72                     ; 'r'
+  0x20000358:  73           DC.B       0x73                     ; 's'
+  0x20000359:  69           DC.B       0x69                     ; 'i'
+  0x2000035A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000035B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000035C:  20           DC.B       0x20                     ; ' '
+  0x2000035D:  32           DC.B       0x32                     ; '2'
+  0x2000035E:  30           DC.B       0x30                     ; '0'
+  0x2000035F:  2E           DC.B       0x2E                     ; '.'
+  0x20000360:  31           DC.B       0x31                     ; '1'
+  0x20000361:  2E           DC.B       0x2E                     ; '.'
+  0x20000362:  32           DC.B       0x32                     ; '2'
+  0x20000363:  20           DC.B       0x20                     ; ' '
+  0x20000364:  28           DC.B       0x28                     ; '('
+  0x20000365:  62           DC.B       0x62                     ; 'b'
+  0x20000366:  61           DC.B       0x61                     ; 'a'
+  0x20000367:  73           DC.B       0x73                     ; 's'
+  0x20000368:  65           DC.B       0x65                     ; 'e'
+  0x20000369:  64           DC.B       0x64                     ; 'd'
+  0x2000036A:  20           DC.B       0x20                     ; ' '
+  0x2000036B:  6F           DC.B       0x6F                     ; 'o'
+  0x2000036C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000036D:  20           DC.B       0x20                     ; ' '
+  0x2000036E:  63           DC.B       0x63                     ; 'c'
+  0x2000036F:  6C           DC.B       0x6C                     ; 'l'
+  0x20000370:  61           DC.B       0x61                     ; 'a'
+  0x20000371:  6E           DC.B       0x6E                     ; 'n'
+  0x20000372:  67           DC.B       0x67                     ; 'g'
+  0x20000373:  20           DC.B       0x20                     ; ' '
+  0x20000374:  32           DC.B       0x32                     ; '2'
+  0x20000375:  30           DC.B       0x30                     ; '0'
+  0x20000376:  2E           DC.B       0x2E                     ; '.'
+  0x20000377:  31           DC.B       0x31                     ; '1'
+  0x20000378:  2E           DC.B       0x2E                     ; '.'
+  0x20000379:  38           DC.B       0x38                     ; '8'
+  0x2000037A:  29           DC.B       0x29                     ; ')'
+  0x2000037B:  00           DC.B       0x00                     ; '\0'
+  0x2000037C:  41           DC.B       0x41                     ; 'A'
+  0x2000037D:  35           DC.B       0x35                     ; '5'
+  0x2000037E:  00           DC.B       0x00                     ; '\0'
+  0x2000037F:  00           DC.B       0x00                     ; '\0'
+  0x20000380:  00           DC.B       0x00                     ; '\0'
+  0x20000381:  61           DC.B       0x61                     ; 'a'
+  0x20000382:  65           DC.B       0x65                     ; 'e'
+  0x20000383:  61           DC.B       0x61                     ; 'a'
+  0x20000384:  62           DC.B       0x62                     ; 'b'
+  0x20000385:  69           DC.B       0x69                     ; 'i'
+  0x20000386:  00           DC.B       0x00                     ; '\0'
+  0x20000387:  01           DC.B       0x01                     ; '\x01'
+  0x20000388:  2B           DC.B       0x2B                     ; '+'
+  0x20000389:  00           DC.B       0x00                     ; '\0'
+  0x2000038A:  00           DC.B       0x00                     ; '\0'
+  0x2000038B:  00           DC.B       0x00                     ; '\0'
+  0x2000038C:  43           DC.B       0x43                     ; 'C'
+  0x2000038D:  32           DC.B       0x32                     ; '2'
+  0x2000038E:  2E           DC.B       0x2E                     ; '.'
+  0x2000038F:  30           DC.B       0x30                     ; '0'
+  0x20000390:  39           DC.B       0x39                     ; '9'
+  0x20000391:  00           DC.B       0x00                     ; '\0'
+  0x20000392:  06           DC.B       0x06                     ; '\x06'
+  0x20000393:  0C           DC.B       0x0C                     ; '\x0C'
+  0x20000394:  07           DC.B       0x07                     ; '\x07'
+  0x20000395:  4D           DC.B       0x4D                     ; 'M'
+  0x20000396:  08           DC.B       0x08                     ; '\b'
+  0x20000397:  00           DC.B       0x00                     ; '\0'
+  0x20000398:  09           DC.B       0x09                     ; '\t'
+  0x20000399:  01           DC.B       0x01                     ; '\x01'
+  0x2000039A:  0E           DC.B       0x0E                     ; '\x0E'
+  0x2000039B:  00           DC.B       0x00                     ; '\0'
+  0x2000039C:  11           DC.B       0x11                     ; '\x11'
+  0x2000039D:  01           DC.B       0x01                     ; '\x01'
+  0x2000039E:  12           DC.B       0x12                     ; '\x12'
+  0x2000039F:  04           DC.B       0x04                     ; '\x04'
+  0x200003A0:  14           DC.B       0x14                     ; '\x14'
+  0x200003A1:  01           DC.B       0x01                     ; '\x01'
+  0x200003A2:  15           DC.B       0x15                     ; '\x15'
+  0x200003A3:  00           DC.B       0x00                     ; '\0'
+  0x200003A4:  17           DC.B       0x17                     ; '\x17'
+  0x200003A5:  03           DC.B       0x03                     ; '\x03'
+  0x200003A6:  18           DC.B       0x18                     ; '\x18'
+  0x200003A7:  01           DC.B       0x01                     ; '\x01'
+  0x200003A8:  19           DC.B       0x19                     ; '\x19'
+  0x200003A9:  01           DC.B       0x01                     ; '\x01'
+  0x200003AA:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200003AB:  01           DC.B       0x01                     ; '\x01'
+  0x200003AC:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200003AD:  04           DC.B       0x04                     ; '\x04'
+  0x200003AE:  22           DC.B       0x22                     ; '\"'
+  0x200003AF:  00           DC.B       0x00                     ; '\0'
+  0x200003B0:  26           DC.B       0x26                     ; '&'
+  0x200003B1:  01           DC.B       0x01                     ; '\x01'
+  0x200003B2:  00           DC.B       0x00                     ; '\0'
+  0x200003B3:  00           DC.B       0x00                     ; '\0'
+  0x200003B4:  00           DC.B       0x00                     ; '\0'
+  0x200003B5:  00           DC.B       0x00                     ; '\0'
+  0x200003B6:  00           DC.B       0x00                     ; '\0'
+  0x200003B7:  00           DC.B       0x00                     ; '\0'
+  0x200003B8:  00           DC.B       0x00                     ; '\0'
+  0x200003B9:  00           DC.B       0x00                     ; '\0'
+  0x200003BA:  00           DC.B       0x00                     ; '\0'
+  0x200003BB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.huart1 from PowerPro_lto.o, size=148, align=4

+
+
huart1:
+  0x200003BC:  73           DC.B       0x73                     ; 's'
+  0x200003BD:  65           DC.B       0x65                     ; 'e'
+  0x200003BE:  74           DC.B       0x74                     ; 't'
+  0x200003BF:  7A           DC.B       0x7A                     ; 'z'
+  0x200003C0:  65           DC.B       0x65                     ; 'e'
+  0x200003C1:  20           DC.B       0x20                     ; ' '
+  0x200003C2:  6F           DC.B       0x6F                     ; 'o'
+  0x200003C3:  70           DC.B       0x70                     ; 'p'
+  0x200003C4:  74           DC.B       0x74                     ; 't'
+  0x200003C5:  69           DC.B       0x69                     ; 'i'
+  0x200003C6:  6F           DC.B       0x6F                     ; 'o'
+  0x200003C7:  6E           DC.B       0x6E                     ; 'n'
+  0x200003C8:  20           DC.B       0x20                     ; ' '
+  0x200003C9:  62           DC.B       0x62                     ; 'b'
+  0x200003CA:  79           DC.B       0x79                     ; 'y'
+  0x200003CB:  74           DC.B       0x74                     ; 't'
+  0x200003CC:  65           DC.B       0x65                     ; 'e'
+  0x200003CD:  0D           DC.B       0x0D                     ; '\r'
+  0x200003CE:  00           DC.B       0x00                     ; '\0'
+  0x200003CF:  4B           DC.B       0x4B                     ; 'K'
+  0x200003D0:  6F           DC.B       0x6F                     ; 'o'
+  0x200003D1:  6E           DC.B       0x6E                     ; 'n'
+  0x200003D2:  66           DC.B       0x66                     ; 'f'
+  0x200003D3:  69           DC.B       0x69                     ; 'i'
+  0x200003D4:  67           DC.B       0x67                     ; 'g'
+  0x200003D5:  20           DC.B       0x20                     ; ' '
+  0x200003D6:  76           DC.B       0x76                     ; 'v'
+  0x200003D7:  6F           DC.B       0x6F                     ; 'o'
+  0x200003D8:  72           DC.B       0x72                     ; 'r'
+  0x200003D9:  68           DC.B       0x68                     ; 'h'
+  0x200003DA:  61           DC.B       0x61                     ; 'a'
+  0x200003DB:  6E           DC.B       0x6E                     ; 'n'
+  0x200003DC:  64           DC.B       0x64                     ; 'd'
+  0x200003DD:  65           DC.B       0x65                     ; 'e'
+  0x200003DE:  6E           DC.B       0x6E                     ; 'n'
+  0x200003DF:  0D           DC.B       0x0D                     ; '\r'
+  0x200003E0:  00           DC.B       0x00                     ; '\0'
+  0x200003E1:  4E           DC.B       0x4E                     ; 'N'
+  0x200003E2:  65           DC.B       0x65                     ; 'e'
+  0x200003E3:  75           DC.B       0x75                     ; 'u'
+  0x200003E4:  65           DC.B       0x65                     ; 'e'
+  0x200003E5:  20           DC.B       0x20                     ; ' '
+  0x200003E6:  56           DC.B       0x56                     ; 'V'
+  0x200003E7:  65           DC.B       0x65                     ; 'e'
+  0x200003E8:  72           DC.B       0x72                     ; 'r'
+  0x200003E9:  73           DC.B       0x73                     ; 's'
+  0x200003EA:  69           DC.B       0x69                     ; 'i'
+  0x200003EB:  6F           DC.B       0x6F                     ; 'o'
+  0x200003EC:  6E           DC.B       0x6E                     ; 'n'
+  0x200003ED:  20           DC.B       0x20                     ; ' '
+  0x200003EE:  50           DC.B       0x50                     ; 'P'
+  0x200003EF:  61           DC.B       0x61                     ; 'a'
+  0x200003F0:  72           DC.B       0x72                     ; 'r'
+  0x200003F1:  61           DC.B       0x61                     ; 'a'
+  0x200003F2:  6D           DC.B       0x6D                     ; 'm'
+  0x200003F3:  65           DC.B       0x65                     ; 'e'
+  0x200003F4:  74           DC.B       0x74                     ; 't'
+  0x200003F5:  65           DC.B       0x65                     ; 'e'
+  0x200003F6:  72           DC.B       0x72                     ; 'r'
+  0x200003F7:  20           DC.B       0x20                     ; ' '
+  0x200003F8:  65           DC.B       0x65                     ; 'e'
+  0x200003F9:  72           DC.B       0x72                     ; 'r'
+  0x200003FA:  6B           DC.B       0x6B                     ; 'k'
+  0x200003FB:  61           DC.B       0x61                     ; 'a'
+  0x200003FC:  6E           DC.B       0x6E                     ; 'n'
+  0x200003FD:  6E           DC.B       0x6E                     ; 'n'
+  0x200003FE:  74           DC.B       0x74                     ; 't'
+  0x200003FF:  2C           DC.B       0x2C                     ; ','
+  0x20000400:  20           DC.B       0x20                     ; ' '
+  0x20000401:  73           DC.B       0x73                     ; 's'
+  0x20000402:  63           DC.B       0x63                     ; 'c'
+  0x20000403:  68           DC.B       0x68                     ; 'h'
+  0x20000404:  72           DC.B       0x72                     ; 'r'
+  0x20000405:  65           DC.B       0x65                     ; 'e'
+  0x20000406:  69           DC.B       0x69                     ; 'i'
+  0x20000407:  62           DC.B       0x62                     ; 'b'
+  0x20000408:  65           DC.B       0x65                     ; 'e'
+  0x20000409:  20           DC.B       0x20                     ; ' '
+  0x2000040A:  57           DC.B       0x57                     ; 'W'
+  0x2000040B:  65           DC.B       0x65                     ; 'e'
+  0x2000040C:  72           DC.B       0x72                     ; 'r'
+  0x2000040D:  6B           DC.B       0x6B                     ; 'k'
+  0x2000040E:  73           DC.B       0x73                     ; 's'
+  0x2000040F:  65           DC.B       0x65                     ; 'e'
+  0x20000410:  69           DC.B       0x69                     ; 'i'
+  0x20000411:  6E           DC.B       0x6E                     ; 'n'
+  0x20000412:  73           DC.B       0x73                     ; 's'
+  0x20000413:  74           DC.B       0x74                     ; 't'
+  0x20000414:  65           DC.B       0x65                     ; 'e'
+  0x20000415:  6C           DC.B       0x6C                     ; 'l'
+  0x20000416:  6C           DC.B       0x6C                     ; 'l'
+  0x20000417:  75           DC.B       0x75                     ; 'u'
+  0x20000418:  6E           DC.B       0x6E                     ; 'n'
+  0x20000419:  67           DC.B       0x67                     ; 'g'
+  0x2000041A:  0D           DC.B       0x0D                     ; '\r'
+  0x2000041B:  00           DC.B       0x00                     ; '\0'
+  0x2000041C:  45           DC.B       0x45                     ; 'E'
+  0x2000041D:  72           DC.B       0x72                     ; 'r'
+  0x2000041E:  73           DC.B       0x73                     ; 's'
+  0x2000041F:  74           DC.B       0x74                     ; 't'
+  0x20000420:  73           DC.B       0x73                     ; 's'
+  0x20000421:  74           DC.B       0x74                     ; 't'
+  0x20000422:  61           DC.B       0x61                     ; 'a'
+  0x20000423:  72           DC.B       0x72                     ; 'r'
+  0x20000424:  74           DC.B       0x74                     ; 't'
+  0x20000425:  20           DC.B       0x20                     ; ' '
+  0x20000426:  65           DC.B       0x65                     ; 'e'
+  0x20000427:  72           DC.B       0x72                     ; 'r'
+  0x20000428:  6B           DC.B       0x6B                     ; 'k'
+  0x20000429:  61           DC.B       0x61                     ; 'a'
+  0x2000042A:  6E           DC.B       0x6E                     ; 'n'
+  0x2000042B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000042C:  74           DC.B       0x74                     ; 't'
+  0x2000042D:  2C           DC.B       0x2C                     ; ','
+  0x2000042E:  20           DC.B       0x20                     ; ' '
+  0x2000042F:  73           DC.B       0x73                     ; 's'
+  0x20000430:  63           DC.B       0x63                     ; 'c'
+  0x20000431:  68           DC.B       0x68                     ; 'h'
+  0x20000432:  72           DC.B       0x72                     ; 'r'
+  0x20000433:  65           DC.B       0x65                     ; 'e'
+  0x20000434:  69           DC.B       0x69                     ; 'i'
+  0x20000435:  62           DC.B       0x62                     ; 'b'
+  0x20000436:  65           DC.B       0x65                     ; 'e'
+  0x20000437:  20           DC.B       0x20                     ; ' '
+  0x20000438:  57           DC.B       0x57                     ; 'W'
+  0x20000439:  65           DC.B       0x65                     ; 'e'
+  0x2000043A:  72           DC.B       0x72                     ; 'r'
+  0x2000043B:  6B           DC.B       0x6B                     ; 'k'
+  0x2000043C:  73           DC.B       0x73                     ; 's'
+  0x2000043D:  65           DC.B       0x65                     ; 'e'
+  0x2000043E:  69           DC.B       0x69                     ; 'i'
+  0x2000043F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000440:  73           DC.B       0x73                     ; 's'
+  0x20000441:  74           DC.B       0x74                     ; 't'
+  0x20000442:  65           DC.B       0x65                     ; 'e'
+  0x20000443:  6C           DC.B       0x6C                     ; 'l'
+  0x20000444:  6C           DC.B       0x6C                     ; 'l'
+  0x20000445:  75           DC.B       0x75                     ; 'u'
+  0x20000446:  6E           DC.B       0x6E                     ; 'n'
+  0x20000447:  67           DC.B       0x67                     ; 'g'
+  0x20000448:  0D           DC.B       0x0D                     ; '\r'
+  0x20000449:  00           DC.B       0x00                     ; '\0'
+  0x2000044A:  64           DC.B       0x64                     ; 'd'
+  0x2000044B:  65           DC.B       0x65                     ; 'e'
+  0x2000044C:  62           DC.B       0x62                     ; 'b'
+  0x2000044D:  75           DC.B       0x75                     ; 'u'
+  0x2000044E:  67           DC.B       0x67                     ; 'g'
+  0x2000044F:  20           DC.B       0x20                     ; ' '
+
+

Section .bss.hadc1 from PowerPro_lto.o, size=100, align=4

+
+
hadc1:
+  0x20000450:  73           DC.B       0x73                     ; 's'
+  0x20000451:  65           DC.B       0x65                     ; 'e'
+  0x20000452:  74           DC.B       0x74                     ; 't'
+  0x20000453:  7A           DC.B       0x7A                     ; 'z'
+  0x20000454:  65           DC.B       0x65                     ; 'e'
+  0x20000455:  20           DC.B       0x20                     ; ' '
+  0x20000456:  6F           DC.B       0x6F                     ; 'o'
+  0x20000457:  70           DC.B       0x70                     ; 'p'
+  0x20000458:  74           DC.B       0x74                     ; 't'
+  0x20000459:  69           DC.B       0x69                     ; 'i'
+  0x2000045A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000045B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000045C:  20           DC.B       0x20                     ; ' '
+  0x2000045D:  62           DC.B       0x62                     ; 'b'
+  0x2000045E:  79           DC.B       0x79                     ; 'y'
+  0x2000045F:  74           DC.B       0x74                     ; 't'
+  0x20000460:  65           DC.B       0x65                     ; 'e'
+  0x20000461:  0D           DC.B       0x0D                     ; '\r'
+  0x20000462:  00           DC.B       0x00                     ; '\0'
+  0x20000463:  4B           DC.B       0x4B                     ; 'K'
+  0x20000464:  6F           DC.B       0x6F                     ; 'o'
+  0x20000465:  6E           DC.B       0x6E                     ; 'n'
+  0x20000466:  66           DC.B       0x66                     ; 'f'
+  0x20000467:  69           DC.B       0x69                     ; 'i'
+  0x20000468:  67           DC.B       0x67                     ; 'g'
+  0x20000469:  20           DC.B       0x20                     ; ' '
+  0x2000046A:  76           DC.B       0x76                     ; 'v'
+  0x2000046B:  6F           DC.B       0x6F                     ; 'o'
+  0x2000046C:  72           DC.B       0x72                     ; 'r'
+  0x2000046D:  68           DC.B       0x68                     ; 'h'
+  0x2000046E:  61           DC.B       0x61                     ; 'a'
+  0x2000046F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000470:  64           DC.B       0x64                     ; 'd'
+  0x20000471:  65           DC.B       0x65                     ; 'e'
+  0x20000472:  6E           DC.B       0x6E                     ; 'n'
+  0x20000473:  0D           DC.B       0x0D                     ; '\r'
+  0x20000474:  00           DC.B       0x00                     ; '\0'
+  0x20000475:  4E           DC.B       0x4E                     ; 'N'
+  0x20000476:  65           DC.B       0x65                     ; 'e'
+  0x20000477:  75           DC.B       0x75                     ; 'u'
+  0x20000478:  65           DC.B       0x65                     ; 'e'
+  0x20000479:  20           DC.B       0x20                     ; ' '
+  0x2000047A:  56           DC.B       0x56                     ; 'V'
+  0x2000047B:  65           DC.B       0x65                     ; 'e'
+  0x2000047C:  72           DC.B       0x72                     ; 'r'
+  0x2000047D:  73           DC.B       0x73                     ; 's'
+  0x2000047E:  69           DC.B       0x69                     ; 'i'
+  0x2000047F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000480:  6E           DC.B       0x6E                     ; 'n'
+  0x20000481:  20           DC.B       0x20                     ; ' '
+  0x20000482:  50           DC.B       0x50                     ; 'P'
+  0x20000483:  61           DC.B       0x61                     ; 'a'
+  0x20000484:  72           DC.B       0x72                     ; 'r'
+  0x20000485:  61           DC.B       0x61                     ; 'a'
+  0x20000486:  6D           DC.B       0x6D                     ; 'm'
+  0x20000487:  65           DC.B       0x65                     ; 'e'
+  0x20000488:  74           DC.B       0x74                     ; 't'
+  0x20000489:  65           DC.B       0x65                     ; 'e'
+  0x2000048A:  72           DC.B       0x72                     ; 'r'
+  0x2000048B:  20           DC.B       0x20                     ; ' '
+  0x2000048C:  65           DC.B       0x65                     ; 'e'
+  0x2000048D:  72           DC.B       0x72                     ; 'r'
+  0x2000048E:  6B           DC.B       0x6B                     ; 'k'
+  0x2000048F:  61           DC.B       0x61                     ; 'a'
+  0x20000490:  6E           DC.B       0x6E                     ; 'n'
+  0x20000491:  6E           DC.B       0x6E                     ; 'n'
+  0x20000492:  74           DC.B       0x74                     ; 't'
+  0x20000493:  2C           DC.B       0x2C                     ; ','
+  0x20000494:  20           DC.B       0x20                     ; ' '
+  0x20000495:  73           DC.B       0x73                     ; 's'
+  0x20000496:  63           DC.B       0x63                     ; 'c'
+  0x20000497:  68           DC.B       0x68                     ; 'h'
+  0x20000498:  72           DC.B       0x72                     ; 'r'
+  0x20000499:  65           DC.B       0x65                     ; 'e'
+  0x2000049A:  69           DC.B       0x69                     ; 'i'
+  0x2000049B:  62           DC.B       0x62                     ; 'b'
+  0x2000049C:  65           DC.B       0x65                     ; 'e'
+  0x2000049D:  20           DC.B       0x20                     ; ' '
+  0x2000049E:  57           DC.B       0x57                     ; 'W'
+  0x2000049F:  65           DC.B       0x65                     ; 'e'
+  0x200004A0:  72           DC.B       0x72                     ; 'r'
+  0x200004A1:  6B           DC.B       0x6B                     ; 'k'
+  0x200004A2:  73           DC.B       0x73                     ; 's'
+  0x200004A3:  65           DC.B       0x65                     ; 'e'
+  0x200004A4:  69           DC.B       0x69                     ; 'i'
+  0x200004A5:  6E           DC.B       0x6E                     ; 'n'
+  0x200004A6:  73           DC.B       0x73                     ; 's'
+  0x200004A7:  74           DC.B       0x74                     ; 't'
+  0x200004A8:  65           DC.B       0x65                     ; 'e'
+  0x200004A9:  6C           DC.B       0x6C                     ; 'l'
+  0x200004AA:  6C           DC.B       0x6C                     ; 'l'
+  0x200004AB:  75           DC.B       0x75                     ; 'u'
+  0x200004AC:  6E           DC.B       0x6E                     ; 'n'
+  0x200004AD:  67           DC.B       0x67                     ; 'g'
+  0x200004AE:  0D           DC.B       0x0D                     ; '\r'
+  0x200004AF:  00           DC.B       0x00                     ; '\0'
+  0x200004B0:  45           DC.B       0x45                     ; 'E'
+  0x200004B1:  72           DC.B       0x72                     ; 'r'
+  0x200004B2:  73           DC.B       0x73                     ; 's'
+  0x200004B3:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.hdma_usart1_tx from PowerPro_lto.o, size=92, align=4

+
+
hdma_usart1_tx:
+  0x200004B4:  00           DC.B       0x00                     ; '\0'
+  0x200004B5:  1B           DC.B       0x1B                     ; '\x1B'
+  0x200004B6:  B7           DC.B       0xB7                     ; '\xB7'
+  0x200004B7:  00           DC.B       0x00                     ; '\0'
+  0x200004B8:  04           DC.B       0x04                     ; '\x04'
+  0x200004B9:  00           DC.B       0x00                     ; '\0'
+  0x200004BA:  00           DC.B       0x00                     ; '\0'
+  0x200004BB:  00           DC.B       0x00                     ; '\0'
+  0x200004BC:  00           DC.B       0x00                     ; '\0'
+  0x200004BD:  00           DC.B       0x00                     ; '\0'
+  0x200004BE:  00           DC.B       0x00                     ; '\0'
+  0x200004BF:  00           DC.B       0x00                     ; '\0'
+  0x200004C0:  00           DC.B       0x00                     ; '\0'
+  0x200004C1:  00           DC.B       0x00                     ; '\0'
+  0x200004C2:  00           DC.B       0x00                     ; '\0'
+  0x200004C3:  00           DC.B       0x00                     ; '\0'
+  0x200004C4:  00           DC.B       0x00                     ; '\0'
+  0x200004C5:  00           DC.B       0x00                     ; '\0'
+  0x200004C6:  00           DC.B       0x00                     ; '\0'
+  0x200004C7:  00           DC.B       0x00                     ; '\0'
+  0x200004C8:  00           DC.B       0x00                     ; '\0'
+  0x200004C9:  00           DC.B       0x00                     ; '\0'
+  0x200004CA:  00           DC.B       0x00                     ; '\0'
+  0x200004CB:  00           DC.B       0x00                     ; '\0'
+  0x200004CC:  00           DC.B       0x00                     ; '\0'
+  0x200004CD:  00           DC.B       0x00                     ; '\0'
+  0x200004CE:  00           DC.B       0x00                     ; '\0'
+  0x200004CF:  00           DC.B       0x00                     ; '\0'
+  0x200004D0:  00           DC.B       0x00                     ; '\0'
+  0x200004D1:  00           DC.B       0x00                     ; '\0'
+  0x200004D2:  00           DC.B       0x00                     ; '\0'
+  0x200004D3:  00           DC.B       0x00                     ; '\0'
+  0x200004D4:  00           DC.B       0x00                     ; '\0'
+  0x200004D5:  00           DC.B       0x00                     ; '\0'
+  0x200004D6:  00           DC.B       0x00                     ; '\0'
+  0x200004D7:  00           DC.B       0x00                     ; '\0'
+  0x200004D8:  00           DC.B       0x00                     ; '\0'
+  0x200004D9:  00           DC.B       0x00                     ; '\0'
+  0x200004DA:  00           DC.B       0x00                     ; '\0'
+  0x200004DB:  00           DC.B       0x00                     ; '\0'
+  0x200004DC:  01           DC.B       0x01                     ; '\x01'
+  0x200004DD:  00           DC.B       0x00                     ; '\0'
+  0x200004DE:  00           DC.B       0x00                     ; '\0'
+  0x200004DF:  00           DC.B       0x00                     ; '\0'
+  0x200004E0:  02           DC.B       0x02                     ; '\x02'
+  0x200004E1:  00           DC.B       0x00                     ; '\0'
+  0x200004E2:  00           DC.B       0x00                     ; '\0'
+  0x200004E3:  00           DC.B       0x00                     ; '\0'
+  0x200004E4:  03           DC.B       0x03                     ; '\x03'
+  0x200004E5:  00           DC.B       0x00                     ; '\0'
+  0x200004E6:  00           DC.B       0x00                     ; '\0'
+  0x200004E7:  00           DC.B       0x00                     ; '\0'
+  0x200004E8:  04           DC.B       0x04                     ; '\x04'
+  0x200004E9:  00           DC.B       0x00                     ; '\0'
+  0x200004EA:  00           DC.B       0x00                     ; '\0'
+  0x200004EB:  00           DC.B       0x00                     ; '\0'
+  0x200004EC:  06           DC.B       0x06                     ; '\x06'
+  0x200004ED:  00           DC.B       0x00                     ; '\0'
+  0x200004EE:  00           DC.B       0x00                     ; '\0'
+  0x200004EF:  00           DC.B       0x00                     ; '\0'
+  0x200004F0:  07           DC.B       0x07                     ; '\x07'
+  0x200004F1:  00           DC.B       0x00                     ; '\0'
+  0x200004F2:  00           DC.B       0x00                     ; '\0'
+  0x200004F3:  00           DC.B       0x00                     ; '\0'
+  0x200004F4:  08           DC.B       0x08                     ; '\b'
+  0x200004F5:  00           DC.B       0x00                     ; '\0'
+  0x200004F6:  00           DC.B       0x00                     ; '\0'
+  0x200004F7:  00           DC.B       0x00                     ; '\0'
+  0x200004F8:  09           DC.B       0x09                     ; '\t'
+  0x200004F9:  00           DC.B       0x00                     ; '\0'
+  0x200004FA:  00           DC.B       0x00                     ; '\0'
+  0x200004FB:  00           DC.B       0x00                     ; '\0'
+  0x200004FC:  00           DC.B       0x00                     ; '\0'
+  0x200004FD:  00           DC.B       0x00                     ; '\0'
+  0x200004FE:  00           DC.B       0x00                     ; '\0'
+  0x200004FF:  00           DC.B       0x00                     ; '\0'
+  0x20000500:  00           DC.B       0x00                     ; '\0'
+  0x20000501:  00           DC.B       0x00                     ; '\0'
+  0x20000502:  00           DC.B       0x00                     ; '\0'
+  0x20000503:  00           DC.B       0x00                     ; '\0'
+  0x20000504:  00           DC.B       0x00                     ; '\0'
+  0x20000505:  00           DC.B       0x00                     ; '\0'
+  0x20000506:  00           DC.B       0x00                     ; '\0'
+  0x20000507:  00           DC.B       0x00                     ; '\0'
+  0x20000508:  00           DC.B       0x00                     ; '\0'
+  0x20000509:  00           DC.B       0x00                     ; '\0'
+  0x2000050A:  00           DC.B       0x00                     ; '\0'
+  0x2000050B:  00           DC.B       0x00                     ; '\0'
+  0x2000050C:  01           DC.B       0x01                     ; '\x01'
+  0x2000050D:  00           DC.B       0x00                     ; '\0'
+  0x2000050E:  00           DC.B       0x00                     ; '\0'
+  0x2000050F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.hdma_usart1_rx from PowerPro_lto.o, size=92, align=4

+
+
hdma_usart1_rx:
+  0x20000510:  00           DC.B       0x00                     ; '\0'
+  0x20000511:  1B           DC.B       0x1B                     ; '\x1B'
+  0x20000512:  B7           DC.B       0xB7                     ; '\xB7'
+  0x20000513:  00           DC.B       0x00                     ; '\0'
+  0x20000514:  04           DC.B       0x04                     ; '\x04'
+  0x20000515:  00           DC.B       0x00                     ; '\0'
+  0x20000516:  00           DC.B       0x00                     ; '\0'
+  0x20000517:  00           DC.B       0x00                     ; '\0'
+  0x20000518:  00           DC.B       0x00                     ; '\0'
+  0x20000519:  00           DC.B       0x00                     ; '\0'
+  0x2000051A:  00           DC.B       0x00                     ; '\0'
+  0x2000051B:  00           DC.B       0x00                     ; '\0'
+  0x2000051C:  00           DC.B       0x00                     ; '\0'
+  0x2000051D:  00           DC.B       0x00                     ; '\0'
+  0x2000051E:  00           DC.B       0x00                     ; '\0'
+  0x2000051F:  00           DC.B       0x00                     ; '\0'
+  0x20000520:  00           DC.B       0x00                     ; '\0'
+  0x20000521:  00           DC.B       0x00                     ; '\0'
+  0x20000522:  00           DC.B       0x00                     ; '\0'
+  0x20000523:  00           DC.B       0x00                     ; '\0'
+  0x20000524:  00           DC.B       0x00                     ; '\0'
+  0x20000525:  00           DC.B       0x00                     ; '\0'
+  0x20000526:  00           DC.B       0x00                     ; '\0'
+  0x20000527:  00           DC.B       0x00                     ; '\0'
+  0x20000528:  00           DC.B       0x00                     ; '\0'
+  0x20000529:  00           DC.B       0x00                     ; '\0'
+  0x2000052A:  00           DC.B       0x00                     ; '\0'
+  0x2000052B:  00           DC.B       0x00                     ; '\0'
+  0x2000052C:  00           DC.B       0x00                     ; '\0'
+  0x2000052D:  00           DC.B       0x00                     ; '\0'
+  0x2000052E:  00           DC.B       0x00                     ; '\0'
+  0x2000052F:  00           DC.B       0x00                     ; '\0'
+  0x20000530:  00           DC.B       0x00                     ; '\0'
+  0x20000531:  00           DC.B       0x00                     ; '\0'
+  0x20000532:  00           DC.B       0x00                     ; '\0'
+  0x20000533:  00           DC.B       0x00                     ; '\0'
+  0x20000534:  00           DC.B       0x00                     ; '\0'
+  0x20000535:  00           DC.B       0x00                     ; '\0'
+  0x20000536:  00           DC.B       0x00                     ; '\0'
+  0x20000537:  00           DC.B       0x00                     ; '\0'
+  0x20000538:  01           DC.B       0x01                     ; '\x01'
+  0x20000539:  00           DC.B       0x00                     ; '\0'
+  0x2000053A:  00           DC.B       0x00                     ; '\0'
+  0x2000053B:  00           DC.B       0x00                     ; '\0'
+  0x2000053C:  02           DC.B       0x02                     ; '\x02'
+  0x2000053D:  00           DC.B       0x00                     ; '\0'
+  0x2000053E:  00           DC.B       0x00                     ; '\0'
+  0x2000053F:  00           DC.B       0x00                     ; '\0'
+  0x20000540:  03           DC.B       0x03                     ; '\x03'
+  0x20000541:  00           DC.B       0x00                     ; '\0'
+  0x20000542:  00           DC.B       0x00                     ; '\0'
+  0x20000543:  00           DC.B       0x00                     ; '\0'
+  0x20000544:  04           DC.B       0x04                     ; '\x04'
+  0x20000545:  00           DC.B       0x00                     ; '\0'
+  0x20000546:  00           DC.B       0x00                     ; '\0'
+  0x20000547:  00           DC.B       0x00                     ; '\0'
+  0x20000548:  06           DC.B       0x06                     ; '\x06'
+  0x20000549:  00           DC.B       0x00                     ; '\0'
+  0x2000054A:  00           DC.B       0x00                     ; '\0'
+  0x2000054B:  00           DC.B       0x00                     ; '\0'
+  0x2000054C:  07           DC.B       0x07                     ; '\x07'
+  0x2000054D:  00           DC.B       0x00                     ; '\0'
+  0x2000054E:  00           DC.B       0x00                     ; '\0'
+  0x2000054F:  00           DC.B       0x00                     ; '\0'
+  0x20000550:  08           DC.B       0x08                     ; '\b'
+  0x20000551:  00           DC.B       0x00                     ; '\0'
+  0x20000552:  00           DC.B       0x00                     ; '\0'
+  0x20000553:  00           DC.B       0x00                     ; '\0'
+  0x20000554:  09           DC.B       0x09                     ; '\t'
+  0x20000555:  00           DC.B       0x00                     ; '\0'
+  0x20000556:  00           DC.B       0x00                     ; '\0'
+  0x20000557:  00           DC.B       0x00                     ; '\0'
+  0x20000558:  00           DC.B       0x00                     ; '\0'
+  0x20000559:  00           DC.B       0x00                     ; '\0'
+  0x2000055A:  00           DC.B       0x00                     ; '\0'
+  0x2000055B:  00           DC.B       0x00                     ; '\0'
+  0x2000055C:  00           DC.B       0x00                     ; '\0'
+  0x2000055D:  00           DC.B       0x00                     ; '\0'
+  0x2000055E:  00           DC.B       0x00                     ; '\0'
+  0x2000055F:  00           DC.B       0x00                     ; '\0'
+  0x20000560:  00           DC.B       0x00                     ; '\0'
+  0x20000561:  00           DC.B       0x00                     ; '\0'
+  0x20000562:  00           DC.B       0x00                     ; '\0'
+  0x20000563:  00           DC.B       0x00                     ; '\0'
+  0x20000564:  00           DC.B       0x00                     ; '\0'
+  0x20000565:  00           DC.B       0x00                     ; '\0'
+  0x20000566:  00           DC.B       0x00                     ; '\0'
+  0x20000567:  00           DC.B       0x00                     ; '\0'
+  0x20000568:  01           DC.B       0x01                     ; '\x01'
+  0x20000569:  00           DC.B       0x00                     ; '\0'
+  0x2000056A:  00           DC.B       0x00                     ; '\0'
+  0x2000056B:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.hdma_adc1 from PowerPro_lto.o, size=92, align=4

+
+
hdma_adc1:
+  0x2000056C:  00           DC.B       0x00                     ; '\0'
+  0x2000056D:  1B           DC.B       0x1B                     ; '\x1B'
+  0x2000056E:  B7           DC.B       0xB7                     ; '\xB7'
+  0x2000056F:  00           DC.B       0x00                     ; '\0'
+  0x20000570:  04           DC.B       0x04                     ; '\x04'
+  0x20000571:  00           DC.B       0x00                     ; '\0'
+  0x20000572:  00           DC.B       0x00                     ; '\0'
+  0x20000573:  00           DC.B       0x00                     ; '\0'
+  0x20000574:  00           DC.B       0x00                     ; '\0'
+  0x20000575:  00           DC.B       0x00                     ; '\0'
+  0x20000576:  00           DC.B       0x00                     ; '\0'
+  0x20000577:  00           DC.B       0x00                     ; '\0'
+  0x20000578:  00           DC.B       0x00                     ; '\0'
+  0x20000579:  00           DC.B       0x00                     ; '\0'
+  0x2000057A:  00           DC.B       0x00                     ; '\0'
+  0x2000057B:  00           DC.B       0x00                     ; '\0'
+  0x2000057C:  00           DC.B       0x00                     ; '\0'
+  0x2000057D:  00           DC.B       0x00                     ; '\0'
+  0x2000057E:  00           DC.B       0x00                     ; '\0'
+  0x2000057F:  00           DC.B       0x00                     ; '\0'
+  0x20000580:  00           DC.B       0x00                     ; '\0'
+  0x20000581:  00           DC.B       0x00                     ; '\0'
+  0x20000582:  00           DC.B       0x00                     ; '\0'
+  0x20000583:  00           DC.B       0x00                     ; '\0'
+  0x20000584:  00           DC.B       0x00                     ; '\0'
+  0x20000585:  00           DC.B       0x00                     ; '\0'
+  0x20000586:  00           DC.B       0x00                     ; '\0'
+  0x20000587:  00           DC.B       0x00                     ; '\0'
+  0x20000588:  00           DC.B       0x00                     ; '\0'
+  0x20000589:  00           DC.B       0x00                     ; '\0'
+  0x2000058A:  00           DC.B       0x00                     ; '\0'
+  0x2000058B:  00           DC.B       0x00                     ; '\0'
+  0x2000058C:  00           DC.B       0x00                     ; '\0'
+  0x2000058D:  00           DC.B       0x00                     ; '\0'
+  0x2000058E:  00           DC.B       0x00                     ; '\0'
+  0x2000058F:  00           DC.B       0x00                     ; '\0'
+  0x20000590:  00           DC.B       0x00                     ; '\0'
+  0x20000591:  00           DC.B       0x00                     ; '\0'
+  0x20000592:  00           DC.B       0x00                     ; '\0'
+  0x20000593:  00           DC.B       0x00                     ; '\0'
+  0x20000594:  01           DC.B       0x01                     ; '\x01'
+  0x20000595:  00           DC.B       0x00                     ; '\0'
+  0x20000596:  00           DC.B       0x00                     ; '\0'
+  0x20000597:  00           DC.B       0x00                     ; '\0'
+  0x20000598:  02           DC.B       0x02                     ; '\x02'
+  0x20000599:  00           DC.B       0x00                     ; '\0'
+  0x2000059A:  00           DC.B       0x00                     ; '\0'
+  0x2000059B:  00           DC.B       0x00                     ; '\0'
+  0x2000059C:  03           DC.B       0x03                     ; '\x03'
+  0x2000059D:  00           DC.B       0x00                     ; '\0'
+  0x2000059E:  00           DC.B       0x00                     ; '\0'
+  0x2000059F:  00           DC.B       0x00                     ; '\0'
+  0x200005A0:  04           DC.B       0x04                     ; '\x04'
+  0x200005A1:  00           DC.B       0x00                     ; '\0'
+  0x200005A2:  00           DC.B       0x00                     ; '\0'
+  0x200005A3:  00           DC.B       0x00                     ; '\0'
+  0x200005A4:  06           DC.B       0x06                     ; '\x06'
+  0x200005A5:  00           DC.B       0x00                     ; '\0'
+  0x200005A6:  00           DC.B       0x00                     ; '\0'
+  0x200005A7:  00           DC.B       0x00                     ; '\0'
+  0x200005A8:  07           DC.B       0x07                     ; '\x07'
+  0x200005A9:  00           DC.B       0x00                     ; '\0'
+  0x200005AA:  00           DC.B       0x00                     ; '\0'
+  0x200005AB:  00           DC.B       0x00                     ; '\0'
+  0x200005AC:  08           DC.B       0x08                     ; '\b'
+  0x200005AD:  00           DC.B       0x00                     ; '\0'
+  0x200005AE:  00           DC.B       0x00                     ; '\0'
+  0x200005AF:  00           DC.B       0x00                     ; '\0'
+  0x200005B0:  09           DC.B       0x09                     ; '\t'
+  0x200005B1:  00           DC.B       0x00                     ; '\0'
+  0x200005B2:  00           DC.B       0x00                     ; '\0'
+  0x200005B3:  00           DC.B       0x00                     ; '\0'
+  0x200005B4:  00           DC.B       0x00                     ; '\0'
+  0x200005B5:  00           DC.B       0x00                     ; '\0'
+  0x200005B6:  00           DC.B       0x00                     ; '\0'
+  0x200005B7:  00           DC.B       0x00                     ; '\0'
+  0x200005B8:  00           DC.B       0x00                     ; '\0'
+  0x200005B9:  00           DC.B       0x00                     ; '\0'
+  0x200005BA:  00           DC.B       0x00                     ; '\0'
+  0x200005BB:  00           DC.B       0x00                     ; '\0'
+  0x200005BC:  00           DC.B       0x00                     ; '\0'
+  0x200005BD:  00           DC.B       0x00                     ; '\0'
+  0x200005BE:  00           DC.B       0x00                     ; '\0'
+  0x200005BF:  00           DC.B       0x00                     ; '\0'
+  0x200005C0:  00           DC.B       0x00                     ; '\0'
+  0x200005C1:  00           DC.B       0x00                     ; '\0'
+  0x200005C2:  00           DC.B       0x00                     ; '\0'
+  0x200005C3:  00           DC.B       0x00                     ; '\0'
+  0x200005C4:  01           DC.B       0x01                     ; '\x01'
+  0x200005C5:  00           DC.B       0x00                     ; '\0'
+  0x200005C6:  00           DC.B       0x00                     ; '\0'
+  0x200005C7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.htim17 from PowerPro_lto.o, size=76, align=4

+
+
htim17:
+  0x200005C8:  00           DC.B       0x00                     ; '\0'
+  0x200005C9:  00           DC.B       0x00                     ; '\0'
+  0x200005CA:  00           DC.B       0x00                     ; '\0'
+  0x200005CB:  00           DC.B       0x00                     ; '\0'
+  0x200005CC:  73           DC.B       0x73                     ; 's'
+  0x200005CD:  65           DC.B       0x65                     ; 'e'
+  0x200005CE:  74           DC.B       0x74                     ; 't'
+  0x200005CF:  7A           DC.B       0x7A                     ; 'z'
+  0x200005D0:  65           DC.B       0x65                     ; 'e'
+  0x200005D1:  20           DC.B       0x20                     ; ' '
+  0x200005D2:  6F           DC.B       0x6F                     ; 'o'
+  0x200005D3:  70           DC.B       0x70                     ; 'p'
+  0x200005D4:  74           DC.B       0x74                     ; 't'
+  0x200005D5:  69           DC.B       0x69                     ; 'i'
+  0x200005D6:  6F           DC.B       0x6F                     ; 'o'
+  0x200005D7:  6E           DC.B       0x6E                     ; 'n'
+  0x200005D8:  20           DC.B       0x20                     ; ' '
+  0x200005D9:  62           DC.B       0x62                     ; 'b'
+  0x200005DA:  79           DC.B       0x79                     ; 'y'
+  0x200005DB:  74           DC.B       0x74                     ; 't'
+  0x200005DC:  65           DC.B       0x65                     ; 'e'
+  0x200005DD:  0D           DC.B       0x0D                     ; '\r'
+  0x200005DE:  00           DC.B       0x00                     ; '\0'
+  0x200005DF:  4B           DC.B       0x4B                     ; 'K'
+  0x200005E0:  6F           DC.B       0x6F                     ; 'o'
+  0x200005E1:  6E           DC.B       0x6E                     ; 'n'
+  0x200005E2:  66           DC.B       0x66                     ; 'f'
+  0x200005E3:  69           DC.B       0x69                     ; 'i'
+  0x200005E4:  67           DC.B       0x67                     ; 'g'
+  0x200005E5:  20           DC.B       0x20                     ; ' '
+  0x200005E6:  76           DC.B       0x76                     ; 'v'
+  0x200005E7:  6F           DC.B       0x6F                     ; 'o'
+  0x200005E8:  72           DC.B       0x72                     ; 'r'
+  0x200005E9:  68           DC.B       0x68                     ; 'h'
+  0x200005EA:  61           DC.B       0x61                     ; 'a'
+  0x200005EB:  6E           DC.B       0x6E                     ; 'n'
+  0x200005EC:  64           DC.B       0x64                     ; 'd'
+  0x200005ED:  65           DC.B       0x65                     ; 'e'
+  0x200005EE:  6E           DC.B       0x6E                     ; 'n'
+  0x200005EF:  0D           DC.B       0x0D                     ; '\r'
+  0x200005F0:  00           DC.B       0x00                     ; '\0'
+  0x200005F1:  4E           DC.B       0x4E                     ; 'N'
+  0x200005F2:  65           DC.B       0x65                     ; 'e'
+  0x200005F3:  75           DC.B       0x75                     ; 'u'
+  0x200005F4:  65           DC.B       0x65                     ; 'e'
+  0x200005F5:  20           DC.B       0x20                     ; ' '
+  0x200005F6:  56           DC.B       0x56                     ; 'V'
+  0x200005F7:  65           DC.B       0x65                     ; 'e'
+  0x200005F8:  72           DC.B       0x72                     ; 'r'
+  0x200005F9:  73           DC.B       0x73                     ; 's'
+  0x200005FA:  69           DC.B       0x69                     ; 'i'
+  0x200005FB:  6F           DC.B       0x6F                     ; 'o'
+  0x200005FC:  6E           DC.B       0x6E                     ; 'n'
+  0x200005FD:  20           DC.B       0x20                     ; ' '
+  0x200005FE:  50           DC.B       0x50                     ; 'P'
+  0x200005FF:  61           DC.B       0x61                     ; 'a'
+  0x20000600:  72           DC.B       0x72                     ; 'r'
+  0x20000601:  61           DC.B       0x61                     ; 'a'
+  0x20000602:  6D           DC.B       0x6D                     ; 'm'
+  0x20000603:  65           DC.B       0x65                     ; 'e'
+  0x20000604:  74           DC.B       0x74                     ; 't'
+  0x20000605:  65           DC.B       0x65                     ; 'e'
+  0x20000606:  72           DC.B       0x72                     ; 'r'
+  0x20000607:  20           DC.B       0x20                     ; ' '
+  0x20000608:  65           DC.B       0x65                     ; 'e'
+  0x20000609:  72           DC.B       0x72                     ; 'r'
+  0x2000060A:  6B           DC.B       0x6B                     ; 'k'
+  0x2000060B:  61           DC.B       0x61                     ; 'a'
+  0x2000060C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000060D:  6E           DC.B       0x6E                     ; 'n'
+  0x2000060E:  74           DC.B       0x74                     ; 't'
+  0x2000060F:  2C           DC.B       0x2C                     ; ','
+  0x20000610:  20           DC.B       0x20                     ; ' '
+  0x20000611:  73           DC.B       0x73                     ; 's'
+  0x20000612:  63           DC.B       0x63                     ; 'c'
+  0x20000613:  68           DC.B       0x68                     ; 'h'
+
+

Section .bss.htim16 from PowerPro_lto.o, size=76, align=4

+
+
htim16:
+  0x20000614:  73           DC.B       0x73                     ; 's'
+  0x20000615:  65           DC.B       0x65                     ; 'e'
+  0x20000616:  74           DC.B       0x74                     ; 't'
+  0x20000617:  7A           DC.B       0x7A                     ; 'z'
+  0x20000618:  65           DC.B       0x65                     ; 'e'
+  0x20000619:  20           DC.B       0x20                     ; ' '
+  0x2000061A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000061B:  70           DC.B       0x70                     ; 'p'
+  0x2000061C:  74           DC.B       0x74                     ; 't'
+  0x2000061D:  69           DC.B       0x69                     ; 'i'
+  0x2000061E:  6F           DC.B       0x6F                     ; 'o'
+  0x2000061F:  6E           DC.B       0x6E                     ; 'n'
+  0x20000620:  20           DC.B       0x20                     ; ' '
+  0x20000621:  62           DC.B       0x62                     ; 'b'
+  0x20000622:  79           DC.B       0x79                     ; 'y'
+  0x20000623:  74           DC.B       0x74                     ; 't'
+  0x20000624:  65           DC.B       0x65                     ; 'e'
+  0x20000625:  0D           DC.B       0x0D                     ; '\r'
+  0x20000626:  00           DC.B       0x00                     ; '\0'
+  0x20000627:  4B           DC.B       0x4B                     ; 'K'
+  0x20000628:  6F           DC.B       0x6F                     ; 'o'
+  0x20000629:  6E           DC.B       0x6E                     ; 'n'
+  0x2000062A:  66           DC.B       0x66                     ; 'f'
+  0x2000062B:  69           DC.B       0x69                     ; 'i'
+  0x2000062C:  67           DC.B       0x67                     ; 'g'
+  0x2000062D:  20           DC.B       0x20                     ; ' '
+  0x2000062E:  76           DC.B       0x76                     ; 'v'
+  0x2000062F:  6F           DC.B       0x6F                     ; 'o'
+  0x20000630:  72           DC.B       0x72                     ; 'r'
+  0x20000631:  68           DC.B       0x68                     ; 'h'
+  0x20000632:  61           DC.B       0x61                     ; 'a'
+  0x20000633:  6E           DC.B       0x6E                     ; 'n'
+  0x20000634:  64           DC.B       0x64                     ; 'd'
+  0x20000635:  65           DC.B       0x65                     ; 'e'
+  0x20000636:  6E           DC.B       0x6E                     ; 'n'
+  0x20000637:  0D           DC.B       0x0D                     ; '\r'
+  0x20000638:  00           DC.B       0x00                     ; '\0'
+  0x20000639:  4E           DC.B       0x4E                     ; 'N'
+  0x2000063A:  65           DC.B       0x65                     ; 'e'
+  0x2000063B:  75           DC.B       0x75                     ; 'u'
+  0x2000063C:  65           DC.B       0x65                     ; 'e'
+  0x2000063D:  20           DC.B       0x20                     ; ' '
+  0x2000063E:  56           DC.B       0x56                     ; 'V'
+  0x2000063F:  65           DC.B       0x65                     ; 'e'
+  0x20000640:  72           DC.B       0x72                     ; 'r'
+  0x20000641:  73           DC.B       0x73                     ; 's'
+  0x20000642:  69           DC.B       0x69                     ; 'i'
+  0x20000643:  6F           DC.B       0x6F                     ; 'o'
+  0x20000644:  6E           DC.B       0x6E                     ; 'n'
+  0x20000645:  20           DC.B       0x20                     ; ' '
+  0x20000646:  50           DC.B       0x50                     ; 'P'
+  0x20000647:  61           DC.B       0x61                     ; 'a'
+  0x20000648:  72           DC.B       0x72                     ; 'r'
+  0x20000649:  61           DC.B       0x61                     ; 'a'
+  0x2000064A:  6D           DC.B       0x6D                     ; 'm'
+  0x2000064B:  65           DC.B       0x65                     ; 'e'
+  0x2000064C:  74           DC.B       0x74                     ; 't'
+  0x2000064D:  65           DC.B       0x65                     ; 'e'
+  0x2000064E:  72           DC.B       0x72                     ; 'r'
+  0x2000064F:  20           DC.B       0x20                     ; ' '
+  0x20000650:  65           DC.B       0x65                     ; 'e'
+  0x20000651:  72           DC.B       0x72                     ; 'r'
+  0x20000652:  6B           DC.B       0x6B                     ; 'k'
+  0x20000653:  61           DC.B       0x61                     ; 'a'
+  0x20000654:  6E           DC.B       0x6E                     ; 'n'
+  0x20000655:  6E           DC.B       0x6E                     ; 'n'
+  0x20000656:  74           DC.B       0x74                     ; 't'
+  0x20000657:  2C           DC.B       0x2C                     ; ','
+  0x20000658:  20           DC.B       0x20                     ; ' '
+  0x20000659:  73           DC.B       0x73                     ; 's'
+  0x2000065A:  63           DC.B       0x63                     ; 'c'
+  0x2000065B:  68           DC.B       0x68                     ; 'h'
+  0x2000065C:  72           DC.B       0x72                     ; 'r'
+  0x2000065D:  65           DC.B       0x65                     ; 'e'
+  0x2000065E:  69           DC.B       0x69                     ; 'i'
+  0x2000065F:  62           DC.B       0x62                     ; 'b'
+
+

Section .bss.adcData from PowerPro_lto.o, size=20, align=4

+
+
adcData:
+  0x20000660:  73           DC.B       0x73                     ; 's'
+  0x20000661:  65           DC.B       0x65                     ; 'e'
+  0x20000662:  74           DC.B       0x74                     ; 't'
+  0x20000663:  7A           DC.B       0x7A                     ; 'z'
+  0x20000664:  65           DC.B       0x65                     ; 'e'
+  0x20000665:  20           DC.B       0x20                     ; ' '
+  0x20000666:  6F           DC.B       0x6F                     ; 'o'
+  0x20000667:  70           DC.B       0x70                     ; 'p'
+  0x20000668:  74           DC.B       0x74                     ; 't'
+  0x20000669:  69           DC.B       0x69                     ; 'i'
+  0x2000066A:  6F           DC.B       0x6F                     ; 'o'
+  0x2000066B:  6E           DC.B       0x6E                     ; 'n'
+  0x2000066C:  20           DC.B       0x20                     ; ' '
+  0x2000066D:  62           DC.B       0x62                     ; 'b'
+  0x2000066E:  79           DC.B       0x79                     ; 'y'
+  0x2000066F:  74           DC.B       0x74                     ; 't'
+  0x20000670:  65           DC.B       0x65                     ; 'e'
+  0x20000671:  0D           DC.B       0x0D                     ; '\r'
+  0x20000672:  00           DC.B       0x00                     ; '\0'
+  0x20000673:  4B           DC.B       0x4B                     ; 'K'
+
+

Section .bss.flash_device_parameter_default from PowerPro_lto.o, size=16, align=4

+
+
flash_device_parameter_default:
+  0x20000674:  00           DC.B       0x00                     ; '\0'
+  0x20000675:  00           DC.B       0x00                     ; '\0'
+  0x20000676:  00           DC.B       0x00                     ; '\0'
+  0x20000677:  00           DC.B       0x00                     ; '\0'
+  0x20000678:  73           DC.B       0x73                     ; 's'
+  0x20000679:  65           DC.B       0x65                     ; 'e'
+  0x2000067A:  74           DC.B       0x74                     ; 't'
+  0x2000067B:  7A           DC.B       0x7A                     ; 'z'
+  0x2000067C:  65           DC.B       0x65                     ; 'e'
+  0x2000067D:  20           DC.B       0x20                     ; ' '
+  0x2000067E:  6F           DC.B       0x6F                     ; 'o'
+  0x2000067F:  70           DC.B       0x70                     ; 'p'
+  0x20000680:  74           DC.B       0x74                     ; 't'
+  0x20000681:  69           DC.B       0x69                     ; 'i'
+  0x20000682:  6F           DC.B       0x6F                     ; 'o'
+  0x20000683:  6E           DC.B       0x6E                     ; 'n'
+
+

Section .bss.voltageUout from PowerPro_lto.o, size=4, align=4

+
+
voltageUout:
+  0x20000684:  76           DC.B       0x76                     ; 'v'
+  0x20000685:  6F           DC.B       0x6F                     ; 'o'
+  0x20000686:  6C           DC.B       0x6C                     ; 'l'
+  0x20000687:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.voltageUin from PowerPro_lto.o, size=4, align=4

+
+
voltageUin:
+  0x20000688:  76           DC.B       0x76                     ; 'v'
+  0x20000689:  6F           DC.B       0x6F                     ; 'o'
+  0x2000068A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000068B:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.uwTick from PowerPro_lto.o, size=4, align=4

+
+
uwTick:
+  0x2000068C:  00           DC.B       0x00                     ; '\0'
+  0x2000068D:  1B           DC.B       0x1B                     ; '\x1B'
+  0x2000068E:  B7           DC.B       0xB7                     ; '\xB7'
+  0x2000068F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.temp from PowerPro_lto.o, size=4, align=4

+
+
temp:
+  0x20000690:  00           DC.B       0x00                     ; '\0'
+  0x20000691:  00           DC.B       0x00                     ; '\0'
+  0x20000692:  00           DC.B       0x00                     ; '\0'
+  0x20000693:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.relais_temperature from PowerPro_lto.o, size=4, align=4

+
+
relais_temperature:
+  0x20000694:  76           DC.B       0x76                     ; 'v'
+  0x20000695:  6F           DC.B       0x6F                     ; 'o'
+  0x20000696:  6C           DC.B       0x6C                     ; 'l'
+  0x20000697:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterSET from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterSET:
+  0x20000698:  76           DC.B       0x76                     ; 'v'
+  0x20000699:  6F           DC.B       0x6F                     ; 'o'
+  0x2000069A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000069B:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterRT from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterRT:
+  0x2000069C:  00           DC.B       0x00                     ; '\0'
+  0x2000069D:  00           DC.B       0x00                     ; '\0'
+  0x2000069E:  00           DC.B       0x00                     ; '\0'
+  0x2000069F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeCounterRESET from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterRESET:
+  0x200006A0:  76           DC.B       0x76                     ; 'v'
+  0x200006A1:  6F           DC.B       0x6F                     ; 'o'
+  0x200006A2:  6C           DC.B       0x6C                     ; 'l'
+  0x200006A3:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.onTimeCounterGN from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounterGN:
+  0x200006A4:  00           DC.B       0x00                     ; '\0'
+  0x200006A5:  00           DC.B       0x00                     ; '\0'
+  0x200006A6:  00           DC.B       0x00                     ; '\0'
+  0x200006A7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
onTimeCounter:
+  0x200006A8:  00           DC.B       0x00                     ; '\0'
+  0x200006A9:  00           DC.B       0x00                     ; '\0'
+  0x200006AA:  00           DC.B       0x00                     ; '\0'
+  0x200006AB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.oldTimeMSTick from PowerPro_lto.o, size=4, align=4

+
+
oldTimeMSTick:
+  0x200006AC:  73           DC.B       0x73                     ; 's'
+  0x200006AD:  65           DC.B       0x65                     ; 'e'
+  0x200006AE:  74           DC.B       0x74                     ; 't'
+  0x200006AF:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.offTimeCounterRT from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounterRT:
+  0x200006B0:  00           DC.B       0x00                     ; '\0'
+  0x200006B1:  00           DC.B       0x00                     ; '\0'
+  0x200006B2:  00           DC.B       0x00                     ; '\0'
+  0x200006B3:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeCounterGN from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounterGN:
+  0x200006B4:  00           DC.B       0x00                     ; '\0'
+  0x200006B5:  00           DC.B       0x00                     ; '\0'
+  0x200006B6:  00           DC.B       0x00                     ; '\0'
+  0x200006B7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
offTimeCounter:
+  0x200006B8:  00           DC.B       0x00                     ; '\0'
+  0x200006B9:  00           DC.B       0x00                     ; '\0'
+  0x200006BA:  00           DC.B       0x00                     ; '\0'
+  0x200006BB:  00           DC.B       0x00                     ; '\0'
+
+ +
+
numberOfBlinks:
+  0x200006BC:  00           DC.B       0x00                     ; '\0'
+  0x200006BD:  00           DC.B       0x00                     ; '\0'
+  0x200006BE:  00           DC.B       0x00                     ; '\0'
+  0x200006BF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.msCounter from PowerPro_lto.o, size=4, align=4

+
+
msCounter:
+  0x200006C0:  73           DC.B       0x73                     ; 's'
+  0x200006C1:  65           DC.B       0x65                     ; 'e'
+  0x200006C2:  74           DC.B       0x74                     ; 't'
+  0x200006C3:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.longPressCounterButtonOn from PowerPro_lto.o, size=4, align=4

+
+
longPressCounterButtonOn:
+  0x200006C4:  42           DC.B       0x42                     ; 'B'
+  0x200006C5:  55           DC.B       0x55                     ; 'U'
+  0x200006C6:  54           DC.B       0x54                     ; 'T'
+  0x200006C7:  54           DC.B       0x54                     ; 'T'
+
+

Section .bss.longPressCounterButtonOff from PowerPro_lto.o, size=4, align=4

+
+
longPressCounterButtonOff:
+  0x200006C8:  42           DC.B       0x42                     ; 'B'
+  0x200006C9:  55           DC.B       0x55                     ; 'U'
+  0x200006CA:  54           DC.B       0x54                     ; 'T'
+  0x200006CB:  54           DC.B       0x54                     ; 'T'
+
+

Section .bss.libc.__SEGGER_RTL_stdout_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stdout_file:
+  0x200006CC:  00           DC.B       0x00                     ; '\0'
+  0x200006CD:  00           DC.B       0x00                     ; '\0'
+  0x200006CE:  00           DC.B       0x00                     ; '\0'
+  0x200006CF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_stdin_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stdin_file:
+  0x200006D0:  00           DC.B       0x00                     ; '\0'
+  0x200006D1:  00           DC.B       0x00                     ; '\0'
+  0x200006D2:  00           DC.B       0x00                     ; '\0'
+  0x200006D3:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_stderr_file from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_stderr_file:
+  0x200006D4:  00           DC.B       0x00                     ; '\0'
+  0x200006D5:  00           DC.B       0x00                     ; '\0'
+  0x200006D6:  00           DC.B       0x00                     ; '\0'
+  0x200006D7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc.__SEGGER_RTL_locale_ptr from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=4, align=4

+
+
__SEGGER_RTL_locale_ptr:
+  0x200006D8:  43           DC.B       0x43                     ; 'C'
+  0x200006D9:  00           DC.B       0x00                     ; '\0'
+  0x200006DA:  50           DC.B       0x50                     ; 'P'
+  0x200006DB:  4F           DC.B       0x4F                     ; 'O'
+
+

Section .bss.ic_overflows from PowerPro_lto.o, size=4, align=4

+
+
ic_overflows:
+  0x200006DC:  73           DC.B       0x73                     ; 's'
+  0x200006DD:  65           DC.B       0x65                     ; 'e'
+  0x200006DE:  74           DC.B       0x74                     ; 't'
+  0x200006DF:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.frequency from PowerPro_lto.o, size=4, align=4

+
+
frequency:
+  0x200006E0:  73           DC.B       0x73                     ; 's'
+  0x200006E1:  65           DC.B       0x65                     ; 'e'
+  0x200006E2:  74           DC.B       0x74                     ; 't'
+  0x200006E3:  7A           DC.B       0x7A                     ; 'z'
+
+

Section .bss.dropLimitCounter from PowerPro_lto.o, size=4, align=4

+
+
dropLimitCounter:
+  0x200006E4:  76           DC.B       0x76                     ; 'v'
+  0x200006E5:  6F           DC.B       0x6F                     ; 'o'
+  0x200006E6:  6C           DC.B       0x6C                     ; 'l'
+  0x200006E7:  74           DC.B       0x74                     ; 't'
+
+

Section .bss.calTemperatureSensor30Value from PowerPro_lto.o, size=4, align=4

+
+
calTemperatureSensor30Value:
+  0x200006E8:  00           DC.B       0x00                     ; '\0'
+  0x200006E9:  00           DC.B       0x00                     ; '\0'
+  0x200006EA:  00           DC.B       0x00                     ; '\0'
+  0x200006EB:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkCounter from PowerPro_lto.o, size=4, align=4

+
+
blinkCounter:
+  0x200006EC:  00           DC.B       0x00                     ; '\0'
+  0x200006ED:  00           DC.B       0x00                     ; '\0'
+  0x200006EE:  00           DC.B       0x00                     ; '\0'
+  0x200006EF:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.autoRetryMode.170 from PowerPro_lto.o, size=4, align=4

+
+
autoRetryMode.170:
+  0x200006F0:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F1:  45           DC.B       0x45                     ; 'E'
+  0x200006F2:  57           DC.B       0x57                     ; 'W'
+  0x200006F3:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.autoRetryMode from PowerPro_lto.o, size=4, align=4

+
+
autoRetryMode:
+  0x200006F4:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F5:  45           DC.B       0x45                     ; 'E'
+  0x200006F6:  57           DC.B       0x57                     ; 'W'
+  0x200006F7:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.oldtime.175 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.oldtime.175:
+  0x200006F8:  4E           DC.B       0x4E                     ; 'N'
+  0x200006F9:  45           DC.B       0x45                     ; 'E'
+  0x200006FA:  57           DC.B       0x57                     ; 'W'
+  0x200006FB:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.oldtime:
+  0x200006FC:  4E           DC.B       0x4E                     ; 'N'
+  0x200006FD:  45           DC.B       0x45                     ; 'E'
+  0x200006FE:  57           DC.B       0x57                     ; 'W'
+  0x200006FF:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter.176:
+  0x20000700:  4E           DC.B       0x4E                     ; 'N'
+  0x20000701:  45           DC.B       0x45                     ; 'E'
+  0x20000702:  57           DC.B       0x57                     ; 'W'
+  0x20000703:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_On.lvpAndOvpInputTimeCounter:
+  0x20000704:  4E           DC.B       0x4E                     ; 'N'
+  0x20000705:  45           DC.B       0x45                     ; 'E'
+  0x20000706:  57           DC.B       0x57                     ; 'W'
+  0x20000707:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.retry_counter.181 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.retry_counter.181:
+  0x20000708:  4E           DC.B       0x4E                     ; 'N'
+  0x20000709:  45           DC.B       0x45                     ; 'E'
+  0x2000070A:  57           DC.B       0x57                     ; 'W'
+  0x2000070B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.retry_counter from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.retry_counter:
+  0x2000070C:  4E           DC.B       0x4E                     ; 'N'
+  0x2000070D:  45           DC.B       0x45                     ; 'E'
+  0x2000070E:  57           DC.B       0x57                     ; 'W'
+  0x2000070F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182 from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.oldTimeMSTick.182:
+  0x20000710:  4E           DC.B       0x4E                     ; 'N'
+  0x20000711:  45           DC.B       0x45                     ; 'E'
+  0x20000712:  57           DC.B       0x57                     ; 'W'
+  0x20000713:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.SECONDARYPROTECTION_SM_Error.oldTimeMSTick from PowerPro_lto.o, size=4, align=4

+
+
SECONDARYPROTECTION_SM_Error.oldTimeMSTick:
+  0x20000714:  4E           DC.B       0x4E                     ; 'N'
+  0x20000715:  45           DC.B       0x45                     ; 'E'
+  0x20000716:  57           DC.B       0x57                     ; 'W'
+  0x20000717:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.OVP_SM_On.ovpTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
OVP_SM_On.ovpTimeCounter:
+  0x20000718:  4F           DC.B       0x4F                     ; 'O'
+  0x20000719:  56           DC.B       0x56                     ; 'V'
+  0x2000071A:  50           DC.B       0x50                     ; 'P'
+  0x2000071B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.OVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
OVP_SM_On.oldtime:
+  0x2000071C:  4F           DC.B       0x4F                     ; 'O'
+  0x2000071D:  56           DC.B       0x56                     ; 'V'
+  0x2000071E:  50           DC.B       0x50                     ; 'P'
+  0x2000071F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
LVP_SM_On.oldtime:
+  0x20000720:  4C           DC.B       0x4C                     ; 'L'
+  0x20000721:  56           DC.B       0x56                     ; 'V'
+  0x20000722:  50           DC.B       0x50                     ; 'P'
+  0x20000723:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_SM_On.lvpTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
LVP_SM_On.lvpTimeCounter:
+  0x20000724:  4C           DC.B       0x4C                     ; 'L'
+  0x20000725:  56           DC.B       0x56                     ; 'V'
+  0x20000726:  50           DC.B       0x50                     ; 'P'
+  0x20000727:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_OVP_SM_On.oldtime from PowerPro_lto.o, size=4, align=4

+
+
LVP_OVP_SM_On.oldtime:
+  0x20000728:  4C           DC.B       0x4C                     ; 'L'
+  0x20000729:  56           DC.B       0x56                     ; 'V'
+  0x2000072A:  50           DC.B       0x50                     ; 'P'
+  0x2000072B:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.LVP_OVP_SM_On.lvpAndOvpInputTimeCounter from PowerPro_lto.o, size=4, align=4

+
+
LVP_OVP_SM_On.lvpAndOvpInputTimeCounter:
+  0x2000072C:  4C           DC.B       0x4C                     ; 'L'
+  0x2000072D:  56           DC.B       0x56                     ; 'V'
+  0x2000072E:  50           DC.B       0x50                     ; 'P'
+  0x2000072F:  5F           DC.B       0x5F                     ; '_'
+
+

Section .bss.relaisState from PowerPro_lto.o, size=1, align=4

+
+
relaisState:
+  0x20000730:  76           DC.B       0x76                     ; 'v'
+
+

Section .bss.smState.171 from PowerPro_lto.o, size=1, align=1

+
+
smState.171:
+  0x20000731:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.160 from PowerPro_lto.o, size=1, align=1

+
+
smState.160:
+  0x20000732:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.145 from PowerPro_lto.o, size=1, align=1

+
+
smState.145:
+  0x20000733:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.pauseTime from PowerPro_lto.o, size=1, align=4

+
+
pauseTime:
+  0x20000734:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.smState.137 from PowerPro_lto.o, size=1, align=1

+
+
smState.137:
+  0x20000735:  4E           DC.B       0x4E                     ; 'N'
+
+

Section .bss.smState.122 from PowerPro_lto.o, size=1, align=1

+
+
smState.122:
+  0x20000736:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.smState from PowerPro_lto.o, size=1, align=1

+
+
smState:
+  0x20000737:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.pFlash.0 from PowerPro_lto.o, size=1, align=4

+
+
pFlash.0:
+  0x20000738:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.mode from PowerPro_lto.o, size=1, align=1

+
+
mode:
+  0x20000739:  6D           DC.B       0x6D                     ; 'm'
+
+

Section .bss.buttonState from PowerPro_lto.o, size=1, align=1

+
+
buttonState:
+  0x2000073A:  42           DC.B       0x42                     ; 'B'
+
+

Section .bss.onTimeRT from PowerPro_lto.o, size=1, align=4

+
+
onTimeRT:
+  0x2000073C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTimeGN from PowerPro_lto.o, size=1, align=4

+
+
onTimeGN:
+  0x20000740:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.onTime from PowerPro_lto.o, size=1, align=4

+
+
onTime:
+  0x20000744:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeRT from PowerPro_lto.o, size=1, align=4

+
+
offTimeRT:
+  0x20000748:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTimeGN from PowerPro_lto.o, size=1, align=4

+
+
offTimeGN:
+  0x2000074C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.offTime from PowerPro_lto.o, size=1, align=4

+
+
offTime:
+  0x20000750:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkModeRT from PowerPro_lto.o, size=1, align=4

+
+
blinkModeRT:
+  0x20000754:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.blinkModeGN from PowerPro_lto.o, size=1, align=4

+
+
blinkModeGN:
+  0x20000758:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.alarmMode from PowerPro_lto.o, size=1, align=4

+
+
alarmMode:
+  0x2000075C:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.OVP_SM_On.ovpInput from PowerPro_lto.o, size=1, align=4

+
+
OVP_SM_On.ovpInput:
+  0x20000760:  4F           DC.B       0x4F                     ; 'O'
+
+

Section .bss.LVP_SM_On.lvpInput from PowerPro_lto.o, size=1, align=4

+
+
LVP_SM_On.lvpInput:
+  0x20000764:  4C           DC.B       0x4C                     ; 'L'
+
+

Section .bss.LVP_OVP_SM_On.lvpOROvpInput from PowerPro_lto.o, size=1, align=4

+
+
LVP_OVP_SM_On.lvpOROvpInput:
+  0x20000768:  4C           DC.B       0x4C                     ; 'L'
+
+

Section .bss.libc._acUpBuffer from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=1024, align=1

+
+
_acUpBuffer:
+  0x20000769:  00           DC.B       0x00                     ; '\0'
+  0x2000076A:  53           DC.B       0x53                     ; 'S'
+  0x2000076B:  45           DC.B       0x45                     ; 'E'
+  0x2000076C:  47           DC.B       0x47                     ; 'G'
+  0x2000076D:  47           DC.B       0x47                     ; 'G'
+  0x2000076E:  45           DC.B       0x45                     ; 'E'
+  0x2000076F:  52           DC.B       0x52                     ; 'R'
+  0x20000770:  20           DC.B       0x20                     ; ' '
+  0x20000771:  43           DC.B       0x43                     ; 'C'
+  0x20000772:  2F           DC.B       0x2F                     ; '/'
+  0x20000773:  43           DC.B       0x43                     ; 'C'
+  0x20000774:  2B           DC.B       0x2B                     ; '+'
+  0x20000775:  2B           DC.B       0x2B                     ; '+'
+  0x20000776:  20           DC.B       0x20                     ; ' '
+  0x20000777:  63           DC.B       0x63                     ; 'c'
+  0x20000778:  6F           DC.B       0x6F                     ; 'o'
+  0x20000779:  6D           DC.B       0x6D                     ; 'm'
+  0x2000077A:  70           DC.B       0x70                     ; 'p'
+  0x2000077B:  69           DC.B       0x69                     ; 'i'
+  0x2000077C:  6C           DC.B       0x6C                     ; 'l'
+  0x2000077D:  65           DC.B       0x65                     ; 'e'
+  0x2000077E:  72           DC.B       0x72                     ; 'r'
+  0x2000077F:  20           DC.B       0x20                     ; ' '
+  0x20000780:  76           DC.B       0x76                     ; 'v'
+  0x20000781:  65           DC.B       0x65                     ; 'e'
+  0x20000782:  72           DC.B       0x72                     ; 'r'
+  0x20000783:  73           DC.B       0x73                     ; 's'
+  0x20000784:  69           DC.B       0x69                     ; 'i'
+  0x20000785:  6F           DC.B       0x6F                     ; 'o'
+  0x20000786:  6E           DC.B       0x6E                     ; 'n'
+  0x20000787:  20           DC.B       0x20                     ; ' '
+  0x20000788:  32           DC.B       0x32                     ; '2'
+  0x20000789:  30           DC.B       0x30                     ; '0'
+  0x2000078A:  2E           DC.B       0x2E                     ; '.'
+  0x2000078B:  31           DC.B       0x31                     ; '1'
+  0x2000078C:  2E           DC.B       0x2E                     ; '.'
+  0x2000078D:  32           DC.B       0x32                     ; '2'
+  0x2000078E:  20           DC.B       0x20                     ; ' '
+  0x2000078F:  28           DC.B       0x28                     ; '('
+  0x20000790:  62           DC.B       0x62                     ; 'b'
+  0x20000791:  61           DC.B       0x61                     ; 'a'
+  0x20000792:  73           DC.B       0x73                     ; 's'
+  0x20000793:  65           DC.B       0x65                     ; 'e'
+  0x20000794:  64           DC.B       0x64                     ; 'd'
+  0x20000795:  20           DC.B       0x20                     ; ' '
+  0x20000796:  6F           DC.B       0x6F                     ; 'o'
+  0x20000797:  6E           DC.B       0x6E                     ; 'n'
+  0x20000798:  20           DC.B       0x20                     ; ' '
+  0x20000799:  63           DC.B       0x63                     ; 'c'
+  0x2000079A:  6C           DC.B       0x6C                     ; 'l'
+  0x2000079B:  61           DC.B       0x61                     ; 'a'
+  0x2000079C:  6E           DC.B       0x6E                     ; 'n'
+  0x2000079D:  67           DC.B       0x67                     ; 'g'
+  0x2000079E:  20           DC.B       0x20                     ; ' '
+  0x2000079F:  32           DC.B       0x32                     ; '2'
+  0x200007A0:  30           DC.B       0x30                     ; '0'
+  0x200007A1:  2E           DC.B       0x2E                     ; '.'
+  0x200007A2:  31           DC.B       0x31                     ; '1'
+  0x200007A3:  2E           DC.B       0x2E                     ; '.'
+  0x200007A4:  38           DC.B       0x38                     ; '8'
+  0x200007A5:  29           DC.B       0x29                     ; ')'
+  0x200007A6:  00           DC.B       0x00                     ; '\0'
+  0x200007A7:  41           DC.B       0x41                     ; 'A'
+  0x200007A8:  35           DC.B       0x35                     ; '5'
+  0x200007A9:  00           DC.B       0x00                     ; '\0'
+  0x200007AA:  00           DC.B       0x00                     ; '\0'
+  0x200007AB:  00           DC.B       0x00                     ; '\0'
+  0x200007AC:  61           DC.B       0x61                     ; 'a'
+  0x200007AD:  65           DC.B       0x65                     ; 'e'
+  0x200007AE:  61           DC.B       0x61                     ; 'a'
+  0x200007AF:  62           DC.B       0x62                     ; 'b'
+  0x200007B0:  69           DC.B       0x69                     ; 'i'
+  0x200007B1:  00           DC.B       0x00                     ; '\0'
+  0x200007B2:  01           DC.B       0x01                     ; '\x01'
+  0x200007B3:  2B           DC.B       0x2B                     ; '+'
+  0x200007B4:  00           DC.B       0x00                     ; '\0'
+  0x200007B5:  00           DC.B       0x00                     ; '\0'
+  0x200007B6:  00           DC.B       0x00                     ; '\0'
+  0x200007B7:  43           DC.B       0x43                     ; 'C'
+  0x200007B8:  32           DC.B       0x32                     ; '2'
+  0x200007B9:  2E           DC.B       0x2E                     ; '.'
+  0x200007BA:  30           DC.B       0x30                     ; '0'
+  0x200007BB:  39           DC.B       0x39                     ; '9'
+  0x200007BC:  00           DC.B       0x00                     ; '\0'
+  0x200007BD:  06           DC.B       0x06                     ; '\x06'
+  0x200007BE:  0C           DC.B       0x0C                     ; '\x0C'
+  0x200007BF:  07           DC.B       0x07                     ; '\x07'
+  0x200007C0:  4D           DC.B       0x4D                     ; 'M'
+  0x200007C1:  08           DC.B       0x08                     ; '\b'
+  0x200007C2:  00           DC.B       0x00                     ; '\0'
+  0x200007C3:  09           DC.B       0x09                     ; '\t'
+  0x200007C4:  01           DC.B       0x01                     ; '\x01'
+  0x200007C5:  0E           DC.B       0x0E                     ; '\x0E'
+  0x200007C6:  00           DC.B       0x00                     ; '\0'
+  0x200007C7:  11           DC.B       0x11                     ; '\x11'
+  0x200007C8:  01           DC.B       0x01                     ; '\x01'
+  0x200007C9:  12           DC.B       0x12                     ; '\x12'
+  0x200007CA:  04           DC.B       0x04                     ; '\x04'
+  0x200007CB:  14           DC.B       0x14                     ; '\x14'
+  0x200007CC:  01           DC.B       0x01                     ; '\x01'
+  0x200007CD:  15           DC.B       0x15                     ; '\x15'
+  0x200007CE:  00           DC.B       0x00                     ; '\0'
+  0x200007CF:  17           DC.B       0x17                     ; '\x17'
+  0x200007D0:  03           DC.B       0x03                     ; '\x03'
+  0x200007D1:  18           DC.B       0x18                     ; '\x18'
+  0x200007D2:  01           DC.B       0x01                     ; '\x01'
+  0x200007D3:  19           DC.B       0x19                     ; '\x19'
+  0x200007D4:  01           DC.B       0x01                     ; '\x01'
+  0x200007D5:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200007D6:  01           DC.B       0x01                     ; '\x01'
+  0x200007D7:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200007D8:  04           DC.B       0x04                     ; '\x04'
+  0x200007D9:  22           DC.B       0x22                     ; '\"'
+  0x200007DA:  00           DC.B       0x00                     ; '\0'
+  0x200007DB:  26           DC.B       0x26                     ; '&'
+  0x200007DC:  01           DC.B       0x01                     ; '\x01'
+  0x200007DD:  00           DC.B       0x00                     ; '\0'
+  0x200007DE:  00           DC.B       0x00                     ; '\0'
+  0x200007DF:  00           DC.B       0x00                     ; '\0'
+  0x200007E0:  00           DC.B       0x00                     ; '\0'
+  0x200007E1:  00           DC.B       0x00                     ; '\0'
+  0x200007E2:  00           DC.B       0x00                     ; '\0'
+  0x200007E3:  00           DC.B       0x00                     ; '\0'
+  0x200007E4:  00           DC.B       0x00                     ; '\0'
+  0x200007E5:  00           DC.B       0x00                     ; '\0'
+  0x200007E6:  00           DC.B       0x00                     ; '\0'
+  0x200007E7:  00           DC.B       0x00                     ; '\0'
+  0x200007E8:  00           DC.B       0x00                     ; '\0'
+  0x200007E9:  00           DC.B       0x00                     ; '\0'
+  0x200007EA:  00           DC.B       0x00                     ; '\0'
+  0x200007EB:  00           DC.B       0x00                     ; '\0'
+  0x200007EC:  00           DC.B       0x00                     ; '\0'
+  0x200007ED:  00           DC.B       0x00                     ; '\0'
+  0x200007EE:  00           DC.B       0x00                     ; '\0'
+  0x200007EF:  40           DC.B       0x40                     ; '@'
+  0x200007F0:  06           DC.B       0x06                     ; '\x06'
+  0x200007F1:  00           DC.B       0x00                     ; '\0'
+  0x200007F2:  00           DC.B       0x00                     ; '\0'
+  0x200007F3:  00           DC.B       0x00                     ; '\0'
+  0x200007F4:  00           DC.B       0x00                     ; '\0'
+  0x200007F5:  00           DC.B       0x00                     ; '\0'
+  0x200007F6:  00           DC.B       0x00                     ; '\0'
+  0x200007F7:  00           DC.B       0x00                     ; '\0'
+  0x200007F8:  00           DC.B       0x00                     ; '\0'
+  0x200007F9:  00           DC.B       0x00                     ; '\0'
+  0x200007FA:  00           DC.B       0x00                     ; '\0'
+  0x200007FB:  04           DC.B       0x04                     ; '\x04'
+  0x200007FC:  00           DC.B       0x00                     ; '\0'
+  0x200007FD:  F1           DC.B       0xF1                     ; '\xF1'
+  0x200007FE:  FF           DC.B       0xFF                     ; '\xFF'
+  0x200007FF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000800:  00           DC.B       0x00                     ; '\0'
+  0x20000801:  00           DC.B       0x00                     ; '\0'
+  0x20000802:  00           DC.B       0x00                     ; '\0'
+  0x20000803:  00           DC.B       0x00                     ; '\0'
+  0x20000804:  00           DC.B       0x00                     ; '\0'
+  0x20000805:  00           DC.B       0x00                     ; '\0'
+  0x20000806:  00           DC.B       0x00                     ; '\0'
+  0x20000807:  00           DC.B       0x00                     ; '\0'
+  0x20000808:  00           DC.B       0x00                     ; '\0'
+  0x20000809:  00           DC.B       0x00                     ; '\0'
+  0x2000080A:  00           DC.B       0x00                     ; '\0'
+  0x2000080B:  00           DC.B       0x00                     ; '\0'
+  0x2000080C:  00           DC.B       0x00                     ; '\0'
+  0x2000080D:  03           DC.B       0x03                     ; '\x03'
+  0x2000080E:  00           DC.B       0x00                     ; '\0'
+  0x2000080F:  AA           DC.B       0xAA                     ; '\xAA'
+  0x20000810:  00           DC.B       0x00                     ; '\0'
+  0x20000811:  00           DC.B       0x00                     ; '\0'
+  0x20000812:  00           DC.B       0x00                     ; '\0'
+  0x20000813:  01           DC.B       0x01                     ; '\x01'
+  0x20000814:  00           DC.B       0x00                     ; '\0'
+  0x20000815:  00           DC.B       0x00                     ; '\0'
+  0x20000816:  00           DC.B       0x00                     ; '\0'
+  0x20000817:  54           DC.B       0x54                     ; 'T'
+  0x20000818:  00           DC.B       0x00                     ; '\0'
+  0x20000819:  00           DC.B       0x00                     ; '\0'
+  0x2000081A:  00           DC.B       0x00                     ; '\0'
+  0x2000081B:  02           DC.B       0x02                     ; '\x02'
+  0x2000081C:  00           DC.B       0x00                     ; '\0'
+  0x2000081D:  05           DC.B       0x05                     ; '\x05'
+  0x2000081E:  00           DC.B       0x00                     ; '\0'
+  0x2000081F:  32           DC.B       0x32                     ; '2'
+  0x20000820:  06           DC.B       0x06                     ; '\x06'
+  0x20000821:  00           DC.B       0x00                     ; '\0'
+  0x20000822:  00           DC.B       0x00                     ; '\0'
+  0x20000823:  84           DC.B       0x84                     ; '\x84'
+  0x20000824:  00           DC.B       0x00                     ; '\0'
+  0x20000825:  00           DC.B       0x00                     ; '\0'
+  0x20000826:  00           DC.B       0x00                     ; '\0'
+  0x20000827:  00           DC.B       0x00                     ; '\0'
+  0x20000828:  00           DC.B       0x00                     ; '\0'
+  0x20000829:  00           DC.B       0x00                     ; '\0'
+  0x2000082A:  00           DC.B       0x00                     ; '\0'
+  0x2000082B:  00           DC.B       0x00                     ; '\0'
+  0x2000082C:  00           DC.B       0x00                     ; '\0'
+  0x2000082D:  03           DC.B       0x03                     ; '\x03'
+  0x2000082E:  00           DC.B       0x00                     ; '\0'
+  0x2000082F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000830:  00           DC.B       0x00                     ; '\0'
+  0x20000831:  00           DC.B       0x00                     ; '\0'
+  0x20000832:  00           DC.B       0x00                     ; '\0'
+  0x20000833:  00           DC.B       0x00                     ; '\0'
+  0x20000834:  00           DC.B       0x00                     ; '\0'
+  0x20000835:  00           DC.B       0x00                     ; '\0'
+  0x20000836:  00           DC.B       0x00                     ; '\0'
+  0x20000837:  00           DC.B       0x00                     ; '\0'
+  0x20000838:  00           DC.B       0x00                     ; '\0'
+  0x20000839:  00           DC.B       0x00                     ; '\0'
+  0x2000083A:  00           DC.B       0x00                     ; '\0'
+  0x2000083B:  00           DC.B       0x00                     ; '\0'
+  0x2000083C:  00           DC.B       0x00                     ; '\0'
+  0x2000083D:  05           DC.B       0x05                     ; '\x05'
+  0x2000083E:  00           DC.B       0x00                     ; '\0'
+  0x2000083F:  32           DC.B       0x32                     ; '2'
+  0x20000840:  06           DC.B       0x06                     ; '\x06'
+  0x20000841:  00           DC.B       0x00                     ; '\0'
+  0x20000842:  00           DC.B       0x00                     ; '\0'
+  0x20000843:  40           DC.B       0x40                     ; '@'
+  0x20000844:  00           DC.B       0x00                     ; '\0'
+  0x20000845:  00           DC.B       0x00                     ; '\0'
+  0x20000846:  00           DC.B       0x00                     ; '\0'
+  0x20000847:  00           DC.B       0x00                     ; '\0'
+  0x20000848:  00           DC.B       0x00                     ; '\0'
+  0x20000849:  00           DC.B       0x00                     ; '\0'
+  0x2000084A:  00           DC.B       0x00                     ; '\0'
+  0x2000084B:  00           DC.B       0x00                     ; '\0'
+  0x2000084C:  00           DC.B       0x00                     ; '\0'
+  0x2000084D:  05           DC.B       0x05                     ; '\x05'
+  0x2000084E:  00           DC.B       0x00                     ; '\0'
+  0x2000084F:  EE           DC.B       0xEE                     ; '\xEE'
+  0x20000850:  01           DC.B       0x01                     ; '\x01'
+  0x20000851:  00           DC.B       0x00                     ; '\0'
+  0x20000852:  00           DC.B       0x00                     ; '\0'
+  0x20000853:  00           DC.B       0x00                     ; '\0'
+  0x20000854:  00           DC.B       0x00                     ; '\0'
+  0x20000855:  00           DC.B       0x00                     ; '\0'
+  0x20000856:  00           DC.B       0x00                     ; '\0'
+  0x20000857:  00           DC.B       0x00                     ; '\0'
+  0x20000858:  04           DC.B       0x04                     ; '\x04'
+  0x20000859:  00           DC.B       0x00                     ; '\0'
+  0x2000085A:  00           DC.B       0x00                     ; '\0'
+  0x2000085B:  01           DC.B       0x01                     ; '\x01'
+  0x2000085C:  00           DC.B       0x00                     ; '\0'
+  0x2000085D:  51           DC.B       0x51                     ; 'Q'
+  0x2000085E:  00           DC.B       0x00                     ; '\0'
+  0x2000085F:  DC           DC.B       0xDC                     ; '\xDC'
+  0x20000860:  02           DC.B       0x02                     ; '\x02'
+  0x20000861:  00           DC.B       0x00                     ; '\0'
+  0x20000862:  00           DC.B       0x00                     ; '\0'
+  0x20000863:  00           DC.B       0x00                     ; '\0'
+  0x20000864:  00           DC.B       0x00                     ; '\0'
+  0x20000865:  00           DC.B       0x00                     ; '\0'
+  0x20000866:  00           DC.B       0x00                     ; '\0'
+  0x20000867:  10           DC.B       0x10                     ; '\x10'
+  0x20000868:  00           DC.B       0x00                     ; '\0'
+  0x20000869:  00           DC.B       0x00                     ; '\0'
+  0x2000086A:  00           DC.B       0x00                     ; '\0'
+  0x2000086B:  01           DC.B       0x01                     ; '\x01'
+  0x2000086C:  00           DC.B       0x00                     ; '\0'
+  0x2000086D:  52           DC.B       0x52                     ; 'R'
+  0x2000086E:  00           DC.B       0x00                     ; '\0'
+  0x2000086F:  05           DC.B       0x05                     ; '\x05'
+  0x20000870:  01           DC.B       0x01                     ; '\x01'
+  0x20000871:  00           DC.B       0x00                     ; '\0'
+  0x20000872:  00           DC.B       0x00                     ; '\0'
+  0x20000873:  00           DC.B       0x00                     ; '\0'
+  0x20000874:  00           DC.B       0x00                     ; '\0'
+  0x20000875:  00           DC.B       0x00                     ; '\0'
+  0x20000876:  00           DC.B       0x00                     ; '\0'
+  0x20000877:  11           DC.B       0x11                     ; '\x11'
+  0x20000878:  00           DC.B       0x00                     ; '\0'
+  0x20000879:  00           DC.B       0x00                     ; '\0'
+  0x2000087A:  00           DC.B       0x00                     ; '\0'
+  0x2000087B:  01           DC.B       0x01                     ; '\x01'
+  0x2000087C:  00           DC.B       0x00                     ; '\0'
+  0x2000087D:  4F           DC.B       0x4F                     ; 'O'
+  0x2000087E:  00           DC.B       0x00                     ; '\0'
+  0x2000087F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000880:  00           DC.B       0x00                     ; '\0'
+  0x20000881:  00           DC.B       0x00                     ; '\0'
+  0x20000882:  00           DC.B       0x00                     ; '\0'
+  0x20000883:  00           DC.B       0x00                     ; '\0'
+  0x20000884:  00           DC.B       0x00                     ; '\0'
+  0x20000885:  00           DC.B       0x00                     ; '\0'
+  0x20000886:  00           DC.B       0x00                     ; '\0'
+  0x20000887:  00           DC.B       0x00                     ; '\0'
+  0x20000888:  00           DC.B       0x00                     ; '\0'
+  0x20000889:  00           DC.B       0x00                     ; '\0'
+  0x2000088A:  00           DC.B       0x00                     ; '\0'
+  0x2000088B:  00           DC.B       0x00                     ; '\0'
+  0x2000088C:  00           DC.B       0x00                     ; '\0'
+  0x2000088D:  07           DC.B       0x07                     ; '\x07'
+  0x2000088E:  00           DC.B       0x00                     ; '\0'
+  0x2000088F:  32           DC.B       0x32                     ; '2'
+  0x20000890:  06           DC.B       0x06                     ; '\x06'
+  0x20000891:  00           DC.B       0x00                     ; '\0'
+  0x20000892:  00           DC.B       0x00                     ; '\0'
+  0x20000893:  84           DC.B       0x84                     ; '\x84'
+  0x20000894:  00           DC.B       0x00                     ; '\0'
+  0x20000895:  00           DC.B       0x00                     ; '\0'
+  0x20000896:  00           DC.B       0x00                     ; '\0'
+  0x20000897:  00           DC.B       0x00                     ; '\0'
+  0x20000898:  00           DC.B       0x00                     ; '\0'
+  0x20000899:  00           DC.B       0x00                     ; '\0'
+  0x2000089A:  00           DC.B       0x00                     ; '\0'
+  0x2000089B:  00           DC.B       0x00                     ; '\0'
+  0x2000089C:  00           DC.B       0x00                     ; '\0'
+  0x2000089D:  07           DC.B       0x07                     ; '\x07'
+  0x2000089E:  00           DC.B       0x00                     ; '\0'
+  0x2000089F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008A0:  00           DC.B       0x00                     ; '\0'
+  0x200008A1:  00           DC.B       0x00                     ; '\0'
+  0x200008A2:  00           DC.B       0x00                     ; '\0'
+  0x200008A3:  00           DC.B       0x00                     ; '\0'
+  0x200008A4:  00           DC.B       0x00                     ; '\0'
+  0x200008A5:  00           DC.B       0x00                     ; '\0'
+  0x200008A6:  00           DC.B       0x00                     ; '\0'
+  0x200008A7:  00           DC.B       0x00                     ; '\0'
+  0x200008A8:  00           DC.B       0x00                     ; '\0'
+  0x200008A9:  00           DC.B       0x00                     ; '\0'
+  0x200008AA:  00           DC.B       0x00                     ; '\0'
+  0x200008AB:  00           DC.B       0x00                     ; '\0'
+  0x200008AC:  00           DC.B       0x00                     ; '\0'
+  0x200008AD:  09           DC.B       0x09                     ; '\t'
+  0x200008AE:  00           DC.B       0x00                     ; '\0'
+  0x200008AF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008B0:  00           DC.B       0x00                     ; '\0'
+  0x200008B1:  00           DC.B       0x00                     ; '\0'
+  0x200008B2:  00           DC.B       0x00                     ; '\0'
+  0x200008B3:  00           DC.B       0x00                     ; '\0'
+  0x200008B4:  00           DC.B       0x00                     ; '\0'
+  0x200008B5:  00           DC.B       0x00                     ; '\0'
+  0x200008B6:  00           DC.B       0x00                     ; '\0'
+  0x200008B7:  00           DC.B       0x00                     ; '\0'
+  0x200008B8:  00           DC.B       0x00                     ; '\0'
+  0x200008B9:  00           DC.B       0x00                     ; '\0'
+  0x200008BA:  00           DC.B       0x00                     ; '\0'
+  0x200008BB:  00           DC.B       0x00                     ; '\0'
+  0x200008BC:  00           DC.B       0x00                     ; '\0'
+  0x200008BD:  0B           DC.B       0x0B                     ; '\v'
+  0x200008BE:  00           DC.B       0x00                     ; '\0'
+  0x200008BF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008C0:  00           DC.B       0x00                     ; '\0'
+  0x200008C1:  00           DC.B       0x00                     ; '\0'
+  0x200008C2:  00           DC.B       0x00                     ; '\0'
+  0x200008C3:  00           DC.B       0x00                     ; '\0'
+  0x200008C4:  00           DC.B       0x00                     ; '\0'
+  0x200008C5:  00           DC.B       0x00                     ; '\0'
+  0x200008C6:  00           DC.B       0x00                     ; '\0'
+  0x200008C7:  00           DC.B       0x00                     ; '\0'
+  0x200008C8:  00           DC.B       0x00                     ; '\0'
+  0x200008C9:  00           DC.B       0x00                     ; '\0'
+  0x200008CA:  00           DC.B       0x00                     ; '\0'
+  0x200008CB:  00           DC.B       0x00                     ; '\0'
+  0x200008CC:  00           DC.B       0x00                     ; '\0'
+  0x200008CD:  0D           DC.B       0x0D                     ; '\r'
+  0x200008CE:  00           DC.B       0x00                     ; '\0'
+  0x200008CF:  32           DC.B       0x32                     ; '2'
+  0x200008D0:  06           DC.B       0x06                     ; '\x06'
+  0x200008D1:  00           DC.B       0x00                     ; '\0'
+  0x200008D2:  00           DC.B       0x00                     ; '\0'
+  0x200008D3:  84           DC.B       0x84                     ; '\x84'
+  0x200008D4:  00           DC.B       0x00                     ; '\0'
+  0x200008D5:  00           DC.B       0x00                     ; '\0'
+  0x200008D6:  00           DC.B       0x00                     ; '\0'
+  0x200008D7:  00           DC.B       0x00                     ; '\0'
+  0x200008D8:  00           DC.B       0x00                     ; '\0'
+  0x200008D9:  00           DC.B       0x00                     ; '\0'
+  0x200008DA:  00           DC.B       0x00                     ; '\0'
+  0x200008DB:  00           DC.B       0x00                     ; '\0'
+  0x200008DC:  00           DC.B       0x00                     ; '\0'
+  0x200008DD:  0D           DC.B       0x0D                     ; '\r'
+  0x200008DE:  00           DC.B       0x00                     ; '\0'
+  0x200008DF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200008E0:  00           DC.B       0x00                     ; '\0'
+  0x200008E1:  00           DC.B       0x00                     ; '\0'
+  0x200008E2:  00           DC.B       0x00                     ; '\0'
+  0x200008E3:  00           DC.B       0x00                     ; '\0'
+  0x200008E4:  00           DC.B       0x00                     ; '\0'
+  0x200008E5:  00           DC.B       0x00                     ; '\0'
+  0x200008E6:  00           DC.B       0x00                     ; '\0'
+  0x200008E7:  00           DC.B       0x00                     ; '\0'
+  0x200008E8:  00           DC.B       0x00                     ; '\0'
+  0x200008E9:  00           DC.B       0x00                     ; '\0'
+  0x200008EA:  00           DC.B       0x00                     ; '\0'
+  0x200008EB:  00           DC.B       0x00                     ; '\0'
+  0x200008EC:  00           DC.B       0x00                     ; '\0'
+  0x200008ED:  0F           DC.B       0x0F                     ; '\x0F'
+  0x200008EE:  00           DC.B       0x00                     ; '\0'
+  0x200008EF:  32           DC.B       0x32                     ; '2'
+  0x200008F0:  06           DC.B       0x06                     ; '\x06'
+  0x200008F1:  00           DC.B       0x00                     ; '\0'
+  0x200008F2:  00           DC.B       0x00                     ; '\0'
+  0x200008F3:  68           DC.B       0x68                     ; 'h'
+  0x200008F4:  00           DC.B       0x00                     ; '\0'
+  0x200008F5:  00           DC.B       0x00                     ; '\0'
+  0x200008F6:  00           DC.B       0x00                     ; '\0'
+  0x200008F7:  00           DC.B       0x00                     ; '\0'
+  0x200008F8:  00           DC.B       0x00                     ; '\0'
+  0x200008F9:  00           DC.B       0x00                     ; '\0'
+  0x200008FA:  00           DC.B       0x00                     ; '\0'
+  0x200008FB:  00           DC.B       0x00                     ; '\0'
+  0x200008FC:  00           DC.B       0x00                     ; '\0'
+  0x200008FD:  0F           DC.B       0x0F                     ; '\x0F'
+  0x200008FE:  00           DC.B       0x00                     ; '\0'
+  0x200008FF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000900:  00           DC.B       0x00                     ; '\0'
+  0x20000901:  00           DC.B       0x00                     ; '\0'
+  0x20000902:  00           DC.B       0x00                     ; '\0'
+  0x20000903:  00           DC.B       0x00                     ; '\0'
+  0x20000904:  00           DC.B       0x00                     ; '\0'
+  0x20000905:  00           DC.B       0x00                     ; '\0'
+  0x20000906:  00           DC.B       0x00                     ; '\0'
+  0x20000907:  00           DC.B       0x00                     ; '\0'
+  0x20000908:  00           DC.B       0x00                     ; '\0'
+  0x20000909:  00           DC.B       0x00                     ; '\0'
+  0x2000090A:  00           DC.B       0x00                     ; '\0'
+  0x2000090B:  00           DC.B       0x00                     ; '\0'
+  0x2000090C:  00           DC.B       0x00                     ; '\0'
+  0x2000090D:  11           DC.B       0x11                     ; '\x11'
+  0x2000090E:  00           DC.B       0x00                     ; '\0'
+  0x2000090F:  E5           DC.B       0xE5                     ; '\xE5'
+  0x20000910:  05           DC.B       0x05                     ; '\x05'
+  0x20000911:  00           DC.B       0x00                     ; '\0'
+  0x20000912:  00           DC.B       0x00                     ; '\0'
+  0x20000913:  01           DC.B       0x01                     ; '\x01'
+  0x20000914:  00           DC.B       0x00                     ; '\0'
+  0x20000915:  00           DC.B       0x00                     ; '\0'
+  0x20000916:  00           DC.B       0x00                     ; '\0'
+  0x20000917:  16           DC.B       0x16                     ; '\x16'
+  0x20000918:  00           DC.B       0x00                     ; '\0'
+  0x20000919:  00           DC.B       0x00                     ; '\0'
+  0x2000091A:  00           DC.B       0x00                     ; '\0'
+  0x2000091B:  02           DC.B       0x02                     ; '\x02'
+  0x2000091C:  00           DC.B       0x00                     ; '\0'
+  0x2000091D:  13           DC.B       0x13                     ; '\x13'
+  0x2000091E:  00           DC.B       0x00                     ; '\0'
+  0x2000091F:  08           DC.B       0x08                     ; '\b'
+  0x20000920:  05           DC.B       0x05                     ; '\x05'
+  0x20000921:  00           DC.B       0x00                     ; '\0'
+  0x20000922:  00           DC.B       0x00                     ; '\0'
+  0x20000923:  01           DC.B       0x01                     ; '\x01'
+  0x20000924:  00           DC.B       0x00                     ; '\0'
+  0x20000925:  00           DC.B       0x00                     ; '\0'
+  0x20000926:  00           DC.B       0x00                     ; '\0'
+  0x20000927:  3A           DC.B       0x3A                     ; ':'
+  0x20000928:  00           DC.B       0x00                     ; '\0'
+  0x20000929:  00           DC.B       0x00                     ; '\0'
+  0x2000092A:  00           DC.B       0x00                     ; '\0'
+  0x2000092B:  02           DC.B       0x02                     ; '\x02'
+  0x2000092C:  00           DC.B       0x00                     ; '\0'
+  0x2000092D:  14           DC.B       0x14                     ; '\x14'
+  0x2000092E:  00           DC.B       0x00                     ; '\0'
+  0x2000092F:  7E           DC.B       0x7E                     ; '~'
+  0x20000930:  05           DC.B       0x05                     ; '\x05'
+  0x20000931:  00           DC.B       0x00                     ; '\0'
+  0x20000932:  00           DC.B       0x00                     ; '\0'
+  0x20000933:  01           DC.B       0x01                     ; '\x01'
+  0x20000934:  00           DC.B       0x00                     ; '\0'
+  0x20000935:  00           DC.B       0x00                     ; '\0'
+  0x20000936:  00           DC.B       0x00                     ; '\0'
+  0x20000937:  58           DC.B       0x58                     ; 'X'
+  0x20000938:  00           DC.B       0x00                     ; '\0'
+  0x20000939:  00           DC.B       0x00                     ; '\0'
+  0x2000093A:  00           DC.B       0x00                     ; '\0'
+  0x2000093B:  02           DC.B       0x02                     ; '\x02'
+  0x2000093C:  00           DC.B       0x00                     ; '\0'
+  0x2000093D:  16           DC.B       0x16                     ; '\x16'
+  0x2000093E:  00           DC.B       0x00                     ; '\0'
+  0x2000093F:  32           DC.B       0x32                     ; '2'
+  0x20000940:  06           DC.B       0x06                     ; '\x06'
+  0x20000941:  00           DC.B       0x00                     ; '\0'
+  0x20000942:  00           DC.B       0x00                     ; '\0'
+  0x20000943:  64           DC.B       0x64                     ; 'd'
+  0x20000944:  00           DC.B       0x00                     ; '\0'
+  0x20000945:  00           DC.B       0x00                     ; '\0'
+  0x20000946:  00           DC.B       0x00                     ; '\0'
+  0x20000947:  00           DC.B       0x00                     ; '\0'
+  0x20000948:  00           DC.B       0x00                     ; '\0'
+  0x20000949:  00           DC.B       0x00                     ; '\0'
+  0x2000094A:  00           DC.B       0x00                     ; '\0'
+  0x2000094B:  00           DC.B       0x00                     ; '\0'
+  0x2000094C:  00           DC.B       0x00                     ; '\0'
+  0x2000094D:  11           DC.B       0x11                     ; '\x11'
+  0x2000094E:  00           DC.B       0x00                     ; '\0'
+  0x2000094F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000950:  00           DC.B       0x00                     ; '\0'
+  0x20000951:  00           DC.B       0x00                     ; '\0'
+  0x20000952:  00           DC.B       0x00                     ; '\0'
+  0x20000953:  00           DC.B       0x00                     ; '\0'
+  0x20000954:  00           DC.B       0x00                     ; '\0'
+  0x20000955:  00           DC.B       0x00                     ; '\0'
+  0x20000956:  00           DC.B       0x00                     ; '\0'
+  0x20000957:  00           DC.B       0x00                     ; '\0'
+  0x20000958:  00           DC.B       0x00                     ; '\0'
+  0x20000959:  00           DC.B       0x00                     ; '\0'
+  0x2000095A:  00           DC.B       0x00                     ; '\0'
+  0x2000095B:  00           DC.B       0x00                     ; '\0'
+  0x2000095C:  00           DC.B       0x00                     ; '\0'
+  0x2000095D:  13           DC.B       0x13                     ; '\x13'
+  0x2000095E:  00           DC.B       0x00                     ; '\0'
+  0x2000095F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000960:  00           DC.B       0x00                     ; '\0'
+  0x20000961:  00           DC.B       0x00                     ; '\0'
+  0x20000962:  00           DC.B       0x00                     ; '\0'
+  0x20000963:  00           DC.B       0x00                     ; '\0'
+  0x20000964:  00           DC.B       0x00                     ; '\0'
+  0x20000965:  00           DC.B       0x00                     ; '\0'
+  0x20000966:  00           DC.B       0x00                     ; '\0'
+  0x20000967:  00           DC.B       0x00                     ; '\0'
+  0x20000968:  00           DC.B       0x00                     ; '\0'
+  0x20000969:  00           DC.B       0x00                     ; '\0'
+  0x2000096A:  00           DC.B       0x00                     ; '\0'
+  0x2000096B:  00           DC.B       0x00                     ; '\0'
+  0x2000096C:  00           DC.B       0x00                     ; '\0'
+  0x2000096D:  14           DC.B       0x14                     ; '\x14'
+  0x2000096E:  00           DC.B       0x00                     ; '\0'
+  0x2000096F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000970:  00           DC.B       0x00                     ; '\0'
+  0x20000971:  00           DC.B       0x00                     ; '\0'
+  0x20000972:  00           DC.B       0x00                     ; '\0'
+  0x20000973:  00           DC.B       0x00                     ; '\0'
+  0x20000974:  00           DC.B       0x00                     ; '\0'
+  0x20000975:  00           DC.B       0x00                     ; '\0'
+  0x20000976:  00           DC.B       0x00                     ; '\0'
+  0x20000977:  00           DC.B       0x00                     ; '\0'
+  0x20000978:  00           DC.B       0x00                     ; '\0'
+  0x20000979:  00           DC.B       0x00                     ; '\0'
+  0x2000097A:  00           DC.B       0x00                     ; '\0'
+  0x2000097B:  00           DC.B       0x00                     ; '\0'
+  0x2000097C:  00           DC.B       0x00                     ; '\0'
+  0x2000097D:  16           DC.B       0x16                     ; '\x16'
+  0x2000097E:  00           DC.B       0x00                     ; '\0'
+  0x2000097F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000980:  00           DC.B       0x00                     ; '\0'
+  0x20000981:  00           DC.B       0x00                     ; '\0'
+  0x20000982:  00           DC.B       0x00                     ; '\0'
+  0x20000983:  00           DC.B       0x00                     ; '\0'
+  0x20000984:  00           DC.B       0x00                     ; '\0'
+  0x20000985:  00           DC.B       0x00                     ; '\0'
+  0x20000986:  00           DC.B       0x00                     ; '\0'
+  0x20000987:  00           DC.B       0x00                     ; '\0'
+  0x20000988:  00           DC.B       0x00                     ; '\0'
+  0x20000989:  00           DC.B       0x00                     ; '\0'
+  0x2000098A:  00           DC.B       0x00                     ; '\0'
+  0x2000098B:  00           DC.B       0x00                     ; '\0'
+  0x2000098C:  00           DC.B       0x00                     ; '\0'
+  0x2000098D:  18           DC.B       0x18                     ; '\x18'
+  0x2000098E:  00           DC.B       0x00                     ; '\0'
+  0x2000098F:  32           DC.B       0x32                     ; '2'
+  0x20000990:  06           DC.B       0x06                     ; '\x06'
+  0x20000991:  00           DC.B       0x00                     ; '\0'
+  0x20000992:  00           DC.B       0x00                     ; '\0'
+  0x20000993:  64           DC.B       0x64                     ; 'd'
+  0x20000994:  00           DC.B       0x00                     ; '\0'
+  0x20000995:  00           DC.B       0x00                     ; '\0'
+  0x20000996:  00           DC.B       0x00                     ; '\0'
+  0x20000997:  00           DC.B       0x00                     ; '\0'
+  0x20000998:  00           DC.B       0x00                     ; '\0'
+  0x20000999:  00           DC.B       0x00                     ; '\0'
+  0x2000099A:  00           DC.B       0x00                     ; '\0'
+  0x2000099B:  00           DC.B       0x00                     ; '\0'
+  0x2000099C:  00           DC.B       0x00                     ; '\0'
+  0x2000099D:  18           DC.B       0x18                     ; '\x18'
+  0x2000099E:  00           DC.B       0x00                     ; '\0'
+  0x2000099F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009A0:  00           DC.B       0x00                     ; '\0'
+  0x200009A1:  00           DC.B       0x00                     ; '\0'
+  0x200009A2:  00           DC.B       0x00                     ; '\0'
+  0x200009A3:  00           DC.B       0x00                     ; '\0'
+  0x200009A4:  00           DC.B       0x00                     ; '\0'
+  0x200009A5:  00           DC.B       0x00                     ; '\0'
+  0x200009A6:  00           DC.B       0x00                     ; '\0'
+  0x200009A7:  00           DC.B       0x00                     ; '\0'
+  0x200009A8:  00           DC.B       0x00                     ; '\0'
+  0x200009A9:  00           DC.B       0x00                     ; '\0'
+  0x200009AA:  00           DC.B       0x00                     ; '\0'
+  0x200009AB:  00           DC.B       0x00                     ; '\0'
+  0x200009AC:  00           DC.B       0x00                     ; '\0'
+  0x200009AD:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200009AE:  00           DC.B       0x00                     ; '\0'
+  0x200009AF:  32           DC.B       0x32                     ; '2'
+  0x200009B0:  06           DC.B       0x06                     ; '\x06'
+  0x200009B1:  00           DC.B       0x00                     ; '\0'
+  0x200009B2:  00           DC.B       0x00                     ; '\0'
+  0x200009B3:  34           DC.B       0x34                     ; '4'
+  0x200009B4:  00           DC.B       0x00                     ; '\0'
+  0x200009B5:  00           DC.B       0x00                     ; '\0'
+  0x200009B6:  00           DC.B       0x00                     ; '\0'
+  0x200009B7:  00           DC.B       0x00                     ; '\0'
+  0x200009B8:  00           DC.B       0x00                     ; '\0'
+  0x200009B9:  00           DC.B       0x00                     ; '\0'
+  0x200009BA:  00           DC.B       0x00                     ; '\0'
+  0x200009BB:  00           DC.B       0x00                     ; '\0'
+  0x200009BC:  00           DC.B       0x00                     ; '\0'
+  0x200009BD:  1A           DC.B       0x1A                     ; '\x1A'
+  0x200009BE:  00           DC.B       0x00                     ; '\0'
+  0x200009BF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009C0:  00           DC.B       0x00                     ; '\0'
+  0x200009C1:  00           DC.B       0x00                     ; '\0'
+  0x200009C2:  00           DC.B       0x00                     ; '\0'
+  0x200009C3:  00           DC.B       0x00                     ; '\0'
+  0x200009C4:  00           DC.B       0x00                     ; '\0'
+  0x200009C5:  00           DC.B       0x00                     ; '\0'
+  0x200009C6:  00           DC.B       0x00                     ; '\0'
+  0x200009C7:  00           DC.B       0x00                     ; '\0'
+  0x200009C8:  00           DC.B       0x00                     ; '\0'
+  0x200009C9:  00           DC.B       0x00                     ; '\0'
+  0x200009CA:  00           DC.B       0x00                     ; '\0'
+  0x200009CB:  00           DC.B       0x00                     ; '\0'
+  0x200009CC:  00           DC.B       0x00                     ; '\0'
+  0x200009CD:  1C           DC.B       0x1C                     ; '\x1C'
+  0x200009CE:  00           DC.B       0x00                     ; '\0'
+  0x200009CF:  32           DC.B       0x32                     ; '2'
+  0x200009D0:  06           DC.B       0x06                     ; '\x06'
+  0x200009D1:  00           DC.B       0x00                     ; '\0'
+  0x200009D2:  00           DC.B       0x00                     ; '\0'
+  0x200009D3:  34           DC.B       0x34                     ; '4'
+  0x200009D4:  00           DC.B       0x00                     ; '\0'
+  0x200009D5:  00           DC.B       0x00                     ; '\0'
+  0x200009D6:  00           DC.B       0x00                     ; '\0'
+  0x200009D7:  00           DC.B       0x00                     ; '\0'
+  0x200009D8:  00           DC.B       0x00                     ; '\0'
+  0x200009D9:  00           DC.B       0x00                     ; '\0'
+  0x200009DA:  00           DC.B       0x00                     ; '\0'
+  0x200009DB:  00           DC.B       0x00                     ; '\0'
+  0x200009DC:  00           DC.B       0x00                     ; '\0'
+  0x200009DD:  1C           DC.B       0x1C                     ; '\x1C'
+  0x200009DE:  00           DC.B       0x00                     ; '\0'
+  0x200009DF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009E0:  00           DC.B       0x00                     ; '\0'
+  0x200009E1:  00           DC.B       0x00                     ; '\0'
+  0x200009E2:  00           DC.B       0x00                     ; '\0'
+  0x200009E3:  00           DC.B       0x00                     ; '\0'
+  0x200009E4:  00           DC.B       0x00                     ; '\0'
+  0x200009E5:  00           DC.B       0x00                     ; '\0'
+  0x200009E6:  00           DC.B       0x00                     ; '\0'
+  0x200009E7:  00           DC.B       0x00                     ; '\0'
+  0x200009E8:  00           DC.B       0x00                     ; '\0'
+  0x200009E9:  00           DC.B       0x00                     ; '\0'
+  0x200009EA:  00           DC.B       0x00                     ; '\0'
+  0x200009EB:  00           DC.B       0x00                     ; '\0'
+  0x200009EC:  00           DC.B       0x00                     ; '\0'
+  0x200009ED:  1E           DC.B       0x1E                     ; '\x1E'
+  0x200009EE:  00           DC.B       0x00                     ; '\0'
+  0x200009EF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x200009F0:  00           DC.B       0x00                     ; '\0'
+  0x200009F1:  00           DC.B       0x00                     ; '\0'
+  0x200009F2:  00           DC.B       0x00                     ; '\0'
+  0x200009F3:  00           DC.B       0x00                     ; '\0'
+  0x200009F4:  00           DC.B       0x00                     ; '\0'
+  0x200009F5:  00           DC.B       0x00                     ; '\0'
+  0x200009F6:  00           DC.B       0x00                     ; '\0'
+  0x200009F7:  00           DC.B       0x00                     ; '\0'
+  0x200009F8:  00           DC.B       0x00                     ; '\0'
+  0x200009F9:  00           DC.B       0x00                     ; '\0'
+  0x200009FA:  00           DC.B       0x00                     ; '\0'
+  0x200009FB:  00           DC.B       0x00                     ; '\0'
+  0x200009FC:  00           DC.B       0x00                     ; '\0'
+  0x200009FD:  20           DC.B       0x20                     ; ' '
+  0x200009FE:  00           DC.B       0x00                     ; '\0'
+  0x200009FF:  32           DC.B       0x32                     ; '2'
+  0x20000A00:  06           DC.B       0x06                     ; '\x06'
+  0x20000A01:  00           DC.B       0x00                     ; '\0'
+  0x20000A02:  00           DC.B       0x00                     ; '\0'
+  0x20000A03:  2C           DC.B       0x2C                     ; ','
+  0x20000A04:  00           DC.B       0x00                     ; '\0'
+  0x20000A05:  00           DC.B       0x00                     ; '\0'
+  0x20000A06:  00           DC.B       0x00                     ; '\0'
+  0x20000A07:  00           DC.B       0x00                     ; '\0'
+  0x20000A08:  00           DC.B       0x00                     ; '\0'
+  0x20000A09:  00           DC.B       0x00                     ; '\0'
+  0x20000A0A:  00           DC.B       0x00                     ; '\0'
+  0x20000A0B:  00           DC.B       0x00                     ; '\0'
+  0x20000A0C:  00           DC.B       0x00                     ; '\0'
+  0x20000A0D:  20           DC.B       0x20                     ; ' '
+  0x20000A0E:  00           DC.B       0x00                     ; '\0'
+  0x20000A0F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A10:  00           DC.B       0x00                     ; '\0'
+  0x20000A11:  00           DC.B       0x00                     ; '\0'
+  0x20000A12:  00           DC.B       0x00                     ; '\0'
+  0x20000A13:  00           DC.B       0x00                     ; '\0'
+  0x20000A14:  00           DC.B       0x00                     ; '\0'
+  0x20000A15:  00           DC.B       0x00                     ; '\0'
+  0x20000A16:  00           DC.B       0x00                     ; '\0'
+  0x20000A17:  00           DC.B       0x00                     ; '\0'
+  0x20000A18:  00           DC.B       0x00                     ; '\0'
+  0x20000A19:  00           DC.B       0x00                     ; '\0'
+  0x20000A1A:  00           DC.B       0x00                     ; '\0'
+  0x20000A1B:  00           DC.B       0x00                     ; '\0'
+  0x20000A1C:  00           DC.B       0x00                     ; '\0'
+  0x20000A1D:  22           DC.B       0x22                     ; '\"'
+  0x20000A1E:  00           DC.B       0x00                     ; '\0'
+  0x20000A1F:  32           DC.B       0x32                     ; '2'
+  0x20000A20:  06           DC.B       0x06                     ; '\x06'
+  0x20000A21:  00           DC.B       0x00                     ; '\0'
+  0x20000A22:  00           DC.B       0x00                     ; '\0'
+  0x20000A23:  48           DC.B       0x48                     ; 'H'
+  0x20000A24:  00           DC.B       0x00                     ; '\0'
+  0x20000A25:  00           DC.B       0x00                     ; '\0'
+  0x20000A26:  00           DC.B       0x00                     ; '\0'
+  0x20000A27:  00           DC.B       0x00                     ; '\0'
+  0x20000A28:  00           DC.B       0x00                     ; '\0'
+  0x20000A29:  00           DC.B       0x00                     ; '\0'
+  0x20000A2A:  00           DC.B       0x00                     ; '\0'
+  0x20000A2B:  00           DC.B       0x00                     ; '\0'
+  0x20000A2C:  00           DC.B       0x00                     ; '\0'
+  0x20000A2D:  22           DC.B       0x22                     ; '\"'
+  0x20000A2E:  00           DC.B       0x00                     ; '\0'
+  0x20000A2F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A30:  00           DC.B       0x00                     ; '\0'
+  0x20000A31:  00           DC.B       0x00                     ; '\0'
+  0x20000A32:  00           DC.B       0x00                     ; '\0'
+  0x20000A33:  00           DC.B       0x00                     ; '\0'
+  0x20000A34:  00           DC.B       0x00                     ; '\0'
+  0x20000A35:  00           DC.B       0x00                     ; '\0'
+  0x20000A36:  00           DC.B       0x00                     ; '\0'
+  0x20000A37:  00           DC.B       0x00                     ; '\0'
+  0x20000A38:  00           DC.B       0x00                     ; '\0'
+  0x20000A39:  00           DC.B       0x00                     ; '\0'
+  0x20000A3A:  00           DC.B       0x00                     ; '\0'
+  0x20000A3B:  00           DC.B       0x00                     ; '\0'
+  0x20000A3C:  00           DC.B       0x00                     ; '\0'
+  0x20000A3D:  24           DC.B       0x24                     ; '$'
+  0x20000A3E:  00           DC.B       0x00                     ; '\0'
+  0x20000A3F:  32           DC.B       0x32                     ; '2'
+  0x20000A40:  06           DC.B       0x06                     ; '\x06'
+  0x20000A41:  00           DC.B       0x00                     ; '\0'
+  0x20000A42:  00           DC.B       0x00                     ; '\0'
+  0x20000A43:  54           DC.B       0x54                     ; 'T'
+  0x20000A44:  00           DC.B       0x00                     ; '\0'
+  0x20000A45:  00           DC.B       0x00                     ; '\0'
+  0x20000A46:  00           DC.B       0x00                     ; '\0'
+  0x20000A47:  00           DC.B       0x00                     ; '\0'
+  0x20000A48:  00           DC.B       0x00                     ; '\0'
+  0x20000A49:  00           DC.B       0x00                     ; '\0'
+  0x20000A4A:  00           DC.B       0x00                     ; '\0'
+  0x20000A4B:  00           DC.B       0x00                     ; '\0'
+  0x20000A4C:  00           DC.B       0x00                     ; '\0'
+  0x20000A4D:  24           DC.B       0x24                     ; '$'
+  0x20000A4E:  00           DC.B       0x00                     ; '\0'
+  0x20000A4F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A50:  00           DC.B       0x00                     ; '\0'
+  0x20000A51:  00           DC.B       0x00                     ; '\0'
+  0x20000A52:  00           DC.B       0x00                     ; '\0'
+  0x20000A53:  00           DC.B       0x00                     ; '\0'
+  0x20000A54:  00           DC.B       0x00                     ; '\0'
+  0x20000A55:  00           DC.B       0x00                     ; '\0'
+  0x20000A56:  00           DC.B       0x00                     ; '\0'
+  0x20000A57:  00           DC.B       0x00                     ; '\0'
+  0x20000A58:  00           DC.B       0x00                     ; '\0'
+  0x20000A59:  00           DC.B       0x00                     ; '\0'
+  0x20000A5A:  00           DC.B       0x00                     ; '\0'
+  0x20000A5B:  00           DC.B       0x00                     ; '\0'
+  0x20000A5C:  00           DC.B       0x00                     ; '\0'
+  0x20000A5D:  26           DC.B       0x26                     ; '&'
+  0x20000A5E:  00           DC.B       0x00                     ; '\0'
+  0x20000A5F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A60:  00           DC.B       0x00                     ; '\0'
+  0x20000A61:  00           DC.B       0x00                     ; '\0'
+  0x20000A62:  00           DC.B       0x00                     ; '\0'
+  0x20000A63:  00           DC.B       0x00                     ; '\0'
+  0x20000A64:  00           DC.B       0x00                     ; '\0'
+  0x20000A65:  00           DC.B       0x00                     ; '\0'
+  0x20000A66:  00           DC.B       0x00                     ; '\0'
+  0x20000A67:  00           DC.B       0x00                     ; '\0'
+  0x20000A68:  00           DC.B       0x00                     ; '\0'
+  0x20000A69:  00           DC.B       0x00                     ; '\0'
+  0x20000A6A:  00           DC.B       0x00                     ; '\0'
+  0x20000A6B:  00           DC.B       0x00                     ; '\0'
+  0x20000A6C:  00           DC.B       0x00                     ; '\0'
+  0x20000A6D:  28           DC.B       0x28                     ; '('
+  0x20000A6E:  00           DC.B       0x00                     ; '\0'
+  0x20000A6F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A70:  00           DC.B       0x00                     ; '\0'
+  0x20000A71:  00           DC.B       0x00                     ; '\0'
+  0x20000A72:  00           DC.B       0x00                     ; '\0'
+  0x20000A73:  00           DC.B       0x00                     ; '\0'
+  0x20000A74:  00           DC.B       0x00                     ; '\0'
+  0x20000A75:  00           DC.B       0x00                     ; '\0'
+  0x20000A76:  00           DC.B       0x00                     ; '\0'
+  0x20000A77:  00           DC.B       0x00                     ; '\0'
+  0x20000A78:  00           DC.B       0x00                     ; '\0'
+  0x20000A79:  00           DC.B       0x00                     ; '\0'
+  0x20000A7A:  00           DC.B       0x00                     ; '\0'
+  0x20000A7B:  00           DC.B       0x00                     ; '\0'
+  0x20000A7C:  00           DC.B       0x00                     ; '\0'
+  0x20000A7D:  2A           DC.B       0x2A                     ; '*'
+  0x20000A7E:  00           DC.B       0x00                     ; '\0'
+  0x20000A7F:  32           DC.B       0x32                     ; '2'
+  0x20000A80:  06           DC.B       0x06                     ; '\x06'
+  0x20000A81:  00           DC.B       0x00                     ; '\0'
+  0x20000A82:  00           DC.B       0x00                     ; '\0'
+  0x20000A83:  1C           DC.B       0x1C                     ; '\x1C'
+  0x20000A84:  00           DC.B       0x00                     ; '\0'
+  0x20000A85:  00           DC.B       0x00                     ; '\0'
+  0x20000A86:  00           DC.B       0x00                     ; '\0'
+  0x20000A87:  00           DC.B       0x00                     ; '\0'
+  0x20000A88:  00           DC.B       0x00                     ; '\0'
+  0x20000A89:  00           DC.B       0x00                     ; '\0'
+  0x20000A8A:  00           DC.B       0x00                     ; '\0'
+  0x20000A8B:  00           DC.B       0x00                     ; '\0'
+  0x20000A8C:  00           DC.B       0x00                     ; '\0'
+  0x20000A8D:  2A           DC.B       0x2A                     ; '*'
+  0x20000A8E:  00           DC.B       0x00                     ; '\0'
+  0x20000A8F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000A90:  00           DC.B       0x00                     ; '\0'
+  0x20000A91:  00           DC.B       0x00                     ; '\0'
+  0x20000A92:  00           DC.B       0x00                     ; '\0'
+  0x20000A93:  00           DC.B       0x00                     ; '\0'
+  0x20000A94:  00           DC.B       0x00                     ; '\0'
+  0x20000A95:  00           DC.B       0x00                     ; '\0'
+  0x20000A96:  00           DC.B       0x00                     ; '\0'
+  0x20000A97:  00           DC.B       0x00                     ; '\0'
+  0x20000A98:  00           DC.B       0x00                     ; '\0'
+  0x20000A99:  00           DC.B       0x00                     ; '\0'
+  0x20000A9A:  00           DC.B       0x00                     ; '\0'
+  0x20000A9B:  00           DC.B       0x00                     ; '\0'
+  0x20000A9C:  00           DC.B       0x00                     ; '\0'
+  0x20000A9D:  2C           DC.B       0x2C                     ; ','
+  0x20000A9E:  00           DC.B       0x00                     ; '\0'
+  0x20000A9F:  32           DC.B       0x32                     ; '2'
+  0x20000AA0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AA1:  00           DC.B       0x00                     ; '\0'
+  0x20000AA2:  00           DC.B       0x00                     ; '\0'
+  0x20000AA3:  10           DC.B       0x10                     ; '\x10'
+  0x20000AA4:  00           DC.B       0x00                     ; '\0'
+  0x20000AA5:  00           DC.B       0x00                     ; '\0'
+  0x20000AA6:  00           DC.B       0x00                     ; '\0'
+  0x20000AA7:  00           DC.B       0x00                     ; '\0'
+  0x20000AA8:  00           DC.B       0x00                     ; '\0'
+  0x20000AA9:  00           DC.B       0x00                     ; '\0'
+  0x20000AAA:  00           DC.B       0x00                     ; '\0'
+  0x20000AAB:  00           DC.B       0x00                     ; '\0'
+  0x20000AAC:  00           DC.B       0x00                     ; '\0'
+  0x20000AAD:  2C           DC.B       0x2C                     ; ','
+  0x20000AAE:  00           DC.B       0x00                     ; '\0'
+  0x20000AAF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AB0:  00           DC.B       0x00                     ; '\0'
+  0x20000AB1:  00           DC.B       0x00                     ; '\0'
+  0x20000AB2:  00           DC.B       0x00                     ; '\0'
+  0x20000AB3:  00           DC.B       0x00                     ; '\0'
+  0x20000AB4:  00           DC.B       0x00                     ; '\0'
+  0x20000AB5:  00           DC.B       0x00                     ; '\0'
+  0x20000AB6:  00           DC.B       0x00                     ; '\0'
+  0x20000AB7:  00           DC.B       0x00                     ; '\0'
+  0x20000AB8:  00           DC.B       0x00                     ; '\0'
+  0x20000AB9:  00           DC.B       0x00                     ; '\0'
+  0x20000ABA:  00           DC.B       0x00                     ; '\0'
+  0x20000ABB:  00           DC.B       0x00                     ; '\0'
+  0x20000ABC:  00           DC.B       0x00                     ; '\0'
+  0x20000ABD:  2E           DC.B       0x2E                     ; '.'
+  0x20000ABE:  00           DC.B       0x00                     ; '\0'
+  0x20000ABF:  32           DC.B       0x32                     ; '2'
+  0x20000AC0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AC1:  00           DC.B       0x00                     ; '\0'
+  0x20000AC2:  00           DC.B       0x00                     ; '\0'
+  0x20000AC3:  10           DC.B       0x10                     ; '\x10'
+  0x20000AC4:  00           DC.B       0x00                     ; '\0'
+  0x20000AC5:  00           DC.B       0x00                     ; '\0'
+  0x20000AC6:  00           DC.B       0x00                     ; '\0'
+  0x20000AC7:  00           DC.B       0x00                     ; '\0'
+  0x20000AC8:  00           DC.B       0x00                     ; '\0'
+  0x20000AC9:  00           DC.B       0x00                     ; '\0'
+  0x20000ACA:  00           DC.B       0x00                     ; '\0'
+  0x20000ACB:  00           DC.B       0x00                     ; '\0'
+  0x20000ACC:  00           DC.B       0x00                     ; '\0'
+  0x20000ACD:  2E           DC.B       0x2E                     ; '.'
+  0x20000ACE:  00           DC.B       0x00                     ; '\0'
+  0x20000ACF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AD0:  00           DC.B       0x00                     ; '\0'
+  0x20000AD1:  00           DC.B       0x00                     ; '\0'
+  0x20000AD2:  00           DC.B       0x00                     ; '\0'
+  0x20000AD3:  00           DC.B       0x00                     ; '\0'
+  0x20000AD4:  00           DC.B       0x00                     ; '\0'
+  0x20000AD5:  00           DC.B       0x00                     ; '\0'
+  0x20000AD6:  00           DC.B       0x00                     ; '\0'
+  0x20000AD7:  00           DC.B       0x00                     ; '\0'
+  0x20000AD8:  00           DC.B       0x00                     ; '\0'
+  0x20000AD9:  00           DC.B       0x00                     ; '\0'
+  0x20000ADA:  00           DC.B       0x00                     ; '\0'
+  0x20000ADB:  00           DC.B       0x00                     ; '\0'
+  0x20000ADC:  00           DC.B       0x00                     ; '\0'
+  0x20000ADD:  30           DC.B       0x30                     ; '0'
+  0x20000ADE:  00           DC.B       0x00                     ; '\0'
+  0x20000ADF:  32           DC.B       0x32                     ; '2'
+  0x20000AE0:  06           DC.B       0x06                     ; '\x06'
+  0x20000AE1:  00           DC.B       0x00                     ; '\0'
+  0x20000AE2:  00           DC.B       0x00                     ; '\0'
+  0x20000AE3:  60           DC.B       0x60                     ; '`'
+  0x20000AE4:  00           DC.B       0x00                     ; '\0'
+  0x20000AE5:  00           DC.B       0x00                     ; '\0'
+  0x20000AE6:  00           DC.B       0x00                     ; '\0'
+  0x20000AE7:  00           DC.B       0x00                     ; '\0'
+  0x20000AE8:  00           DC.B       0x00                     ; '\0'
+  0x20000AE9:  00           DC.B       0x00                     ; '\0'
+  0x20000AEA:  00           DC.B       0x00                     ; '\0'
+  0x20000AEB:  00           DC.B       0x00                     ; '\0'
+  0x20000AEC:  00           DC.B       0x00                     ; '\0'
+  0x20000AED:  30           DC.B       0x30                     ; '0'
+  0x20000AEE:  00           DC.B       0x00                     ; '\0'
+  0x20000AEF:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000AF0:  00           DC.B       0x00                     ; '\0'
+  0x20000AF1:  00           DC.B       0x00                     ; '\0'
+  0x20000AF2:  00           DC.B       0x00                     ; '\0'
+  0x20000AF3:  00           DC.B       0x00                     ; '\0'
+  0x20000AF4:  00           DC.B       0x00                     ; '\0'
+  0x20000AF5:  00           DC.B       0x00                     ; '\0'
+  0x20000AF6:  00           DC.B       0x00                     ; '\0'
+  0x20000AF7:  00           DC.B       0x00                     ; '\0'
+  0x20000AF8:  00           DC.B       0x00                     ; '\0'
+  0x20000AF9:  00           DC.B       0x00                     ; '\0'
+  0x20000AFA:  00           DC.B       0x00                     ; '\0'
+  0x20000AFB:  00           DC.B       0x00                     ; '\0'
+  0x20000AFC:  00           DC.B       0x00                     ; '\0'
+  0x20000AFD:  32           DC.B       0x32                     ; '2'
+  0x20000AFE:  00           DC.B       0x00                     ; '\0'
+  0x20000AFF:  32           DC.B       0x32                     ; '2'
+  0x20000B00:  06           DC.B       0x06                     ; '\x06'
+  0x20000B01:  00           DC.B       0x00                     ; '\0'
+  0x20000B02:  00           DC.B       0x00                     ; '\0'
+  0x20000B03:  60           DC.B       0x60                     ; '`'
+  0x20000B04:  00           DC.B       0x00                     ; '\0'
+  0x20000B05:  00           DC.B       0x00                     ; '\0'
+  0x20000B06:  00           DC.B       0x00                     ; '\0'
+  0x20000B07:  00           DC.B       0x00                     ; '\0'
+  0x20000B08:  00           DC.B       0x00                     ; '\0'
+  0x20000B09:  00           DC.B       0x00                     ; '\0'
+  0x20000B0A:  00           DC.B       0x00                     ; '\0'
+  0x20000B0B:  00           DC.B       0x00                     ; '\0'
+  0x20000B0C:  00           DC.B       0x00                     ; '\0'
+  0x20000B0D:  32           DC.B       0x32                     ; '2'
+  0x20000B0E:  00           DC.B       0x00                     ; '\0'
+  0x20000B0F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B10:  00           DC.B       0x00                     ; '\0'
+  0x20000B11:  00           DC.B       0x00                     ; '\0'
+  0x20000B12:  00           DC.B       0x00                     ; '\0'
+  0x20000B13:  00           DC.B       0x00                     ; '\0'
+  0x20000B14:  00           DC.B       0x00                     ; '\0'
+  0x20000B15:  00           DC.B       0x00                     ; '\0'
+  0x20000B16:  00           DC.B       0x00                     ; '\0'
+  0x20000B17:  00           DC.B       0x00                     ; '\0'
+  0x20000B18:  00           DC.B       0x00                     ; '\0'
+  0x20000B19:  00           DC.B       0x00                     ; '\0'
+  0x20000B1A:  00           DC.B       0x00                     ; '\0'
+  0x20000B1B:  00           DC.B       0x00                     ; '\0'
+  0x20000B1C:  00           DC.B       0x00                     ; '\0'
+  0x20000B1D:  34           DC.B       0x34                     ; '4'
+  0x20000B1E:  00           DC.B       0x00                     ; '\0'
+  0x20000B1F:  32           DC.B       0x32                     ; '2'
+  0x20000B20:  06           DC.B       0x06                     ; '\x06'
+  0x20000B21:  00           DC.B       0x00                     ; '\0'
+  0x20000B22:  00           DC.B       0x00                     ; '\0'
+  0x20000B23:  50           DC.B       0x50                     ; 'P'
+  0x20000B24:  00           DC.B       0x00                     ; '\0'
+  0x20000B25:  00           DC.B       0x00                     ; '\0'
+  0x20000B26:  00           DC.B       0x00                     ; '\0'
+  0x20000B27:  00           DC.B       0x00                     ; '\0'
+  0x20000B28:  00           DC.B       0x00                     ; '\0'
+  0x20000B29:  00           DC.B       0x00                     ; '\0'
+  0x20000B2A:  00           DC.B       0x00                     ; '\0'
+  0x20000B2B:  00           DC.B       0x00                     ; '\0'
+  0x20000B2C:  00           DC.B       0x00                     ; '\0'
+  0x20000B2D:  34           DC.B       0x34                     ; '4'
+  0x20000B2E:  00           DC.B       0x00                     ; '\0'
+  0x20000B2F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B30:  00           DC.B       0x00                     ; '\0'
+  0x20000B31:  00           DC.B       0x00                     ; '\0'
+  0x20000B32:  00           DC.B       0x00                     ; '\0'
+  0x20000B33:  00           DC.B       0x00                     ; '\0'
+  0x20000B34:  00           DC.B       0x00                     ; '\0'
+  0x20000B35:  00           DC.B       0x00                     ; '\0'
+  0x20000B36:  00           DC.B       0x00                     ; '\0'
+  0x20000B37:  00           DC.B       0x00                     ; '\0'
+  0x20000B38:  00           DC.B       0x00                     ; '\0'
+  0x20000B39:  00           DC.B       0x00                     ; '\0'
+  0x20000B3A:  00           DC.B       0x00                     ; '\0'
+  0x20000B3B:  00           DC.B       0x00                     ; '\0'
+  0x20000B3C:  00           DC.B       0x00                     ; '\0'
+  0x20000B3D:  36           DC.B       0x36                     ; '6'
+  0x20000B3E:  00           DC.B       0x00                     ; '\0'
+  0x20000B3F:  32           DC.B       0x32                     ; '2'
+  0x20000B40:  06           DC.B       0x06                     ; '\x06'
+  0x20000B41:  00           DC.B       0x00                     ; '\0'
+  0x20000B42:  00           DC.B       0x00                     ; '\0'
+  0x20000B43:  50           DC.B       0x50                     ; 'P'
+  0x20000B44:  00           DC.B       0x00                     ; '\0'
+  0x20000B45:  00           DC.B       0x00                     ; '\0'
+  0x20000B46:  00           DC.B       0x00                     ; '\0'
+  0x20000B47:  00           DC.B       0x00                     ; '\0'
+  0x20000B48:  00           DC.B       0x00                     ; '\0'
+  0x20000B49:  00           DC.B       0x00                     ; '\0'
+  0x20000B4A:  00           DC.B       0x00                     ; '\0'
+  0x20000B4B:  00           DC.B       0x00                     ; '\0'
+  0x20000B4C:  00           DC.B       0x00                     ; '\0'
+  0x20000B4D:  36           DC.B       0x36                     ; '6'
+  0x20000B4E:  00           DC.B       0x00                     ; '\0'
+  0x20000B4F:  D1           DC.B       0xD1                     ; '\xD1'
+  0x20000B50:  00           DC.B       0x00                     ; '\0'
+  0x20000B51:  00           DC.B       0x00                     ; '\0'
+  0x20000B52:  00           DC.B       0x00                     ; '\0'
+  0x20000B53:  00           DC.B       0x00                     ; '\0'
+  0x20000B54:  00           DC.B       0x00                     ; '\0'
+  0x20000B55:  00           DC.B       0x00                     ; '\0'
+  0x20000B56:  00           DC.B       0x00                     ; '\0'
+  0x20000B57:  00           DC.B       0x00                     ; '\0'
+  0x20000B58:  00           DC.B       0x00                     ; '\0'
+  0x20000B59:  00           DC.B       0x00                     ; '\0'
+  0x20000B5A:  00           DC.B       0x00                     ; '\0'
+  0x20000B5B:  00           DC.B       0x00                     ; '\0'
+  0x20000B5C:  00           DC.B       0x00                     ; '\0'
+  0x20000B5D:  38           DC.B       0x38                     ; '8'
+  0x20000B5E:  00           DC.B       0x00                     ; '\0'
+  0x20000B5F:  32           DC.B       0x32                     ; '2'
+  0x20000B60:  06           DC.B       0x06                     ; '\x06'
+  0x20000B61:  00           DC.B       0x00                     ; '\0'
+  0x20000B62:  00           DC.B       0x00                     ; '\0'
+  0x20000B63:  34           DC.B       0x34                     ; '4'
+  0x20000B64:  00           DC.B       0x00                     ; '\0'
+  0x20000B65:  00           DC.B       0x00                     ; '\0'
+  0x20000B66:  00           DC.B       0x00                     ; '\0'
+  0x20000B67:  00           DC.B       0x00                     ; '\0'
+  0x20000B68:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.libc._acDownBuffer from SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_small.a), size=16, align=1

+
+
_acDownBuffer:
+  0x20000B69:  00           DC.B       0x00                     ; '\0'
+  0x20000B6A:  53           DC.B       0x53                     ; 'S'
+  0x20000B6B:  45           DC.B       0x45                     ; 'E'
+  0x20000B6C:  47           DC.B       0x47                     ; 'G'
+  0x20000B6D:  47           DC.B       0x47                     ; 'G'
+  0x20000B6E:  45           DC.B       0x45                     ; 'E'
+  0x20000B6F:  52           DC.B       0x52                     ; 'R'
+  0x20000B70:  20           DC.B       0x20                     ; ' '
+  0x20000B71:  43           DC.B       0x43                     ; 'C'
+  0x20000B72:  2F           DC.B       0x2F                     ; '/'
+  0x20000B73:  43           DC.B       0x43                     ; 'C'
+  0x20000B74:  2B           DC.B       0x2B                     ; '+'
+  0x20000B75:  2B           DC.B       0x2B                     ; '+'
+  0x20000B76:  20           DC.B       0x20                     ; ' '
+  0x20000B77:  63           DC.B       0x63                     ; 'c'
+  0x20000B78:  6F           DC.B       0x6F                     ; 'o'
+
+

Section .no_init from PowerPro_lto.o, size=1, align=4

+
+
bootLoaderMark:
+  0x20000B7C:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.libc.__SEGGER_RTL_global_locale from mbops.o (mbops_timeops_v6m_t_le_eabi_small.a), size=20, align=4

+
+
__SEGGER_RTL_global_locale:
+__RAL_global_locale:
+  0x20000B80:  08005784     DC.W       __SEGGER_RTL_c_locale
+  0x20000B84:  08005784     DC.W       __SEGGER_RTL_c_locale
+  0x20000B88:  08005784     DC.W       __SEGGER_RTL_c_locale
+  0x20000B8C:  08005784     DC.W       __SEGGER_RTL_c_locale
+  0x20000B90:  08005784     DC.W       __SEGGER_RTL_c_locale
+
+

Section .data.uwTickPrio from PowerPro_lto.o, size=4, align=4

+
+
uwTickPrio:
+  0x20000B94:  04           DC.B       0x04                     ; '\x04'
+  0x20000B95:  00           DC.B       0x00                     ; '\0'
+  0x20000B96:  00           DC.B       0x00                     ; '\0'
+  0x20000B97:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.libc.stdout from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stdout:
+  0x20000B98:  200006CC     DC.W       __SEGGER_RTL_stdout_file
+
+

Section .data.libc.stdin from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stdin:
+  0x20000B9C:  200006D0     DC.W       __SEGGER_RTL_stdin_file
+
+

Section .data.libc.stderr from prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_small.a), size=4, align=4

+
+
stderr:
+  0x20000BA0:  200006D4     DC.W       __SEGGER_RTL_stderr_file
+
+

Section .data.SystemCoreClock from PowerPro_lto.o, size=4, align=4

+
+
SystemCoreClock:
+  0x20000BA4:  00           DC.B       0x00                     ; '\0'
+  0x20000BA5:  1B           DC.B       0x1B                     ; '\x1B'
+  0x20000BA6:  B7           DC.B       0xB7                     ; '\xB7'
+  0x20000BA7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.block.stack from [ Linker created ], size=2048, align=8

+
+  0x20002800:  00           DC.B       0x00                     ; '\0'
+  0x20002801:  00           DC.B       0x00                     ; '\0'
+  0x20002802:  00           DC.B       0x00                     ; '\0'
+  0x20002803:  00           DC.B       0x00                     ; '\0'
+  0x20002804:  00           DC.B       0x00                     ; '\0'
+  0x20002805:  00           DC.B       0x00                     ; '\0'
+  0x20002806:  00           DC.B       0x00                     ; '\0'
+  0x20002807:  00           DC.B       0x00                     ; '\0'
+  0x20002808:  00           DC.B       0x00                     ; '\0'
+  0x20002809:  00           DC.B       0x00                     ; '\0'
+  0x2000280A:  00           DC.B       0x00                     ; '\0'
+  0x2000280B:  00           DC.B       0x00                     ; '\0'
+  0x2000280C:  00           DC.B       0x00                     ; '\0'
+  0x2000280D:  00           DC.B       0x00                     ; '\0'
+  0x2000280E:  00           DC.B       0x00                     ; '\0'
+  0x2000280F:  00           DC.B       0x00                     ; '\0'
+  0x20002810:  00           DC.B       0x00                     ; '\0'
+  0x20002811:  00           DC.B       0x00                     ; '\0'
+  0x20002812:  00           DC.B       0x00                     ; '\0'
+  0x20002813:  00           DC.B       0x00                     ; '\0'
+  0x20002814:  00           DC.B       0x00                     ; '\0'
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+  0x20002FE1:  00           DC.B       0x00                     ; '\0'
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+  0x20002FE5:  00           DC.B       0x00                     ; '\0'
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+  0x20002FE8:  00           DC.B       0x00                     ; '\0'
+  0x20002FE9:  00           DC.B       0x00                     ; '\0'
+  0x20002FEA:  00           DC.B       0x00                     ; '\0'
+  0x20002FEB:  00           DC.B       0x00                     ; '\0'
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+  0x20002FED:  00           DC.B       0x00                     ; '\0'
+  0x20002FEE:  00           DC.B       0x00                     ; '\0'
+  0x20002FEF:  00           DC.B       0x00                     ; '\0'
+  0x20002FF0:  00           DC.B       0x00                     ; '\0'
+  0x20002FF1:  00           DC.B       0x00                     ; '\0'
+  0x20002FF2:  00           DC.B       0x00                     ; '\0'
+  0x20002FF3:  00           DC.B       0x00                     ; '\0'
+  0x20002FF4:  00           DC.B       0x00                     ; '\0'
+  0x20002FF5:  00           DC.B       0x00                     ; '\0'
+  0x20002FF6:  00           DC.B       0x00                     ; '\0'
+  0x20002FF7:  00           DC.B       0x00                     ; '\0'
+  0x20002FF8:  00           DC.B       0x00                     ; '\0'
+  0x20002FF9:  00           DC.B       0x00                     ; '\0'
+  0x20002FFA:  00           DC.B       0x00                     ; '\0'
+  0x20002FFB:  00           DC.B       0x00                     ; '\0'
+  0x20002FFC:  00           DC.B       0x00                     ; '\0'
+  0x20002FFD:  00           DC.B       0x00                     ; '\0'
+  0x20002FFE:  00           DC.B       0x00                     ; '\0'
+  0x20002FFF:  00           DC.B       0x00                     ; '\0'
+
+

LINK SUMMARY

+ +
+ 24 876 bytes read-only  code    + 
+  2 625 bytes read-only  data    =  27 501 bytes read-only (total)
+  4 992 bytes read-write data
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSizeUsedUnusedAlignment Loss
FLASH08000000-080077FF30 72027 505 89.53%3 215 10.47%0 0.00%
RAM20000000-20002FFF12 2884 992 40.62%7 260 59.08%36 0.29%
+ +
+Link complete: 0 error.
+
+ Index: /trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.map =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.map (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Exe/PowerPro.map (revision 41) @@ -0,0 +1,1213 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.44.2 compiled Apr 14 2025 15:08:43 + Copyright (c) 2017-2024 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + PowerPro_lto.o 15 446 1 467 8 514 + SEGGER_THUMB_Startup.o 20 + stm32c031xx_Vectors.o 218 + STM32C0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 15 692 1 467 8 514 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_balanced.a 2 372 32 + mbops_timeops_v6m_t_le_eabi_balanced.a 190 541 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 484 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 74 + strops_v6m_t_le_eabi_balanced.a 144 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (5 archives) 3 264 599 32 1 224 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 208 2 048 + ============================================= ========== ========== ========== ========== + Total: 18 956 2 274 40 3 786 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 904 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 146 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 604 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 352 + mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 190 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 366 32 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 66 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 74 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 418 26 1 208 + strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 36 + strops.o (strops_v6m_t_le_eabi_balanced.a) 108 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (11 members from 5 archives) 3 264 599 32 1 224 + Objects (4 files) 15 692 1 467 8 514 + Linker created (shared data, fills, blocks): 208 2 048 + ============================================= ========== ========== ========== ========== + Total: 18 956 2 274 40 3 786 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 208 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 208 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 15 692 1 467 8 514 + Archives (5 files) 3 264 599 32 1 224 + ============================================= ========== ========== ========== ========== + Total: 18 956 2 274 40 3 786 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000b3 _vectors 180 256 + Code RX stm32c031xx_Vectors.o + 080000b4-080000c3 SysTick_Handler 16 4 Code RX PowerPro_lto.o + 080000c4-080001a7 DMA1_Channel1_IRQHandler 228 4 Code RX PowerPro_lto.o + 080001a8-0800034f TIM16_IRQHandler 424 4 Code RX PowerPro_lto.o + 08000350-080003bf HAL_TIM_IC_CaptureCallback + 112 4 Code RX PowerPro_lto.o + 080003c0-080003cf SystemInit 16 4 Code RX PowerPro_lto.o + 080003d0-0800041f SystemCoreClockUpdate 80 4 Code RX PowerPro_lto.o + 08000420-0800047f HAL_InitTick 96 4 Code RX PowerPro_lto.o + 08000480-080006d3 HAL_ADC_ConfigChannel 596 4 Code RX PowerPro_lto.o + 080006d4-0800085b HAL_GPIO_Init 392 4 Code RX PowerPro_lto.o + 0800085c-080008af HAL_RCC_GetSysClockFreq 84 4 Code RX PowerPro_lto.o + 080008b0-0800097b HAL_TIM_Base_Init 204 4 Code RX PowerPro_lto.o + 0800097c-08000a13 TIM_Base_SetConfig 152 4 Code RX PowerPro_lto.o + 08000a14-08003c87 main 12 916 4 Code RX PowerPro_lto.o + 08003c88-08003cc7 AHBPrescTable 64 4 Cnst RO PowerPro_lto.o + 08003cc8-08003ce7 APBPrescTable 32 4 Cnst RO PowerPro_lto.o + 08003ce8-08003cfb _start 20 4 Code RX SEGGER_THUMB_Startup.o + 08003cfc-08003d0b putchar 16 4 Code RX fileops.o (libc_v6m_t_le_eabi_balanced.a) + 08003d0c-08003d37 puts 44 4 Code RX fileops.o (libc_v6m_t_le_eabi_balanced.a) + 08003d38-08003def __aeabi_fmul 184 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003df0-08003eb3 __aeabi_ddiv 196 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003eb4-08003ee7 __aeabi_d2iz 52 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003ee8-08003f0b __aeabi_f2uiz 36 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003f0c-08003f3b __aeabi_d2uiz 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003f3c-08003f57 __aeabi_i2d 28 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003f58-08003f77 __aeabi_ui2f 32 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003f78-08003f93 __aeabi_ui2d 28 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003f94-08003fc3 __aeabi_lmul 48 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08003fc4-08004003 __aeabi_idiv 64 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08004004-0800403b __aeabi_uidiv 56 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800403c-0800404b __aeabi_uidivmod 16 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800404c-080040eb __aeabi_uldivmod 160 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080040ec-080040f3 __aeabi_idiv0 8 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080040f4-0800416b vfprintf_l 120 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0800416c-08004193 printf 40 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 08004194-0800451b __SEGGER_RTL_vfprintf_int_nwp + 904 4 Code RX __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0800451c-0800454f __SEGGER_RTL_X_file_stat 52 4 Code RX prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 08004550-080045a3 _DoInit 84 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 080045a4-0800460b SEGGER_RTT_WriteNoLock 104 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800460c-08004643 SEGGER_RTT_Write 56 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 08004644-080046af strlen 108 4 Code RX strops.o (strops_v6m_t_le_eabi_balanced.a) + 080046b0-080046bf memcpy 16 4 Code RX strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 080046c0-080046d3 __aeabi_memclr 20 4 Code RX strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 080046d4-080046e7 __SEGGER_RTL_current_locale + 20 4 Code RX mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 080046e8-08004703 __SEGGER_RTL_ascii_isctype + 28 4 Code RX mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 08004704-0800471f __SEGGER_RTL_ascii_iswctype + 28 4 Code RX mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 08004720-0800472b __SEGGER_RTL_c_locale 12 4 Cnst RO mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0800472c-0800474b __SEGGER_RTL_codeset_ascii + 32 4 Cnst RO mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0800474c-080047a3 __SEGGER_RTL_c_locale_data + 88 4 Cnst RO mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 080047a4-080047a5 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2000070c-2000070f stderr 4 4 Init RW prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 20000710-20000713 SystemCoreClock 4 4 Init RW PowerPro_lto.o + 20000714-200027ff ( UNUSED .=.+8428 ) 8 428 - ---- - - + 20002800-20002fff [.bss.block.stack] 2 048 8 None ZI [ Linker created ] + + +*********************************************************************************************** +*** *** +*** SYMBOL LIST *** +*** *** +*********************************************************************************************** + +Function symbols by name: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + ADC1_IRQHandler 0x080047C1 2 Code Wk stm32c031xx_Vectors.o + ADC_DMAConvCplt 0x080049B7 100 2 Code Lc PowerPro_lto.o + ADC_DMAError 0x08004A1B 20 2 Code Lc PowerPro_lto.o + ADC_DMAHalfConvCplt 0x080047AD 2 2 Code Lc PowerPro_lto.o + DMA1_Channel1_IRQHandler 0x080000C5 228 4 Code Gb PowerPro_lto.o + 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RCC_IRQHandler 0x080047B5 2 Code Wk stm32c031xx_Vectors.o + RTC_IRQHandler 0x080047B1 2 Code Wk stm32c031xx_Vectors.o + Reset_Handler 0x08004A2F 2 Code Gb STM32C0xx_Startup.o + SEGGER_RTT_Write 0x0800460D 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_WriteNoLock 0x080045A5 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SPI1_IRQHandler 0x080047CF 2 Code Wk stm32c031xx_Vectors.o + SVC_Handler 0x080047A9 2 2 Code Gb PowerPro_lto.o + SysTick_Handler 0x080000B5 16 4 Code Gb PowerPro_lto.o + SystemCoreClockUpdate 0x080003D1 80 4 Code Gb PowerPro_lto.o + SystemInit 0x080003C1 16 4 Code Gb PowerPro_lto.o + TIM14_IRQHandler 0x080047C9 2 Code Wk stm32c031xx_Vectors.o + TIM16_IRQHandler 0x080001A9 424 4 Code Gb PowerPro_lto.o + TIM17_IRQHandler 0x080047CB 2 Code Wk stm32c031xx_Vectors.o + TIM1_BRK_UP_TRG_COM_IRQHandler + 0x080047C3 2 Code Wk stm32c031xx_Vectors.o + TIM1_CC_IRQHandler 0x080047C5 2 Code Wk stm32c031xx_Vectors.o + TIM3_IRQHandler 0x080047C7 2 Code Wk stm32c031xx_Vectors.o + TIM_Base_SetConfig 0x0800097D 152 4 Code Lc PowerPro_lto.o + USART1_IRQHandler 0x080047D1 2 Code Wk stm32c031xx_Vectors.o + USART2_IRQHandler 0x080047D3 2 Code Wk stm32c031xx_Vectors.o + WWDG_IRQHandler 0x080047AF 2 Code Wk stm32c031xx_Vectors.o + _DoInit 0x08004551 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + _GetAvailWriteSpace 0x080048BF 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + _WriteBlocking 0x0800490F 94 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + _WriteNoCheck 0x080048D5 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_bufsize + 0x08004A7B 4 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_stat 0x0800451D 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_write 0x080048B5 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_isctype + 0x080046E9 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 0x08004705 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_mbtowc 0x0800496D 46 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_tolower + 0x0800499B 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_toupper + 0x08004A8F 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towlower + 0x080049A9 14 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towupper + 0x08004A9B 12 2 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_wctomb 0x08004A7F 16 2 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_current_locale + 0x080046D5 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_prin_flush 0x08004881 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_putc 0x080047F7 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_stream_write 0x08004A6B 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_vfprintf 0x08004195 904 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_vfprintf_int_nwp + 0x08004195 904 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_copy 0x080052DF 20 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 0x080051D9 26 4 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __SEGGER_init_done 0x08003CF3 4 Code Gb SEGGER_THUMB_Startup.o + __SEGGER_init_zero 0x080052CD 18 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + __aeabi_d2iz 0x08003EB5 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_d2uiz 0x08003F0D 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ddiv 0x08003DF1 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_f2uiz 0x08003EE9 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fmul 0x08003D39 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_i2d 0x08003F3D 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv 0x08003FC5 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv0 0x080040ED 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 0x08003F95 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr 0x080046C1 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr4 0x080046C1 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memclr8 0x080046C1 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy 0x080046B1 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy4 0x080046B1 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy8 0x080046B1 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset 0x080046C3 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset4 0x080046C3 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_memset8 0x080046C3 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 0x08003F79 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 0x08003F59 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidiv 0x08004005 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uidivmod 0x0800403D 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_uldivmod 0x0800404D 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __startup_complete 0x08003CF3 4 Code Gb SEGGER_THUMB_Startup.o + _start 0x08003CE9 14 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x08003CF7 2 4 Code Gb SEGGER_THUMB_Startup.o + fputc 0x080047D5 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + fwrite 0x08004A37 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x08000A15 12 916 4 Code Gb PowerPro_lto.o + memcpy 0x080046B1 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + memset 0x080046C9 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + printf 0x0800416D 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + putchar 0x08003CFD 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + puts 0x08003D0D 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + reset_handler 0x08004A2F 2 Code Gb STM32C0xx_Startup.o + strlen 0x08004645 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + vfprintf 0x0800489B 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x080040F5 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000B5 SysTick_Handler 16 4 Code Gb PowerPro_lto.o + 0x080000C5 DMA1_Channel1_IRQHandler 228 4 Code Gb PowerPro_lto.o + 0x080001A9 TIM16_IRQHandler 424 4 Code Gb PowerPro_lto.o + 0x08000351 HAL_TIM_IC_CaptureCallback + 112 4 Code Lc PowerPro_lto.o + 0x080003C1 SystemInit 16 4 Code Gb PowerPro_lto.o + 0x080003D1 SystemCoreClockUpdate 80 4 Code Gb PowerPro_lto.o + 0x08000421 HAL_InitTick 96 4 Code Lc PowerPro_lto.o + 0x08000481 HAL_ADC_ConfigChannel 596 4 Code Lc PowerPro_lto.o + 0x080006D5 HAL_GPIO_Init 392 4 Code Lc PowerPro_lto.o + 0x0800085D HAL_RCC_GetSysClockFreq 84 4 Code Lc PowerPro_lto.o + 0x080008B1 HAL_TIM_Base_Init 204 4 Code Lc PowerPro_lto.o + 0x0800097D TIM_Base_SetConfig 152 4 Code Lc PowerPro_lto.o + 0x08000A15 main 12 916 4 Code Gb PowerPro_lto.o + 0x08003CE9 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003CF3 __startup_complete 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003CF3 __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003CF7 exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003CFD putchar 16 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003D0D puts 44 4 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003D39 __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003DF1 __aeabi_ddiv 196 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003EB5 __aeabi_d2iz 52 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003EE9 __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003F0D __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003F3D __aeabi_i2d 22 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003F59 __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003F79 __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003F95 __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08003FC5 __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004005 __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800403D __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800404D __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080040ED __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x080040F5 vfprintf_l 120 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800416D printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004195 __SEGGER_RTL_vfprintf_int_nwp + 904 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004195 __SEGGER_RTL_vfprintf 904 4 Code Gb __SEGGER_RTL_vfprintf_int_nwp.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800451D __SEGGER_RTL_X_file_stat 52 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004551 _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080045A5 SEGGER_RTT_WriteNoLock 104 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x0800460D SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x08004645 strlen 108 4 Code Wk strops.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046B1 memcpy 14 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046B1 __aeabi_memcpy8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046B1 __aeabi_memcpy4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046B1 __aeabi_memcpy 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C1 __aeabi_memclr8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C1 __aeabi_memclr4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C1 __aeabi_memclr 20 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C3 __aeabi_memset8 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C3 __aeabi_memset4 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C3 __aeabi_memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046C9 memset 4 Code Wk strasmops_arm.o (strops_v6m_t_le_eabi_balanced.a) + 0x080046D5 __SEGGER_RTL_current_locale + 20 4 Code Gb mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080046E9 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x08004705 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (mbops_timeops_v6m_t_le_eabi_balanced.a) + 0x080047A5 NMI_Handler 2 2 Code Gb PowerPro_lto.o + 0x080047A7 HardFault_Handler 2 2 Code Gb PowerPro_lto.o + 0x080047A9 SVC_Handler 2 2 Code Gb PowerPro_lto.o + 0x080047AB PendSV_Handler 2 2 Code Gb PowerPro_lto.o + 0x080047AD ADC_DMAHalfConvCplt 2 2 Code Lc PowerPro_lto.o + 0x080047AF WWDG_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047B1 RTC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047B3 FLASH_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047B5 RCC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047B7 EXTI0_1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047B9 EXTI2_3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047BB EXTI4_15_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047BD DMA1_Channel2_3_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x080047BF DMAMUX1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047C1 ADC1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047C3 TIM1_BRK_UP_TRG_COM_IRQHandler + 2 Code Wk stm32c031xx_Vectors.o + 0x080047C5 TIM1_CC_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047C7 TIM3_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047C9 TIM14_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047CB TIM17_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047CD I2C1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047CF SPI1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047D1 USART1_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047D3 USART2_IRQHandler 2 Code Wk stm32c031xx_Vectors.o + 0x080047D5 fputc 34 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + 0x080047F7 __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x08004881 __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800489B vfprintf 26 2 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0x080048B5 __SEGGER_RTL_X_file_write 10 2 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080048BF _GetAvailWriteSpace 22 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x080048D5 _WriteNoCheck 58 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x0800490F _WriteBlocking 94 2 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0x0800496D __SEGGER_RTL_ascii_mbtowc 46 2 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20000000-20002fff 12 288 3 826 31.14% 8 432 68.62% 30 0.24% + +Link complete: 0 errors, 0 warnings, 0 remarks Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/PowerPro_link.ind =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/PowerPro_link.ind (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/PowerPro_link.ind (revision 41) @@ -0,0 +1,10 @@ +Output/Release_48V/Obj/PowerPro/SEGGER_THUMB_Startup.o +Output/Release_48V/Obj/PowerPro/stm32c031xx_Vectors.o +Output/Release_48V/Obj/PowerPro/STM32C0xx_Startup.o +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_small.a" Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/SEGGER_THUMB_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/SEGGER_THUMB_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_48V/Obj/PowerPro/SEGGER_THUMB_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\SEGGER_THUMB_Startup.s Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/STM32C0xx_Startup.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/STM32C0xx_Startup.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_48V/Obj/PowerPro/STM32C0xx_Startup.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\STM32C0xx_Startup.s Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/adc.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/button.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/button.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/button.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_48V/Obj/PowerPro/button.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\button.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/buzzer.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/buzzer.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/buzzer.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/buzzer.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\buzzer.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/chip_temperature.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/chip_temperature.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/chip_temperature.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_48V/Obj/PowerPro/chip_temperature.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\chip_temperature.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/dma.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/eeprom.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/eeprom.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/eeprom.d (revision 41) @@ -0,0 +1,49 @@ +Output/Release_48V/Obj/PowerPro/eeprom.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\eeprom.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\string.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/fan.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/fan.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/fan.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_48V/Obj/PowerPro/fan.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\fan.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/gpio.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/iwdg.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/leds.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/leds.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/leds.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/leds.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\leds.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/main.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/main.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/main.d (revision 41) @@ -0,0 +1,70 @@ +Output/Release_48V/Obj/PowerPro/main.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\main.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\iwdg.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\fan.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\eeprom.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/modbus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/modbus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/modbus.d (revision 41) @@ -0,0 +1,48 @@ +Output/Release_48V/Obj/PowerPro/modbus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modbus.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_lvp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_lvp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_lvp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_48V/Obj/PowerPro/mode_lvp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_lvp_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_lvp_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_48V/Obj/PowerPro/mode_lvp_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_lvp_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_mainswitch.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_48V/Obj/PowerPro/mode_mainswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_mainswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_mainswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_ovp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_ovp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_ovp.d (revision 41) @@ -0,0 +1,52 @@ +Output/Release_48V/Obj/PowerPro/mode_ovp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_ovp.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_ovp.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,53 @@ +Output/Release_48V/Obj/PowerPro/mode_secondaryprotection.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_secondaryprotection_plus.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/mode_secondaryprotection_plus.d (revision 41) @@ -0,0 +1,53 @@ +Output/Release_48V/Obj/PowerPro/mode_secondaryprotection_plus.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection_plus.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\mode_secondaryprotection_plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\button.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\leds.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\buzzer.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\chip_temperature.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/modeswitch.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/modeswitch.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/modeswitch.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_48V/Obj/PowerPro/modeswitch.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modeswitch.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modeswitch.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/relais.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/relais.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/relais.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_48V/Obj/PowerPro/relais.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\relais.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c031xx_Vectors.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c031xx_Vectors.d (revision 41) @@ -0,0 +1,2 @@ +Output/Release_48V/Obj/PowerPro/stm32c031xx_Vectors.o: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v2\SES\STM32C0xx\Source\stm32c031xx_Vectors.s Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_cortex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_exti.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_gpio.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,43 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_msp.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_hal_msp.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,42 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/stm32c0xx_it.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release_48V/Obj/PowerPro/stm32c0xx_it.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_it.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_it.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/sysdata.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/sysdata.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/sysdata.d (revision 41) @@ -0,0 +1,46 @@ +Output/Release_48V/Obj/PowerPro/sysdata.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\sysdata.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdbool.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/system_stm32c0xx.d (revision 41) @@ -0,0 +1,15 @@ +Output/Release_48V/Obj/PowerPro/system_stm32c0xx.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\system_stm32c0xx.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/tim.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/tim.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/tim.d (revision 41) @@ -0,0 +1,45 @@ +Output/Release_48V/Obj/PowerPro/tim.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\tim.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/usart.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/usart.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/usart.d (revision 41) @@ -0,0 +1,44 @@ +Output/Release_48V/Obj/PowerPro/usart.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\usart.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\usart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h Index: /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/voltage_meas.d =================================================================== --- /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/voltage_meas.d (revision 41) +++ /trunk/firmware_v3/SES/Output/Release_48V/Obj/PowerPro/voltage_meas.d (revision 41) @@ -0,0 +1,49 @@ +Output/Release_48V/Obj/PowerPro/voltage_meas.bc: \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\voltage_meas.c \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c031xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\__SEGGER_RTL_Arm_Conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_version.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\cmsis_gcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Include\mpu_armv7.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Inc\stm32c0xx_hal_conf.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stddef.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_iwdg.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\voltage_meas.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\main.h \ + D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\inc\relais.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\inttypes.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ 8.26c\include\stdio.h Index: /trunk/firmware_v3/SES/PowerPro.emProject =================================================================== --- /trunk/firmware_v3/SES/PowerPro.emProject (revision 41) +++ /trunk/firmware_v3/SES/PowerPro.emProject (revision 41) @@ -0,0 +1,241 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /trunk/firmware_v3/SES/PowerPro.emSession =================================================================== --- /trunk/firmware_v3/SES/PowerPro.emSession (revision 41) +++ /trunk/firmware_v3/SES/PowerPro.emSession (revision 41) @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /trunk/firmware_v3/SES/PowerPro.mak =================================================================== --- /trunk/firmware_v3/SES/PowerPro.mak (revision 41) +++ /trunk/firmware_v3/SES/PowerPro.mak (revision 41) @@ -0,0 +1,326 @@ +all: \ + Output/Debug_24V/Obj/PowerPro\ + Output/Debug_24V/Exe\ + Output/Debug_24V/Exe/PowerPro.elf\ + +Output/Debug_24V/Obj/PowerPro: + mkdir -p "Output/Debug_24V/Obj/PowerPro" +Output/Debug_24V/Exe: + mkdir -p "Output/Debug_24V/Exe" + +-include Output/Debug_24V/Obj/PowerPro/adc.d +Output/Debug_24V/Obj/PowerPro/adc.bc:../Core/Src/adc.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/adc.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/adc.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name adc.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\adc.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/adc.bc + +-include Output/Debug_24V/Obj/PowerPro/dma.d +Output/Debug_24V/Obj/PowerPro/dma.bc:../Core/Src/dma.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/dma.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/dma.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name dma.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\dma.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/dma.bc + +-include Output/Debug_24V/Obj/PowerPro/gpio.d +Output/Debug_24V/Obj/PowerPro/gpio.bc:../Core/Src/gpio.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/gpio.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/gpio.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name gpio.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\gpio.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/gpio.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.bc:../Core/Src/stm32c0xx_hal_msp.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_msp.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_hal_msp.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.bc:../Core/Src/stm32c0xx_it.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_it.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\stm32c0xx_it.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.bc + +-include Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.d +Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.bc:../Core/Src/system_stm32c0xx.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name system_stm32c0xx.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\system_stm32c0xx.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.bc + +-include Output/Debug_24V/Obj/PowerPro/tim.d +Output/Debug_24V/Obj/PowerPro/tim.bc:../Core/Src/tim.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/tim.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/tim.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name tim.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\tim.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/tim.bc + +-include Output/Debug_24V/Obj/PowerPro/usart.d +Output/Debug_24V/Obj/PowerPro/usart.bc:../Core/Src/usart.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/usart.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/usart.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name usart.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\usart.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/usart.bc + +-include Output/Debug_24V/Obj/PowerPro/iwdg.d +Output/Debug_24V/Obj/PowerPro/iwdg.bc:../Core/Src/iwdg.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/iwdg.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/iwdg.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name iwdg.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Core\Src\iwdg.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/iwdg.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_adc.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_adc_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_cortex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_dma.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_dma_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_exti.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_flash.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_flash_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_gpio.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_iwdg.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_iwdg.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_pwr.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_pwr_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_rcc.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_rcc_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_tim.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_tim_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_uart.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.bc + +-include Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d +Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc:../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name stm32c0xx_hal_uart_ex.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc + +-include Output/Debug_24V/Obj/PowerPro/button.d +Output/Debug_24V/Obj/PowerPro/button.bc:src/button.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/button.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/button.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name button.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\button.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/button.bc + +-include Output/Debug_24V/Obj/PowerPro/buzzer.d +Output/Debug_24V/Obj/PowerPro/buzzer.bc:src/buzzer.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/buzzer.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/buzzer.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name buzzer.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\buzzer.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/buzzer.bc + +-include Output/Debug_24V/Obj/PowerPro/chip_temperature.d +Output/Debug_24V/Obj/PowerPro/chip_temperature.bc:src/chip_temperature.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/chip_temperature.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/chip_temperature.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name chip_temperature.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\chip_temperature.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/chip_temperature.bc + +-include Output/Debug_24V/Obj/PowerPro/eeprom.d +Output/Debug_24V/Obj/PowerPro/eeprom.bc:src/eeprom.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/eeprom.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/eeprom.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name eeprom.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\eeprom.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/eeprom.bc + +-include Output/Debug_24V/Obj/PowerPro/fan.d +Output/Debug_24V/Obj/PowerPro/fan.bc:src/fan.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/fan.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/fan.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name fan.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\fan.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/fan.bc + +-include Output/Debug_24V/Obj/PowerPro/leds.d +Output/Debug_24V/Obj/PowerPro/leds.bc:src/leds.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/leds.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/leds.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name leds.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\leds.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/leds.bc + +-include Output/Debug_24V/Obj/PowerPro/main.d +Output/Debug_24V/Obj/PowerPro/main.bc:src/main.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/main.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/main.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name main.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\main.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/main.bc + +-include Output/Debug_24V/Obj/PowerPro/modbus.d +Output/Debug_24V/Obj/PowerPro/modbus.bc:src/modbus.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modbus.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/modbus.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name modbus.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modbus.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/modbus.bc + +-include Output/Debug_24V/Obj/PowerPro/mode_lvp.d +Output/Debug_24V/Obj/PowerPro/mode_lvp.bc:src/mode_lvp.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/mode_lvp.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name mode_lvp.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/mode_lvp.bc + +-include Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.d +Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.bc:src/mode_lvp_ovp.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name mode_lvp_ovp.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_lvp_ovp.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.bc + +-include Output/Debug_24V/Obj/PowerPro/mode_mainswitch.d +Output/Debug_24V/Obj/PowerPro/mode_mainswitch.bc:src/mode_mainswitch.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_mainswitch.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/mode_mainswitch.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name mode_mainswitch.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_mainswitch.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/mode_mainswitch.bc + +-include Output/Debug_24V/Obj/PowerPro/mode_ovp.d +Output/Debug_24V/Obj/PowerPro/mode_ovp.bc:src/mode_ovp.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_ovp.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/mode_ovp.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name mode_ovp.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_ovp.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/mode_ovp.bc + +-include Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.d +Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.bc:src/mode_secondaryprotection.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name mode_secondaryprotection.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.bc + +-include Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.d +Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.bc:src/mode_secondaryprotection_plus.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name mode_secondaryprotection_plus.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\mode_secondaryprotection_plus.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.bc + +-include Output/Debug_24V/Obj/PowerPro/modeswitch.d +Output/Debug_24V/Obj/PowerPro/modeswitch.bc:src/modeswitch.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/modeswitch.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/modeswitch.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name modeswitch.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\modeswitch.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/modeswitch.bc + +-include Output/Debug_24V/Obj/PowerPro/relais.d +Output/Debug_24V/Obj/PowerPro/relais.bc:src/relais.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/relais.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/relais.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name relais.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\relais.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/relais.bc + +-include Output/Debug_24V/Obj/PowerPro/sysdata.d +Output/Debug_24V/Obj/PowerPro/sysdata.bc:src/sysdata.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/sysdata.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/sysdata.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name sysdata.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\sysdata.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/sysdata.bc + +-include Output/Debug_24V/Obj/PowerPro/voltage_meas.d +Output/Debug_24V/Obj/PowerPro/voltage_meas.bc:src/voltage_meas.c + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1 -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -nostdsysteminc -nobuiltininc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -dependency-file D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/voltage_meas.d -sys-header-deps -MT Output/Debug_24V/Obj/PowerPro/voltage_meas.bc -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -main-file-name voltage_meas.c D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\src\voltage_meas.c -emit-llvm-bc -o Output/Debug_24V/Obj/PowerPro/voltage_meas.bc + +-include Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d +Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o:SEGGER_THUMB_Startup.s + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/gcc/arm-none-eabi/bin/cc1.exe" -fmessage-length=0 -lang-asm -fdiagnostics-color=never -fdiagnostics-show-caret -E -march=armv6-m -mlittle-endian -mfloat-abi=soft -mthumb -mno-unaligned-access -nostdinc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -MD D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.d -MQ Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o -quiet D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\SEGGER_THUMB_Startup.s -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup_PP.s + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/gcc/arm-none-eabi/bin/as.exe" --traditional-format -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -march=armv6-m -mlittle-endian -mfloat-abi=soft -mthumb D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup_PP.s -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o -g -gdwarf-4 + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/rm.exe" D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup_PP.s + +-include Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.d +Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o:STM32C0xx/Source/stm32c031xx_Vectors.s + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/gcc/arm-none-eabi/bin/cc1.exe" -fmessage-length=0 -lang-asm -fdiagnostics-color=never -fdiagnostics-show-caret -E -march=armv6-m -mlittle-endian -mfloat-abi=soft -mthumb -mno-unaligned-access -nostdinc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -MD D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.d -MQ Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o -quiet D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\stm32c031xx_Vectors.s -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors_PP.s + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/gcc/arm-none-eabi/bin/as.exe" --traditional-format -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -march=armv6-m -mlittle-endian -mfloat-abi=soft -mthumb D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors_PP.s -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o -g -gdwarf-4 + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/rm.exe" D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors_PP.s + +-include Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.d +Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o:STM32C0xx/Source/STM32C0xx_Startup.s + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/gcc/arm-none-eabi/bin/cc1.exe" -fmessage-length=0 -lang-asm -fdiagnostics-color=never -fdiagnostics-show-caret -E -march=armv6-m -mlittle-endian -mfloat-abi=soft -mthumb -mno-unaligned-access -nostdinc "-isystemC:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/include" -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -D__ARM_ARCH_6M__ -D__SES_ARM -D__HEAP_SIZE__=1024 -D__SEGGER_LINKER -D__SES_VERSION=82603 -DARM_MATH_CM0PLUS -DSTM32C031xx -D__STM32C031_SUBFAMILY -D__STM32C0XX_FAMILY -D__NO_FPU_ENABLE -DSYSTEM_VOLTAGE_24V -MD D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.d -MQ Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o -quiet D:\Projekte\ecs_PowerPro\trunk\firmware_v3\SES\STM32C0xx\Source\STM32C0xx_Startup.s -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup_PP.s + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/gcc/arm-none-eabi/bin/as.exe" --traditional-format -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/STM32C0xx_HAL_Driver/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Core/Inc -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/Drivers/CMSIS/Device/ST/STM32C0xx/Include -ID:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/inc -march=armv6-m -mlittle-endian -mfloat-abi=soft -mthumb D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup_PP.s -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o -g -gdwarf-4 + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/rm.exe" D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup_PP.s + +D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind: + echo "Output/Debug_24V/Obj/PowerPro/adc.bc"> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/dma.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/gpio.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/tim.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/usart.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/iwdg.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/button.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/buzzer.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/chip_temperature.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/eeprom.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/fan.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/leds.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/main.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/modbus.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/mode_lvp.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/mode_mainswitch.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/mode_ovp.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/modeswitch.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/relais.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/sysdata.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/voltage_meas.bc">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/libc_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/SEGGER_crtinit_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/prinops_rtt_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_basic_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/strops_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + echo "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/lib/mbops_timeops_v6m_t_le_eabi_balanced.a">> "D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind" + +Output/Debug_24V/Exe/PowerPro.elf:\ + D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind\ + Output/Debug_24V/Obj/PowerPro/adc.bc\ + Output/Debug_24V/Obj/PowerPro/dma.bc\ + Output/Debug_24V/Obj/PowerPro/gpio.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_msp.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_it.bc\ + Output/Debug_24V/Obj/PowerPro/system_stm32c0xx.bc\ + Output/Debug_24V/Obj/PowerPro/tim.bc\ + Output/Debug_24V/Obj/PowerPro/usart.bc\ + Output/Debug_24V/Obj/PowerPro/iwdg.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_adc_ex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_cortex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_dma_ex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_exti.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_flash_ex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_gpio.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_iwdg.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_pwr_ex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_rcc_ex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_tim_ex.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart.bc\ + Output/Debug_24V/Obj/PowerPro/stm32c0xx_hal_uart_ex.bc\ + Output/Debug_24V/Obj/PowerPro/button.bc\ + Output/Debug_24V/Obj/PowerPro/buzzer.bc\ + Output/Debug_24V/Obj/PowerPro/chip_temperature.bc\ + Output/Debug_24V/Obj/PowerPro/eeprom.bc\ + Output/Debug_24V/Obj/PowerPro/fan.bc\ + Output/Debug_24V/Obj/PowerPro/leds.bc\ + Output/Debug_24V/Obj/PowerPro/main.bc\ + Output/Debug_24V/Obj/PowerPro/modbus.bc\ + Output/Debug_24V/Obj/PowerPro/mode_lvp.bc\ + Output/Debug_24V/Obj/PowerPro/mode_lvp_ovp.bc\ + Output/Debug_24V/Obj/PowerPro/mode_mainswitch.bc\ + Output/Debug_24V/Obj/PowerPro/mode_ovp.bc\ + Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection.bc\ + Output/Debug_24V/Obj/PowerPro/mode_secondaryprotection_plus.bc\ + Output/Debug_24V/Obj/PowerPro/modeswitch.bc\ + Output/Debug_24V/Obj/PowerPro/relais.bc\ + Output/Debug_24V/Obj/PowerPro/sysdata.bc\ + Output/Debug_24V/Obj/PowerPro/voltage_meas.bc\ + Output/Debug_24V/Obj/PowerPro/SEGGER_THUMB_Startup.o\ + Output/Debug_24V/Obj/PowerPro/stm32c031xx_Vectors.o\ + Output/Debug_24V/Obj/PowerPro/STM32C0xx_Startup.o\ + D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-cc.exe" -cc1lto -disable-free -disable-llvm-verifier -fgnuc-version=14.3.0 -mrelocation-model static -mconstructor-aliases -x c -triple thumbv6m-none-eabi -target-cpu cortex-m0plus -target-feature +strict-align -target-feature +soft-float -target-feature +soft-float-abi -msoft-float -target-abi aapcs -mfloat-abi soft -fno-signed-char -fnative-half-type -fnative-half-arguments-and-returns -mllvm -arm-global-merge=false -dwarf-version=4 -debug-info-kind=standalone -debugger-tuning=gdb -mllvm -generate-arange-section -gpubnames -fno-dwarf-directory-asm -Og -fmath-errno -ffunction-sections -fdata-sections -fshort-enums -fno-common -input-list D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind -output-list D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_link.ind -emit-obj -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_lto.o --keep-symbol _vectors + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/segger-ld.exe" --add-region:FLASH1=0x00007800@0x08000000 --add-region:RAM1=0x00003000@0x20000000 --full-section-headers --merge-sections --merge-strings --map-text --map-file=Output/Debug_24V/Exe/PowerPro.map --map-standard --list-all-undefineds -eReset_Handler -EL -mcpu=6-M --silent -TD:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/STM32C0xx_Flash.icf --defsym=__STACKSIZE__=2048 --defsym=__STACKSIZE_PROCESS__=0 --defsym=__HEAPSIZE__=1024 --defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_int_nwp --defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int -u_vectors -o D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Exe/PowerPro.elf D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_lto.o @D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_link.ind + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/rm.exe" D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_lto.o + "C:/Program Files/SEGGER/SEGGER Embedded Studio 8.26c/bin/rm.exe" D:/Projekte/ecs_PowerPro/trunk/firmware_v3/SES/Output/Debug_24V/Obj/PowerPro/PowerPro_files.ind Index: /trunk/firmware_v3/SES/PowerPro_Debug.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Debug.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Debug.jlink (revision 41) @@ -0,0 +1,48 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x3000 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[MEM_MAP] +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/PowerPro_Debug_12V.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Debug_12V.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Debug_12V.jlink (revision 41) @@ -0,0 +1,47 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/PowerPro_Debug_24V.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Debug_24V.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Debug_24V.jlink (revision 41) @@ -0,0 +1,48 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[MEM_MAP] +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/PowerPro_Debug_48V.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Debug_48V.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Debug_48V.jlink (revision 41) @@ -0,0 +1,48 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[MEM_MAP] +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/PowerPro_Release.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Release.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Release.jlink (revision 41) @@ -0,0 +1,47 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/PowerPro_Release_12V.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Release_12V.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Release_12V.jlink (revision 41) @@ -0,0 +1,47 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/PowerPro_Release_24V.jlink =================================================================== --- /trunk/firmware_v3/SES/PowerPro_Release_24V.jlink (revision 41) +++ /trunk/firmware_v3/SES/PowerPro_Release_24V.jlink (revision 41) @@ -0,0 +1,47 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[DYN_MEM_MAP] +NumUserRegion = 0x00 Index: /trunk/firmware_v3/SES/SEGGER_THUMB_Startup.s =================================================================== --- /trunk/firmware_v3/SES/SEGGER_THUMB_Startup.s (revision 41) +++ /trunk/firmware_v3/SES/SEGGER_THUMB_Startup.s (revision 41) @@ -0,0 +1,288 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2025 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_THUMB_Startup.s +Purpose : Generic runtime init startup code for ARM CPUs running + in THUMB mode. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + + .syntax unified + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .thumb_func + .code 16 +\Name: +.endm +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .weak \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + ldr R4, =__SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + ldr R0, [R4] // Get next initialization function from table + adds R4, R4, #4 // Increment table pointer to point to function arguments + blx R0 // Call initialization function + b L(RunInit) + // +MARK_FUNC __SEGGER_init_done +MARK_FUNC __startup_complete + // + // Time to call main(), the application entry point. + // +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init R0 and R1. + // + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + b . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load R0 and R1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + movs R0, #ARGSSPACE + ldr R1, =__SEGGER_init_arg_data + bl SEGGER_SEMIHOST_GetArgs + ldr R1, =__SEGGER_init_arg_data + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + bl exit // Call exit function + b . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mov R5, R0 // Save the exit parameter/return result + // + // Call destructors + // + ldr R0, =__dtors_start__ // Pointer to destructor list + ldr R1, =__dtors_end__ +L(Loop): + cmp R0, R1 + beq L(End) // Reached end of destructor list? => Done + ldr R2, [R0] // Load current destructor address into R2 + adds R0, R0, #4 // Increment pointer + push {R0-R1} // Save R0 and R1 + blx R2 // Call destructor + pop {R0-R1} // Restore R0 and R1 + b L(Loop) +L(End): + // + // Call atexit functions + // + bl __SEGGER_RTL_execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mov R0, R5 + // + // Entry points for _exit and _Exit, which terminate immediately. + // Note: Destructors and registered atexit functions are not called. File descriptors are not closed. + // +MARK_FUNC _exit +MARK_FUNC _Exit + bl SEGGER_SEMIHOST_Exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + b L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss + .balign 4 +__SEGGER_init_arg_data: + .space ARGSSPACE + .size __SEGGER_init_arg_data, .-__SEGGER_init_arg_data + .type __SEGGER_init_arg_data, %object +#endif + +/*************************** End of file ****************************/ Index: /trunk/firmware_v3/SES/STM32C031K4Tx_MemoryMap.xml =================================================================== --- /trunk/firmware_v3/SES/STM32C031K4Tx_MemoryMap.xml (revision 41) +++ /trunk/firmware_v3/SES/STM32C031K4Tx_MemoryMap.xml (revision 41) @@ -0,0 +1,5 @@ + + + + + Index: /trunk/firmware_v3/SES/STM32C031_Registers.xml =================================================================== --- /trunk/firmware_v3/SES/STM32C031_Registers.xml (revision 41) +++ /trunk/firmware_v3/SES/STM32C031_Registers.xml (revision 41) @@ -0,0 +1,10097 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32c011xx + * @{ + */ + +#ifndef STM32C011xx_H +#define STM32C011xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32C0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32C0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32c011xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32C0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMAMUX1_IRQn = 11, /*!< DMAMUX Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32c0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKPREG1; /*!< Backup register 1, Address offset: 0x70 */ + __IO uint32_t BKPREG2; /*!< Backup register 2, Address offset: 0x74 */ + __IO uint32_t BKPREG3; /*!< Backup register 3, Address offset: 0x78 */ + __IO uint32_t BKPREG4; /*!< Backup register 4, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00001500UL) /*!< maximum SRAM size (up to 6 KBytes) */ +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) + + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) + + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/********************************* DEVICE ID ********************************/ +#define DEV_ID 0x443UL + +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ + +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ + +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ + +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ + +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFEAFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ + +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ + +#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ +#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ +#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk +#define FLASH_ACR_DBG_SWEN_Pos (18U) +#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ +#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_SEC_PROT_Pos (28U) +#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ +#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_EN_Pos (8U) +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk +#define FLASH_OPTR_BORF_LEV_Pos (9U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORR_LEV_Pos (11U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (15U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk +#define FLASH_OPTR_NRST_MODE_Pos (27U) +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_IRHEN_Pos (29U) +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk + + +/****************** Bits definition for FLASH_SECR register *****************/ +#define FLASH_SECR_SEC_SIZE_Pos (0U) +#define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */ +#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk +#define FLASH_SECR_BOOT_LOCK_Pos (16U) +#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ +#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKPREG1; /*!< Backup register 1, Address offset: 0x70 */ + __IO uint32_t BKPREG2; /*!< Backup register 2, Address offset: 0x74 */ + __IO uint32_t BKPREG3; /*!< Backup register 3, Address offset: 0x78 */ + __IO uint32_t BKPREG4; /*!< Backup register 4, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00003000UL) /*!< maximum SRAM size (up to 12 KBytes) */ +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) + + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) + + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/********************************* DEVICE ID ********************************/ +#define DEV_ID 0x453UL + +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ + +/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) +#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ +#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ + +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ +#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ + +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ +#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ + +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ +#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ + +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFEAFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ + +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ + +#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ +#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ +#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk +#define FLASH_ACR_DBG_SWEN_Pos (18U) +#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ +#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_SEC_PROT_Pos (28U) +#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ +#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_EN_Pos (8U) +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk +#define FLASH_OPTR_BORF_LEV_Pos (9U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORR_LEV_Pos (11U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (15U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk +#define FLASH_OPTR_NRST_MODE_Pos (27U) +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_IRHEN_Pos (29U) +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk + + +/****************** Bits definition for FLASH_SECR register *****************/ +#define FLASH_SECR_SEC_SIZE_Pos (0U) +#define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */ +#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk +#define FLASH_SECR_BOOT_LOCK_Pos (16U) +#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ +#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 48 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value + * 48 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware_v3/SES/STM32C0xx/Scripts/STM32C0xx_Target.js =================================================================== --- /trunk/firmware_v3/SES/STM32C0xx/Scripts/STM32C0xx_Target.js (revision 41) +++ /trunk/firmware_v3/SES/STM32C0xx/Scripts/STM32C0xx_Target.js (revision 41) @@ -0,0 +1,44 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2024 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + Index: /trunk/firmware_v3/SES/STM32C0xx/Source/STM32C0xx_Startup.s =================================================================== --- /trunk/firmware_v3/SES/STM32C0xx/Source/STM32C0xx_Startup.s (revision 41) +++ /trunk/firmware_v3/SES/STM32C0xx/Source/STM32C0xx_Startup.s (revision 41) @@ -0,0 +1,275 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2024 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32C0xx_Startup.s +Purpose : Startup and exception handlers for STM32C0xx devices. + +Additional information: + Preprocessor Definitions + __NO_SYSTEM_INIT + If defined, + SystemInit is not called. + If not defined, + SystemInit is called. + SystemInit is usually supplied by the CMSIS files. + This file declares a weak implementation as fallback. + + __NO_SYSTEM_CLK_UPDATE + If defined, + SystemCoreClockUpdate is not automatically called. + Should be defined if SystemCoreClockUpdate must not be called before main(). + If not defined, + SystemCoreClockUpdate is called before the application entry point. + + __MEMORY_INIT + If defined, + MemoryInit is called after SystemInit. + void MemoryInit(void) can be implemented to enable external + memory controllers. + + __VECTORS_IN_RAM + If defined, + the vector table will be copied from Flash to RAM, + and the vector table offset register is adjusted. + + __VTOR_CONFIG + If defined, + the vector table offset register is set to point to the + application's vector table. + + __NO_FPU_ENABLE + If defined, the FPU is explicitly not enabled, + even if the compiler could use floating point operations. + + __SOFTFP__ + Defined by the build system. + If not defined, the FPU is enabled for floating point operations. +*/ + + .syntax unified + + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* Reset_Handler +* +* Function description +* Exception handler for reset. +* Generic bringup of a Cortex-M system. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .global reset_handler + .global Reset_Handler + .equ reset_handler, Reset_Handler + .section .init.Reset_Handler, "ax" + .balign 2 + .thumb_func +Reset_Handler: +#ifdef __SEGGER_STOP + .extern __SEGGER_STOP_Limit_MSP + // + // Initialize main stack limit to 0 to disable stack checks before runtime init + // + movs R0, #0 + ldr R1, =__SEGGER_STOP_Limit_MSP + str R0, [R1] +#endif +#ifndef __NO_SYSTEM_INIT + // + // Call SystemInit + // + bl SystemInit +#endif +#ifdef __MEMORY_INIT + // + // Call MemoryInit + // + bl MemoryInit +#endif +#ifdef __VECTORS_IN_RAM + // + // Copy vector table (from Flash) to RAM + // + ldr R0, =__vectors_start__ + ldr R1, =__vectors_end__ + ldr R2, =__vectors_ram_start__ +1: + cmp R0, R1 + beq 2f + ldr R3, [R0] + str R3, [R2] + adds R0, R0, #4 + adds R2, R2, #4 + b 1b +2: +#endif + +#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM) + // + // Configure vector table offset register + // +#ifdef __ARM_ARCH_6M__ + ldr R0, =0xE000ED08 // VTOR_REG +#else + movw R0, 0xED08 // VTOR_REG + movt R0, 0xE000 +#endif +#ifdef __VECTORS_IN_RAM + ldr R1, =_vectors_ram +#else + ldr R1, =_vectors +#endif + str R1, [R0] +#endif +#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE) + // + // Enable CP11 and CP10 with CPACR |= (0xf<<20) + // + movw R0, 0xED88 // CPACR + movt R0, 0xE000 + ldr R1, [R0] + orrs R1, R1, #(0xf << 20) + str R1, [R0] +#endif + // + // Call runtime initialization, which calls main(). + // + bl _start + + // + // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, + // when there is no strong definition of SystemInit. + // + .weak SystemInit + // + // Place SystemCoreClockUpdate in .init_array + // to be called after runtime initialization + // +#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE) + .section .init_array, "aw" + .balign 4 + .word SystemCoreClockUpdate +#endif + +/********************************************************************* +* +* HardFault_Handler +* +* Function description +* Simple exception handler for HardFault. +* In case of a HardFault caused by BKPT instruction without +* debugger attached, return execution, otherwise stay in loop. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + +#undef L +#define L(label) .LHardFault_Handler_##label + + .weak HardFault_Handler + .section .init.HardFault_Handler, "ax" + .balign 2 + .thumb_func +HardFault_Handler: + // + // Check if HardFault is caused by BKPT instruction + // + ldr R1, =0xE000ED2C // Load NVIC_HFSR + ldr R2, [R1] + cmp R2, #0 // Check NVIC_HFSR[31] + +L(hfLoop): + bmi L(hfLoop) // Not set? Stay in HardFault Handler. + // + // Continue execution after BKPT instruction + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R0, #4 + mov R1, LR + tst R0, R1 // Check EXC_RETURN in Link register bit 2. + bne L(Uses_PSP) + mrs R0, MSP // Stacking was using MSP. + b L(Pass_StackPtr) +L(Uses_PSP): + mrs R0, PSP // Stacking was using PSP. +L(Pass_StackPtr): +#else + tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack + ite eq + mrseq R0, MSP // Frame stored on MSP + mrsne R0, PSP // Frame stored on PSP +#endif + // + // Reset HardFault Status + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R3, #1 + lsls R3, R3, #31 + orrs R2, R3 + str R2, [R1] +#else + orr R2, R2, #0x80000000 + str R2, [R1] +#endif + // + // Adjust return address + // + ldr R1, [R0, #24] // Get stored PC from stack + adds R1, #2 // Adjust PC by 2 to skip current BKPT + str R1, [R0, #24] // Write back adjusted PC to stack + // + bx LR // Return + +/*************************** End of file ****************************/ Index: /trunk/firmware_v3/SES/STM32C0xx/Source/stm32c031xx_Vectors.s =================================================================== --- /trunk/firmware_v3/SES/STM32C0xx/Source/stm32c031xx_Vectors.s (revision 41) +++ /trunk/firmware_v3/SES/STM32C0xx/Source/stm32c031xx_Vectors.s (revision 41) @@ -0,0 +1,262 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2024 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : stm32c031xx_Vectors.s +Purpose : Exception and interrupt vectors for stm32c031xx devices. + +Additional information: + Preprocessor Definitions + __NO_EXTERNAL_INTERRUPTS + If defined, + the vector table will contain only the internal exceptions + and interrupts. + __VECTORS_IN_RAM + If defined, + an area of RAM, large enough to store the vector table, + will be reserved. + + __OPTIMIZATION_SMALL + If defined, + all weak definitions of interrupt handlers will share the + same implementation. + If not defined, + all weak definitions of interrupt handlers will be defined + with their own implementation. +*/ + .syntax unified + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ + +// +// Directly place a vector (word) in the vector table +// +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// +// Declare an exception handler with a weak definition +// +.macro EXC_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// +// Declare an interrupt handler with a weak definition +// +.macro ISR_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern __stack_end__ + .extern Reset_Handler + .extern HardFault_Handler + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* Setup of the vector table and weak definition of interrupt handlers +* +*/ + .section .vectors, "ax" + .code 16 + .balign 256 + .global _vectors +_vectors: + // + // Internal exceptions and interrupts + // + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + VECTOR HardFault_Handler +#ifdef __ARM_ARCH_6M__ + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED +#else + EXC_HANDLER MemManage_Handler + EXC_HANDLER BusFault_Handler + EXC_HANDLER UsageFault_Handler +#endif + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER SVC_Handler +#ifdef __ARM_ARCH_6M__ + ISR_RESERVED +#else + EXC_HANDLER DebugMon_Handler +#endif + ISR_RESERVED + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + // + // External interrupts + // +#ifndef __NO_EXTERNAL_INTERRUPTS + ISR_HANDLER WWDG_IRQHandler + ISR_RESERVED + ISR_HANDLER RTC_IRQHandler + ISR_HANDLER FLASH_IRQHandler + ISR_HANDLER RCC_IRQHandler + ISR_HANDLER EXTI0_1_IRQHandler + ISR_HANDLER EXTI2_3_IRQHandler + ISR_HANDLER EXTI4_15_IRQHandler + ISR_RESERVED + ISR_HANDLER DMA1_Channel1_IRQHandler + ISR_HANDLER DMA1_Channel2_3_IRQHandler + ISR_HANDLER DMAMUX1_IRQHandler + ISR_HANDLER ADC1_IRQHandler + ISR_HANDLER TIM1_BRK_UP_TRG_COM_IRQHandler + ISR_HANDLER TIM1_CC_IRQHandler + ISR_RESERVED + ISR_HANDLER TIM3_IRQHandler + ISR_RESERVED + ISR_RESERVED + ISR_HANDLER TIM14_IRQHandler + ISR_RESERVED + ISR_HANDLER TIM16_IRQHandler + ISR_HANDLER TIM17_IRQHandler + ISR_HANDLER I2C1_IRQHandler + ISR_RESERVED + ISR_HANDLER SPI1_IRQHandler + ISR_RESERVED + ISR_HANDLER USART1_IRQHandler + ISR_HANDLER USART2_IRQHandler +#endif + // + .section .vectors, "ax" +_vectors_end: + +#ifdef __VECTORS_IN_RAM + // + // Reserve space with the size of the vector table + // in the designated RAM section. + // + .section .vectors_ram, "ax" + .balign 256 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop + + +/*************************** End of file ****************************/ Index: /trunk/firmware_v3/SES/STM32C0xx_Flash.icf =================================================================== --- /trunk/firmware_v3/SES/STM32C0xx_Flash.icf (revision 41) +++ /trunk/firmware_v3/SES/STM32C0xx_Flash.icf (revision 41) @@ -0,0 +1,133 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2024 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32C0xx_Flash.icf +Purpose : STM32C0xx linker script for application placement in Flash, + for use with the SEGGER Linker. +Maps : STM32C011D6Yx, STM32C011F4Px, STM32C011F4Ux, STM32C011F6Px, + STM32C011F6Ux, STM32C011J4Mx, STM32C011J6Mx, STM32C031C4Tx, + STM32C031C4Ux, STM32C031C6Tx, STM32C031C6Ux, STM32C031F4Px, + STM32C031F6Px, STM32C031G4Ux, STM32C031G6Ux, STM32C031K4Tx, + STM32C031K4Ux, STM32C031K6Tx, STM32C031K6Ux +Literature: + [1] SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html) + [2] SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files) +*/ + +define memory with size = 4G; + +// +// Combined regions per memory type +// +define region FLASH = FLASH1; +define region RAM = RAM1; + +// +// Block definitions +// +define block vectors { section .vectors }; // Vector table section +define block vectors_ram { section .vectors_ram }; // Vector table section +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block exidx { section .ARM.exidx, section .ARM.exidx.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with auto size = __HEAPSIZE__, alignment = 8, readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, readwrite access { }; +define block stack_process with size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +// +// Explicit initialization settings for sections +// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits +// +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { block vectors_ram }; +initialize by copy with packing=auto { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by calling __SEGGER_STOP_X_InitLimits { section .data.stop.* }; + +#define USES_ALLOC_FUNC \ + linked symbol malloc || linked symbol aligned_alloc || \ + linked symbol calloc || linked symbol realloc + +initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap }; // Init the heap if one is required +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +//assert with warning "free() linked into application but there are no calls to an allocation function!" { +// linked symbol free => USES_ALLOC_FUNC +//}; + +assert with error "heap is too small!" { USES_ALLOC_FUNC => size of block heap >= 48 }; +assert with error "heap size not a multiple of 8!" { USES_ALLOC_FUNC => size of block heap % 8 == 0 }; +assert with error "heap not correctly aligned!" { USES_ALLOC_FUNC => start of block heap % 8 == 0 }; + +// +// Explicit placement in FLASHn +// +place in FLASH1 { section .FLASH1, section .FLASH1.* }; +// +// FLASH Placement +// +place at start of FLASH { block vectors }; // Vector table section +place in FLASH with minimum size order { block tdata_load, // Thread-local-storage load image + block exidx, // ARM exception unwinding block + block ctors, // Constructors block + block dtors, // Destructors block + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// Explicit placement in RAMn +// +place in RAM1 { section .RAM1, section .RAM1.* }; +// +// RAM Placement +// +place at start of RAM { block vectors_ram }; +place in RAM { section .fast, section .fast.* }; // "ramfunc" section +place in RAM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack }; // Stack reserved block at the end Index: /trunk/firmware_v3/SES/inc/button.h =================================================================== --- /trunk/firmware_v3/SES/inc/button.h (revision 41) +++ /trunk/firmware_v3/SES/inc/button.h (revision 41) @@ -0,0 +1,20 @@ +#ifndef __BUTTON_H +#define __BUTTON_H + + + + +typedef enum BUTTON_State_enum +{ + BUTTON_OFF, + BUTTON_AUTO, + BUTTON_MANUAL_ON +} button_state_t; + + +button_state_t BUTTON_Exec(void); +button_state_t BUTTON_GetMode(void); +void BUTTON_SetModeOff(void); +void BUTTON_SetModeAuto(void); + +#endif Index: /trunk/firmware_v3/SES/inc/buzzer.h =================================================================== --- /trunk/firmware_v3/SES/inc/buzzer.h (revision 41) +++ /trunk/firmware_v3/SES/inc/buzzer.h (revision 41) @@ -0,0 +1,11 @@ +#ifndef __BUZZER_H +#define __BUZZER_H + + +void BUZZER_Exec(void); +void BUZZER_Beep(unsigned int time); +void BUZZER_Alarm_Start(unsigned int on, unsigned int off ); +void BUZZER_Alarm_Stop(void); + + +#endif Index: /trunk/firmware_v3/SES/inc/chip_temperature.h =================================================================== --- /trunk/firmware_v3/SES/inc/chip_temperature.h (revision 41) +++ /trunk/firmware_v3/SES/inc/chip_temperature.h (revision 41) @@ -0,0 +1,38 @@ +/****************************************************************************** +* +* @file chipTemperature.h +* @author ECS, Joseph Zimmer +* @version V1.0.0 +* @date 24-04-2019 +* @brief +* +******************************************************************************/ +#ifndef __CHIP_TEMPERATURE_H +#define __CHIP_TEMPERATURE_H + +//--- INCLUDEs ----------------------------------------------------------------- +#include "main.h" +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- + +/* +* @brief +* @param kein +* @retval kein +*/ +void CHIP_TEMPERATURE_Calibration(void); + +/* +* @brief +* @param kein +* @retval kein +*/ +void CHIP_TEMPERATURE_Exec(uint32_t adcValue); + +int CHIP_TEMPERATURE_GetTemp(void); +#endif // !__CHIP_TEMPERATURE_H Index: /trunk/firmware_v3/SES/inc/doku.h =================================================================== --- /trunk/firmware_v3/SES/inc/doku.h (revision 41) +++ /trunk/firmware_v3/SES/inc/doku.h (revision 41) @@ -0,0 +1,3 @@ +//entfernt +//$(ProjectDir)/CMSIS_5/CMSIS/Core/Include +//$(ProjectDir)/STM32C0xx/Device/Include Index: /trunk/firmware_v3/SES/inc/eeprom.h =================================================================== --- /trunk/firmware_v3/SES/inc/eeprom.h (revision 41) +++ /trunk/firmware_v3/SES/inc/eeprom.h (revision 41) @@ -0,0 +1,82 @@ +#include "stm32c0xx_hal.h" +#include +#include + +/** + * @file eeprom_emulation.h + * @brief Einfache EEPROM-Emulation für STM32C031 (Double-Word Schreibzugriff) + * @note Nutzt die HAL-Library für Flash-Operationen. + */ + +#ifndef EEPROM_EMULATION_H +#define EEPROM_EMULATION_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32c0xx_hal.h" +#include + +/* --- KONFIGURATION --- */ + +/** * @brief Flash-Adresse für die Emulation. + * Für STM32C031 mit 32KB Flash ist 0x08007800 der Start der letzten Page (Page 15). + * WICHTIG: Sicherstellen, dass der Programmcode diese Adresse nicht erreicht! + */ + +#define MY_EEPROM_FLASH_ADDR ((uint32_t)0x08007800) + + +/** @brief Die entsprechende Page-Nummer zur Adresse (für das Löschen benötigt) */ +#define MY_EEPROM_PAGE 15 + +#define FLASH_PAGE_SIZE_C0 2048 // 2 KB Page Size für STM32C0 + +#define FIRST_START_ID 2 + +/* --- FUNKTIONEN --- */ + +/** + * @brief Liest eine Datenstruktur direkt aus dem Flash-Speicher. + * * @param data_ptr Zeiger auf die Ziel-Struktur im RAM (z.B. &myConfig). + * @param size Größe der Struktur in Bytes (sizeof(myConfig)). + */ +void EEPROM_Read(void* data_ptr, size_t size); + +/** + * @brief Speichert eine Datenstruktur im Flash-Speicher. + * * Diese Funktion prüft zuerst, ob sich die Daten im Vergleich zum Flash + * geändert haben. Falls ja, wird die gesamte Flash-Page gelöscht und + * die Struktur neu geschrieben (Double-Word Alignment wird automatisch gehandhabt). + * * @param data_ptr Zeiger auf die zu speichernde Struktur im RAM. + * @param size Größe der Struktur in Bytes. + * @return HAL_StatusTypeDef HAL_OK bei Erfolg, ansonsten Fehlercode. + */ +HAL_StatusTypeDef EEPROM_Write(void* data_ptr, size_t size); + + + +void EEPROM_WriteDefaults(void); +void EEPROM_ReadDeviceParameter(void); +uint16_t EEPROM_ReadFirstStart(void); +void EEPROM_StoreConfig(bool writeSN); + +typedef struct __attribute__((packed)) +{ + uint32_t sn; + uint32_t baudrate; // 8-9 Die Modbus Baudrate (default 19200 Bit/s). Gltig im Bereich von 50 Bit/s bis 1000 000 Bit/s + uint16_t parityMode; // 10 UART Parity Mode (default EVEN) mgliche Werte 0=EVEN, 1=ODD, 2=NONE + uint16_t stopBit; // 11 UART Stop Bit Reserviert, Aktuell automatisch selektiert nach Modbus standart Bei Parity EVEN oder ODD 1, bei NONE werden 2 stopbits genutzt + uint16_t slave_address; // 12 Modbus Slave Adresse (default 1) mgliche Werte von 1 bis 247 + uint16_t first_start_id; + +} flash_device_parameter_t ; + + + +#ifdef __cplusplus +} +#endif + +#endif /* EEPROM_EMULATION_H */ Index: /trunk/firmware_v3/SES/inc/fan.h =================================================================== --- /trunk/firmware_v3/SES/inc/fan.h (revision 41) +++ /trunk/firmware_v3/SES/inc/fan.h (revision 41) @@ -0,0 +1,12 @@ +#ifndef __FAN_H +#define __FAN_H + + + + +void FAN_SetSpeed(unsigned speed); +unsigned FAN_GetLastSpeed(void); + + +#endif + Index: /trunk/firmware_v3/SES/inc/leds.h =================================================================== --- /trunk/firmware_v3/SES/inc/leds.h (revision 41) +++ /trunk/firmware_v3/SES/inc/leds.h (revision 41) @@ -0,0 +1,21 @@ +#ifndef __LEDS_H +#define __LEDS_H + + + +void LEDS_Exec(void); +void LEDS_GN_On(void); +void LEDS_GN_Off(void); +void LEDS_GN_Flash(unsigned int time); +void LEDS_GN_Blink_Start(unsigned int on, unsigned int off ); + + +void LEDS_RT_On(void); +void LEDS_RT_Off(void); +void LEDS_RT_Flash(unsigned int time); +void LEDS_RT_Blink_Start(unsigned int on, unsigned int off ); +void LEDS_RT_BlinkCode_Start(unsigned int blinks, unsigned int on, unsigned int off, unsigned int pause ); + + +#endif + Index: /trunk/firmware_v3/SES/inc/main.h =================================================================== --- /trunk/firmware_v3/SES/inc/main.h (revision 41) +++ /trunk/firmware_v3/SES/inc/main.h (revision 41) @@ -0,0 +1,98 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define GPIO_INPUT_MODE_B3_Pin GPIO_PIN_7 +#define GPIO_INPUT_MODE_B3_GPIO_Port GPIOB +#define GPIO_INPUT_MODE_B1_Pin GPIO_PIN_14 +#define GPIO_INPUT_MODE_B1_GPIO_Port GPIOC +#define GPIO_INPUT_MODE_B0_Pin GPIO_PIN_15 +#define GPIO_INPUT_MODE_B0_GPIO_Port GPIOC +#define GPIO_INPUT_LVP_Pin GPIO_PIN_0 +#define GPIO_INPUT_LVP_GPIO_Port GPIOA +#define GPIO_INPUT_OVP_Pin GPIO_PIN_1 +#define GPIO_INPUT_OVP_GPIO_Port GPIOA +#define GPIO_INPUT_BTN_ON_Pin GPIO_PIN_2 +#define GPIO_INPUT_BTN_ON_GPIO_Port GPIOA +#define GPIO_INPUT_BTN_OFF_Pin GPIO_PIN_3 +#define GPIO_INPUT_BTN_OFF_GPIO_Port GPIOA +#define GPIO_OUTPUT_LED_ON_Pin GPIO_PIN_4 +#define GPIO_OUTPUT_LED_ON_GPIO_Port GPIOA +#define GPIO_OUTPUT_LED_ERROR_Pin GPIO_PIN_5 +#define GPIO_OUTPUT_LED_ERROR_GPIO_Port GPIOA +#define GPIO_INPUT_FAULT_Pin GPIO_PIN_6 +#define GPIO_INPUT_FAULT_GPIO_Port GPIOA +#define GPIO_OUTPUT_RELAIS_SET_Pin GPIO_PIN_7 +#define GPIO_OUTPUT_RELAIS_SET_GPIO_Port GPIOA +#define GPIO_OUTPUT_RELAIS_RESET_Pin GPIO_PIN_8 +#define GPIO_OUTPUT_RELAIS_RESET_GPIO_Port GPIOA +#define GPIO_OUTPUT_BUZZER_Pin GPIO_PIN_11 +#define GPIO_OUTPUT_BUZZER_GPIO_Port GPIOA +#define GPIO_INPUT_BMS_Pin GPIO_PIN_12 +#define GPIO_INPUT_BMS_GPIO_Port GPIOA +#define GPIO_INPUT_MODE_B2_Pin GPIO_PIN_6 +#define GPIO_INPUT_MODE_B2_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ Index: /trunk/firmware_v3/SES/inc/modbus.h =================================================================== --- /trunk/firmware_v3/SES/inc/modbus.h (revision 41) +++ /trunk/firmware_v3/SES/inc/modbus.h (revision 41) @@ -0,0 +1,155 @@ +/* + * modbus.h + * + * Created: 03.09.2012 08:39:40 + * Author: Falko + */ + + +#ifndef MODBUS_H_ +#define MODBUS_H_ + + #if MODBUS_SUPPORT == TRUE + + #include "stdint.h" + #include "stdbool.h" + #include "main.h" + #include "sysdata.h" + + //! brief Anzahl der Startbits, nach Modbus Spezifikation immer 1, stop bits werden aus den Einstellungen geladen + #define NUMBER_OF_STARTBITS 1U + + //! brief Anzahl der Datenbits, nach Modbus Spezifikation immer 8 + #define NUMBER_OF_DATABITS 8U + + //! brief Max Timeput zwischen zwei gesendeten char + #define TIMEOUT_BETWEEN_CHARACTERS 1.5 + + //! brief Timeput bei dem fertig gesendetes Frame erkannt wird + #define TIMEOUT_FRAME_COMPLETE 3.5 + + //! define der Größe der Ein- und Ausgangsbuffer + #define RXBUFFERSIZE 256 + #define TXBUFFERSIZE 256 + + #define FORWARD_DATA TRUE + #define SEND_TO_LOKALBUS 1 + #define RESPOND_TO_QUERY 2 + + #define MAX_ADRESS ((sizeof(sys_data_struct_t) / 2)-1) + + #define MODBUS_UART_PARITY_EVEN 0 + #define MODBUS_UART_PARITY_ODD 1 + #define MODBUS_UART_PARITY_NONE 2 + +// typedef union bword +// { +// uint16_t w; +// int16_t sw; +// uint8_t lb; +// int8_t slb; +// uint8_t b[2]; +// int8_t sb[2]; +// } +// bword_t; + + typedef enum mb_error_codes_enum + { + MB_ERROR_NOTHING = 0, + MB_ERROR_TIMEOUT = 1, + MB_ERROR_CRC = 2, + MB_ERROR_SLAVE_ADRESS = 3, + MB_ERROR_FUNCTION_CODE = 4, + MB_ERROR_BYTE_COUNT = 5, + MB_ERROR_START_ADRESS = 6, + MB_ERROR_UART_PE = 7, //Parity + MB_ERROR_UART_NE = 8, //Noise + MB_ERROR_UART_FE = 9, //Frame + MB_ERROR_UART_ORE = 10, //Overrun + } + mb_error_codes_t; + + + + typedef enum + { + MB_QUERY_NOTHING, + MB_QUERY_READ_IDENT, + MB_QUERY_READ_DATA, + MB_QUERY_READ_LIPRO_DATA, + MB_QUERY_WRITE_LIPRO_BALANCER_VOLTAGE, + MB_QUERY_WRITE_BUTTONS, + MB_QUERY_GSM_GATEWAY, + MB_QUERY_REMOTEBUS_GATEWAY, + MB_QUERY_WRITE_TO_GC, + MB_QUERY_SEND_DEVICE_ADDRESS, + MB_QUERY_SEND_SAVE_COMMAND, + MB_QUERY_GATEWAY, + MB_QUERY_SEND_DATA + } + mb_status_t; + + + typedef struct + { + //TIM_HandleTypeDef * timer; // Timer config + //TIM_OC_InitTypeDef * timerOcConfig; // Zeiger auf TimerInit Struktur + UART_HandleTypeDef * uart; // Zeiger auf das Uart Modul + GPIO_TypeDef * driverEnableGPIO; // Zuständiger einschalt Port + uint16_t driverEnableGPIOPin; // Zuständiger einschalt Pin + uint32_t mb_t15_total_timer_ticks; // max timeout zwischen einzelnen char + uint32_t mb_t35_total_timer_ticks; // timeout frame complete + volatile bool mb_rx_frame_complete; // frame complete ja/nein + uint32_t response_timeout_counter; // antwort Timeout + // QUERY (Anfrage): + uint8_t last_query_slave_adress; // zugehörige Slave Andresse + uint8_t last_query_function_code; // function Code + bword_t last_query_start_adress; // start Adresse + bword_t last_query_number_of_register; // Anzahl der Register + bool last_query_timeout; // Timeout + bword_t last_query_tcp_id; // stack ID + mb_status_t current_query; // Zeiger auf Statusstruktur + uint8_t rx_buffer[RXBUFFERSIZE]; // Bufferarray Empfangen + uint8_t tx_buffer[TXBUFFERSIZE]; // Bufferarray Senden + uint32_t rx_head; // + uint32_t tx_head; // + volatile bool setTxLed; // status Led + volatile bool setRxLed; // status Led + } + modbus_t; + + + + //Public Functions Modbus + + // Timer Interrupt erkennt Fehler bei Framekomplettierung + void mbTimerIsr (modbus_t * mb_data); + // Initialiserung des Moduls muss mit den passenden Parametern gefüllt werden + void mbInit(modbus_t * mb_data, uint32_t baudrate, uint32_t parityMode, uint16_t stopBits, UART_HandleTypeDef * usart); + // überprüft ob ein Frame komplett ist + bool mbGetFrameComplete (modbus_t * mb_data); + + void mbClearRxFrame (modbus_t * mb_data); + // handelt den Interrupt + void mbUartIsr (modbus_t* mb_data); + + + //Public Fuctions Modbus SLAVE + + // Umgang mit ankommenden Anfragen und Verarbeitung dieser + void mbSlaveProcessRtuQuery (modbus_t * mb_data); + // Bedeutung der Anfrage und wie mit dieser umgegangen werden soll + uint32_t mbSlaveCheckModbusRtuQuery (modbus_t * mb_data); + // Verarbeite eine Anfrage + uint32_t mbSlaveProcessPdu( uint8_t* response_string, uint8_t * msg, uint32_t tx_position, uint8_t deviceID); + + //Public Fuctions Modbus MASTER + void mbMasterStartRtuReadHoldingRegister (uint8_t slave_adress, uint16_t start_adress, uint16_t number_of_registers, modbus_t * mb_data); + bool mbMasterGetTimeout (modbus_t * mb_data); + void mbMasterCheckResponseTimeout (modbus_t * mb_data); + mb_error_codes_t mbMasterCheckReadMultipleRegisterResponse (modbus_t * mb_data) ; + mb_error_codes_t check_write_multiple_register_response (modbus_t * mb_data) ; + void mb_start_rtu_write_multiple_register (uint8_t slave_adress, uint16_t adress, uint16_t * values, uint8_t number_of_registers, modbus_t * mb_data); + void MODBUS_UART_IRQHandler(UART_HandleTypeDef *huart); + #endif +#endif /* MODBUS_H_ */ Index: /trunk/firmware_v3/SES/inc/mode_lvp.h =================================================================== --- /trunk/firmware_v3/SES/inc/mode_lvp.h (revision 41) +++ /trunk/firmware_v3/SES/inc/mode_lvp.h (revision 41) @@ -0,0 +1,9 @@ +#ifndef __MODE_LVP_H +#define __MODE_LVP_H + +void MODE_LVP_Exec(void); + + +#endif + + Index: /trunk/firmware_v3/SES/inc/mode_lvp_ovp.h =================================================================== --- /trunk/firmware_v3/SES/inc/mode_lvp_ovp.h (revision 41) +++ /trunk/firmware_v3/SES/inc/mode_lvp_ovp.h (revision 41) @@ -0,0 +1,9 @@ +#ifndef __MODE_LVP_OVP_H +#define __MODE_LVP_OVP_H + +void MODE_LVP_OVP_Exec(void); + + +#endif + + Index: /trunk/firmware_v3/SES/inc/mode_mainswitch.h =================================================================== --- /trunk/firmware_v3/SES/inc/mode_mainswitch.h (revision 41) +++ /trunk/firmware_v3/SES/inc/mode_mainswitch.h (revision 41) @@ -0,0 +1,10 @@ +#ifndef __MODE_MAINSWITCH_H +#define __MODE_MAINSWITCH_H + + +void MODE_MAINSWITCH_Exec(void); + + +#endif + + Index: /trunk/firmware_v3/SES/inc/mode_ovp.h =================================================================== --- /trunk/firmware_v3/SES/inc/mode_ovp.h (revision 41) +++ /trunk/firmware_v3/SES/inc/mode_ovp.h (revision 41) @@ -0,0 +1,9 @@ +#ifndef __MODE_OVP_H +#define __MODE_OVP_H + +void MODE_OVP_Exec(void); + + +#endif + + Index: /trunk/firmware_v3/SES/inc/mode_secondaryprotection.h =================================================================== --- /trunk/firmware_v3/SES/inc/mode_secondaryprotection.h (revision 41) +++ /trunk/firmware_v3/SES/inc/mode_secondaryprotection.h (revision 41) @@ -0,0 +1,9 @@ +#ifndef __MODE_SECONDARYPROTECTION_H +#define __MODE_SECONDARYPROTECTION_H + +void MODE_SECONDARYPROTECTION_Exec(int am); + + +#endif + + Index: /trunk/firmware_v3/SES/inc/mode_secondaryprotection_plus.h =================================================================== --- /trunk/firmware_v3/SES/inc/mode_secondaryprotection_plus.h (revision 41) +++ /trunk/firmware_v3/SES/inc/mode_secondaryprotection_plus.h (revision 41) @@ -0,0 +1,9 @@ +#ifndef __MODE_SECONDARYPROTECTION_PLUS_H +#define __MODE_SECONDARYPROTECTION_PLUS_H + +void MODE_SECONDARYPROTECTION_PLUS_Exec(int am); + + +#endif + + Index: /trunk/firmware_v3/SES/inc/modeswitch.h =================================================================== --- /trunk/firmware_v3/SES/inc/modeswitch.h (revision 41) +++ /trunk/firmware_v3/SES/inc/modeswitch.h (revision 41) @@ -0,0 +1,29 @@ +#ifndef __MODESWITCH_H +#define __MODESWITCH_H + + + + +typedef enum MODESWITCH_mode_enum +{ + MODE_MAINSWITCH = 0, + MODE_MAINSWITCH_SECONDARYPROTECTION = 1, + MODE_MAINSWITCH_SECONDARYPROTECTION_PLUS = 2, + MODE_MAINSWITCH_SECONDARYPROTECTION_AUTO_RETRY = 3, + MODE_MAINSWITCH_SECONDARYPROTECTION_PLUS_AUTO_RETRY = 4, + MODE_MAINSWITCH_LVP_OVP = 5, + MODE_MAINSWITCH_LVP = 6, + MODE_MAINSWITCH_OVP = 7, + +} MODESWITCH_mode_t; + + +MODESWITCH_mode_t MODESWITCH_ReadMode(void); +MODESWITCH_mode_t MODESWITCH_GetMode(void); + + + + + + +#endif Index: /trunk/firmware_v3/SES/inc/relais.h =================================================================== --- /trunk/firmware_v3/SES/inc/relais.h (revision 41) +++ /trunk/firmware_v3/SES/inc/relais.h (revision 41) @@ -0,0 +1,18 @@ +#ifndef __RELAIS_H +#define __RELAIS_H + + +#include + +void RELAIS_Exec(uint32_t adcValue); +void RELAIS_SetPuls(void); +void RELAIS_ResetPuls(void); +unsigned int RELAIS_GetState(void); +uint16_t RELAIS_GetTemp(void); + + + +#endif + + + Index: /trunk/firmware_v3/SES/inc/sysdata.h =================================================================== --- /trunk/firmware_v3/SES/inc/sysdata.h (revision 41) +++ /trunk/firmware_v3/SES/inc/sysdata.h (revision 41) @@ -0,0 +1,110 @@ +/*! + * \file : sysdata.h + * \brief : Header for sysdata.c file. + * This file contains the common defines of the application. + * + */ + +#ifndef __SYS_DATA_H +#define __SYS_DATA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdint.h" + +#define CONCAT(a, b) CONCAT_INNER(a, b) // These three macros +#define CONCAT_INNER(a, b) a ## b // generate unique variables +#define UNIQUE_NAME(base) CONCAT(base, __COUNTER__) // according to template "baseX", like "base1", "base2" and etc. + +#define SAMPLE_ARRAY_SIZE 64 + +//------------------------------------------------------------------------------ + +typedef union +{ + uint16_t w; + int16_t sw; + uint8_t b[2]; + int8_t sb[2]; +} bword_t; + +//------------------------------------------------------------------------------ +// This structure must be aligned to 4-byte address +volatile typedef struct +{ + // Device spezifisch / Einstellungsbereich + uint16_t device_type; // 0 ECS interne Gertetyp Kennung (IHP 500 -> daher wird angedacht die Gerätekennung 500 zu nehmen) + uint16_t UNIQUE_NAME(reserved); // 1 Reserviert wg Alignement + uint32_t sn; // 2-3 Seriennummer Teil 1 -> wird bei der Produktion geschrieben + + uint16_t fw_revision_major; // 4 Firmware Revision Major -> wird bei einer neuen Gertegeneration hochgezhlt + uint16_t fw_revision_minor; // 5 Firmware Revision Minor -> wird hochegezhlt, wenn nderungen in der Firmware auch nderungen in der Bedienungsanleitung zur Folge haben + + uint16_t fw_revision_revision; // 6 Firmware Revision Revision -> wird bei jeder nderung der Firmware hochgezhlt + uint16_t UNIQUE_NAME(reserved); // 7 Reserviert wg Alignement + + uint32_t baudrate; // 8-9 Die Modbus Baudrate (default 19200 Bit/s). Gltig im Bereich von 50 Bit/s bis 1000 000 Bit/s + + uint16_t parityMode; // 10 UART Parity Mode (default EVEN) mgliche Werte 0=EVEN, 1=ODD, 2=NONE + uint16_t stopBit; // 11 UART Stop Bit Reserviert, Aktuell automatisch selektiert nach Modbus standart Bei Parity EVEN oder ODD 1, bei NONE werden 2 stopbits genutzt + + uint16_t slave_address; // 12 Modbus Slave Adresse (default 1) mgliche Werte von 1 bis 247 + uint16_t command; // 13 Kommando Word, das Schreiben bestimmter Werte in dieses Register fhrt bestimmte Aktionen aus + + uint16_t res1[6]; + + uint16_t operatingMode; + + uint16_t reserved[79]; + + + +} device_parameter_t; + +//------------------------------------------------------------------------------ +// This structure must be aligned to 4-byte address +volatile typedef struct +{ /*offset 0*/ + /* 2 of 8 */ int16_t chipTemp; // 100 + /* 4 of 8 */ int16_t relaisTemp; // 101 + /* 6 of 8 */ uint16_t voltage_input; // 102 + /* 8 of 8 */ uint16_t voltage_output; // 103 + /* 2 of 8 */ int16_t voltage_relais; // 104 + /* 2 of 8 */ int16_t fan_pwm; // 105 + /* 2 of 8 */ int16_t fan_rpm; // 106 + /* 2 of 8 */ int16_t ovp_state; // 107 + /* 2 of 8 */ int16_t lvp_state; // 108 + /* 2 of 8 */ int16_t fault_state; // 109 + /* 2 of 8 */ int16_t relais_state; // 115 +} device_values_t; + +//------------------------------------------------------------------------------ + +typedef struct +{ + device_parameter_t parameter; // 0-99 + device_values_t values; // 100 +} sys_data_struct_t; + +//------------------------------------------------------------------------------ +typedef volatile union +{ + sys_data_struct_t s; + bword_t mb[sizeof(sys_data_struct_t) / 2]; +} sys_data_t; + +//------------------------------------------------------------------------------ + +extern sys_data_t sys_data; + +//------------------------------------------------------------------------------ + +void SYS_DATA_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYS_DATA_H Index: /trunk/firmware_v3/SES/inc/voltage_meas.h =================================================================== --- /trunk/firmware_v3/SES/inc/voltage_meas.h (revision 41) +++ /trunk/firmware_v3/SES/inc/voltage_meas.h (revision 41) @@ -0,0 +1,16 @@ +#ifndef __VOLTAGE_MEAS_H +#define __VOLTAGE_MEAS_H + +#include "main.h" + +uint32_t VOLTAGE_MEAS_GetUin(void); +uint32_t VOLTAGE_MEAS_GetUout(void); + +void VOLTAGE_MEAS_Exec(uint32_t adcValUin, uint32_t adcValUout); + +uint32_t VOLTAGE_MEAS_GetLimitAlarm(void); +void VOLTAGE_MEAS_ResetCounter(void); + +#endif + + Index: /trunk/firmware_v3/SES/src/button.c =================================================================== --- /trunk/firmware_v3/SES/src/button.c (revision 41) +++ /trunk/firmware_v3/SES/src/button.c (revision 41) @@ -0,0 +1,89 @@ +#include +#include "button.h" +#include "main.h" + +#define LONG_PRESS_TIME 5000 +#define MIN_PRESS_TIME 10 + +button_state_t buttonState; +uint32_t longPressCounterButtonOn; +uint32_t longPressCounterButtonOff; + + +// Diese funktion muss regelmäßig aufgerufen werden um die Taster abzufragen. +// 1ms +button_state_t BUTTON_Exec(void) +{ + + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_SET) + { + //Taste On wird gedrückt + longPressCounterButtonOn++; + } + + + if (longPressCounterButtonOn > LONG_PRESS_TIME) + { + + if (buttonState != BUTTON_MANUAL_ON) + { + printf("BUTTON: Auto Mode Manual On\n"); + buttonState = BUTTON_MANUAL_ON; + } + } + else if ( (longPressCounterButtonOn > MIN_PRESS_TIME) && (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET)) + { + //Taste On wurde for 10m gesdrückt und losgelassen + if (buttonState != BUTTON_AUTO) + { + printf("BUTTON: Auto Mode\n"); + buttonState = BUTTON_AUTO; + } + } + + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET) + { + longPressCounterButtonOn = 0; + } + + + // ------ Taste OFF ----- + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_OFF_GPIO_Port, GPIO_INPUT_BTN_OFF_Pin) == GPIO_PIN_SET) + { + //Taste Off wird gedrückt + longPressCounterButtonOff++; + if (longPressCounterButtonOff > MIN_PRESS_TIME) + { + if (buttonState != BUTTON_OFF) + { + printf("BUTTON: Off Mode\n"); + buttonState = BUTTON_OFF; + } + } + } + else + { + longPressCounterButtonOff = 0; + } + + return buttonState; + +} + + +button_state_t BUTTON_GetMode(void) +{ + return buttonState; +} + +void BUTTON_SetModeOff(void) +{ + buttonState = BUTTON_OFF; +} + +void BUTTON_SetModeAuto(void) +{ + buttonState = BUTTON_AUTO; +} Index: /trunk/firmware_v3/SES/src/buzzer.c =================================================================== --- /trunk/firmware_v3/SES/src/buzzer.c (revision 41) +++ /trunk/firmware_v3/SES/src/buzzer.c (revision 41) @@ -0,0 +1,64 @@ +#include "main.h" +#include "buzzer.h" + +unsigned int onTimeCounter; +unsigned int offTimeCounter; +unsigned int onTime; +unsigned int offTime; +unsigned int alarmMode; + + + +void BUZZER_Exec(void) +{ + + if (onTimeCounter > 0) + { + onTimeCounter--; + if (onTimeCounter == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + + if (alarmMode == 1) offTimeCounter = offTime; + } + } + + if (offTimeCounter > 0) + { + offTimeCounter--; + if (offTimeCounter == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = onTime; + } + } +} + + + +void BUZZER_Beep(unsigned int time) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = time; + +} + +void BUZZER_Alarm_Start(unsigned int on, unsigned int off ) +{ + onTime = on; + offTime = off; + alarmMode = 1; + + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = on; + +} + +void BUZZER_Alarm_Stop(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + alarmMode = 0; + offTimeCounter = 0; + onTimeCounter = 0; + +} Index: /trunk/firmware_v3/SES/src/chip_temperature.c =================================================================== --- /trunk/firmware_v3/SES/src/chip_temperature.c (revision 41) +++ /trunk/firmware_v3/SES/src/chip_temperature.c (revision 41) @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* @file chipTemperature.c +* @author ECS, Joseph Zimmer +* @version V1.0.0 +* @date 24-04-2019 +* @brief +* +******************************************************************************/ + +// --- INCLUDES ----------------------------------------------------------------- +#include +//#include +#include "chip_temperature.h" + +// --- EXTERNE VARIABLEN -------------------------------------------------------- + +// --- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- + +// --- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +// --- DEFINITIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +// --- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ +uint32_t calTemperatureSensor30Value; // Kalibrierungswert für den Temperatursensor auf dem STM32G0 (Werksmäßig im SCB Bereich gespeichert wird beim Programmstart ausgelesen) + // Daten Temperaturanzeige µProzessor +int32_t temp; +// --- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- + +void calc_temp_compensation(void); + + +// --- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- + +/* +* @brief +* @param kein +* @retval kein +*/ + +// --- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void CHIP_TEMPERATURE_Calibration(void) +{ + uint16_t * pCalibrationData; + float calibrationData30; + float calibrationData130; + + // lade Temperatur Kalibrierungswert (Wert bei 30°C) + pCalibrationData = (uint16_t *)TEMPSENSOR_CAL1_ADDR; + calibrationData30 = * pCalibrationData; + + //Berechnung Spannung in mV bei CAL Punk 30°C + //Kalbibrierung wurde mit 12 Bit und 3000mV Vref durchgeführt + calibrationData30 = calibrationData30 / 4096; + calTemperatureSensor30Value = calibrationData30 * 3000 ; // jetzt haben wir die Kalibrierungsspannung in mVolt bei 30°C; +} + +void CHIP_TEMPERATURE_Exec(uint32_t adcValue) +{ + + //Aktuelle Spannung am Temp Sensor + temp = (3300 * (uint32_t)adcValue) / 65536; + + + temp = temp - (calTemperatureSensor30Value); + + temp = temp / 2.530; //2,53mV/°C + temp = temp + 25; //30000 da Erste Kalibrierpunkt bei 25°C --> 25 + +} + +int CHIP_TEMPERATURE_GetTemp(void) +{ + return temp; +} + + +//------------------------------------------------------------------------------ + + + Index: /trunk/firmware_v3/SES/src/eeprom.c =================================================================== --- /trunk/firmware_v3/SES/src/eeprom.c (revision 41) +++ /trunk/firmware_v3/SES/src/eeprom.c (revision 41) @@ -0,0 +1,138 @@ +#include "eeprom.h" +#include +#include "modbus.h" +HAL_StatusTypeDef EEPROM_ErasePage(void); +flash_device_parameter_t flash_device_parameter_default; + + +/** + * @brief Liest die Struktur aus dem Flash in den RAM + * @param data_ptr Zeiger auf die Ziel-Struktur im RAM + * @param size Größe der Struktur (sizeof) + */ +void EEPROM_Read(void* data_ptr, size_t size) { + // Flash ist Memory-Mapped, wir können direkt mit memcpy lesen + memcpy(data_ptr, (void*)MY_EEPROM_FLASH_ADDR, size); +} + +/** + * @brief Hilfsfunktion zum Löschen der Flash-Page + */ + HAL_StatusTypeDef EEPROM_ErasePage(void) { + FLASH_EraseInitTypeDef eraseInit; + uint32_t pageError = 0; + + eraseInit.TypeErase = FLASH_TYPEERASE_PAGES; + eraseInit.Page = MY_EEPROM_PAGE; + eraseInit.NbPages = 1; + return HAL_FLASHEx_Erase(&eraseInit, &pageError); +} + +/** + * @brief Speichert die Struktur im Flash (Löschen -> Schreiben) + * @return HAL_OK oder Fehlercode + */ +HAL_StatusTypeDef EEPROM_Write(void* data_ptr, size_t size) { + // 1. Check: Haben sich die Daten überhaupt geändert? (Flash-Schonung) + if (memcmp(data_ptr, (void*)MY_EEPROM_FLASH_ADDR, size) == 0) { + return HAL_OK; // Keine Änderung, kein Schreibvorgang nötig + } + + HAL_StatusTypeDef status; + uint8_t *byte_ptr = (uint8_t*)data_ptr; + uint32_t current_addr = MY_EEPROM_FLASH_ADDR; + + // 2. Flash entsperren + HAL_FLASH_Unlock(); + + // 3. Page löschen (Flash muss vor dem Schreiben 0xFF sein) + status = EEPROM_ErasePage(); + if (status != HAL_OK) { + HAL_FLASH_Lock(); + return status; + } + + // 4. In 8-Byte Blöcken schreiben (Double Word) + for (size_t i = 0; i < size; i += 8) { + uint64_t double_word = 0xFFFFFFFFFFFFFFFF; + size_t remaining = size - i; + + if (remaining >= 8) { + memcpy(&double_word, &byte_ptr[i], 8); + } else { + memcpy(&double_word, &byte_ptr[i], remaining); + } + + status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, current_addr, double_word); + if (status != HAL_OK) break; + + current_addr += 8; + } + + // 5. Flash wieder sperren + HAL_FLASH_Lock(); + return status; +} + +void EEPROM_WriteDefaults(void) +{ + + flash_device_parameter_default.baudrate = 19200; + flash_device_parameter_default.parityMode = MODBUS_UART_PARITY_EVEN; + flash_device_parameter_default.stopBit = 1; + flash_device_parameter_default.slave_address = 1; + flash_device_parameter_default.first_start_id = FIRST_START_ID; + + EEPROM_Write( (void*) &flash_device_parameter_default, sizeof(flash_device_parameter_default)); + +} + + + +uint16_t EEPROM_ReadFirstStart(void) +{ + + flash_device_parameter_t dp; + + EEPROM_Read( (void*) &dp, sizeof(dp)); + + return dp.first_start_id; + + +} + +void EEPROM_ReadDeviceParameter(void) +{ + + flash_device_parameter_t dp; + + EEPROM_Read( (void*) &dp, sizeof(dp)); + sys_data.s.parameter.sn = dp.sn; + sys_data.s.parameter.baudrate = dp.baudrate; + sys_data.s.parameter.parityMode = dp.parityMode; + sys_data.s.parameter.stopBit = dp.stopBit; + sys_data.s.parameter.slave_address = dp.slave_address; + +} + +void EEPROM_StoreConfig(bool writeSN) +{ + flash_device_parameter_t dp; + + EEPROM_Read( (void*) &dp, sizeof(dp)); + + + + dp.baudrate = sys_data.s.parameter.baudrate; + dp.parityMode = sys_data.s.parameter.parityMode; + dp.stopBit = sys_data.s.parameter.stopBit; + dp.slave_address = sys_data.s.parameter.slave_address; + + if (writeSN == true) + { + dp.sn = sys_data.s.parameter.sn; + } + + + EEPROM_Write( (void*) &dp, sizeof(dp)); +} Index: /trunk/firmware_v3/SES/src/fan.c =================================================================== --- /trunk/firmware_v3/SES/src/fan.c (revision 41) +++ /trunk/firmware_v3/SES/src/fan.c (revision 41) @@ -0,0 +1,25 @@ +#include "fan.h" +#include "tim.h" +static unsigned lastSpeed; + +void FAN_SetSpeed(unsigned speed) +{ + const unsigned MAX_RPM = 100U; // 100.0% + + if (speed > MAX_RPM) speed = MAX_RPM; + + lastSpeed = speed; + + const unsigned MAX_PWM = __HAL_TIM_GET_AUTORELOAD(&htim17) + 1U; + //printf("%u", MAX_PWM); + const unsigned newPWM = (MAX_PWM * speed/ MAX_RPM); + + __HAL_TIM_SET_COMPARE(&htim17, TIM_CHANNEL_1, newPWM); +} + +//----------------------------------------------------------------------------- + +unsigned FAN_GetLastSpeed(void) +{ + return lastSpeed; +} Index: /trunk/firmware_v3/SES/src/leds.c =================================================================== --- /trunk/firmware_v3/SES/src/leds.c (revision 41) +++ /trunk/firmware_v3/SES/src/leds.c (revision 41) @@ -0,0 +1,170 @@ +#include "main.h" +#include "leds.h" + +unsigned int onTimeCounterGN; +unsigned int offTimeCounterGN; +unsigned int onTimeGN; +unsigned int offTimeGN; +unsigned int blinkModeGN; + + +unsigned int onTimeCounterRT; +unsigned int offTimeCounterRT; +unsigned int onTimeRT; +unsigned int offTimeRT; +unsigned int blinkModeRT; +unsigned int numberOfBlinks; +unsigned int pauseTime; +unsigned int blinkCounter; + +void LEDS_Exec(void) +{ + + if (onTimeCounterGN > 0) + { + onTimeCounterGN--; + if (onTimeCounterGN == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + + if (blinkModeGN == 1) offTimeCounterGN = offTimeGN; + } + } + + if (offTimeCounterGN > 0) + { + offTimeCounterGN--; + if (offTimeCounterGN == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = onTimeGN; + } + } + + + // --- LED ROT --- + if (onTimeCounterRT > 0) + { + onTimeCounterRT--; + if (onTimeCounterRT == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + if (blinkModeRT == 1) offTimeCounterRT = offTimeRT; + + if (blinkCounter > 0) + { + blinkCounter--; + } + } + } + + + if(blinkCounter == 0) + { + //Blink code wurde angezeigt, jetzt eine lange Pause + offTimeCounterRT = pauseTime; + blinkCounter = numberOfBlinks; + } + + + if (offTimeCounterRT > 0) + { + offTimeCounterRT--; + if (offTimeCounterRT == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = onTimeRT; + } + } +} + +// --- Steuerfunktionen LED grün ------------ +void LEDS_GN_On(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + + blinkModeGN = 0; // Blinkmode zurücksetzen, falls es eingeschaltet war + onTimeCounterGN = 0; + offTimeCounterGN = 0; +} + + + +void LEDS_GN_Flash(unsigned int time) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = time; +} + +void LEDS_GN_Blink_Start(unsigned int on, unsigned int off ) +{ + onTimeGN = on; + offTimeGN = off; + blinkModeGN = 1; + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = on; +} + +void LEDS_GN_Off(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + blinkModeGN = 0; + offTimeCounterGN = 0; + onTimeCounterGN = 0; +} + + + +// --- Steuerfunktionen LED rot ------------ +void LEDS_RT_On(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + + blinkModeRT = 0; // Blinkmode zurücksetzen, falls es eingeschaltet war + onTimeCounterRT = 0; + offTimeCounterRT = 0; +} + + + +void LEDS_RT_Flash(unsigned int time) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = time; +} + +void LEDS_RT_Blink_Start(unsigned int on, unsigned int off ) +{ + onTimeRT = on; + offTimeRT = off; + blinkModeRT = 1; + pauseTime = off; + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = on; +} + + +void LEDS_RT_BlinkCode_Start(unsigned int blinks, unsigned int on, unsigned int off, unsigned int pause ) +{ + onTimeRT = on; + offTimeRT = off; + blinkModeRT = 1; + numberOfBlinks = blinks; + blinkCounter = blinks; + pauseTime = pause; + + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = on; +} + + +void LEDS_RT_Off(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + blinkModeRT = 0; + offTimeCounterRT = 0; + onTimeCounterRT = 0; +} Index: /trunk/firmware_v3/SES/src/main.c =================================================================== --- /trunk/firmware_v3/SES/src/main.c (revision 41) +++ /trunk/firmware_v3/SES/src/main.c (revision 41) @@ -0,0 +1,507 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "adc.h" +#include "dma.h" +#include "tim.h" +#include "usart.h" +#include "gpio.h" +#include "iwdg.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include "button.h" +#include "buzzer.h" +#include "relais.h" +#include "leds.h" +#include "fan.h" +#include "chip_temperature.h" +#include "modeswitch.h" +#include "mode_mainswitch.h" +#include "mode_secondaryprotection.h" +#include "mode_secondaryprotection_plus.h" +#include "mode_lvp.h" +#include "mode_ovp.h" +#include "mode_lvp_ovp.h" +#include "voltage_meas.h" +#include "modbus.h" +#include "sysdata.h" +#include "eeprom.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +int oldTimeMSTick; +int oldTimeSeconds; +int msCounter; +int silentmode = 0; +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +uint32_t bootLoaderMark __attribute__((section(".no_init"))); +static volatile uint32_t adcData[5]; +modbus_t modbusData __attribute__((section(".RAM1"))); +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); + +/* USER CODE BEGIN PFP */ +void JumpToBootloader(void); +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + if (bootLoaderMark == GOTO_SYSTEM_BOOTLOADER_MARK) + { + bootLoaderMark = 0; + JumpToBootloader(); + } + + if (FLASH->OPTR & FLASH_OPTR_nBOOT_SEL) + { + printf("setze option byte\r\n"); + + HAL_FLASH_Unlock(); + FLASH_WaitForLastOperation(1000); + HAL_FLASH_OB_Unlock(); + FLASH_WaitForLastOperation(1000); + + FLASH->OPTR &= ~FLASH_OPTR_nBOOT_SEL; + + FLASH_WaitForLastOperation(1000); + + FLASH->CR |= FLASH_CR_OPTSTRT; + + FLASH_WaitForLastOperation(1000); + + HAL_FLASH_OB_Launch(); + } + + unsigned pwm = 0U; + + + + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_ADC1_Init(); + MX_TIM16_Init(); + MX_TIM17_Init(); + MX_IWDG_Init(); + MX_USART1_UART_Init(); + /* USER CODE BEGIN 2 */ + + + //Eprom test + if (EEPROM_ReadFirstStart() == 0xff) + { + printf("Erststart erkannt, schreibe Werkseinstellung\r\n"); + EEPROM_WriteDefaults(); + } + else if(EEPROM_ReadFirstStart() != FIRST_START_ID) + { + printf("Neue Version Parameter erkannt, schreibe Werkseinstellung\r\n"); + EEPROM_WriteDefaults(); + } + else + { + printf("Konfig vorhanden\r\n"); + } + + EEPROM_ReadDeviceParameter(); + // + + SYS_DATA_Init(); + printf("debug io test...ok\r\n"); + + mbInit(&modbusData, sys_data.s.parameter.baudrate, sys_data.s.parameter.parityMode, sys_data.s.parameter.stopBit, &huart1); + + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + HAL_Delay(500); + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + + //Spannungsregler für Mosfet ein (Relais Schaltstufe) + HAL_GPIO_WritePin(GPIO_OUTPUT_10V_EN_GPIO_Port, GPIO_OUTPUT_10V_EN_Pin, GPIO_PIN_SET); + + //--- RELAIS ZURÜCKSETZEN, damit es definitiv aus ist --- + //Sicherstellen das nicht noch die Set Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_SET); + HAL_Delay(50); + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + //--- RELAIS ZURÜCKSETZEN ENDE ---- + + MODESWITCH_ReadMode(); + sys_data.s.parameter.operatingMode = MODESWITCH_GetMode(); + + CHIP_TEMPERATURE_Calibration(/*&sys_data*/); + HAL_ADCEx_Calibration_Start(&hadc1); + HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adcData, 5); + + + + extern uint32_t frequency, ic_overflows; + ic_overflows = 0U; + __HAL_TIM_SetCounter(&htim16, 0U); + + HAL_TIM_Base_Start_IT(&htim16); + HAL_TIM_IC_Start_IT(&htim16, TIM_CHANNEL_1); + int oldcaptureValue=0; + + + + + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + HAL_IWDG_Refresh(&hiwdg); + + + if (mbGetFrameComplete(&modbusData) == true) + { + if (mbSlaveCheckModbusRtuQuery(&modbusData) == RESPOND_TO_QUERY) + { + if (silentmode == 0) + { + mbSlaveProcessRtuQuery(&modbusData); + } + } + else + { + huart1.RxState = HAL_UART_STATE_BUSY_RX; + } + } + + + + + if (oldTimeMSTick != HAL_GetTick()) + { + BUTTON_Exec(); + BUZZER_Exec(); + RELAIS_Exec(adcData[0]); + LEDS_Exec(); + VOLTAGE_MEAS_Exec(adcData[1],adcData[2]); + + oldTimeMSTick = HAL_GetTick(); + msCounter++; + } + + + //Sekunden tick + if (msCounter >= 999) + { + msCounter = 0; + CHIP_TEMPERATURE_Exec(adcData[4]); + sys_data.s.values.chipTemp = CHIP_TEMPERATURE_GetTemp(); + + if ( sys_data.s.values.chipTemp > 50) + { + pwm++; + if (pwm > 100U) pwm = 100U; + + } + if (sys_data.s.values.chipTemp < 50) + { + if (pwm > 0) pwm--; + } + + FAN_SetSpeed(pwm); + + sys_data.s.values.voltage_input = VOLTAGE_MEAS_GetUin(); + sys_data.s.values.voltage_output = VOLTAGE_MEAS_GetUout(); + sys_data.s.values.voltage_relais = (int32_t) sys_data.s.values.voltage_input - (int32_t) sys_data.s.values.voltage_output ; + uint32_t rpm; + rpm = frequency / 2; + rpm = rpm * 60; + sys_data.s.values.fan_rpm = rpm; + sys_data.s.values.fan_pwm = pwm; + sys_data.s.values.lvp_state = HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin); + sys_data.s.values.ovp_state = HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin); + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + sys_data.s.values.fault_state = 1; + }else + { + sys_data.s.values.fault_state = 0; + } + + sys_data.s.values.relais_state = RELAIS_GetState(); + sys_data.s.values.relaisTemp = RELAIS_GetTemp(); + + + + + + + } //endsecond tick + + + + switch (MODESWITCH_GetMode()) + { + case MODE_MAINSWITCH: //0 + MODE_MAINSWITCH_Exec(); + break; + + case MODE_MAINSWITCH_SECONDARYPROTECTION://1 + MODE_SECONDARYPROTECTION_Exec(0); + break; + + case MODE_MAINSWITCH_SECONDARYPROTECTION_PLUS://2 + MODE_SECONDARYPROTECTION_PLUS_Exec(0); + break; + + case MODE_MAINSWITCH_SECONDARYPROTECTION_AUTO_RETRY://3 + MODE_SECONDARYPROTECTION_Exec(1); + break; + + case MODE_MAINSWITCH_SECONDARYPROTECTION_PLUS_AUTO_RETRY://4 + MODE_SECONDARYPROTECTION_PLUS_Exec(1); + break; + + case MODE_MAINSWITCH_LVP_OVP://5 + MODE_LVP_OVP_Exec(); + break; + + case MODE_MAINSWITCH_LVP://6 + MODE_LVP_Exec(); + break; + + case MODE_MAINSWITCH_OVP://7 + MODE_OVP_Exec(); + break; + + default: + printf("mode not yet implemented\n"); + } + + + if(sys_data.s.parameter.command != 0) + { + if (modbusData.current_query == MB_QUERY_NOTHING) + { + //printf("CMD = %d\n", sys_data.s.parameter.command); + switch (sys_data.s.parameter.command ) + { + case COMMAND_STORE_CONFIG: EEPROM_StoreConfig(false); break; + case COMMAND_FULL_RESTORE: EEPROM_WriteDefaults(); break; + case COMMAND_FACTORY_RESTORE: EEPROM_WriteDefaults(); break; + case COMMAND_RESTORE_LAST_SAVED_VALUES: EEPROM_ReadDeviceParameter(); break; + case COMMAND_STORE_WITH_SERIAL_NUMBER: EEPROM_StoreConfig(true); break; // Seriennummer schreiben + case COMMAND_RESTART: while(1); break; + case COMMAND_GOTO_SYS_BOOTLOADER: bootLoaderMark = GOTO_SYSTEM_BOOTLOADER_MARK; + HAL_NVIC_SystemReset(); + break; + default: printf("UNKNOWN COMMAND\n"); + } + sys_data.s.parameter.command = 0; + } + else + { + //printf("wait with execution till modbus communnikation finished\n"); + } + } + + } + + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_0); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV4; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ +void JumpToBootloader (void) +{ + typedef void (SystemBootloader)(void); +#ifdef DEBUG + printf("Cannot jump in DEBUG mode!\n"); + return; +#endif + // Disable all interrupts + __disable_irq(); + +#ifdef DEINIT_RCC + // Set the clock to the default state + HAL_RCC_DeInit(); +#endif +#ifdef DEINIT_SYSTICK + // Disable Systick timer + SysTick->CTRL = SysTick->LOAD = SysTick->VAL = 0; +#endif + // Clear Interrupt Enable Register & Interrupt Pending Register + for (int i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) + { + NVIC->ICER[i] = 0xFFFFFFFF; + NVIC->ICPR[i] = 0xFFFFFFFF; + } + + // Set up the jump to boot loader address + 4 + SystemBootloader* sb = (SystemBootloader*) (*((uint32_t *) ((SYSTEM_BOOTLOADER_START_ADDR + 4)))); + + // Set the main stack pointer to the bootloader stack + __set_MSP(*(uint32_t *)SYSTEM_BOOTLOADER_START_ADDR); + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH(); + //__HAL_RCC_SYSCFG_CLK_DISABLE(); + + // Re-enable all interrupts + __enable_irq(); + + // Call the function to jump to boot loader location + sb(); + + // Jump is done successfully + while (1) + { + // Code should never reach this loop + printf("Jump has failed!\n"); + } +} + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + printf("Wrong parameters value: file %s on line %d\r\n", file, line) ; + /* USER CODE END 6 */ + +} +#endif /* USE_FULL_ASSERT */ Index: /trunk/firmware_v3/SES/src/modbus.c =================================================================== --- /trunk/firmware_v3/SES/src/modbus.c (revision 41) +++ /trunk/firmware_v3/SES/src/modbus.c (revision 41) @@ -0,0 +1,648 @@ +/* + * modbus.c + * + * Created: 03.09.2012 08:39:20 + * Author: Falko + */ + + + +#if MODBUS_SUPPORT == TRUE + + #include "modbus.h" + //#include "stm32g4xx_hal.h" + #include "main.h" + //#include "stm32g0xx_hal_tim.h" + //#include "stm32_hal_legacy.h" + #include + // --------------------------------------------------------- + // -------------------- MODUL DEFINES ---------------------- + // --------------------------------------------------------- + + + + + #define MODBUS_BROADCAST_ADDRESS 0x00 + #define FC_READ_COILS 0x01 + #define FC_READ_HOLDING_REGISTERS 0x03 + #define FC_WRITE_SINGLE_REGISTER 0x06 + #define FC_WRITE_MULTIPLE_REGISTER 0x10 + + /* Protocol exceptions */ + #define ILLEGAL_FUNCTION 0x01 + #define ILLEGAL_DATA_ADDRESS 0x02 + #define ILLEGAL_DATA_VALUE 0x03 + #define SLAVE_DEVICE_FAILURE 0x04 + #define SERVER_FAILURE 0x04 + #define ACKNOWLEDGE 0x05 + #define SLAVE_DEVICE_BUSY 0x06 + #define SERVER_BUSY 0x06 + #define NEGATIVE_ACKNOWLEDGE 0x07 + #define MEMORY_PARITY_ERROR 0x08 + #define GATEWAY_PROBLEM_PATH 0x0A + #define GATEWAY_PROBLEM_TARGET 0x0B + + /* Local Error codes */ + #define INVALID_CRC -1 + + // Position der Daten im Rx String + #define OFFSET_SLAVE_ADRESS 0x00 + #define OFFSET_FUNCTION_CODE 0x01 + #define OFFSET_START_ADRESS_HI 0x02 + #define OFFSET_START_ADRESS_LO 0x03 + #define OFFSET_NO_OF_REGISTERS_HI 0x04 + #define OFFSET_NO_OF_REGISTERS_LO 0x05 + + #define MIN_NUMBER_OF_REGISTERS_FC3 0x01 + #define MAX_NUMBER_OF_REGISTERS_FC3 0x7D + #define MIN_NUMBER_OF_REGISTERS_FC16 0x01 + #define MAX_NUMBER_OF_REGISTERS_FC16 0x7B + + #ifdef DEBUG + #define RESPONSE_TIMEOUT 300 // * 1ms + #else + #define RESPONSE_TIMEOUT 1000 // * 1ms + #endif + + #define FAST_BAUDRATE_INTERFRAME_DELAY_us (1750UL) + // --- Externe Variablen -------------------------------------------- + extern modbus_t modbusData; + extern sys_data_t sys_data; + + + // --- Private Funktions Prototypen -------------------------------------------- + + void mbUartInit (modbus_t * mb_data,UART_HandleTypeDef * usart, uint32_t baudrate, uint32_t parityMode, uint32_t stopBits , uint32_t nrOfBitsPerChar); + uint16_t mbCrc16 (uint8_t *buf, uint32_t len); + void mbSend (modbus_t * mb_data ); + uint32_t mbSlaveReadHoldingRegisters (uint8_t * response_string, uint8_t *msg, uint32_t tx_position, uint8_t deviceID); + uint32_t mbSlaveWriteMultipleRegisters (uint8_t * response_string, uint8_t *msg, uint32_t tx_position, uint32_t deviceID); + uint32_t mbSlaveWriteSingleRegister (uint8_t * response_string,uint8_t *msg,uint32_t tx_position, uint32_t deviceID); + uint32_t mbSlaveResponseException (uint8_t* response_string, uint32_t function_code, uint32_t exception_code,uint32_t tx_position) ; +static HAL_StatusTypeDef RS485_ModbusEx_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime, uint32_t charReceiveTimeout); +static void UART_TxISR_8BIT (UART_HandleTypeDef *huart); + + // --- GEMEINSAME MODBUS FUNKTIONEN -------------------------------------------- + // Diese Funktionen werden sowohl von Modbus Master als auch Modbus Slave verwendet + + /* + * + * @brief Diese Funktion Initialisert die Modbus Datenstrukturen und die Hardware + * + * Das Modbus Modul bentigt einen UART und einen Timer pro Modbus Anschluss + * Die Funktion erfordert eine vorhandene Callback funktion namens HAL_UART_MspInit + * In dieser muss: + * - Der UART CLK eingeschaltet werden + * - Die Pins initialisert werden (Alternate Port Funktion) + * - Der NVIC Interrupt eingeschaltet werden + * @param mb_data : Datenstruktur zur Aufnahme aller Daten + * @param baudrate : Bautrate + * @param parityMode : Parity, mglich ist UART_PARITY_ODD, UART_PARITY_EVEN, UART_PARITY_NONE. Default ist lt. Modbus Standart EVEN + * @param usart : Timer Modul, z.B. USART1 + * @retval None + */ + void mbInit(modbus_t* mb_data, uint32_t baudrate, uint32_t parityMode, uint16_t stopBits, UART_HandleTypeDef* usart) + { + uint32_t numberOfBitsPerChar; + //uint32_t stopBits; + + if (stopBits < 1U || stopBits > 2U) stopBits = 1U; + + + // Berechne Anzahl der Bits per Char + numberOfBitsPerChar = NUMBER_OF_STARTBITS + NUMBER_OF_DATABITS + stopBits; + if ((parityMode == MODBUS_UART_PARITY_EVEN) || (parityMode == MODBUS_UART_PARITY_ODD)) + { + numberOfBitsPerChar +=1; + } + + mbUartInit(mb_data,usart, baudrate, parityMode, stopBits, numberOfBitsPerChar); + + // Datenstrukturen zurcksetzen + mb_data->last_query_function_code = 0; + mb_data->last_query_tcp_id.w = 0; + mb_data->last_query_number_of_register.w = 0; + mb_data->current_query = MB_QUERY_NOTHING; + mb_data->last_query_slave_adress = 0; + mb_data->last_query_start_adress.w = 0; + mb_data->last_query_timeout = false; + } + + /* + * + * @brief Diese Funktion Initialisert die Modbus UART Hardware + * + * @param mb_data : Datenstruktur zur Aufnahme aller Daten + * @param usart : UART Modul, z.B. USART1 + * @param baudrate : UART BAUD + * @param parityMmode : Parity, mglich ist: + UART_PARITY_ODD, UART_PARITY_EVEN, UART_PARITY_NONE. + Default ist lt. Modbus Standart EVEN + * @param stopBits : Anzahl der Stop Bits, lt Modbus Standart + * 2 Stop Bits bei Parity None, ansonsten 2 Stop Bits + * @retval None + */ + void mbUartInit(modbus_t * mb_data,UART_HandleTypeDef * usart, uint32_t baudrate, uint32_t parityMode, uint32_t stopBits , uint32_t nrOfBitsPerChar) + { + //--- Uart Init ------------------------------------------------------------ + mb_data->uart = usart; + + // Baudrate + mb_data->uart->Init.BaudRate = baudrate; + + // Parity Mode // Word length + if(parityMode == MODBUS_UART_PARITY_EVEN) + { + mb_data->uart->Init.Parity = UART_PARITY_EVEN; + mb_data->uart->Init.WordLength = UART_WORDLENGTH_9B; + } + else if(parityMode == MODBUS_UART_PARITY_ODD) + { + mb_data->uart->Init.Parity = UART_PARITY_ODD; + mb_data->uart->Init.WordLength = UART_WORDLENGTH_9B; + } + else + { + mb_data->uart->Init.Parity = UART_PARITY_NONE; + mb_data->uart->Init.WordLength = UART_WORDLENGTH_8B; + } + + // Stopbits + if (stopBits == 1) + { + mb_data->uart->Init.StopBits = UART_STOPBITS_1; + } + else + { + mb_data->uart->Init.StopBits = UART_STOPBITS_2; + } + + if (HAL_UART_Init(mb_data->uart) != HAL_OK) + { + printf("ERROR Uart INIT\r\n"); + Error_Handler(); + } + + + HAL_UART_EnableReceiverTimeout( usart); + if (baudrate <= 19200) + { + HAL_UART_ReceiverTimeout_Config(usart, 3.5 * nrOfBitsPerChar); + } + else + { + uint32_t fixedDelayInBitDurations = (FAST_BAUDRATE_INTERFRAME_DELAY_us * baudrate) / 1000000UL + 1UL; + HAL_UART_ReceiverTimeout_Config(usart, fixedDelayInBitDurations); + } + + + SET_BIT(usart->Instance->CR1, USART_CR1_RTOIE); + + + if(HAL_UART_Receive_DMA(mb_data->uart, mb_data->rx_buffer, RXBUFFERSIZE) != HAL_OK) + { + printf("uart error \n\r"); + while(1) + { + } + } + } + + + +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + modbusData.mb_rx_frame_complete = 1; + modbusData.setRxLed = false; + modbusData.rx_head = huart->RxXferSize - __HAL_DMA_GET_COUNTER(huart->hdmarx); + + + if (huart->ErrorCode == HAL_UART_ERROR_RTO) + { + + // printf("MB RTO Event! \n\r"); + // Kein Fehler, normale Funktion + } + if (huart->ErrorCode == HAL_UART_ERROR_FE) + { + printf("MB FE Error! \n\r"); + } + + if (huart->ErrorCode == HAL_UART_ERROR_PE) + { + printf("MB PE Error! \n\r"); + } + + if (huart->ErrorCode == HAL_UART_ERROR_NE) + { + printf("MB NE Error! \n\r"); + } + + if (huart->ErrorCode == HAL_UART_ERROR_DMA) + { + printf("MB DMA Error! \n\r"); + } + + if (huart->ErrorCode == HAL_UART_ERROR_DMA) + { + printf("MB DMA Error! \n\r"); + } + + if (huart->ErrorCode == HAL_UART_ERROR_ORE) + { + printf("MB ORE Error! \n\r"); + } + + + + if(HAL_UART_Receive_DMA(huart, huart->pRxBuffPtr, RXBUFFERSIZE) != HAL_OK) + { + printf("Uart Error bei neustart nach Fehler \n\r"); + // while(1) + // { + // } + } + +} + +//void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +//{ +// //printf("MB rxEvent!RX=%d \n\r",Size); +// modbusData.setRxLed = true; + +// modbusData.mb_rx_frame_complete = 1; +// modbusData.rx_head= Size +1; + +// if(HAL_UART_Receive_DMA(huart, huart->pRxBuffPtr, RXBUFFERSIZE) != HAL_OK) +// { +// printf("uart error \n\r"); +// // while(1) +// // { +// // } +// } + + +//} + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + //printf("uart complete \n\r"); + modbusData.current_query = MB_QUERY_NOTHING; + +} + + + + + + + + + + + + + + + + + + + + + + void mbSend(modbus_t * mb_data ) + { + mb_data->current_query = MB_QUERY_SEND_DATA; + HAL_UART_Transmit_DMA(mb_data->uart, mb_data->tx_buffer, mb_data->tx_head); + } + + void mbClearTxBuffer(modbus_t * mb_data) + { + mb_data->tx_head = 0; + } + + + + // Compute the MODBUS RTU CRC + uint16_t mbCrc16 ( uint8_t *buf, uint32_t len) + { + uint16_t crc = 0xFFFF; + + for (uint32_t pos = 0; pos < len; pos++) + { + crc ^= (uint16_t)buf[pos]; // XOR byte into least sig. byte of crc + + for (int i = 8; i != 0; i--) + { // Loop over each bit + if ((crc & 0x0001) != 0) + { // If the LSB is set + crc >>= 1; // Shift right and XOR 0xA001 + crc ^= 0xA001; + } + else // Else LSB is not set + { + crc >>= 1; // Just shift right + } + } + } + + // Note, this number has low and high bytes swapped, so use it accordingly (or swap bytes) + return crc; + } + + /* If CRC is correct returns msg_length else returns INVALID_CRC */ + int mbCheckCrc16( uint8_t *msg, const int msg_length) + { + int ret; + uint16_t crc_calc; + uint16_t crc_received; + + crc_calc = mbCrc16(msg, msg_length - 2); + crc_received = (msg[msg_length - 1] << 8) | msg[msg_length - 2]; + + // Check CRC of msg + if (crc_calc == crc_received) { + ret = msg_length; + } else { + ret = INVALID_CRC; + } + return ret; + } + + uint32_t mbAppendCrc16(uint8_t * buffer, uint32_t tx_position) + { + uint16_t crc = mbCrc16( buffer , tx_position); + + uint8_t l_crc = (uint8_t) (crc & 0x00FF) ; + uint8_t h_crc = (uint8_t) (crc >> 8); + buffer[tx_position] = l_crc; + tx_position++; + buffer[tx_position] = h_crc; + tx_position++; + return tx_position; + } + + /************************************************************************************************************ + Function: mb_get_frame_complete + Purpose: Rckabe ob Frame komplett empfangen wurde + *************************************************************************************************************/ + bool mbGetFrameComplete(modbus_t * mb_data) + { + return mb_data->mb_rx_frame_complete; + } + + void mbClearRxFrame(modbus_t * mb_data) + { + // Wieder bei 0 im buffer anfangen + mb_data->rx_head = 0; + + // keine Daten mehr vorhanden + mb_data->mb_rx_frame_complete=false; + } + + + // --------------------- SLAVE FUNCTIONS --------------------------------------- + +#define SEND_TO_SLAVES_BUFFER_COUNT 1000 +//static TASK_MODBUS_MASTER_Message_t xMessage[255]; +//static TASK_MODBUS_MASTER_Message_t *pxMessage; +static bword_t values[SEND_TO_SLAVES_BUFFER_COUNT]; +static uint32_t y; +static uint32_t z; + + uint32_t mbSlaveCheckModbusRtuQuery(modbus_t * mb_data) + { + uint32_t message_lengh; + uint8_t *modbus_rx_message; + modbus_rx_message = mb_data->rx_buffer; + message_lengh= mb_data->rx_head; + uint32_t slave_adress; + slave_adress = modbus_rx_message[0]; + + if (message_lengh < 5) //Mindestens 5 Zeichen (Slave Adress + Function Code + 2x CRC + { + mbClearRxFrame(mb_data); + return 0; + } + + // Prfe CRC + if (mbCheckCrc16(modbus_rx_message,message_lengh) == INVALID_CRC) + { + mbClearRxFrame(mb_data); + return 0; + } + + if (slave_adress == MODBUS_BROADCAST_ADDRESS) + { + + return RESPOND_TO_QUERY; + } + /* auf richtige Slave Adresse checken ansonsten nicht antworten*/ + else if (slave_adress == sys_data.s.parameter.slave_address) + { + return RESPOND_TO_QUERY; + } + + mbClearRxFrame(mb_data); + return 0; + } + + void mbSlaveProcessRtuQuery(modbus_t * mb_data) + { + uint32_t tx_position=0; //die _Nchste_ Position in der Zeichen eingefgt werden mssen + uint8_t *modbus_rx_message; + modbus_rx_message = &mb_data->rx_buffer[0]; + + //Vorbereiten auf neues senden + mbClearTxBuffer(mb_data); + + //mb_data->tx_buffer[0] = sys_data.s.vmGreenview.s.lb_slave_adress; + mb_data->tx_buffer[0] = *modbus_rx_message; + tx_position++; + tx_position = mbSlaveProcessPdu(mb_data->tx_buffer , modbus_rx_message,tx_position, *modbus_rx_message); + + tx_position = mbAppendCrc16(mb_data->tx_buffer ,tx_position); + mb_data->tx_head=tx_position; + mbSend(mb_data); + mbClearRxFrame(mb_data); + } + + uint32_t mbSlaveProcessPdu (uint8_t* response_string, uint8_t * msg, uint32_t tx_position, uint8_t deviceID) + { + uint32_t function_code; + uint32_t ret; + + function_code = msg[OFFSET_FUNCTION_CODE]; + + switch (function_code) + { + case FC_READ_HOLDING_REGISTERS: + ret= mbSlaveReadHoldingRegisters(response_string, msg,tx_position, deviceID); + break; + + case FC_WRITE_SINGLE_REGISTER: + ret = mbSlaveWriteSingleRegister(response_string, msg,tx_position, deviceID); + break; + + case FC_WRITE_MULTIPLE_REGISTER: + ret=mbSlaveWriteMultipleRegisters(response_string, msg,tx_position, deviceID); + break; + + default: + ret=mbSlaveResponseException(response_string,function_code,ILLEGAL_FUNCTION,tx_position); + break; + } + + return ret; + } + + + uint32_t mbSlaveReadHoldingRegisters( uint8_t * response_string, uint8_t *msg, uint32_t tx_position, uint8_t deviceID) + { + uint32_t start_adress; + uint32_t adress; + uint32_t number_of_registers; + + /*stimmt die device ID mit der eigenen berein*/ + if((deviceID != sys_data.s.parameter.slave_address) && (deviceID != 0)) + { + return mbSlaveResponseException(response_string,FC_WRITE_SINGLE_REGISTER,GATEWAY_PROBLEM_TARGET,tx_position); + } + + start_adress = (msg[OFFSET_START_ADRESS_HI] << 8) + msg[OFFSET_START_ADRESS_LO]; + number_of_registers = ( msg[OFFSET_NO_OF_REGISTERS_HI] << 8) + msg[OFFSET_NO_OF_REGISTERS_LO]; + + if ((number_of_registers < MIN_NUMBER_OF_REGISTERS_FC3) || (number_of_registers > MAX_NUMBER_OF_REGISTERS_FC3) ) + { + return mbSlaveResponseException(response_string,FC_READ_HOLDING_REGISTERS,ILLEGAL_DATA_VALUE,tx_position); + } + + if (start_adress+number_of_registers-1 > MAX_ADRESS) + { + return mbSlaveResponseException(response_string, FC_READ_HOLDING_REGISTERS,ILLEGAL_DATA_ADDRESS,tx_position); + } + + response_string[tx_position] = FC_READ_HOLDING_REGISTERS; // FUNCTION CODE + tx_position++; + response_string[tx_position] = number_of_registers * 2; // Bytes + tx_position++; + + for(adress=start_adress;adress < (start_adress + number_of_registers);adress++) + { + /*Daten aus dem Speicher senden*/ + response_string[tx_position] = sys_data.mb[adress].b[1]; + tx_position++; + response_string[tx_position] = sys_data.mb[adress].b[0]; + tx_position++; + } + + return tx_position; + } + + + uint32_t mbSlaveWriteMultipleRegisters(uint8_t * response_string, uint8_t *msg, uint32_t tx_position, uint32_t deviceID) + { + + uint32_t start_adress; + uint32_t number_of_registers; + uint32_t adress; + uint32_t offset; + + /*stimmt die device ID mit der eigenen berein*/ + if((deviceID != sys_data.s.parameter.slave_address) && (deviceID != 0)) + { + return mbSlaveResponseException(response_string,FC_WRITE_SINGLE_REGISTER,GATEWAY_PROBLEM_TARGET,tx_position); + } + + start_adress = (msg[OFFSET_START_ADRESS_HI] << 8) + msg[OFFSET_START_ADRESS_LO]; + number_of_registers = ( msg[OFFSET_NO_OF_REGISTERS_HI] << 8) + msg[OFFSET_NO_OF_REGISTERS_LO]; + offset=7; + + if ((number_of_registers < MIN_NUMBER_OF_REGISTERS_FC16) || (number_of_registers > MAX_NUMBER_OF_REGISTERS_FC16) ) + { + return mbSlaveResponseException(response_string, FC_WRITE_MULTIPLE_REGISTER,ILLEGAL_DATA_VALUE,tx_position); + } + + if (start_adress+number_of_registers-1 > MAX_ADRESS) + { + return mbSlaveResponseException(response_string, FC_WRITE_MULTIPLE_REGISTER,ILLEGAL_DATA_ADDRESS,tx_position); + } + + /*Daten in Gertespeicher schreiben*/ + for(adress=start_adress;adress < (start_adress + number_of_registers);adress++) + { + sys_data.mb[adress].b[1] = msg[offset]; + sys_data.mb[adress].b[0] = msg[offset+1]; + offset+=2; + } + + response_string[tx_position] = FC_WRITE_MULTIPLE_REGISTER; // FUNCTION CODE - 1 byte + tx_position++; + response_string[tx_position] = start_adress >> 8; + tx_position++; + response_string[tx_position] = (uint8_t ) ( start_adress & 0x00FF); // start adresse 2 byte + tx_position++; + response_string[tx_position] = number_of_registers >> 8; + tx_position++; + response_string[tx_position] = (uint8_t ) ( number_of_registers & 0x00FF); // Anzahl Register 2 byte + tx_position++; + return tx_position; + } + + + uint32_t mbSlaveWriteSingleRegister(uint8_t * response_string,uint8_t *msg,uint32_t tx_position, uint32_t deviceID) + { + + uint32_t adress; + + /*stimmt die device ID mit der eigenen berein*/ + if((deviceID != sys_data.s.parameter.slave_address) && (deviceID != 0)) + { + return mbSlaveResponseException(response_string,FC_WRITE_SINGLE_REGISTER,GATEWAY_PROBLEM_TARGET,tx_position); + } + + adress = (msg[2] << 8) + msg[3]; + + if (adress > MAX_ADRESS) + { + return mbSlaveResponseException(response_string,FC_WRITE_SINGLE_REGISTER,ILLEGAL_DATA_ADDRESS,tx_position); + } + + /*schreibe Daten in eigenen Speicher*/ + sys_data.mb[adress].b[1] = msg[4]; + sys_data.mb[adress].b[0] = msg[5]; + + response_string[tx_position]= FC_WRITE_SINGLE_REGISTER; // FUNCTION CODE + tx_position++; + response_string[tx_position]= adress >> 8; + tx_position++; + response_string[tx_position]= (uint8_t ) ( adress & 0x00FF); + + tx_position++; + response_string[tx_position]= msg[4]; + tx_position++; + response_string[tx_position]= msg[5]; + tx_position++; + + return tx_position; + } + + + uint32_t mbSlaveResponseException(uint8_t* response_string, uint32_t function_code, uint32_t exception_code,uint32_t tx_position ) + { + function_code += 0x80; + response_string[tx_position] = function_code; // FUNCTION CODE + tx_position++; + response_string[tx_position] = exception_code; // + tx_position++; + return tx_position; + } + + + //---------------------------- UNKNOWN ----------------------------------------- + //- - + //------------------------------------------------------------------------------ + +#endif + Index: /trunk/firmware_v3/SES/src/mode_lvp.c =================================================================== --- /trunk/firmware_v3/SES/src/mode_lvp.c (revision 41) +++ /trunk/firmware_v3/SES/src/mode_lvp.c (revision 41) @@ -0,0 +1,303 @@ + +// Wie LVP||OVP Modul +// Jedoch hier nur LVP + + + +#include "stdio.h" +#include "mode_lvp.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" +#include "chip_temperature.h" + + +typedef enum LVP_State_enum +{ + LVP_OFF, + LVP_ON, + LVP_MANUAL_ON, + LVP_ERROR +} LVP_state_t; + + +static LVP_state_t smState; + + +static void LVP_SM_Off(void) +{ + int faultInput; + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("LVP_SM_Off: NEW_STATE: LVP_ON\n"); + smState = LVP_ON; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + //LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("LVP_SM_Off: NEW_STATE: LVP_ERROR_FAULT_INPUT\n"); + smState =LVP_ERROR; + } + } + + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME * 5); //Fehler Anzeigen + printf("NEW_STATE: LVP_MANUAL_ON\n"); + smState = LVP_MANUAL_ON; + } + + + +} + +static void LVP_SM_On(void) +{ + int faultInput = 0; + static int lvpInput = 0; + static int lvpTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) || (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + if (HAL_GetTick() != oldtime) + { + if (lvpTimeCounter < 5000) lvpTimeCounter++; + if (lvpTimeCounter >= 5000) + { + lvpInput = 1; + lvpTimeCounter=0; + } + oldtime = HAL_GetTick(); + } + } + + if (HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_RESET) + { +// if (HAL_GetTick() != oldtime) +// { +// lvpAndOvpInputTimeCounter++; +// if (lvpAndOvpInputTimeCounter > 30000) +// { + lvpInput = 0; + lvpTimeCounter=0; +// } +// oldtime = HAL_GetTick(); +// } + } + + + + + //Prüfe auf Fehlermode + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: LVP_ERROR\n"); + smState = LVP_ERROR; + } + + if (CHIP_TEMPERATURE_GetTemp() > 80) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_TEMP, LED_RT_ON_TIME_WARN_TEMP, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR, Temp too high\n"); + smState = LVP_ERROR; + } + + + //LVP oder OVP hat stattgefunden, und Relais ist ein, dann aus + if ((lvpInput == 1) && (RELAIS_GetState() == 1)) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_OVP_LVP, LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("LVP OFF!\n"); + printf("NEW_STATE: LVP_Auto On, Relais off\n"); + + } + + //KEIN LVP und keine OVP Abschaltung, Relais ist aber noch aus, dann einschalten + if ((lvpInput == 0) && (RELAIS_GetState() == 0)) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Warnung + LEDS_GN_Off(); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("LVP ON!\n"); + printf("NEW_STATE: LVP_OVP_Auto On, Relais on\n"); + + } + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: LVP_OFF\n"); + smState = LVP_OFF; + //Damit beim drücken auf on erstmal eingeschaltet wird + lvpTimeCounter=0; + lvpInput = 0; + } + + +} + +static void LVP_SM_ManualOn(void) +{ + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: LVP_OFF\n"); + smState = LVP_OFF; + } + +} + +static void LVP_SM_Error(void) +{ + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: LVP_ON\n"); + smState = LVP_ON; + } + else + { + //Wechsel nicht möglich. Fehler Eingang weiterhin aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: LVP_MANUAL_ON\n"); + smState = LVP_MANUAL_ON; + } + + + +} + + + +void MODE_LVP_Exec(void) +{ + + + + switch (smState) + { + case LVP_OFF: + LVP_SM_Off(); + break; + + case LVP_ON: + LVP_SM_On(); + break; + + case LVP_MANUAL_ON: + LVP_SM_ManualOn(); + break; + + case LVP_ERROR: + LVP_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/SES/src/mode_lvp_ovp.c =================================================================== --- /trunk/firmware_v3/SES/src/mode_lvp_ovp.c (revision 41) +++ /trunk/firmware_v3/SES/src/mode_lvp_ovp.c (revision 41) @@ -0,0 +1,319 @@ + +// Dieser Modus ist ein Hauptschaltermodus mit Secondary Protection +// Secondary Protection löst aus, wenn OVP und LVP wegfällt. +// OVP und LVP fällt wegbei: +// - Sehr tiefe Entladung +// - Sehr hohe Spannung +// - Übertemperatur +// - je nach Liproeinstellung möglicherweise auch wenn sowohl Untertemperaturschutz für Ladung und für Last erreicht ist +// - je nach Liproeinstellung möglicherweise auch wenn sowohl Überttemperaturschutz für Ladung und für Last erreicht ist +// - Die letzten beiden Positionen können vielleicht ungewollt sein. + +// OVP UND LVP Signal gleichzeitig: +// Es wurde eine Verzögerung von ca. 30 Sekunden implementiert. So kann noch problemlos ein Testjumper auf die Lipro gesteckt werden und die +// einzelnennen Funktionen zu prüfen. Außerdem ist es eventuell für die Prametrierung hilfreich, wenn nicht sofort ausgeht +// Auch wäre es hilfreich um zum Beispiel die Ursache über Modbus abfragen heruas zu bekommen + +// +// Fault Input: +// Hier ohne Verzögerung um schnell auf kurzschluss reagieren zu können +// Ansonsten wie Modus 0 + + + +#include "stdio.h" +#include "mode_lvp_ovp.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" +#include "chip_temperature.h" + + +typedef enum LVP_OVP_State_enum +{ + LVP_OVP_OFF, + LVP_OVP_ON, + LVP_OVP_MANUAL_ON, + LVP_OVP_ERROR +} LVP_OVP_state_t; + + +static LVP_OVP_state_t smState; + + +static void LVP_OVP_SM_Off(void) +{ + int faultInput; + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("LVP_OVP_SM_Off: NEW_STATE: LVP_OVP_ON\n"); + smState = LVP_OVP_ON; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + //LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("LVP_OVP_SM_Off: NEW_STATE: LVP_OVP_ERROR_FAULT_INPUT\n"); + smState =LVP_OVP_ERROR; + } + } + + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME * 5); //Fehler Anzeigen + printf("NEW_STATE: LVP_OVP_MANUAL_ON\n"); + smState = LVP_OVP_MANUAL_ON; + } + + + +} + +static void LVP_OVP_SM_On(void) +{ + int faultInput = 0; + static int lvpOROvpInput = 0; + static int lvpAndOvpInputTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) || (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + if (HAL_GetTick() != oldtime) + { + if (lvpAndOvpInputTimeCounter < 5000)lvpAndOvpInputTimeCounter++; + if (lvpAndOvpInputTimeCounter >= 5000) + { + lvpOROvpInput = 1; + lvpAndOvpInputTimeCounter=0; + } + oldtime = HAL_GetTick(); + } + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_RESET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_RESET)) + { +// if (HAL_GetTick() != oldtime) +// { +// lvpAndOvpInputTimeCounter++; +// if (lvpAndOvpInputTimeCounter > 30000) +// { + lvpOROvpInput = 0; + lvpAndOvpInputTimeCounter=0; +// } +// oldtime = HAL_GetTick(); +// } + } + + + + + //Prüfe auf Fehlermode + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: LVP_OVP_ERROR\n"); + smState = LVP_OVP_ERROR; + } + + if (CHIP_TEMPERATURE_GetTemp() > 80) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_TEMP, LED_RT_ON_TIME_WARN_TEMP, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR, Temp too high\n"); + smState = LVP_OVP_ERROR; + } + + + //LVP oder OVP hat stattgefunden, und Relais ist ein, dann aus + if ((lvpOROvpInput == 1) && (RELAIS_GetState() == 1)) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_OVP_LVP, LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("LVP OR OVP OFF!\n"); + printf("NEW_STATE: LVP_OVP_Auto On, Relais off\n"); + + } + + //KEIN LVP und keine OVP Abschaltung, Relais ist aber noch aus, dann einschalten + if ((lvpOROvpInput == 0) && (RELAIS_GetState() == 0)) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Warnung + LEDS_GN_Off(); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("LVP AND OVP ON!\n"); + printf("NEW_STATE: LVP_OVP_Auto On, Relais on\n"); + + } + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: LVP_OVP_OFF\n"); + smState = LVP_OVP_OFF; + //Damit beim drücken auf on erstmal eingeschaltet wird + lvpAndOvpInputTimeCounter=0; + lvpOROvpInput = 0; + } + + +} + +static void LVP_OVP_SM_ManualOn(void) +{ + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: LVP_OVP_OFF\n"); + smState = LVP_OVP_OFF; + } + +} + +static void LVP_OVP_SM_Error(void) +{ + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: LVP_OVP_ON\n"); + smState = LVP_OVP_ON; + } + else + { + //Wechsel nicht möglich. Fehler Eingang weiterhin aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: LVP_OVP_MANUAL_ON\n"); + smState = LVP_OVP_MANUAL_ON; + } + + + +} + + + +void MODE_LVP_OVP_Exec(void) +{ + + + + switch (smState) + { + case LVP_OVP_OFF: + LVP_OVP_SM_Off(); + break; + + case LVP_OVP_ON: + LVP_OVP_SM_On(); + break; + + case LVP_OVP_MANUAL_ON: + LVP_OVP_SM_ManualOn(); + break; + + case LVP_OVP_ERROR: + LVP_OVP_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/SES/src/mode_mainswitch.c =================================================================== --- /trunk/firmware_v3/SES/src/mode_mainswitch.c (revision 41) +++ /trunk/firmware_v3/SES/src/mode_mainswitch.c (revision 41) @@ -0,0 +1,236 @@ +// Keine LVP und OVP Überwachung aber Fault wird geprüft! +// Falls nicht benötigt, nicht anschließen ?! Ist Low active mit PullUp +// Dieser Modus ist als Hauptschaltermodus ohne BMS gedacht. Z.B. für Bleibatterien +// Oder als Hauptschalter mit Fremd BMS + + + +#include "stdio.h" +#include "mode_mainswitch.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" +#include "chip_temperature.h" + + +typedef enum MAINSWITCH_State_enum +{ + MAINSWITCH_OFF, + MAINSWITCH_ON, + MAINSWITCH_MANUAL_ON, + MAINSWITCH_ERROR +} MAINSWITCH_state_t; + + +static MAINSWITCH_state_t smState; + + +void MAINSWITCH_SM_Off(void) +{ + int faultInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: MAINSWITCH_ON\n"); + smState = MAINSWITCH_ON; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + smState = MAINSWITCH_ERROR; + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: MAINSWITCH_MANUAL_ON\n"); + smState = MAINSWITCH_MANUAL_ON; + } + + + +} + +void MAINSWITCH_SM_On(void) +{ + int faultInput; + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: MAINSWITCH_OFF\n"); + smState = MAINSWITCH_OFF; + } + + //Prüfe auf Fehlermode + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + smState = MAINSWITCH_ERROR; + } + + if (CHIP_TEMPERATURE_GetTemp() > 80) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_TEMP, LED_RT_ON_TIME_WARN_TEMP, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR, Temp too high\n"); + smState = MAINSWITCH_ERROR; + } + + + + +} + +void MAINSWITCH_SM_ManualOn(void) +{ + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: MAINSWITCH_OFF\n"); + smState = MAINSWITCH_OFF; + } + +} + +void MAINSWITCH_SM_Error(void) +{ + int faultInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: MAINSWITCH_ON\n"); + smState = MAINSWITCH_ON; + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: MAINSWITCH_MANUAL_ON\n"); + smState = MAINSWITCH_MANUAL_ON; + } + + + +} + + + +void MODE_MAINSWITCH_Exec(void) +{ + + + + switch (smState) + { + case MAINSWITCH_OFF: + MAINSWITCH_SM_Off(); + break; + + case MAINSWITCH_ON: + MAINSWITCH_SM_On(); + break; + + case MAINSWITCH_MANUAL_ON: + MAINSWITCH_SM_ManualOn(); + break; + + case MAINSWITCH_ERROR: + MAINSWITCH_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/SES/src/mode_ovp.c =================================================================== --- /trunk/firmware_v3/SES/src/mode_ovp.c (revision 41) +++ /trunk/firmware_v3/SES/src/mode_ovp.c (revision 41) @@ -0,0 +1,302 @@ + +// Wie OVP||OVP Modul +// Jedoch hier nur OVP + + + +#include "stdio.h" +#include "mode_ovp.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" +#include "chip_temperature.h" + + +typedef enum OVP_State_enum +{ + OVP_OFF, + OVP_ON, + OVP_MANUAL_ON, + OVP_ERROR +} OVP_state_t; + + +static OVP_state_t smState; + + +static void OVP_SM_Off(void) +{ + int faultInput; + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("OVP_SM_Off: NEW_STATE: OVP_ON\n"); + smState = OVP_ON; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + //LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("OVP_SM_Off: NEW_STATE: OVP_ERROR_FAULT_INPUT\n"); + smState =OVP_ERROR; + } + } + + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME * 5); //Fehler Anzeigen + printf("NEW_STATE: OVP_MANUAL_ON\n"); + smState = OVP_MANUAL_ON; + } + + + +} + +static void OVP_SM_On(void) +{ + int faultInput = 0; + static int ovpInput = 0; + static int ovpTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET) || (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + if (HAL_GetTick() != oldtime) + { + if (ovpTimeCounter < 5000) ovpTimeCounter++; + if (ovpTimeCounter >= 5000) + { + ovpInput = 1; + ovpTimeCounter=0; + } + oldtime = HAL_GetTick(); + } + } + + if (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_RESET) + { +// if (HAL_GetTick() != oldtime) +// { +// ovpAndOvpInputTimeCounter++; +// if (ovpAndOvpInputTimeCounter > 30000) +// { + ovpInput = 0; + ovpTimeCounter=0; +// } +// oldtime = HAL_GetTick(); +// } + } + + + + + //Prüfe auf Fehlermode + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: OVP_ERROR\n"); + smState = OVP_ERROR; + } + + if (CHIP_TEMPERATURE_GetTemp() > 80) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_TEMP, LED_RT_ON_TIME_WARN_TEMP, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR, Temp too high\n"); + smState = OVP_ERROR; + } + + + //OVP oder OVP hat stattgefunden, und Relais ist ein, dann aus + if ((ovpInput == 1) && (RELAIS_GetState() == 1)) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + printf("OVP OFF!\n"); + printf("NEW_STATE: OVP_Auto On, Relais off\n"); + + } + + //KEIN OVP und keine OVP Abschaltung, Relais ist aber noch aus, dann einschalten + if ((ovpInput == 0) && (RELAIS_GetState() == 0)) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Warnung + LEDS_GN_Off(); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("OVP ON!\n"); + printf("NEW_STATE: OVP_OVP_Auto On, Relais on\n"); + + } + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: OVP_OFF\n"); + smState = OVP_OFF; + //Damit beim drücken auf on erstmal eingeschaltet wird + ovpTimeCounter=0; + ovpInput = 0; + } + + +} + +static void OVP_SM_ManualOn(void) +{ + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: OVP_OFF\n"); + smState = OVP_OFF; + } + +} + +static void OVP_SM_Error(void) +{ + int faultInput; + int ovpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: OVP_ON\n"); + smState = OVP_ON; + } + else + { + //Wechsel nicht möglich. Fehler Eingang weiterhin aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: OVP_MANUAL_ON\n"); + smState = OVP_MANUAL_ON; + } + + + +} + + + +void MODE_OVP_Exec(void) +{ + + + + switch (smState) + { + case OVP_OFF: + OVP_SM_Off(); + break; + + case OVP_ON: + OVP_SM_On(); + break; + + case OVP_MANUAL_ON: + OVP_SM_ManualOn(); + break; + + case OVP_ERROR: + OVP_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/SES/src/mode_secondaryprotection.c =================================================================== --- /trunk/firmware_v3/SES/src/mode_secondaryprotection.c (revision 41) +++ /trunk/firmware_v3/SES/src/mode_secondaryprotection.c (revision 41) @@ -0,0 +1,377 @@ + +// Dieser Modus ist ein Hauptschaltermodus mit Secondary Protection +// Secondary Protection löst aus, wenn OVP und LVP wegfällt. +// OVP und LVP fällt wegbei: +// - Sehr tiefe Entladung +// - Sehr hohe Spannung +// - Übertemperatur +// - je nach Liproeinstellung möglicherweise auch wenn sowohl Untertemperaturschutz für Ladung und für Last erreicht ist +// - je nach Liproeinstellung möglicherweise auch wenn sowohl Überttemperaturschutz für Ladung und für Last erreicht ist +// - Die letzten beiden Positionen können vielleicht ungewollt sein. + +// OVP UND LVP Signal gleichzeitig: +// Es wurde eine Verzögerung von ca. 30 Sekunden implementiert. So kann noch problemlos ein Testjumper auf die Lipro gesteckt werden und die +// einzelnennen Funktionen zu prüfen. Außerdem ist es eventuell für die Prametrierung hilfreich, wenn nicht sofort ausgeht +// Auch wäre es hilfreich um zum Beispiel die Ursache über Modbus abfragen heruas zu bekommen + +// +// Fault Input: +// Hier ohne Verzögerung um schnell auf kurzschluss reagieren zu können +// Ansonsten wie Modus 0 + + + +#include "stdio.h" +#include "mode_secondaryprotection.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" +#include "voltage_meas.h" +#include "chip_temperature.h" + + +typedef enum SECONDARYPROTECTION_State_enum +{ + SECONDARYPROTECTION_OFF, + SECONDARYPROTECTION_ON, + SECONDARYPROTECTION_MANUAL_ON, + SECONDARYPROTECTION_ERROR +} SECONDARYPROTECTION_state_t; + +typedef enum SECONDARYPROTECTION_ErrorState_enum +{ + ERROR_NONE, + ERROR_EXTERNAL_FAULT, //z.B Kurzschluss + ERROR_TEMPERATURE, + ERROR_VOLTAGE_DROP, + ERROR_LVP_AND_OVP, //z.B. kritische Überspannung, tiefeEntladung +} SECONDARYPROTECTION_ErrorState_t; + + +static SECONDARYPROTECTION_state_t smState; +static SECONDARYPROTECTION_ErrorState_t smError; +static int autoRetryMode; + + +static void SECONDARYPROTECTION_SM_Off(void) +{ + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + lvpAndOvpInput = 1; + }else { + lvpAndOvpInput = 0; + } + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + smState = SECONDARYPROTECTION_ON; + smError = ERROR_NONE; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + //LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState =SECONDARYPROTECTION_ERROR; + smError = ERROR_EXTERNAL_FAULT; + } + } + + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME * 5); //Fehler Anzeigen + printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + smState = SECONDARYPROTECTION_MANUAL_ON; + smError = ERROR_NONE; + } + + + +} + +static void SECONDARYPROTECTION_SM_On(void) +{ + int faultInput = 0; + int lvpAndOvpInput = 0; + static int lvpAndOvpInputTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_EXTERNAL_FAULT; + return; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + if (HAL_GetTick() != oldtime) + { + lvpAndOvpInputTimeCounter++; + if (lvpAndOvpInputTimeCounter > 30000) + { + lvpAndOvpInput = 1; + lvpAndOvpInputTimeCounter=0; + } + oldtime = HAL_GetTick(); + } + } + else + { + lvpAndOvpInputTimeCounter = 0; + lvpAndOvpInput = 0; + } + + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + } + + //Prüfe auf Fehlermode + if (VOLTAGE_MEAS_GetLimitAlarm() == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_VOLTAGE_DROP, LED_RT_ON_TIME_WARN_VOLTAGE_DROP, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT VOLTAGE DROP DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_VOLTAGE_DROP; + VOLTAGE_MEAS_ResetCounter(); // Damit Fehlerzähler bei Neustart auf 0 + } + + + + if (lvpAndOvpInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_OVP_LVP, LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("BMS SECONDARY PROTECTION FAULT EVENT DETECTED (LVP & OVP )!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_LVP_AND_OVP; + } + + if (CHIP_TEMPERATURE_GetTemp() > 80) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_TEMP, LED_RT_ON_TIME_WARN_TEMP, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR, Temp too high\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_TEMPERATURE; + } + + + +} + +static void SECONDARYPROTECTION_SM_ManualOn(void) +{ + + int faultInput = 0; + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_EXTERNAL_FAULT; + } + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + smError = ERROR_NONE; + } + +} + +static void SECONDARYPROTECTION_SM_Error(void) +{ + int faultInput; + int lvpAndOvpInput; + static uint32_t retry_counter = 0; + static uint32_t oldTimeMSTick; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + smState = SECONDARYPROTECTION_ON; + smError = ERROR_NONE; + } + else + { + //Wechsel nicht möglich. Fehler Eingang weiterhin aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + smState = SECONDARYPROTECTION_MANUAL_ON; + smError = ERROR_NONE; + } + + + if (autoRetryMode == 1) { + + if (oldTimeMSTick != HAL_GetTick()) + { + oldTimeMSTick = HAL_GetTick(); + retry_counter++; + } + + if (retry_counter > 3600000) // 10 Minuten * 60 * 1000 = 600000 || 60 * 60 * 1000 =3600000 + { + BUTTON_SetModeAuto(); + retry_counter=0; + } + } +} + + + +void MODE_SECONDARYPROTECTION_Exec(int am) +{ + + autoRetryMode = am; + + switch (smState) + { + case SECONDARYPROTECTION_OFF: + SECONDARYPROTECTION_SM_Off(); + break; + + case SECONDARYPROTECTION_ON: + SECONDARYPROTECTION_SM_On(); + break; + + case SECONDARYPROTECTION_MANUAL_ON: + SECONDARYPROTECTION_SM_ManualOn(); + break; + + case SECONDARYPROTECTION_ERROR: + SECONDARYPROTECTION_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/SES/src/mode_secondaryprotection_plus.c =================================================================== --- /trunk/firmware_v3/SES/src/mode_secondaryprotection_plus.c (revision 41) +++ /trunk/firmware_v3/SES/src/mode_secondaryprotection_plus.c (revision 41) @@ -0,0 +1,351 @@ + +// Dieser Modus ist ein Hauptschaltermodus mit Secondary Protection +// Secondary Protection löst aus, wenn OVP und LVP wegfällt. +// OVP und LVP fällt wegbei: +// - Sehr tiefe Entladung +// - Sehr hohe Spannung +// - Übertemperatur +// - je nach Liproeinstellung möglicherweise auch wenn sowohl Untertemperaturschutz für Ladung und für Last erreicht ist +// - je nach Liproeinstellung möglicherweise auch wenn sowohl Überttemperaturschutz für Ladung und für Last erreicht ist +// - Die letzten beiden Positionen können vielleicht ungewollt sein. + + +// Hier wird Manuall On nicht erlaubt -> Extra sicher +// Ansonsten wie Modus 1 + + + +#include "stdio.h" +#include "mode_secondaryprotection_plus.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" +#include "chip_temperature.h" +#include "voltage_meas.h" + + +typedef enum SECONDARYPROTECTION_State_enum +{ + SECONDARYPROTECTION_OFF, + SECONDARYPROTECTION_ON, + // SECONDARYPROTECTION_MANUAL_ON, HIer nicht erlaubt für mehr Sicherheit + SECONDARYPROTECTION_ERROR +} SECONDARYPROTECTION_state_t; + +typedef enum SECONDARYPROTECTION_ErrorState_enum +{ + ERROR_NONE, + ERROR_EXTERNAL_FAULT, //z.B Kurzschluss + ERROR_TEMPERATURE, + ERROR_VOLTAGE_DROP, + ERROR_LVP_AND_OVP, //z.B. kritische Überspannung, tiefeEntladung +} SECONDARYPROTECTION_ErrorState_t; + + +static SECONDARYPROTECTION_state_t smState; +static SECONDARYPROTECTION_ErrorState_t smError = ERROR_NONE; +static int autoRetryMode; + +static void SECONDARYPROTECTION_SM_Off(void) +{ + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + lvpAndOvpInput = 1; + }else { + lvpAndOvpInput = 0; + } + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + smState = SECONDARYPROTECTION_ON; + smError = ERROR_NONE; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + //LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_EXTERNAL_FAULT; + + } + } + + + ////Prüfe auf Wechsel in MANUAL ON Mode + ////Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + //if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + //{ + + // RELAIS_SetPuls(); + // BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + // LEDS_GN_On(); + // LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME * 5); //Fehler Anzeigen + // printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + // smState = SECONDARYPROTECTION_MANUAL_ON; + //} + + + +} + +static void SECONDARYPROTECTION_SM_On(void) +{ + int faultInput = 0; + int lvpAndOvpInput = 0; + static int lvpAndOvpInputTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_FAULT_INPUT, LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_EXTERNAL_FAULT; + return; + } + + + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + if (HAL_GetTick() != oldtime) + { + lvpAndOvpInputTimeCounter++; + if (lvpAndOvpInputTimeCounter > 30000) + { + lvpAndOvpInput = 1; + lvpAndOvpInputTimeCounter=0; + } + oldtime = HAL_GetTick(); + } + } + else + { + lvpAndOvpInputTimeCounter = 0; + lvpAndOvpInput = 0; + } + + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + smError = ERROR_NONE; + } + + //Prüfe auf Fehlermode + if (VOLTAGE_MEAS_GetLimitAlarm() == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_VOLTAGE_DROP, LED_RT_ON_TIME_WARN_VOLTAGE_DROP, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT VOLTAGE DROP DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_VOLTAGE_DROP; + VOLTAGE_MEAS_ResetCounter(); // Damit Fehlerzähler bei Neustart auf 0 + } + + + + if (lvpAndOvpInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_OVP_LVP, LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("BMS SECONDARY PROTECTION FAULT EVENT DETECTED (LVP & OVP )!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_LVP_AND_OVP; + } + + if (CHIP_TEMPERATURE_GetTemp() > 80) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_BlinkCode_Start(BLINK_CODE_ERROR_TEMP, LED_RT_ON_TIME_WARN_TEMP, LED_GN_OFF_TIME, LED_GN_OFF_TIME *5); //Fehler Anzeigen + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR, Temp too high\n"); + smState = SECONDARYPROTECTION_ERROR; + smError = ERROR_TEMPERATURE; + } + + + +} + +//static void SECONDARYPROTECTION_SM_ManualOn(void) +//{ +// // Prüfe Wechsel in off mode +// if (BUTTON_GetMode() == BUTTON_OFF) +// { +// //Ausschalten muss immer möglich sein +// RELAIS_ResetPuls(); +// BUZZER_Alarm_Stop(); +// LEDS_GN_Off(); +// LEDS_RT_Off(); +// printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); +// smState = SECONDARYPROTECTION_OFF; +// } + +//} + +static void SECONDARYPROTECTION_SM_Error(void) +{ + int faultInput; + int lvpAndOvpInput; + static uint32_t retry_counter = 0; + static uint32_t oldTimeMSTick; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + retry_counter = 0; + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + smState = SECONDARYPROTECTION_ON; + smError = ERROR_NONE; + } + else + { + //Wechsel nicht möglich. Fehler Eingang weiterhin aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + if (autoRetryMode == 1) { + + if (oldTimeMSTick != HAL_GetTick()) + { + oldTimeMSTick = HAL_GetTick(); + retry_counter++; + } + + if (retry_counter > 3600000) // jede stunde + { + BUTTON_SetModeAuto(); + retry_counter = 0; + } + } + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + //if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + //{ + + // RELAIS_SetPuls(); + // BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + // LEDS_GN_On(); + // LEDS_RT_Off(); + // LEDS_RT_BlinkCode_Start(BLINK_CODE_WARN_MANUAL, LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME, LED_RT_OFF_TIME *5); //Fehler Anzeigen + // printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + // smState = SECONDARYPROTECTION_MANUAL_ON; + //} + + + +} + + + +void MODE_SECONDARYPROTECTION_PLUS_Exec(int am) +{ + + autoRetryMode = am; + + switch (smState) + { + case SECONDARYPROTECTION_OFF: + SECONDARYPROTECTION_SM_Off(); + break; + + case SECONDARYPROTECTION_ON: + SECONDARYPROTECTION_SM_On(); + break; + + //case SECONDARYPROTECTION_MANUAL_ON: + //SECONDARYPROTECTION_SM_ManualOn(); + //break; + + case SECONDARYPROTECTION_ERROR: + SECONDARYPROTECTION_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/SES/src/modeswitch.c =================================================================== --- /trunk/firmware_v3/SES/src/modeswitch.c (revision 41) +++ /trunk/firmware_v3/SES/src/modeswitch.c (revision 41) @@ -0,0 +1,31 @@ +#include +#include "modeswitch.h" +#include "main.h" + + +static MODESWITCH_mode_t mode; + +MODESWITCH_mode_t MODESWITCH_ReadMode(void) +{ + + + int m0 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B0_GPIO_Port, GPIO_INPUT_MODE_B0_Pin) << 0); + int m1 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B1_GPIO_Port, GPIO_INPUT_MODE_B1_Pin) << 1); + int m2 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B2_GPIO_Port, GPIO_INPUT_MODE_B2_Pin) << 2); + int m3 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B3_GPIO_Port, GPIO_INPUT_MODE_B3_Pin) << 3); + + + + mode = m0 | m1 | m2 | m3; + mode = 0x0f &~mode; + printf("mode=%i\n",mode); + + return mode; +} + + +MODESWITCH_mode_t MODESWITCH_GetMode(void) +{ + return mode; +} + Index: /trunk/firmware_v3/SES/src/relais.c =================================================================== --- /trunk/firmware_v3/SES/src/relais.c (revision 41) +++ /trunk/firmware_v3/SES/src/relais.c (revision 41) @@ -0,0 +1,83 @@ +#include "relais.h" +#include "main.h" + + +#define PULS_TIME 50 + + + +unsigned int onTimeCounterSET; //Set Coil +unsigned int onTimeCounterRESET; //Reset Coil +unsigned int relaisState; +int32_t relais_temperature; + + +uint16_t RELAIS_GetTemp(void) +{ + return relais_temperature; +} + +void RELAIS_Exec(uint32_t adcValue) +{ + + + int32_t temp = adcValue; + temp = temp * VREF; + temp = temp / 65635; // Spannung + temp = (temp - 600) / 10; //Temperatur + relais_temperature = temp; + + + if (onTimeCounterSET > 0) + { + onTimeCounterSET--; + if (onTimeCounterSET == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + } + } + + + +if (onTimeCounterRESET > 0) + { + onTimeCounterRESET--; + if (onTimeCounterRESET == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + } + } + +} + +void RELAIS_SetPuls(void) +{ + + //Sicherstellen das nicht noch die Reset Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_SET); + onTimeCounterSET = PULS_TIME; + relaisState = 1; + +} + +void RELAIS_ResetPuls(void) +{ + + //Sicherstellen das nicht noch die Set Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_SET); + onTimeCounterRESET = PULS_TIME; + relaisState = 0; + +} + + +unsigned int RELAIS_GetState(void) +{ + return relaisState; +} Index: /trunk/firmware_v3/SES/src/sysdata.c =================================================================== --- /trunk/firmware_v3/SES/src/sysdata.c (revision 41) +++ /trunk/firmware_v3/SES/src/sysdata.c (revision 41) @@ -0,0 +1,28 @@ +/*! + * \file : sysdata.c + * \brief : Contains definition of SYS_DATA structure. + * + */ + +#include "sysdata.h" +#include "modbus.h" + +sys_data_t sys_data; + +void SYS_DATA_Init(void) +{ + // Gertetyp angeben + + sys_data.s.parameter.device_type = 600; + + sys_data.s.parameter.fw_revision_major = 1; + sys_data.s.parameter.fw_revision_minor = 0; + sys_data.s.parameter.fw_revision_revision = 0; + + + + + + + +} Index: /trunk/firmware_v3/SES/src/voltage_meas.c =================================================================== --- /trunk/firmware_v3/SES/src/voltage_meas.c (revision 41) +++ /trunk/firmware_v3/SES/src/voltage_meas.c (revision 41) @@ -0,0 +1,89 @@ +#include "main.h" +#include "voltage_meas.h" +#include "relais.h" +#include +#include + + + +static uint32_t voltageUin; +static uint32_t voltageUout; +static uint32_t voltageDrop; + + + +#if defined SYSTEM_VOLTAGE_12V + #define VOLTAGE_DIVIDER 6 +#elif defined SYSTEM_VOLTAGE_24V + #define VOLTAGE_DIVIDER 11 +#elif defined SYSTEM_VOLTAGE_48V + #define VOLTAGE_DIVIDER 21 +#else + #error "System voltage not defined" +#endif + + +#define VOLTAGE_DROP_U_LIMIT 90 //mV ca. 30 mV Messfehler + 60mV bei 150A +#define VOLTAGE_DROP_T_LIMIT 1000 + +uint32_t dropLimitCounter=0; + + +void VOLTAGE_MEAS_Exec(uint32_t adcValUin, uint32_t adcValUout) +{ + + int32_t vuin; + vuin = adcValUin * VREF; + vuin = vuin / 65635; + vuin = vuin * VOLTAGE_DIVIDER; //Divider für 12V Version + voltageUin = vuin; + + + int32_t vuout; + vuout = adcValUout * VREF; + vuout = vuout / 65635; + vuout = vuout * VOLTAGE_DIVIDER; //Divider für 12V Version + voltageUout = vuout; + + voltageDrop = abs((int32_t)voltageUin - (int32_t)voltageUout); + + if ((RELAIS_GetState() == 1) && (voltageDrop > VOLTAGE_DROP_U_LIMIT)) + { + if (dropLimitCounter < VOLTAGE_DROP_T_LIMIT) dropLimitCounter++; + printf("voltage in= %d, out= %d, drop %d\r\n", voltageUin, voltageUout, voltageDrop); + } + else + { + if (dropLimitCounter > 0) dropLimitCounter--; + } + +} + + +uint32_t VOLTAGE_MEAS_GetLimitAlarm(void) +{ + if (dropLimitCounter == VOLTAGE_DROP_T_LIMIT) { + return 1; + } + else { + return 0; + } + +} + +void VOLTAGE_MEAS_ResetCounter(void) +{ + dropLimitCounter = 0; + +} + +uint32_t VOLTAGE_MEAS_GetUin(void) +{ + return voltageUin; + +} + +uint32_t VOLTAGE_MEAS_GetUout(void) +{ + return voltageUout; +} Index: /trunk/firmware_v3/STM32CubeIDE/.cproject =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/.cproject (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/.cproject (revision 41) @@ -0,0 +1,173 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /trunk/firmware_v3/STM32CubeIDE/.project =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/.project (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/.project (revision 41) @@ -0,0 +1,185 @@ + + + firmware_v2 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + firmware_v2.ioc + 1 + PARENT-1-PROJECT_LOC/firmware_v2.ioc + + + Drivers/CMSIS/system_stm32c0xx.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/system_stm32c0xx.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_iwdg.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c + + + Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c + + + Application/User/Core/adc.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/adc.c + + + Application/User/Core/dma.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/dma.c + + + Application/User/Core/gpio.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/gpio.c + + + Application/User/Core/iwdg.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/iwdg.c + + + Application/User/Core/main.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/main.c + + + Application/User/Core/stm32c0xx_hal_msp.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/stm32c0xx_hal_msp.c + + + Application/User/Core/stm32c0xx_it.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/stm32c0xx_it.c + + + Application/User/Core/tim.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/tim.c + + + Application/User/Core/usart.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/usart.c + + + Index: /trunk/firmware_v3/STM32CubeIDE/.settings/language.settings.xml =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/.settings/language.settings.xml (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/.settings/language.settings.xml (revision 41) @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + Index: /trunk/firmware_v3/STM32CubeIDE/.settings/org.eclipse.core.resources.prefs =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/.settings/org.eclipse.core.resources.prefs (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/.settings/org.eclipse.core.resources.prefs (revision 41) @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 Index: /trunk/firmware_v3/STM32CubeIDE/.settings/stm32cubeide.project.prefs =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/.settings/stm32cubeide.project.prefs (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/.settings/stm32cubeide.project.prefs (revision 41) @@ -0,0 +1,3 @@ +8DF89ED150041C4CBC7CB9A9CAA90856=952B439DCA27C12ED81C67E8720491D0 +DC22A860405A8BF2F2C095E5B6529F12=DD04E5640BE8ED43763E5F554A6B8730 +eclipse.preferences.version=1 Index: /trunk/firmware_v3/STM32CubeIDE/Application/User/Core/syscalls.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Application/User/Core/syscalls.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Application/User/Core/syscalls.c (revision 41) @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} Index: /trunk/firmware_v3/STM32CubeIDE/Application/User/Core/sysmem.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Application/User/Core/sysmem.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Application/User/Core/sysmem.c (revision 41) @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} Index: /trunk/firmware_v3/STM32CubeIDE/Application/User/Startup/startup_stm32c031k4tx.s =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Application/User/Startup/startup_stm32c031k4tx.s (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Application/User/Startup/startup_stm32c031k4tx.s (revision 41) @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file startup_stm32c031xx.s + * @author MCD Application Team + * @brief STM32C031xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMAMUX1_IRQHandler /* DMAMUX1 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* reserved */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word 0 /* reserved */ + + .size g_pfnVectors, .-g_pfnVectors +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMAMUX1_IRQHandler + .thumb_set DMAMUX1_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.cyclo (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:31:6:MX_ADC1_Init 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:118:6:HAL_ADC_MspInit 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:177:6:HAL_ADC_MspDeInit 2 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/adc.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c \ + ../../Core/Inc/adc.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/adc.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/adc.su (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:31:6:MX_ADC1_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:118:6:HAL_ADC_MspInit 72 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:177:6:HAL_ADC_MspDeInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.cyclo (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c:39:6:MX_DMA_Init 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/dma.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c \ + ../../Core/Inc/dma.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/dma.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/dma.su (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c:39:6:MX_DMA_Init 16 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.cyclo (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c:42:6:MX_GPIO_Init 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/gpio.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c \ + ../../Core/Inc/gpio.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/gpio.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/gpio.su (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c:42:6:MX_GPIO_Init 56 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.cyclo (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:159:6:Error_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:117:6:SystemClock_Config 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:68:5:main 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.d (revision 41) @@ -0,0 +1,80 @@ +Application/User/Core/main.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + ../../Core/Inc/adc.h ../../Core/Inc/main.h ../../Core/Inc/dma.h \ + ../../Core/Inc/tim.h ../../Core/Inc/usart.h ../../Core/Inc/gpio.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +../../Core/Inc/adc.h: +../../Core/Inc/main.h: +../../Core/Inc/dma.h: +../../Core/Inc/tim.h: +../../Core/Inc/usart.h: +../../Core/Inc/gpio.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/main.su (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:159:6:Error_Handler 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:117:6:SystemClock_Config 56 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:68:5:main 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.cyclo (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c:63:6:HAL_MspInit 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,72 @@ +Application/User/Core/stm32c0xx_hal_msp.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_hal_msp.su (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c:63:6:HAL_MspInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.cyclo (revision 41) @@ -0,0 +1,9 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:78:6:NMI_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:93:6:HardFault_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:108:6:SVC_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:121:6:PendSV_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:134:6:SysTick_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:155:6:DMA1_Channel1_IRQHandler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:169:6:TIM16_IRQHandler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:182:6:HAL_TIM_IC_CaptureCallback 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:195:6:HAL_TIM_PeriodElapsedCallback 3 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.d (revision 41) @@ -0,0 +1,76 @@ +Application/User/Core/stm32c0xx_it.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + ../../Core/Inc/stm32c0xx_it.h ../../Core/Inc/tim.h ../../Core/Inc/main.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +../../Core/Inc/stm32c0xx_it.h: +../../Core/Inc/tim.h: +../../Core/Inc/main.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/stm32c0xx_it.su (revision 41) @@ -0,0 +1,9 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:78:6:NMI_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:93:6:HardFault_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:108:6:SVC_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:121:6:PendSV_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:134:6:SysTick_Handler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:155:6:DMA1_Channel1_IRQHandler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:169:6:TIM16_IRQHandler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:182:6:HAL_TIM_IC_CaptureCallback 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:195:6:HAL_TIM_PeriodElapsedCallback 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/subdir.mk (revision 41) @@ -0,0 +1,70 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c \ +../Application/User/Core/syscalls.c \ +../Application/User/Core/sysmem.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c + +OBJS += \ +./Application/User/Core/adc.o \ +./Application/User/Core/dma.o \ +./Application/User/Core/gpio.o \ +./Application/User/Core/main.o \ +./Application/User/Core/stm32c0xx_hal_msp.o \ +./Application/User/Core/stm32c0xx_it.o \ +./Application/User/Core/syscalls.o \ +./Application/User/Core/sysmem.o \ +./Application/User/Core/tim.o \ +./Application/User/Core/usart.o + +C_DEPS += \ +./Application/User/Core/adc.d \ +./Application/User/Core/dma.d \ +./Application/User/Core/gpio.d \ +./Application/User/Core/main.d \ +./Application/User/Core/stm32c0xx_hal_msp.d \ +./Application/User/Core/stm32c0xx_it.d \ +./Application/User/Core/syscalls.d \ +./Application/User/Core/sysmem.d \ +./Application/User/Core/tim.d \ +./Application/User/Core/usart.d + + +# Each subdirectory must supply rules for building sources it contributes +Application/User/Core/adc.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/dma.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/gpio.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/main.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/stm32c0xx_hal_msp.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/stm32c0xx_it.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/%.o Application/User/Core/%.su Application/User/Core/%.cyclo: ../Application/User/Core/%.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/tim.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/usart.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Application-2f-User-2f-Core + +clean-Application-2f-User-2f-Core: + -$(RM) ./Application/User/Core/adc.cyclo ./Application/User/Core/adc.d ./Application/User/Core/adc.o ./Application/User/Core/adc.su ./Application/User/Core/dma.cyclo ./Application/User/Core/dma.d ./Application/User/Core/dma.o ./Application/User/Core/dma.su ./Application/User/Core/gpio.cyclo ./Application/User/Core/gpio.d ./Application/User/Core/gpio.o ./Application/User/Core/gpio.su ./Application/User/Core/main.cyclo ./Application/User/Core/main.d ./Application/User/Core/main.o ./Application/User/Core/main.su ./Application/User/Core/stm32c0xx_hal_msp.cyclo ./Application/User/Core/stm32c0xx_hal_msp.d ./Application/User/Core/stm32c0xx_hal_msp.o ./Application/User/Core/stm32c0xx_hal_msp.su ./Application/User/Core/stm32c0xx_it.cyclo ./Application/User/Core/stm32c0xx_it.d ./Application/User/Core/stm32c0xx_it.o ./Application/User/Core/stm32c0xx_it.su ./Application/User/Core/syscalls.cyclo ./Application/User/Core/syscalls.d ./Application/User/Core/syscalls.o ./Application/User/Core/syscalls.su ./Application/User/Core/sysmem.cyclo ./Application/User/Core/sysmem.d ./Application/User/Core/sysmem.o ./Application/User/Core/sysmem.su ./Application/User/Core/tim.cyclo ./Application/User/Core/tim.d ./Application/User/Core/tim.o ./Application/User/Core/tim.su ./Application/User/Core/usart.cyclo ./Application/User/Core/usart.d ./Application/User/Core/usart.o ./Application/User/Core/usart.su + +.PHONY: clean-Application-2f-User-2f-Core + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.cyclo (revision 41) @@ -0,0 +1,18 @@ +../Application/User/Core/syscalls.c:44:6:initialise_monitor_handles 1 +../Application/User/Core/syscalls.c:48:5:_getpid 1 +../Application/User/Core/syscalls.c:53:5:_kill 1 +../Application/User/Core/syscalls.c:61:6:_exit 1 +../Application/User/Core/syscalls.c:67:27:_read 2 +../Application/User/Core/syscalls.c:80:27:_write 2 +../Application/User/Core/syscalls.c:92:5:_close 1 +../Application/User/Core/syscalls.c:99:5:_fstat 1 +../Application/User/Core/syscalls.c:106:5:_isatty 1 +../Application/User/Core/syscalls.c:112:5:_lseek 1 +../Application/User/Core/syscalls.c:120:5:_open 1 +../Application/User/Core/syscalls.c:128:5:_wait 1 +../Application/User/Core/syscalls.c:135:5:_unlink 1 +../Application/User/Core/syscalls.c:142:5:_times 1 +../Application/User/Core/syscalls.c:148:5:_stat 1 +../Application/User/Core/syscalls.c:155:5:_link 1 +../Application/User/Core/syscalls.c:163:5:_fork 1 +../Application/User/Core/syscalls.c:169:5:_execve 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.d (revision 41) @@ -0,0 +1,1 @@ +Application/User/Core/syscalls.o: ../Application/User/Core/syscalls.c Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/syscalls.su (revision 41) @@ -0,0 +1,18 @@ +../Application/User/Core/syscalls.c:44:6:initialise_monitor_handles 0 static +../Application/User/Core/syscalls.c:48:5:_getpid 0 static +../Application/User/Core/syscalls.c:53:5:_kill 8 static +../Application/User/Core/syscalls.c:61:6:_exit 8 static +../Application/User/Core/syscalls.c:67:27:_read 16 static +../Application/User/Core/syscalls.c:80:27:_write 16 static +../Application/User/Core/syscalls.c:92:5:_close 0 static +../Application/User/Core/syscalls.c:99:5:_fstat 0 static +../Application/User/Core/syscalls.c:106:5:_isatty 0 static +../Application/User/Core/syscalls.c:112:5:_lseek 0 static +../Application/User/Core/syscalls.c:120:5:_open 0 static +../Application/User/Core/syscalls.c:128:5:_wait 8 static +../Application/User/Core/syscalls.c:135:5:_unlink 8 static +../Application/User/Core/syscalls.c:142:5:_times 0 static +../Application/User/Core/syscalls.c:148:5:_stat 0 static +../Application/User/Core/syscalls.c:155:5:_link 8 static +../Application/User/Core/syscalls.c:163:5:_fork 8 static +../Application/User/Core/syscalls.c:169:5:_execve 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.cyclo (revision 41) @@ -0,0 +1,1 @@ +../Application/User/Core/sysmem.c:53:7:_sbrk 3 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.d (revision 41) @@ -0,0 +1,1 @@ +Application/User/Core/sysmem.o: ../Application/User/Core/sysmem.c Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/sysmem.su (revision 41) @@ -0,0 +1,1 @@ +../Application/User/Core/sysmem.c:53:7:_sbrk 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.cyclo (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:37:6:MX_TIM16_Init 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:140:6:HAL_TIM_Base_MspInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:182:6:HAL_TIM_MspPostInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:78:6:MX_TIM17_Init 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:212:6:HAL_TIM_Base_MspDeInit 3 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/tim.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c \ + ../../Core/Inc/tim.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/tim.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/tim.su (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:37:6:MX_TIM16_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:140:6:HAL_TIM_Base_MspInit 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:182:6:HAL_TIM_MspPostInit 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:78:6:MX_TIM17_Init 88 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:212:6:HAL_TIM_Base_MspDeInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.cyclo (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:31:6:MX_USART1_UART_Init 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:74:6:HAL_UART_MspInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:122:6:HAL_UART_MspDeInit 2 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/usart.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c \ + ../../Core/Inc/usart.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/usart.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Core/usart.su (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:31:6:MX_USART1_UART_Init 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:74:6:HAL_UART_MspInit 80 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:122:6:HAL_UART_MspDeInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Startup/startup_stm32c031k4tx.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Startup/startup_stm32c031k4tx.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Startup/startup_stm32c031k4tx.d (revision 41) @@ -0,0 +1,2 @@ +Application/User/Startup/startup_stm32c031k4tx.o: \ + ../Application/User/Startup/startup_stm32c031k4tx.s Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Startup/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Startup/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Application/User/Startup/subdir.mk (revision 41) @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Application/User/Startup/startup_stm32c031k4tx.s + +OBJS += \ +./Application/User/Startup/startup_stm32c031k4tx.o + +S_DEPS += \ +./Application/User/Startup/startup_stm32c031k4tx.d + + +# Each subdirectory must supply rules for building sources it contributes +Application/User/Startup/%.o: ../Application/User/Startup/%.s Application/User/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -DDEBUG -c -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Application-2f-User-2f-Startup + +clean-Application-2f-User-2f-Startup: + -$(RM) ./Application/User/Startup/startup_stm32c031k4tx.d ./Application/User/Startup/startup_stm32c031k4tx.o + +.PHONY: clean-Application-2f-User-2f-Startup + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/subdir.mk (revision 41) @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c + +OBJS += \ +./Drivers/CMSIS/system_stm32c0xx.o + +C_DEPS += \ +./Drivers/CMSIS/system_stm32c0xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/system_stm32c0xx.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c Drivers/CMSIS/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS + +clean-Drivers-2f-CMSIS: + -$(RM) ./Drivers/CMSIS/system_stm32c0xx.cyclo ./Drivers/CMSIS/system_stm32c0xx.d ./Drivers/CMSIS/system_stm32c0xx.o ./Drivers/CMSIS/system_stm32c0xx.su + +.PHONY: clean-Drivers-2f-CMSIS + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.cyclo (revision 41) @@ -0,0 +1,2 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:142:6:SystemInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate 4 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/CMSIS/system_stm32c0xx.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/CMSIS/system_stm32c0xx.su (revision 41) @@ -0,0 +1,2 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:142:6:SystemInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo (revision 41) @@ -0,0 +1,27 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:332:19:HAL_SetTickFreq 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:357:21:HAL_GetTickFreq 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:373:13:HAL_Delay 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:399:13:HAL_SuspendTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:415:13:HAL_ResumeTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:425:10:HAL_GetHalVersion 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:434:10:HAL_GetREVID 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:443:10:HAL_GetDEVID 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:452:10:HAL_GetUIDw0 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:461:10:HAL_GetUIDw1 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:470:10:HAL_GetUIDw2 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:498:6:HAL_DBGMCU_EnableDBGStopMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:507:6:HAL_DBGMCU_DisableDBGStopMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:554:6:HAL_SYSCFG_EnableRemap 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:569:6:HAL_SYSCFG_DisableRemap 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:582:6:HAL_SYSCFG_SetPinBinding 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:595:10:HAL_SYSCFG_GetPinBinding 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su (revision 41) @@ -0,0 +1,27 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:332:19:HAL_SetTickFreq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:357:21:HAL_GetTickFreq 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:373:13:HAL_Delay 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:399:13:HAL_SuspendTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:415:13:HAL_ResumeTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:425:10:HAL_GetHalVersion 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:434:10:HAL_GetREVID 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:443:10:HAL_GetDEVID 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:452:10:HAL_GetUIDw0 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:461:10:HAL_GetUIDw1 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:470:10:HAL_GetUIDw2 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:498:6:HAL_DBGMCU_EnableDBGStopMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:507:6:HAL_DBGMCU_DisableDBGStopMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:554:6:HAL_SYSCFG_EnableRemap 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:569:6:HAL_SYSCFG_DisableRemap 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:582:6:HAL_SYSCFG_SetPinBinding 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:595:10:HAL_SYSCFG_GetPinBinding 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo (revision 41) @@ -0,0 +1,32 @@ +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4004:22:LL_ADC_SetAnalogWDMonitChannels 2 +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4231:22:LL_ADC_ConfigAnalogWDThresholds 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:874:13:HAL_ADC_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:387:19:HAL_ADC_Init 22 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:891:13:HAL_ADC_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1282:19:HAL_ADC_PollForConversion 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1412:19:HAL_ADC_PollForEvent 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1865:10:HAL_ADC_GetValue 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2130:13:HAL_ADC_ConvCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2145:13:HAL_ADC_ConvHalfCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3017:13:ADC_DMAHalfConvCplt 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2160:13:HAL_ADC_LevelOutOfWindowCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2182:13:HAL_ADC_ErrorCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3035:13:ADC_DMAError 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2939:13:ADC_DMAConvCplt 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2197:13:HAL_ADC_CalibrationCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2212:13:HAL_ADC_ADCReadyCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1882:6:HAL_ADC_IRQHandler 30 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2258:19:HAL_ADC_ConfigChannel 42 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2701:10:HAL_ADC_GetState 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2715:10:HAL_ADC_GetError 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2742:19:ADC_ConversionStop 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2792:19:ADC_Enable 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1158:19:HAL_ADC_Start 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1539:19:HAL_ADC_Start_IT 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1683:19:HAL_ADC_Start_DMA 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2881:19:ADC_Disable 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:742:19:HAL_ADC_DeInit 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1228:19:HAL_ADC_Stop 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1633:19:HAL_ADC_Stop_IT 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1781:19:HAL_ADC_Stop_DMA 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2458:19:HAL_ADC_AnalogWDGConfig 65 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su (revision 41) @@ -0,0 +1,32 @@ +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4004:22:LL_ADC_SetAnalogWDMonitChannels 8 static +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4231:22:LL_ADC_ConfigAnalogWDThresholds 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:874:13:HAL_ADC_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:387:19:HAL_ADC_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:891:13:HAL_ADC_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1282:19:HAL_ADC_PollForConversion 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1412:19:HAL_ADC_PollForEvent 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1865:10:HAL_ADC_GetValue 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2130:13:HAL_ADC_ConvCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2145:13:HAL_ADC_ConvHalfCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3017:13:ADC_DMAHalfConvCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2160:13:HAL_ADC_LevelOutOfWindowCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2182:13:HAL_ADC_ErrorCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3035:13:ADC_DMAError 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2939:13:ADC_DMAConvCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2197:13:HAL_ADC_CalibrationCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2212:13:HAL_ADC_ADCReadyCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1882:6:HAL_ADC_IRQHandler 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2258:19:HAL_ADC_ConfigChannel 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2701:10:HAL_ADC_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2715:10:HAL_ADC_GetError 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2742:19:ADC_ConversionStop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2792:19:ADC_Enable 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1158:19:HAL_ADC_Start 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1539:19:HAL_ADC_Start_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1683:19:HAL_ADC_Start_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2881:19:ADC_Disable 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:742:19:HAL_ADC_DeInit 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1228:19:HAL_ADC_Stop 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1633:19:HAL_ADC_Stop_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1781:19:HAL_ADC_Stop_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2458:19:HAL_ADC_AnalogWDGConfig 24 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo (revision 41) @@ -0,0 +1,8 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:105:19:HAL_ADCEx_Calibration_Start 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:252:10:HAL_ADCEx_Calibration_GetValue 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:268:19:HAL_ADCEx_Calibration_SetValue 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:314:13:HAL_ADCEx_LevelOutOfWindow2Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:329:13:HAL_ADCEx_LevelOutOfWindow3Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:345:13:HAL_ADCEx_EndOfSamplingCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:360:13:HAL_ADCEx_ChannelConfigReadyCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:383:19:HAL_ADCEx_DisableVoltageRegulator 2 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su (revision 41) @@ -0,0 +1,8 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:105:19:HAL_ADCEx_Calibration_Start 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:252:10:HAL_ADCEx_Calibration_GetValue 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:268:19:HAL_ADCEx_Calibration_SetValue 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:314:13:HAL_ADCEx_LevelOutOfWindow2Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:329:13:HAL_ADCEx_LevelOutOfWindow3Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:345:13:HAL_ADCEx_EndOfSamplingCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:360:13:HAL_ADCEx_ChannelConfigReadyCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:383:19:HAL_ADCEx_DisableVoltageRegulator 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo (revision 41) @@ -0,0 +1,21 @@ +../../Drivers/CMSIS/Include/core_cm0plus.h:850:22:__NVIC_SetPriority 2 +../../Drivers/CMSIS/Include/core_cm0plus.h:874:26:__NVIC_GetPriority 2 +../../Drivers/CMSIS/Include/core_cm0plus.h:987:34:__NVIC_SystemReset 1 +../../Drivers/CMSIS/Include/core_cm0plus.h:1058:26:SysTick_Config 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset 0 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:380:6:HAL_MPU_DisableRegion 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:398:6:HAL_MPU_ConfigRegion 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su (revision 41) @@ -0,0 +1,21 @@ +../../Drivers/CMSIS/Include/core_cm0plus.h:850:22:__NVIC_SetPriority 16 static +../../Drivers/CMSIS/Include/core_cm0plus.h:874:26:__NVIC_GetPriority 0 static +../../Drivers/CMSIS/Include/core_cm0plus.h:987:34:__NVIC_SystemReset 0 static,ignoring_inline_asm +../../Drivers/CMSIS/Include/core_cm0plus.h:1058:26:SysTick_Config 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:380:6:HAL_MPU_DisableRegion 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:398:6:HAL_MPU_ConfigRegion 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo (revision 41) @@ -0,0 +1,15 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1047:13:DMA_CalcDMAMUXRequestGenBaseAndMask 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:345:19:HAL_DMA_Start 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:392:19:HAL_DMA_Start_IT 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer 13 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:724:6:HAL_DMA_IRQHandler 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su (revision 41) @@ -0,0 +1,15 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig 20 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1047:13:DMA_CalcDMAMUXRequestGenBaseAndMask 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:345:19:HAL_DMA_Start 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:392:19:HAL_DMA_Start_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:724:6:HAL_DMA_IRQHandler 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:94:19:HAL_DMAEx_ConfigMuxSync 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:142:19:HAL_DMAEx_ConfigMuxRequestGenerator 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:208:19:HAL_DMAEx_DisableMuxRequestGenerator 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:236:6:HAL_DMAEx_MUX_IRQHandler 6 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:94:19:HAL_DMAEx_ConfigMuxSync 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:142:19:HAL_DMAEx_ConfigMuxRequestGenerator 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:208:19:HAL_DMAEx_DisableMuxRequestGenerator 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:236:6:HAL_DMAEx_MUX_IRQHandler 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo (revision 41) @@ -0,0 +1,9 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:588:6:HAL_EXTI_ClearPending 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:624:6:HAL_EXTI_GenerateSWI 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su (revision 41) @@ -0,0 +1,9 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:588:6:HAL_EXTI_ClearPending 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:624:6:HAL_EXTI_GenerateSWI 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo (revision 41) @@ -0,0 +1,14 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:631:13:FLASH_Program_DoubleWord 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT 4 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su (revision 41) @@ -0,0 +1,14 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:631:13:FLASH_Program_DoubleWord 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT 32 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo (revision 41) @@ -0,0 +1,23 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:479:13:FLASH_MassErase 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:543:13:FLASH_OB_WRPConfig 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:594:13:FLASH_OB_OptrConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:624:13:FLASH_OB_PCROP1AConfig 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:676:13:FLASH_OB_PCROP1BConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:705:13:FLASH_OB_SecMemConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:730:13:FLASH_OB_GetWRP 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:756:17:FLASH_OB_GetRDP 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:792:17:FLASH_OB_GetUser 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:807:13:FLASH_OB_GetPCROP1A 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:832:13:FLASH_OB_GetPCROP1B 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:852:13:FLASH_OB_GetSecMem 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches 2 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su (revision 41) @@ -0,0 +1,23 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:479:13:FLASH_MassErase 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:543:13:FLASH_OB_WRPConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:594:13:FLASH_OB_OptrConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:624:13:FLASH_OB_PCROP1AConfig 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:676:13:FLASH_OB_PCROP1BConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:705:13:FLASH_OB_SecMemConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:730:13:FLASH_OB_GetWRP 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:756:17:FLASH_OB_GetRDP 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:792:17:FLASH_OB_GetUser 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:807:13:FLASH_OB_GetPCROP1A 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:832:13:FLASH_OB_GetPCROP1B 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:852:13:FLASH_OB_GetSecMem 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init 19 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler 3 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit 28 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:73:6:HAL_PWR_DeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:207:6:HAL_PWR_EnableWakeUpPin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:228:6:HAL_PWR_DisableWakeUpPin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:252:6:HAL_PWR_EnterSLEEPMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:300:6:HAL_PWR_EnterSTOPMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:343:6:HAL_PWR_EnterSTANDBYMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:364:6:HAL_PWR_EnableSleepOnExit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:377:6:HAL_PWR_DisableSleepOnExit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:390:6:HAL_PWR_EnableSEVOnPend 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:402:6:HAL_PWR_DisableSEVOnPend 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:73:6:HAL_PWR_DeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:207:6:HAL_PWR_EnableWakeUpPin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:228:6:HAL_PWR_DisableWakeUpPin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:252:6:HAL_PWR_EnterSLEEPMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:300:6:HAL_PWR_EnterSTOPMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:343:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:364:6:HAL_PWR_EnableSleepOnExit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:377:6:HAL_PWR_DisableSleepOnExit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:390:6:HAL_PWR_EnableSEVOnPend 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:402:6:HAL_PWR_DisableSEVOnPend 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo (revision 41) @@ -0,0 +1,13 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:163:6:HAL_PWREx_EnableInternalWakeUpLine 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableInternalWakeUpLine 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:198:19:HAL_PWREx_EnableGPIOPullUp 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:254:19:HAL_PWREx_DisableGPIOPullUp 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:311:19:HAL_PWREx_EnableGPIOPullDown 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:367:19:HAL_PWREx_DisableGPIOPullDown 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:415:6:HAL_PWREx_EnablePullUpPullDownConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:426:6:HAL_PWREx_DisablePullUpPullDownConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:440:6:HAL_PWREx_EnableFlashPowerDown 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:456:6:HAL_PWREx_DisableFlashPowerDown 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:481:6:HAL_PWREx_EnterSHUTDOWNMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:525:6:HAL_PWREx_BKUPWrite 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:546:10:HAL_PWREx_BKUPRead 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su (revision 41) @@ -0,0 +1,13 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:163:6:HAL_PWREx_EnableInternalWakeUpLine 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableInternalWakeUpLine 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:198:19:HAL_PWREx_EnableGPIOPullUp 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:254:19:HAL_PWREx_DisableGPIOPullUp 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:311:19:HAL_PWREx_EnableGPIOPullDown 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:367:19:HAL_PWREx_DisableGPIOPullDown 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:415:6:HAL_PWREx_EnablePullUpPullDownConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:426:6:HAL_PWREx_DisablePullUpPullDownConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:440:6:HAL_PWREx_EnableFlashPowerDown 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:456:6:HAL_PWREx_DisableFlashPowerDown 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:481:6:HAL_PWREx_EnterSHUTDOWNMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:525:6:HAL_PWREx_BKUPWrite 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:546:10:HAL_PWREx_BKUPRead 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo (revision 41) @@ -0,0 +1,15 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig 39 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig 21 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:996:10:HAL_RCC_GetHCLKFreq 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1009:10:HAL_RCC_GetPCLK1Freq 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1082:6:HAL_RCC_GetClockConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler 3 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su (revision 41) @@ -0,0 +1,15 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig 48 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:996:10:HAL_RCC_GetHCLKFreq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1009:10:HAL_RCC_GetPCLK1Freq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1082:6:HAL_RCC_GetClockConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig 15 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq 30 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:520:6:HAL_RCCEx_EnableLSCO 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:520:6:HAL_RCCEx_EnableLSCO 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo (revision 41) @@ -0,0 +1,121 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7330:13:TIM_OC6_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7566:13:TIM_TI1_ConfigInputStage 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7609:13:TIM_TI2_SetConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7649:13:TIM_TI2_ConfigInputStage 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7692:13:TIM_TI3_SetConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7740:13:TIM_TI4_SetConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7783:13:TIM_ITRx_SetConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:380:13:HAL_TIM_Base_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:395:13:HAL_TIM_Base_MspDeInit 1 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3487:19:HAL_TIM_Encoder_Stop_IT 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3552:19:HAL_TIM_Encoder_Start_DMA 32 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3765:19:HAL_TIM_Encoder_Stop_DMA 7 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su (revision 41) @@ -0,0 +1,121 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7330:13:TIM_OC6_SetConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7566:13:TIM_TI1_ConfigInputStage 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7609:13:TIM_TI2_SetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7649:13:TIM_TI2_ConfigInputStage 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7692:13:TIM_TI3_SetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7740:13:TIM_TI4_SetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7783:13:TIM_ITRx_SetConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:380:13:HAL_TIM_Base_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:395:13:HAL_TIM_Base_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:337:19:HAL_TIM_Base_DeInit 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:411:19:HAL_TIM_Base_Start 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:450:19:HAL_TIM_Base_Stop 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:470:19:HAL_TIM_Base_Start_IT 0 static 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=================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo (revision 41) @@ -0,0 +1,48 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:313:13:HAL_TIMEx_HallSensor_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:253:19:HAL_TIMEx_HallSensor_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:328:19:HAL_TIMEx_HallSensor_Start 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:382:19:HAL_TIMEx_HallSensor_Stop 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:410:19:HAL_TIMEx_HallSensor_Start_IT 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:467:19:HAL_TIMEx_HallSensor_Stop_IT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:500:19:HAL_TIMEx_HallSensor_Start_DMA 12 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2529:13:HAL_TIMEx_CommutCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2543:13:HAL_TIMEx_CommutHalfCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState 4 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su (revision 41) @@ -0,0 +1,48 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init 56 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:313:13:HAL_TIMEx_HallSensor_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:253:19:HAL_TIMEx_HallSensor_DeInit 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:328:19:HAL_TIMEx_HallSensor_Start 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:382:19:HAL_TIMEx_HallSensor_Stop 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:410:19:HAL_TIMEx_HallSensor_Start_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:467:19:HAL_TIMEx_HallSensor_Stop_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:500:19:HAL_TIMEx_HallSensor_Start_DMA 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:576:19:HAL_TIMEx_HallSensor_Stop_DMA 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:638:19:HAL_TIMEx_OCN_Start 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:689:19:HAL_TIMEx_OCN_Stop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:721:19:HAL_TIMEx_OCN_Start_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:808:19:HAL_TIMEx_OCN_Stop_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:883:19:HAL_TIMEx_OCN_Start_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1021:19:HAL_TIMEx_OCN_Stop_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1111:19:HAL_TIMEx_PWMN_Start 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1161:19:HAL_TIMEx_PWMN_Stop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1193:19:HAL_TIMEx_PWMN_Start_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1279:19:HAL_TIMEx_PWMN_Stop_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Start_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1492:19:HAL_TIMEx_PWMN_Stop_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1583:19:HAL_TIMEx_OnePulseN_Start 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1632:19:HAL_TIMEx_OnePulseN_Stop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1671:19:HAL_TIMEx_OnePulseN_Start_IT 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1726:19:HAL_TIMEx_OnePulseN_Stop_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1811:19:HAL_TIMEx_ConfigCommutEvent 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1877:19:HAL_TIMEx_ConfigCommutEvent_IT 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1944:19:HAL_TIMEx_ConfigCommutEvent_DMA 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1999:19:HAL_TIMEx_MasterConfigSynchronization 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2072:19:HAL_TIMEx_ConfigBreakDeadTime 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2140:19:HAL_TIMEx_ConfigBreakInput 20 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2251:19:HAL_TIMEx_RemapConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2306:20:HAL_TIMEx_TISelection 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2348:19:HAL_TIMEx_GroupChannel5 20 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2386:19:HAL_TIMEx_DisarmBreakInput 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2440:19:HAL_TIMEx_ReArmBreakInput 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2529:13:HAL_TIMEx_CommutCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2543:13:HAL_TIMEx_CommutHalfCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo (revision 41) @@ -0,0 +1,70 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4166:13:UART_TxISR_16BIT_FIFOEN 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:679:13:HAL_UART_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:694:13:HAL_UART_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:632:19:HAL_UART_DeInit 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1332:19:HAL_UART_Transmit_IT 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1471:19:HAL_UART_Transmit_DMA 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1601:19:HAL_UART_DMAPause 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1631:19:HAL_UART_DMAResume 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1662:19:HAL_UART_DMAStop 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1738:19:HAL_UART_Abort 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1843:19:HAL_UART_AbortTransmit 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1904:19:HAL_UART_AbortReceive 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2675:13:HAL_UART_TxCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3656:13:UART_DMATransmitCplt 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4207:13:UART_EndTransmit_IT 1 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA 8 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su (revision 41) @@ -0,0 +1,70 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT 8 static,ignoring_inline_asm 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static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1601:19:HAL_UART_DMAPause 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1631:19:HAL_UART_DMAResume 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1662:19:HAL_UART_DMAStop 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1738:19:HAL_UART_Abort 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1843:19:HAL_UART_AbortTransmit 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1904:19:HAL_UART_AbortReceive 16 static,ignoring_inline_asm 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0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2735:13:HAL_UART_ErrorCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3829:13:UART_DMAError 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3869:13:UART_DMAAbortOnError 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2750:13:HAL_UART_AbortCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1974:19:HAL_UART_Abort_IT 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3946:13:UART_DMARxAbortCallback 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3891:13:UART_DMATxAbortCallback 8 static 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2797:13:HAL_UARTEx_RxEventCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2317:6:HAL_UART_IRQHandler 24 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4232:13:UART_RxISR_8BIT 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4320:13:UART_RxISR_16BIT 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4410:13:UART_RxISR_8BIT_FIFOEN 32 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4570:13:UART_RxISR_16BIT_FIFOEN 32 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3781:13:UART_DMARxHalfCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3708:13:UART_DMAReceiveCplt 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2845:6:HAL_UART_ReceiverTimeout_Config 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2857:19:HAL_UART_EnableReceiverTimeout 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2888:19:HAL_UART_DisableReceiverTimeout 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2959:6:HAL_MultiProcessor_EnterMuteMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2969:19:HAL_HalfDuplex_EnableTransmitter 20 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2992:19:HAL_HalfDuplex_EnableReceiver 20 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3016:19:HAL_LIN_SendBreak 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3061:23:HAL_UART_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3077:10:HAL_UART_GetError 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3123:19:UART_SetConfig 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3269:6:UART_AdvFeatureConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1126:19:HAL_UART_Transmit 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1232:19:HAL_UART_Receive 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3345:19:UART_CheckIdleState 24 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:307:19:HAL_UART_Init 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:382:19:HAL_HalfDuplex_Init 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:457:19:HAL_LIN_Init 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:556:19:HAL_MultiProcessor_Init 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3555:19:UART_Start_Receive_DMA 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA 16 static,ignoring_inline_asm Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo (revision 41) @@ -0,0 +1,18 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1031:13:UARTEx_Wakeup_AddressConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle 23 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su (revision 41) @@ -0,0 +1,18 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1031:13:UARTEx_Wakeup_AddressConfig 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/Drivers/STM32C0xx_HAL_Driver/subdir.mk (revision 41) @@ -0,0 +1,112 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32C0xx_HAL_Driver + +clean-Drivers-2f-STM32C0xx_HAL_Driver: + -$(RM) ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su + +.PHONY: clean-Drivers-2f-STM32C0xx_HAL_Driver + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/firmware_v2.list =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/firmware_v2.list (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/firmware_v2.list (revision 41) @@ -0,0 +1,6323 @@ + +firmware_v2.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000000c0 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000026a8 080000c0 080000c0 000010c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000244 08002768 08002768 00003768 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 080029ac 080029ac 00004068 2**0 + CONTENTS, READONLY + 4 .ARM 00000000 080029ac 080029ac 00004068 2**0 + CONTENTS, READONLY + 5 .preinit_array 00000000 080029ac 080029ac 00004068 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 080029ac 080029ac 000039ac 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 080029b0 080029b0 000039b0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 00000068 20000000 080029b4 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000234 20000068 08002a1c 00004068 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000029c 08002a1c 0000429c 2**0 + ALLOC + 11 .ARM.attributes 00000028 00000000 00000000 00004068 2**0 + CONTENTS, READONLY + 12 .debug_info 000077b2 00000000 00000000 00004090 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00002266 00000000 00000000 0000b842 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_loclists 00001831 00000000 00000000 0000daa8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_aranges 000006c8 00000000 00000000 0000f2e0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_rnglists 000004f6 00000000 00000000 0000f9a8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_macro 00016e46 00000000 00000000 0000fe9e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line 0000ce5f 00000000 00000000 00026ce4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_str 000898c0 00000000 00000000 00033b43 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .comment 00000043 00000000 00000000 000bd403 2**0 + CONTENTS, READONLY + 21 .debug_frame 00001620 00000000 00000000 000bd448 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line_str 00000072 00000000 00000000 000bea68 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080000c0 <__do_global_dtors_aux>: + 80000c0: b510 push {r4, lr} + 80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>) + 80000c4: 7823 ldrb r3, [r4, #0] + 80000c6: 2b00 cmp r3, #0 + 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> + 80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>) + 80000cc: 2b00 cmp r3, #0 + 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>) + 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d4: bf00 nop + 80000d6: 2301 movs r3, #1 + 80000d8: 7023 strb r3, [r4, #0] + 80000da: bd10 pop {r4, pc} + 80000dc: 20000068 .word 0x20000068 + 80000e0: 00000000 .word 0x00000000 + 80000e4: 08002750 .word 0x08002750 + +080000e8 : + 80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc ) + 80000ea: b510 push {r4, lr} + 80000ec: 2b00 cmp r3, #0 + 80000ee: d003 beq.n 80000f8 + 80000f0: 4903 ldr r1, [pc, #12] @ (8000100 ) + 80000f2: 4804 ldr r0, [pc, #16] @ (8000104 ) + 80000f4: e000 b.n 80000f8 + 80000f6: bf00 nop + 80000f8: bd10 pop {r4, pc} + 80000fa: 46c0 nop @ (mov r8, r8) + 80000fc: 00000000 .word 0x00000000 + 8000100: 2000006c .word 0x2000006c + 8000104: 08002750 .word 0x08002750 + +08000108 <__gnu_thumb1_case_shi>: + 8000108: b403 push {r0, r1} + 800010a: 4671 mov r1, lr + 800010c: 0849 lsrs r1, r1, #1 + 800010e: 0040 lsls r0, r0, #1 + 8000110: 0049 lsls r1, r1, #1 + 8000112: 5e09 ldrsh r1, [r1, r0] + 8000114: 0049 lsls r1, r1, #1 + 8000116: 448e add lr, r1 + 8000118: bc03 pop {r0, r1} + 800011a: 4770 bx lr + +0800011c <__udivsi3>: + 800011c: 2200 movs r2, #0 + 800011e: 0843 lsrs r3, r0, #1 + 8000120: 428b cmp r3, r1 + 8000122: d374 bcc.n 800020e <__udivsi3+0xf2> + 8000124: 0903 lsrs r3, r0, #4 + 8000126: 428b cmp r3, r1 + 8000128: d35f bcc.n 80001ea <__udivsi3+0xce> + 800012a: 0a03 lsrs r3, r0, #8 + 800012c: 428b cmp r3, r1 + 800012e: d344 bcc.n 80001ba <__udivsi3+0x9e> + 8000130: 0b03 lsrs r3, r0, #12 + 8000132: 428b cmp r3, r1 + 8000134: d328 bcc.n 8000188 <__udivsi3+0x6c> + 8000136: 0c03 lsrs r3, r0, #16 + 8000138: 428b cmp r3, r1 + 800013a: d30d bcc.n 8000158 <__udivsi3+0x3c> + 800013c: 22ff movs r2, #255 @ 0xff + 800013e: 0209 lsls r1, r1, #8 + 8000140: ba12 rev r2, r2 + 8000142: 0c03 lsrs r3, r0, #16 + 8000144: 428b cmp r3, r1 + 8000146: d302 bcc.n 800014e <__udivsi3+0x32> + 8000148: 1212 asrs r2, r2, #8 + 800014a: 0209 lsls r1, r1, #8 + 800014c: d065 beq.n 800021a <__udivsi3+0xfe> + 800014e: 0b03 lsrs r3, r0, #12 + 8000150: 428b cmp r3, r1 + 8000152: d319 bcc.n 8000188 <__udivsi3+0x6c> + 8000154: e000 b.n 8000158 <__udivsi3+0x3c> + 8000156: 0a09 lsrs r1, r1, #8 + 8000158: 0bc3 lsrs r3, r0, #15 + 800015a: 428b cmp r3, r1 + 800015c: d301 bcc.n 8000162 <__udivsi3+0x46> + 800015e: 03cb lsls r3, r1, #15 + 8000160: 1ac0 subs r0, r0, r3 + 8000162: 4152 adcs r2, r2 + 8000164: 0b83 lsrs r3, r0, #14 + 8000166: 428b cmp r3, r1 + 8000168: d301 bcc.n 800016e <__udivsi3+0x52> + 800016a: 038b lsls r3, r1, #14 + 800016c: 1ac0 subs r0, r0, r3 + 800016e: 4152 adcs r2, r2 + 8000170: 0b43 lsrs r3, r0, #13 + 8000172: 428b cmp r3, r1 + 8000174: d301 bcc.n 800017a <__udivsi3+0x5e> + 8000176: 034b lsls r3, r1, #13 + 8000178: 1ac0 subs r0, r0, r3 + 800017a: 4152 adcs r2, r2 + 800017c: 0b03 lsrs r3, r0, #12 + 800017e: 428b cmp r3, r1 + 8000180: d301 bcc.n 8000186 <__udivsi3+0x6a> + 8000182: 030b lsls r3, r1, #12 + 8000184: 1ac0 subs r0, r0, r3 + 8000186: 4152 adcs r2, r2 + 8000188: 0ac3 lsrs r3, r0, #11 + 800018a: 428b cmp r3, r1 + 800018c: d301 bcc.n 8000192 <__udivsi3+0x76> + 800018e: 02cb lsls r3, r1, #11 + 8000190: 1ac0 subs r0, r0, r3 + 8000192: 4152 adcs r2, r2 + 8000194: 0a83 lsrs r3, r0, #10 + 8000196: 428b cmp r3, r1 + 8000198: d301 bcc.n 800019e <__udivsi3+0x82> + 800019a: 028b lsls r3, r1, #10 + 800019c: 1ac0 subs r0, r0, r3 + 800019e: 4152 adcs r2, r2 + 80001a0: 0a43 lsrs r3, r0, #9 + 80001a2: 428b cmp r3, r1 + 80001a4: d301 bcc.n 80001aa <__udivsi3+0x8e> + 80001a6: 024b lsls r3, r1, #9 + 80001a8: 1ac0 subs r0, r0, r3 + 80001aa: 4152 adcs r2, r2 + 80001ac: 0a03 lsrs r3, r0, #8 + 80001ae: 428b cmp r3, r1 + 80001b0: d301 bcc.n 80001b6 <__udivsi3+0x9a> + 80001b2: 020b lsls r3, r1, #8 + 80001b4: 1ac0 subs r0, r0, r3 + 80001b6: 4152 adcs r2, r2 + 80001b8: d2cd bcs.n 8000156 <__udivsi3+0x3a> + 80001ba: 09c3 lsrs r3, r0, #7 + 80001bc: 428b cmp r3, r1 + 80001be: d301 bcc.n 80001c4 <__udivsi3+0xa8> + 80001c0: 01cb lsls r3, r1, #7 + 80001c2: 1ac0 subs r0, r0, r3 + 80001c4: 4152 adcs r2, r2 + 80001c6: 0983 lsrs r3, r0, #6 + 80001c8: 428b cmp r3, r1 + 80001ca: d301 bcc.n 80001d0 <__udivsi3+0xb4> + 80001cc: 018b lsls r3, r1, #6 + 80001ce: 1ac0 subs r0, r0, r3 + 80001d0: 4152 adcs r2, r2 + 80001d2: 0943 lsrs r3, r0, #5 + 80001d4: 428b cmp r3, r1 + 80001d6: d301 bcc.n 80001dc <__udivsi3+0xc0> + 80001d8: 014b lsls r3, r1, #5 + 80001da: 1ac0 subs r0, r0, r3 + 80001dc: 4152 adcs r2, r2 + 80001de: 0903 lsrs r3, r0, #4 + 80001e0: 428b cmp r3, r1 + 80001e2: d301 bcc.n 80001e8 <__udivsi3+0xcc> + 80001e4: 010b lsls r3, r1, #4 + 80001e6: 1ac0 subs r0, r0, r3 + 80001e8: 4152 adcs r2, r2 + 80001ea: 08c3 lsrs r3, r0, #3 + 80001ec: 428b cmp r3, r1 + 80001ee: d301 bcc.n 80001f4 <__udivsi3+0xd8> + 80001f0: 00cb lsls r3, r1, #3 + 80001f2: 1ac0 subs r0, r0, r3 + 80001f4: 4152 adcs r2, r2 + 80001f6: 0883 lsrs r3, r0, #2 + 80001f8: 428b cmp r3, r1 + 80001fa: d301 bcc.n 8000200 <__udivsi3+0xe4> + 80001fc: 008b lsls r3, r1, #2 + 80001fe: 1ac0 subs r0, r0, r3 + 8000200: 4152 adcs r2, r2 + 8000202: 0843 lsrs r3, r0, #1 + 8000204: 428b cmp r3, r1 + 8000206: d301 bcc.n 800020c <__udivsi3+0xf0> + 8000208: 004b lsls r3, r1, #1 + 800020a: 1ac0 subs r0, r0, r3 + 800020c: 4152 adcs r2, r2 + 800020e: 1a41 subs r1, r0, r1 + 8000210: d200 bcs.n 8000214 <__udivsi3+0xf8> + 8000212: 4601 mov r1, r0 + 8000214: 4152 adcs r2, r2 + 8000216: 4610 mov r0, r2 + 8000218: 4770 bx lr + 800021a: e7ff b.n 800021c <__udivsi3+0x100> + 800021c: b501 push {r0, lr} + 800021e: 2000 movs r0, #0 + 8000220: f000 f806 bl 8000230 <__aeabi_idiv0> + 8000224: bd02 pop {r1, pc} + 8000226: 46c0 nop @ (mov r8, r8) + +08000228 <__aeabi_uidivmod>: + 8000228: 2900 cmp r1, #0 + 800022a: d0f7 beq.n 800021c <__udivsi3+0x100> + 800022c: e776 b.n 800011c <__udivsi3> + 800022e: 4770 bx lr + +08000230 <__aeabi_idiv0>: + 8000230: 4770 bx lr + 8000232: 46c0 nop @ (mov r8, r8) + +08000234 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000234: b082 sub sp, #8 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000236: 4b0a ldr r3, [pc, #40] @ (8000260 ) + 8000238: 6c19 ldr r1, [r3, #64] @ 0x40 + 800023a: 2201 movs r2, #1 + 800023c: 4311 orrs r1, r2 + 800023e: 6419 str r1, [r3, #64] @ 0x40 + 8000240: 6c19 ldr r1, [r3, #64] @ 0x40 + 8000242: 400a ands r2, r1 + 8000244: 9200 str r2, [sp, #0] + 8000246: 9a00 ldr r2, [sp, #0] + __HAL_RCC_PWR_CLK_ENABLE(); + 8000248: 6bda ldr r2, [r3, #60] @ 0x3c + 800024a: 2180 movs r1, #128 @ 0x80 + 800024c: 0549 lsls r1, r1, #21 + 800024e: 430a orrs r2, r1 + 8000250: 63da str r2, [r3, #60] @ 0x3c + 8000252: 6bdb ldr r3, [r3, #60] @ 0x3c + 8000254: 400b ands r3, r1 + 8000256: 9301 str r3, [sp, #4] + 8000258: 9b01 ldr r3, [sp, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 800025a: b002 add sp, #8 + 800025c: 4770 bx lr + 800025e: 46c0 nop @ (mov r8, r8) + 8000260: 40021000 .word 0x40021000 + +08000264 : +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000264: e7fe b.n 8000264 + +08000266 : +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000266: e7fe b.n 8000266 + +08000268 : + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000268: 4770 bx lr + +0800026a : + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 800026a: 4770 bx lr + +0800026c : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800026c: b510 push {r4, lr} + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800026e: f000 f8bf bl 80003f0 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000272: bd10 pop {r4, pc} + +08000274 : + +/** + * @brief This function handles DMA1 channel 1 interrupt. + */ +void DMA1_Channel1_IRQHandler(void) +{ + 8000274: b510 push {r4, lr} + /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ + + /* USER CODE END DMA1_Channel1_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + 8000276: 4802 ldr r0, [pc, #8] @ (8000280 ) + 8000278: f000 f932 bl 80004e0 + /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ + + /* USER CODE END DMA1_Channel1_IRQn 1 */ +} + 800027c: bd10 pop {r4, pc} + 800027e: 46c0 nop @ (mov r8, r8) + 8000280: 20000084 .word 0x20000084 + +08000284 <_read>: + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + 8000284: b570 push {r4, r5, r6, lr} + 8000286: 000c movs r4, r1 + 8000288: 0016 movs r6, r2 + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 800028a: 2500 movs r5, #0 + 800028c: e004 b.n 8000298 <_read+0x14> + { + *ptr++ = __io_getchar(); + 800028e: e000 b.n 8000292 <_read+0xe> + 8000290: bf00 nop + 8000292: 7020 strb r0, [r4, #0] + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000294: 3501 adds r5, #1 + *ptr++ = __io_getchar(); + 8000296: 3401 adds r4, #1 + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000298: 42b5 cmp r5, r6 + 800029a: dbf8 blt.n 800028e <_read+0xa> + } + + return len; +} + 800029c: 0030 movs r0, r6 + 800029e: bd70 pop {r4, r5, r6, pc} + +080002a0 <_write>: + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + 80002a0: b570 push {r4, r5, r6, lr} + 80002a2: 0016 movs r6, r2 + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 80002a4: 2400 movs r4, #0 + 80002a6: e005 b.n 80002b4 <_write+0x14> + { + __io_putchar(*ptr++); + 80002a8: 1c4d adds r5, r1, #1 + 80002aa: 7808 ldrb r0, [r1, #0] + 80002ac: e000 b.n 80002b0 <_write+0x10> + 80002ae: bf00 nop + for (DataIdx = 0; DataIdx < len; DataIdx++) + 80002b0: 3401 adds r4, #1 + __io_putchar(*ptr++); + 80002b2: 0029 movs r1, r5 + for (DataIdx = 0; DataIdx < len; DataIdx++) + 80002b4: 42b4 cmp r4, r6 + 80002b6: dbf7 blt.n 80002a8 <_write+0x8> + } + return len; +} + 80002b8: 0030 movs r0, r6 + 80002ba: bd70 pop {r4, r5, r6, pc} + +080002bc <_close>: + +int _close(int file) +{ + (void)file; + return -1; + 80002bc: 2001 movs r0, #1 +} + 80002be: 4240 negs r0, r0 + 80002c0: 4770 bx lr + +080002c2 <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + 80002c2: 2380 movs r3, #128 @ 0x80 + 80002c4: 019b lsls r3, r3, #6 + 80002c6: 604b str r3, [r1, #4] + return 0; +} + 80002c8: 2000 movs r0, #0 + 80002ca: 4770 bx lr + +080002cc <_isatty>: + +int _isatty(int file) +{ + (void)file; + return 1; +} + 80002cc: 2001 movs r0, #1 + 80002ce: 4770 bx lr + +080002d0 <_lseek>: +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + 80002d0: 2000 movs r0, #0 + 80002d2: 4770 bx lr + +080002d4 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 80002d4: b510 push {r4, lr} + 80002d6: 0003 movs r3, r0 + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 80002d8: 4a0c ldr r2, [pc, #48] @ (800030c <_sbrk+0x38>) + 80002da: 490d ldr r1, [pc, #52] @ (8000310 <_sbrk+0x3c>) + 80002dc: 1a52 subs r2, r2, r1 + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 80002de: 490d ldr r1, [pc, #52] @ (8000314 <_sbrk+0x40>) + 80002e0: 6809 ldr r1, [r1, #0] + 80002e2: 2900 cmp r1, #0 + 80002e4: d007 beq.n 80002f6 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 80002e6: 490b ldr r1, [pc, #44] @ (8000314 <_sbrk+0x40>) + 80002e8: 6808 ldr r0, [r1, #0] + 80002ea: 18c3 adds r3, r0, r3 + 80002ec: 4293 cmp r3, r2 + 80002ee: d806 bhi.n 80002fe <_sbrk+0x2a> + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + 80002f0: 4a08 ldr r2, [pc, #32] @ (8000314 <_sbrk+0x40>) + 80002f2: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; +} + 80002f4: bd10 pop {r4, pc} + __sbrk_heap_end = &_end; + 80002f6: 4907 ldr r1, [pc, #28] @ (8000314 <_sbrk+0x40>) + 80002f8: 4807 ldr r0, [pc, #28] @ (8000318 <_sbrk+0x44>) + 80002fa: 6008 str r0, [r1, #0] + 80002fc: e7f3 b.n 80002e6 <_sbrk+0x12> + errno = ENOMEM; + 80002fe: f001 fcdd bl 8001cbc <__errno> + 8000302: 230c movs r3, #12 + 8000304: 6003 str r3, [r0, #0] + return (void *)-1; + 8000306: 2001 movs r0, #1 + 8000308: 4240 negs r0, r0 + 800030a: e7f3 b.n 80002f4 <_sbrk+0x20> + 800030c: 20003000 .word 0x20003000 + 8000310: 00000400 .word 0x00000400 + 8000314: 200000e0 .word 0x200000e0 + 8000318: 200002a0 .word 0x200002a0 + +0800031c : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 800031c: 480d ldr r0, [pc, #52] @ (8000354 ) + mov sp, r0 /* set stack pointer */ + 800031e: 4685 mov sp, r0 +/* Call the clock system initialization function.*/ + bl SystemInit + 8000320: f000 f826 bl 8000370 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8000324: 2100 movs r1, #0 + b LoopCopyDataInit + 8000326: e003 b.n 8000330 + +08000328 : + +CopyDataInit: + ldr r3, =_sidata + 8000328: 4b0b ldr r3, [pc, #44] @ (8000358 ) + ldr r3, [r3, r1] + 800032a: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 800032c: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 800032e: 3104 adds r1, #4 + +08000330 : + +LoopCopyDataInit: + ldr r0, =_sdata + 8000330: 480a ldr r0, [pc, #40] @ (800035c ) + ldr r3, =_edata + 8000332: 4b0b ldr r3, [pc, #44] @ (8000360 ) + adds r2, r0, r1 + 8000334: 1842 adds r2, r0, r1 + cmp r2, r3 + 8000336: 429a cmp r2, r3 + bcc CopyDataInit + 8000338: d3f6 bcc.n 8000328 + ldr r2, =_sbss + 800033a: 4a0a ldr r2, [pc, #40] @ (8000364 ) + b LoopFillZerobss + 800033c: e002 b.n 8000344 + +0800033e : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 800033e: 2300 movs r3, #0 + str r3, [r2] + 8000340: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000342: 3204 adds r2, #4 + +08000344 : + + +LoopFillZerobss: + ldr r3, = _ebss + 8000344: 4b08 ldr r3, [pc, #32] @ (8000368 ) + cmp r2, r3 + 8000346: 429a cmp r2, r3 + bcc FillZerobss + 8000348: d3f9 bcc.n 800033e + + +/* Call static constructors */ + bl __libc_init_array + 800034a: f001 fcbd bl 8001cc8 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800034e: f000 fed3 bl 80010f8
+ +08000352 : + +LoopForever: + b LoopForever + 8000352: e7fe b.n 8000352 + ldr r0, =_estack + 8000354: 20003000 .word 0x20003000 + ldr r3, =_sidata + 8000358: 080029b4 .word 0x080029b4 + ldr r0, =_sdata + 800035c: 20000000 .word 0x20000000 + ldr r3, =_edata + 8000360: 20000068 .word 0x20000068 + ldr r2, =_sbss + 8000364: 20000068 .word 0x20000068 + ldr r3, = _ebss + 8000368: 2000029c .word 0x2000029c + +0800036c : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 800036c: e7fe b.n 800036c + ... + +08000370 : + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8000370: 4b02 ldr r3, [pc, #8] @ (800037c ) + 8000372: 2280 movs r2, #128 @ 0x80 + 8000374: 0512 lsls r2, r2, #20 + 8000376: 609a str r2, [r3, #8] +#endif +} + 8000378: 4770 bx lr + 800037a: 46c0 nop @ (mov r8, r8) + 800037c: e000ed00 .word 0xe000ed00 + +08000380 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000380: b510 push {r4, lr} + 8000382: 0004 movs r4, r0 + HAL_StatusTypeDef status = HAL_OK; + + if ((uint32_t)uwTickFreq != 0UL) + 8000384: 4b11 ldr r3, [pc, #68] @ (80003cc ) + 8000386: 7819 ldrb r1, [r3, #0] + 8000388: 2900 cmp r1, #0 + 800038a: d101 bne.n 8000390 + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + 800038c: 2001 movs r0, #1 + } + + /* Return function status */ + return status; +} + 800038e: bd10 pop {r4, pc} + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U) + 8000390: 20fa movs r0, #250 @ 0xfa + 8000392: 0080 lsls r0, r0, #2 + 8000394: f7ff fec2 bl 800011c <__udivsi3> + 8000398: 0001 movs r1, r0 + 800039a: 4b0d ldr r3, [pc, #52] @ (80003d0 ) + 800039c: 6818 ldr r0, [r3, #0] + 800039e: f7ff febd bl 800011c <__udivsi3> + 80003a2: f000 f899 bl 80004d8 + 80003a6: 2800 cmp r0, #0 + 80003a8: d10d bne.n 80003c6 + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 80003aa: 2c03 cmp r4, #3 + 80003ac: d901 bls.n 80003b2 + status = HAL_ERROR; + 80003ae: 2001 movs r0, #1 + 80003b0: e7ed b.n 800038e + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 80003b2: 3001 adds r0, #1 + 80003b4: 2200 movs r2, #0 + 80003b6: 0021 movs r1, r4 + 80003b8: 4240 negs r0, r0 + 80003ba: f000 f889 bl 80004d0 + uwTickPrio = TickPriority; + 80003be: 4b05 ldr r3, [pc, #20] @ (80003d4 ) + 80003c0: 601c str r4, [r3, #0] + HAL_StatusTypeDef status = HAL_OK; + 80003c2: 2000 movs r0, #0 + 80003c4: e7e3 b.n 800038e + status = HAL_ERROR; + 80003c6: 2001 movs r0, #1 + 80003c8: e7e1 b.n 800038e + 80003ca: 46c0 nop @ (mov r8, r8) + 80003cc: 20000004 .word 0x20000004 + 80003d0: 20000000 .word 0x20000000 + 80003d4: 20000008 .word 0x20000008 + +080003d8 : +{ + 80003d8: b510 push {r4, lr} + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 80003da: 2003 movs r0, #3 + 80003dc: f7ff ffd0 bl 8000380 + 80003e0: 1e04 subs r4, r0, #0 + 80003e2: d002 beq.n 80003ea + status = HAL_ERROR; + 80003e4: 2401 movs r4, #1 +} + 80003e6: 0020 movs r0, r4 + 80003e8: bd10 pop {r4, pc} + HAL_MspInit(); + 80003ea: f7ff ff23 bl 8000234 + 80003ee: e7fa b.n 80003e6 + +080003f0 : + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; + 80003f0: 4b03 ldr r3, [pc, #12] @ (8000400 ) + 80003f2: 781b ldrb r3, [r3, #0] + 80003f4: 4a03 ldr r2, [pc, #12] @ (8000404 ) + 80003f6: 6811 ldr r1, [r2, #0] + 80003f8: 185b adds r3, r3, r1 + 80003fa: 6013 str r3, [r2, #0] +} + 80003fc: 4770 bx lr + 80003fe: 46c0 nop @ (mov r8, r8) + 8000400: 20000004 .word 0x20000004 + 8000404: 200000e4 .word 0x200000e4 + +08000408 : + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; + 8000408: 4b01 ldr r3, [pc, #4] @ (8000410 ) + 800040a: 6818 ldr r0, [r3, #0] +} + 800040c: 4770 bx lr + 800040e: 46c0 nop @ (mov r8, r8) + 8000410: 200000e4 .word 0x200000e4 + +08000414 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000414: b570 push {r4, r5, r6, lr} + 8000416: 0004 movs r4, r0 + uint32_t tickstart = HAL_GetTick(); + 8000418: f7ff fff6 bl 8000408 + 800041c: 0005 movs r5, r0 + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 800041e: 1c63 adds r3, r4, #1 + 8000420: d002 beq.n 8000428 + { + wait += (uint32_t)(uwTickFreq); + 8000422: 4b04 ldr r3, [pc, #16] @ (8000434 ) + 8000424: 781b ldrb r3, [r3, #0] + 8000426: 18e4 adds r4, r4, r3 + } + + while ((HAL_GetTick() - tickstart) < wait) + 8000428: f7ff ffee bl 8000408 + 800042c: 1b40 subs r0, r0, r5 + 800042e: 42a0 cmp r0, r4 + 8000430: d3fa bcc.n 8000428 + { + } +} + 8000432: bd70 pop {r4, r5, r6, pc} + 8000434: 20000004 .word 0x20000004 + +08000438 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000438: b570 push {r4, r5, r6, lr} + if ((int32_t)(IRQn) >= 0) + 800043a: 2800 cmp r0, #0 + 800043c: db11 blt.n 8000462 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 800043e: 0883 lsrs r3, r0, #2 + 8000440: 4d13 ldr r5, [pc, #76] @ (8000490 <__NVIC_SetPriority+0x58>) + 8000442: 33c0 adds r3, #192 @ 0xc0 + 8000444: 009b lsls r3, r3, #2 + 8000446: 595c ldr r4, [r3, r5] + 8000448: 2203 movs r2, #3 + 800044a: 4010 ands r0, r2 + 800044c: 00c0 lsls r0, r0, #3 + 800044e: 32fc adds r2, #252 @ 0xfc + 8000450: 0016 movs r6, r2 + 8000452: 4086 lsls r6, r0 + 8000454: 43b4 bics r4, r6 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000456: 0189 lsls r1, r1, #6 + 8000458: 400a ands r2, r1 + 800045a: 4082 lsls r2, r0 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 800045c: 4322 orrs r2, r4 + 800045e: 515a str r2, [r3, r5] + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + 8000460: bd70 pop {r4, r5, r6, pc} + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000462: 230f movs r3, #15 + 8000464: 4003 ands r3, r0 + 8000466: 3b08 subs r3, #8 + 8000468: 089b lsrs r3, r3, #2 + 800046a: 3306 adds r3, #6 + 800046c: 009b lsls r3, r3, #2 + 800046e: 4a09 ldr r2, [pc, #36] @ (8000494 <__NVIC_SetPriority+0x5c>) + 8000470: 4694 mov ip, r2 + 8000472: 4463 add r3, ip + 8000474: 685c ldr r4, [r3, #4] + 8000476: 2203 movs r2, #3 + 8000478: 4010 ands r0, r2 + 800047a: 00c0 lsls r0, r0, #3 + 800047c: 32fc adds r2, #252 @ 0xfc + 800047e: 0015 movs r5, r2 + 8000480: 4085 lsls r5, r0 + 8000482: 43ac bics r4, r5 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000484: 0189 lsls r1, r1, #6 + 8000486: 400a ands r2, r1 + 8000488: 4082 lsls r2, r0 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 800048a: 4322 orrs r2, r4 + 800048c: 605a str r2, [r3, #4] +} + 800048e: e7e7 b.n 8000460 <__NVIC_SetPriority+0x28> + 8000490: e000e100 .word 0xe000e100 + 8000494: e000ed00 .word 0xe000ed00 + +08000498 : + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000498: 3801 subs r0, #1 + 800049a: 2380 movs r3, #128 @ 0x80 + 800049c: 045b lsls r3, r3, #17 + 800049e: 4298 cmp r0, r3 + 80004a0: d20f bcs.n 80004c2 + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 80004a2: 4a09 ldr r2, [pc, #36] @ (80004c8 ) + 80004a4: 6050 str r0, [r2, #4] + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80004a6: 4809 ldr r0, [pc, #36] @ (80004cc ) + 80004a8: 6a03 ldr r3, [r0, #32] + 80004aa: 021b lsls r3, r3, #8 + 80004ac: 0a1b lsrs r3, r3, #8 + 80004ae: 21c0 movs r1, #192 @ 0xc0 + 80004b0: 0609 lsls r1, r1, #24 + 80004b2: 430b orrs r3, r1 + 80004b4: 6203 str r3, [r0, #32] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 80004b6: 2300 movs r3, #0 + 80004b8: 6093 str r3, [r2, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 80004ba: 3307 adds r3, #7 + 80004bc: 6013 str r3, [r2, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 80004be: 2000 movs r0, #0 +} + 80004c0: 4770 bx lr + return (1UL); /* Reload value impossible */ + 80004c2: 2001 movs r0, #1 + 80004c4: e7fc b.n 80004c0 + 80004c6: 46c0 nop @ (mov r8, r8) + 80004c8: e000e010 .word 0xe000e010 + 80004cc: e000ed00 .word 0xe000ed00 + +080004d0 : + * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80004d0: b510 push {r4, lr} + /* Prevent unused argument(s) compilation warning */ + UNUSED(SubPriority); + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn, PreemptPriority); + 80004d2: f7ff ffb1 bl 8000438 <__NVIC_SetPriority> +} + 80004d6: bd10 pop {r4, pc} + +080004d8 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80004d8: b510 push {r4, lr} + return SysTick_Config(TicksNumb); + 80004da: f7ff ffdd bl 8000498 +} + 80004de: bd10 pop {r4, pc} + +080004e0 : + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + 80004e0: b570 push {r4, r5, r6, lr} + uint32_t flag_it = DMA1->ISR; + 80004e2: 4b31 ldr r3, [pc, #196] @ (80005a8 ) + 80004e4: 6819 ldr r1, [r3, #0] + uint32_t source_it = hdma->Instance->CCR; + 80004e6: 6804 ldr r4, [r0, #0] + 80004e8: 6825 ldr r5, [r4, #0] + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + 80004ea: 6c02 ldr r2, [r0, #64] @ 0x40 + 80004ec: 231c movs r3, #28 + 80004ee: 4013 ands r3, r2 + 80004f0: 2204 movs r2, #4 + 80004f2: 409a lsls r2, r3 + 80004f4: 4211 tst r1, r2 + 80004f6: d016 beq.n 8000526 + 80004f8: 076a lsls r2, r5, #29 + 80004fa: d514 bpl.n 8000526 + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 80004fc: 6823 ldr r3, [r4, #0] + 80004fe: 069b lsls r3, r3, #26 + 8000500: d403 bmi.n 800050a + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8000502: 6823 ldr r3, [r4, #0] + 8000504: 2204 movs r2, #4 + 8000506: 4393 bics r3, r2 + 8000508: 6023 str r3, [r4, #0] + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))); + 800050a: 4c27 ldr r4, [pc, #156] @ (80005a8 ) + 800050c: 6863 ldr r3, [r4, #4] + 800050e: 6c02 ldr r2, [r0, #64] @ 0x40 + 8000510: 211c movs r1, #28 + 8000512: 4011 ands r1, r2 + 8000514: 2204 movs r2, #4 + 8000516: 408a lsls r2, r1 + 8000518: 4313 orrs r3, r2 + 800051a: 6063 str r3, [r4, #4] + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + 800051c: 6b03 ldr r3, [r0, #48] @ 0x30 + 800051e: 2b00 cmp r3, #0 + 8000520: d000 beq.n 8000524 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 8000522: 4798 blx r3 + else + { + /* Nothing To Do */ + } + return; +} + 8000524: bd70 pop {r4, r5, r6, pc} + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) + 8000526: 2202 movs r2, #2 + 8000528: 409a lsls r2, r3 + 800052a: 4211 tst r1, r2 + 800052c: d01c beq.n 8000568 + 800052e: 07aa lsls r2, r5, #30 + 8000530: d51a bpl.n 8000568 + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 8000532: 6823 ldr r3, [r4, #0] + 8000534: 069b lsls r3, r3, #26 + 8000536: d406 bmi.n 8000546 + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + 8000538: 6823 ldr r3, [r4, #0] + 800053a: 220a movs r2, #10 + 800053c: 4393 bics r3, r2 + 800053e: 6023 str r3, [r4, #0] + hdma->State = HAL_DMA_STATE_READY; + 8000540: 2325 movs r3, #37 @ 0x25 + 8000542: 3a09 subs r2, #9 + 8000544: 54c2 strb r2, [r0, r3] + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))); + 8000546: 4c18 ldr r4, [pc, #96] @ (80005a8 ) + 8000548: 6863 ldr r3, [r4, #4] + 800054a: 6c02 ldr r2, [r0, #64] @ 0x40 + 800054c: 211c movs r1, #28 + 800054e: 4011 ands r1, r2 + 8000550: 2202 movs r2, #2 + 8000552: 408a lsls r2, r1 + 8000554: 4313 orrs r3, r2 + 8000556: 6063 str r3, [r4, #4] + __HAL_UNLOCK(hdma); + 8000558: 2324 movs r3, #36 @ 0x24 + 800055a: 2200 movs r2, #0 + 800055c: 54c2 strb r2, [r0, r3] + if (hdma->XferCpltCallback != NULL) + 800055e: 6ac3 ldr r3, [r0, #44] @ 0x2c + 8000560: 2b00 cmp r3, #0 + 8000562: d0df beq.n 8000524 + hdma->XferCpltCallback(hdma); + 8000564: 4798 blx r3 + 8000566: e7dd b.n 8000524 + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + 8000568: 2208 movs r2, #8 + 800056a: 409a lsls r2, r3 + 800056c: 4211 tst r1, r2 + 800056e: d0d9 beq.n 8000524 + 8000570: 072d lsls r5, r5, #28 + 8000572: d5d7 bpl.n 8000524 + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8000574: 6823 ldr r3, [r4, #0] + 8000576: 220e movs r2, #14 + 8000578: 4393 bics r3, r2 + 800057a: 6023 str r3, [r4, #0] + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); + 800057c: 4c0a ldr r4, [pc, #40] @ (80005a8 ) + 800057e: 6862 ldr r2, [r4, #4] + 8000580: 6c03 ldr r3, [r0, #64] @ 0x40 + 8000582: 211c movs r1, #28 + 8000584: 4019 ands r1, r3 + 8000586: 2301 movs r3, #1 + 8000588: 001d movs r5, r3 + 800058a: 408d lsls r5, r1 + 800058c: 432a orrs r2, r5 + 800058e: 6062 str r2, [r4, #4] + hdma->ErrorCode = HAL_DMA_ERROR_TE; + 8000590: 63c3 str r3, [r0, #60] @ 0x3c + hdma->State = HAL_DMA_STATE_READY; + 8000592: 2225 movs r2, #37 @ 0x25 + 8000594: 5483 strb r3, [r0, r2] + __HAL_UNLOCK(hdma); + 8000596: 3323 adds r3, #35 @ 0x23 + 8000598: 2200 movs r2, #0 + 800059a: 54c2 strb r2, [r0, r3] + if (hdma->XferErrorCallback != NULL) + 800059c: 6b43 ldr r3, [r0, #52] @ 0x34 + 800059e: 2b00 cmp r3, #0 + 80005a0: d0c0 beq.n 8000524 + hdma->XferErrorCallback(hdma); + 80005a2: 4798 blx r3 + return; + 80005a4: e7be b.n 8000524 + 80005a6: 46c0 nop @ (mov r8, r8) + 80005a8: 40020000 .word 0x40020000 + +080005ac : + * @param pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) +{ + 80005ac: b5f0 push {r4, r5, r6, r7, lr} + 80005ae: 46d6 mov lr, sl + 80005b0: 464f mov r7, r9 + 80005b2: 4646 mov r6, r8 + 80005b4: b5c0 push {r6, r7, lr} + uint32_t tmp; + uint32_t iocurrent; + uint32_t position = 0U; + 80005b6: 2300 movs r3, #0 + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); + + /* Configure the port pins */ + while (((pGPIO_Init->Pin) >> position) != 0U) + 80005b8: e03b b.n 8000632 + /* Configure the External Interrupt or event for the current IO */ + if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + 80005ba: 2505 movs r5, #5 + 80005bc: e000 b.n 80005c0 + 80005be: 2500 movs r5, #0 + 80005c0: 40a5 lsls r5, r4 + 80005c2: 002c movs r4, r5 + 80005c4: 433c orrs r4, r7 + EXTI->EXTICR[position >> 2U] = tmp; + 80005c6: 4d63 ldr r5, [pc, #396] @ (8000754 ) + 80005c8: 3218 adds r2, #24 + 80005ca: 0092 lsls r2, r2, #2 + 80005cc: 5154 str r4, [r2, r5] + + /* Clear EXTI line configuration */ + tmp = EXTI->IMR1; + 80005ce: 2280 movs r2, #128 @ 0x80 + 80005d0: 58af ldr r7, [r5, r2] + tmp &= ~((uint32_t)iocurrent); + 80005d2: 464a mov r2, r9 + 80005d4: 43d2 mvns r2, r2 + 80005d6: 003d movs r5, r7 + 80005d8: 464c mov r4, r9 + 80005da: 43a5 bics r5, r4 + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80005dc: 684c ldr r4, [r1, #4] + 80005de: 03e4 lsls r4, r4, #15 + 80005e0: d502 bpl.n 80005e8 + { + tmp |= iocurrent; + 80005e2: 003d movs r5, r7 + 80005e4: 464c mov r4, r9 + 80005e6: 4325 orrs r5, r4 + } + EXTI->IMR1 = tmp; + 80005e8: 4c5a ldr r4, [pc, #360] @ (8000754 ) + 80005ea: 2780 movs r7, #128 @ 0x80 + 80005ec: 51e5 str r5, [r4, r7] + + tmp = EXTI->EMR1; + 80005ee: 2584 movs r5, #132 @ 0x84 + 80005f0: 5967 ldr r7, [r4, r5] + tmp &= ~((uint32_t)iocurrent); + 80005f2: 003d movs r5, r7 + 80005f4: 4015 ands r5, r2 + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80005f6: 684c ldr r4, [r1, #4] + 80005f8: 03a4 lsls r4, r4, #14 + 80005fa: d502 bpl.n 8000602 + { + tmp |= iocurrent; + 80005fc: 003d movs r5, r7 + 80005fe: 464c mov r4, r9 + 8000600: 4325 orrs r5, r4 + } + EXTI->EMR1 = tmp; + 8000602: 4c54 ldr r4, [pc, #336] @ (8000754 ) + 8000604: 2784 movs r7, #132 @ 0x84 + 8000606: 51e5 str r5, [r4, r7] + + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; + 8000608: 6827 ldr r7, [r4, #0] + tmp &= ~((uint32_t)iocurrent); + 800060a: 003d movs r5, r7 + 800060c: 4015 ands r5, r2 + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 800060e: 684c ldr r4, [r1, #4] + 8000610: 02e4 lsls r4, r4, #11 + 8000612: d502 bpl.n 800061a + { + tmp |= iocurrent; + 8000614: 003d movs r5, r7 + 8000616: 464c mov r4, r9 + 8000618: 4325 orrs r5, r4 + } + EXTI->RTSR1 = tmp; + 800061a: 4c4e ldr r4, [pc, #312] @ (8000754 ) + 800061c: 6025 str r5, [r4, #0] + + tmp = EXTI->FTSR1; + 800061e: 6865 ldr r5, [r4, #4] + tmp &= ~((uint32_t)iocurrent); + 8000620: 402a ands r2, r5 + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8000622: 684c ldr r4, [r1, #4] + 8000624: 02a4 lsls r4, r4, #10 + 8000626: d501 bpl.n 800062c + { + tmp |= iocurrent; + 8000628: 464a mov r2, r9 + 800062a: 432a orrs r2, r5 + } + EXTI->FTSR1 = tmp; + 800062c: 4c49 ldr r4, [pc, #292] @ (8000754 ) + 800062e: 6062 str r2, [r4, #4] + } + } + + position++; + 8000630: 3301 adds r3, #1 + while (((pGPIO_Init->Pin) >> position) != 0U) + 8000632: 680c ldr r4, [r1, #0] + 8000634: 0022 movs r2, r4 + 8000636: 40da lsrs r2, r3 + 8000638: d100 bne.n 800063c + 800063a: e086 b.n 800074a + iocurrent = (pGPIO_Init->Pin) & (1UL << position); + 800063c: 2201 movs r2, #1 + 800063e: 409a lsls r2, r3 + 8000640: 0026 movs r6, r4 + 8000642: 4016 ands r6, r2 + 8000644: 46b1 mov r9, r6 + if (iocurrent != 0U) + 8000646: 4214 tst r4, r2 + 8000648: d0f2 beq.n 8000630 + if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + 800064a: 684c ldr r4, [r1, #4] + 800064c: 2c02 cmp r4, #2 + 800064e: d001 beq.n 8000654 + 8000650: 2c12 cmp r4, #18 + 8000652: d118 bne.n 8000686 + tmp = GPIOx->AFR[position >> 3U]; + 8000654: 08dd lsrs r5, r3, #3 + 8000656: 3508 adds r5, #8 + 8000658: 00ad lsls r5, r5, #2 + 800065a: 582c ldr r4, [r5, r0] + 800065c: 46a4 mov ip, r4 + tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; + 800065e: 2707 movs r7, #7 + 8000660: 401f ands r7, r3 + 8000662: 00bf lsls r7, r7, #2 + 8000664: 240f movs r4, #15 + 8000666: 46a2 mov sl, r4 + 8000668: 0026 movs r6, r4 + 800066a: 40be lsls r6, r7 + 800066c: 46b0 mov r8, r6 + 800066e: 4666 mov r6, ip + 8000670: 4644 mov r4, r8 + 8000672: 43a6 bics r6, r4 + 8000674: 46b4 mov ip, r6 + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + 8000676: 690c ldr r4, [r1, #16] + 8000678: 4656 mov r6, sl + 800067a: 4026 ands r6, r4 + 800067c: 0034 movs r4, r6 + 800067e: 40bc lsls r4, r7 + 8000680: 4666 mov r6, ip + 8000682: 4334 orrs r4, r6 + GPIOx->AFR[position >> 3U] = tmp; + 8000684: 502c str r4, [r5, r0] + tmp = GPIOx->MODER; + 8000686: 6804 ldr r4, [r0, #0] + 8000688: 46a4 mov ip, r4 + tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + 800068a: 005d lsls r5, r3, #1 + 800068c: 2403 movs r4, #3 + 800068e: 46a2 mov sl, r4 + 8000690: 0027 movs r7, r4 + 8000692: 40af lsls r7, r5 + 8000694: 46b8 mov r8, r7 + 8000696: 43ff mvns r7, r7 + 8000698: 4666 mov r6, ip + 800069a: 4644 mov r4, r8 + 800069c: 43a6 bics r6, r4 + 800069e: 46b4 mov ip, r6 + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); + 80006a0: 684c ldr r4, [r1, #4] + 80006a2: 4656 mov r6, sl + 80006a4: 4026 ands r6, r4 + 80006a6: 0034 movs r4, r6 + 80006a8: 40ac lsls r4, r5 + 80006aa: 4666 mov r6, ip + 80006ac: 4334 orrs r4, r6 + GPIOx->MODER = tmp; + 80006ae: 6004 str r4, [r0, #0] + if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || + 80006b0: 684c ldr r4, [r1, #4] + 80006b2: 1e66 subs r6, r4, #1 + 80006b4: 2e01 cmp r6, #1 + 80006b6: d903 bls.n 80006c0 + 80006b8: 2c11 cmp r4, #17 + 80006ba: d001 beq.n 80006c0 + (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80006bc: 2c12 cmp r4, #18 + 80006be: d112 bne.n 80006e6 + tmp = GPIOx->OSPEEDR; + 80006c0: 6884 ldr r4, [r0, #8] + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + 80006c2: 403c ands r4, r7 + 80006c4: 46a4 mov ip, r4 + tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + 80006c6: 68cc ldr r4, [r1, #12] + 80006c8: 40ac lsls r4, r5 + 80006ca: 4666 mov r6, ip + 80006cc: 4334 orrs r4, r6 + GPIOx->OSPEEDR = tmp; + 80006ce: 6084 str r4, [r0, #8] + tmp = GPIOx->OTYPER; + 80006d0: 6844 ldr r4, [r0, #4] + tmp &= ~(GPIO_OTYPER_OT0 << position) ; + 80006d2: 4394 bics r4, r2 + tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 80006d4: 684a ldr r2, [r1, #4] + 80006d6: 0912 lsrs r2, r2, #4 + 80006d8: 4694 mov ip, r2 + 80006da: 2201 movs r2, #1 + 80006dc: 4666 mov r6, ip + 80006de: 4032 ands r2, r6 + 80006e0: 409a lsls r2, r3 + 80006e2: 4322 orrs r2, r4 + GPIOx->OTYPER = tmp; + 80006e4: 6042 str r2, [r0, #4] + if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) + 80006e6: 684a ldr r2, [r1, #4] + 80006e8: 2a03 cmp r2, #3 + 80006ea: d005 beq.n 80006f8 + tmp = GPIOx->PUPDR; + 80006ec: 68c4 ldr r4, [r0, #12] + tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + 80006ee: 403c ands r4, r7 + tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); + 80006f0: 688a ldr r2, [r1, #8] + 80006f2: 40aa lsls r2, r5 + 80006f4: 4322 orrs r2, r4 + GPIOx->PUPDR = tmp; + 80006f6: 60c2 str r2, [r0, #12] + if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 80006f8: 684a ldr r2, [r1, #4] + 80006fa: 00d2 lsls r2, r2, #3 + 80006fc: d598 bpl.n 8000630 + tmp = EXTI->EXTICR[position >> 2U]; + 80006fe: 089a lsrs r2, r3, #2 + 8000700: 0014 movs r4, r2 + 8000702: 3418 adds r4, #24 + 8000704: 00a4 lsls r4, r4, #2 + 8000706: 4d13 ldr r5, [pc, #76] @ (8000754 ) + 8000708: 5967 ldr r7, [r4, r5] + tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + 800070a: 2403 movs r4, #3 + 800070c: 401c ands r4, r3 + 800070e: 00e4 lsls r4, r4, #3 + 8000710: 250f movs r5, #15 + 8000712: 40a5 lsls r5, r4 + 8000714: 43af bics r7, r5 + tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + 8000716: 25a0 movs r5, #160 @ 0xa0 + 8000718: 05ed lsls r5, r5, #23 + 800071a: 42a8 cmp r0, r5 + 800071c: d100 bne.n 8000720 + 800071e: e74e b.n 80005be + 8000720: 4d0d ldr r5, [pc, #52] @ (8000758 ) + 8000722: 42a8 cmp r0, r5 + 8000724: d00b beq.n 800073e + 8000726: 4d0d ldr r5, [pc, #52] @ (800075c ) + 8000728: 42a8 cmp r0, r5 + 800072a: d00a beq.n 8000742 + 800072c: 4d0c ldr r5, [pc, #48] @ (8000760 ) + 800072e: 42a8 cmp r0, r5 + 8000730: d009 beq.n 8000746 + 8000732: 4d0c ldr r5, [pc, #48] @ (8000764 ) + 8000734: 42a8 cmp r0, r5 + 8000736: d100 bne.n 800073a + 8000738: e73f b.n 80005ba + 800073a: 2506 movs r5, #6 + 800073c: e740 b.n 80005c0 + 800073e: 2501 movs r5, #1 + 8000740: e73e b.n 80005c0 + 8000742: 2502 movs r5, #2 + 8000744: e73c b.n 80005c0 + 8000746: 2503 movs r5, #3 + 8000748: e73a b.n 80005c0 + } +} + 800074a: bce0 pop {r5, r6, r7} + 800074c: 46ba mov sl, r7 + 800074e: 46b1 mov r9, r6 + 8000750: 46a8 mov r8, r5 + 8000752: bdf0 pop {r4, r5, r6, r7, pc} + 8000754: 40021800 .word 0x40021800 + 8000758: 50000400 .word 0x50000400 + 800075c: 50000800 .word 0x50000800 + 8000760: 50000c00 .word 0x50000c00 + 8000764: 50001400 .word 0x50001400 + +08000768 : + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0U) + 8000768: 6903 ldr r3, [r0, #16] + 800076a: 420b tst r3, r1 + 800076c: d001 beq.n 8000772 + { + bitstatus = GPIO_PIN_SET; + 800076e: 2001 movs r0, #1 + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + 8000770: 4770 bx lr + bitstatus = GPIO_PIN_RESET; + 8000772: 2000 movs r0, #0 + 8000774: e7fc b.n 8000770 + +08000776 : +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8000776: 2a00 cmp r2, #0 + 8000778: d001 beq.n 800077e + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 800077a: 6181 str r1, [r0, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 800077c: 4770 bx lr + GPIOx->BRR = (uint32_t)GPIO_Pin; + 800077e: 6281 str r1, [r0, #40] @ 0x28 +} + 8000780: e7fc b.n 800077c + ... + +08000784 : + must adjust the number of CPU wait states in their application (SystemClock_Config() API) + before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8000784: b570 push {r4, r5, r6, lr} + 8000786: 1e04 subs r4, r0, #0 + uint32_t tickstart; + uint32_t temp_sysclksrc; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8000788: d100 bne.n 800078c + 800078a: e139 b.n 8000a00 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 800078c: 6803 ldr r3, [r0, #0] + 800078e: 07db lsls r3, r3, #31 + 8000790: d52c bpl.n 80007ec + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8000792: 4ba1 ldr r3, [pc, #644] @ (8000a18 ) + 8000794: 689a ldr r2, [r3, #8] + 8000796: 2338 movs r3, #56 @ 0x38 + 8000798: 4013 ands r3, r2 + + /* When the HSE is used as system clock in these cases it is not allowed to be disabled */ + if (temp_sysclksrc == RCC_CFGR_SWS_HSE) + 800079a: 2b08 cmp r3, #8 + 800079c: d022 beq.n 80007e4 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800079e: 6843 ldr r3, [r0, #4] + 80007a0: 2280 movs r2, #128 @ 0x80 + 80007a2: 0252 lsls r2, r2, #9 + 80007a4: 4293 cmp r3, r2 + 80007a6: d02e beq.n 8000806 + 80007a8: 22a0 movs r2, #160 @ 0xa0 + 80007aa: 02d2 lsls r2, r2, #11 + 80007ac: 4293 cmp r3, r2 + 80007ae: d031 beq.n 8000814 + 80007b0: 4b99 ldr r3, [pc, #612] @ (8000a18 ) + 80007b2: 681a ldr r2, [r3, #0] + 80007b4: 4999 ldr r1, [pc, #612] @ (8000a1c ) + 80007b6: 400a ands r2, r1 + 80007b8: 601a str r2, [r3, #0] + 80007ba: 681a ldr r2, [r3, #0] + 80007bc: 4998 ldr r1, [pc, #608] @ (8000a20 ) + 80007be: 400a ands r2, r1 + 80007c0: 601a str r2, [r3, #0] + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80007c2: 6863 ldr r3, [r4, #4] + 80007c4: 2b00 cmp r3, #0 + 80007c6: d031 beq.n 800082c + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80007c8: f7ff fe1e bl 8000408 + 80007cc: 0005 movs r5, r0 + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 80007ce: 4b92 ldr r3, [pc, #584] @ (8000a18 ) + 80007d0: 681b ldr r3, [r3, #0] + 80007d2: 039b lsls r3, r3, #14 + 80007d4: d40a bmi.n 80007ec + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + 80007d6: f7ff fe17 bl 8000408 + 80007da: 1b40 subs r0, r0, r5 + 80007dc: 2864 cmp r0, #100 @ 0x64 + 80007de: d9f6 bls.n 80007ce + { + return HAL_TIMEOUT; + 80007e0: 2003 movs r0, #3 + 80007e2: e10e b.n 8000a02 + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + 80007e4: 6843 ldr r3, [r0, #4] + 80007e6: 2b00 cmp r3, #0 + 80007e8: d100 bne.n 80007ec + 80007ea: e10b b.n 8000a04 + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80007ec: 6823 ldr r3, [r4, #0] + 80007ee: 079b lsls r3, r3, #30 + 80007f0: d547 bpl.n 8000882 + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + + /* Check if HSI48 is used as system clock */ + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80007f2: 4b89 ldr r3, [pc, #548] @ (8000a18 ) + 80007f4: 689b ldr r3, [r3, #8] + 80007f6: 2238 movs r2, #56 @ 0x38 + + if (temp_sysclksrc == RCC_CFGR_SWS_HSI) + 80007f8: 421a tst r2, r3 + 80007fa: d161 bne.n 80008c0 + { + /* When HSI is used as system clock it can not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 80007fc: 68e3 ldr r3, [r4, #12] + 80007fe: 2b00 cmp r3, #0 + 8000800: d122 bne.n 8000848 + { + return HAL_ERROR; + 8000802: 2001 movs r0, #1 + 8000804: e0fd b.n 8000a02 + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8000806: 4a84 ldr r2, [pc, #528] @ (8000a18 ) + 8000808: 6811 ldr r1, [r2, #0] + 800080a: 2380 movs r3, #128 @ 0x80 + 800080c: 025b lsls r3, r3, #9 + 800080e: 430b orrs r3, r1 + 8000810: 6013 str r3, [r2, #0] + 8000812: e7d6 b.n 80007c2 + 8000814: 4b80 ldr r3, [pc, #512] @ (8000a18 ) + 8000816: 6819 ldr r1, [r3, #0] + 8000818: 2280 movs r2, #128 @ 0x80 + 800081a: 02d2 lsls r2, r2, #11 + 800081c: 430a orrs r2, r1 + 800081e: 601a str r2, [r3, #0] + 8000820: 6819 ldr r1, [r3, #0] + 8000822: 2280 movs r2, #128 @ 0x80 + 8000824: 0252 lsls r2, r2, #9 + 8000826: 430a orrs r2, r1 + 8000828: 601a str r2, [r3, #0] + 800082a: e7ca b.n 80007c2 + tickstart = HAL_GetTick(); + 800082c: f7ff fdec bl 8000408 + 8000830: 0005 movs r5, r0 + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 8000832: 4b79 ldr r3, [pc, #484] @ (8000a18 ) + 8000834: 681b ldr r3, [r3, #0] + 8000836: 039b lsls r3, r3, #14 + 8000838: d5d8 bpl.n 80007ec + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + 800083a: f7ff fde5 bl 8000408 + 800083e: 1b40 subs r0, r0, r5 + 8000840: 2864 cmp r0, #100 @ 0x64 + 8000842: d9f6 bls.n 8000832 + return HAL_TIMEOUT; + 8000844: 2003 movs r0, #3 + 8000846: e0dc b.n 8000a02 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8000848: 4b73 ldr r3, [pc, #460] @ (8000a18 ) + 800084a: 685a ldr r2, [r3, #4] + 800084c: 4975 ldr r1, [pc, #468] @ (8000a24 ) + 800084e: 400a ands r2, r1 + 8000850: 6961 ldr r1, [r4, #20] + 8000852: 0209 lsls r1, r1, #8 + 8000854: 430a orrs r2, r1 + 8000856: 605a str r2, [r3, #4] + + if (temp_sysclksrc == RCC_CFGR_SWS_HSI) + { + /* Adjust the HSI48 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + 8000858: 681a ldr r2, [r3, #0] + 800085a: 4973 ldr r1, [pc, #460] @ (8000a28 ) + 800085c: 400a ands r2, r1 + 800085e: 6921 ldr r1, [r4, #16] + 8000860: 430a orrs r2, r1 + 8000862: 601a str r2, [r3, #0] + + /* Update the SystemCoreClock global variable with HSISYS value */ + SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); + 8000864: 681b ldr r3, [r3, #0] + 8000866: 0adb lsrs r3, r3, #11 + 8000868: 2207 movs r2, #7 + 800086a: 401a ands r2, r3 + 800086c: 4b6f ldr r3, [pc, #444] @ (8000a2c ) + 800086e: 40d3 lsrs r3, r2 + 8000870: 4a6f ldr r2, [pc, #444] @ (8000a30 ) + 8000872: 6013 str r3, [r2, #0] + } + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + 8000874: 4b6f ldr r3, [pc, #444] @ (8000a34 ) + 8000876: 6818 ldr r0, [r3, #0] + 8000878: f7ff fd82 bl 8000380 + 800087c: 2800 cmp r0, #0 + 800087e: d000 beq.n 8000882 + 8000880: e0c2 b.n 8000a08 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8000882: 6823 ldr r3, [r4, #0] + 8000884: 071b lsls r3, r3, #28 + 8000886: d557 bpl.n 8000938 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check if LSI is used as system clock */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) + 8000888: 4b63 ldr r3, [pc, #396] @ (8000a18 ) + 800088a: 689a ldr r2, [r3, #8] + 800088c: 2338 movs r3, #56 @ 0x38 + 800088e: 4013 ands r3, r2 + 8000890: 2b18 cmp r3, #24 + 8000892: d04e beq.n 8000932 + } + } + else + { + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8000894: 69a3 ldr r3, [r4, #24] + 8000896: 2b00 cmp r3, #0 + 8000898: d077 beq.n 800098a + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800089a: 4a5f ldr r2, [pc, #380] @ (8000a18 ) + 800089c: 6e13 ldr r3, [r2, #96] @ 0x60 + 800089e: 2101 movs r1, #1 + 80008a0: 430b orrs r3, r1 + 80008a2: 6613 str r3, [r2, #96] @ 0x60 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80008a4: f7ff fdb0 bl 8000408 + 80008a8: 0005 movs r5, r0 + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) + 80008aa: 4b5b ldr r3, [pc, #364] @ (8000a18 ) + 80008ac: 6e1b ldr r3, [r3, #96] @ 0x60 + 80008ae: 079b lsls r3, r3, #30 + 80008b0: d442 bmi.n 8000938 + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + 80008b2: f7ff fda9 bl 8000408 + 80008b6: 1b40 subs r0, r0, r5 + 80008b8: 2802 cmp r0, #2 + 80008ba: d9f6 bls.n 80008aa + { + return HAL_TIMEOUT; + 80008bc: 2003 movs r0, #3 + 80008be: e0a0 b.n 8000a02 + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80008c0: 68e3 ldr r3, [r4, #12] + 80008c2: 2b00 cmp r3, #0 + 80008c4: d022 beq.n 800090c + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + 80008c6: 4a54 ldr r2, [pc, #336] @ (8000a18 ) + 80008c8: 6813 ldr r3, [r2, #0] + 80008ca: 4957 ldr r1, [pc, #348] @ (8000a28 ) + 80008cc: 400b ands r3, r1 + 80008ce: 6921 ldr r1, [r4, #16] + 80008d0: 430b orrs r3, r1 + 80008d2: 6013 str r3, [r2, #0] + __HAL_RCC_HSI_ENABLE(); + 80008d4: 6811 ldr r1, [r2, #0] + 80008d6: 2380 movs r3, #128 @ 0x80 + 80008d8: 005b lsls r3, r3, #1 + 80008da: 430b orrs r3, r1 + 80008dc: 6013 str r3, [r2, #0] + tickstart = HAL_GetTick(); + 80008de: f7ff fd93 bl 8000408 + 80008e2: 0005 movs r5, r0 + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 80008e4: 4b4c ldr r3, [pc, #304] @ (8000a18 ) + 80008e6: 681b ldr r3, [r3, #0] + 80008e8: 055b lsls r3, r3, #21 + 80008ea: d406 bmi.n 80008fa + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + 80008ec: f7ff fd8c bl 8000408 + 80008f0: 1b40 subs r0, r0, r5 + 80008f2: 2802 cmp r0, #2 + 80008f4: d9f6 bls.n 80008e4 + return HAL_TIMEOUT; + 80008f6: 2003 movs r0, #3 + 80008f8: e083 b.n 8000a02 + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80008fa: 4947 ldr r1, [pc, #284] @ (8000a18 ) + 80008fc: 684b ldr r3, [r1, #4] + 80008fe: 4a49 ldr r2, [pc, #292] @ (8000a24 ) + 8000900: 4013 ands r3, r2 + 8000902: 6962 ldr r2, [r4, #20] + 8000904: 0212 lsls r2, r2, #8 + 8000906: 4313 orrs r3, r2 + 8000908: 604b str r3, [r1, #4] + 800090a: e7ba b.n 8000882 + __HAL_RCC_HSI_DISABLE(); + 800090c: 4a42 ldr r2, [pc, #264] @ (8000a18 ) + 800090e: 6813 ldr r3, [r2, #0] + 8000910: 4949 ldr r1, [pc, #292] @ (8000a38 ) + 8000912: 400b ands r3, r1 + 8000914: 6013 str r3, [r2, #0] + tickstart = HAL_GetTick(); + 8000916: f7ff fd77 bl 8000408 + 800091a: 0005 movs r5, r0 + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + 800091c: 4b3e ldr r3, [pc, #248] @ (8000a18 ) + 800091e: 681b ldr r3, [r3, #0] + 8000920: 055b lsls r3, r3, #21 + 8000922: d5ae bpl.n 8000882 + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + 8000924: f7ff fd70 bl 8000408 + 8000928: 1b40 subs r0, r0, r5 + 800092a: 2802 cmp r0, #2 + 800092c: d9f6 bls.n 800091c + return HAL_TIMEOUT; + 800092e: 2003 movs r0, #3 + 8000930: e067 b.n 8000a02 + if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF) + 8000932: 69a3 ldr r3, [r4, #24] + 8000934: 2b00 cmp r3, #0 + 8000936: d069 beq.n 8000a0c + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8000938: 6823 ldr r3, [r4, #0] + 800093a: 075b lsls r3, r3, #29 + 800093c: d568 bpl.n 8000a10 + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* When the LSE is used as system clock, it is not allowed disable it */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) + 800093e: 4b36 ldr r3, [pc, #216] @ (8000a18 ) + 8000940: 689a ldr r2, [r3, #8] + 8000942: 2338 movs r3, #56 @ 0x38 + 8000944: 4013 ands r3, r2 + 8000946: 2b20 cmp r3, #32 + 8000948: d032 beq.n 80009b0 + } + else + { + /* Update LSE configuration in RTC Domain control register */ + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 800094a: 68a3 ldr r3, [r4, #8] + 800094c: 2b01 cmp r3, #1 + 800094e: d034 beq.n 80009ba + 8000950: 2b05 cmp r3, #5 + 8000952: d038 beq.n 80009c6 + 8000954: 4b30 ldr r3, [pc, #192] @ (8000a18 ) + 8000956: 6dda ldr r2, [r3, #92] @ 0x5c + 8000958: 2101 movs r1, #1 + 800095a: 438a bics r2, r1 + 800095c: 65da str r2, [r3, #92] @ 0x5c + 800095e: 6dda ldr r2, [r3, #92] @ 0x5c + 8000960: 3103 adds r1, #3 + 8000962: 438a bics r2, r1 + 8000964: 65da str r2, [r3, #92] @ 0x5c + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8000966: 68a3 ldr r3, [r4, #8] + 8000968: 2b00 cmp r3, #0 + 800096a: d038 beq.n 80009de + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800096c: f7ff fd4c bl 8000408 + 8000970: 0004 movs r4, r0 + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) + 8000972: 4b29 ldr r3, [pc, #164] @ (8000a18 ) + 8000974: 6ddb ldr r3, [r3, #92] @ 0x5c + 8000976: 079b lsls r3, r3, #30 + 8000978: d42f bmi.n 80009da + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800097a: f7ff fd45 bl 8000408 + 800097e: 1b00 subs r0, r0, r4 + 8000980: 4b2e ldr r3, [pc, #184] @ (8000a3c ) + 8000982: 4298 cmp r0, r3 + 8000984: d9f5 bls.n 8000972 + { + return HAL_TIMEOUT; + 8000986: 2003 movs r0, #3 + 8000988: e03b b.n 8000a02 + __HAL_RCC_LSI_DISABLE(); + 800098a: 4a23 ldr r2, [pc, #140] @ (8000a18 ) + 800098c: 6e13 ldr r3, [r2, #96] @ 0x60 + 800098e: 2101 movs r1, #1 + 8000990: 438b bics r3, r1 + 8000992: 6613 str r3, [r2, #96] @ 0x60 + tickstart = HAL_GetTick(); + 8000994: f7ff fd38 bl 8000408 + 8000998: 0005 movs r5, r0 + while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) + 800099a: 4b1f ldr r3, [pc, #124] @ (8000a18 ) + 800099c: 6e1b ldr r3, [r3, #96] @ 0x60 + 800099e: 079b lsls r3, r3, #30 + 80009a0: d5ca bpl.n 8000938 + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + 80009a2: f7ff fd31 bl 8000408 + 80009a6: 1b40 subs r0, r0, r5 + 80009a8: 2802 cmp r0, #2 + 80009aa: d9f6 bls.n 800099a + return HAL_TIMEOUT; + 80009ac: 2003 movs r0, #3 + 80009ae: e028 b.n 8000a02 + if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF) + 80009b0: 68a3 ldr r3, [r4, #8] + 80009b2: 2b00 cmp r3, #0 + 80009b4: d02e beq.n 8000a14 + } + } + } + } +#endif /* RCC_CR_HSIUSB48ON */ + return HAL_OK; + 80009b6: 2000 movs r0, #0 + 80009b8: e023 b.n 8000a02 + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80009ba: 4a17 ldr r2, [pc, #92] @ (8000a18 ) + 80009bc: 6dd3 ldr r3, [r2, #92] @ 0x5c + 80009be: 2101 movs r1, #1 + 80009c0: 430b orrs r3, r1 + 80009c2: 65d3 str r3, [r2, #92] @ 0x5c + 80009c4: e7cf b.n 8000966 + 80009c6: 4b14 ldr r3, [pc, #80] @ (8000a18 ) + 80009c8: 6dda ldr r2, [r3, #92] @ 0x5c + 80009ca: 2104 movs r1, #4 + 80009cc: 430a orrs r2, r1 + 80009ce: 65da str r2, [r3, #92] @ 0x5c + 80009d0: 6dda ldr r2, [r3, #92] @ 0x5c + 80009d2: 3903 subs r1, #3 + 80009d4: 430a orrs r2, r1 + 80009d6: 65da str r2, [r3, #92] @ 0x5c + 80009d8: e7c5 b.n 8000966 + return HAL_OK; + 80009da: 2000 movs r0, #0 + 80009dc: e011 b.n 8000a02 + tickstart = HAL_GetTick(); + 80009de: f7ff fd13 bl 8000408 + 80009e2: 0004 movs r4, r0 + while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) + 80009e4: 4b0c ldr r3, [pc, #48] @ (8000a18 ) + 80009e6: 6ddb ldr r3, [r3, #92] @ 0x5c + 80009e8: 079b lsls r3, r3, #30 + 80009ea: d507 bpl.n 80009fc + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80009ec: f7ff fd0c bl 8000408 + 80009f0: 1b00 subs r0, r0, r4 + 80009f2: 4b12 ldr r3, [pc, #72] @ (8000a3c ) + 80009f4: 4298 cmp r0, r3 + 80009f6: d9f5 bls.n 80009e4 + return HAL_TIMEOUT; + 80009f8: 2003 movs r0, #3 + 80009fa: e002 b.n 8000a02 + return HAL_OK; + 80009fc: 2000 movs r0, #0 + 80009fe: e000 b.n 8000a02 + return HAL_ERROR; + 8000a00: 2001 movs r0, #1 +} + 8000a02: bd70 pop {r4, r5, r6, pc} + return HAL_ERROR; + 8000a04: 2001 movs r0, #1 + 8000a06: e7fc b.n 8000a02 + return HAL_ERROR; + 8000a08: 2001 movs r0, #1 + 8000a0a: e7fa b.n 8000a02 + return HAL_ERROR; + 8000a0c: 2001 movs r0, #1 + 8000a0e: e7f8 b.n 8000a02 + return HAL_OK; + 8000a10: 2000 movs r0, #0 + 8000a12: e7f6 b.n 8000a02 + return HAL_ERROR; + 8000a14: 2001 movs r0, #1 + 8000a16: e7f4 b.n 8000a02 + 8000a18: 40021000 .word 0x40021000 + 8000a1c: fffeffff .word 0xfffeffff + 8000a20: fffbffff .word 0xfffbffff + 8000a24: ffff80ff .word 0xffff80ff + 8000a28: ffffc7ff .word 0xffffc7ff + 8000a2c: 02dc6c00 .word 0x02dc6c00 + 8000a30: 20000000 .word 0x20000000 + 8000a34: 20000008 .word 0x20000008 + 8000a38: fffffeff .word 0xfffffeff + 8000a3c: 00001388 .word 0x00001388 + +08000a40 : + uint32_t sysclockfreq; +#if defined(RCC_CR_SYSDIV) + uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U); +#endif /* RCC_CR_SYSDIV */ + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + 8000a40: 4b14 ldr r3, [pc, #80] @ (8000a94 ) + 8000a42: 689b ldr r3, [r3, #8] + 8000a44: 2238 movs r2, #56 @ 0x38 + 8000a46: 421a tst r2, r3 + 8000a48: d107 bne.n 8000a5a + { + /* HSISYS can be derived for HSI48 */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + 8000a4a: 4b12 ldr r3, [pc, #72] @ (8000a94 ) + 8000a4c: 681a ldr r2, [r3, #0] + 8000a4e: 0ad2 lsrs r2, r2, #11 + 8000a50: 2307 movs r3, #7 + 8000a52: 4013 ands r3, r2 + + /* HSI used as system clock source */ + sysclockfreq = (HSI_VALUE / hsidiv); + 8000a54: 4810 ldr r0, [pc, #64] @ (8000a98 ) + 8000a56: 40d8 lsrs r0, r3 + } +#if defined(RCC_CR_SYSDIV) + sysclockfreq = sysclockfreq / sysclockdiv; +#endif /* RCC_CR_SYSDIV */ + return sysclockfreq; +} + 8000a58: 4770 bx lr + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + 8000a5a: 4b0e ldr r3, [pc, #56] @ (8000a94 ) + 8000a5c: 689a ldr r2, [r3, #8] + 8000a5e: 2338 movs r3, #56 @ 0x38 + 8000a60: 4013 ands r3, r2 + 8000a62: 2b08 cmp r3, #8 + 8000a64: d010 beq.n 8000a88 + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) + 8000a66: 4b0b ldr r3, [pc, #44] @ (8000a94 ) + 8000a68: 689a ldr r2, [r3, #8] + 8000a6a: 2338 movs r3, #56 @ 0x38 + 8000a6c: 4013 ands r3, r2 + 8000a6e: 2b20 cmp r3, #32 + 8000a70: d00c beq.n 8000a8c + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) + 8000a72: 4b08 ldr r3, [pc, #32] @ (8000a94 ) + 8000a74: 689a ldr r2, [r3, #8] + 8000a76: 2338 movs r3, #56 @ 0x38 + 8000a78: 4013 ands r3, r2 + 8000a7a: 2b18 cmp r3, #24 + 8000a7c: d001 beq.n 8000a82 + sysclockfreq = 0U; + 8000a7e: 2000 movs r0, #0 + return sysclockfreq; + 8000a80: e7ea b.n 8000a58 + sysclockfreq = LSI_VALUE; + 8000a82: 20fa movs r0, #250 @ 0xfa + 8000a84: 01c0 lsls r0, r0, #7 + 8000a86: e7e7 b.n 8000a58 + sysclockfreq = HSE_VALUE; + 8000a88: 4804 ldr r0, [pc, #16] @ (8000a9c ) + 8000a8a: e7e5 b.n 8000a58 + sysclockfreq = LSE_VALUE; + 8000a8c: 2080 movs r0, #128 @ 0x80 + 8000a8e: 0200 lsls r0, r0, #8 + 8000a90: e7e2 b.n 8000a58 + 8000a92: 46c0 nop @ (mov r8, r8) + 8000a94: 40021000 .word 0x40021000 + 8000a98: 02dc6c00 .word 0x02dc6c00 + 8000a9c: 007a1200 .word 0x007a1200 + +08000aa0 : +{ + 8000aa0: b570 push {r4, r5, r6, lr} + 8000aa2: 0004 movs r4, r0 + 8000aa4: 000d movs r5, r1 + if (RCC_ClkInitStruct == NULL) + 8000aa6: 2800 cmp r0, #0 + 8000aa8: d100 bne.n 8000aac + 8000aaa: e0a4 b.n 8000bf6 + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8000aac: 4b54 ldr r3, [pc, #336] @ (8000c00 ) + 8000aae: 681a ldr r2, [r3, #0] + 8000ab0: 2307 movs r3, #7 + 8000ab2: 4013 ands r3, r2 + 8000ab4: 428b cmp r3, r1 + 8000ab6: d321 bcc.n 8000afc + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8000ab8: 6823 ldr r3, [r4, #0] + 8000aba: 079a lsls r2, r3, #30 + 8000abc: d510 bpl.n 8000ae0 + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8000abe: 075b lsls r3, r3, #29 + 8000ac0: d507 bpl.n 8000ad2 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + 8000ac2: 4950 ldr r1, [pc, #320] @ (8000c04 ) + 8000ac4: 688a ldr r2, [r1, #8] + 8000ac6: 4b50 ldr r3, [pc, #320] @ (8000c08 ) + 8000ac8: 401a ands r2, r3 + 8000aca: 23b0 movs r3, #176 @ 0xb0 + 8000acc: 011b lsls r3, r3, #4 + 8000ace: 4313 orrs r3, r2 + 8000ad0: 608b str r3, [r1, #8] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8000ad2: 4a4c ldr r2, [pc, #304] @ (8000c04 ) + 8000ad4: 6893 ldr r3, [r2, #8] + 8000ad6: 494d ldr r1, [pc, #308] @ (8000c0c ) + 8000ad8: 400b ands r3, r1 + 8000ada: 68e1 ldr r1, [r4, #12] + 8000adc: 430b orrs r3, r1 + 8000ade: 6093 str r3, [r2, #8] + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8000ae0: 6823 ldr r3, [r4, #0] + 8000ae2: 07db lsls r3, r3, #31 + 8000ae4: d54c bpl.n 8000b80 + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8000ae6: 6863 ldr r3, [r4, #4] + 8000ae8: 2b01 cmp r3, #1 + 8000aea: d01e beq.n 8000b2a + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8000aec: 2b00 cmp r3, #0 + 8000aee: d139 bne.n 8000b64 + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 8000af0: 4a44 ldr r2, [pc, #272] @ (8000c04 ) + 8000af2: 6812 ldr r2, [r2, #0] + 8000af4: 0552 lsls r2, r2, #21 + 8000af6: d41c bmi.n 8000b32 + return HAL_ERROR; + 8000af8: 2001 movs r0, #1 + 8000afa: e064 b.n 8000bc6 + __HAL_FLASH_SET_LATENCY(FLatency); + 8000afc: 4a40 ldr r2, [pc, #256] @ (8000c00 ) + 8000afe: 6813 ldr r3, [r2, #0] + 8000b00: 2107 movs r1, #7 + 8000b02: 438b bics r3, r1 + 8000b04: 432b orrs r3, r5 + 8000b06: 6013 str r3, [r2, #0] + tickstart = HAL_GetTick(); + 8000b08: f7ff fc7e bl 8000408 + 8000b0c: 0006 movs r6, r0 + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 8000b0e: 4b3c ldr r3, [pc, #240] @ (8000c00 ) + 8000b10: 681a ldr r2, [r3, #0] + 8000b12: 2307 movs r3, #7 + 8000b14: 4013 ands r3, r2 + 8000b16: 42ab cmp r3, r5 + 8000b18: d0ce beq.n 8000ab8 + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + 8000b1a: f7ff fc75 bl 8000408 + 8000b1e: 1b80 subs r0, r0, r6 + 8000b20: 4a3b ldr r2, [pc, #236] @ (8000c10 ) + 8000b22: 4290 cmp r0, r2 + 8000b24: d9f3 bls.n 8000b0e + return HAL_TIMEOUT; + 8000b26: 2003 movs r0, #3 + 8000b28: e04d b.n 8000bc6 + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 8000b2a: 4a36 ldr r2, [pc, #216] @ (8000c04 ) + 8000b2c: 6812 ldr r2, [r2, #0] + 8000b2e: 0392 lsls r2, r2, #14 + 8000b30: d563 bpl.n 8000bfa + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + 8000b32: 4934 ldr r1, [pc, #208] @ (8000c04 ) + 8000b34: 688a ldr r2, [r1, #8] + 8000b36: 2007 movs r0, #7 + 8000b38: 4382 bics r2, r0 + 8000b3a: 4313 orrs r3, r2 + 8000b3c: 608b str r3, [r1, #8] + tickstart = HAL_GetTick(); + 8000b3e: f7ff fc63 bl 8000408 + 8000b42: 0006 movs r6, r0 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8000b44: 4b2f ldr r3, [pc, #188] @ (8000c04 ) + 8000b46: 689b ldr r3, [r3, #8] + 8000b48: 2238 movs r2, #56 @ 0x38 + 8000b4a: 401a ands r2, r3 + 8000b4c: 6863 ldr r3, [r4, #4] + 8000b4e: 00db lsls r3, r3, #3 + 8000b50: 429a cmp r2, r3 + 8000b52: d015 beq.n 8000b80 + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + 8000b54: f7ff fc58 bl 8000408 + 8000b58: 1b80 subs r0, r0, r6 + 8000b5a: 4b2d ldr r3, [pc, #180] @ (8000c10 ) + 8000b5c: 4298 cmp r0, r3 + 8000b5e: d9f1 bls.n 8000b44 + return HAL_TIMEOUT; + 8000b60: 2003 movs r0, #3 + 8000b62: e030 b.n 8000bc6 + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) + 8000b64: 2b03 cmp r3, #3 + 8000b66: d005 beq.n 8000b74 + if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) + 8000b68: 4a26 ldr r2, [pc, #152] @ (8000c04 ) + 8000b6a: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8000b6c: 0792 lsls r2, r2, #30 + 8000b6e: d4e0 bmi.n 8000b32 + return HAL_ERROR; + 8000b70: 2001 movs r0, #1 + 8000b72: e028 b.n 8000bc6 + if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) + 8000b74: 4a23 ldr r2, [pc, #140] @ (8000c04 ) + 8000b76: 6e12 ldr r2, [r2, #96] @ 0x60 + 8000b78: 0792 lsls r2, r2, #30 + 8000b7a: d4da bmi.n 8000b32 + return HAL_ERROR; + 8000b7c: 2001 movs r0, #1 + 8000b7e: e022 b.n 8000bc6 + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8000b80: 4b1f ldr r3, [pc, #124] @ (8000c00 ) + 8000b82: 681a ldr r2, [r3, #0] + 8000b84: 2307 movs r3, #7 + 8000b86: 4013 ands r3, r2 + 8000b88: 42ab cmp r3, r5 + 8000b8a: d81d bhi.n 8000bc8 + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8000b8c: 6823 ldr r3, [r4, #0] + 8000b8e: 075b lsls r3, r3, #29 + 8000b90: d506 bpl.n 8000ba0 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + 8000b92: 4a1c ldr r2, [pc, #112] @ (8000c04 ) + 8000b94: 6893 ldr r3, [r2, #8] + 8000b96: 491f ldr r1, [pc, #124] @ (8000c14 ) + 8000b98: 400b ands r3, r1 + 8000b9a: 6921 ldr r1, [r4, #16] + 8000b9c: 430b orrs r3, r1 + 8000b9e: 6093 str r3, [r2, #8] + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ + 8000ba0: f7ff ff4e bl 8000a40 + 8000ba4: 4b17 ldr r3, [pc, #92] @ (8000c04 ) + 8000ba6: 689a ldr r2, [r3, #8] + >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + 8000ba8: 0a12 lsrs r2, r2, #8 + 8000baa: 230f movs r3, #15 + 8000bac: 4013 ands r3, r2 + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ + 8000bae: 4a1a ldr r2, [pc, #104] @ (8000c18 ) + 8000bb0: 009b lsls r3, r3, #2 + 8000bb2: 589a ldr r2, [r3, r2] + >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + 8000bb4: 231f movs r3, #31 + 8000bb6: 4013 ands r3, r2 + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ + 8000bb8: 40d8 lsrs r0, r3 + 8000bba: 4b18 ldr r3, [pc, #96] @ (8000c1c ) + 8000bbc: 6018 str r0, [r3, #0] + return HAL_InitTick(uwTickPrio); + 8000bbe: 4b18 ldr r3, [pc, #96] @ (8000c20 ) + 8000bc0: 6818 ldr r0, [r3, #0] + 8000bc2: f7ff fbdd bl 8000380 +} + 8000bc6: bd70 pop {r4, r5, r6, pc} + __HAL_FLASH_SET_LATENCY(FLatency); + 8000bc8: 4a0d ldr r2, [pc, #52] @ (8000c00 ) + 8000bca: 6813 ldr r3, [r2, #0] + 8000bcc: 2107 movs r1, #7 + 8000bce: 438b bics r3, r1 + 8000bd0: 432b orrs r3, r5 + 8000bd2: 6013 str r3, [r2, #0] + tickstart = HAL_GetTick(); + 8000bd4: f7ff fc18 bl 8000408 + 8000bd8: 0006 movs r6, r0 + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 8000bda: 4b09 ldr r3, [pc, #36] @ (8000c00 ) + 8000bdc: 681a ldr r2, [r3, #0] + 8000bde: 2307 movs r3, #7 + 8000be0: 4013 ands r3, r2 + 8000be2: 42ab cmp r3, r5 + 8000be4: d0d2 beq.n 8000b8c + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + 8000be6: f7ff fc0f bl 8000408 + 8000bea: 1b80 subs r0, r0, r6 + 8000bec: 4b08 ldr r3, [pc, #32] @ (8000c10 ) + 8000bee: 4298 cmp r0, r3 + 8000bf0: d9f3 bls.n 8000bda + return HAL_TIMEOUT; + 8000bf2: 2003 movs r0, #3 + 8000bf4: e7e7 b.n 8000bc6 + return HAL_ERROR; + 8000bf6: 2001 movs r0, #1 + 8000bf8: e7e5 b.n 8000bc6 + return HAL_ERROR; + 8000bfa: 2001 movs r0, #1 + 8000bfc: e7e3 b.n 8000bc6 + 8000bfe: 46c0 nop @ (mov r8, r8) + 8000c00: 40022000 .word 0x40022000 + 8000c04: 40021000 .word 0x40021000 + 8000c08: ffff84ff .word 0xffff84ff + 8000c0c: fffff0ff .word 0xfffff0ff + 8000c10: 00001388 .word 0x00001388 + 8000c14: ffff8fff .word 0xffff8fff + 8000c18: 08002768 .word 0x08002768 + 8000c1c: 20000000 .word 0x20000000 + 8000c20: 20000008 .word 0x20000008 + +08000c24 : + + +// Diese funktion muss regelmäßig aufgerufen werden um die Taster abzufragen. +// 1ms +button_state_t BUTTON_Exec(void) +{ + 8000c24: b510 push {r4, lr} + + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_SET) + 8000c26: 2101 movs r1, #1 + 8000c28: 4829 ldr r0, [pc, #164] @ (8000cd0 ) + 8000c2a: f7ff fd9d bl 8000768 + 8000c2e: 2801 cmp r0, #1 + 8000c30: d00f beq.n 8000c52 + //Taste On wird gedrückt + longPressCounterButtonOn++; + } + + + if (longPressCounterButtonOn > LONG_PRESS_TIME) + 8000c32: 4b28 ldr r3, [pc, #160] @ (8000cd4 ) + 8000c34: 681b ldr r3, [r3, #0] + 8000c36: 4a28 ldr r2, [pc, #160] @ (8000cd8 ) + 8000c38: 4293 cmp r3, r2 + 8000c3a: d90f bls.n 8000c5c + { + + if (buttonState != BUTTON_MANUAL_ON) + 8000c3c: 4b27 ldr r3, [pc, #156] @ (8000cdc ) + 8000c3e: 781b ldrb r3, [r3, #0] + 8000c40: 2b02 cmp r3, #2 + 8000c42: d00d beq.n 8000c60 + { + printf("BUTTON: Auto Mode Manual On\n"); + 8000c44: 4826 ldr r0, [pc, #152] @ (8000ce0 ) + 8000c46: f000 feed bl 8001a24 + buttonState = BUTTON_MANUAL_ON; + 8000c4a: 4b24 ldr r3, [pc, #144] @ (8000cdc ) + 8000c4c: 2202 movs r2, #2 + 8000c4e: 701a strb r2, [r3, #0] + 8000c50: e006 b.n 8000c60 + longPressCounterButtonOn++; + 8000c52: 4a20 ldr r2, [pc, #128] @ (8000cd4 ) + 8000c54: 6813 ldr r3, [r2, #0] + 8000c56: 3301 adds r3, #1 + 8000c58: 6013 str r3, [r2, #0] + 8000c5a: e7ea b.n 8000c32 + } + } + else if ( (longPressCounterButtonOn > MIN_PRESS_TIME) && (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET)) + 8000c5c: 2b0a cmp r3, #10 + 8000c5e: d814 bhi.n 8000c8a + } + } + + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET) + 8000c60: 2101 movs r1, #1 + 8000c62: 481b ldr r0, [pc, #108] @ (8000cd0 ) + 8000c64: f7ff fd80 bl 8000768 + 8000c68: 2800 cmp r0, #0 + 8000c6a: d102 bne.n 8000c72 + { + longPressCounterButtonOn = 0; + 8000c6c: 4b19 ldr r3, [pc, #100] @ (8000cd4 ) + 8000c6e: 2200 movs r2, #0 + 8000c70: 601a str r2, [r3, #0] + } + + + // ------ Taste OFF ----- + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_OFF_GPIO_Port, GPIO_INPUT_BTN_OFF_Pin) == GPIO_PIN_SET) + 8000c72: 2102 movs r1, #2 + 8000c74: 4816 ldr r0, [pc, #88] @ (8000cd0 ) + 8000c76: f7ff fd77 bl 8000768 + 8000c7a: 2801 cmp r0, #1 + 8000c7c: d016 beq.n 8000cac + } + } + } + else + { + longPressCounterButtonOff = 0; + 8000c7e: 4b19 ldr r3, [pc, #100] @ (8000ce4 ) + 8000c80: 2200 movs r2, #0 + 8000c82: 601a str r2, [r3, #0] + } + + return buttonState; + 8000c84: 4b15 ldr r3, [pc, #84] @ (8000cdc ) + 8000c86: 7818 ldrb r0, [r3, #0] + +} + 8000c88: bd10 pop {r4, pc} + else if ( (longPressCounterButtonOn > MIN_PRESS_TIME) && (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET)) + 8000c8a: 2101 movs r1, #1 + 8000c8c: 4810 ldr r0, [pc, #64] @ (8000cd0 ) + 8000c8e: f7ff fd6b bl 8000768 + 8000c92: 2800 cmp r0, #0 + 8000c94: d1e4 bne.n 8000c60 + if (buttonState != BUTTON_AUTO) + 8000c96: 4b11 ldr r3, [pc, #68] @ (8000cdc ) + 8000c98: 781b ldrb r3, [r3, #0] + 8000c9a: 2b01 cmp r3, #1 + 8000c9c: d0e0 beq.n 8000c60 + printf("BUTTON: Auto Mode\n"); + 8000c9e: 4812 ldr r0, [pc, #72] @ (8000ce8 ) + 8000ca0: f000 fec0 bl 8001a24 + buttonState = BUTTON_AUTO; + 8000ca4: 4b0d ldr r3, [pc, #52] @ (8000cdc ) + 8000ca6: 2201 movs r2, #1 + 8000ca8: 701a strb r2, [r3, #0] + 8000caa: e7d9 b.n 8000c60 + longPressCounterButtonOff++; + 8000cac: 4a0d ldr r2, [pc, #52] @ (8000ce4 ) + 8000cae: 6813 ldr r3, [r2, #0] + 8000cb0: 3301 adds r3, #1 + 8000cb2: 6013 str r3, [r2, #0] + if (longPressCounterButtonOff > MIN_PRESS_TIME) + 8000cb4: 2b0a cmp r3, #10 + 8000cb6: d9e5 bls.n 8000c84 + if (buttonState != BUTTON_OFF) + 8000cb8: 4b08 ldr r3, [pc, #32] @ (8000cdc ) + 8000cba: 781b ldrb r3, [r3, #0] + 8000cbc: 2b00 cmp r3, #0 + 8000cbe: d0e1 beq.n 8000c84 + printf("BUTTON: Off Mode\n"); + 8000cc0: 480a ldr r0, [pc, #40] @ (8000cec ) + 8000cc2: f000 feaf bl 8001a24 + buttonState = BUTTON_OFF; + 8000cc6: 4b05 ldr r3, [pc, #20] @ (8000cdc ) + 8000cc8: 2200 movs r2, #0 + 8000cca: 701a strb r2, [r3, #0] + 8000ccc: e7da b.n 8000c84 + 8000cce: 46c0 nop @ (mov r8, r8) + 8000cd0: 50000400 .word 0x50000400 + 8000cd4: 200000ec .word 0x200000ec + 8000cd8: 00001388 .word 0x00001388 + 8000cdc: 200000f0 .word 0x200000f0 + 8000ce0: 080027a8 .word 0x080027a8 + 8000ce4: 200000e8 .word 0x200000e8 + 8000ce8: 080027c4 .word 0x080027c4 + 8000cec: 080027d8 .word 0x080027d8 + +08000cf0 : + + +button_state_t BUTTON_GetMode(void) +{ + return buttonState; + 8000cf0: 4b01 ldr r3, [pc, #4] @ (8000cf8 ) + 8000cf2: 7818 ldrb r0, [r3, #0] +} + 8000cf4: 4770 bx lr + 8000cf6: 46c0 nop @ (mov r8, r8) + 8000cf8: 200000f0 .word 0x200000f0 + +08000cfc : + +void BUTTON_SetModeOff(void) +{ + buttonState = BUTTON_OFF; + 8000cfc: 4b01 ldr r3, [pc, #4] @ (8000d04 ) + 8000cfe: 2200 movs r2, #0 + 8000d00: 701a strb r2, [r3, #0] + 8000d02: 4770 bx lr + 8000d04: 200000f0 .word 0x200000f0 + +08000d08 : +unsigned int alarmMode; + + + +void BUZZER_Exec(void) +{ + 8000d08: b510 push {r4, lr} + + if (onTimeCounter > 0) + 8000d0a: 4b15 ldr r3, [pc, #84] @ (8000d60 ) + 8000d0c: 681b ldr r3, [r3, #0] + 8000d0e: 2b00 cmp r3, #0 + 8000d10: d004 beq.n 8000d1c + { + onTimeCounter--; + 8000d12: 3b01 subs r3, #1 + 8000d14: 4a12 ldr r2, [pc, #72] @ (8000d60 ) + 8000d16: 6013 str r3, [r2, #0] + if (onTimeCounter == 0) + 8000d18: 2b00 cmp r3, #0 + 8000d1a: d009 beq.n 8000d30 + + if (alarmMode == 1) offTimeCounter = offTime; + } + } + + if (offTimeCounter > 0) + 8000d1c: 4b11 ldr r3, [pc, #68] @ (8000d64 ) + 8000d1e: 681b ldr r3, [r3, #0] + 8000d20: 2b00 cmp r3, #0 + 8000d22: d004 beq.n 8000d2e + { + offTimeCounter--; + 8000d24: 3b01 subs r3, #1 + 8000d26: 4a0f ldr r2, [pc, #60] @ (8000d64 ) + 8000d28: 6013 str r3, [r2, #0] + if (offTimeCounter == 0) + 8000d2a: 2b00 cmp r3, #0 + 8000d2c: d00e beq.n 8000d4c + { + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = onTime; + } + } +} + 8000d2e: bd10 pop {r4, pc} + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + 8000d30: 2200 movs r2, #0 + 8000d32: 2120 movs r1, #32 + 8000d34: 480c ldr r0, [pc, #48] @ (8000d68 ) + 8000d36: f7ff fd1e bl 8000776 + if (alarmMode == 1) offTimeCounter = offTime; + 8000d3a: 4b0c ldr r3, [pc, #48] @ (8000d6c ) + 8000d3c: 681b ldr r3, [r3, #0] + 8000d3e: 2b01 cmp r3, #1 + 8000d40: d1ec bne.n 8000d1c + 8000d42: 4b08 ldr r3, [pc, #32] @ (8000d64 ) + 8000d44: 4a0a ldr r2, [pc, #40] @ (8000d70 ) + 8000d46: 6812 ldr r2, [r2, #0] + 8000d48: 601a str r2, [r3, #0] + 8000d4a: e7e7 b.n 8000d1c + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + 8000d4c: 2201 movs r2, #1 + 8000d4e: 2120 movs r1, #32 + 8000d50: 4805 ldr r0, [pc, #20] @ (8000d68 ) + 8000d52: f7ff fd10 bl 8000776 + onTimeCounter = onTime; + 8000d56: 4b02 ldr r3, [pc, #8] @ (8000d60 ) + 8000d58: 4a06 ldr r2, [pc, #24] @ (8000d74 ) + 8000d5a: 6812 ldr r2, [r2, #0] + 8000d5c: 601a str r2, [r3, #0] +} + 8000d5e: e7e6 b.n 8000d2e + 8000d60: 20000104 .word 0x20000104 + 8000d64: 20000100 .word 0x20000100 + 8000d68: 50000400 .word 0x50000400 + 8000d6c: 200000f4 .word 0x200000f4 + 8000d70: 200000f8 .word 0x200000f8 + 8000d74: 200000fc .word 0x200000fc + +08000d78 : + + + +void BUZZER_Beep(unsigned int time) +{ + 8000d78: b510 push {r4, lr} + 8000d7a: 0004 movs r4, r0 + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + 8000d7c: 2201 movs r2, #1 + 8000d7e: 2120 movs r1, #32 + 8000d80: 4802 ldr r0, [pc, #8] @ (8000d8c ) + 8000d82: f7ff fcf8 bl 8000776 + onTimeCounter = time; + 8000d86: 4b02 ldr r3, [pc, #8] @ (8000d90 ) + 8000d88: 601c str r4, [r3, #0] + +} + 8000d8a: bd10 pop {r4, pc} + 8000d8c: 50000400 .word 0x50000400 + 8000d90: 20000104 .word 0x20000104 + +08000d94 : + +void BUZZER_Alarm_Start(unsigned int on, unsigned int off ) +{ + 8000d94: b510 push {r4, lr} + 8000d96: 0004 movs r4, r0 + onTime = on; + 8000d98: 4b06 ldr r3, [pc, #24] @ (8000db4 ) + 8000d9a: 6018 str r0, [r3, #0] + offTime = off; + 8000d9c: 4b06 ldr r3, [pc, #24] @ (8000db8 ) + 8000d9e: 6019 str r1, [r3, #0] + alarmMode = 1; + 8000da0: 4b06 ldr r3, [pc, #24] @ (8000dbc ) + 8000da2: 2201 movs r2, #1 + 8000da4: 601a str r2, [r3, #0] + + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + 8000da6: 2120 movs r1, #32 + 8000da8: 4805 ldr r0, [pc, #20] @ (8000dc0 ) + 8000daa: f7ff fce4 bl 8000776 + onTimeCounter = on; + 8000dae: 4b05 ldr r3, [pc, #20] @ (8000dc4 ) + 8000db0: 601c str r4, [r3, #0] + +} + 8000db2: bd10 pop {r4, pc} + 8000db4: 200000fc .word 0x200000fc + 8000db8: 200000f8 .word 0x200000f8 + 8000dbc: 200000f4 .word 0x200000f4 + 8000dc0: 50000400 .word 0x50000400 + 8000dc4: 20000104 .word 0x20000104 + +08000dc8 : + +void BUZZER_Alarm_Stop(void) +{ + 8000dc8: b510 push {r4, lr} + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + 8000dca: 2200 movs r2, #0 + 8000dcc: 2120 movs r1, #32 + 8000dce: 4805 ldr r0, [pc, #20] @ (8000de4 ) + 8000dd0: f7ff fcd1 bl 8000776 + alarmMode = 0; + 8000dd4: 4a04 ldr r2, [pc, #16] @ (8000de8 ) + 8000dd6: 2300 movs r3, #0 + 8000dd8: 6013 str r3, [r2, #0] + offTimeCounter = 0; + 8000dda: 4a04 ldr r2, [pc, #16] @ (8000dec ) + 8000ddc: 6013 str r3, [r2, #0] + onTimeCounter = 0; + 8000dde: 4a04 ldr r2, [pc, #16] @ (8000df0 ) + 8000de0: 6013 str r3, [r2, #0] + + 8000de2: bd10 pop {r4, pc} + 8000de4: 50000400 .word 0x50000400 + 8000de8: 200000f4 .word 0x200000f4 + 8000dec: 20000100 .word 0x20000100 + 8000df0: 20000104 .word 0x20000104 + +08000df4 : +unsigned int onTimeRT; +unsigned int offTimeRT; +unsigned int blinkModeRT; + +void LEDS_Exec(void) +{ + 8000df4: b510 push {r4, lr} + + if (onTimeCounterGN > 0) + 8000df6: 4b2c ldr r3, [pc, #176] @ (8000ea8 ) + 8000df8: 681b ldr r3, [r3, #0] + 8000dfa: 2b00 cmp r3, #0 + 8000dfc: d004 beq.n 8000e08 + { + onTimeCounterGN--; + 8000dfe: 3b01 subs r3, #1 + 8000e00: 4a29 ldr r2, [pc, #164] @ (8000ea8 ) + 8000e02: 6013 str r3, [r2, #0] + if (onTimeCounterGN == 0) + 8000e04: 2b00 cmp r3, #0 + 8000e06: d01b beq.n 8000e40 + + if (blinkModeGN == 1) offTimeCounterGN = offTimeGN; + } + } + + if (offTimeCounterGN > 0) + 8000e08: 4b28 ldr r3, [pc, #160] @ (8000eac ) + 8000e0a: 681b ldr r3, [r3, #0] + 8000e0c: 2b00 cmp r3, #0 + 8000e0e: d004 beq.n 8000e1a + { + offTimeCounterGN--; + 8000e10: 3b01 subs r3, #1 + 8000e12: 4a26 ldr r2, [pc, #152] @ (8000eac ) + 8000e14: 6013 str r3, [r2, #0] + if (offTimeCounterGN == 0) + 8000e16: 2b00 cmp r3, #0 + 8000e18: d021 beq.n 8000e5e + } + } + + + // --- LED ROT --- + if (onTimeCounterRT > 0) + 8000e1a: 4b25 ldr r3, [pc, #148] @ (8000eb0 ) + 8000e1c: 681b ldr r3, [r3, #0] + 8000e1e: 2b00 cmp r3, #0 + 8000e20: d004 beq.n 8000e2c + { + onTimeCounterRT--; + 8000e22: 3b01 subs r3, #1 + 8000e24: 4a22 ldr r2, [pc, #136] @ (8000eb0 ) + 8000e26: 6013 str r3, [r2, #0] + if (onTimeCounterRT == 0) + 8000e28: 2b00 cmp r3, #0 + 8000e2a: d023 beq.n 8000e74 + + if (blinkModeRT == 1) offTimeCounterRT = offTimeRT; + } + } + + if (offTimeCounterRT > 0) + 8000e2c: 4b21 ldr r3, [pc, #132] @ (8000eb4 ) + 8000e2e: 681b ldr r3, [r3, #0] + 8000e30: 2b00 cmp r3, #0 + 8000e32: d004 beq.n 8000e3e + { + offTimeCounterRT--; + 8000e34: 3b01 subs r3, #1 + 8000e36: 4a1f ldr r2, [pc, #124] @ (8000eb4 ) + 8000e38: 6013 str r3, [r2, #0] + if (offTimeCounterRT == 0) + 8000e3a: 2b00 cmp r3, #0 + 8000e3c: d029 beq.n 8000e92 + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = onTimeRT; + } + } +} + 8000e3e: bd10 pop {r4, pc} + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + 8000e40: 2180 movs r1, #128 @ 0x80 + 8000e42: 2200 movs r2, #0 + 8000e44: 01c9 lsls r1, r1, #7 + 8000e46: 481c ldr r0, [pc, #112] @ (8000eb8 ) + 8000e48: f7ff fc95 bl 8000776 + if (blinkModeGN == 1) offTimeCounterGN = offTimeGN; + 8000e4c: 4b1b ldr r3, [pc, #108] @ (8000ebc ) + 8000e4e: 681b ldr r3, [r3, #0] + 8000e50: 2b01 cmp r3, #1 + 8000e52: d1d9 bne.n 8000e08 + 8000e54: 4b15 ldr r3, [pc, #84] @ (8000eac ) + 8000e56: 4a1a ldr r2, [pc, #104] @ (8000ec0 ) + 8000e58: 6812 ldr r2, [r2, #0] + 8000e5a: 601a str r2, [r3, #0] + 8000e5c: e7d4 b.n 8000e08 + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + 8000e5e: 2180 movs r1, #128 @ 0x80 + 8000e60: 2201 movs r2, #1 + 8000e62: 01c9 lsls r1, r1, #7 + 8000e64: 4814 ldr r0, [pc, #80] @ (8000eb8 ) + 8000e66: f7ff fc86 bl 8000776 + onTimeCounterGN = onTimeGN; + 8000e6a: 4b0f ldr r3, [pc, #60] @ (8000ea8 ) + 8000e6c: 4a15 ldr r2, [pc, #84] @ (8000ec4 ) + 8000e6e: 6812 ldr r2, [r2, #0] + 8000e70: 601a str r2, [r3, #0] + 8000e72: e7d2 b.n 8000e1a + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + 8000e74: 2180 movs r1, #128 @ 0x80 + 8000e76: 2200 movs r2, #0 + 8000e78: 0209 lsls r1, r1, #8 + 8000e7a: 480f ldr r0, [pc, #60] @ (8000eb8 ) + 8000e7c: f7ff fc7b bl 8000776 + if (blinkModeRT == 1) offTimeCounterRT = offTimeRT; + 8000e80: 4b11 ldr r3, [pc, #68] @ (8000ec8 ) + 8000e82: 681b ldr r3, [r3, #0] + 8000e84: 2b01 cmp r3, #1 + 8000e86: d1d1 bne.n 8000e2c + 8000e88: 4b0a ldr r3, [pc, #40] @ (8000eb4 ) + 8000e8a: 4a10 ldr r2, [pc, #64] @ (8000ecc ) + 8000e8c: 6812 ldr r2, [r2, #0] + 8000e8e: 601a str r2, [r3, #0] + 8000e90: e7cc b.n 8000e2c + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + 8000e92: 2180 movs r1, #128 @ 0x80 + 8000e94: 2201 movs r2, #1 + 8000e96: 0209 lsls r1, r1, #8 + 8000e98: 4807 ldr r0, [pc, #28] @ (8000eb8 ) + 8000e9a: f7ff fc6c bl 8000776 + onTimeCounterRT = onTimeRT; + 8000e9e: 4b04 ldr r3, [pc, #16] @ (8000eb0 ) + 8000ea0: 4a0b ldr r2, [pc, #44] @ (8000ed0 ) + 8000ea2: 6812 ldr r2, [r2, #0] + 8000ea4: 601a str r2, [r3, #0] +} + 8000ea6: e7ca b.n 8000e3e + 8000ea8: 2000012c .word 0x2000012c + 8000eac: 20000128 .word 0x20000128 + 8000eb0: 20000118 .word 0x20000118 + 8000eb4: 20000114 .word 0x20000114 + 8000eb8: 50000800 .word 0x50000800 + 8000ebc: 2000011c .word 0x2000011c + 8000ec0: 20000120 .word 0x20000120 + 8000ec4: 20000124 .word 0x20000124 + 8000ec8: 20000108 .word 0x20000108 + 8000ecc: 2000010c .word 0x2000010c + 8000ed0: 20000110 .word 0x20000110 + +08000ed4 : + +// --- Steuerfunktionen LED grün ------------ +void LEDS_GN_On(void) +{ + 8000ed4: b510 push {r4, lr} + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + 8000ed6: 2180 movs r1, #128 @ 0x80 + 8000ed8: 2201 movs r2, #1 + 8000eda: 01c9 lsls r1, r1, #7 + 8000edc: 4805 ldr r0, [pc, #20] @ (8000ef4 ) + 8000ede: f7ff fc4a bl 8000776 + + blinkModeGN = 0; // Blinkmode zurücksetzen, falls es eingeschaltet war + 8000ee2: 4a05 ldr r2, [pc, #20] @ (8000ef8 ) + 8000ee4: 2300 movs r3, #0 + 8000ee6: 6013 str r3, [r2, #0] + onTimeCounterGN = 0; + 8000ee8: 4a04 ldr r2, [pc, #16] @ (8000efc ) + 8000eea: 6013 str r3, [r2, #0] + offTimeCounterGN = 0; + 8000eec: 4a04 ldr r2, [pc, #16] @ (8000f00 ) + 8000eee: 6013 str r3, [r2, #0] +} + 8000ef0: bd10 pop {r4, pc} + 8000ef2: 46c0 nop @ (mov r8, r8) + 8000ef4: 50000800 .word 0x50000800 + 8000ef8: 2000011c .word 0x2000011c + 8000efc: 2000012c .word 0x2000012c + 8000f00: 20000128 .word 0x20000128 + +08000f04 : + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = time; +} + +void LEDS_GN_Blink_Start(unsigned int on, unsigned int off ) +{ + 8000f04: b510 push {r4, lr} + 8000f06: 0004 movs r4, r0 + onTimeGN = on; + 8000f08: 4b07 ldr r3, [pc, #28] @ (8000f28 ) + 8000f0a: 6018 str r0, [r3, #0] + offTimeGN = off; + 8000f0c: 4b07 ldr r3, [pc, #28] @ (8000f2c ) + 8000f0e: 6019 str r1, [r3, #0] + blinkModeGN = 1; + 8000f10: 4b07 ldr r3, [pc, #28] @ (8000f30 ) + 8000f12: 2201 movs r2, #1 + 8000f14: 601a str r2, [r3, #0] + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + 8000f16: 2180 movs r1, #128 @ 0x80 + 8000f18: 01c9 lsls r1, r1, #7 + 8000f1a: 4806 ldr r0, [pc, #24] @ (8000f34 ) + 8000f1c: f7ff fc2b bl 8000776 + onTimeCounterGN = on; + 8000f20: 4b05 ldr r3, [pc, #20] @ (8000f38 ) + 8000f22: 601c str r4, [r3, #0] +} + 8000f24: bd10 pop {r4, pc} + 8000f26: 46c0 nop @ (mov r8, r8) + 8000f28: 20000124 .word 0x20000124 + 8000f2c: 20000120 .word 0x20000120 + 8000f30: 2000011c .word 0x2000011c + 8000f34: 50000800 .word 0x50000800 + 8000f38: 2000012c .word 0x2000012c + +08000f3c : + +void LEDS_GN_Off(void) +{ + 8000f3c: b510 push {r4, lr} + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + 8000f3e: 2180 movs r1, #128 @ 0x80 + 8000f40: 2200 movs r2, #0 + 8000f42: 01c9 lsls r1, r1, #7 + 8000f44: 4805 ldr r0, [pc, #20] @ (8000f5c ) + 8000f46: f7ff fc16 bl 8000776 + blinkModeGN = 0; + 8000f4a: 4a05 ldr r2, [pc, #20] @ (8000f60 ) + 8000f4c: 2300 movs r3, #0 + 8000f4e: 6013 str r3, [r2, #0] + offTimeCounterGN = 0; + 8000f50: 4a04 ldr r2, [pc, #16] @ (8000f64 ) + 8000f52: 6013 str r3, [r2, #0] + onTimeCounterGN = 0; + 8000f54: 4a04 ldr r2, [pc, #16] @ (8000f68 ) + 8000f56: 6013 str r3, [r2, #0] +} + 8000f58: bd10 pop {r4, pc} + 8000f5a: 46c0 nop @ (mov r8, r8) + 8000f5c: 50000800 .word 0x50000800 + 8000f60: 2000011c .word 0x2000011c + 8000f64: 20000128 .word 0x20000128 + 8000f68: 2000012c .word 0x2000012c + +08000f6c : + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = time; +} + +void LEDS_RT_Blink_Start(unsigned int on, unsigned int off ) +{ + 8000f6c: b510 push {r4, lr} + 8000f6e: 0004 movs r4, r0 + onTimeRT = on; + 8000f70: 4b07 ldr r3, [pc, #28] @ (8000f90 ) + 8000f72: 6018 str r0, [r3, #0] + offTimeRT = off; + 8000f74: 4b07 ldr r3, [pc, #28] @ (8000f94 ) + 8000f76: 6019 str r1, [r3, #0] + blinkModeRT = 1; + 8000f78: 4b07 ldr r3, [pc, #28] @ (8000f98 ) + 8000f7a: 2201 movs r2, #1 + 8000f7c: 601a str r2, [r3, #0] + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + 8000f7e: 2180 movs r1, #128 @ 0x80 + 8000f80: 0209 lsls r1, r1, #8 + 8000f82: 4806 ldr r0, [pc, #24] @ (8000f9c ) + 8000f84: f7ff fbf7 bl 8000776 + onTimeCounterRT = on; + 8000f88: 4b05 ldr r3, [pc, #20] @ (8000fa0 ) + 8000f8a: 601c str r4, [r3, #0] +} + 8000f8c: bd10 pop {r4, pc} + 8000f8e: 46c0 nop @ (mov r8, r8) + 8000f90: 20000110 .word 0x20000110 + 8000f94: 2000010c .word 0x2000010c + 8000f98: 20000108 .word 0x20000108 + 8000f9c: 50000800 .word 0x50000800 + 8000fa0: 20000118 .word 0x20000118 + +08000fa4 : + +void LEDS_RT_Off(void) +{ + 8000fa4: b510 push {r4, lr} + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + 8000fa6: 2180 movs r1, #128 @ 0x80 + 8000fa8: 2200 movs r2, #0 + 8000faa: 0209 lsls r1, r1, #8 + 8000fac: 4805 ldr r0, [pc, #20] @ (8000fc4 ) + 8000fae: f7ff fbe2 bl 8000776 + blinkModeRT = 0; + 8000fb2: 4a05 ldr r2, [pc, #20] @ (8000fc8 ) + 8000fb4: 2300 movs r3, #0 + 8000fb6: 6013 str r3, [r2, #0] + offTimeCounterRT = 0; + 8000fb8: 4a04 ldr r2, [pc, #16] @ (8000fcc ) + 8000fba: 6013 str r3, [r2, #0] + onTimeCounterRT = 0; + 8000fbc: 4a04 ldr r2, [pc, #16] @ (8000fd0 ) + 8000fbe: 6013 str r3, [r2, #0] + 8000fc0: bd10 pop {r4, pc} + 8000fc2: 46c0 nop @ (mov r8, r8) + 8000fc4: 50000800 .word 0x50000800 + 8000fc8: 20000108 .word 0x20000108 + 8000fcc: 20000114 .word 0x20000114 + 8000fd0: 20000118 .word 0x20000118 + +08000fd4 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000fd4: b5f0 push {r4, r5, r6, r7, lr} + 8000fd6: b089 sub sp, #36 @ 0x24 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000fd8: 2214 movs r2, #20 + 8000fda: 2100 movs r1, #0 + 8000fdc: a803 add r0, sp, #12 + 8000fde: f000 fe17 bl 8001c10 +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000fe2: 4b26 ldr r3, [pc, #152] @ (800107c ) + 8000fe4: 6b59 ldr r1, [r3, #52] @ 0x34 + 8000fe6: 2202 movs r2, #2 + 8000fe8: 4311 orrs r1, r2 + 8000fea: 6359 str r1, [r3, #52] @ 0x34 + 8000fec: 6b59 ldr r1, [r3, #52] @ 0x34 + 8000fee: 400a ands r2, r1 + 8000ff0: 9200 str r2, [sp, #0] + 8000ff2: 9a00 ldr r2, [sp, #0] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000ff4: 6b59 ldr r1, [r3, #52] @ 0x34 + 8000ff6: 2204 movs r2, #4 + 8000ff8: 4311 orrs r1, r2 + 8000ffa: 6359 str r1, [r3, #52] @ 0x34 + 8000ffc: 6b59 ldr r1, [r3, #52] @ 0x34 + 8000ffe: 400a ands r2, r1 + 8001000: 9201 str r2, [sp, #4] + 8001002: 9a01 ldr r2, [sp, #4] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001004: 6b5a ldr r2, [r3, #52] @ 0x34 + 8001006: 2401 movs r4, #1 + 8001008: 4322 orrs r2, r4 + 800100a: 635a str r2, [r3, #52] @ 0x34 + 800100c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800100e: 4023 ands r3, r4 + 8001010: 9302 str r3, [sp, #8] + 8001012: 9b02 ldr r3, [sp, #8] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_OUTPUT_LED_ON_Pin|GPIO_OUTPUT_LED_ERROR_Pin|GPIO_OUTPUT_RELAIS_SET_Pin|GPIO_OUTPUT_RELAIS_RESET_Pin + 8001014: 4f1a ldr r7, [pc, #104] @ (8001080 ) + 8001016: 26a0 movs r6, #160 @ 0xa0 + 8001018: 05f6 lsls r6, r6, #23 + 800101a: 2200 movs r2, #0 + 800101c: 0039 movs r1, r7 + 800101e: 0030 movs r0, r6 + 8001020: f7ff fba9 bl 8000776 + |GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : GPIO_INPUT_MODE_B3_Pin GPIO_INPUT_MODE_B2_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_MODE_B3_Pin|GPIO_INPUT_MODE_B2_Pin; + 8001024: 23c0 movs r3, #192 @ 0xc0 + 8001026: 009b lsls r3, r3, #2 + 8001028: 9303 str r3, [sp, #12] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800102a: 2500 movs r5, #0 + 800102c: 9504 str r5, [sp, #16] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800102e: 9405 str r4, [sp, #20] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001030: a903 add r1, sp, #12 + 8001032: 4814 ldr r0, [pc, #80] @ (8001084 ) + 8001034: f7ff faba bl 80005ac + + /*Configure GPIO pins : GPIO_INPUT_MODE_B1_Pin GPIO_INPUT_MODE_B0_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_MODE_B1_Pin|GPIO_INPUT_MODE_B0_Pin; + 8001038: 23c0 movs r3, #192 @ 0xc0 + 800103a: 9303 str r3, [sp, #12] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800103c: 9504 str r5, [sp, #16] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800103e: 9405 str r4, [sp, #20] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8001040: a903 add r1, sp, #12 + 8001042: 4811 ldr r0, [pc, #68] @ (8001088 ) + 8001044: f7ff fab2 bl 80005ac + + /*Configure GPIO pins : GPIO_INPUT_LVP_Pin GPIO_INPUT_OVP_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_LVP_Pin|GPIO_INPUT_OVP_Pin; + 8001048: 2303 movs r3, #3 + 800104a: 9303 str r3, [sp, #12] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800104c: 9504 str r5, [sp, #16] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800104e: 9405 str r4, [sp, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001050: a903 add r1, sp, #12 + 8001052: 0030 movs r0, r6 + 8001054: f7ff faaa bl 80005ac + + /*Configure GPIO pins : GPIO_INPUT_BTN_ON_Pin GPIO_INPUT_BTN_OFF_Pin GPIO_INPUT_FAULT_Pin GPIO_INPUT_BMS_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_BTN_ON_Pin|GPIO_INPUT_BTN_OFF_Pin|GPIO_INPUT_FAULT_Pin|GPIO_INPUT_BMS_Pin; + 8001058: 2347 movs r3, #71 @ 0x47 + 800105a: 9303 str r3, [sp, #12] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800105c: 9504 str r5, [sp, #16] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800105e: 9405 str r4, [sp, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001060: a903 add r1, sp, #12 + 8001062: 0030 movs r0, r6 + 8001064: f7ff faa2 bl 80005ac + + /*Configure GPIO pins : GPIO_OUTPUT_LED_ON_Pin GPIO_OUTPUT_LED_ERROR_Pin GPIO_OUTPUT_RELAIS_SET_Pin GPIO_OUTPUT_RELAIS_RESET_Pin + GPIO_OUTPUT_BUZZER_Pin */ + GPIO_InitStruct.Pin = GPIO_OUTPUT_LED_ON_Pin|GPIO_OUTPUT_LED_ERROR_Pin|GPIO_OUTPUT_RELAIS_SET_Pin|GPIO_OUTPUT_RELAIS_RESET_Pin + 8001068: 9703 str r7, [sp, #12] + |GPIO_OUTPUT_BUZZER_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800106a: 9404 str r4, [sp, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800106c: 9505 str r5, [sp, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800106e: 9506 str r5, [sp, #24] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001070: a903 add r1, sp, #12 + 8001072: 0030 movs r0, r6 + 8001074: f7ff fa9a bl 80005ac + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + 8001078: b009 add sp, #36 @ 0x24 + 800107a: bdf0 pop {r4, r5, r6, r7, pc} + 800107c: 40021000 .word 0x40021000 + 8001080: 0000c038 .word 0x0000c038 + 8001084: 50000400 .word 0x50000400 + 8001088: 50000800 .word 0x50000800 + +0800108c : + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800108c: b672 cpsid i +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 800108e: e7fe b.n 800108e + +08001090 : +{ + 8001090: b500 push {lr} + 8001092: b08d sub sp, #52 @ 0x34 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8001094: 221c movs r2, #28 + 8001096: 2100 movs r1, #0 + 8001098: a805 add r0, sp, #20 + 800109a: f000 fdb9 bl 8001c10 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 800109e: 2214 movs r2, #20 + 80010a0: 2100 movs r1, #0 + 80010a2: 4668 mov r0, sp + 80010a4: f000 fdb4 bl 8001c10 + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_0); + 80010a8: 4a12 ldr r2, [pc, #72] @ (80010f4 ) + 80010aa: 6813 ldr r3, [r2, #0] + 80010ac: 2107 movs r1, #7 + 80010ae: 438b bics r3, r1 + 80010b0: 6013 str r3, [r2, #0] + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 80010b2: 2302 movs r3, #2 + 80010b4: 9305 str r3, [sp, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 80010b6: 33fe adds r3, #254 @ 0xfe + 80010b8: 9308 str r3, [sp, #32] + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV4; + 80010ba: 2380 movs r3, #128 @ 0x80 + 80010bc: 015b lsls r3, r3, #5 + 80010be: 9309 str r3, [sp, #36] @ 0x24 + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 80010c0: 2340 movs r3, #64 @ 0x40 + 80010c2: 930a str r3, [sp, #40] @ 0x28 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80010c4: a805 add r0, sp, #20 + 80010c6: f7ff fb5d bl 8000784 + 80010ca: 2800 cmp r0, #0 + 80010cc: d10e bne.n 80010ec + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80010ce: 2307 movs r3, #7 + 80010d0: 9300 str r3, [sp, #0] + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 80010d2: 2300 movs r3, #0 + 80010d4: 9301 str r3, [sp, #4] + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + 80010d6: 9302 str r3, [sp, #8] + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + 80010d8: 9303 str r3, [sp, #12] + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + 80010da: 9304 str r3, [sp, #16] + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80010dc: 2100 movs r1, #0 + 80010de: 4668 mov r0, sp + 80010e0: f7ff fcde bl 8000aa0 + 80010e4: 2800 cmp r0, #0 + 80010e6: d103 bne.n 80010f0 +} + 80010e8: b00d add sp, #52 @ 0x34 + 80010ea: bd00 pop {pc} + Error_Handler(); + 80010ec: f7ff ffce bl 800108c + Error_Handler(); + 80010f0: f7ff ffcc bl 800108c + 80010f4: 40022000 .word 0x40022000 + +080010f8
: +{ + 80010f8: b510 push {r4, lr} + HAL_Init(); + 80010fa: f7ff f96d bl 80003d8 + SystemClock_Config(); + 80010fe: f7ff ffc7 bl 8001090 + MX_GPIO_Init(); + 8001102: f7ff ff67 bl 8000fd4 + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + 8001106: 4c1c ldr r4, [pc, #112] @ (8001178 ) + 8001108: 2200 movs r2, #0 + 800110a: 2108 movs r1, #8 + 800110c: 0020 movs r0, r4 + 800110e: f7ff fb32 bl 8000776 + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_SET); + 8001112: 2201 movs r2, #1 + 8001114: 2110 movs r1, #16 + 8001116: 0020 movs r0, r4 + 8001118: f7ff fb2d bl 8000776 + HAL_Delay(50); + 800111c: 2032 movs r0, #50 @ 0x32 + 800111e: f7ff f979 bl 8000414 + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + 8001122: 2200 movs r2, #0 + 8001124: 2110 movs r1, #16 + 8001126: 0020 movs r0, r4 + 8001128: f7ff fb25 bl 8000776 + MODESWITCH_ReadMode(); + 800112c: f000 fac0 bl 80016b0 + 8001130: e00e b.n 8001150 + BUTTON_Exec(); + 8001132: f7ff fd77 bl 8000c24 + BUZZER_Exec(); + 8001136: f7ff fde7 bl 8000d08 + RELAIS_Exec(); + 800113a: f000 faef bl 800171c + LEDS_Exec(); + 800113e: f7ff fe59 bl 8000df4 + oldTimeMSTick = HAL_GetTick(); + 8001142: f7ff f961 bl 8000408 + 8001146: 4b0d ldr r3, [pc, #52] @ (800117c ) + 8001148: 6018 str r0, [r3, #0] + 800114a: e007 b.n 800115c + MODE_MAINSWITCH_Exec(); + 800114c: f000 f91a bl 8001384 + if (oldTimeMSTick != HAL_GetTick()) + 8001150: f7ff f95a bl 8000408 + 8001154: 4b09 ldr r3, [pc, #36] @ (800117c ) + 8001156: 681b ldr r3, [r3, #0] + 8001158: 4298 cmp r0, r3 + 800115a: d1ea bne.n 8001132 + switch (MODESWITCH_GetMode()) + 800115c: f000 fad8 bl 8001710 + 8001160: 2800 cmp r0, #0 + 8001162: d0f3 beq.n 800114c + 8001164: 2801 cmp r0, #1 + 8001166: d003 beq.n 8001170 + printf("mode not yet implemented\n"); + 8001168: 4805 ldr r0, [pc, #20] @ (8001180 ) + 800116a: f000 fc5b bl 8001a24 + 800116e: e7ef b.n 8001150 + MODE_SECONDARYPROTECTION_Exec(); + 8001170: f000 fa84 bl 800167c + break; + 8001174: e7ec b.n 8001150 + 8001176: 46c0 nop @ (mov r8, r8) + 8001178: 50000400 .word 0x50000400 + 800117c: 20000130 .word 0x20000130 + 8001180: 080027ec .word 0x080027ec + +08001184 : + +static MAINSWITCH_state_t smState; + + +void MAINSWITCH_SM_Off(void) +{ + 8001184: b510 push {r4, lr} + int faultInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + 8001186: 2104 movs r1, #4 + 8001188: 4825 ldr r0, [pc, #148] @ (8001220 ) + 800118a: f7ff faed bl 8000768 + 800118e: 2800 cmp r0, #0 + 8001190: d109 bne.n 80011a6 + { + faultInput = 1; + 8001192: 2401 movs r4, #1 + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + 8001194: f7ff fdac bl 8000cf0 + 8001198: 2801 cmp r0, #1 + 800119a: d006 beq.n 80011aa + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + 800119c: f7ff fda8 bl 8000cf0 + 80011a0: 2802 cmp r0, #2 + 80011a2: d028 beq.n 80011f6 + smState = MAINSWITCH_MANUAL_ON; + } + + + +} + 80011a4: bd10 pop {r4, pc} + faultInput = 0; + 80011a6: 2400 movs r4, #0 + 80011a8: e7f4 b.n 8001194 + if (faultInput == 0) + 80011aa: 2c00 cmp r4, #0 + 80011ac: d110 bne.n 80011d0 + RELAIS_SetPuls(); + 80011ae: f000 fadb bl 8001768 + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + 80011b2: 20c8 movs r0, #200 @ 0xc8 + 80011b4: f7ff fde0 bl 8000d78 + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + 80011b8: 21fa movs r1, #250 @ 0xfa + 80011ba: 0089 lsls r1, r1, #2 + 80011bc: 20c8 movs r0, #200 @ 0xc8 + 80011be: f7ff fea1 bl 8000f04 + printf("NEW_STATE: MAINSWITCH_ON\n"); + 80011c2: 4818 ldr r0, [pc, #96] @ (8001224 ) + 80011c4: f000 fc2e bl 8001a24 + smState = MAINSWITCH_ON; + 80011c8: 4b17 ldr r3, [pc, #92] @ (8001228 ) + 80011ca: 2201 movs r2, #1 + 80011cc: 701a strb r2, [r3, #0] + 80011ce: e7e5 b.n 800119c + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + 80011d0: 24fa movs r4, #250 @ 0xfa + 80011d2: 0064 lsls r4, r4, #1 + 80011d4: 0020 movs r0, r4 + 80011d6: f7ff fdcf bl 8000d78 + BUTTON_SetModeOff(); + 80011da: f7ff fd8f bl 8000cfc + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + 80011de: 21fa movs r1, #250 @ 0xfa + 80011e0: 0089 lsls r1, r1, #2 + 80011e2: 0020 movs r0, r4 + 80011e4: f7ff fec2 bl 8000f6c + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + 80011e8: 4810 ldr r0, [pc, #64] @ (800122c ) + 80011ea: f000 fc1b bl 8001a24 + smState = MAINSWITCH_ERROR; + 80011ee: 4b0e ldr r3, [pc, #56] @ (8001228 ) + 80011f0: 2203 movs r2, #3 + 80011f2: 701a strb r2, [r3, #0] + 80011f4: e7d2 b.n 800119c + RELAIS_SetPuls(); + 80011f6: f000 fab7 bl 8001768 + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + 80011fa: 24fa movs r4, #250 @ 0xfa + 80011fc: 00a4 lsls r4, r4, #2 + 80011fe: 0021 movs r1, r4 + 8001200: 20c8 movs r0, #200 @ 0xc8 + 8001202: f7ff fdc7 bl 8000d94 + LEDS_GN_On(); + 8001206: f7ff fe65 bl 8000ed4 + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_GN_OFF_TIME); + 800120a: 0021 movs r1, r4 + 800120c: 20c8 movs r0, #200 @ 0xc8 + 800120e: f7ff fead bl 8000f6c + printf("NEW_STATE: MAINSWITCH_MANUAL_ON\n"); + 8001212: 4807 ldr r0, [pc, #28] @ (8001230 ) + 8001214: f000 fc06 bl 8001a24 + smState = MAINSWITCH_MANUAL_ON; + 8001218: 4b03 ldr r3, [pc, #12] @ (8001228 ) + 800121a: 2202 movs r2, #2 + 800121c: 701a strb r2, [r3, #0] +} + 800121e: e7c1 b.n 80011a4 + 8001220: 50000400 .word 0x50000400 + 8001224: 08002808 .word 0x08002808 + 8001228: 20000134 .word 0x20000134 + 800122c: 08002824 .word 0x08002824 + 8001230: 08002840 .word 0x08002840 + +08001234 : + +void MAINSWITCH_SM_On(void) +{ + 8001234: b510 push {r4, lr} + int faultInput; + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + 8001236: 2104 movs r1, #4 + 8001238: 481a ldr r0, [pc, #104] @ (80012a4 ) + 800123a: f7ff fa95 bl 8000768 + 800123e: 2800 cmp r0, #0 + 8001240: d107 bne.n 8001252 + { + faultInput = 1; + 8001242: 2401 movs r4, #1 + faultInput = 0; + } + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + 8001244: f7ff fd54 bl 8000cf0 + 8001248: 2800 cmp r0, #0 + 800124a: d004 beq.n 8001256 + printf("NEW_STATE: MAINSWITCH_OFF\n"); + smState = MAINSWITCH_OFF; + } + + //Prüfe auf Fehlermode + if (faultInput == 1) + 800124c: 2c01 cmp r4, #1 + 800124e: d012 beq.n 8001276 + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + smState = MAINSWITCH_ERROR; + } + + +} + 8001250: bd10 pop {r4, pc} + faultInput = 0; + 8001252: 2400 movs r4, #0 + 8001254: e7f6 b.n 8001244 + RELAIS_ResetPuls(); + 8001256: f000 faa1 bl 800179c + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + 800125a: 20c8 movs r0, #200 @ 0xc8 + 800125c: f7ff fd8c bl 8000d78 + LEDS_GN_Off(); + 8001260: f7ff fe6c bl 8000f3c + LEDS_RT_Off(); + 8001264: f7ff fe9e bl 8000fa4 + printf("NEW_STATE: MAINSWITCH_OFF\n"); + 8001268: 480f ldr r0, [pc, #60] @ (80012a8 ) + 800126a: f000 fbdb bl 8001a24 + smState = MAINSWITCH_OFF; + 800126e: 4b0f ldr r3, [pc, #60] @ (80012ac ) + 8001270: 2200 movs r2, #0 + 8001272: 701a strb r2, [r3, #0] + 8001274: e7ea b.n 800124c + RELAIS_ResetPuls(); + 8001276: f000 fa91 bl 800179c + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + 800127a: 34f4 adds r4, #244 @ 0xf4 + 800127c: 34ff adds r4, #255 @ 0xff + 800127e: 0020 movs r0, r4 + 8001280: f7ff fd7a bl 8000d78 + LEDS_GN_Off(); + 8001284: f7ff fe5a bl 8000f3c + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME); //Fehlercode fault + 8001288: 21fa movs r1, #250 @ 0xfa + 800128a: 0089 lsls r1, r1, #2 + 800128c: 0020 movs r0, r4 + 800128e: f7ff fe6d bl 8000f6c + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + 8001292: f7ff fd33 bl 8000cfc + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + 8001296: 4806 ldr r0, [pc, #24] @ (80012b0 ) + 8001298: f000 fbc4 bl 8001a24 + smState = MAINSWITCH_ERROR; + 800129c: 4b03 ldr r3, [pc, #12] @ (80012ac ) + 800129e: 2203 movs r2, #3 + 80012a0: 701a strb r2, [r3, #0] +} + 80012a2: e7d5 b.n 8001250 + 80012a4: 50000400 .word 0x50000400 + 80012a8: 08002860 .word 0x08002860 + 80012ac: 20000134 .word 0x20000134 + 80012b0: 08002824 .word 0x08002824 + +080012b4 : + +void MAINSWITCH_SM_ManualOn(void) +{ + 80012b4: b510 push {r4, lr} + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + 80012b6: f7ff fd1b bl 8000cf0 + 80012ba: 2800 cmp r0, #0 + 80012bc: d000 beq.n 80012c0 + LEDS_RT_Off(); + printf("NEW_STATE: MAINSWITCH_OFF\n"); + smState = MAINSWITCH_OFF; + } + +} + 80012be: bd10 pop {r4, pc} + RELAIS_ResetPuls(); + 80012c0: f000 fa6c bl 800179c + BUZZER_Alarm_Stop(); + 80012c4: f7ff fd80 bl 8000dc8 + LEDS_GN_Off(); + 80012c8: f7ff fe38 bl 8000f3c + LEDS_RT_Off(); + 80012cc: f7ff fe6a bl 8000fa4 + printf("NEW_STATE: MAINSWITCH_OFF\n"); + 80012d0: 4803 ldr r0, [pc, #12] @ (80012e0 ) + 80012d2: f000 fba7 bl 8001a24 + smState = MAINSWITCH_OFF; + 80012d6: 4b03 ldr r3, [pc, #12] @ (80012e4 ) + 80012d8: 2200 movs r2, #0 + 80012da: 701a strb r2, [r3, #0] +} + 80012dc: e7ef b.n 80012be + 80012de: 46c0 nop @ (mov r8, r8) + 80012e0: 08002860 .word 0x08002860 + 80012e4: 20000134 .word 0x20000134 + +080012e8 : + +void MAINSWITCH_SM_Error(void) +{ + 80012e8: b510 push {r4, lr} + int faultInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + 80012ea: 2104 movs r1, #4 + 80012ec: 4821 ldr r0, [pc, #132] @ (8001374 ) + 80012ee: f7ff fa3b bl 8000768 + 80012f2: 2800 cmp r0, #0 + 80012f4: d109 bne.n 800130a + { + faultInput = 1; + 80012f6: 2401 movs r4, #1 + faultInput = 0; + } + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + 80012f8: f7ff fcfa bl 8000cf0 + 80012fc: 2801 cmp r0, #1 + 80012fe: d006 beq.n 800130e + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + 8001300: f7ff fcf6 bl 8000cf0 + 8001304: 2802 cmp r0, #2 + 8001306: d01e beq.n 8001346 + smState = MAINSWITCH_MANUAL_ON; + } + + + +} + 8001308: bd10 pop {r4, pc} + faultInput = 0; + 800130a: 2400 movs r4, #0 + 800130c: e7f4 b.n 80012f8 + if (faultInput == 0) + 800130e: 2c00 cmp r4, #0 + 8001310: d112 bne.n 8001338 + RELAIS_SetPuls(); + 8001312: f000 fa29 bl 8001768 + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + 8001316: 20c8 movs r0, #200 @ 0xc8 + 8001318: f7ff fd2e bl 8000d78 + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + 800131c: 21fa movs r1, #250 @ 0xfa + 800131e: 0089 lsls r1, r1, #2 + 8001320: 20c8 movs r0, #200 @ 0xc8 + 8001322: f7ff fdef bl 8000f04 + LEDS_RT_Off(); //Fehler löschen + 8001326: f7ff fe3d bl 8000fa4 + printf("NEW_STATE: MAINSWITCH_ON\n"); + 800132a: 4813 ldr r0, [pc, #76] @ (8001378 ) + 800132c: f000 fb7a bl 8001a24 + smState = MAINSWITCH_ON; + 8001330: 4b12 ldr r3, [pc, #72] @ (800137c ) + 8001332: 2201 movs r2, #1 + 8001334: 701a strb r2, [r3, #0] + 8001336: e7e3 b.n 8001300 + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + 8001338: 20fa movs r0, #250 @ 0xfa + 800133a: 0040 lsls r0, r0, #1 + 800133c: f7ff fd1c bl 8000d78 + BUTTON_SetModeOff(); + 8001340: f7ff fcdc bl 8000cfc + 8001344: e7dc b.n 8001300 + RELAIS_SetPuls(); + 8001346: f000 fa0f bl 8001768 + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + 800134a: 24fa movs r4, #250 @ 0xfa + 800134c: 00a4 lsls r4, r4, #2 + 800134e: 0021 movs r1, r4 + 8001350: 20c8 movs r0, #200 @ 0xc8 + 8001352: f7ff fd1f bl 8000d94 + LEDS_GN_On(); + 8001356: f7ff fdbd bl 8000ed4 + LEDS_RT_Off(); + 800135a: f7ff fe23 bl 8000fa4 + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME); + 800135e: 0021 movs r1, r4 + 8001360: 20c8 movs r0, #200 @ 0xc8 + 8001362: f7ff fe03 bl 8000f6c + printf("NEW_STATE: MAINSWITCH_MANUAL_ON\n"); + 8001366: 4806 ldr r0, [pc, #24] @ (8001380 ) + 8001368: f000 fb5c bl 8001a24 + smState = MAINSWITCH_MANUAL_ON; + 800136c: 4b03 ldr r3, [pc, #12] @ (800137c ) + 800136e: 2202 movs r2, #2 + 8001370: 701a strb r2, [r3, #0] +} + 8001372: e7c9 b.n 8001308 + 8001374: 50000400 .word 0x50000400 + 8001378: 08002808 .word 0x08002808 + 800137c: 20000134 .word 0x20000134 + 8001380: 08002840 .word 0x08002840 + +08001384 : + + + +void MODE_MAINSWITCH_Exec(void) +{ + 8001384: b510 push {r4, lr} + + + + switch (smState) + 8001386: 4b0b ldr r3, [pc, #44] @ (80013b4 ) + 8001388: 781b ldrb r3, [r3, #0] + 800138a: 2b02 cmp r3, #2 + 800138c: d00f beq.n 80013ae + 800138e: d806 bhi.n 800139e + 8001390: 2b00 cmp r3, #0 + 8001392: d009 beq.n 80013a8 + 8001394: 2b01 cmp r3, #1 + 8001396: d109 bne.n 80013ac + case MAINSWITCH_OFF: + MAINSWITCH_SM_Off(); + break; + + case MAINSWITCH_ON: + MAINSWITCH_SM_On(); + 8001398: f7ff ff4c bl 8001234 + break; + 800139c: e006 b.n 80013ac + switch (smState) + 800139e: 2b03 cmp r3, #3 + 80013a0: d104 bne.n 80013ac + case MAINSWITCH_MANUAL_ON: + MAINSWITCH_SM_ManualOn(); + break; + + case MAINSWITCH_ERROR: + MAINSWITCH_SM_Error(); + 80013a2: f7ff ffa1 bl 80012e8 + break; + + default: + break; + } +} + 80013a6: e001 b.n 80013ac + MAINSWITCH_SM_Off(); + 80013a8: f7ff feec bl 8001184 +} + 80013ac: bd10 pop {r4, pc} + MAINSWITCH_SM_ManualOn(); + 80013ae: f7ff ff81 bl 80012b4 + break; + 80013b2: e7fb b.n 80013ac + 80013b4: 20000134 .word 0x20000134 + +080013b8 : + +static SECONDARYPROTECTION_state_t smState; + + +void SECONDARYPROTECTION_SM_Off(void) +{ + 80013b8: b510 push {r4, lr} + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + 80013ba: 2104 movs r1, #4 + 80013bc: 482c ldr r0, [pc, #176] @ (8001470 ) + 80013be: f7ff f9d3 bl 8000768 + 80013c2: 2800 cmp r0, #0 + 80013c4: d110 bne.n 80013e8 + { + faultInput = 1; + 80013c6: 2401 movs r4, #1 + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + 80013c8: 20a0 movs r0, #160 @ 0xa0 + 80013ca: 2101 movs r1, #1 + 80013cc: 05c0 lsls r0, r0, #23 + 80013ce: f7ff f9cb bl 8000768 + 80013d2: 2801 cmp r0, #1 + 80013d4: d00a beq.n 80013ec + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + 80013d6: f7ff fc8b bl 8000cf0 + 80013da: 2801 cmp r0, #1 + 80013dc: d00c beq.n 80013f8 + } + + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + 80013de: f7ff fc87 bl 8000cf0 + 80013e2: 2802 cmp r0, #2 + 80013e4: d02e beq.n 8001444 + smState = SECONDARYPROTECTION_MANUAL_ON; + } + + + +} + 80013e6: bd10 pop {r4, pc} + faultInput = 0; + 80013e8: 2400 movs r4, #0 + 80013ea: e7ed b.n 80013c8 + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + 80013ec: 309f adds r0, #159 @ 0x9f + 80013ee: 2102 movs r1, #2 + 80013f0: 05c0 lsls r0, r0, #23 + 80013f2: f7ff f9b9 bl 8000768 + 80013f6: e7ee b.n 80013d6 + if (faultInput == 0) + 80013f8: 2c00 cmp r4, #0 + 80013fa: d110 bne.n 800141e + RELAIS_SetPuls(); + 80013fc: f000 f9b4 bl 8001768 + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + 8001400: 20c8 movs r0, #200 @ 0xc8 + 8001402: f7ff fcb9 bl 8000d78 + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + 8001406: 21fa movs r1, #250 @ 0xfa + 8001408: 0089 lsls r1, r1, #2 + 800140a: 20c8 movs r0, #200 @ 0xc8 + 800140c: f7ff fd7a bl 8000f04 + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + 8001410: 4818 ldr r0, [pc, #96] @ (8001474 ) + 8001412: f000 fb07 bl 8001a24 + smState = SECONDARYPROTECTION_ON; + 8001416: 4b18 ldr r3, [pc, #96] @ (8001478 ) + 8001418: 2201 movs r2, #1 + 800141a: 701a strb r2, [r3, #0] + 800141c: e7df b.n 80013de + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + 800141e: 24fa movs r4, #250 @ 0xfa + 8001420: 0064 lsls r4, r4, #1 + 8001422: 0020 movs r0, r4 + 8001424: f7ff fca8 bl 8000d78 + BUTTON_SetModeOff(); + 8001428: f7ff fc68 bl 8000cfc + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + 800142c: 21fa movs r1, #250 @ 0xfa + 800142e: 0089 lsls r1, r1, #2 + 8001430: 0020 movs r0, r4 + 8001432: f7ff fd9b bl 8000f6c + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + 8001436: 4811 ldr r0, [pc, #68] @ (800147c ) + 8001438: f000 faf4 bl 8001a24 + smState =SECONDARYPROTECTION_ERROR; + 800143c: 4b0e ldr r3, [pc, #56] @ (8001478 ) + 800143e: 2203 movs r2, #3 + 8001440: 701a strb r2, [r3, #0] + 8001442: e7cc b.n 80013de + RELAIS_SetPuls(); + 8001444: f000 f990 bl 8001768 + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + 8001448: 24fa movs r4, #250 @ 0xfa + 800144a: 00a4 lsls r4, r4, #2 + 800144c: 0021 movs r1, r4 + 800144e: 20c8 movs r0, #200 @ 0xc8 + 8001450: f7ff fca0 bl 8000d94 + LEDS_GN_On(); + 8001454: f7ff fd3e bl 8000ed4 + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_GN_OFF_TIME); + 8001458: 0021 movs r1, r4 + 800145a: 20c8 movs r0, #200 @ 0xc8 + 800145c: f7ff fd86 bl 8000f6c + printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + 8001460: 4807 ldr r0, [pc, #28] @ (8001480 ) + 8001462: f000 fadf bl 8001a24 + smState = SECONDARYPROTECTION_MANUAL_ON; + 8001466: 4b04 ldr r3, [pc, #16] @ (8001478 ) + 8001468: 2202 movs r2, #2 + 800146a: 701a strb r2, [r3, #0] +} + 800146c: e7bb b.n 80013e6 + 800146e: 46c0 nop @ (mov r8, r8) + 8001470: 50000400 .word 0x50000400 + 8001474: 0800287c .word 0x0800287c + 8001478: 20000140 .word 0x20000140 + 800147c: 080028a0 .word 0x080028a0 + 8001480: 080028c8 .word 0x080028c8 + +08001484 : + +void SECONDARYPROTECTION_SM_On(void) +{ + 8001484: b570 push {r4, r5, r6, lr} + int faultInput = 0; + int lvpAndOvpInput = 0; + static int lvpAndOvpInputTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + 8001486: 2104 movs r1, #4 + 8001488: 483f ldr r0, [pc, #252] @ (8001588 ) + 800148a: f7ff f96d bl 8000768 + 800148e: 2800 cmp r0, #0 + 8001490: d114 bne.n 80014bc + { + faultInput = 1; + 8001492: 2401 movs r4, #1 + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + 8001494: 20a0 movs r0, #160 @ 0xa0 + 8001496: 2101 movs r1, #1 + 8001498: 05c0 lsls r0, r0, #23 + 800149a: f7ff f965 bl 8000768 + 800149e: 2801 cmp r0, #1 + 80014a0: d00e beq.n 80014c0 + oldtime = HAL_GetTick(); + } + } + else + { + lvpAndOvpInputTimeCounter = 0; + 80014a2: 4b3a ldr r3, [pc, #232] @ (800158c ) + 80014a4: 2200 movs r2, #0 + 80014a6: 601a str r2, [r3, #0] + lvpAndOvpInput = 0; + 80014a8: 2500 movs r5, #0 + } + + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + 80014aa: f7ff fc21 bl 8000cf0 + 80014ae: 2800 cmp r0, #0 + 80014b0: d027 beq.n 8001502 + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + } + + //Prüfe auf Fehlermode + if (faultInput == 1) + 80014b2: 2c01 cmp r4, #1 + 80014b4: d035 beq.n 8001522 + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + } + + if (lvpAndOvpInput == 1) + 80014b6: 2d01 cmp r5, #1 + 80014b8: d04d beq.n 8001556 + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + } + + +} + 80014ba: bd70 pop {r4, r5, r6, pc} + faultInput = 0; + 80014bc: 2400 movs r4, #0 + 80014be: e7e9 b.n 8001494 + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + 80014c0: 309f adds r0, #159 @ 0x9f + 80014c2: 2102 movs r1, #2 + 80014c4: 05c0 lsls r0, r0, #23 + 80014c6: f7ff f94f bl 8000768 + 80014ca: 2801 cmp r0, #1 + 80014cc: d1e9 bne.n 80014a2 + if (HAL_GetTick() != oldtime) + 80014ce: f7fe ff9b bl 8000408 + 80014d2: 4b2f ldr r3, [pc, #188] @ (8001590 ) + 80014d4: 681b ldr r3, [r3, #0] + 80014d6: 4298 cmp r0, r3 + 80014d8: d011 beq.n 80014fe + lvpAndOvpInputTimeCounter++; + 80014da: 4a2c ldr r2, [pc, #176] @ (800158c ) + 80014dc: 6813 ldr r3, [r2, #0] + 80014de: 3301 adds r3, #1 + 80014e0: 6013 str r3, [r2, #0] + if (lvpAndOvpInputTimeCounter > 30000) + 80014e2: 4a2c ldr r2, [pc, #176] @ (8001594 ) + 80014e4: 4293 cmp r3, r2 + 80014e6: dd08 ble.n 80014fa + lvpAndOvpInputTimeCounter=0; + 80014e8: 4b28 ldr r3, [pc, #160] @ (800158c ) + 80014ea: 2200 movs r2, #0 + 80014ec: 601a str r2, [r3, #0] + lvpAndOvpInput = 1; + 80014ee: 2501 movs r5, #1 + oldtime = HAL_GetTick(); + 80014f0: f7fe ff8a bl 8000408 + 80014f4: 4b26 ldr r3, [pc, #152] @ (8001590 ) + 80014f6: 6018 str r0, [r3, #0] + 80014f8: e7d7 b.n 80014aa + int lvpAndOvpInput = 0; + 80014fa: 2500 movs r5, #0 + 80014fc: e7f8 b.n 80014f0 + 80014fe: 2500 movs r5, #0 + 8001500: e7d3 b.n 80014aa + RELAIS_ResetPuls(); + 8001502: f000 f94b bl 800179c + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + 8001506: 20c8 movs r0, #200 @ 0xc8 + 8001508: f7ff fc36 bl 8000d78 + LEDS_GN_Off(); + 800150c: f7ff fd16 bl 8000f3c + LEDS_RT_Off(); + 8001510: f7ff fd48 bl 8000fa4 + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + 8001514: 4820 ldr r0, [pc, #128] @ (8001598 ) + 8001516: f000 fa85 bl 8001a24 + smState = SECONDARYPROTECTION_OFF; + 800151a: 4b20 ldr r3, [pc, #128] @ (800159c ) + 800151c: 2200 movs r2, #0 + 800151e: 701a strb r2, [r3, #0] + 8001520: e7c7 b.n 80014b2 + RELAIS_ResetPuls(); + 8001522: f000 f93b bl 800179c + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + 8001526: 34f4 adds r4, #244 @ 0xf4 + 8001528: 34ff adds r4, #255 @ 0xff + 800152a: 0020 movs r0, r4 + 800152c: f7ff fc24 bl 8000d78 + LEDS_GN_Off(); + 8001530: f7ff fd04 bl 8000f3c + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME); //Fehlercode fault + 8001534: 21fa movs r1, #250 @ 0xfa + 8001536: 0089 lsls r1, r1, #2 + 8001538: 0020 movs r0, r4 + 800153a: f7ff fd17 bl 8000f6c + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + 800153e: f7ff fbdd bl 8000cfc + printf("FAULT INPUT EVENT DETECTED!\n"); + 8001542: 4817 ldr r0, [pc, #92] @ (80015a0 ) + 8001544: f000 fa6e bl 8001a24 + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + 8001548: 4816 ldr r0, [pc, #88] @ (80015a4 ) + 800154a: f000 fa6b bl 8001a24 + smState = SECONDARYPROTECTION_ERROR; + 800154e: 4b13 ldr r3, [pc, #76] @ (800159c ) + 8001550: 2203 movs r2, #3 + 8001552: 701a strb r2, [r3, #0] + 8001554: e7af b.n 80014b6 + RELAIS_ResetPuls(); + 8001556: f000 f921 bl 800179c + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + 800155a: 20fa movs r0, #250 @ 0xfa + 800155c: 0040 lsls r0, r0, #1 + 800155e: f7ff fc0b bl 8000d78 + LEDS_GN_Off(); + 8001562: f7ff fceb bl 8000f3c + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT, LED_RT_OFF_TIME); //Fehlercode fault + 8001566: 20fa movs r0, #250 @ 0xfa + 8001568: 0080 lsls r0, r0, #2 + 800156a: 0001 movs r1, r0 + 800156c: f7ff fcfe bl 8000f6c + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + 8001570: f7ff fbc4 bl 8000cfc + printf("BMS SECONDARY PROTECTION FAULT EVENT DETECTED (LVP & OVP )!\n"); + 8001574: 480c ldr r0, [pc, #48] @ (80015a8 ) + 8001576: f000 fa55 bl 8001a24 + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + 800157a: 480a ldr r0, [pc, #40] @ (80015a4 ) + 800157c: f000 fa52 bl 8001a24 + smState = SECONDARYPROTECTION_ERROR; + 8001580: 4b06 ldr r3, [pc, #24] @ (800159c ) + 8001582: 2203 movs r2, #3 + 8001584: 701a strb r2, [r3, #0] +} + 8001586: e798 b.n 80014ba + 8001588: 50000400 .word 0x50000400 + 800158c: 20000138 .word 0x20000138 + 8001590: 2000013c .word 0x2000013c + 8001594: 00007530 .word 0x00007530 + 8001598: 080028f4 .word 0x080028f4 + 800159c: 20000140 .word 0x20000140 + 80015a0: 08002918 .word 0x08002918 + 80015a4: 080028a0 .word 0x080028a0 + 80015a8: 08002934 .word 0x08002934 + +080015ac : + +void SECONDARYPROTECTION_SM_ManualOn(void) +{ + 80015ac: b510 push {r4, lr} + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + 80015ae: f7ff fb9f bl 8000cf0 + 80015b2: 2800 cmp r0, #0 + 80015b4: d000 beq.n 80015b8 + LEDS_RT_Off(); + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + } + +} + 80015b6: bd10 pop {r4, pc} + RELAIS_ResetPuls(); + 80015b8: f000 f8f0 bl 800179c + BUZZER_Alarm_Stop(); + 80015bc: f7ff fc04 bl 8000dc8 + LEDS_GN_Off(); + 80015c0: f7ff fcbc bl 8000f3c + LEDS_RT_Off(); + 80015c4: f7ff fcee bl 8000fa4 + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + 80015c8: 4803 ldr r0, [pc, #12] @ (80015d8 ) + 80015ca: f000 fa2b bl 8001a24 + smState = SECONDARYPROTECTION_OFF; + 80015ce: 4b03 ldr r3, [pc, #12] @ (80015dc ) + 80015d0: 2200 movs r2, #0 + 80015d2: 701a strb r2, [r3, #0] +} + 80015d4: e7ef b.n 80015b6 + 80015d6: 46c0 nop @ (mov r8, r8) + 80015d8: 080028f4 .word 0x080028f4 + 80015dc: 20000140 .word 0x20000140 + +080015e0 : + +void SECONDARYPROTECTION_SM_Error(void) +{ + 80015e0: b510 push {r4, lr} + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + 80015e2: 2104 movs r1, #4 + 80015e4: 4821 ldr r0, [pc, #132] @ (800166c ) + 80015e6: f7ff f8bf bl 8000768 + 80015ea: 2800 cmp r0, #0 + 80015ec: d109 bne.n 8001602 + { + faultInput = 1; + 80015ee: 2401 movs r4, #1 + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + 80015f0: f7ff fb7e bl 8000cf0 + 80015f4: 2801 cmp r0, #1 + 80015f6: d006 beq.n 8001606 + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + 80015f8: f7ff fb7a bl 8000cf0 + 80015fc: 2802 cmp r0, #2 + 80015fe: d01e beq.n 800163e + smState = SECONDARYPROTECTION_MANUAL_ON; + } + + + +} + 8001600: bd10 pop {r4, pc} + faultInput = 0; + 8001602: 2400 movs r4, #0 + 8001604: e7f4 b.n 80015f0 + if (faultInput == 0) + 8001606: 2c00 cmp r4, #0 + 8001608: d112 bne.n 8001630 + RELAIS_SetPuls(); + 800160a: f000 f8ad bl 8001768 + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + 800160e: 20c8 movs r0, #200 @ 0xc8 + 8001610: f7ff fbb2 bl 8000d78 + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + 8001614: 21fa movs r1, #250 @ 0xfa + 8001616: 0089 lsls r1, r1, #2 + 8001618: 20c8 movs r0, #200 @ 0xc8 + 800161a: f7ff fc73 bl 8000f04 + LEDS_RT_Off(); //Fehler löschen + 800161e: f7ff fcc1 bl 8000fa4 + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + 8001622: 4813 ldr r0, [pc, #76] @ (8001670 ) + 8001624: f000 f9fe bl 8001a24 + smState = SECONDARYPROTECTION_ON; + 8001628: 4b12 ldr r3, [pc, #72] @ (8001674 ) + 800162a: 2201 movs r2, #1 + 800162c: 701a strb r2, [r3, #0] + 800162e: e7e3 b.n 80015f8 + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + 8001630: 20fa movs r0, #250 @ 0xfa + 8001632: 0040 lsls r0, r0, #1 + 8001634: f7ff fba0 bl 8000d78 + BUTTON_SetModeOff(); + 8001638: f7ff fb60 bl 8000cfc + 800163c: e7dc b.n 80015f8 + RELAIS_SetPuls(); + 800163e: f000 f893 bl 8001768 + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + 8001642: 24fa movs r4, #250 @ 0xfa + 8001644: 00a4 lsls r4, r4, #2 + 8001646: 0021 movs r1, r4 + 8001648: 20c8 movs r0, #200 @ 0xc8 + 800164a: f7ff fba3 bl 8000d94 + LEDS_GN_On(); + 800164e: f7ff fc41 bl 8000ed4 + LEDS_RT_Off(); + 8001652: f7ff fca7 bl 8000fa4 + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME); + 8001656: 0021 movs r1, r4 + 8001658: 20c8 movs r0, #200 @ 0xc8 + 800165a: f7ff fc87 bl 8000f6c + printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + 800165e: 4806 ldr r0, [pc, #24] @ (8001678 ) + 8001660: f000 f9e0 bl 8001a24 + smState = SECONDARYPROTECTION_MANUAL_ON; + 8001664: 4b03 ldr r3, [pc, #12] @ (8001674 ) + 8001666: 2202 movs r2, #2 + 8001668: 701a strb r2, [r3, #0] +} + 800166a: e7c9 b.n 8001600 + 800166c: 50000400 .word 0x50000400 + 8001670: 0800287c .word 0x0800287c + 8001674: 20000140 .word 0x20000140 + 8001678: 080028c8 .word 0x080028c8 + +0800167c : + + + +void MODE_SECONDARYPROTECTION_Exec(void) +{ + 800167c: b510 push {r4, lr} + + + + switch (smState) + 800167e: 4b0b ldr r3, [pc, #44] @ (80016ac ) + 8001680: 781b ldrb r3, [r3, #0] + 8001682: 2b02 cmp r3, #2 + 8001684: d00f beq.n 80016a6 + 8001686: d806 bhi.n 8001696 + 8001688: 2b00 cmp r3, #0 + 800168a: d009 beq.n 80016a0 + 800168c: 2b01 cmp r3, #1 + 800168e: d109 bne.n 80016a4 + case SECONDARYPROTECTION_OFF: + SECONDARYPROTECTION_SM_Off(); + break; + + case SECONDARYPROTECTION_ON: + SECONDARYPROTECTION_SM_On(); + 8001690: f7ff fef8 bl 8001484 + break; + 8001694: e006 b.n 80016a4 + switch (smState) + 8001696: 2b03 cmp r3, #3 + 8001698: d104 bne.n 80016a4 + case SECONDARYPROTECTION_MANUAL_ON: + SECONDARYPROTECTION_SM_ManualOn(); + break; + + case SECONDARYPROTECTION_ERROR: + SECONDARYPROTECTION_SM_Error(); + 800169a: f7ff ffa1 bl 80015e0 + break; + + default: + break; + } +} + 800169e: e001 b.n 80016a4 + SECONDARYPROTECTION_SM_Off(); + 80016a0: f7ff fe8a bl 80013b8 +} + 80016a4: bd10 pop {r4, pc} + SECONDARYPROTECTION_SM_ManualOn(); + 80016a6: f7ff ff81 bl 80015ac + break; + 80016aa: e7fb b.n 80016a4 + 80016ac: 20000140 .word 0x20000140 + +080016b0 : + + +MODESWITCH_mode_t mode; + +MODESWITCH_mode_t MODESWITCH_ReadMode(void) +{ + 80016b0: b5f8 push {r3, r4, r5, r6, r7, lr} + + + int m0 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B0_GPIO_Port, GPIO_INPUT_MODE_B0_Pin) << 0); + 80016b2: 4e14 ldr r6, [pc, #80] @ (8001704 ) + 80016b4: 2140 movs r1, #64 @ 0x40 + 80016b6: 0030 movs r0, r6 + 80016b8: f7ff f856 bl 8000768 + 80016bc: 0007 movs r7, r0 + int m1 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B1_GPIO_Port, GPIO_INPUT_MODE_B1_Pin) << 1); + 80016be: 2180 movs r1, #128 @ 0x80 + 80016c0: 0030 movs r0, r6 + 80016c2: f7ff f851 bl 8000768 + 80016c6: 0004 movs r4, r0 + int m2 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B2_GPIO_Port, GPIO_INPUT_MODE_B2_Pin) << 2); + 80016c8: 2180 movs r1, #128 @ 0x80 + 80016ca: 0049 lsls r1, r1, #1 + 80016cc: 0030 movs r0, r6 + 80016ce: f7ff f84b bl 8000768 + 80016d2: 0005 movs r5, r0 + int m3 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B3_GPIO_Port, GPIO_INPUT_MODE_B3_Pin) << 3); + 80016d4: 2180 movs r1, #128 @ 0x80 + 80016d6: 0089 lsls r1, r1, #2 + 80016d8: 0030 movs r0, r6 + 80016da: f7ff f845 bl 8000768 + + + + mode = m0 | m1 | m2 | m3; + 80016de: 0064 lsls r4, r4, #1 + 80016e0: 433c orrs r4, r7 + 80016e2: b264 sxtb r4, r4 + 80016e4: 00ad lsls r5, r5, #2 + 80016e6: 432c orrs r4, r5 + 80016e8: b264 sxtb r4, r4 + 80016ea: 00c0 lsls r0, r0, #3 + 80016ec: 4320 orrs r0, r4 + 80016ee: b2c0 uxtb r0, r0 + 80016f0: 4c05 ldr r4, [pc, #20] @ (8001708 ) + 80016f2: 7020 strb r0, [r4, #0] + mode = 0x0f &~mode; + 80016f4: 210f movs r1, #15 + 80016f6: 4381 bics r1, r0 + 80016f8: 7021 strb r1, [r4, #0] + printf("mode=%i\n",mode); + 80016fa: 4804 ldr r0, [pc, #16] @ (800170c ) + 80016fc: f000 f92c bl 8001958 + + return mode; + 8001700: 7820 ldrb r0, [r4, #0] +} + 8001702: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8001704: 50000400 .word 0x50000400 + 8001708: 20000141 .word 0x20000141 + 800170c: 08002970 .word 0x08002970 + +08001710 : + + +MODESWITCH_mode_t MODESWITCH_GetMode(void) +{ + return mode; + 8001710: 4b01 ldr r3, [pc, #4] @ (8001718 ) + 8001712: 7818 ldrb r0, [r3, #0] +} + 8001714: 4770 bx lr + 8001716: 46c0 nop @ (mov r8, r8) + 8001718: 20000141 .word 0x20000141 + +0800171c : +unsigned int onTimeCounterRESET; //Reset Coil +unsigned int relaisState; + + +void RELAIS_Exec(void) +{ + 800171c: b510 push {r4, lr} + + if (onTimeCounterSET > 0) + 800171e: 4b0f ldr r3, [pc, #60] @ (800175c ) + 8001720: 681b ldr r3, [r3, #0] + 8001722: 2b00 cmp r3, #0 + 8001724: d004 beq.n 8001730 + { + onTimeCounterSET--; + 8001726: 3b01 subs r3, #1 + 8001728: 4a0c ldr r2, [pc, #48] @ (800175c ) + 800172a: 6013 str r3, [r2, #0] + if (onTimeCounterSET == 0) + 800172c: 2b00 cmp r3, #0 + 800172e: d009 beq.n 8001744 + } + } + + + +if (onTimeCounterRESET > 0) + 8001730: 4b0b ldr r3, [pc, #44] @ (8001760 ) + 8001732: 681b ldr r3, [r3, #0] + 8001734: 2b00 cmp r3, #0 + 8001736: d004 beq.n 8001742 + { + onTimeCounterRESET--; + 8001738: 3b01 subs r3, #1 + 800173a: 4a09 ldr r2, [pc, #36] @ (8001760 ) + 800173c: 6013 str r3, [r2, #0] + if (onTimeCounterRESET == 0) + 800173e: 2b00 cmp r3, #0 + 8001740: d006 beq.n 8001750 + { + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + } + } + +} + 8001742: bd10 pop {r4, pc} + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + 8001744: 2200 movs r2, #0 + 8001746: 2108 movs r1, #8 + 8001748: 4806 ldr r0, [pc, #24] @ (8001764 ) + 800174a: f7ff f814 bl 8000776 + 800174e: e7ef b.n 8001730 + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + 8001750: 2200 movs r2, #0 + 8001752: 2110 movs r1, #16 + 8001754: 4803 ldr r0, [pc, #12] @ (8001764 ) + 8001756: f7ff f80e bl 8000776 +} + 800175a: e7f2 b.n 8001742 + 800175c: 2000014c .word 0x2000014c + 8001760: 20000148 .word 0x20000148 + 8001764: 50000400 .word 0x50000400 + +08001768 : + +void RELAIS_SetPuls(void) +{ + 8001768: b510 push {r4, lr} + + //Sicherstellen das nicht noch die Reset Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + 800176a: 4c09 ldr r4, [pc, #36] @ (8001790 ) + 800176c: 2200 movs r2, #0 + 800176e: 2110 movs r1, #16 + 8001770: 0020 movs r0, r4 + 8001772: f7ff f800 bl 8000776 + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_SET); + 8001776: 2201 movs r2, #1 + 8001778: 2108 movs r1, #8 + 800177a: 0020 movs r0, r4 + 800177c: f7fe fffb bl 8000776 + onTimeCounterSET = PULS_TIME; + 8001780: 4b04 ldr r3, [pc, #16] @ (8001794 ) + 8001782: 2232 movs r2, #50 @ 0x32 + 8001784: 601a str r2, [r3, #0] + relaisState = 1; + 8001786: 4b04 ldr r3, [pc, #16] @ (8001798 ) + 8001788: 3a31 subs r2, #49 @ 0x31 + 800178a: 601a str r2, [r3, #0] + +} + 800178c: bd10 pop {r4, pc} + 800178e: 46c0 nop @ (mov r8, r8) + 8001790: 50000400 .word 0x50000400 + 8001794: 2000014c .word 0x2000014c + 8001798: 20000144 .word 0x20000144 + +0800179c : + +void RELAIS_ResetPuls(void) +{ + 800179c: b510 push {r4, lr} + + //Sicherstellen das nicht noch die Set Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + 800179e: 4c09 ldr r4, [pc, #36] @ (80017c4 ) + 80017a0: 2200 movs r2, #0 + 80017a2: 2108 movs r1, #8 + 80017a4: 0020 movs r0, r4 + 80017a6: f7fe ffe6 bl 8000776 + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_SET); + 80017aa: 2201 movs r2, #1 + 80017ac: 2110 movs r1, #16 + 80017ae: 0020 movs r0, r4 + 80017b0: f7fe ffe1 bl 8000776 + onTimeCounterRESET = PULS_TIME; + 80017b4: 4b04 ldr r3, [pc, #16] @ (80017c8 ) + 80017b6: 2232 movs r2, #50 @ 0x32 + 80017b8: 601a str r2, [r3, #0] + relaisState = 0; + 80017ba: 4b04 ldr r3, [pc, #16] @ (80017cc ) + 80017bc: 2200 movs r2, #0 + 80017be: 601a str r2, [r3, #0] + +} + 80017c0: bd10 pop {r4, pc} + 80017c2: 46c0 nop @ (mov r8, r8) + 80017c4: 50000400 .word 0x50000400 + 80017c8: 20000148 .word 0x20000148 + 80017cc: 20000144 .word 0x20000144 + +080017d0 : + 80017d0: 2300 movs r3, #0 + 80017d2: b510 push {r4, lr} + 80017d4: 0004 movs r4, r0 + 80017d6: 6003 str r3, [r0, #0] + 80017d8: 6043 str r3, [r0, #4] + 80017da: 6083 str r3, [r0, #8] + 80017dc: 8181 strh r1, [r0, #12] + 80017de: 6643 str r3, [r0, #100] @ 0x64 + 80017e0: 81c2 strh r2, [r0, #14] + 80017e2: 6103 str r3, [r0, #16] + 80017e4: 6143 str r3, [r0, #20] + 80017e6: 6183 str r3, [r0, #24] + 80017e8: 0019 movs r1, r3 + 80017ea: 2208 movs r2, #8 + 80017ec: 305c adds r0, #92 @ 0x5c + 80017ee: f000 fa0f bl 8001c10 + 80017f2: 4b0b ldr r3, [pc, #44] @ (8001820 ) + 80017f4: 6224 str r4, [r4, #32] + 80017f6: 6263 str r3, [r4, #36] @ 0x24 + 80017f8: 4b0a ldr r3, [pc, #40] @ (8001824 ) + 80017fa: 62a3 str r3, [r4, #40] @ 0x28 + 80017fc: 4b0a ldr r3, [pc, #40] @ (8001828 ) + 80017fe: 62e3 str r3, [r4, #44] @ 0x2c + 8001800: 4b0a ldr r3, [pc, #40] @ (800182c ) + 8001802: 6323 str r3, [r4, #48] @ 0x30 + 8001804: 4b0a ldr r3, [pc, #40] @ (8001830 ) + 8001806: 429c cmp r4, r3 + 8001808: d005 beq.n 8001816 + 800180a: 4b0a ldr r3, [pc, #40] @ (8001834 ) + 800180c: 429c cmp r4, r3 + 800180e: d002 beq.n 8001816 + 8001810: 4b09 ldr r3, [pc, #36] @ (8001838 ) + 8001812: 429c cmp r4, r3 + 8001814: d103 bne.n 800181e + 8001816: 0020 movs r0, r4 + 8001818: 3058 adds r0, #88 @ 0x58 + 800181a: f000 fa79 bl 8001d10 <__retarget_lock_init_recursive> + 800181e: bd10 pop {r4, pc} + 8001820: 08001a39 .word 0x08001a39 + 8001824: 08001a61 .word 0x08001a61 + 8001828: 08001a99 .word 0x08001a99 + 800182c: 08001ac5 .word 0x08001ac5 + 8001830: 20000150 .word 0x20000150 + 8001834: 200001b8 .word 0x200001b8 + 8001838: 20000220 .word 0x20000220 + +0800183c : + 800183c: b510 push {r4, lr} + 800183e: 4a03 ldr r2, [pc, #12] @ (800184c ) + 8001840: 4903 ldr r1, [pc, #12] @ (8001850 ) + 8001842: 4804 ldr r0, [pc, #16] @ (8001854 ) + 8001844: f000 f86c bl 8001920 <_fwalk_sglue> + 8001848: bd10 pop {r4, pc} + 800184a: 46c0 nop @ (mov r8, r8) + 800184c: 2000000c .word 0x2000000c + 8001850: 0800259d .word 0x0800259d + 8001854: 2000001c .word 0x2000001c + +08001858 : + 8001858: 6841 ldr r1, [r0, #4] + 800185a: 4b0b ldr r3, [pc, #44] @ (8001888 ) + 800185c: b510 push {r4, lr} + 800185e: 0004 movs r4, r0 + 8001860: 4299 cmp r1, r3 + 8001862: d001 beq.n 8001868 + 8001864: f000 fe9a bl 800259c <_fflush_r> + 8001868: 68a1 ldr r1, [r4, #8] + 800186a: 4b08 ldr r3, [pc, #32] @ (800188c ) + 800186c: 4299 cmp r1, r3 + 800186e: d002 beq.n 8001876 + 8001870: 0020 movs r0, r4 + 8001872: f000 fe93 bl 800259c <_fflush_r> + 8001876: 68e1 ldr r1, [r4, #12] + 8001878: 4b05 ldr r3, [pc, #20] @ (8001890 ) + 800187a: 4299 cmp r1, r3 + 800187c: d002 beq.n 8001884 + 800187e: 0020 movs r0, r4 + 8001880: f000 fe8c bl 800259c <_fflush_r> + 8001884: bd10 pop {r4, pc} + 8001886: 46c0 nop @ (mov r8, r8) + 8001888: 20000150 .word 0x20000150 + 800188c: 200001b8 .word 0x200001b8 + 8001890: 20000220 .word 0x20000220 + +08001894 : + 8001894: b510 push {r4, lr} + 8001896: 4b09 ldr r3, [pc, #36] @ (80018bc ) + 8001898: 4a09 ldr r2, [pc, #36] @ (80018c0 ) + 800189a: 2104 movs r1, #4 + 800189c: 601a str r2, [r3, #0] + 800189e: 4809 ldr r0, [pc, #36] @ (80018c4 ) + 80018a0: 2200 movs r2, #0 + 80018a2: f7ff ff95 bl 80017d0 + 80018a6: 2201 movs r2, #1 + 80018a8: 2109 movs r1, #9 + 80018aa: 4807 ldr r0, [pc, #28] @ (80018c8 ) + 80018ac: f7ff ff90 bl 80017d0 + 80018b0: 2202 movs r2, #2 + 80018b2: 2112 movs r1, #18 + 80018b4: 4805 ldr r0, [pc, #20] @ (80018cc ) + 80018b6: f7ff ff8b bl 80017d0 + 80018ba: bd10 pop {r4, pc} + 80018bc: 20000288 .word 0x20000288 + 80018c0: 0800183d .word 0x0800183d + 80018c4: 20000150 .word 0x20000150 + 80018c8: 200001b8 .word 0x200001b8 + 80018cc: 20000220 .word 0x20000220 + +080018d0 <__sfp_lock_acquire>: + 80018d0: b510 push {r4, lr} + 80018d2: 4802 ldr r0, [pc, #8] @ (80018dc <__sfp_lock_acquire+0xc>) + 80018d4: f000 fa1d bl 8001d12 <__retarget_lock_acquire_recursive> + 80018d8: bd10 pop {r4, pc} + 80018da: 46c0 nop @ (mov r8, r8) + 80018dc: 20000291 .word 0x20000291 + +080018e0 <__sfp_lock_release>: + 80018e0: b510 push {r4, lr} + 80018e2: 4802 ldr r0, [pc, #8] @ (80018ec <__sfp_lock_release+0xc>) + 80018e4: f000 fa16 bl 8001d14 <__retarget_lock_release_recursive> + 80018e8: bd10 pop {r4, pc} + 80018ea: 46c0 nop @ (mov r8, r8) + 80018ec: 20000291 .word 0x20000291 + +080018f0 <__sinit>: + 80018f0: b510 push {r4, lr} + 80018f2: 0004 movs r4, r0 + 80018f4: f7ff ffec bl 80018d0 <__sfp_lock_acquire> + 80018f8: 6a23 ldr r3, [r4, #32] + 80018fa: 2b00 cmp r3, #0 + 80018fc: d002 beq.n 8001904 <__sinit+0x14> + 80018fe: f7ff ffef bl 80018e0 <__sfp_lock_release> + 8001902: bd10 pop {r4, pc} + 8001904: 4b04 ldr r3, [pc, #16] @ (8001918 <__sinit+0x28>) + 8001906: 6223 str r3, [r4, #32] + 8001908: 4b04 ldr r3, [pc, #16] @ (800191c <__sinit+0x2c>) + 800190a: 681b ldr r3, [r3, #0] + 800190c: 2b00 cmp r3, #0 + 800190e: d1f6 bne.n 80018fe <__sinit+0xe> + 8001910: f7ff ffc0 bl 8001894 + 8001914: e7f3 b.n 80018fe <__sinit+0xe> + 8001916: 46c0 nop @ (mov r8, r8) + 8001918: 08001859 .word 0x08001859 + 800191c: 20000288 .word 0x20000288 + +08001920 <_fwalk_sglue>: + 8001920: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8001922: 0014 movs r4, r2 + 8001924: 2600 movs r6, #0 + 8001926: 9000 str r0, [sp, #0] + 8001928: 9101 str r1, [sp, #4] + 800192a: 68a5 ldr r5, [r4, #8] + 800192c: 6867 ldr r7, [r4, #4] + 800192e: 3f01 subs r7, #1 + 8001930: d504 bpl.n 800193c <_fwalk_sglue+0x1c> + 8001932: 6824 ldr r4, [r4, #0] + 8001934: 2c00 cmp r4, #0 + 8001936: d1f8 bne.n 800192a <_fwalk_sglue+0xa> + 8001938: 0030 movs r0, r6 + 800193a: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + 800193c: 89ab ldrh r3, [r5, #12] + 800193e: 2b01 cmp r3, #1 + 8001940: d908 bls.n 8001954 <_fwalk_sglue+0x34> + 8001942: 220e movs r2, #14 + 8001944: 5eab ldrsh r3, [r5, r2] + 8001946: 3301 adds r3, #1 + 8001948: d004 beq.n 8001954 <_fwalk_sglue+0x34> + 800194a: 0029 movs r1, r5 + 800194c: 9800 ldr r0, [sp, #0] + 800194e: 9b01 ldr r3, [sp, #4] + 8001950: 4798 blx r3 + 8001952: 4306 orrs r6, r0 + 8001954: 3568 adds r5, #104 @ 0x68 + 8001956: e7ea b.n 800192e <_fwalk_sglue+0xe> + +08001958 : + 8001958: b40f push {r0, r1, r2, r3} + 800195a: b507 push {r0, r1, r2, lr} + 800195c: 4905 ldr r1, [pc, #20] @ (8001974 ) + 800195e: ab04 add r3, sp, #16 + 8001960: 6808 ldr r0, [r1, #0] + 8001962: cb04 ldmia r3!, {r2} + 8001964: 6881 ldr r1, [r0, #8] + 8001966: 9301 str r3, [sp, #4] + 8001968: f000 fafa bl 8001f60 <_vfiprintf_r> + 800196c: b003 add sp, #12 + 800196e: bc08 pop {r3} + 8001970: b004 add sp, #16 + 8001972: 4718 bx r3 + 8001974: 20000018 .word 0x20000018 + +08001978 <_puts_r>: + 8001978: 6a03 ldr r3, [r0, #32] + 800197a: b570 push {r4, r5, r6, lr} + 800197c: 0005 movs r5, r0 + 800197e: 000e movs r6, r1 + 8001980: 6884 ldr r4, [r0, #8] + 8001982: 2b00 cmp r3, #0 + 8001984: d101 bne.n 800198a <_puts_r+0x12> + 8001986: f7ff ffb3 bl 80018f0 <__sinit> + 800198a: 6e63 ldr r3, [r4, #100] @ 0x64 + 800198c: 07db lsls r3, r3, #31 + 800198e: d405 bmi.n 800199c <_puts_r+0x24> + 8001990: 89a3 ldrh r3, [r4, #12] + 8001992: 059b lsls r3, r3, #22 + 8001994: d402 bmi.n 800199c <_puts_r+0x24> + 8001996: 6da0 ldr r0, [r4, #88] @ 0x58 + 8001998: f000 f9bb bl 8001d12 <__retarget_lock_acquire_recursive> + 800199c: 89a3 ldrh r3, [r4, #12] + 800199e: 071b lsls r3, r3, #28 + 80019a0: d502 bpl.n 80019a8 <_puts_r+0x30> + 80019a2: 6923 ldr r3, [r4, #16] + 80019a4: 2b00 cmp r3, #0 + 80019a6: d11f bne.n 80019e8 <_puts_r+0x70> + 80019a8: 0021 movs r1, r4 + 80019aa: 0028 movs r0, r5 + 80019ac: f000 f8d2 bl 8001b54 <__swsetup_r> + 80019b0: 2800 cmp r0, #0 + 80019b2: d019 beq.n 80019e8 <_puts_r+0x70> + 80019b4: 2501 movs r5, #1 + 80019b6: 426d negs r5, r5 + 80019b8: 6e63 ldr r3, [r4, #100] @ 0x64 + 80019ba: 07db lsls r3, r3, #31 + 80019bc: d405 bmi.n 80019ca <_puts_r+0x52> + 80019be: 89a3 ldrh r3, [r4, #12] + 80019c0: 059b lsls r3, r3, #22 + 80019c2: d402 bmi.n 80019ca <_puts_r+0x52> + 80019c4: 6da0 ldr r0, [r4, #88] @ 0x58 + 80019c6: f000 f9a5 bl 8001d14 <__retarget_lock_release_recursive> + 80019ca: 0028 movs r0, r5 + 80019cc: bd70 pop {r4, r5, r6, pc} + 80019ce: 3601 adds r6, #1 + 80019d0: 60a3 str r3, [r4, #8] + 80019d2: 2b00 cmp r3, #0 + 80019d4: da04 bge.n 80019e0 <_puts_r+0x68> + 80019d6: 69a2 ldr r2, [r4, #24] + 80019d8: 429a cmp r2, r3 + 80019da: dc16 bgt.n 8001a0a <_puts_r+0x92> + 80019dc: 290a cmp r1, #10 + 80019de: d014 beq.n 8001a0a <_puts_r+0x92> + 80019e0: 6823 ldr r3, [r4, #0] + 80019e2: 1c5a adds r2, r3, #1 + 80019e4: 6022 str r2, [r4, #0] + 80019e6: 7019 strb r1, [r3, #0] + 80019e8: 68a3 ldr r3, [r4, #8] + 80019ea: 7831 ldrb r1, [r6, #0] + 80019ec: 3b01 subs r3, #1 + 80019ee: 2900 cmp r1, #0 + 80019f0: d1ed bne.n 80019ce <_puts_r+0x56> + 80019f2: 60a3 str r3, [r4, #8] + 80019f4: 2b00 cmp r3, #0 + 80019f6: da0f bge.n 8001a18 <_puts_r+0xa0> + 80019f8: 0022 movs r2, r4 + 80019fa: 0028 movs r0, r5 + 80019fc: 310a adds r1, #10 + 80019fe: f000 f867 bl 8001ad0 <__swbuf_r> + 8001a02: 3001 adds r0, #1 + 8001a04: d0d6 beq.n 80019b4 <_puts_r+0x3c> + 8001a06: 250a movs r5, #10 + 8001a08: e7d6 b.n 80019b8 <_puts_r+0x40> + 8001a0a: 0022 movs r2, r4 + 8001a0c: 0028 movs r0, r5 + 8001a0e: f000 f85f bl 8001ad0 <__swbuf_r> + 8001a12: 3001 adds r0, #1 + 8001a14: d1e8 bne.n 80019e8 <_puts_r+0x70> + 8001a16: e7cd b.n 80019b4 <_puts_r+0x3c> + 8001a18: 6823 ldr r3, [r4, #0] + 8001a1a: 1c5a adds r2, r3, #1 + 8001a1c: 6022 str r2, [r4, #0] + 8001a1e: 220a movs r2, #10 + 8001a20: 701a strb r2, [r3, #0] + 8001a22: e7f0 b.n 8001a06 <_puts_r+0x8e> + +08001a24 : + 8001a24: b510 push {r4, lr} + 8001a26: 4b03 ldr r3, [pc, #12] @ (8001a34 ) + 8001a28: 0001 movs r1, r0 + 8001a2a: 6818 ldr r0, [r3, #0] + 8001a2c: f7ff ffa4 bl 8001978 <_puts_r> + 8001a30: bd10 pop {r4, pc} + 8001a32: 46c0 nop @ (mov r8, r8) + 8001a34: 20000018 .word 0x20000018 + +08001a38 <__sread>: + 8001a38: b570 push {r4, r5, r6, lr} + 8001a3a: 000c movs r4, r1 + 8001a3c: 250e movs r5, #14 + 8001a3e: 5f49 ldrsh r1, [r1, r5] + 8001a40: f000 f914 bl 8001c6c <_read_r> + 8001a44: 2800 cmp r0, #0 + 8001a46: db03 blt.n 8001a50 <__sread+0x18> + 8001a48: 6d63 ldr r3, [r4, #84] @ 0x54 + 8001a4a: 181b adds r3, r3, r0 + 8001a4c: 6563 str r3, [r4, #84] @ 0x54 + 8001a4e: bd70 pop {r4, r5, r6, pc} + 8001a50: 89a3 ldrh r3, [r4, #12] + 8001a52: 4a02 ldr r2, [pc, #8] @ (8001a5c <__sread+0x24>) + 8001a54: 4013 ands r3, r2 + 8001a56: 81a3 strh r3, [r4, #12] + 8001a58: e7f9 b.n 8001a4e <__sread+0x16> + 8001a5a: 46c0 nop @ (mov r8, r8) + 8001a5c: ffffefff .word 0xffffefff + +08001a60 <__swrite>: + 8001a60: b5f8 push {r3, r4, r5, r6, r7, lr} + 8001a62: 001f movs r7, r3 + 8001a64: 898b ldrh r3, [r1, #12] + 8001a66: 0005 movs r5, r0 + 8001a68: 000c movs r4, r1 + 8001a6a: 0016 movs r6, r2 + 8001a6c: 05db lsls r3, r3, #23 + 8001a6e: d505 bpl.n 8001a7c <__swrite+0x1c> + 8001a70: 230e movs r3, #14 + 8001a72: 5ec9 ldrsh r1, [r1, r3] + 8001a74: 2200 movs r2, #0 + 8001a76: 2302 movs r3, #2 + 8001a78: f000 f8e4 bl 8001c44 <_lseek_r> + 8001a7c: 89a3 ldrh r3, [r4, #12] + 8001a7e: 4a05 ldr r2, [pc, #20] @ (8001a94 <__swrite+0x34>) + 8001a80: 0028 movs r0, r5 + 8001a82: 4013 ands r3, r2 + 8001a84: 81a3 strh r3, [r4, #12] + 8001a86: 0032 movs r2, r6 + 8001a88: 230e movs r3, #14 + 8001a8a: 5ee1 ldrsh r1, [r4, r3] + 8001a8c: 003b movs r3, r7 + 8001a8e: f000 f901 bl 8001c94 <_write_r> + 8001a92: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8001a94: ffffefff .word 0xffffefff + +08001a98 <__sseek>: + 8001a98: b570 push {r4, r5, r6, lr} + 8001a9a: 000c movs r4, r1 + 8001a9c: 250e movs r5, #14 + 8001a9e: 5f49 ldrsh r1, [r1, r5] + 8001aa0: f000 f8d0 bl 8001c44 <_lseek_r> + 8001aa4: 89a3 ldrh r3, [r4, #12] + 8001aa6: 1c42 adds r2, r0, #1 + 8001aa8: d103 bne.n 8001ab2 <__sseek+0x1a> + 8001aaa: 4a05 ldr r2, [pc, #20] @ (8001ac0 <__sseek+0x28>) + 8001aac: 4013 ands r3, r2 + 8001aae: 81a3 strh r3, [r4, #12] + 8001ab0: bd70 pop {r4, r5, r6, pc} + 8001ab2: 2280 movs r2, #128 @ 0x80 + 8001ab4: 0152 lsls r2, r2, #5 + 8001ab6: 4313 orrs r3, r2 + 8001ab8: 81a3 strh r3, [r4, #12] + 8001aba: 6560 str r0, [r4, #84] @ 0x54 + 8001abc: e7f8 b.n 8001ab0 <__sseek+0x18> + 8001abe: 46c0 nop @ (mov r8, r8) + 8001ac0: ffffefff .word 0xffffefff + +08001ac4 <__sclose>: + 8001ac4: b510 push {r4, lr} + 8001ac6: 230e movs r3, #14 + 8001ac8: 5ec9 ldrsh r1, [r1, r3] + 8001aca: f000 f8a9 bl 8001c20 <_close_r> + 8001ace: bd10 pop {r4, pc} + +08001ad0 <__swbuf_r>: + 8001ad0: b5f8 push {r3, r4, r5, r6, r7, lr} + 8001ad2: 0006 movs r6, r0 + 8001ad4: 000d movs r5, r1 + 8001ad6: 0014 movs r4, r2 + 8001ad8: 2800 cmp r0, #0 + 8001ada: d004 beq.n 8001ae6 <__swbuf_r+0x16> + 8001adc: 6a03 ldr r3, [r0, #32] + 8001ade: 2b00 cmp r3, #0 + 8001ae0: d101 bne.n 8001ae6 <__swbuf_r+0x16> + 8001ae2: f7ff ff05 bl 80018f0 <__sinit> + 8001ae6: 69a3 ldr r3, [r4, #24] + 8001ae8: 60a3 str r3, [r4, #8] + 8001aea: 89a3 ldrh r3, [r4, #12] + 8001aec: 071b lsls r3, r3, #28 + 8001aee: d502 bpl.n 8001af6 <__swbuf_r+0x26> + 8001af0: 6923 ldr r3, [r4, #16] + 8001af2: 2b00 cmp r3, #0 + 8001af4: d109 bne.n 8001b0a <__swbuf_r+0x3a> + 8001af6: 0021 movs r1, r4 + 8001af8: 0030 movs r0, r6 + 8001afa: f000 f82b bl 8001b54 <__swsetup_r> + 8001afe: 2800 cmp r0, #0 + 8001b00: d003 beq.n 8001b0a <__swbuf_r+0x3a> + 8001b02: 2501 movs r5, #1 + 8001b04: 426d negs r5, r5 + 8001b06: 0028 movs r0, r5 + 8001b08: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8001b0a: 6923 ldr r3, [r4, #16] + 8001b0c: 6820 ldr r0, [r4, #0] + 8001b0e: b2ef uxtb r7, r5 + 8001b10: 1ac0 subs r0, r0, r3 + 8001b12: 6963 ldr r3, [r4, #20] + 8001b14: b2ed uxtb r5, r5 + 8001b16: 4283 cmp r3, r0 + 8001b18: dc05 bgt.n 8001b26 <__swbuf_r+0x56> + 8001b1a: 0021 movs r1, r4 + 8001b1c: 0030 movs r0, r6 + 8001b1e: f000 fd3d bl 800259c <_fflush_r> + 8001b22: 2800 cmp r0, #0 + 8001b24: d1ed bne.n 8001b02 <__swbuf_r+0x32> + 8001b26: 68a3 ldr r3, [r4, #8] + 8001b28: 3001 adds r0, #1 + 8001b2a: 3b01 subs r3, #1 + 8001b2c: 60a3 str r3, [r4, #8] + 8001b2e: 6823 ldr r3, [r4, #0] + 8001b30: 1c5a adds r2, r3, #1 + 8001b32: 6022 str r2, [r4, #0] + 8001b34: 701f strb r7, [r3, #0] + 8001b36: 6963 ldr r3, [r4, #20] + 8001b38: 4283 cmp r3, r0 + 8001b3a: d004 beq.n 8001b46 <__swbuf_r+0x76> + 8001b3c: 89a3 ldrh r3, [r4, #12] + 8001b3e: 07db lsls r3, r3, #31 + 8001b40: d5e1 bpl.n 8001b06 <__swbuf_r+0x36> + 8001b42: 2d0a cmp r5, #10 + 8001b44: d1df bne.n 8001b06 <__swbuf_r+0x36> + 8001b46: 0021 movs r1, r4 + 8001b48: 0030 movs r0, r6 + 8001b4a: f000 fd27 bl 800259c <_fflush_r> + 8001b4e: 2800 cmp r0, #0 + 8001b50: d0d9 beq.n 8001b06 <__swbuf_r+0x36> + 8001b52: e7d6 b.n 8001b02 <__swbuf_r+0x32> + +08001b54 <__swsetup_r>: + 8001b54: 4b2d ldr r3, [pc, #180] @ (8001c0c <__swsetup_r+0xb8>) + 8001b56: b570 push {r4, r5, r6, lr} + 8001b58: 0005 movs r5, r0 + 8001b5a: 6818 ldr r0, [r3, #0] + 8001b5c: 000c movs r4, r1 + 8001b5e: 2800 cmp r0, #0 + 8001b60: d004 beq.n 8001b6c <__swsetup_r+0x18> + 8001b62: 6a03 ldr r3, [r0, #32] + 8001b64: 2b00 cmp r3, #0 + 8001b66: d101 bne.n 8001b6c <__swsetup_r+0x18> + 8001b68: f7ff fec2 bl 80018f0 <__sinit> + 8001b6c: 220c movs r2, #12 + 8001b6e: 5ea3 ldrsh r3, [r4, r2] + 8001b70: 071a lsls r2, r3, #28 + 8001b72: d423 bmi.n 8001bbc <__swsetup_r+0x68> + 8001b74: 06da lsls r2, r3, #27 + 8001b76: d407 bmi.n 8001b88 <__swsetup_r+0x34> + 8001b78: 2209 movs r2, #9 + 8001b7a: 602a str r2, [r5, #0] + 8001b7c: 2240 movs r2, #64 @ 0x40 + 8001b7e: 2001 movs r0, #1 + 8001b80: 4313 orrs r3, r2 + 8001b82: 81a3 strh r3, [r4, #12] + 8001b84: 4240 negs r0, r0 + 8001b86: e03a b.n 8001bfe <__swsetup_r+0xaa> + 8001b88: 075b lsls r3, r3, #29 + 8001b8a: d513 bpl.n 8001bb4 <__swsetup_r+0x60> + 8001b8c: 6b61 ldr r1, [r4, #52] @ 0x34 + 8001b8e: 2900 cmp r1, #0 + 8001b90: d008 beq.n 8001ba4 <__swsetup_r+0x50> + 8001b92: 0023 movs r3, r4 + 8001b94: 3344 adds r3, #68 @ 0x44 + 8001b96: 4299 cmp r1, r3 + 8001b98: d002 beq.n 8001ba0 <__swsetup_r+0x4c> + 8001b9a: 0028 movs r0, r5 + 8001b9c: f000 f8bc bl 8001d18 <_free_r> + 8001ba0: 2300 movs r3, #0 + 8001ba2: 6363 str r3, [r4, #52] @ 0x34 + 8001ba4: 2224 movs r2, #36 @ 0x24 + 8001ba6: 89a3 ldrh r3, [r4, #12] + 8001ba8: 4393 bics r3, r2 + 8001baa: 81a3 strh r3, [r4, #12] + 8001bac: 2300 movs r3, #0 + 8001bae: 6063 str r3, [r4, #4] + 8001bb0: 6923 ldr r3, [r4, #16] + 8001bb2: 6023 str r3, [r4, #0] + 8001bb4: 2308 movs r3, #8 + 8001bb6: 89a2 ldrh r2, [r4, #12] + 8001bb8: 4313 orrs r3, r2 + 8001bba: 81a3 strh r3, [r4, #12] + 8001bbc: 6923 ldr r3, [r4, #16] + 8001bbe: 2b00 cmp r3, #0 + 8001bc0: d10b bne.n 8001bda <__swsetup_r+0x86> + 8001bc2: 21a0 movs r1, #160 @ 0xa0 + 8001bc4: 2280 movs r2, #128 @ 0x80 + 8001bc6: 89a3 ldrh r3, [r4, #12] + 8001bc8: 0089 lsls r1, r1, #2 + 8001bca: 0092 lsls r2, r2, #2 + 8001bcc: 400b ands r3, r1 + 8001bce: 4293 cmp r3, r2 + 8001bd0: d003 beq.n 8001bda <__swsetup_r+0x86> + 8001bd2: 0021 movs r1, r4 + 8001bd4: 0028 movs r0, r5 + 8001bd6: f000 fd37 bl 8002648 <__smakebuf_r> + 8001bda: 220c movs r2, #12 + 8001bdc: 5ea3 ldrsh r3, [r4, r2] + 8001bde: 2101 movs r1, #1 + 8001be0: 001a movs r2, r3 + 8001be2: 400a ands r2, r1 + 8001be4: 420b tst r3, r1 + 8001be6: d00b beq.n 8001c00 <__swsetup_r+0xac> + 8001be8: 2200 movs r2, #0 + 8001bea: 60a2 str r2, [r4, #8] + 8001bec: 6962 ldr r2, [r4, #20] + 8001bee: 4252 negs r2, r2 + 8001bf0: 61a2 str r2, [r4, #24] + 8001bf2: 2000 movs r0, #0 + 8001bf4: 6922 ldr r2, [r4, #16] + 8001bf6: 4282 cmp r2, r0 + 8001bf8: d101 bne.n 8001bfe <__swsetup_r+0xaa> + 8001bfa: 061a lsls r2, r3, #24 + 8001bfc: d4be bmi.n 8001b7c <__swsetup_r+0x28> + 8001bfe: bd70 pop {r4, r5, r6, pc} + 8001c00: 0799 lsls r1, r3, #30 + 8001c02: d400 bmi.n 8001c06 <__swsetup_r+0xb2> + 8001c04: 6962 ldr r2, [r4, #20] + 8001c06: 60a2 str r2, [r4, #8] + 8001c08: e7f3 b.n 8001bf2 <__swsetup_r+0x9e> + 8001c0a: 46c0 nop @ (mov r8, r8) + 8001c0c: 20000018 .word 0x20000018 + +08001c10 : + 8001c10: 0003 movs r3, r0 + 8001c12: 1882 adds r2, r0, r2 + 8001c14: 4293 cmp r3, r2 + 8001c16: d100 bne.n 8001c1a + 8001c18: 4770 bx lr + 8001c1a: 7019 strb r1, [r3, #0] + 8001c1c: 3301 adds r3, #1 + 8001c1e: e7f9 b.n 8001c14 + +08001c20 <_close_r>: + 8001c20: 2300 movs r3, #0 + 8001c22: b570 push {r4, r5, r6, lr} + 8001c24: 4d06 ldr r5, [pc, #24] @ (8001c40 <_close_r+0x20>) + 8001c26: 0004 movs r4, r0 + 8001c28: 0008 movs r0, r1 + 8001c2a: 602b str r3, [r5, #0] + 8001c2c: f7fe fb46 bl 80002bc <_close> + 8001c30: 1c43 adds r3, r0, #1 + 8001c32: d103 bne.n 8001c3c <_close_r+0x1c> + 8001c34: 682b ldr r3, [r5, #0] + 8001c36: 2b00 cmp r3, #0 + 8001c38: d000 beq.n 8001c3c <_close_r+0x1c> + 8001c3a: 6023 str r3, [r4, #0] + 8001c3c: bd70 pop {r4, r5, r6, pc} + 8001c3e: 46c0 nop @ (mov r8, r8) + 8001c40: 2000028c .word 0x2000028c + +08001c44 <_lseek_r>: + 8001c44: b570 push {r4, r5, r6, lr} + 8001c46: 0004 movs r4, r0 + 8001c48: 0008 movs r0, r1 + 8001c4a: 0011 movs r1, r2 + 8001c4c: 001a movs r2, r3 + 8001c4e: 2300 movs r3, #0 + 8001c50: 4d05 ldr r5, [pc, #20] @ (8001c68 <_lseek_r+0x24>) + 8001c52: 602b str r3, [r5, #0] + 8001c54: f7fe fb3c bl 80002d0 <_lseek> + 8001c58: 1c43 adds r3, r0, #1 + 8001c5a: d103 bne.n 8001c64 <_lseek_r+0x20> + 8001c5c: 682b ldr r3, [r5, #0] + 8001c5e: 2b00 cmp r3, #0 + 8001c60: d000 beq.n 8001c64 <_lseek_r+0x20> + 8001c62: 6023 str r3, [r4, #0] + 8001c64: bd70 pop {r4, r5, r6, pc} + 8001c66: 46c0 nop @ (mov r8, r8) + 8001c68: 2000028c .word 0x2000028c + +08001c6c <_read_r>: + 8001c6c: b570 push {r4, r5, r6, lr} + 8001c6e: 0004 movs r4, r0 + 8001c70: 0008 movs r0, r1 + 8001c72: 0011 movs r1, r2 + 8001c74: 001a movs r2, r3 + 8001c76: 2300 movs r3, #0 + 8001c78: 4d05 ldr r5, [pc, #20] @ (8001c90 <_read_r+0x24>) + 8001c7a: 602b str r3, [r5, #0] + 8001c7c: f7fe fb02 bl 8000284 <_read> + 8001c80: 1c43 adds r3, r0, #1 + 8001c82: d103 bne.n 8001c8c <_read_r+0x20> + 8001c84: 682b ldr r3, [r5, #0] + 8001c86: 2b00 cmp r3, #0 + 8001c88: d000 beq.n 8001c8c <_read_r+0x20> + 8001c8a: 6023 str r3, [r4, #0] + 8001c8c: bd70 pop {r4, r5, r6, pc} + 8001c8e: 46c0 nop @ (mov r8, r8) + 8001c90: 2000028c .word 0x2000028c + +08001c94 <_write_r>: + 8001c94: b570 push {r4, r5, r6, lr} + 8001c96: 0004 movs r4, r0 + 8001c98: 0008 movs r0, r1 + 8001c9a: 0011 movs r1, r2 + 8001c9c: 001a movs r2, r3 + 8001c9e: 2300 movs r3, #0 + 8001ca0: 4d05 ldr r5, [pc, #20] @ (8001cb8 <_write_r+0x24>) + 8001ca2: 602b str r3, [r5, #0] + 8001ca4: f7fe fafc bl 80002a0 <_write> + 8001ca8: 1c43 adds r3, r0, #1 + 8001caa: d103 bne.n 8001cb4 <_write_r+0x20> + 8001cac: 682b ldr r3, [r5, #0] + 8001cae: 2b00 cmp r3, #0 + 8001cb0: d000 beq.n 8001cb4 <_write_r+0x20> + 8001cb2: 6023 str r3, [r4, #0] + 8001cb4: bd70 pop {r4, r5, r6, pc} + 8001cb6: 46c0 nop @ (mov r8, r8) + 8001cb8: 2000028c .word 0x2000028c + +08001cbc <__errno>: + 8001cbc: 4b01 ldr r3, [pc, #4] @ (8001cc4 <__errno+0x8>) + 8001cbe: 6818 ldr r0, [r3, #0] + 8001cc0: 4770 bx lr + 8001cc2: 46c0 nop @ (mov r8, r8) + 8001cc4: 20000018 .word 0x20000018 + +08001cc8 <__libc_init_array>: + 8001cc8: b570 push {r4, r5, r6, lr} + 8001cca: 2600 movs r6, #0 + 8001ccc: 4c0c ldr r4, [pc, #48] @ (8001d00 <__libc_init_array+0x38>) + 8001cce: 4d0d ldr r5, [pc, #52] @ (8001d04 <__libc_init_array+0x3c>) + 8001cd0: 1b64 subs r4, r4, r5 + 8001cd2: 10a4 asrs r4, r4, #2 + 8001cd4: 42a6 cmp r6, r4 + 8001cd6: d109 bne.n 8001cec <__libc_init_array+0x24> + 8001cd8: 2600 movs r6, #0 + 8001cda: f000 fd39 bl 8002750 <_init> + 8001cde: 4c0a ldr r4, [pc, #40] @ (8001d08 <__libc_init_array+0x40>) + 8001ce0: 4d0a ldr r5, [pc, #40] @ (8001d0c <__libc_init_array+0x44>) + 8001ce2: 1b64 subs r4, r4, r5 + 8001ce4: 10a4 asrs r4, r4, #2 + 8001ce6: 42a6 cmp r6, r4 + 8001ce8: d105 bne.n 8001cf6 <__libc_init_array+0x2e> + 8001cea: bd70 pop {r4, r5, r6, pc} + 8001cec: 00b3 lsls r3, r6, #2 + 8001cee: 58eb ldr r3, [r5, r3] + 8001cf0: 4798 blx r3 + 8001cf2: 3601 adds r6, #1 + 8001cf4: e7ee b.n 8001cd4 <__libc_init_array+0xc> + 8001cf6: 00b3 lsls r3, r6, #2 + 8001cf8: 58eb ldr r3, [r5, r3] + 8001cfa: 4798 blx r3 + 8001cfc: 3601 adds r6, #1 + 8001cfe: e7f2 b.n 8001ce6 <__libc_init_array+0x1e> + 8001d00: 080029ac .word 0x080029ac + 8001d04: 080029ac .word 0x080029ac + 8001d08: 080029b0 .word 0x080029b0 + 8001d0c: 080029ac .word 0x080029ac + +08001d10 <__retarget_lock_init_recursive>: + 8001d10: 4770 bx lr + +08001d12 <__retarget_lock_acquire_recursive>: + 8001d12: 4770 bx lr + +08001d14 <__retarget_lock_release_recursive>: + 8001d14: 4770 bx lr + ... + +08001d18 <_free_r>: + 8001d18: b570 push {r4, r5, r6, lr} + 8001d1a: 0005 movs r5, r0 + 8001d1c: 1e0c subs r4, r1, #0 + 8001d1e: d010 beq.n 8001d42 <_free_r+0x2a> + 8001d20: 3c04 subs r4, #4 + 8001d22: 6823 ldr r3, [r4, #0] + 8001d24: 2b00 cmp r3, #0 + 8001d26: da00 bge.n 8001d2a <_free_r+0x12> + 8001d28: 18e4 adds r4, r4, r3 + 8001d2a: 0028 movs r0, r5 + 8001d2c: f000 f8e0 bl 8001ef0 <__malloc_lock> + 8001d30: 4a1d ldr r2, [pc, #116] @ (8001da8 <_free_r+0x90>) + 8001d32: 6813 ldr r3, [r2, #0] + 8001d34: 2b00 cmp r3, #0 + 8001d36: d105 bne.n 8001d44 <_free_r+0x2c> + 8001d38: 6063 str r3, [r4, #4] + 8001d3a: 6014 str r4, [r2, #0] + 8001d3c: 0028 movs r0, r5 + 8001d3e: f000 f8df bl 8001f00 <__malloc_unlock> + 8001d42: bd70 pop {r4, r5, r6, pc} + 8001d44: 42a3 cmp r3, r4 + 8001d46: d908 bls.n 8001d5a <_free_r+0x42> + 8001d48: 6820 ldr r0, [r4, #0] + 8001d4a: 1821 adds r1, r4, r0 + 8001d4c: 428b cmp r3, r1 + 8001d4e: d1f3 bne.n 8001d38 <_free_r+0x20> + 8001d50: 6819 ldr r1, [r3, #0] + 8001d52: 685b ldr r3, [r3, #4] + 8001d54: 1809 adds r1, r1, r0 + 8001d56: 6021 str r1, [r4, #0] + 8001d58: e7ee b.n 8001d38 <_free_r+0x20> + 8001d5a: 001a movs r2, r3 + 8001d5c: 685b ldr r3, [r3, #4] + 8001d5e: 2b00 cmp r3, #0 + 8001d60: d001 beq.n 8001d66 <_free_r+0x4e> + 8001d62: 42a3 cmp r3, r4 + 8001d64: d9f9 bls.n 8001d5a <_free_r+0x42> + 8001d66: 6811 ldr r1, [r2, #0] + 8001d68: 1850 adds r0, r2, r1 + 8001d6a: 42a0 cmp r0, r4 + 8001d6c: d10b bne.n 8001d86 <_free_r+0x6e> + 8001d6e: 6820 ldr r0, [r4, #0] + 8001d70: 1809 adds r1, r1, r0 + 8001d72: 1850 adds r0, r2, r1 + 8001d74: 6011 str r1, [r2, #0] + 8001d76: 4283 cmp r3, r0 + 8001d78: d1e0 bne.n 8001d3c <_free_r+0x24> + 8001d7a: 6818 ldr r0, [r3, #0] + 8001d7c: 685b ldr r3, [r3, #4] + 8001d7e: 1841 adds r1, r0, r1 + 8001d80: 6011 str r1, [r2, #0] + 8001d82: 6053 str r3, [r2, #4] + 8001d84: e7da b.n 8001d3c <_free_r+0x24> + 8001d86: 42a0 cmp r0, r4 + 8001d88: d902 bls.n 8001d90 <_free_r+0x78> + 8001d8a: 230c movs r3, #12 + 8001d8c: 602b str r3, [r5, #0] + 8001d8e: e7d5 b.n 8001d3c <_free_r+0x24> + 8001d90: 6820 ldr r0, [r4, #0] + 8001d92: 1821 adds r1, r4, r0 + 8001d94: 428b cmp r3, r1 + 8001d96: d103 bne.n 8001da0 <_free_r+0x88> + 8001d98: 6819 ldr r1, [r3, #0] + 8001d9a: 685b ldr r3, [r3, #4] + 8001d9c: 1809 adds r1, r1, r0 + 8001d9e: 6021 str r1, [r4, #0] + 8001da0: 6063 str r3, [r4, #4] + 8001da2: 6054 str r4, [r2, #4] + 8001da4: e7ca b.n 8001d3c <_free_r+0x24> + 8001da6: 46c0 nop @ (mov r8, r8) + 8001da8: 20000298 .word 0x20000298 + +08001dac : + 8001dac: b570 push {r4, r5, r6, lr} + 8001dae: 4e0f ldr r6, [pc, #60] @ (8001dec ) + 8001db0: 000d movs r5, r1 + 8001db2: 6831 ldr r1, [r6, #0] + 8001db4: 0004 movs r4, r0 + 8001db6: 2900 cmp r1, #0 + 8001db8: d102 bne.n 8001dc0 + 8001dba: f000 fcab bl 8002714 <_sbrk_r> + 8001dbe: 6030 str r0, [r6, #0] + 8001dc0: 0029 movs r1, r5 + 8001dc2: 0020 movs r0, r4 + 8001dc4: f000 fca6 bl 8002714 <_sbrk_r> + 8001dc8: 1c43 adds r3, r0, #1 + 8001dca: d103 bne.n 8001dd4 + 8001dcc: 2501 movs r5, #1 + 8001dce: 426d negs r5, r5 + 8001dd0: 0028 movs r0, r5 + 8001dd2: bd70 pop {r4, r5, r6, pc} + 8001dd4: 2303 movs r3, #3 + 8001dd6: 1cc5 adds r5, r0, #3 + 8001dd8: 439d bics r5, r3 + 8001dda: 42a8 cmp r0, r5 + 8001ddc: d0f8 beq.n 8001dd0 + 8001dde: 1a29 subs r1, r5, r0 + 8001de0: 0020 movs r0, r4 + 8001de2: f000 fc97 bl 8002714 <_sbrk_r> + 8001de6: 3001 adds r0, #1 + 8001de8: d1f2 bne.n 8001dd0 + 8001dea: e7ef b.n 8001dcc + 8001dec: 20000294 .word 0x20000294 + +08001df0 <_malloc_r>: + 8001df0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8001df2: 2203 movs r2, #3 + 8001df4: 1ccb adds r3, r1, #3 + 8001df6: 4393 bics r3, r2 + 8001df8: 3308 adds r3, #8 + 8001dfa: 0005 movs r5, r0 + 8001dfc: 001f movs r7, r3 + 8001dfe: 2b0c cmp r3, #12 + 8001e00: d234 bcs.n 8001e6c <_malloc_r+0x7c> + 8001e02: 270c movs r7, #12 + 8001e04: 42b9 cmp r1, r7 + 8001e06: d833 bhi.n 8001e70 <_malloc_r+0x80> + 8001e08: 0028 movs r0, r5 + 8001e0a: f000 f871 bl 8001ef0 <__malloc_lock> + 8001e0e: 4e37 ldr r6, [pc, #220] @ (8001eec <_malloc_r+0xfc>) + 8001e10: 6833 ldr r3, [r6, #0] + 8001e12: 001c movs r4, r3 + 8001e14: 2c00 cmp r4, #0 + 8001e16: d12f bne.n 8001e78 <_malloc_r+0x88> + 8001e18: 0039 movs r1, r7 + 8001e1a: 0028 movs r0, r5 + 8001e1c: f7ff ffc6 bl 8001dac + 8001e20: 0004 movs r4, r0 + 8001e22: 1c43 adds r3, r0, #1 + 8001e24: d15f bne.n 8001ee6 <_malloc_r+0xf6> + 8001e26: 6834 ldr r4, [r6, #0] + 8001e28: 9400 str r4, [sp, #0] + 8001e2a: 9b00 ldr r3, [sp, #0] + 8001e2c: 2b00 cmp r3, #0 + 8001e2e: d14a bne.n 8001ec6 <_malloc_r+0xd6> + 8001e30: 2c00 cmp r4, #0 + 8001e32: d052 beq.n 8001eda <_malloc_r+0xea> + 8001e34: 6823 ldr r3, [r4, #0] + 8001e36: 0028 movs r0, r5 + 8001e38: 18e3 adds r3, r4, r3 + 8001e3a: 9900 ldr r1, [sp, #0] + 8001e3c: 9301 str r3, [sp, #4] + 8001e3e: f000 fc69 bl 8002714 <_sbrk_r> + 8001e42: 9b01 ldr r3, [sp, #4] + 8001e44: 4283 cmp r3, r0 + 8001e46: d148 bne.n 8001eda <_malloc_r+0xea> + 8001e48: 6823 ldr r3, [r4, #0] + 8001e4a: 0028 movs r0, r5 + 8001e4c: 1aff subs r7, r7, r3 + 8001e4e: 0039 movs r1, r7 + 8001e50: f7ff ffac bl 8001dac + 8001e54: 3001 adds r0, #1 + 8001e56: d040 beq.n 8001eda <_malloc_r+0xea> + 8001e58: 6823 ldr r3, [r4, #0] + 8001e5a: 19db adds r3, r3, r7 + 8001e5c: 6023 str r3, [r4, #0] + 8001e5e: 6833 ldr r3, [r6, #0] + 8001e60: 685a ldr r2, [r3, #4] + 8001e62: 2a00 cmp r2, #0 + 8001e64: d133 bne.n 8001ece <_malloc_r+0xde> + 8001e66: 9b00 ldr r3, [sp, #0] + 8001e68: 6033 str r3, [r6, #0] + 8001e6a: e019 b.n 8001ea0 <_malloc_r+0xb0> + 8001e6c: 2b00 cmp r3, #0 + 8001e6e: dac9 bge.n 8001e04 <_malloc_r+0x14> + 8001e70: 230c movs r3, #12 + 8001e72: 602b str r3, [r5, #0] + 8001e74: 2000 movs r0, #0 + 8001e76: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + 8001e78: 6821 ldr r1, [r4, #0] + 8001e7a: 1bc9 subs r1, r1, r7 + 8001e7c: d420 bmi.n 8001ec0 <_malloc_r+0xd0> + 8001e7e: 290b cmp r1, #11 + 8001e80: d90a bls.n 8001e98 <_malloc_r+0xa8> + 8001e82: 19e2 adds r2, r4, r7 + 8001e84: 6027 str r7, [r4, #0] + 8001e86: 42a3 cmp r3, r4 + 8001e88: d104 bne.n 8001e94 <_malloc_r+0xa4> + 8001e8a: 6032 str r2, [r6, #0] + 8001e8c: 6863 ldr r3, [r4, #4] + 8001e8e: 6011 str r1, [r2, #0] + 8001e90: 6053 str r3, [r2, #4] + 8001e92: e005 b.n 8001ea0 <_malloc_r+0xb0> + 8001e94: 605a str r2, [r3, #4] + 8001e96: e7f9 b.n 8001e8c <_malloc_r+0x9c> + 8001e98: 6862 ldr r2, [r4, #4] + 8001e9a: 42a3 cmp r3, r4 + 8001e9c: d10e bne.n 8001ebc <_malloc_r+0xcc> + 8001e9e: 6032 str r2, [r6, #0] + 8001ea0: 0028 movs r0, r5 + 8001ea2: f000 f82d bl 8001f00 <__malloc_unlock> + 8001ea6: 0020 movs r0, r4 + 8001ea8: 2207 movs r2, #7 + 8001eaa: 300b adds r0, #11 + 8001eac: 1d23 adds r3, r4, #4 + 8001eae: 4390 bics r0, r2 + 8001eb0: 1ac2 subs r2, r0, r3 + 8001eb2: 4298 cmp r0, r3 + 8001eb4: d0df beq.n 8001e76 <_malloc_r+0x86> + 8001eb6: 1a1b subs r3, r3, r0 + 8001eb8: 50a3 str r3, [r4, r2] + 8001eba: e7dc b.n 8001e76 <_malloc_r+0x86> + 8001ebc: 605a str r2, [r3, #4] + 8001ebe: e7ef b.n 8001ea0 <_malloc_r+0xb0> + 8001ec0: 0023 movs r3, r4 + 8001ec2: 6864 ldr r4, [r4, #4] + 8001ec4: e7a6 b.n 8001e14 <_malloc_r+0x24> + 8001ec6: 9c00 ldr r4, [sp, #0] + 8001ec8: 6863 ldr r3, [r4, #4] + 8001eca: 9300 str r3, [sp, #0] + 8001ecc: e7ad b.n 8001e2a <_malloc_r+0x3a> + 8001ece: 001a movs r2, r3 + 8001ed0: 685b ldr r3, [r3, #4] + 8001ed2: 42a3 cmp r3, r4 + 8001ed4: d1fb bne.n 8001ece <_malloc_r+0xde> + 8001ed6: 2300 movs r3, #0 + 8001ed8: e7da b.n 8001e90 <_malloc_r+0xa0> + 8001eda: 230c movs r3, #12 + 8001edc: 0028 movs r0, r5 + 8001ede: 602b str r3, [r5, #0] + 8001ee0: f000 f80e bl 8001f00 <__malloc_unlock> + 8001ee4: e7c6 b.n 8001e74 <_malloc_r+0x84> + 8001ee6: 6007 str r7, [r0, #0] + 8001ee8: e7da b.n 8001ea0 <_malloc_r+0xb0> + 8001eea: 46c0 nop @ (mov r8, r8) + 8001eec: 20000298 .word 0x20000298 + +08001ef0 <__malloc_lock>: + 8001ef0: b510 push {r4, lr} + 8001ef2: 4802 ldr r0, [pc, #8] @ (8001efc <__malloc_lock+0xc>) + 8001ef4: f7ff ff0d bl 8001d12 <__retarget_lock_acquire_recursive> + 8001ef8: bd10 pop {r4, pc} + 8001efa: 46c0 nop @ (mov r8, r8) + 8001efc: 20000290 .word 0x20000290 + +08001f00 <__malloc_unlock>: + 8001f00: b510 push {r4, lr} + 8001f02: 4802 ldr r0, [pc, #8] @ (8001f0c <__malloc_unlock+0xc>) + 8001f04: f7ff ff06 bl 8001d14 <__retarget_lock_release_recursive> + 8001f08: bd10 pop {r4, pc} + 8001f0a: 46c0 nop @ (mov r8, r8) + 8001f0c: 20000290 .word 0x20000290 + +08001f10 <__sfputc_r>: + 8001f10: 6893 ldr r3, [r2, #8] + 8001f12: b510 push {r4, lr} + 8001f14: 3b01 subs r3, #1 + 8001f16: 6093 str r3, [r2, #8] + 8001f18: 2b00 cmp r3, #0 + 8001f1a: da04 bge.n 8001f26 <__sfputc_r+0x16> + 8001f1c: 6994 ldr r4, [r2, #24] + 8001f1e: 42a3 cmp r3, r4 + 8001f20: db07 blt.n 8001f32 <__sfputc_r+0x22> + 8001f22: 290a cmp r1, #10 + 8001f24: d005 beq.n 8001f32 <__sfputc_r+0x22> + 8001f26: 6813 ldr r3, [r2, #0] + 8001f28: 1c58 adds r0, r3, #1 + 8001f2a: 6010 str r0, [r2, #0] + 8001f2c: 7019 strb r1, [r3, #0] + 8001f2e: 0008 movs r0, r1 + 8001f30: bd10 pop {r4, pc} + 8001f32: f7ff fdcd bl 8001ad0 <__swbuf_r> + 8001f36: 0001 movs r1, r0 + 8001f38: e7f9 b.n 8001f2e <__sfputc_r+0x1e> + +08001f3a <__sfputs_r>: + 8001f3a: b5f8 push {r3, r4, r5, r6, r7, lr} + 8001f3c: 0006 movs r6, r0 + 8001f3e: 000f movs r7, r1 + 8001f40: 0014 movs r4, r2 + 8001f42: 18d5 adds r5, r2, r3 + 8001f44: 42ac cmp r4, r5 + 8001f46: d101 bne.n 8001f4c <__sfputs_r+0x12> + 8001f48: 2000 movs r0, #0 + 8001f4a: e007 b.n 8001f5c <__sfputs_r+0x22> + 8001f4c: 7821 ldrb r1, [r4, #0] + 8001f4e: 003a movs r2, r7 + 8001f50: 0030 movs r0, r6 + 8001f52: f7ff ffdd bl 8001f10 <__sfputc_r> + 8001f56: 3401 adds r4, #1 + 8001f58: 1c43 adds r3, r0, #1 + 8001f5a: d1f3 bne.n 8001f44 <__sfputs_r+0xa> + 8001f5c: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +08001f60 <_vfiprintf_r>: + 8001f60: b5f0 push {r4, r5, r6, r7, lr} + 8001f62: b0a1 sub sp, #132 @ 0x84 + 8001f64: 000f movs r7, r1 + 8001f66: 0015 movs r5, r2 + 8001f68: 001e movs r6, r3 + 8001f6a: 9003 str r0, [sp, #12] + 8001f6c: 2800 cmp r0, #0 + 8001f6e: d004 beq.n 8001f7a <_vfiprintf_r+0x1a> + 8001f70: 6a03 ldr r3, [r0, #32] + 8001f72: 2b00 cmp r3, #0 + 8001f74: d101 bne.n 8001f7a <_vfiprintf_r+0x1a> + 8001f76: f7ff fcbb bl 80018f0 <__sinit> + 8001f7a: 6e7b ldr r3, [r7, #100] @ 0x64 + 8001f7c: 07db lsls r3, r3, #31 + 8001f7e: d405 bmi.n 8001f8c <_vfiprintf_r+0x2c> + 8001f80: 89bb ldrh r3, [r7, #12] + 8001f82: 059b lsls r3, r3, #22 + 8001f84: d402 bmi.n 8001f8c <_vfiprintf_r+0x2c> + 8001f86: 6db8 ldr r0, [r7, #88] @ 0x58 + 8001f88: f7ff fec3 bl 8001d12 <__retarget_lock_acquire_recursive> + 8001f8c: 89bb ldrh r3, [r7, #12] + 8001f8e: 071b lsls r3, r3, #28 + 8001f90: d502 bpl.n 8001f98 <_vfiprintf_r+0x38> + 8001f92: 693b ldr r3, [r7, #16] + 8001f94: 2b00 cmp r3, #0 + 8001f96: d113 bne.n 8001fc0 <_vfiprintf_r+0x60> + 8001f98: 0039 movs r1, r7 + 8001f9a: 9803 ldr r0, [sp, #12] + 8001f9c: f7ff fdda bl 8001b54 <__swsetup_r> + 8001fa0: 2800 cmp r0, #0 + 8001fa2: d00d beq.n 8001fc0 <_vfiprintf_r+0x60> + 8001fa4: 6e7b ldr r3, [r7, #100] @ 0x64 + 8001fa6: 07db lsls r3, r3, #31 + 8001fa8: d503 bpl.n 8001fb2 <_vfiprintf_r+0x52> + 8001faa: 2001 movs r0, #1 + 8001fac: 4240 negs r0, r0 + 8001fae: b021 add sp, #132 @ 0x84 + 8001fb0: bdf0 pop {r4, r5, r6, r7, pc} + 8001fb2: 89bb ldrh r3, [r7, #12] + 8001fb4: 059b lsls r3, r3, #22 + 8001fb6: d4f8 bmi.n 8001faa <_vfiprintf_r+0x4a> + 8001fb8: 6db8 ldr r0, [r7, #88] @ 0x58 + 8001fba: f7ff feab bl 8001d14 <__retarget_lock_release_recursive> + 8001fbe: e7f4 b.n 8001faa <_vfiprintf_r+0x4a> + 8001fc0: 2300 movs r3, #0 + 8001fc2: ac08 add r4, sp, #32 + 8001fc4: 6163 str r3, [r4, #20] + 8001fc6: 3320 adds r3, #32 + 8001fc8: 7663 strb r3, [r4, #25] + 8001fca: 3310 adds r3, #16 + 8001fcc: 76a3 strb r3, [r4, #26] + 8001fce: 9607 str r6, [sp, #28] + 8001fd0: 002e movs r6, r5 + 8001fd2: 7833 ldrb r3, [r6, #0] + 8001fd4: 2b00 cmp r3, #0 + 8001fd6: d001 beq.n 8001fdc <_vfiprintf_r+0x7c> + 8001fd8: 2b25 cmp r3, #37 @ 0x25 + 8001fda: d148 bne.n 800206e <_vfiprintf_r+0x10e> + 8001fdc: 1b73 subs r3, r6, r5 + 8001fde: 9305 str r3, [sp, #20] + 8001fe0: 42ae cmp r6, r5 + 8001fe2: d00b beq.n 8001ffc <_vfiprintf_r+0x9c> + 8001fe4: 002a movs r2, r5 + 8001fe6: 0039 movs r1, r7 + 8001fe8: 9803 ldr r0, [sp, #12] + 8001fea: f7ff ffa6 bl 8001f3a <__sfputs_r> + 8001fee: 3001 adds r0, #1 + 8001ff0: d100 bne.n 8001ff4 <_vfiprintf_r+0x94> + 8001ff2: e0ae b.n 8002152 <_vfiprintf_r+0x1f2> + 8001ff4: 6963 ldr r3, [r4, #20] + 8001ff6: 9a05 ldr r2, [sp, #20] + 8001ff8: 189b adds r3, r3, r2 + 8001ffa: 6163 str r3, [r4, #20] + 8001ffc: 7833 ldrb r3, [r6, #0] + 8001ffe: 2b00 cmp r3, #0 + 8002000: d100 bne.n 8002004 <_vfiprintf_r+0xa4> + 8002002: e0a6 b.n 8002152 <_vfiprintf_r+0x1f2> + 8002004: 2201 movs r2, #1 + 8002006: 2300 movs r3, #0 + 8002008: 4252 negs r2, r2 + 800200a: 6062 str r2, [r4, #4] + 800200c: a904 add r1, sp, #16 + 800200e: 3254 adds r2, #84 @ 0x54 + 8002010: 1852 adds r2, r2, r1 + 8002012: 1c75 adds r5, r6, #1 + 8002014: 6023 str r3, [r4, #0] + 8002016: 60e3 str r3, [r4, #12] + 8002018: 60a3 str r3, [r4, #8] + 800201a: 7013 strb r3, [r2, #0] + 800201c: 65a3 str r3, [r4, #88] @ 0x58 + 800201e: 4b59 ldr r3, [pc, #356] @ (8002184 <_vfiprintf_r+0x224>) + 8002020: 2205 movs r2, #5 + 8002022: 0018 movs r0, r3 + 8002024: 7829 ldrb r1, [r5, #0] + 8002026: 9305 str r3, [sp, #20] + 8002028: f000 fb86 bl 8002738 + 800202c: 1c6e adds r6, r5, #1 + 800202e: 2800 cmp r0, #0 + 8002030: d11f bne.n 8002072 <_vfiprintf_r+0x112> + 8002032: 6822 ldr r2, [r4, #0] + 8002034: 06d3 lsls r3, r2, #27 + 8002036: d504 bpl.n 8002042 <_vfiprintf_r+0xe2> + 8002038: 2353 movs r3, #83 @ 0x53 + 800203a: a904 add r1, sp, #16 + 800203c: 185b adds r3, r3, r1 + 800203e: 2120 movs r1, #32 + 8002040: 7019 strb r1, [r3, #0] + 8002042: 0713 lsls r3, r2, #28 + 8002044: d504 bpl.n 8002050 <_vfiprintf_r+0xf0> + 8002046: 2353 movs r3, #83 @ 0x53 + 8002048: a904 add r1, sp, #16 + 800204a: 185b adds r3, r3, r1 + 800204c: 212b movs r1, #43 @ 0x2b + 800204e: 7019 strb r1, [r3, #0] + 8002050: 782b ldrb r3, [r5, #0] + 8002052: 2b2a cmp r3, #42 @ 0x2a + 8002054: d016 beq.n 8002084 <_vfiprintf_r+0x124> + 8002056: 002e movs r6, r5 + 8002058: 2100 movs r1, #0 + 800205a: 200a movs r0, #10 + 800205c: 68e3 ldr r3, [r4, #12] + 800205e: 7832 ldrb r2, [r6, #0] + 8002060: 1c75 adds r5, r6, #1 + 8002062: 3a30 subs r2, #48 @ 0x30 + 8002064: 2a09 cmp r2, #9 + 8002066: d950 bls.n 800210a <_vfiprintf_r+0x1aa> + 8002068: 2900 cmp r1, #0 + 800206a: d111 bne.n 8002090 <_vfiprintf_r+0x130> + 800206c: e017 b.n 800209e <_vfiprintf_r+0x13e> + 800206e: 3601 adds r6, #1 + 8002070: e7af b.n 8001fd2 <_vfiprintf_r+0x72> + 8002072: 9b05 ldr r3, [sp, #20] + 8002074: 6822 ldr r2, [r4, #0] + 8002076: 1ac0 subs r0, r0, r3 + 8002078: 2301 movs r3, #1 + 800207a: 4083 lsls r3, r0 + 800207c: 4313 orrs r3, r2 + 800207e: 0035 movs r5, r6 + 8002080: 6023 str r3, [r4, #0] + 8002082: e7cc b.n 800201e <_vfiprintf_r+0xbe> + 8002084: 9b07 ldr r3, [sp, #28] + 8002086: 1d19 adds r1, r3, #4 + 8002088: 681b ldr r3, [r3, #0] + 800208a: 9107 str r1, [sp, #28] + 800208c: 2b00 cmp r3, #0 + 800208e: db01 blt.n 8002094 <_vfiprintf_r+0x134> + 8002090: 930b str r3, [sp, #44] @ 0x2c + 8002092: e004 b.n 800209e <_vfiprintf_r+0x13e> + 8002094: 425b negs r3, r3 + 8002096: 60e3 str r3, [r4, #12] + 8002098: 2302 movs r3, #2 + 800209a: 4313 orrs r3, r2 + 800209c: 6023 str r3, [r4, #0] + 800209e: 7833 ldrb r3, [r6, #0] + 80020a0: 2b2e cmp r3, #46 @ 0x2e + 80020a2: d10c bne.n 80020be <_vfiprintf_r+0x15e> + 80020a4: 7873 ldrb r3, [r6, #1] + 80020a6: 2b2a cmp r3, #42 @ 0x2a + 80020a8: d134 bne.n 8002114 <_vfiprintf_r+0x1b4> + 80020aa: 9b07 ldr r3, [sp, #28] + 80020ac: 3602 adds r6, #2 + 80020ae: 1d1a adds r2, r3, #4 + 80020b0: 681b ldr r3, [r3, #0] + 80020b2: 9207 str r2, [sp, #28] + 80020b4: 2b00 cmp r3, #0 + 80020b6: da01 bge.n 80020bc <_vfiprintf_r+0x15c> + 80020b8: 2301 movs r3, #1 + 80020ba: 425b negs r3, r3 + 80020bc: 9309 str r3, [sp, #36] @ 0x24 + 80020be: 4d32 ldr r5, [pc, #200] @ (8002188 <_vfiprintf_r+0x228>) + 80020c0: 2203 movs r2, #3 + 80020c2: 0028 movs r0, r5 + 80020c4: 7831 ldrb r1, [r6, #0] + 80020c6: f000 fb37 bl 8002738 + 80020ca: 2800 cmp r0, #0 + 80020cc: d006 beq.n 80020dc <_vfiprintf_r+0x17c> + 80020ce: 2340 movs r3, #64 @ 0x40 + 80020d0: 1b40 subs r0, r0, r5 + 80020d2: 4083 lsls r3, r0 + 80020d4: 6822 ldr r2, [r4, #0] + 80020d6: 3601 adds r6, #1 + 80020d8: 4313 orrs r3, r2 + 80020da: 6023 str r3, [r4, #0] + 80020dc: 7831 ldrb r1, [r6, #0] + 80020de: 2206 movs r2, #6 + 80020e0: 482a ldr r0, [pc, #168] @ (800218c <_vfiprintf_r+0x22c>) + 80020e2: 1c75 adds r5, r6, #1 + 80020e4: 7621 strb r1, [r4, #24] + 80020e6: f000 fb27 bl 8002738 + 80020ea: 2800 cmp r0, #0 + 80020ec: d040 beq.n 8002170 <_vfiprintf_r+0x210> + 80020ee: 4b28 ldr r3, [pc, #160] @ (8002190 <_vfiprintf_r+0x230>) + 80020f0: 2b00 cmp r3, #0 + 80020f2: d122 bne.n 800213a <_vfiprintf_r+0x1da> + 80020f4: 2207 movs r2, #7 + 80020f6: 9b07 ldr r3, [sp, #28] + 80020f8: 3307 adds r3, #7 + 80020fa: 4393 bics r3, r2 + 80020fc: 3308 adds r3, #8 + 80020fe: 9307 str r3, [sp, #28] + 8002100: 6963 ldr r3, [r4, #20] + 8002102: 9a04 ldr r2, [sp, #16] + 8002104: 189b adds r3, r3, r2 + 8002106: 6163 str r3, [r4, #20] + 8002108: e762 b.n 8001fd0 <_vfiprintf_r+0x70> + 800210a: 4343 muls r3, r0 + 800210c: 002e movs r6, r5 + 800210e: 2101 movs r1, #1 + 8002110: 189b adds r3, r3, r2 + 8002112: e7a4 b.n 800205e <_vfiprintf_r+0xfe> + 8002114: 2300 movs r3, #0 + 8002116: 200a movs r0, #10 + 8002118: 0019 movs r1, r3 + 800211a: 3601 adds r6, #1 + 800211c: 6063 str r3, [r4, #4] + 800211e: 7832 ldrb r2, [r6, #0] + 8002120: 1c75 adds r5, r6, #1 + 8002122: 3a30 subs r2, #48 @ 0x30 + 8002124: 2a09 cmp r2, #9 + 8002126: d903 bls.n 8002130 <_vfiprintf_r+0x1d0> + 8002128: 2b00 cmp r3, #0 + 800212a: d0c8 beq.n 80020be <_vfiprintf_r+0x15e> + 800212c: 9109 str r1, [sp, #36] @ 0x24 + 800212e: e7c6 b.n 80020be <_vfiprintf_r+0x15e> + 8002130: 4341 muls r1, r0 + 8002132: 002e movs r6, r5 + 8002134: 2301 movs r3, #1 + 8002136: 1889 adds r1, r1, r2 + 8002138: e7f1 b.n 800211e <_vfiprintf_r+0x1be> + 800213a: aa07 add r2, sp, #28 + 800213c: 9200 str r2, [sp, #0] + 800213e: 0021 movs r1, r4 + 8002140: 003a movs r2, r7 + 8002142: 4b14 ldr r3, [pc, #80] @ (8002194 <_vfiprintf_r+0x234>) + 8002144: 9803 ldr r0, [sp, #12] + 8002146: e000 b.n 800214a <_vfiprintf_r+0x1ea> + 8002148: bf00 nop + 800214a: 9004 str r0, [sp, #16] + 800214c: 9b04 ldr r3, [sp, #16] + 800214e: 3301 adds r3, #1 + 8002150: d1d6 bne.n 8002100 <_vfiprintf_r+0x1a0> + 8002152: 6e7b ldr r3, [r7, #100] @ 0x64 + 8002154: 07db lsls r3, r3, #31 + 8002156: d405 bmi.n 8002164 <_vfiprintf_r+0x204> + 8002158: 89bb ldrh r3, [r7, #12] + 800215a: 059b lsls r3, r3, #22 + 800215c: d402 bmi.n 8002164 <_vfiprintf_r+0x204> + 800215e: 6db8 ldr r0, [r7, #88] @ 0x58 + 8002160: f7ff fdd8 bl 8001d14 <__retarget_lock_release_recursive> + 8002164: 89bb ldrh r3, [r7, #12] + 8002166: 065b lsls r3, r3, #25 + 8002168: d500 bpl.n 800216c <_vfiprintf_r+0x20c> + 800216a: e71e b.n 8001faa <_vfiprintf_r+0x4a> + 800216c: 980d ldr r0, [sp, #52] @ 0x34 + 800216e: e71e b.n 8001fae <_vfiprintf_r+0x4e> + 8002170: aa07 add r2, sp, #28 + 8002172: 9200 str r2, [sp, #0] + 8002174: 0021 movs r1, r4 + 8002176: 003a movs r2, r7 + 8002178: 4b06 ldr r3, [pc, #24] @ (8002194 <_vfiprintf_r+0x234>) + 800217a: 9803 ldr r0, [sp, #12] + 800217c: f000 f87c bl 8002278 <_printf_i> + 8002180: e7e3 b.n 800214a <_vfiprintf_r+0x1ea> + 8002182: 46c0 nop @ (mov r8, r8) + 8002184: 08002979 .word 0x08002979 + 8002188: 0800297f .word 0x0800297f + 800218c: 08002983 .word 0x08002983 + 8002190: 00000000 .word 0x00000000 + 8002194: 08001f3b .word 0x08001f3b + +08002198 <_printf_common>: + 8002198: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 800219a: 0016 movs r6, r2 + 800219c: 9301 str r3, [sp, #4] + 800219e: 688a ldr r2, [r1, #8] + 80021a0: 690b ldr r3, [r1, #16] + 80021a2: 000c movs r4, r1 + 80021a4: 9000 str r0, [sp, #0] + 80021a6: 4293 cmp r3, r2 + 80021a8: da00 bge.n 80021ac <_printf_common+0x14> + 80021aa: 0013 movs r3, r2 + 80021ac: 0022 movs r2, r4 + 80021ae: 6033 str r3, [r6, #0] + 80021b0: 3243 adds r2, #67 @ 0x43 + 80021b2: 7812 ldrb r2, [r2, #0] + 80021b4: 2a00 cmp r2, #0 + 80021b6: d001 beq.n 80021bc <_printf_common+0x24> + 80021b8: 3301 adds r3, #1 + 80021ba: 6033 str r3, [r6, #0] + 80021bc: 6823 ldr r3, [r4, #0] + 80021be: 069b lsls r3, r3, #26 + 80021c0: d502 bpl.n 80021c8 <_printf_common+0x30> + 80021c2: 6833 ldr r3, [r6, #0] + 80021c4: 3302 adds r3, #2 + 80021c6: 6033 str r3, [r6, #0] + 80021c8: 6822 ldr r2, [r4, #0] + 80021ca: 2306 movs r3, #6 + 80021cc: 0015 movs r5, r2 + 80021ce: 401d ands r5, r3 + 80021d0: 421a tst r2, r3 + 80021d2: d027 beq.n 8002224 <_printf_common+0x8c> + 80021d4: 0023 movs r3, r4 + 80021d6: 3343 adds r3, #67 @ 0x43 + 80021d8: 781b ldrb r3, [r3, #0] + 80021da: 1e5a subs r2, r3, #1 + 80021dc: 4193 sbcs r3, r2 + 80021de: 6822 ldr r2, [r4, #0] + 80021e0: 0692 lsls r2, r2, #26 + 80021e2: d430 bmi.n 8002246 <_printf_common+0xae> + 80021e4: 0022 movs r2, r4 + 80021e6: 9901 ldr r1, [sp, #4] + 80021e8: 9800 ldr r0, [sp, #0] + 80021ea: 9d08 ldr r5, [sp, #32] + 80021ec: 3243 adds r2, #67 @ 0x43 + 80021ee: 47a8 blx r5 + 80021f0: 3001 adds r0, #1 + 80021f2: d025 beq.n 8002240 <_printf_common+0xa8> + 80021f4: 2206 movs r2, #6 + 80021f6: 6823 ldr r3, [r4, #0] + 80021f8: 2500 movs r5, #0 + 80021fa: 4013 ands r3, r2 + 80021fc: 2b04 cmp r3, #4 + 80021fe: d105 bne.n 800220c <_printf_common+0x74> + 8002200: 6833 ldr r3, [r6, #0] + 8002202: 68e5 ldr r5, [r4, #12] + 8002204: 1aed subs r5, r5, r3 + 8002206: 43eb mvns r3, r5 + 8002208: 17db asrs r3, r3, #31 + 800220a: 401d ands r5, r3 + 800220c: 68a3 ldr r3, [r4, #8] + 800220e: 6922 ldr r2, [r4, #16] + 8002210: 4293 cmp r3, r2 + 8002212: dd01 ble.n 8002218 <_printf_common+0x80> + 8002214: 1a9b subs r3, r3, r2 + 8002216: 18ed adds r5, r5, r3 + 8002218: 2600 movs r6, #0 + 800221a: 42b5 cmp r5, r6 + 800221c: d120 bne.n 8002260 <_printf_common+0xc8> + 800221e: 2000 movs r0, #0 + 8002220: e010 b.n 8002244 <_printf_common+0xac> + 8002222: 3501 adds r5, #1 + 8002224: 68e3 ldr r3, [r4, #12] + 8002226: 6832 ldr r2, [r6, #0] + 8002228: 1a9b subs r3, r3, r2 + 800222a: 42ab cmp r3, r5 + 800222c: ddd2 ble.n 80021d4 <_printf_common+0x3c> + 800222e: 0022 movs r2, r4 + 8002230: 2301 movs r3, #1 + 8002232: 9901 ldr r1, [sp, #4] + 8002234: 9800 ldr r0, [sp, #0] + 8002236: 9f08 ldr r7, [sp, #32] + 8002238: 3219 adds r2, #25 + 800223a: 47b8 blx r7 + 800223c: 3001 adds r0, #1 + 800223e: d1f0 bne.n 8002222 <_printf_common+0x8a> + 8002240: 2001 movs r0, #1 + 8002242: 4240 negs r0, r0 + 8002244: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + 8002246: 2030 movs r0, #48 @ 0x30 + 8002248: 18e1 adds r1, r4, r3 + 800224a: 3143 adds r1, #67 @ 0x43 + 800224c: 7008 strb r0, [r1, #0] + 800224e: 0021 movs r1, r4 + 8002250: 1c5a adds r2, r3, #1 + 8002252: 3145 adds r1, #69 @ 0x45 + 8002254: 7809 ldrb r1, [r1, #0] + 8002256: 18a2 adds r2, r4, r2 + 8002258: 3243 adds r2, #67 @ 0x43 + 800225a: 3302 adds r3, #2 + 800225c: 7011 strb r1, [r2, #0] + 800225e: e7c1 b.n 80021e4 <_printf_common+0x4c> + 8002260: 0022 movs r2, r4 + 8002262: 2301 movs r3, #1 + 8002264: 9901 ldr r1, [sp, #4] + 8002266: 9800 ldr r0, [sp, #0] + 8002268: 9f08 ldr r7, [sp, #32] + 800226a: 321a adds r2, #26 + 800226c: 47b8 blx r7 + 800226e: 3001 adds r0, #1 + 8002270: d0e6 beq.n 8002240 <_printf_common+0xa8> + 8002272: 3601 adds r6, #1 + 8002274: e7d1 b.n 800221a <_printf_common+0x82> + ... + +08002278 <_printf_i>: + 8002278: b5f0 push {r4, r5, r6, r7, lr} + 800227a: b08b sub sp, #44 @ 0x2c + 800227c: 9206 str r2, [sp, #24] + 800227e: 000a movs r2, r1 + 8002280: 3243 adds r2, #67 @ 0x43 + 8002282: 9307 str r3, [sp, #28] + 8002284: 9005 str r0, [sp, #20] + 8002286: 9203 str r2, [sp, #12] + 8002288: 7e0a ldrb r2, [r1, #24] + 800228a: 000c movs r4, r1 + 800228c: 9b10 ldr r3, [sp, #64] @ 0x40 + 800228e: 2a78 cmp r2, #120 @ 0x78 + 8002290: d809 bhi.n 80022a6 <_printf_i+0x2e> + 8002292: 2a62 cmp r2, #98 @ 0x62 + 8002294: d80b bhi.n 80022ae <_printf_i+0x36> + 8002296: 2a00 cmp r2, #0 + 8002298: d100 bne.n 800229c <_printf_i+0x24> + 800229a: e0ba b.n 8002412 <_printf_i+0x19a> + 800229c: 497a ldr r1, [pc, #488] @ (8002488 <_printf_i+0x210>) + 800229e: 9104 str r1, [sp, #16] + 80022a0: 2a58 cmp r2, #88 @ 0x58 + 80022a2: d100 bne.n 80022a6 <_printf_i+0x2e> + 80022a4: e08e b.n 80023c4 <_printf_i+0x14c> + 80022a6: 0025 movs r5, r4 + 80022a8: 3542 adds r5, #66 @ 0x42 + 80022aa: 702a strb r2, [r5, #0] + 80022ac: e022 b.n 80022f4 <_printf_i+0x7c> + 80022ae: 0010 movs r0, r2 + 80022b0: 3863 subs r0, #99 @ 0x63 + 80022b2: 2815 cmp r0, #21 + 80022b4: d8f7 bhi.n 80022a6 <_printf_i+0x2e> + 80022b6: f7fd ff27 bl 8000108 <__gnu_thumb1_case_shi> + 80022ba: 0016 .short 0x0016 + 80022bc: fff6001f .word 0xfff6001f + 80022c0: fff6fff6 .word 0xfff6fff6 + 80022c4: 001ffff6 .word 0x001ffff6 + 80022c8: fff6fff6 .word 0xfff6fff6 + 80022cc: fff6fff6 .word 0xfff6fff6 + 80022d0: 0036009f .word 0x0036009f + 80022d4: fff6007e .word 0xfff6007e + 80022d8: 00b0fff6 .word 0x00b0fff6 + 80022dc: 0036fff6 .word 0x0036fff6 + 80022e0: fff6fff6 .word 0xfff6fff6 + 80022e4: 0082 .short 0x0082 + 80022e6: 0025 movs r5, r4 + 80022e8: 681a ldr r2, [r3, #0] + 80022ea: 3542 adds r5, #66 @ 0x42 + 80022ec: 1d11 adds r1, r2, #4 + 80022ee: 6019 str r1, [r3, #0] + 80022f0: 6813 ldr r3, [r2, #0] + 80022f2: 702b strb r3, [r5, #0] + 80022f4: 2301 movs r3, #1 + 80022f6: e09e b.n 8002436 <_printf_i+0x1be> + 80022f8: 6818 ldr r0, [r3, #0] + 80022fa: 6809 ldr r1, [r1, #0] + 80022fc: 1d02 adds r2, r0, #4 + 80022fe: 060d lsls r5, r1, #24 + 8002300: d50b bpl.n 800231a <_printf_i+0xa2> + 8002302: 6806 ldr r6, [r0, #0] + 8002304: 601a str r2, [r3, #0] + 8002306: 2e00 cmp r6, #0 + 8002308: da03 bge.n 8002312 <_printf_i+0x9a> + 800230a: 232d movs r3, #45 @ 0x2d + 800230c: 9a03 ldr r2, [sp, #12] + 800230e: 4276 negs r6, r6 + 8002310: 7013 strb r3, [r2, #0] + 8002312: 4b5d ldr r3, [pc, #372] @ (8002488 <_printf_i+0x210>) + 8002314: 270a movs r7, #10 + 8002316: 9304 str r3, [sp, #16] + 8002318: e018 b.n 800234c <_printf_i+0xd4> + 800231a: 6806 ldr r6, [r0, #0] + 800231c: 601a str r2, [r3, #0] + 800231e: 0649 lsls r1, r1, #25 + 8002320: d5f1 bpl.n 8002306 <_printf_i+0x8e> + 8002322: b236 sxth r6, r6 + 8002324: e7ef b.n 8002306 <_printf_i+0x8e> + 8002326: 6808 ldr r0, [r1, #0] + 8002328: 6819 ldr r1, [r3, #0] + 800232a: c940 ldmia r1!, {r6} + 800232c: 0605 lsls r5, r0, #24 + 800232e: d402 bmi.n 8002336 <_printf_i+0xbe> + 8002330: 0640 lsls r0, r0, #25 + 8002332: d500 bpl.n 8002336 <_printf_i+0xbe> + 8002334: b2b6 uxth r6, r6 + 8002336: 6019 str r1, [r3, #0] + 8002338: 4b53 ldr r3, [pc, #332] @ (8002488 <_printf_i+0x210>) + 800233a: 270a movs r7, #10 + 800233c: 9304 str r3, [sp, #16] + 800233e: 2a6f cmp r2, #111 @ 0x6f + 8002340: d100 bne.n 8002344 <_printf_i+0xcc> + 8002342: 3f02 subs r7, #2 + 8002344: 0023 movs r3, r4 + 8002346: 2200 movs r2, #0 + 8002348: 3343 adds r3, #67 @ 0x43 + 800234a: 701a strb r2, [r3, #0] + 800234c: 6863 ldr r3, [r4, #4] + 800234e: 60a3 str r3, [r4, #8] + 8002350: 2b00 cmp r3, #0 + 8002352: db06 blt.n 8002362 <_printf_i+0xea> + 8002354: 2104 movs r1, #4 + 8002356: 6822 ldr r2, [r4, #0] + 8002358: 9d03 ldr r5, [sp, #12] + 800235a: 438a bics r2, r1 + 800235c: 6022 str r2, [r4, #0] + 800235e: 4333 orrs r3, r6 + 8002360: d00c beq.n 800237c <_printf_i+0x104> + 8002362: 9d03 ldr r5, [sp, #12] + 8002364: 0030 movs r0, r6 + 8002366: 0039 movs r1, r7 + 8002368: f7fd ff5e bl 8000228 <__aeabi_uidivmod> + 800236c: 9b04 ldr r3, [sp, #16] + 800236e: 3d01 subs r5, #1 + 8002370: 5c5b ldrb r3, [r3, r1] + 8002372: 702b strb r3, [r5, #0] + 8002374: 0033 movs r3, r6 + 8002376: 0006 movs r6, r0 + 8002378: 429f cmp r7, r3 + 800237a: d9f3 bls.n 8002364 <_printf_i+0xec> + 800237c: 2f08 cmp r7, #8 + 800237e: d109 bne.n 8002394 <_printf_i+0x11c> + 8002380: 6823 ldr r3, [r4, #0] + 8002382: 07db lsls r3, r3, #31 + 8002384: d506 bpl.n 8002394 <_printf_i+0x11c> + 8002386: 6862 ldr r2, [r4, #4] + 8002388: 6923 ldr r3, [r4, #16] + 800238a: 429a cmp r2, r3 + 800238c: dc02 bgt.n 8002394 <_printf_i+0x11c> + 800238e: 2330 movs r3, #48 @ 0x30 + 8002390: 3d01 subs r5, #1 + 8002392: 702b strb r3, [r5, #0] + 8002394: 9b03 ldr r3, [sp, #12] + 8002396: 1b5b subs r3, r3, r5 + 8002398: 6123 str r3, [r4, #16] + 800239a: 9b07 ldr r3, [sp, #28] + 800239c: 0021 movs r1, r4 + 800239e: 9300 str r3, [sp, #0] + 80023a0: 9805 ldr r0, [sp, #20] + 80023a2: 9b06 ldr r3, [sp, #24] + 80023a4: aa09 add r2, sp, #36 @ 0x24 + 80023a6: f7ff fef7 bl 8002198 <_printf_common> + 80023aa: 3001 adds r0, #1 + 80023ac: d148 bne.n 8002440 <_printf_i+0x1c8> + 80023ae: 2001 movs r0, #1 + 80023b0: 4240 negs r0, r0 + 80023b2: b00b add sp, #44 @ 0x2c + 80023b4: bdf0 pop {r4, r5, r6, r7, pc} + 80023b6: 2220 movs r2, #32 + 80023b8: 6809 ldr r1, [r1, #0] + 80023ba: 430a orrs r2, r1 + 80023bc: 6022 str r2, [r4, #0] + 80023be: 2278 movs r2, #120 @ 0x78 + 80023c0: 4932 ldr r1, [pc, #200] @ (800248c <_printf_i+0x214>) + 80023c2: 9104 str r1, [sp, #16] + 80023c4: 0021 movs r1, r4 + 80023c6: 3145 adds r1, #69 @ 0x45 + 80023c8: 700a strb r2, [r1, #0] + 80023ca: 6819 ldr r1, [r3, #0] + 80023cc: 6822 ldr r2, [r4, #0] + 80023ce: c940 ldmia r1!, {r6} + 80023d0: 0610 lsls r0, r2, #24 + 80023d2: d402 bmi.n 80023da <_printf_i+0x162> + 80023d4: 0650 lsls r0, r2, #25 + 80023d6: d500 bpl.n 80023da <_printf_i+0x162> + 80023d8: b2b6 uxth r6, r6 + 80023da: 6019 str r1, [r3, #0] + 80023dc: 07d3 lsls r3, r2, #31 + 80023de: d502 bpl.n 80023e6 <_printf_i+0x16e> + 80023e0: 2320 movs r3, #32 + 80023e2: 4313 orrs r3, r2 + 80023e4: 6023 str r3, [r4, #0] + 80023e6: 2e00 cmp r6, #0 + 80023e8: d001 beq.n 80023ee <_printf_i+0x176> + 80023ea: 2710 movs r7, #16 + 80023ec: e7aa b.n 8002344 <_printf_i+0xcc> + 80023ee: 2220 movs r2, #32 + 80023f0: 6823 ldr r3, [r4, #0] + 80023f2: 4393 bics r3, r2 + 80023f4: 6023 str r3, [r4, #0] + 80023f6: e7f8 b.n 80023ea <_printf_i+0x172> + 80023f8: 681a ldr r2, [r3, #0] + 80023fa: 680d ldr r5, [r1, #0] + 80023fc: 1d10 adds r0, r2, #4 + 80023fe: 6949 ldr r1, [r1, #20] + 8002400: 6018 str r0, [r3, #0] + 8002402: 6813 ldr r3, [r2, #0] + 8002404: 062e lsls r6, r5, #24 + 8002406: d501 bpl.n 800240c <_printf_i+0x194> + 8002408: 6019 str r1, [r3, #0] + 800240a: e002 b.n 8002412 <_printf_i+0x19a> + 800240c: 066d lsls r5, r5, #25 + 800240e: d5fb bpl.n 8002408 <_printf_i+0x190> + 8002410: 8019 strh r1, [r3, #0] + 8002412: 2300 movs r3, #0 + 8002414: 9d03 ldr r5, [sp, #12] + 8002416: 6123 str r3, [r4, #16] + 8002418: e7bf b.n 800239a <_printf_i+0x122> + 800241a: 681a ldr r2, [r3, #0] + 800241c: 1d11 adds r1, r2, #4 + 800241e: 6019 str r1, [r3, #0] + 8002420: 6815 ldr r5, [r2, #0] + 8002422: 2100 movs r1, #0 + 8002424: 0028 movs r0, r5 + 8002426: 6862 ldr r2, [r4, #4] + 8002428: f000 f986 bl 8002738 + 800242c: 2800 cmp r0, #0 + 800242e: d001 beq.n 8002434 <_printf_i+0x1bc> + 8002430: 1b40 subs r0, r0, r5 + 8002432: 6060 str r0, [r4, #4] + 8002434: 6863 ldr r3, [r4, #4] + 8002436: 6123 str r3, [r4, #16] + 8002438: 2300 movs r3, #0 + 800243a: 9a03 ldr r2, [sp, #12] + 800243c: 7013 strb r3, [r2, #0] + 800243e: e7ac b.n 800239a <_printf_i+0x122> + 8002440: 002a movs r2, r5 + 8002442: 6923 ldr r3, [r4, #16] + 8002444: 9906 ldr r1, [sp, #24] + 8002446: 9805 ldr r0, [sp, #20] + 8002448: 9d07 ldr r5, [sp, #28] + 800244a: 47a8 blx r5 + 800244c: 3001 adds r0, #1 + 800244e: d0ae beq.n 80023ae <_printf_i+0x136> + 8002450: 6823 ldr r3, [r4, #0] + 8002452: 079b lsls r3, r3, #30 + 8002454: d415 bmi.n 8002482 <_printf_i+0x20a> + 8002456: 9b09 ldr r3, [sp, #36] @ 0x24 + 8002458: 68e0 ldr r0, [r4, #12] + 800245a: 4298 cmp r0, r3 + 800245c: daa9 bge.n 80023b2 <_printf_i+0x13a> + 800245e: 0018 movs r0, r3 + 8002460: e7a7 b.n 80023b2 <_printf_i+0x13a> + 8002462: 0022 movs r2, r4 + 8002464: 2301 movs r3, #1 + 8002466: 9906 ldr r1, [sp, #24] + 8002468: 9805 ldr r0, [sp, #20] + 800246a: 9e07 ldr r6, [sp, #28] + 800246c: 3219 adds r2, #25 + 800246e: 47b0 blx r6 + 8002470: 3001 adds r0, #1 + 8002472: d09c beq.n 80023ae <_printf_i+0x136> + 8002474: 3501 adds r5, #1 + 8002476: 68e3 ldr r3, [r4, #12] + 8002478: 9a09 ldr r2, [sp, #36] @ 0x24 + 800247a: 1a9b subs r3, r3, r2 + 800247c: 42ab cmp r3, r5 + 800247e: dcf0 bgt.n 8002462 <_printf_i+0x1ea> + 8002480: e7e9 b.n 8002456 <_printf_i+0x1de> + 8002482: 2500 movs r5, #0 + 8002484: e7f7 b.n 8002476 <_printf_i+0x1fe> + 8002486: 46c0 nop @ (mov r8, r8) + 8002488: 0800298a .word 0x0800298a + 800248c: 0800299b .word 0x0800299b + +08002490 <__sflush_r>: + 8002490: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8002492: 220c movs r2, #12 + 8002494: 5e8b ldrsh r3, [r1, r2] + 8002496: 0005 movs r5, r0 + 8002498: 000c movs r4, r1 + 800249a: 071a lsls r2, r3, #28 + 800249c: d456 bmi.n 800254c <__sflush_r+0xbc> + 800249e: 684a ldr r2, [r1, #4] + 80024a0: 2a00 cmp r2, #0 + 80024a2: dc02 bgt.n 80024aa <__sflush_r+0x1a> + 80024a4: 6c0a ldr r2, [r1, #64] @ 0x40 + 80024a6: 2a00 cmp r2, #0 + 80024a8: dd4e ble.n 8002548 <__sflush_r+0xb8> + 80024aa: 6ae7 ldr r7, [r4, #44] @ 0x2c + 80024ac: 2f00 cmp r7, #0 + 80024ae: d04b beq.n 8002548 <__sflush_r+0xb8> + 80024b0: 2200 movs r2, #0 + 80024b2: 2080 movs r0, #128 @ 0x80 + 80024b4: 682e ldr r6, [r5, #0] + 80024b6: 602a str r2, [r5, #0] + 80024b8: 001a movs r2, r3 + 80024ba: 0140 lsls r0, r0, #5 + 80024bc: 6a21 ldr r1, [r4, #32] + 80024be: 4002 ands r2, r0 + 80024c0: 4203 tst r3, r0 + 80024c2: d033 beq.n 800252c <__sflush_r+0x9c> + 80024c4: 6d62 ldr r2, [r4, #84] @ 0x54 + 80024c6: 89a3 ldrh r3, [r4, #12] + 80024c8: 075b lsls r3, r3, #29 + 80024ca: d506 bpl.n 80024da <__sflush_r+0x4a> + 80024cc: 6863 ldr r3, [r4, #4] + 80024ce: 1ad2 subs r2, r2, r3 + 80024d0: 6b63 ldr r3, [r4, #52] @ 0x34 + 80024d2: 2b00 cmp r3, #0 + 80024d4: d001 beq.n 80024da <__sflush_r+0x4a> + 80024d6: 6c23 ldr r3, [r4, #64] @ 0x40 + 80024d8: 1ad2 subs r2, r2, r3 + 80024da: 2300 movs r3, #0 + 80024dc: 0028 movs r0, r5 + 80024de: 6ae7 ldr r7, [r4, #44] @ 0x2c + 80024e0: 6a21 ldr r1, [r4, #32] + 80024e2: 47b8 blx r7 + 80024e4: 89a2 ldrh r2, [r4, #12] + 80024e6: 1c43 adds r3, r0, #1 + 80024e8: d106 bne.n 80024f8 <__sflush_r+0x68> + 80024ea: 6829 ldr r1, [r5, #0] + 80024ec: 291d cmp r1, #29 + 80024ee: d846 bhi.n 800257e <__sflush_r+0xee> + 80024f0: 4b29 ldr r3, [pc, #164] @ (8002598 <__sflush_r+0x108>) + 80024f2: 40cb lsrs r3, r1 + 80024f4: 07db lsls r3, r3, #31 + 80024f6: d542 bpl.n 800257e <__sflush_r+0xee> + 80024f8: 2300 movs r3, #0 + 80024fa: 6063 str r3, [r4, #4] + 80024fc: 6923 ldr r3, [r4, #16] + 80024fe: 6023 str r3, [r4, #0] + 8002500: 04d2 lsls r2, r2, #19 + 8002502: d505 bpl.n 8002510 <__sflush_r+0x80> + 8002504: 1c43 adds r3, r0, #1 + 8002506: d102 bne.n 800250e <__sflush_r+0x7e> + 8002508: 682b ldr r3, [r5, #0] + 800250a: 2b00 cmp r3, #0 + 800250c: d100 bne.n 8002510 <__sflush_r+0x80> + 800250e: 6560 str r0, [r4, #84] @ 0x54 + 8002510: 6b61 ldr r1, [r4, #52] @ 0x34 + 8002512: 602e str r6, [r5, #0] + 8002514: 2900 cmp r1, #0 + 8002516: d017 beq.n 8002548 <__sflush_r+0xb8> + 8002518: 0023 movs r3, r4 + 800251a: 3344 adds r3, #68 @ 0x44 + 800251c: 4299 cmp r1, r3 + 800251e: d002 beq.n 8002526 <__sflush_r+0x96> + 8002520: 0028 movs r0, r5 + 8002522: f7ff fbf9 bl 8001d18 <_free_r> + 8002526: 2300 movs r3, #0 + 8002528: 6363 str r3, [r4, #52] @ 0x34 + 800252a: e00d b.n 8002548 <__sflush_r+0xb8> + 800252c: 2301 movs r3, #1 + 800252e: 0028 movs r0, r5 + 8002530: 47b8 blx r7 + 8002532: 0002 movs r2, r0 + 8002534: 1c43 adds r3, r0, #1 + 8002536: d1c6 bne.n 80024c6 <__sflush_r+0x36> + 8002538: 682b ldr r3, [r5, #0] + 800253a: 2b00 cmp r3, #0 + 800253c: d0c3 beq.n 80024c6 <__sflush_r+0x36> + 800253e: 2b1d cmp r3, #29 + 8002540: d001 beq.n 8002546 <__sflush_r+0xb6> + 8002542: 2b16 cmp r3, #22 + 8002544: d11a bne.n 800257c <__sflush_r+0xec> + 8002546: 602e str r6, [r5, #0] + 8002548: 2000 movs r0, #0 + 800254a: e01e b.n 800258a <__sflush_r+0xfa> + 800254c: 690e ldr r6, [r1, #16] + 800254e: 2e00 cmp r6, #0 + 8002550: d0fa beq.n 8002548 <__sflush_r+0xb8> + 8002552: 680f ldr r7, [r1, #0] + 8002554: 600e str r6, [r1, #0] + 8002556: 1bba subs r2, r7, r6 + 8002558: 9201 str r2, [sp, #4] + 800255a: 2200 movs r2, #0 + 800255c: 079b lsls r3, r3, #30 + 800255e: d100 bne.n 8002562 <__sflush_r+0xd2> + 8002560: 694a ldr r2, [r1, #20] + 8002562: 60a2 str r2, [r4, #8] + 8002564: 9b01 ldr r3, [sp, #4] + 8002566: 2b00 cmp r3, #0 + 8002568: ddee ble.n 8002548 <__sflush_r+0xb8> + 800256a: 6aa3 ldr r3, [r4, #40] @ 0x28 + 800256c: 0032 movs r2, r6 + 800256e: 001f movs r7, r3 + 8002570: 0028 movs r0, r5 + 8002572: 9b01 ldr r3, [sp, #4] + 8002574: 6a21 ldr r1, [r4, #32] + 8002576: 47b8 blx r7 + 8002578: 2800 cmp r0, #0 + 800257a: dc07 bgt.n 800258c <__sflush_r+0xfc> + 800257c: 89a2 ldrh r2, [r4, #12] + 800257e: 2340 movs r3, #64 @ 0x40 + 8002580: 2001 movs r0, #1 + 8002582: 4313 orrs r3, r2 + 8002584: b21b sxth r3, r3 + 8002586: 81a3 strh r3, [r4, #12] + 8002588: 4240 negs r0, r0 + 800258a: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + 800258c: 9b01 ldr r3, [sp, #4] + 800258e: 1836 adds r6, r6, r0 + 8002590: 1a1b subs r3, r3, r0 + 8002592: 9301 str r3, [sp, #4] + 8002594: e7e6 b.n 8002564 <__sflush_r+0xd4> + 8002596: 46c0 nop @ (mov r8, r8) + 8002598: 20400001 .word 0x20400001 + +0800259c <_fflush_r>: + 800259c: 690b ldr r3, [r1, #16] + 800259e: b570 push {r4, r5, r6, lr} + 80025a0: 0005 movs r5, r0 + 80025a2: 000c movs r4, r1 + 80025a4: 2b00 cmp r3, #0 + 80025a6: d102 bne.n 80025ae <_fflush_r+0x12> + 80025a8: 2500 movs r5, #0 + 80025aa: 0028 movs r0, r5 + 80025ac: bd70 pop {r4, r5, r6, pc} + 80025ae: 2800 cmp r0, #0 + 80025b0: d004 beq.n 80025bc <_fflush_r+0x20> + 80025b2: 6a03 ldr r3, [r0, #32] + 80025b4: 2b00 cmp r3, #0 + 80025b6: d101 bne.n 80025bc <_fflush_r+0x20> + 80025b8: f7ff f99a bl 80018f0 <__sinit> + 80025bc: 220c movs r2, #12 + 80025be: 5ea3 ldrsh r3, [r4, r2] + 80025c0: 2b00 cmp r3, #0 + 80025c2: d0f1 beq.n 80025a8 <_fflush_r+0xc> + 80025c4: 6e62 ldr r2, [r4, #100] @ 0x64 + 80025c6: 07d2 lsls r2, r2, #31 + 80025c8: d404 bmi.n 80025d4 <_fflush_r+0x38> + 80025ca: 059b lsls r3, r3, #22 + 80025cc: d402 bmi.n 80025d4 <_fflush_r+0x38> + 80025ce: 6da0 ldr r0, [r4, #88] @ 0x58 + 80025d0: f7ff fb9f bl 8001d12 <__retarget_lock_acquire_recursive> + 80025d4: 0028 movs r0, r5 + 80025d6: 0021 movs r1, r4 + 80025d8: f7ff ff5a bl 8002490 <__sflush_r> + 80025dc: 6e63 ldr r3, [r4, #100] @ 0x64 + 80025de: 0005 movs r5, r0 + 80025e0: 07db lsls r3, r3, #31 + 80025e2: d4e2 bmi.n 80025aa <_fflush_r+0xe> + 80025e4: 89a3 ldrh r3, [r4, #12] + 80025e6: 059b lsls r3, r3, #22 + 80025e8: d4df bmi.n 80025aa <_fflush_r+0xe> + 80025ea: 6da0 ldr r0, [r4, #88] @ 0x58 + 80025ec: f7ff fb92 bl 8001d14 <__retarget_lock_release_recursive> + 80025f0: e7db b.n 80025aa <_fflush_r+0xe> + ... + +080025f4 <__swhatbuf_r>: + 80025f4: b570 push {r4, r5, r6, lr} + 80025f6: 000e movs r6, r1 + 80025f8: 001d movs r5, r3 + 80025fa: 230e movs r3, #14 + 80025fc: 5ec9 ldrsh r1, [r1, r3] + 80025fe: 0014 movs r4, r2 + 8002600: b096 sub sp, #88 @ 0x58 + 8002602: 2900 cmp r1, #0 + 8002604: da0c bge.n 8002620 <__swhatbuf_r+0x2c> + 8002606: 89b2 ldrh r2, [r6, #12] + 8002608: 2380 movs r3, #128 @ 0x80 + 800260a: 0011 movs r1, r2 + 800260c: 4019 ands r1, r3 + 800260e: 421a tst r2, r3 + 8002610: d114 bne.n 800263c <__swhatbuf_r+0x48> + 8002612: 2380 movs r3, #128 @ 0x80 + 8002614: 00db lsls r3, r3, #3 + 8002616: 2000 movs r0, #0 + 8002618: 6029 str r1, [r5, #0] + 800261a: 6023 str r3, [r4, #0] + 800261c: b016 add sp, #88 @ 0x58 + 800261e: bd70 pop {r4, r5, r6, pc} + 8002620: 466a mov r2, sp + 8002622: f000 f853 bl 80026cc <_fstat_r> + 8002626: 2800 cmp r0, #0 + 8002628: dbed blt.n 8002606 <__swhatbuf_r+0x12> + 800262a: 23f0 movs r3, #240 @ 0xf0 + 800262c: 9901 ldr r1, [sp, #4] + 800262e: 021b lsls r3, r3, #8 + 8002630: 4019 ands r1, r3 + 8002632: 4b04 ldr r3, [pc, #16] @ (8002644 <__swhatbuf_r+0x50>) + 8002634: 18c9 adds r1, r1, r3 + 8002636: 424b negs r3, r1 + 8002638: 4159 adcs r1, r3 + 800263a: e7ea b.n 8002612 <__swhatbuf_r+0x1e> + 800263c: 2100 movs r1, #0 + 800263e: 2340 movs r3, #64 @ 0x40 + 8002640: e7e9 b.n 8002616 <__swhatbuf_r+0x22> + 8002642: 46c0 nop @ (mov r8, r8) + 8002644: ffffe000 .word 0xffffe000 + +08002648 <__smakebuf_r>: + 8002648: b5f0 push {r4, r5, r6, r7, lr} + 800264a: 2602 movs r6, #2 + 800264c: 898b ldrh r3, [r1, #12] + 800264e: 0005 movs r5, r0 + 8002650: 000c movs r4, r1 + 8002652: b085 sub sp, #20 + 8002654: 4233 tst r3, r6 + 8002656: d007 beq.n 8002668 <__smakebuf_r+0x20> + 8002658: 0023 movs r3, r4 + 800265a: 3347 adds r3, #71 @ 0x47 + 800265c: 6023 str r3, [r4, #0] + 800265e: 6123 str r3, [r4, #16] + 8002660: 2301 movs r3, #1 + 8002662: 6163 str r3, [r4, #20] + 8002664: b005 add sp, #20 + 8002666: bdf0 pop {r4, r5, r6, r7, pc} + 8002668: ab03 add r3, sp, #12 + 800266a: aa02 add r2, sp, #8 + 800266c: f7ff ffc2 bl 80025f4 <__swhatbuf_r> + 8002670: 9f02 ldr r7, [sp, #8] + 8002672: 9001 str r0, [sp, #4] + 8002674: 0039 movs r1, r7 + 8002676: 0028 movs r0, r5 + 8002678: f7ff fbba bl 8001df0 <_malloc_r> + 800267c: 2800 cmp r0, #0 + 800267e: d108 bne.n 8002692 <__smakebuf_r+0x4a> + 8002680: 220c movs r2, #12 + 8002682: 5ea3 ldrsh r3, [r4, r2] + 8002684: 059a lsls r2, r3, #22 + 8002686: d4ed bmi.n 8002664 <__smakebuf_r+0x1c> + 8002688: 2203 movs r2, #3 + 800268a: 4393 bics r3, r2 + 800268c: 431e orrs r6, r3 + 800268e: 81a6 strh r6, [r4, #12] + 8002690: e7e2 b.n 8002658 <__smakebuf_r+0x10> + 8002692: 2380 movs r3, #128 @ 0x80 + 8002694: 89a2 ldrh r2, [r4, #12] + 8002696: 6020 str r0, [r4, #0] + 8002698: 4313 orrs r3, r2 + 800269a: 81a3 strh r3, [r4, #12] + 800269c: 9b03 ldr r3, [sp, #12] + 800269e: 6120 str r0, [r4, #16] + 80026a0: 6167 str r7, [r4, #20] + 80026a2: 2b00 cmp r3, #0 + 80026a4: d00c beq.n 80026c0 <__smakebuf_r+0x78> + 80026a6: 0028 movs r0, r5 + 80026a8: 230e movs r3, #14 + 80026aa: 5ee1 ldrsh r1, [r4, r3] + 80026ac: f000 f820 bl 80026f0 <_isatty_r> + 80026b0: 2800 cmp r0, #0 + 80026b2: d005 beq.n 80026c0 <__smakebuf_r+0x78> + 80026b4: 2303 movs r3, #3 + 80026b6: 89a2 ldrh r2, [r4, #12] + 80026b8: 439a bics r2, r3 + 80026ba: 3b02 subs r3, #2 + 80026bc: 4313 orrs r3, r2 + 80026be: 81a3 strh r3, [r4, #12] + 80026c0: 89a3 ldrh r3, [r4, #12] + 80026c2: 9a01 ldr r2, [sp, #4] + 80026c4: 4313 orrs r3, r2 + 80026c6: 81a3 strh r3, [r4, #12] + 80026c8: e7cc b.n 8002664 <__smakebuf_r+0x1c> + ... + +080026cc <_fstat_r>: + 80026cc: 2300 movs r3, #0 + 80026ce: b570 push {r4, r5, r6, lr} + 80026d0: 4d06 ldr r5, [pc, #24] @ (80026ec <_fstat_r+0x20>) + 80026d2: 0004 movs r4, r0 + 80026d4: 0008 movs r0, r1 + 80026d6: 0011 movs r1, r2 + 80026d8: 602b str r3, [r5, #0] + 80026da: f7fd fdf2 bl 80002c2 <_fstat> + 80026de: 1c43 adds r3, r0, #1 + 80026e0: d103 bne.n 80026ea <_fstat_r+0x1e> + 80026e2: 682b ldr r3, [r5, #0] + 80026e4: 2b00 cmp r3, #0 + 80026e6: d000 beq.n 80026ea <_fstat_r+0x1e> + 80026e8: 6023 str r3, [r4, #0] + 80026ea: bd70 pop {r4, r5, r6, pc} + 80026ec: 2000028c .word 0x2000028c + +080026f0 <_isatty_r>: + 80026f0: 2300 movs r3, #0 + 80026f2: b570 push {r4, r5, r6, lr} + 80026f4: 4d06 ldr r5, [pc, #24] @ (8002710 <_isatty_r+0x20>) + 80026f6: 0004 movs r4, r0 + 80026f8: 0008 movs r0, r1 + 80026fa: 602b str r3, [r5, #0] + 80026fc: f7fd fde6 bl 80002cc <_isatty> + 8002700: 1c43 adds r3, r0, #1 + 8002702: d103 bne.n 800270c <_isatty_r+0x1c> + 8002704: 682b ldr r3, [r5, #0] + 8002706: 2b00 cmp r3, #0 + 8002708: d000 beq.n 800270c <_isatty_r+0x1c> + 800270a: 6023 str r3, [r4, #0] + 800270c: bd70 pop {r4, r5, r6, pc} + 800270e: 46c0 nop @ (mov r8, r8) + 8002710: 2000028c .word 0x2000028c + +08002714 <_sbrk_r>: + 8002714: 2300 movs r3, #0 + 8002716: b570 push {r4, r5, r6, lr} + 8002718: 4d06 ldr r5, [pc, #24] @ (8002734 <_sbrk_r+0x20>) + 800271a: 0004 movs r4, r0 + 800271c: 0008 movs r0, r1 + 800271e: 602b str r3, [r5, #0] + 8002720: f7fd fdd8 bl 80002d4 <_sbrk> + 8002724: 1c43 adds r3, r0, #1 + 8002726: d103 bne.n 8002730 <_sbrk_r+0x1c> + 8002728: 682b ldr r3, [r5, #0] + 800272a: 2b00 cmp r3, #0 + 800272c: d000 beq.n 8002730 <_sbrk_r+0x1c> + 800272e: 6023 str r3, [r4, #0] + 8002730: bd70 pop {r4, r5, r6, pc} + 8002732: 46c0 nop @ (mov r8, r8) + 8002734: 2000028c .word 0x2000028c + +08002738 : + 8002738: b2c9 uxtb r1, r1 + 800273a: 1882 adds r2, r0, r2 + 800273c: 4290 cmp r0, r2 + 800273e: d101 bne.n 8002744 + 8002740: 2000 movs r0, #0 + 8002742: 4770 bx lr + 8002744: 7803 ldrb r3, [r0, #0] + 8002746: 428b cmp r3, r1 + 8002748: d0fb beq.n 8002742 + 800274a: 3001 adds r0, #1 + 800274c: e7f6 b.n 800273c + ... + +08002750 <_init>: + 8002750: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002752: 46c0 nop @ (mov r8, r8) + 8002754: bcf8 pop {r3, r4, r5, r6, r7} + 8002756: bc08 pop {r3} + 8002758: 469e mov lr, r3 + 800275a: 4770 bx lr + +0800275c <_fini>: + 800275c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800275e: 46c0 nop @ (mov r8, r8) + 8002760: bcf8 pop {r3, r4, r5, r6, r7} + 8002762: bc08 pop {r3} + 8002764: 469e mov lr, r3 + 8002766: 4770 bx lr Index: /trunk/firmware_v3/STM32CubeIDE/Debug/firmware_v2.map =================================================================== --- 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C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00003000 xrw +FLASH 0x08000000 0x00004000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD ./Application/User/Core/adc.o +LOAD ./Application/User/Core/dma.o +LOAD ./Application/User/Core/gpio.o +LOAD ./Application/User/Core/main.o +LOAD ./Application/User/Core/stm32c0xx_hal_msp.o +LOAD ./Application/User/Core/stm32c0xx_it.o +LOAD ./Application/User/Core/syscalls.o +LOAD ./Application/User/Core/sysmem.o +LOAD ./Application/User/Core/tim.o +LOAD ./Application/User/Core/usart.o +LOAD ./Application/User/Startup/startup_stm32c031k4tx.o +LOAD ./Drivers/CMSIS/system_stm32c0xx.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o +LOAD ./src/button.o +LOAD ./src/buzzer.o +LOAD ./src/leds.o +LOAD ./src/main.o +LOAD ./src/mode_mainswitch.o +LOAD ./src/mode_secondaryprotection.o +LOAD ./src/modeswitch.o +LOAD ./src/relais.o +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtend.o +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + 0x20003000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0xc0 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0xc0 ./Application/User/Startup/startup_stm32c031k4tx.o + 0x08000000 g_pfnVectors + 0x080000c0 . = ALIGN (0x4) + +.text 0x080000c0 0x2c7c + 0x080000c0 . = ALIGN (0x4) + *(.text) + .text 0x080000c0 0x48 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x08000108 0x114 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + 0x08000108 __aeabi_uidiv + 0x08000108 __udivsi3 + 0x08000214 __aeabi_uidivmod + .text 0x0800021c 0x1d4 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + 0x0800021c __divsi3 + 0x0800021c __aeabi_idiv + 0x080003e8 __aeabi_idivmod + .text 0x080003f0 0x4 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + 0x080003f0 __aeabi_idiv0 + 0x080003f0 __aeabi_ldiv0 + *(.text*) + .text.MX_ADC1_Init + 0x080003f4 0xf4 ./Application/User/Core/adc.o + 0x080003f4 MX_ADC1_Init + .text.HAL_ADC_MspInit + 0x080004e8 0xbc ./Application/User/Core/adc.o + 0x080004e8 HAL_ADC_MspInit + .text.MX_DMA_Init + 0x080005a4 0x30 ./Application/User/Core/dma.o + 0x080005a4 MX_DMA_Init + .text.MX_GPIO_Init + 0x080005d4 0xe8 ./Application/User/Core/gpio.o + 0x080005d4 MX_GPIO_Init + .text.Error_Handler + 0x080006bc 0x4 ./Application/User/Core/main.o + 0x080006bc Error_Handler + .text.SystemClock_Config + 0x080006c0 0x68 ./Application/User/Core/main.o + 0x080006c0 SystemClock_Config + .text.main 0x08000728 0x24 ./Application/User/Core/main.o + 0x08000728 main + .text.HAL_MspInit + 0x0800074c 0x30 ./Application/User/Core/stm32c0xx_hal_msp.o + 0x0800074c HAL_MspInit + .text.NMI_Handler + 0x0800077c 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x0800077c NMI_Handler + .text.HardFault_Handler + 0x0800077e 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x0800077e HardFault_Handler + .text.SVC_Handler + 0x08000780 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x08000780 SVC_Handler + .text.PendSV_Handler + 0x08000782 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x08000782 PendSV_Handler + .text.SysTick_Handler + 0x08000784 0x8 ./Application/User/Core/stm32c0xx_it.o + 0x08000784 SysTick_Handler + .text.DMA1_Channel1_IRQHandler + 0x0800078c 0x10 ./Application/User/Core/stm32c0xx_it.o + 0x0800078c DMA1_Channel1_IRQHandler + .text.TIM16_IRQHandler + 0x0800079c 0x10 ./Application/User/Core/stm32c0xx_it.o + 0x0800079c TIM16_IRQHandler + .text.HAL_TIM_IC_CaptureCallback + 0x080007ac 0x48 ./Application/User/Core/stm32c0xx_it.o + 0x080007ac HAL_TIM_IC_CaptureCallback + .text.HAL_TIM_PeriodElapsedCallback + 0x080007f4 0x2c ./Application/User/Core/stm32c0xx_it.o + 0x080007f4 HAL_TIM_PeriodElapsedCallback + .text.MX_TIM16_Init + 0x08000820 0x78 ./Application/User/Core/tim.o + 0x08000820 MX_TIM16_Init + .text.HAL_TIM_Base_MspInit + 0x08000898 0x94 ./Application/User/Core/tim.o + 0x08000898 HAL_TIM_Base_MspInit + .text.HAL_TIM_MspPostInit + 0x0800092c 0x60 ./Application/User/Core/tim.o + 0x0800092c HAL_TIM_MspPostInit + .text.MX_TIM17_Init + 0x0800098c 0xb4 ./Application/User/Core/tim.o + 0x0800098c MX_TIM17_Init + .text.MX_USART1_UART_Init + 0x08000a40 0x70 ./Application/User/Core/usart.o + 0x08000a40 MX_USART1_UART_Init + .text.HAL_UART_MspInit + 0x08000ab0 0xa0 ./Application/User/Core/usart.o + 0x08000ab0 HAL_UART_MspInit + .text.Reset_Handler + 0x08000b50 0x50 ./Application/User/Startup/startup_stm32c031k4tx.o + 0x08000b50 Reset_Handler + .text.Default_Handler + 0x08000ba0 0x2 ./Application/User/Startup/startup_stm32c031k4tx.o + 0x08000ba0 TIM1_CC_IRQHandler + 0x08000ba0 I2C1_IRQHandler + 0x08000ba0 DMAMUX1_IRQHandler + 0x08000ba0 SPI1_IRQHandler + 0x08000ba0 EXTI2_3_IRQHandler + 0x08000ba0 ADC1_IRQHandler + 0x08000ba0 TIM17_IRQHandler + 0x08000ba0 RTC_IRQHandler + 0x08000ba0 TIM3_IRQHandler + 0x08000ba0 EXTI4_15_IRQHandler + 0x08000ba0 RCC_IRQHandler + 0x08000ba0 Default_Handler + 0x08000ba0 TIM14_IRQHandler + 0x08000ba0 EXTI0_1_IRQHandler + 0x08000ba0 WWDG_IRQHandler + 0x08000ba0 DMA1_Channel2_3_IRQHandler + 0x08000ba0 USART2_IRQHandler + 0x08000ba0 FLASH_IRQHandler + 0x08000ba0 USART1_IRQHandler + 0x08000ba0 TIM1_BRK_UP_TRG_COM_IRQHandler + *fill* 0x08000ba2 0x2 + .text.SystemInit + 0x08000ba4 0x10 ./Drivers/CMSIS/system_stm32c0xx.o + 0x08000ba4 SystemInit + .text.HAL_InitTick + 0x08000bb4 0x58 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000bb4 HAL_InitTick + .text.HAL_Init + 0x08000c0c 0x18 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000c0c HAL_Init + .text.HAL_IncTick + 0x08000c24 0x18 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000c24 HAL_IncTick + .text.HAL_GetTick + 0x08000c3c 0xc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000c3c HAL_GetTick + .text.HAL_ADC_Init + 0x08000c48 0x240 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + 0x08000c48 HAL_ADC_Init + .text.HAL_ADC_ConfigChannel + 0x08000e88 0x280 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + 0x08000e88 HAL_ADC_ConfigChannel + .text.__NVIC_SetPriority + 0x08001108 0x60 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .text.SysTick_Config + 0x08001168 0x38 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .text.HAL_NVIC_SetPriority + 0x080011a0 0x8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + 0x080011a0 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x080011a8 0x18 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + 0x080011a8 HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x080011c0 0x8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + 0x080011c0 HAL_SYSTICK_Config + .text.DMA_CalcDMAMUXChannelBaseAndMask + 0x080011c8 0x38 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .text.DMA_CalcDMAMUXRequestGenBaseAndMask + 0x08001200 0x28 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .text.HAL_DMA_Init + 0x08001228 0xb0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + 0x08001228 HAL_DMA_Init + .text.HAL_DMA_IRQHandler + 0x080012d8 0xcc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + 0x080012d8 HAL_DMA_IRQHandler + .text.HAL_GPIO_Init + 0x080013a4 0x1bc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + 0x080013a4 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x08001560 0xc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + 0x08001560 HAL_GPIO_WritePin + .text.HAL_RCC_OscConfig + 0x0800156c 0x2bc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + 0x0800156c HAL_RCC_OscConfig + .text.HAL_RCC_GetSysClockFreq + 0x08001828 0x60 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + 0x08001828 HAL_RCC_GetSysClockFreq + .text.HAL_RCC_ClockConfig + 0x08001888 0x184 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + 0x08001888 HAL_RCC_ClockConfig + .text.HAL_RCC_GetHCLKFreq + 0x08001a0c 0x30 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + 0x08001a0c HAL_RCC_GetHCLKFreq + .text.HAL_RCC_GetPCLK1Freq + 0x08001a3c 0x28 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + 0x08001a3c HAL_RCC_GetPCLK1Freq + .text.HAL_RCCEx_PeriphCLKConfig + 0x08001a64 0x134 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + 0x08001a64 HAL_RCCEx_PeriphCLKConfig + .text.TIM_OC1_SetConfig + 0x08001b98 0x80 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC3_SetConfig + 0x08001c18 0x84 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x08001c9c 0x68 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC5_SetConfig + 0x08001d04 0x64 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC6_SetConfig + 0x08001d68 0x68 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_TI2_SetConfig + 0x08001dd0 0x38 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_TI3_SetConfig + 0x08001e08 0x40 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_TI4_SetConfig + 0x08001e48 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.HAL_TIM_PWM_MspInit + 0x08001e8c 0x2 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o 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./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .ARM.attributes + 0x0000032c 0x2c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .ARM.attributes + 0x00000358 0x2c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .ARM.attributes + 0x00000384 0x2c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .ARM.attributes + 0x000003b0 0x2c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + .ARM.attributes + 0x000003dc 0x2c C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x00000408 0x2c C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x00000434 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .ARM.attributes + 0x00000452 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + .ARM.attributes + 0x00000470 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000048e 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(firmware_v2.elf elf32-littlearm) +LOAD linker stubs +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a + +.debug_info 0x00000000 0x16ca6 + .debug_info 0x00000000 0xd82 ./Application/User/Core/adc.o + .debug_info 0x00000d82 0x30f ./Application/User/Core/dma.o + .debug_info 0x00001091 0x4b3 ./Application/User/Core/gpio.o + .debug_info 0x00001544 0x449 ./Application/User/Core/main.o + .debug_info 0x0000198d 0x217 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_info 0x00001ba4 0x8e7 ./Application/User/Core/stm32c0xx_it.o + .debug_info 0x0000248b 0x115a ./Application/User/Core/tim.o + .debug_info 0x000035e5 0xd04 ./Application/User/Core/usart.o + .debug_info 0x000042e9 0x30 ./Application/User/Startup/startup_stm32c031k4tx.o + .debug_info 0x00004319 0x37f ./Drivers/CMSIS/system_stm32c0xx.o + .debug_info 0x00004698 0x90b ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_info 0x00004fa3 0x226d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_info 0x00007210 0x9cf ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_info 0x00007bdf 0x9d4 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_info 0x000085b3 0x60b ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_info 0x00008bbe 0xb0d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_info 0x000096cb 0x613 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_info 0x00009cde 0x3e79 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_info 0x0000db57 0x1e93 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_info 0x0000f9ea 0x60e5 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_info 0x00015acf 0x11d7 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_abbrev 0x00000000 0x2dc2 + .debug_abbrev 0x00000000 0x215 ./Application/User/Core/adc.o + .debug_abbrev 0x00000215 0x12b ./Application/User/Core/dma.o + .debug_abbrev 0x00000340 0x180 ./Application/User/Core/gpio.o + .debug_abbrev 0x000004c0 0x1d2 ./Application/User/Core/main.o + .debug_abbrev 0x00000692 0xd6 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_abbrev 0x00000768 0x23f ./Application/User/Core/stm32c0xx_it.o + .debug_abbrev 0x000009a7 0x246 ./Application/User/Core/tim.o + .debug_abbrev 0x00000bed 0x227 ./Application/User/Core/usart.o + .debug_abbrev 0x00000e14 0x24 ./Application/User/Startup/startup_stm32c031k4tx.o + .debug_abbrev 0x00000e38 0x12e ./Drivers/CMSIS/system_stm32c0xx.o + .debug_abbrev 0x00000f66 0x30e ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_abbrev 0x00001274 0x2fd ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_abbrev 0x00001571 0x317 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_abbrev 0x00001888 0x1e9 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_abbrev 0x00001a71 0x209 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_abbrev 0x00001c7a 0x2c3 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_abbrev 0x00001f3d 0x299 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_abbrev 0x000021d6 0x285 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_abbrev 0x0000245b 0x298 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_abbrev 0x000026f3 0x377 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_abbrev 0x00002a6a 0x358 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_loclists + 0x00000000 0xb8c4 + .debug_loclists + 0x00000000 0x6a ./Application/User/Core/adc.o + .debug_loclists + 0x0000006a 0x3e ./Application/User/Core/stm32c0xx_it.o + .debug_loclists + 0x000000a8 0x9e ./Application/User/Core/tim.o + .debug_loclists + 0x00000146 0x85 ./Application/User/Core/usart.o + .debug_loclists + 0x000001cb 0x26 ./Drivers/CMSIS/system_stm32c0xx.o + .debug_loclists + 0x000001f1 0x19a ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_loclists + 0x0000038b 0x1062 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_loclists + 0x000013ed 0x225 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_loclists + 0x00001612 0x696 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_loclists + 0x00001ca8 0x307 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_loclists + 0x00001faf 0x461 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_loclists + 0x00002410 0x4b6 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_loclists + 0x000028c6 0x3f16 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_loclists + 0x000067dc 0x1c85 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_loclists + 0x00008461 0x2c1c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_loclists + 0x0000b07d 0x847 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_aranges 0x00000000 0xed8 + .debug_aranges + 0x00000000 0x30 ./Application/User/Core/adc.o + .debug_aranges + 0x00000030 0x20 ./Application/User/Core/dma.o + .debug_aranges + 0x00000050 0x20 ./Application/User/Core/gpio.o + .debug_aranges + 0x00000070 0x30 ./Application/User/Core/main.o + .debug_aranges + 0x000000a0 0x20 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_aranges + 0x000000c0 0x60 ./Application/User/Core/stm32c0xx_it.o + .debug_aranges + 0x00000120 0x40 ./Application/User/Core/tim.o + .debug_aranges + 0x00000160 0x30 ./Application/User/Core/usart.o + .debug_aranges + 0x00000190 0x28 ./Application/User/Startup/startup_stm32c031k4tx.o + .debug_aranges + 0x000001b8 0x28 ./Drivers/CMSIS/system_stm32c0xx.o + .debug_aranges + 0x000001e0 0xf0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_aranges + 0x000002d0 0x118 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_aranges + 0x000003e8 0xc0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_aranges + 0x000004a8 0x90 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_aranges + 0x00000538 0x68 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_aranges + 0x000005a0 0x90 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_aranges + 0x00000630 0x40 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_aranges + 0x00000670 0x3e0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_aranges + 0x00000a50 0x198 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_aranges + 0x00000be8 0x248 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_aranges + 0x00000e30 0xa8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_rnglists + 0x00000000 0xca6 + .debug_rnglists + 0x00000000 0x21 ./Application/User/Core/adc.o + .debug_rnglists + 0x00000021 0x13 ./Application/User/Core/dma.o + .debug_rnglists + 0x00000034 0x14 ./Application/User/Core/gpio.o + .debug_rnglists + 0x00000048 0x1f ./Application/User/Core/main.o + .debug_rnglists + 0x00000067 0x13 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_rnglists + 0x0000007a 0x43 ./Application/User/Core/stm32c0xx_it.o + .debug_rnglists + 0x000000bd 0x2d ./Application/User/Core/tim.o + .debug_rnglists + 0x000000ea 0x20 ./Application/User/Core/usart.o + .debug_rnglists + 0x0000010a 0x19 ./Application/User/Startup/startup_stm32c031k4tx.o + .debug_rnglists + 0x00000123 0x19 ./Drivers/CMSIS/system_stm32c0xx.o + .debug_rnglists + 0x0000013c 0xaf ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_rnglists + 0x000001eb 0x146 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_rnglists + 0x00000331 0x97 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_rnglists + 0x000003c8 0x6e ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_rnglists + 0x00000436 0x4b ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_rnglists + 0x00000481 0x8a ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_rnglists + 0x0000050b 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_rnglists + 0x0000054f 0x310 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_rnglists + 0x0000085f 0x13f ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_rnglists + 0x0000099e 0x25c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_rnglists + 0x00000bfa 0xac ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_macro 0x00000000 0x15f85 + .debug_macro 0x00000000 0x211 ./Application/User/Core/adc.o + .debug_macro 0x00000211 0xaae ./Application/User/Core/adc.o + .debug_macro 0x00000cbf 0x2e ./Application/User/Core/adc.o + .debug_macro 0x00000ced 0x28 ./Application/User/Core/adc.o + .debug_macro 0x00000d15 0x22 ./Application/User/Core/adc.o + .debug_macro 0x00000d37 0x8e ./Application/User/Core/adc.o + .debug_macro 0x00000dc5 0x51 ./Application/User/Core/adc.o + .debug_macro 0x00000e16 0x103 ./Application/User/Core/adc.o + .debug_macro 0x00000f19 0x6a ./Application/User/Core/adc.o + .debug_macro 0x00000f83 0x1df ./Application/User/Core/adc.o + .debug_macro 0x00001162 0x1c ./Application/User/Core/adc.o + .debug_macro 0x0000117e 0x22 ./Application/User/Core/adc.o + .debug_macro 0x000011a0 0xd1 ./Application/User/Core/adc.o + .debug_macro 0x00001271 0x4da ./Application/User/Core/adc.o + .debug_macro 0x0000174b 0x11f ./Application/User/Core/adc.o + .debug_macro 0x0000186a 0x93cf ./Application/User/Core/adc.o + .debug_macro 0x0000ac39 0x6d ./Application/User/Core/adc.o + .debug_macro 0x0000aca6 0x175 ./Application/User/Core/adc.o + .debug_macro 0x0000ae1b 0xef ./Application/User/Core/adc.o + .debug_macro 0x0000af0a 0x3440 ./Application/User/Core/adc.o + .debug_macro 0x0000e34a 0x190 ./Application/User/Core/adc.o + .debug_macro 0x0000e4da 0x5b ./Application/User/Core/adc.o + .debug_macro 0x0000e535 0x366 ./Application/User/Core/adc.o + .debug_macro 0x0000e89b 0xb47 ./Application/User/Core/adc.o + .debug_macro 0x0000f3e2 0x145 ./Application/User/Core/adc.o + .debug_macro 0x0000f527 0x15f ./Application/User/Core/adc.o + .debug_macro 0x0000f686 0x19d ./Application/User/Core/adc.o + .debug_macro 0x0000f823 0x264 ./Application/User/Core/adc.o + .debug_macro 0x0000fa87 0x17e ./Application/User/Core/adc.o + .debug_macro 0x0000fc05 0x43 ./Application/User/Core/adc.o + .debug_macro 0x0000fc48 0x1f1 ./Application/User/Core/adc.o + .debug_macro 0x0000fe39 0x91d ./Application/User/Core/adc.o + .debug_macro 0x00010756 0x5d7 ./Application/User/Core/adc.o + .debug_macro 0x00010d2d 0x2e ./Application/User/Core/adc.o + .debug_macro 0x00010d5b 0x1b1 ./Application/User/Core/adc.o + .debug_macro 0x00010f0c 0x37c ./Application/User/Core/adc.o + .debug_macro 0x00011288 0x28 ./Application/User/Core/adc.o + .debug_macro 0x000112b0 0xb3 ./Application/User/Core/adc.o + .debug_macro 0x00011363 0x104 ./Application/User/Core/adc.o + .debug_macro 0x00011467 0xf6 ./Application/User/Core/adc.o + .debug_macro 0x0001155d 0xaa6 ./Application/User/Core/adc.o + .debug_macro 0x00012003 0xd9 ./Application/User/Core/adc.o + .debug_macro 0x000120dc 0x67e ./Application/User/Core/adc.o + .debug_macro 0x0001275a 0xa6 ./Application/User/Core/adc.o + .debug_macro 0x00012800 0x3a9 ./Application/User/Core/adc.o + .debug_macro 0x00012ba9 0x184 ./Application/User/Core/adc.o + .debug_macro 0x00012d2d 0x211 ./Application/User/Core/dma.o + .debug_macro 0x00012f3e 0x211 ./Application/User/Core/gpio.o + .debug_macro 0x0001314f 0x23d ./Application/User/Core/main.o + .debug_macro 0x0001338c 0x207 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_macro 0x00013593 0x2f7 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x0001388a 0x61 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x000138eb 0x24 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x0001390f 0x43 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013952 0x34 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013986 0x16 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x0001399c 0x3c ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x000139d8 0x370 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013d48 0x10 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013d58 0x16 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013d6e 0x4a ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013db8 0x34 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013dec 0x10 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013dfc 0x58 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013e54 0x8e ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013ee2 0x1c ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00013efe 0x185 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00014083 0x16 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x00014099 0x16 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x000140af 0x146 ./Application/User/Core/stm32c0xx_it.o + .debug_macro 0x000141f5 0x2e9 ./Application/User/Core/tim.o + .debug_macro 0x000144de 0x211 ./Application/User/Core/usart.o + .debug_macro 0x000146ef 0x1fe ./Drivers/CMSIS/system_stm32c0xx.o + .debug_macro 0x000148ed 0x216 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_macro 0x00014b03 0x21c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_macro 0x00014d1f 0x1f8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_macro 0x00014f17 0x1f8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_macro 0x0001510f 0x22d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_macro 0x0001533c 0x228 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_macro 0x00015564 0x20a ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_macro 0x0001576e 0x200 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_macro 0x0001596e 0x1fe ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_macro 0x00015b6c 0x215 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_macro 0x00015d81 0x204 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_line 0x00000000 0x1a445 + .debug_line 0x00000000 0xa58 ./Application/User/Core/adc.o + .debug_line 0x00000a58 0x7f3 ./Application/User/Core/dma.o + .debug_line 0x0000124b 0x8bd ./Application/User/Core/gpio.o + .debug_line 0x00001b08 0x8eb ./Application/User/Core/main.o + .debug_line 0x000023f3 0x7fc ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_line 0x00002bef 0xaa3 ./Application/User/Core/stm32c0xx_it.o + .debug_line 0x00003692 0xc2e ./Application/User/Core/tim.o + .debug_line 0x000042c0 0x987 ./Application/User/Core/usart.o + .debug_line 0x00004c47 0x7d ./Application/User/Startup/startup_stm32c031k4tx.o + .debug_line 0x00004cc4 0x862 ./Drivers/CMSIS/system_stm32c0xx.o + .debug_line 0x00005526 0xbc8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_line 0x000060ee 0x20a9 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_line 0x00008197 0xccf ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_line 0x00008e66 0x1187 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_line 0x00009fed 0xd52 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_line 0x0000ad3f 0x10f7 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_line 0x0000be36 0xbfb ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_line 0x0000ca31 0x51de ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_line 0x00011c0f 0x23e5 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_line 0x00013ff4 0x5329 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_line 0x0001931d 0x1128 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_str 0x00000000 0x8a5e8 + .debug_str 0x00000000 0x8a5e8 ./Application/User/Core/adc.o + 0x82c0c (size before relaxing) + .debug_str 0x0008a5e8 0x8260b ./Application/User/Core/dma.o + .debug_str 0x0008a5e8 0x8256c ./Application/User/Core/gpio.o + .debug_str 0x0008a5e8 0x8264f ./Application/User/Core/main.o + .debug_str 0x0008a5e8 0x82489 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_str 0x0008a5e8 0x862ba ./Application/User/Core/stm32c0xx_it.o + .debug_str 0x0008a5e8 0x86734 ./Application/User/Core/tim.o + .debug_str 0x0008a5e8 0x82c24 ./Application/User/Core/usart.o + .debug_str 0x0008a5e8 0x8e ./Application/User/Startup/startup_stm32c031k4tx.o + .debug_str 0x0008a5e8 0x81d5a ./Drivers/CMSIS/system_stm32c0xx.o + .debug_str 0x0008a5e8 0x8235e ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_str 0x0008a5e8 0x82b2e ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_str 0x0008a5e8 0x82173 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_str 0x0008a5e8 0x821df ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_str 0x0008a5e8 0x81f52 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_str 0x0008a5e8 0x82345 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_str 0x0008a5e8 0x81fd1 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_str 0x0008a5e8 0x83282 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_str 0x0008a5e8 0x82c10 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_str 0x0008a5e8 0x82cb8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_str 0x0008a5e8 0x825e0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Application/User/Core/adc.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Application/User/Core/dma.o + .comment 0x00000043 0x44 ./Application/User/Core/gpio.o + .comment 0x00000043 0x44 ./Application/User/Core/main.o + .comment 0x00000043 0x44 ./Application/User/Core/stm32c0xx_hal_msp.o + .comment 0x00000043 0x44 ./Application/User/Core/stm32c0xx_it.o + .comment 0x00000043 0x44 ./Application/User/Core/tim.o + .comment 0x00000043 0x44 ./Application/User/Core/usart.o + .comment 0x00000043 0x44 ./Drivers/CMSIS/system_stm32c0xx.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_frame 0x00000000 0x2714 + .debug_frame 0x00000000 0x5c ./Application/User/Core/adc.o + .debug_frame 0x0000005c 0x28 ./Application/User/Core/dma.o + .debug_frame 0x00000084 0x38 ./Application/User/Core/gpio.o + .debug_frame 0x000000bc 0x50 ./Application/User/Core/main.o + .debug_frame 0x0000010c 0x24 ./Application/User/Core/stm32c0xx_hal_msp.o + .debug_frame 0x00000130 0xc4 ./Application/User/Core/stm32c0xx_it.o + .debug_frame 0x000001f4 0x90 ./Application/User/Core/tim.o + .debug_frame 0x00000284 0x60 ./Application/User/Core/usart.o + .debug_frame 0x000002e4 0x30 ./Drivers/CMSIS/system_stm32c0xx.o + .debug_frame 0x00000314 0x1ec ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .debug_frame 0x00000500 0x2fc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .debug_frame 0x000007fc 0x194 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .debug_frame 0x00000990 0x188 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .debug_frame 0x00000b18 0xe8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .debug_frame 0x00000c00 0x168 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .debug_frame 0x00000d68 0x84 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .debug_frame 0x00000dec 0xb20 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .debug_frame 0x0000190c 0x4c0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .debug_frame 0x00001dcc 0x6dc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .debug_frame 0x000024a8 0x1e0 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + .debug_frame 0x00002688 0x20 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .debug_frame 0x000026a8 0x2c C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .debug_frame 0x000026d4 0x20 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .debug_frame 0x000026f4 0x20 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + +.debug_line_str + 0x00000000 0x72 + .debug_line_str + 0x00000000 0x72 ./Application/User/Startup/startup_stm32c031k4tx.o Index: /trunk/firmware_v3/STM32CubeIDE/Debug/makefile =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/makefile (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/makefile (revision 41) @@ -0,0 +1,96 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include src/subdir.mk +-include Drivers/STM32C0xx_HAL_Driver/subdir.mk +-include Drivers/CMSIS/subdir.mk +-include Application/User/Startup/subdir.mk +-include Application/User/Core/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := firmware_v2 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +firmware_v2.elf \ + +MAP_FILES += \ +firmware_v2.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +firmware_v2.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: firmware_v2.elf secondary-outputs + +# Tool invocations +firmware_v2.elf firmware_v2.map: $(OBJS) $(USER_OBJS) D:\Projekte\ecs_PowerPro\trunk\firmware_v2\STM32CubeIDE\STM32C031K4TX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "firmware_v2.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"D:\Projekte\ecs_PowerPro\trunk\firmware_v2\STM32CubeIDE\STM32C031K4TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="firmware_v2.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +firmware_v2.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "firmware_v2.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) default.size.stdout firmware_v2.elf firmware_v2.list firmware_v2.map + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets Index: /trunk/firmware_v3/STM32CubeIDE/Debug/objects.list =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/objects.list (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/objects.list (revision 41) @@ -0,0 +1,38 @@ +"./Application/User/Core/adc.o" +"./Application/User/Core/dma.o" +"./Application/User/Core/gpio.o" +"./Application/User/Core/main.o" +"./Application/User/Core/stm32c0xx_hal_msp.o" +"./Application/User/Core/stm32c0xx_it.o" +"./Application/User/Core/syscalls.o" +"./Application/User/Core/sysmem.o" +"./Application/User/Core/tim.o" +"./Application/User/Core/usart.o" +"./Application/User/Startup/startup_stm32c031k4tx.o" +"./Drivers/CMSIS/system_stm32c0xx.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o" +"./src/button.o" +"./src/buzzer.o" +"./src/leds.o" +"./src/main.o" +"./src/mode_mainswitch.o" +"./src/mode_secondaryprotection.o" +"./src/modeswitch.o" +"./src/relais.o" Index: /trunk/firmware_v3/STM32CubeIDE/Debug/objects.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/objects.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/objects.mk (revision 41) @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/sources.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/sources.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/sources.mk (revision 41) @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Application/User/Core \ +Application/User/Startup \ +Drivers/CMSIS \ +Drivers/STM32C0xx_HAL_Driver \ +src \ + Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.cyclo (revision 41) @@ -0,0 +1,3 @@ +../src/button.c:15:16:BUTTON_Exec 11 +../src/button.c:76:16:BUTTON_GetMode 1 +../src/button.c:81:6:BUTTON_SetModeOff 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.d (revision 41) @@ -0,0 +1,73 @@ +src/button.o: ../src/button.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/button.su (revision 41) @@ -0,0 +1,3 @@ +../src/button.c:15:16:BUTTON_Exec 8 static +../src/button.c:76:16:BUTTON_GetMode 0 static +../src/button.c:81:6:BUTTON_SetModeOff 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.cyclo (revision 41) @@ -0,0 +1,4 @@ +../src/buzzer.c:12:6:BUZZER_Exec 6 +../src/buzzer.c:39:6:BUZZER_Beep 1 +../src/buzzer.c:46:6:BUZZER_Alarm_Start 1 +../src/buzzer.c:57:6:BUZZER_Alarm_Stop 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.d (revision 41) @@ -0,0 +1,72 @@ +src/buzzer.o: ../src/buzzer.c ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/buzzer.su (revision 41) @@ -0,0 +1,4 @@ +../src/buzzer.c:12:6:BUZZER_Exec 8 static +../src/buzzer.c:39:6:BUZZER_Beep 8 static +../src/buzzer.c:46:6:BUZZER_Alarm_Start 8 static +../src/buzzer.c:57:6:BUZZER_Alarm_Stop 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.cyclo (revision 41) @@ -0,0 +1,9 @@ +../src/leds.c:17:6:LEDS_Exec 11 +../src/leds.c:66:6:LEDS_GN_On 1 +../src/leds.c:77:6:LEDS_GN_Flash 1 +../src/leds.c:83:6:LEDS_GN_Blink_Start 1 +../src/leds.c:93:6:LEDS_GN_Off 1 +../src/leds.c:104:6:LEDS_RT_On 1 +../src/leds.c:115:6:LEDS_RT_Flash 1 +../src/leds.c:121:6:LEDS_RT_Blink_Start 1 +../src/leds.c:131:6:LEDS_RT_Off 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.d (revision 41) @@ -0,0 +1,72 @@ +src/leds.o: ../src/leds.c ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/leds.su (revision 41) @@ -0,0 +1,9 @@ +../src/leds.c:17:6:LEDS_Exec 8 static +../src/leds.c:66:6:LEDS_GN_On 8 static +../src/leds.c:77:6:LEDS_GN_Flash 8 static +../src/leds.c:83:6:LEDS_GN_Blink_Start 8 static +../src/leds.c:93:6:LEDS_GN_Off 8 static +../src/leds.c:104:6:LEDS_RT_On 8 static +../src/leds.c:115:6:LEDS_RT_Flash 8 static +../src/leds.c:121:6:LEDS_RT_Blink_Start 8 static +../src/leds.c:131:6:LEDS_RT_Off 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.cyclo (revision 41) @@ -0,0 +1,4 @@ +../src/main.c:201:13:MX_GPIO_Init 1 +../src/main.c:261:6:Error_Handler 1 +../src/main.c:162:6:SystemClock_Config 1 +../src/main.c:72:5:main 4 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.d (revision 41) @@ -0,0 +1,84 @@ +src/main.o: ../src/main.c ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/main.su (revision 41) @@ -0,0 +1,4 @@ +../src/main.c:201:13:MX_GPIO_Init 56 static +../src/main.c:261:6:Error_Handler 0 static,ignoring_inline_asm +../src/main.c:162:6:SystemClock_Config 56 static +../src/main.c:72:5:main 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.cyclo (revision 41) @@ -0,0 +1,5 @@ +../src/mode_mainswitch.c:42:6:MAINSWITCH_SM_Off 5 +../src/mode_mainswitch.c:97:6:MAINSWITCH_SM_On 4 +../src/mode_mainswitch.c:137:6:MAINSWITCH_SM_ManualOn 2 +../src/mode_mainswitch.c:153:6:MAINSWITCH_SM_Error 5 +../src/mode_mainswitch.c:207:6:MODE_MAINSWITCH_Exec 6 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.d (revision 41) @@ -0,0 +1,81 @@ +src/mode_mainswitch.o: ../src/mode_mainswitch.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_mainswitch.su (revision 41) @@ -0,0 +1,5 @@ +../src/mode_mainswitch.c:42:6:MAINSWITCH_SM_Off 8 static +../src/mode_mainswitch.c:97:6:MAINSWITCH_SM_On 8 static +../src/mode_mainswitch.c:137:6:MAINSWITCH_SM_ManualOn 8 static +../src/mode_mainswitch.c:153:6:MAINSWITCH_SM_Error 8 static +../src/mode_mainswitch.c:207:6:MODE_MAINSWITCH_Exec 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.cyclo (revision 41) @@ -0,0 +1,5 @@ +../src/mode_secondaryprotection.c:41:6:SECONDARYPROTECTION_SM_Off 6 +../src/mode_secondaryprotection.c:106:6:SECONDARYPROTECTION_SM_On 9 +../src/mode_secondaryprotection.c:183:6:SECONDARYPROTECTION_SM_ManualOn 2 +../src/mode_secondaryprotection.c:199:6:SECONDARYPROTECTION_SM_Error 5 +../src/mode_secondaryprotection.c:255:6:MODE_SECONDARYPROTECTION_Exec 6 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,81 @@ +src/mode_secondaryprotection.o: ../src/mode_secondaryprotection.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/mode_secondaryprotection.su (revision 41) @@ -0,0 +1,5 @@ +../src/mode_secondaryprotection.c:41:6:SECONDARYPROTECTION_SM_Off 8 static +../src/mode_secondaryprotection.c:106:6:SECONDARYPROTECTION_SM_On 16 static +../src/mode_secondaryprotection.c:183:6:SECONDARYPROTECTION_SM_ManualOn 8 static +../src/mode_secondaryprotection.c:199:6:SECONDARYPROTECTION_SM_Error 8 static +../src/mode_secondaryprotection.c:255:6:MODE_SECONDARYPROTECTION_Exec 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.cyclo (revision 41) @@ -0,0 +1,2 @@ +../src/modeswitch.c:8:19:MODESWITCH_ReadMode 1 +../src/modeswitch.c:27:19:MODESWITCH_GetMode 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.d (revision 41) @@ -0,0 +1,73 @@ +src/modeswitch.o: ../src/modeswitch.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/modeswitch.su (revision 41) @@ -0,0 +1,2 @@ +../src/modeswitch.c:8:19:MODESWITCH_ReadMode 24 static +../src/modeswitch.c:27:19:MODESWITCH_GetMode 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.cyclo (revision 41) @@ -0,0 +1,4 @@ +../src/relais.c:14:6:RELAIS_Exec 5 +../src/relais.c:39:6:RELAIS_SetPuls 1 +../src/relais.c:52:6:RELAIS_ResetPuls 1 +../src/relais.c:66:14:RELAIS_GetState 1 Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.d (revision 41) @@ -0,0 +1,73 @@ +src/relais.o: ../src/relais.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/relais.su (revision 41) @@ -0,0 +1,4 @@ +../src/relais.c:14:6:RELAIS_Exec 8 static +../src/relais.c:39:6:RELAIS_SetPuls 8 static +../src/relais.c:52:6:RELAIS_ResetPuls 8 static +../src/relais.c:66:14:RELAIS_GetState 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Debug/src/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Debug/src/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Debug/src/subdir.mk (revision 41) @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../src/button.c \ +../src/buzzer.c \ +../src/leds.c \ +../src/main.c \ +../src/mode_mainswitch.c \ +../src/mode_secondaryprotection.c \ +../src/modeswitch.c \ +../src/relais.c + +OBJS += \ +./src/button.o \ +./src/buzzer.o \ +./src/leds.o \ +./src/main.o \ +./src/mode_mainswitch.o \ +./src/mode_secondaryprotection.o \ +./src/modeswitch.o \ +./src/relais.o + +C_DEPS += \ +./src/button.d \ +./src/buzzer.d \ +./src/leds.d \ +./src/main.d \ +./src/mode_mainswitch.d \ +./src/mode_secondaryprotection.d \ +./src/modeswitch.d \ +./src/relais.d + + +# Each subdirectory must supply rules for building sources it contributes +src/%.o src/%.su src/%.cyclo: ../src/%.c src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Og -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-src + +clean-src: + -$(RM) ./src/button.cyclo ./src/button.d ./src/button.o ./src/button.su ./src/buzzer.cyclo ./src/buzzer.d ./src/buzzer.o ./src/buzzer.su ./src/leds.cyclo ./src/leds.d ./src/leds.o ./src/leds.su ./src/main.cyclo ./src/main.d ./src/main.o ./src/main.su ./src/mode_mainswitch.cyclo ./src/mode_mainswitch.d ./src/mode_mainswitch.o ./src/mode_mainswitch.su ./src/mode_secondaryprotection.cyclo ./src/mode_secondaryprotection.d ./src/mode_secondaryprotection.o ./src/mode_secondaryprotection.su ./src/modeswitch.cyclo ./src/modeswitch.d ./src/modeswitch.o ./src/modeswitch.su ./src/relais.cyclo ./src/relais.d ./src/relais.o ./src/relais.su + +.PHONY: clean-src + Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.cyclo (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:31:6:MX_ADC1_Init 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:118:6:HAL_ADC_MspInit 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:177:6:HAL_ADC_MspDeInit 2 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/adc.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c \ + ../../Core/Inc/adc.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/adc.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/adc.su (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:31:6:MX_ADC1_Init 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:118:6:HAL_ADC_MspInit 72 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c:177:6:HAL_ADC_MspDeInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.cyclo (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c:39:6:MX_DMA_Init 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/dma.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c \ + ../../Core/Inc/dma.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/dma.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/dma.su (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c:39:6:MX_DMA_Init 16 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.cyclo (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c:42:6:MX_GPIO_Init 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/gpio.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c \ + ../../Core/Inc/gpio.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/gpio.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/gpio.su (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c:42:6:MX_GPIO_Init 56 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.cyclo (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:117:6:SystemClock_Config 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:68:5:main 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:159:6:Error_Handler 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.d (revision 41) @@ -0,0 +1,80 @@ +Application/User/Core/main.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + ../../Core/Inc/adc.h ../../Core/Inc/main.h ../../Core/Inc/dma.h \ + ../../Core/Inc/tim.h ../../Core/Inc/usart.h ../../Core/Inc/gpio.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +../../Core/Inc/adc.h: +../../Core/Inc/main.h: +../../Core/Inc/dma.h: +../../Core/Inc/tim.h: +../../Core/Inc/usart.h: +../../Core/Inc/gpio.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/main.su (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:117:6:SystemClock_Config 56 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:68:5:main 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c:159:6:Error_Handler 0 static,ignoring_inline_asm Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.cyclo (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c:63:6:HAL_MspInit 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.d (revision 41) @@ -0,0 +1,72 @@ +Application/User/Core/stm32c0xx_hal_msp.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_hal_msp.su (revision 41) @@ -0,0 +1,1 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c:63:6:HAL_MspInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.cyclo (revision 41) @@ -0,0 +1,6 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:69:6:NMI_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:84:6:HardFault_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:99:6:SVC_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:112:6:PendSV_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:125:6:SysTick_Handler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:146:6:DMA1_Channel1_IRQHandler 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.d (revision 41) @@ -0,0 +1,74 @@ +Application/User/Core/stm32c0xx_it.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + ../../Core/Inc/stm32c0xx_it.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +../../Core/Inc/stm32c0xx_it.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/stm32c0xx_it.su (revision 41) @@ -0,0 +1,6 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:69:6:NMI_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:84:6:HardFault_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:99:6:SVC_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:112:6:PendSV_Handler 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:125:6:SysTick_Handler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c:146:6:DMA1_Channel1_IRQHandler 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/subdir.mk (revision 41) @@ -0,0 +1,70 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c \ +../Application/User/Core/syscalls.c \ +../Application/User/Core/sysmem.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c + +OBJS += \ +./Application/User/Core/adc.o \ +./Application/User/Core/dma.o \ +./Application/User/Core/gpio.o \ +./Application/User/Core/main.o \ +./Application/User/Core/stm32c0xx_hal_msp.o \ +./Application/User/Core/stm32c0xx_it.o \ +./Application/User/Core/syscalls.o \ +./Application/User/Core/sysmem.o \ +./Application/User/Core/tim.o \ +./Application/User/Core/usart.o + +C_DEPS += \ +./Application/User/Core/adc.d \ +./Application/User/Core/dma.d \ +./Application/User/Core/gpio.d \ +./Application/User/Core/main.d \ +./Application/User/Core/stm32c0xx_hal_msp.d \ +./Application/User/Core/stm32c0xx_it.d \ +./Application/User/Core/syscalls.d \ +./Application/User/Core/sysmem.d \ +./Application/User/Core/tim.d \ +./Application/User/Core/usart.d + + +# Each subdirectory must supply rules for building sources it contributes +Application/User/Core/adc.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/adc.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/dma.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/dma.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/gpio.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/gpio.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/main.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/main.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/stm32c0xx_hal_msp.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_hal_msp.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/stm32c0xx_it.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/stm32c0xx_it.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/%.o Application/User/Core/%.su Application/User/Core/%.cyclo: ../Application/User/Core/%.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/tim.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Application/User/Core/usart.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c Application/User/Core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Application-2f-User-2f-Core + +clean-Application-2f-User-2f-Core: + -$(RM) ./Application/User/Core/adc.cyclo ./Application/User/Core/adc.d ./Application/User/Core/adc.o ./Application/User/Core/adc.su ./Application/User/Core/dma.cyclo ./Application/User/Core/dma.d ./Application/User/Core/dma.o ./Application/User/Core/dma.su ./Application/User/Core/gpio.cyclo ./Application/User/Core/gpio.d ./Application/User/Core/gpio.o ./Application/User/Core/gpio.su ./Application/User/Core/main.cyclo ./Application/User/Core/main.d ./Application/User/Core/main.o ./Application/User/Core/main.su ./Application/User/Core/stm32c0xx_hal_msp.cyclo ./Application/User/Core/stm32c0xx_hal_msp.d ./Application/User/Core/stm32c0xx_hal_msp.o ./Application/User/Core/stm32c0xx_hal_msp.su ./Application/User/Core/stm32c0xx_it.cyclo ./Application/User/Core/stm32c0xx_it.d ./Application/User/Core/stm32c0xx_it.o ./Application/User/Core/stm32c0xx_it.su ./Application/User/Core/syscalls.cyclo ./Application/User/Core/syscalls.d ./Application/User/Core/syscalls.o ./Application/User/Core/syscalls.su ./Application/User/Core/sysmem.cyclo ./Application/User/Core/sysmem.d ./Application/User/Core/sysmem.o ./Application/User/Core/sysmem.su ./Application/User/Core/tim.cyclo ./Application/User/Core/tim.d ./Application/User/Core/tim.o ./Application/User/Core/tim.su ./Application/User/Core/usart.cyclo ./Application/User/Core/usart.d ./Application/User/Core/usart.o ./Application/User/Core/usart.su + +.PHONY: clean-Application-2f-User-2f-Core + Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.cyclo (revision 41) @@ -0,0 +1,18 @@ +../Application/User/Core/syscalls.c:44:6:initialise_monitor_handles 1 +../Application/User/Core/syscalls.c:48:5:_getpid 1 +../Application/User/Core/syscalls.c:53:5:_kill 1 +../Application/User/Core/syscalls.c:61:6:_exit 1 +../Application/User/Core/syscalls.c:67:27:_read 2 +../Application/User/Core/syscalls.c:80:27:_write 2 +../Application/User/Core/syscalls.c:92:5:_close 1 +../Application/User/Core/syscalls.c:99:5:_fstat 1 +../Application/User/Core/syscalls.c:106:5:_isatty 1 +../Application/User/Core/syscalls.c:112:5:_lseek 1 +../Application/User/Core/syscalls.c:120:5:_open 1 +../Application/User/Core/syscalls.c:128:5:_wait 1 +../Application/User/Core/syscalls.c:135:5:_unlink 1 +../Application/User/Core/syscalls.c:142:5:_times 1 +../Application/User/Core/syscalls.c:148:5:_stat 1 +../Application/User/Core/syscalls.c:155:5:_link 1 +../Application/User/Core/syscalls.c:163:5:_fork 1 +../Application/User/Core/syscalls.c:169:5:_execve 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.d (revision 41) @@ -0,0 +1,1 @@ +Application/User/Core/syscalls.o: ../Application/User/Core/syscalls.c Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/syscalls.su (revision 41) @@ -0,0 +1,18 @@ +../Application/User/Core/syscalls.c:44:6:initialise_monitor_handles 0 static +../Application/User/Core/syscalls.c:48:5:_getpid 0 static +../Application/User/Core/syscalls.c:53:5:_kill 8 static +../Application/User/Core/syscalls.c:61:6:_exit 8 static +../Application/User/Core/syscalls.c:67:27:_read 16 static +../Application/User/Core/syscalls.c:80:27:_write 16 static +../Application/User/Core/syscalls.c:92:5:_close 0 static +../Application/User/Core/syscalls.c:99:5:_fstat 0 static +../Application/User/Core/syscalls.c:106:5:_isatty 0 static +../Application/User/Core/syscalls.c:112:5:_lseek 0 static +../Application/User/Core/syscalls.c:120:5:_open 0 static +../Application/User/Core/syscalls.c:128:5:_wait 8 static +../Application/User/Core/syscalls.c:135:5:_unlink 8 static +../Application/User/Core/syscalls.c:142:5:_times 0 static +../Application/User/Core/syscalls.c:148:5:_stat 0 static +../Application/User/Core/syscalls.c:155:5:_link 8 static +../Application/User/Core/syscalls.c:163:5:_fork 8 static +../Application/User/Core/syscalls.c:169:5:_execve 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.cyclo (revision 41) @@ -0,0 +1,1 @@ +../Application/User/Core/sysmem.c:53:7:_sbrk 3 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.d (revision 41) @@ -0,0 +1,1 @@ +Application/User/Core/sysmem.o: ../Application/User/Core/sysmem.c Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/sysmem.su (revision 41) @@ -0,0 +1,1 @@ +../Application/User/Core/sysmem.c:53:7:_sbrk 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.cyclo (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:31:6:MX_TIM16_Init 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:130:6:HAL_TIM_Base_MspInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:169:6:HAL_TIM_MspPostInit 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:72:6:MX_TIM17_Init 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:197:6:HAL_TIM_Base_MspDeInit 3 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/tim.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c \ + ../../Core/Inc/tim.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/tim.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/tim.su (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:31:6:MX_TIM16_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:130:6:HAL_TIM_Base_MspInit 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:169:6:HAL_TIM_MspPostInit 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:72:6:MX_TIM17_Init 96 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/tim.c:197:6:HAL_TIM_Base_MspDeInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.cyclo (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:31:6:MX_USART1_UART_Init 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:74:6:HAL_UART_MspInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:122:6:HAL_UART_MspDeInit 2 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.d (revision 41) @@ -0,0 +1,73 @@ +Application/User/Core/usart.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c \ + ../../Core/Inc/usart.h ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Core/Inc/usart.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Core/usart.su (revision 41) @@ -0,0 +1,3 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:31:6:MX_USART1_UART_Init 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:74:6:HAL_UART_MspInit 72 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/usart.c:122:6:HAL_UART_MspDeInit 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Startup/startup_stm32c031k4tx.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Startup/startup_stm32c031k4tx.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Startup/startup_stm32c031k4tx.d (revision 41) @@ -0,0 +1,2 @@ +Application/User/Startup/startup_stm32c031k4tx.o: \ + ../Application/User/Startup/startup_stm32c031k4tx.s Index: /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Startup/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Startup/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Application/User/Startup/subdir.mk (revision 41) @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Application/User/Startup/startup_stm32c031k4tx.s + +OBJS += \ +./Application/User/Startup/startup_stm32c031k4tx.o + +S_DEPS += \ +./Application/User/Startup/startup_stm32c031k4tx.d + + +# Each subdirectory must supply rules for building sources it contributes +Application/User/Startup/%.o: ../Application/User/Startup/%.s Application/User/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m0plus -c -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Application-2f-User-2f-Startup + +clean-Application-2f-User-2f-Startup: + -$(RM) ./Application/User/Startup/startup_stm32c031k4tx.d ./Application/User/Startup/startup_stm32c031k4tx.o + +.PHONY: clean-Application-2f-User-2f-Startup + Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/subdir.mk (revision 41) @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c + +OBJS += \ +./Drivers/CMSIS/system_stm32c0xx.o + +C_DEPS += \ +./Drivers/CMSIS/system_stm32c0xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/system_stm32c0xx.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c Drivers/CMSIS/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS + +clean-Drivers-2f-CMSIS: + -$(RM) ./Drivers/CMSIS/system_stm32c0xx.cyclo ./Drivers/CMSIS/system_stm32c0xx.d ./Drivers/CMSIS/system_stm32c0xx.o ./Drivers/CMSIS/system_stm32c0xx.su + +.PHONY: clean-Drivers-2f-CMSIS + Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.cyclo (revision 41) @@ -0,0 +1,2 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:142:6:SystemInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate 4 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/CMSIS/system_stm32c0xx.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/CMSIS/system_stm32c0xx.su (revision 41) @@ -0,0 +1,2 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:142:6:SystemInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo (revision 41) @@ -0,0 +1,27 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:332:19:HAL_SetTickFreq 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:357:21:HAL_GetTickFreq 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:373:13:HAL_Delay 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:399:13:HAL_SuspendTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:415:13:HAL_ResumeTick 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:425:10:HAL_GetHalVersion 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:434:10:HAL_GetREVID 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:443:10:HAL_GetDEVID 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:452:10:HAL_GetUIDw0 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:461:10:HAL_GetUIDw1 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:470:10:HAL_GetUIDw2 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:498:6:HAL_DBGMCU_EnableDBGStopMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:507:6:HAL_DBGMCU_DisableDBGStopMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:554:6:HAL_SYSCFG_EnableRemap 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:569:6:HAL_SYSCFG_DisableRemap 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:582:6:HAL_SYSCFG_SetPinBinding 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:595:10:HAL_SYSCFG_GetPinBinding 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su (revision 41) @@ -0,0 +1,27 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:332:19:HAL_SetTickFreq 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:357:21:HAL_GetTickFreq 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:373:13:HAL_Delay 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:399:13:HAL_SuspendTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:415:13:HAL_ResumeTick 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:425:10:HAL_GetHalVersion 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:434:10:HAL_GetREVID 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:443:10:HAL_GetDEVID 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:452:10:HAL_GetUIDw0 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:461:10:HAL_GetUIDw1 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:470:10:HAL_GetUIDw2 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:498:6:HAL_DBGMCU_EnableDBGStopMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:507:6:HAL_DBGMCU_DisableDBGStopMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:554:6:HAL_SYSCFG_EnableRemap 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:569:6:HAL_SYSCFG_DisableRemap 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:582:6:HAL_SYSCFG_SetPinBinding 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:595:10:HAL_SYSCFG_GetPinBinding 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo (revision 41) @@ -0,0 +1,32 @@ +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4004:22:LL_ADC_SetAnalogWDMonitChannels 2 +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4783:26:LL_ADC_REG_IsConversionOngoing 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:874:13:HAL_ADC_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:387:19:HAL_ADC_Init 18 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:891:13:HAL_ADC_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1282:19:HAL_ADC_PollForConversion 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1412:19:HAL_ADC_PollForEvent 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1865:10:HAL_ADC_GetValue 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2130:13:HAL_ADC_ConvCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2145:13:HAL_ADC_ConvHalfCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3017:13:ADC_DMAHalfConvCplt 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2160:13:HAL_ADC_LevelOutOfWindowCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2182:13:HAL_ADC_ErrorCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3035:13:ADC_DMAError 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2939:13:ADC_DMAConvCplt 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2197:13:HAL_ADC_CalibrationCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2212:13:HAL_ADC_ADCReadyCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1882:6:HAL_ADC_IRQHandler 30 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2258:19:HAL_ADC_ConfigChannel 40 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2701:10:HAL_ADC_GetState 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2715:10:HAL_ADC_GetError 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2742:19:ADC_ConversionStop 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2792:19:ADC_Enable 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1158:19:HAL_ADC_Start 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1539:19:HAL_ADC_Start_IT 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1683:19:HAL_ADC_Start_DMA 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2881:19:ADC_Disable 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:742:19:HAL_ADC_DeInit 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1228:19:HAL_ADC_Stop 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1633:19:HAL_ADC_Stop_IT 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1781:19:HAL_ADC_Stop_DMA 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2458:19:HAL_ADC_AnalogWDGConfig 63 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su (revision 41) @@ -0,0 +1,32 @@ +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4004:22:LL_ADC_SetAnalogWDMonitChannels 8 static +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:4783:26:LL_ADC_REG_IsConversionOngoing 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:874:13:HAL_ADC_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:387:19:HAL_ADC_Init 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:891:13:HAL_ADC_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1282:19:HAL_ADC_PollForConversion 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1412:19:HAL_ADC_PollForEvent 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1865:10:HAL_ADC_GetValue 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2130:13:HAL_ADC_ConvCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2145:13:HAL_ADC_ConvHalfCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3017:13:ADC_DMAHalfConvCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2160:13:HAL_ADC_LevelOutOfWindowCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2182:13:HAL_ADC_ErrorCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:3035:13:ADC_DMAError 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2939:13:ADC_DMAConvCplt 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2197:13:HAL_ADC_CalibrationCpltCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2212:13:HAL_ADC_ADCReadyCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1882:6:HAL_ADC_IRQHandler 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2258:19:HAL_ADC_ConfigChannel 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2701:10:HAL_ADC_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2715:10:HAL_ADC_GetError 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2742:19:ADC_ConversionStop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2792:19:ADC_Enable 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1158:19:HAL_ADC_Start 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1539:19:HAL_ADC_Start_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1683:19:HAL_ADC_Start_DMA 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2881:19:ADC_Disable 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:742:19:HAL_ADC_DeInit 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1228:19:HAL_ADC_Stop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1633:19:HAL_ADC_Stop_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:1781:19:HAL_ADC_Stop_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c:2458:19:HAL_ADC_AnalogWDGConfig 32 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo (revision 41) @@ -0,0 +1,8 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:105:19:HAL_ADCEx_Calibration_Start 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:252:10:HAL_ADCEx_Calibration_GetValue 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:268:19:HAL_ADCEx_Calibration_SetValue 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:314:13:HAL_ADCEx_LevelOutOfWindow2Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:329:13:HAL_ADCEx_LevelOutOfWindow3Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:345:13:HAL_ADCEx_EndOfSamplingCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:360:13:HAL_ADCEx_ChannelConfigReadyCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:383:19:HAL_ADCEx_DisableVoltageRegulator 2 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su (revision 41) @@ -0,0 +1,8 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:105:19:HAL_ADCEx_Calibration_Start 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:252:10:HAL_ADCEx_Calibration_GetValue 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:268:19:HAL_ADCEx_Calibration_SetValue 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:314:13:HAL_ADCEx_LevelOutOfWindow2Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:329:13:HAL_ADCEx_LevelOutOfWindow3Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:345:13:HAL_ADCEx_EndOfSamplingCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:360:13:HAL_ADCEx_ChannelConfigReadyCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c:383:19:HAL_ADCEx_DisableVoltageRegulator 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo (revision 41) @@ -0,0 +1,17 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:380:6:HAL_MPU_DisableRegion 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:398:6:HAL_MPU_ConfigRegion 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su (revision 41) @@ -0,0 +1,17 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:380:6:HAL_MPU_DisableRegion 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:398:6:HAL_MPU_ConfigRegion 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo (revision 41) @@ -0,0 +1,14 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:345:19:HAL_DMA_Start 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:392:19:HAL_DMA_Start_IT 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer 13 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:724:6:HAL_DMA_IRQHandler 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su (revision 41) @@ -0,0 +1,14 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig 20 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:345:19:HAL_DMA_Start 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:392:19:HAL_DMA_Start_IT 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort 20 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:724:6:HAL_DMA_IRQHandler 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:94:19:HAL_DMAEx_ConfigMuxSync 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:142:19:HAL_DMAEx_ConfigMuxRequestGenerator 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:208:19:HAL_DMAEx_DisableMuxRequestGenerator 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:236:6:HAL_DMAEx_MUX_IRQHandler 6 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:94:19:HAL_DMAEx_ConfigMuxSync 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:142:19:HAL_DMAEx_ConfigMuxRequestGenerator 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:208:19:HAL_DMAEx_DisableMuxRequestGenerator 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:236:6:HAL_DMAEx_MUX_IRQHandler 16 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo (revision 41) @@ -0,0 +1,9 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:588:6:HAL_EXTI_ClearPending 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:624:6:HAL_EXTI_GenerateSWI 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su (revision 41) @@ -0,0 +1,9 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine 20 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:588:6:HAL_EXTI_ClearPending 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:624:6:HAL_EXTI_GenerateSWI 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo (revision 41) @@ -0,0 +1,13 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT 4 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su (revision 41) @@ -0,0 +1,13 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program 32 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT 32 static,ignoring_inline_asm Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo (revision 41) @@ -0,0 +1,11 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram 16 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches 2 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su (revision 41) @@ -0,0 +1,11 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init 15 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler 3 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler 16 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:73:6:HAL_PWR_DeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:207:6:HAL_PWR_EnableWakeUpPin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:228:6:HAL_PWR_DisableWakeUpPin 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:252:6:HAL_PWR_EnterSLEEPMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:300:6:HAL_PWR_EnterSTOPMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:343:6:HAL_PWR_EnterSTANDBYMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:364:6:HAL_PWR_EnableSleepOnExit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:377:6:HAL_PWR_DisableSleepOnExit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:390:6:HAL_PWR_EnableSEVOnPend 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:402:6:HAL_PWR_DisableSEVOnPend 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su (revision 41) @@ -0,0 +1,10 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:73:6:HAL_PWR_DeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:207:6:HAL_PWR_EnableWakeUpPin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:228:6:HAL_PWR_DisableWakeUpPin 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:252:6:HAL_PWR_EnterSLEEPMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:300:6:HAL_PWR_EnterSTOPMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:343:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:364:6:HAL_PWR_EnableSleepOnExit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:377:6:HAL_PWR_DisableSleepOnExit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:390:6:HAL_PWR_EnableSEVOnPend 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:402:6:HAL_PWR_DisableSEVOnPend 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo (revision 41) @@ -0,0 +1,13 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:163:6:HAL_PWREx_EnableInternalWakeUpLine 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableInternalWakeUpLine 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:198:19:HAL_PWREx_EnableGPIOPullUp 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:254:19:HAL_PWREx_DisableGPIOPullUp 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:311:19:HAL_PWREx_EnableGPIOPullDown 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:367:19:HAL_PWREx_DisableGPIOPullDown 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:415:6:HAL_PWREx_EnablePullUpPullDownConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:426:6:HAL_PWREx_DisablePullUpPullDownConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:440:6:HAL_PWREx_EnableFlashPowerDown 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:456:6:HAL_PWREx_DisableFlashPowerDown 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:481:6:HAL_PWREx_EnterSHUTDOWNMode 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:525:6:HAL_PWREx_BKUPWrite 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:546:10:HAL_PWREx_BKUPRead 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su (revision 41) @@ -0,0 +1,13 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:163:6:HAL_PWREx_EnableInternalWakeUpLine 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableInternalWakeUpLine 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:198:19:HAL_PWREx_EnableGPIOPullUp 4 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:254:19:HAL_PWREx_DisableGPIOPullUp 4 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:311:19:HAL_PWREx_EnableGPIOPullDown 4 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:367:19:HAL_PWREx_DisableGPIOPullDown 4 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:415:6:HAL_PWREx_EnablePullUpPullDownConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:426:6:HAL_PWREx_DisablePullUpPullDownConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:440:6:HAL_PWREx_EnableFlashPowerDown 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:456:6:HAL_PWREx_DisableFlashPowerDown 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:481:6:HAL_PWREx_EnterSHUTDOWNMode 0 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:525:6:HAL_PWREx_BKUPWrite 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:546:10:HAL_PWREx_BKUPRead 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo (revision 41) @@ -0,0 +1,15 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig 38 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig 21 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:996:10:HAL_RCC_GetHCLKFreq 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1009:10:HAL_RCC_GetPCLK1Freq 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1082:6:HAL_RCC_GetClockConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler 3 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su (revision 41) @@ -0,0 +1,15 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig 48 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:996:10:HAL_RCC_GetHCLKFreq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1009:10:HAL_RCC_GetPCLK1Freq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1082:6:HAL_RCC_GetClockConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig 14 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq 27 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:520:6:HAL_RCCEx_EnableLSCO 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su (revision 41) @@ -0,0 +1,5 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:520:6:HAL_RCCEx_EnableLSCO 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo (revision 41) @@ -0,0 +1,115 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7330:13:TIM_OC6_SetConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:380:13:HAL_TIM_Base_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:395:13:HAL_TIM_Base_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:337:19:HAL_TIM_Base_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:411:19:HAL_TIM_Base_Start 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:450:19:HAL_TIM_Base_Stop 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:470:19:HAL_TIM_Base_Start_IT 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:512:19:HAL_TIM_Base_Stop_IT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:537:19:HAL_TIM_Base_Start_DMA 10 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:606:19:HAL_TIM_Base_Stop_DMA 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:764:13:HAL_TIM_OC_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:779:13:HAL_TIM_OC_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:721:19:HAL_TIM_OC_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1448:13:HAL_TIM_PWM_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1390:19:HAL_TIM_PWM_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2101:13:HAL_TIM_IC_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2116:13:HAL_TIM_IC_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2058:19:HAL_TIM_IC_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2761:13:HAL_TIM_OnePulse_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2776:13:HAL_TIM_OnePulse_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2716:19:HAL_TIM_OnePulse_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2796:19:HAL_TIM_OnePulse_Start 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2853:19:HAL_TIM_OnePulse_Stop 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2896:19:HAL_TIM_OnePulse_Start_IT 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2959:19:HAL_TIM_OnePulse_Stop_IT 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3198:13:HAL_TIM_Encoder_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3213:13:HAL_TIM_Encoder_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3153:19:HAL_TIM_Encoder_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3233:19:HAL_TIM_Encoder_Start 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3327:19:HAL_TIM_Encoder_Stop 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3387:19:HAL_TIM_Encoder_Start_IT 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3487:19:HAL_TIM_Encoder_Stop_IT 7 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7385:26:TIM_SlaveTimer_SetConfig.constprop 10 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5678:19:HAL_TIM_SlaveConfigSynchro_IT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5638:19:HAL_TIM_SlaveConfigSynchro 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7845:6:TIM_CCxChannelCmd 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:802:19:HAL_TIM_OC_Start 21 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1471:19:HAL_TIM_PWM_Start 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:858:19:HAL_TIM_OC_Stop 14 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1527:19:HAL_TIM_PWM_Stop 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:893:19:HAL_TIM_OC_Start_IT 21 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:986:19:HAL_TIM_OC_Stop_IT 16 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1063:19:HAL_TIM_OC_Start_DMA 37 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1227:19:HAL_TIM_OC_Stop_DMA 16 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1895:19:HAL_TIM_PWM_Stop_DMA 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2137:19:HAL_TIM_IC_Start 19 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2189:19:HAL_TIM_IC_Stop 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2219:19:HAL_TIM_IC_Start_IT 19 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2311:19:HAL_TIM_IC_Stop_IT 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2383:19:HAL_TIM_IC_Start_DMA 32 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2542:19:HAL_TIM_IC_Stop_DMA 11 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su (revision 41) @@ -0,0 +1,115 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig 16 static 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:986:19:HAL_TIM_OC_Stop_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1063:19:HAL_TIM_OC_Start_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1227:19:HAL_TIM_OC_Stop_DMA 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1895:19:HAL_TIM_PWM_Stop_DMA 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2137:19:HAL_TIM_IC_Start 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2189:19:HAL_TIM_IC_Stop 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2219:19:HAL_TIM_IC_Start_IT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2311:19:HAL_TIM_IC_Stop_IT 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2383:19:HAL_TIM_IC_Start_DMA 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2542:19:HAL_TIM_IC_Stop_DMA 16 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo (revision 41) @@ -0,0 +1,48 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:313:13:HAL_TIMEx_HallSensor_MspDeInit 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:253:19:HAL_TIMEx_HallSensor_DeInit 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:328:19:HAL_TIMEx_HallSensor_Start 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:382:19:HAL_TIMEx_HallSensor_Stop 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:410:19:HAL_TIMEx_HallSensor_Start_IT 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:467:19:HAL_TIMEx_HallSensor_Stop_IT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:500:19:HAL_TIMEx_HallSensor_Start_DMA 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:576:19:HAL_TIMEx_HallSensor_Stop_DMA 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:638:19:HAL_TIMEx_OCN_Start 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:689:19:HAL_TIMEx_OCN_Stop 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:721:19:HAL_TIMEx_OCN_Start_IT 12 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:808:19:HAL_TIMEx_OCN_Stop_IT 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:883:19:HAL_TIMEx_OCN_Start_DMA 21 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1021:19:HAL_TIMEx_OCN_Stop_DMA 10 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1111:19:HAL_TIMEx_PWMN_Start 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1161:19:HAL_TIMEx_PWMN_Stop 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1193:19:HAL_TIMEx_PWMN_Start_IT 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1279:19:HAL_TIMEx_PWMN_Stop_IT 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Start_DMA 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1492:19:HAL_TIMEx_PWMN_Stop_DMA 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1583:19:HAL_TIMEx_OnePulseN_Start 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1632:19:HAL_TIMEx_OnePulseN_Stop 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1671:19:HAL_TIMEx_OnePulseN_Start_IT 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1726:19:HAL_TIMEx_OnePulseN_Stop_IT 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1811:19:HAL_TIMEx_ConfigCommutEvent 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1877:19:HAL_TIMEx_ConfigCommutEvent_IT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1944:19:HAL_TIMEx_ConfigCommutEvent_DMA 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1999:19:HAL_TIMEx_MasterConfigSynchronization 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2072:19:HAL_TIMEx_ConfigBreakDeadTime 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2140:19:HAL_TIMEx_ConfigBreakInput 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2251:19:HAL_TIMEx_RemapConfig 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2306:20:HAL_TIMEx_TISelection 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2348:19:HAL_TIMEx_GroupChannel5 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2386:19:HAL_TIMEx_DisarmBreakInput 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2440:19:HAL_TIMEx_ReArmBreakInput 11 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2529:13:HAL_TIMEx_CommutCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2543:13:HAL_TIMEx_CommutHalfCpltCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState 4 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su (revision 41) @@ -0,0 +1,48 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit 0 static 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static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo (revision 41) @@ -0,0 +1,70 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT.part.0 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT 3 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN 5 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:457:19:HAL_LIN_Init 7 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:556:19:HAL_MultiProcessor_Init 6 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT 14 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3555:19:UART_Start_Receive_DMA 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA 8 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su (revision 41) @@ -0,0 +1,70 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT.part.0 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4166:13:UART_TxISR_16BIT_FIFOEN 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:679:13:HAL_UART_MspInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:694:13:HAL_UART_MspDeInit 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:632:19:HAL_UART_DeInit 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1332:19:HAL_UART_Transmit_IT 12 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1471:19:HAL_UART_Transmit_DMA 32 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1601:19:HAL_UART_DMAPause 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1631:19:HAL_UART_DMAResume 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1662:19:HAL_UART_DMAStop 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1738:19:HAL_UART_Abort 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1843:19:HAL_UART_AbortTransmit 16 static,ignoring_inline_asm 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+D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2959:6:HAL_MultiProcessor_EnterMuteMode 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2969:19:HAL_HalfDuplex_EnableTransmitter 20 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2992:19:HAL_HalfDuplex_EnableReceiver 20 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3016:19:HAL_LIN_SendBreak 8 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3061:23:HAL_UART_GetState 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3077:10:HAL_UART_GetError 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3123:19:UART_SetConfig 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3269:6:UART_AdvFeatureConfig 12 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1126:19:HAL_UART_Transmit 48 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1232:19:HAL_UART_Receive 48 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3345:19:UART_CheckIdleState 24 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:307:19:HAL_UART_Init 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:382:19:HAL_HalfDuplex_Init 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:457:19:HAL_LIN_Init 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:556:19:HAL_MultiProcessor_Init 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3555:19:UART_Start_Receive_DMA 24 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA 16 static,ignoring_inline_asm Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo (revision 41) @@ -0,0 +1,17 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 5 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 1 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 2 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle 21 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT 8 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA 9 +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d (revision 41) @@ -0,0 +1,70 @@ +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o: \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su (revision 41) @@ -0,0 +1,17 @@ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 32 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 0 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 8 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 16 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 24 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle 40 static +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA 16 static,ignoring_inline_asm +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/Drivers/STM32C0xx_HAL_Driver/subdir.mk (revision 41) @@ -0,0 +1,112 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c \ +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d \ +./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o: D:/Projekte/ecs_PowerPro/trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c Drivers/STM32C0xx_HAL_Driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32C0xx_HAL_Driver + +clean-Drivers-2f-STM32C0xx_HAL_Driver: + -$(RM) ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.su ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.d ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.su + +.PHONY: clean-Drivers-2f-STM32C0xx_HAL_Driver + Index: /trunk/firmware_v3/STM32CubeIDE/Release/firmware_v2.map =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/firmware_v2.map (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/firmware_v2.map (revision 41) @@ -0,0 +1,2156 @@ +Archive member included to satisfy reference by file (symbol) + +C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + 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C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00003000 xrw +FLASH 0x08000000 0x00004000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD ./Application/User/Core/adc.o +LOAD ./Application/User/Core/dma.o +LOAD ./Application/User/Core/gpio.o +LOAD ./Application/User/Core/main.o +LOAD ./Application/User/Core/stm32c0xx_hal_msp.o +LOAD ./Application/User/Core/stm32c0xx_it.o +LOAD ./Application/User/Core/syscalls.o +LOAD ./Application/User/Core/sysmem.o +LOAD ./Application/User/Core/tim.o +LOAD ./Application/User/Core/usart.o +LOAD ./Application/User/Startup/startup_stm32c031k4tx.o +LOAD ./Drivers/CMSIS/system_stm32c0xx.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o +LOAD ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o +LOAD ./src/button.o +LOAD ./src/buzzer.o +LOAD ./src/leds.o +LOAD ./src/main.o +LOAD ./src/mode_mainswitch.o +LOAD ./src/mode_secondaryprotection.o +LOAD ./src/modeswitch.o +LOAD ./src/relais.o +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtend.o +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o + 0x20003000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0xc0 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0xc0 ./Application/User/Startup/startup_stm32c031k4tx.o + 0x08000000 g_pfnVectors + 0x080000c0 . = ALIGN (0x4) + +.text 0x080000c0 0x25c0 + 0x080000c0 . = ALIGN (0x4) + *(.text) + .text 0x080000c0 0x48 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x08000108 0x14 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_thumb1_case_uqi.o) + 0x08000108 __gnu_thumb1_case_uqi + .text 0x0800011c 0x114 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + 0x0800011c __aeabi_uidiv + 0x0800011c __udivsi3 + 0x08000228 __aeabi_uidivmod + .text 0x08000230 0x1d4 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + 0x08000230 __divsi3 + 0x08000230 __aeabi_idiv + 0x080003fc __aeabi_idivmod + .text 0x08000404 0x4 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + 0x08000404 __aeabi_idiv0 + 0x08000404 __aeabi_ldiv0 + *(.text*) + .text.MX_ADC1_Init + 0x08000408 0xec ./Application/User/Core/adc.o + 0x08000408 MX_ADC1_Init + .text.HAL_ADC_MspInit + 0x080004f4 0xb4 ./Application/User/Core/adc.o + 0x080004f4 HAL_ADC_MspInit + .text.MX_DMA_Init + 0x080005a8 0x2c ./Application/User/Core/dma.o + 0x080005a8 MX_DMA_Init + .text.MX_GPIO_Init + 0x080005d4 0xec ./Application/User/Core/gpio.o + 0x080005d4 MX_GPIO_Init + .text.SystemClock_Config + 0x080006c0 0x64 ./Application/User/Core/main.o + 0x080006c0 SystemClock_Config + .text.startup.main + 0x08000724 0x24 ./Application/User/Core/main.o + 0x08000724 main + .text.Error_Handler + 0x08000748 0x4 ./Application/User/Core/main.o + 0x08000748 Error_Handler + .text.HAL_MspInit + 0x0800074c 0x30 ./Application/User/Core/stm32c0xx_hal_msp.o + 0x0800074c HAL_MspInit + .text.NMI_Handler + 0x0800077c 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x0800077c NMI_Handler + .text.HardFault_Handler + 0x0800077e 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x0800077e HardFault_Handler + .text.SVC_Handler + 0x08000780 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x08000780 SVC_Handler + .text.PendSV_Handler + 0x08000782 0x2 ./Application/User/Core/stm32c0xx_it.o + 0x08000782 PendSV_Handler + .text.SysTick_Handler + 0x08000784 0x8 ./Application/User/Core/stm32c0xx_it.o + 0x08000784 SysTick_Handler + .text.DMA1_Channel1_IRQHandler + 0x0800078c 0x10 ./Application/User/Core/stm32c0xx_it.o + 0x0800078c DMA1_Channel1_IRQHandler + .text.MX_TIM16_Init + 0x0800079c 0x68 ./Application/User/Core/tim.o + 0x0800079c MX_TIM16_Init + .text.HAL_TIM_Base_MspInit + 0x08000804 0x80 ./Application/User/Core/tim.o + 0x08000804 HAL_TIM_Base_MspInit + .text.HAL_TIM_MspPostInit + 0x08000884 0x4c ./Application/User/Core/tim.o + 0x08000884 HAL_TIM_MspPostInit + .text.MX_TIM17_Init + 0x080008d0 0xa8 ./Application/User/Core/tim.o + 0x080008d0 MX_TIM17_Init + .text.MX_USART1_UART_Init + 0x08000978 0x6c ./Application/User/Core/usart.o + 0x08000978 MX_USART1_UART_Init + .text.HAL_UART_MspInit + 0x080009e4 0x9c ./Application/User/Core/usart.o + 0x080009e4 HAL_UART_MspInit + .text.Reset_Handler + 0x08000a80 0x50 ./Application/User/Startup/startup_stm32c031k4tx.o + 0x08000a80 Reset_Handler + .text.Default_Handler + 0x08000ad0 0x2 ./Application/User/Startup/startup_stm32c031k4tx.o + 0x08000ad0 TIM1_CC_IRQHandler + 0x08000ad0 I2C1_IRQHandler + 0x08000ad0 DMAMUX1_IRQHandler + 0x08000ad0 SPI1_IRQHandler + 0x08000ad0 EXTI2_3_IRQHandler + 0x08000ad0 ADC1_IRQHandler + 0x08000ad0 TIM17_IRQHandler + 0x08000ad0 RTC_IRQHandler + 0x08000ad0 TIM16_IRQHandler + 0x08000ad0 TIM3_IRQHandler + 0x08000ad0 EXTI4_15_IRQHandler + 0x08000ad0 RCC_IRQHandler + 0x08000ad0 Default_Handler + 0x08000ad0 TIM14_IRQHandler + 0x08000ad0 EXTI0_1_IRQHandler + 0x08000ad0 WWDG_IRQHandler + 0x08000ad0 DMA1_Channel2_3_IRQHandler + 0x08000ad0 USART2_IRQHandler + 0x08000ad0 FLASH_IRQHandler + 0x08000ad0 USART1_IRQHandler + 0x08000ad0 TIM1_BRK_UP_TRG_COM_IRQHandler + *fill* 0x08000ad2 0x2 + .text.SystemInit + 0x08000ad4 0x10 ./Drivers/CMSIS/system_stm32c0xx.o + 0x08000ad4 SystemInit + .text.HAL_InitTick + 0x08000ae4 0x50 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000ae4 HAL_InitTick + .text.HAL_Init + 0x08000b34 0x18 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000b34 HAL_Init + .text.HAL_IncTick + 0x08000b4c 0x18 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000b4c HAL_IncTick + .text.HAL_GetTick + 0x08000b64 0xc ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x08000b64 HAL_GetTick + .text.LL_ADC_REG_IsConversionOngoing + 0x08000b70 0x8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .text.HAL_ADC_Init + 0x08000b78 0x220 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + 0x08000b78 HAL_ADC_Init + .text.HAL_ADC_ConfigChannel + 0x08000d98 0x248 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + 0x08000d98 HAL_ADC_ConfigChannel + .text.HAL_NVIC_SetPriority + 0x08000fe0 0x54 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + 0x08000fe0 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x08001034 0x18 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + 0x08001034 HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x0800104c 0x34 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + 0x0800104c HAL_SYSTICK_Config + .text.DMA_CalcDMAMUXChannelBaseAndMask + 0x08001080 0x34 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .text.HAL_DMA_Init + 0x080010b4 0xb4 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + 0x080010b4 HAL_DMA_Init + .text.HAL_DMA_IRQHandler + 0x08001168 0xa8 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + 0x08001168 HAL_DMA_IRQHandler + .text.HAL_GPIO_Init + 0x08001210 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HAL_RCCEx_PeriphCLKConfig + .text.TIM_OC1_SetConfig + 0x08001904 0x6c ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC3_SetConfig + 0x08001970 0x84 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x080019f4 0x68 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC5_SetConfig + 0x08001a5c 0x60 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.TIM_OC6_SetConfig + 0x08001abc 0x68 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .text.HAL_TIM_PWM_MspInit + 0x08001b24 0x2 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + 0x08001b24 HAL_TIM_PWM_MspInit + .text.HAL_TIM_IC_MspInit + 0x08001b26 0x2 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + 0x08001b26 HAL_TIM_IC_MspInit + .text.TIM_Base_SetConfig + 0x08001b28 0x84 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + 0x08001b28 TIM_Base_SetConfig + .text.HAL_TIM_Base_Init + 0x08001bac 0x54 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + 0x08001bac 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C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08002714 . = ALIGN (0x4) + 0x08002714 _sidata = LOADADDR (.data) + +.rel.dyn 0x08002714 0x0 + .rel.iplt 0x08002714 0x0 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o + +.data 0x20000000 0xc load address 0x08002714 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Drivers/CMSIS/system_stm32c0xx.o + 0x20000000 SystemCoreClock + .data.uwTickFreq + 0x20000004 0x1 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + 0x20000004 uwTickFreq + *fill* 0x20000005 0x3 + .data.uwTickPrio + 0x20000008 0x4 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C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_thumb1_case_uqi.o) + .ARM.attributes + 0x00000452 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .ARM.attributes + 0x00000470 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + .ARM.attributes + 0x0000048e 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000004ac 0x1e C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(firmware_v2.elf elf32-littlearm) +LOAD linker stubs +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +LOAD C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Application/User/Core/adc.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Application/User/Core/dma.o + .comment 0x00000043 0x44 ./Application/User/Core/gpio.o + .comment 0x00000043 0x44 ./Application/User/Core/main.o + .comment 0x00000043 0x44 ./Application/User/Core/stm32c0xx_hal_msp.o + .comment 0x00000043 0x44 ./Application/User/Core/stm32c0xx_it.o + .comment 0x00000043 0x44 ./Application/User/Core/tim.o + .comment 0x00000043 0x44 ./Application/User/Core/usart.o + .comment 0x00000043 0x44 ./Drivers/CMSIS/system_stm32c0xx.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o + .comment 0x00000043 0x44 ./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o + +.debug_frame 0x00000000 0x8c + .debug_frame 0x00000000 0x20 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .debug_frame 0x00000020 0x2c C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .debug_frame 0x0000004c 0x20 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .debug_frame 0x0000006c 0x20 C:/ST/STM32CubeIDE_1.19.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.0.202411081344/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) Index: /trunk/firmware_v3/STM32CubeIDE/Release/makefile =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/makefile (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/makefile (revision 41) @@ -0,0 +1,96 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include src/subdir.mk +-include Drivers/STM32C0xx_HAL_Driver/subdir.mk +-include Drivers/CMSIS/subdir.mk +-include Application/User/Startup/subdir.mk +-include Application/User/Core/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := firmware_v2 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +firmware_v2.elf \ + +MAP_FILES += \ +firmware_v2.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +firmware_v2.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: firmware_v2.elf secondary-outputs + +# Tool invocations +firmware_v2.elf firmware_v2.map: $(OBJS) $(USER_OBJS) D:\Projekte\ecs_PowerPro\trunk\firmware_v2\STM32CubeIDE\STM32C031K4TX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "firmware_v2.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"D:\Projekte\ecs_PowerPro\trunk\firmware_v2\STM32CubeIDE\STM32C031K4TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="firmware_v2.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +firmware_v2.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "firmware_v2.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) default.size.stdout firmware_v2.elf firmware_v2.list firmware_v2.map + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets Index: /trunk/firmware_v3/STM32CubeIDE/Release/objects.list =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/objects.list (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/objects.list (revision 41) @@ -0,0 +1,38 @@ +"./Application/User/Core/adc.o" +"./Application/User/Core/dma.o" +"./Application/User/Core/gpio.o" +"./Application/User/Core/main.o" +"./Application/User/Core/stm32c0xx_hal_msp.o" +"./Application/User/Core/stm32c0xx_it.o" +"./Application/User/Core/syscalls.o" +"./Application/User/Core/sysmem.o" +"./Application/User/Core/tim.o" +"./Application/User/Core/usart.o" +"./Application/User/Startup/startup_stm32c031k4tx.o" +"./Drivers/CMSIS/system_stm32c0xx.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_adc_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_cortex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_dma_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_exti.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_flash_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_gpio.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_pwr_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_rcc_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_tim_ex.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart.o" +"./Drivers/STM32C0xx_HAL_Driver/stm32c0xx_hal_uart_ex.o" +"./src/button.o" +"./src/buzzer.o" +"./src/leds.o" +"./src/main.o" +"./src/mode_mainswitch.o" +"./src/mode_secondaryprotection.o" +"./src/modeswitch.o" +"./src/relais.o" Index: /trunk/firmware_v3/STM32CubeIDE/Release/objects.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/objects.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/objects.mk (revision 41) @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + Index: /trunk/firmware_v3/STM32CubeIDE/Release/sources.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/sources.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/sources.mk (revision 41) @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Application/User/Core \ +Application/User/Startup \ +Drivers/CMSIS \ +Drivers/STM32C0xx_HAL_Driver \ +src \ + Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/button.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/button.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/button.cyclo (revision 41) @@ -0,0 +1,3 @@ +../src/button.c:15:16:BUTTON_Exec 11 +../src/button.c:76:16:BUTTON_GetMode 1 +../src/button.c:81:6:BUTTON_SetModeOff 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/button.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/button.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/button.d (revision 41) @@ -0,0 +1,73 @@ +src/button.o: ../src/button.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/button.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/button.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/button.su (revision 41) @@ -0,0 +1,3 @@ +../src/button.c:15:16:BUTTON_Exec 16 static +../src/button.c:76:16:BUTTON_GetMode 0 static +../src/button.c:81:6:BUTTON_SetModeOff 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.cyclo (revision 41) @@ -0,0 +1,4 @@ +../src/buzzer.c:12:6:BUZZER_Exec 6 +../src/buzzer.c:39:6:BUZZER_Beep 1 +../src/buzzer.c:46:6:BUZZER_Alarm_Start 1 +../src/buzzer.c:57:6:BUZZER_Alarm_Stop 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.d (revision 41) @@ -0,0 +1,72 @@ +src/buzzer.o: ../src/buzzer.c ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/buzzer.su (revision 41) @@ -0,0 +1,4 @@ +../src/buzzer.c:12:6:BUZZER_Exec 16 static +../src/buzzer.c:39:6:BUZZER_Beep 8 static +../src/buzzer.c:46:6:BUZZER_Alarm_Start 8 static +../src/buzzer.c:57:6:BUZZER_Alarm_Stop 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.cyclo (revision 41) @@ -0,0 +1,9 @@ +../src/leds.c:17:6:LEDS_Exec 11 +../src/leds.c:66:6:LEDS_GN_On 1 +../src/leds.c:77:6:LEDS_GN_Flash 1 +../src/leds.c:83:6:LEDS_GN_Blink_Start 1 +../src/leds.c:93:6:LEDS_GN_Off 1 +../src/leds.c:104:6:LEDS_RT_On 1 +../src/leds.c:115:6:LEDS_RT_Flash 1 +../src/leds.c:121:6:LEDS_RT_Blink_Start 1 +../src/leds.c:131:6:LEDS_RT_Off 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.d (revision 41) @@ -0,0 +1,72 @@ +src/leds.o: ../src/leds.c ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/leds.su (revision 41) @@ -0,0 +1,9 @@ +../src/leds.c:17:6:LEDS_Exec 16 static +../src/leds.c:66:6:LEDS_GN_On 8 static +../src/leds.c:77:6:LEDS_GN_Flash 8 static +../src/leds.c:83:6:LEDS_GN_Blink_Start 8 static +../src/leds.c:93:6:LEDS_GN_Off 8 static +../src/leds.c:104:6:LEDS_RT_On 8 static +../src/leds.c:115:6:LEDS_RT_Flash 8 static +../src/leds.c:121:6:LEDS_RT_Blink_Start 8 static +../src/leds.c:131:6:LEDS_RT_Off 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/main.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/main.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/main.cyclo (revision 41) @@ -0,0 +1,3 @@ +../src/main.c:162:6:SystemClock_Config 3 +../src/main.c:72:5:main 4 +../src/main.c:261:6:Error_Handler 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/main.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/main.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/main.d (revision 41) @@ -0,0 +1,84 @@ +src/main.o: ../src/main.c ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/main.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/main.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/main.su (revision 41) @@ -0,0 +1,3 @@ +../src/main.c:162:6:SystemClock_Config 56 static,ignoring_inline_asm +../src/main.c:72:5:main 48 static +../src/main.c:261:6:Error_Handler 0 static,ignoring_inline_asm Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.cyclo (revision 41) @@ -0,0 +1,5 @@ +../src/mode_mainswitch.c:42:6:MAINSWITCH_SM_Off 4 +../src/mode_mainswitch.c:97:6:MAINSWITCH_SM_On 3 +../src/mode_mainswitch.c:137:6:MAINSWITCH_SM_ManualOn 2 +../src/mode_mainswitch.c:153:6:MAINSWITCH_SM_Error 4 +../src/mode_mainswitch.c:207:6:MODE_MAINSWITCH_Exec 5 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.d (revision 41) @@ -0,0 +1,81 @@ +src/mode_mainswitch.o: ../src/mode_mainswitch.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_mainswitch.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_mainswitch.su (revision 41) @@ -0,0 +1,5 @@ +../src/mode_mainswitch.c:42:6:MAINSWITCH_SM_Off 16 static +../src/mode_mainswitch.c:97:6:MAINSWITCH_SM_On 16 static +../src/mode_mainswitch.c:137:6:MAINSWITCH_SM_ManualOn 8 static +../src/mode_mainswitch.c:153:6:MAINSWITCH_SM_Error 16 static +../src/mode_mainswitch.c:207:6:MODE_MAINSWITCH_Exec 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.cyclo (revision 41) @@ -0,0 +1,5 @@ +../src/mode_secondaryprotection.c:41:6:SECONDARYPROTECTION_SM_Off 5 +../src/mode_secondaryprotection.c:106:6:SECONDARYPROTECTION_SM_On 8 +../src/mode_secondaryprotection.c:183:6:SECONDARYPROTECTION_SM_ManualOn 2 +../src/mode_secondaryprotection.c:199:6:SECONDARYPROTECTION_SM_Error 4 +../src/mode_secondaryprotection.c:255:6:MODE_SECONDARYPROTECTION_Exec 5 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.d (revision 41) @@ -0,0 +1,81 @@ +src/mode_secondaryprotection.o: ../src/mode_secondaryprotection.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/mode_secondaryprotection.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/button.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/leds.h: +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/buzzer.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/mode_secondaryprotection.su (revision 41) @@ -0,0 +1,5 @@ +../src/mode_secondaryprotection.c:41:6:SECONDARYPROTECTION_SM_Off 16 static +../src/mode_secondaryprotection.c:106:6:SECONDARYPROTECTION_SM_On 16 static +../src/mode_secondaryprotection.c:183:6:SECONDARYPROTECTION_SM_ManualOn 8 static +../src/mode_secondaryprotection.c:199:6:SECONDARYPROTECTION_SM_Error 16 static +../src/mode_secondaryprotection.c:255:6:MODE_SECONDARYPROTECTION_Exec 8 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.cyclo (revision 41) @@ -0,0 +1,2 @@ +../src/modeswitch.c:8:19:MODESWITCH_ReadMode 1 +../src/modeswitch.c:27:19:MODESWITCH_GetMode 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.d (revision 41) @@ -0,0 +1,73 @@ +src/modeswitch.o: ../src/modeswitch.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/modeswitch.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/modeswitch.su (revision 41) @@ -0,0 +1,2 @@ +../src/modeswitch.c:8:19:MODESWITCH_ReadMode 24 static +../src/modeswitch.c:27:19:MODESWITCH_GetMode 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.cyclo =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.cyclo (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.cyclo (revision 41) @@ -0,0 +1,4 @@ +../src/relais.c:14:6:RELAIS_Exec 5 +../src/relais.c:39:6:RELAIS_SetPuls 1 +../src/relais.c:52:6:RELAIS_ResetPuls 1 +../src/relais.c:66:14:RELAIS_GetState 1 Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.d =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.d (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.d (revision 41) @@ -0,0 +1,73 @@ +src/relais.o: ../src/relais.c \ + D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h \ + ../../Core/Inc/main.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h \ + ../../Drivers/CMSIS/Include/core_cm0plus.h \ + ../../Drivers/CMSIS/Include/cmsis_version.h \ + ../../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../../Drivers/CMSIS/Include/mpu_armv7.h \ + ../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h \ + ../../Core/Inc/stm32c0xx_hal_conf.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h \ + ../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h +D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc/relais.h: +../../Core/Inc/main.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h: +../../Drivers/CMSIS/Include/core_cm0plus.h: +../../Drivers/CMSIS/Include/cmsis_version.h: +../../Drivers/CMSIS/Include/cmsis_compiler.h: +../../Drivers/CMSIS/Include/cmsis_gcc.h: +../../Drivers/CMSIS/Include/mpu_armv7.h: +../../Drivers/CMSIS/Device/ST/STM32C0xx/Include/system_stm32c0xx.h: +../../Core/Inc/stm32c0xx_hal_conf.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pwr_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim_ex.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h: +../../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart_ex.h: Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.su =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.su (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/relais.su (revision 41) @@ -0,0 +1,4 @@ +../src/relais.c:14:6:RELAIS_Exec 8 static +../src/relais.c:39:6:RELAIS_SetPuls 8 static +../src/relais.c:52:6:RELAIS_ResetPuls 8 static +../src/relais.c:66:14:RELAIS_GetState 0 static Index: /trunk/firmware_v3/STM32CubeIDE/Release/src/subdir.mk =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/Release/src/subdir.mk (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/Release/src/subdir.mk (revision 41) @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../src/button.c \ +../src/buzzer.c \ +../src/leds.c \ +../src/main.c \ +../src/mode_mainswitch.c \ +../src/mode_secondaryprotection.c \ +../src/modeswitch.c \ +../src/relais.c + +OBJS += \ +./src/button.o \ +./src/buzzer.o \ +./src/leds.o \ +./src/main.o \ +./src/mode_mainswitch.o \ +./src/mode_secondaryprotection.o \ +./src/modeswitch.o \ +./src/relais.o + +C_DEPS += \ +./src/button.d \ +./src/buzzer.d \ +./src/leds.d \ +./src/main.d \ +./src/mode_mainswitch.d \ +./src/mode_secondaryprotection.d \ +./src/modeswitch.d \ +./src/relais.d + + +# Each subdirectory must supply rules for building sources it contributes +src/%.o src/%.su src/%.cyclo: ../src/%.c src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -DUSE_HAL_DRIVER -DSTM32C031xx -c -I../../Core/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc -I../../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../../Drivers/CMSIS/Include -I"D:/Projekte/ecs_PowerPro/trunk/firmware_v2/STM32CubeIDE/inc" -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-src + +clean-src: + -$(RM) ./src/button.cyclo ./src/button.d ./src/button.o ./src/button.su ./src/buzzer.cyclo ./src/buzzer.d ./src/buzzer.o ./src/buzzer.su ./src/leds.cyclo ./src/leds.d ./src/leds.o ./src/leds.su ./src/main.cyclo ./src/main.d ./src/main.o ./src/main.su ./src/mode_mainswitch.cyclo ./src/mode_mainswitch.d ./src/mode_mainswitch.o ./src/mode_mainswitch.su ./src/mode_secondaryprotection.cyclo ./src/mode_secondaryprotection.d ./src/mode_secondaryprotection.o ./src/mode_secondaryprotection.su ./src/modeswitch.cyclo ./src/modeswitch.d ./src/modeswitch.o ./src/modeswitch.su ./src/relais.cyclo ./src/relais.d ./src/relais.o ./src/relais.su + +.PHONY: clean-src + Index: /trunk/firmware_v3/STM32CubeIDE/STM32C031K4TX_FLASH.ld =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/STM32C031K4TX_FLASH.ld (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/STM32C031K4TX_FLASH.ld (revision 41) @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32C031K4Tx Device from STM32C0 series +** 16KBytes FLASH +** 12KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 16K +} + +/* Sections */ +SECTIONS +{ + + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} Index: /trunk/firmware_v3/STM32CubeIDE/firmware_v2_debug.launch =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/firmware_v2_debug.launch (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/firmware_v2_debug.launch (revision 41) @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /trunk/firmware_v3/STM32CubeIDE/firmware_v2_release.launch =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/firmware_v2_release.launch (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/firmware_v2_release.launch (revision 41) @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /trunk/firmware_v3/STM32CubeIDE/inc/button.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/button.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/button.h (revision 41) @@ -0,0 +1,19 @@ +#ifndef __BUTTON_H +#define __BUTTON_H + + + + +typedef enum BUTTON_State_enum +{ + BUTTON_OFF, + BUTTON_AUTO, + BUTTON_MANUAL_ON +} button_state_t; + + +button_state_t BUTTON_Exec(void); +button_state_t BUTTON_GetMode(void); +void BUTTON_SetModeOff(void); + +#endif Index: /trunk/firmware_v3/STM32CubeIDE/inc/buzzer.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/buzzer.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/buzzer.h (revision 41) @@ -0,0 +1,11 @@ +#ifndef __BUZZER_H +#define __BUZZER_H + + +void BUZZER_Exec(void); +void BUZZER_Beep(unsigned int time); +void BUZZER_Alarm_Start(unsigned int on, unsigned int off ); +void BUZZER_Alarm_Stop(void); + + +#endif Index: /trunk/firmware_v3/STM32CubeIDE/inc/leds.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/leds.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/leds.h (revision 41) @@ -0,0 +1,20 @@ +#ifndef __LEDS_H +#define __LEDS_H + + + +void LEDS_Exec(void); +void LEDS_GN_On(void); +void LEDS_GN_Off(void); +void LEDS_GN_Flash(unsigned int time); +void LEDS_GN_Blink_Start(unsigned int on, unsigned int off ); + + +void LEDS_RT_On(void); +void LEDS_RT_Off(void); +void LEDS_RT_Flash(unsigned int time); +void LEDS_RT_Blink_Start(unsigned int on, unsigned int off ); + + +#endif + Index: /trunk/firmware_v3/STM32CubeIDE/inc/main.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/main.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/main.h (revision 41) @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define GPIO_INPUT_MODE_B3_Pin GPIO_PIN_7 +#define GPIO_INPUT_MODE_B3_GPIO_Port GPIOB +#define GPIO_INPUT_MODE_B1_Pin GPIO_PIN_14 +#define GPIO_INPUT_MODE_B1_GPIO_Port GPIOC +#define GPIO_INPUT_MODE_B0_Pin GPIO_PIN_15 +#define GPIO_INPUT_MODE_B0_GPIO_Port GPIOC +#define GPIO_INPUT_LVP_Pin GPIO_PIN_0 +#define GPIO_INPUT_LVP_GPIO_Port GPIOA +#define GPIO_INPUT_OVP_Pin GPIO_PIN_1 +#define GPIO_INPUT_OVP_GPIO_Port GPIOA +#define GPIO_INPUT_BTN_ON_Pin GPIO_PIN_2 +#define GPIO_INPUT_BTN_ON_GPIO_Port GPIOA +#define GPIO_INPUT_BTN_OFF_Pin GPIO_PIN_3 +#define GPIO_INPUT_BTN_OFF_GPIO_Port GPIOA +#define GPIO_OUTPUT_LED_ON_Pin GPIO_PIN_4 +#define GPIO_OUTPUT_LED_ON_GPIO_Port GPIOA +#define GPIO_OUTPUT_LED_ERROR_Pin GPIO_PIN_5 +#define GPIO_OUTPUT_LED_ERROR_GPIO_Port GPIOA +#define GPIO_INPUT_FAULT_Pin GPIO_PIN_6 +#define GPIO_INPUT_FAULT_GPIO_Port GPIOA +#define GPIO_OUTPUT_RELAIS_SET_Pin GPIO_PIN_7 +#define GPIO_OUTPUT_RELAIS_SET_GPIO_Port GPIOA +#define GPIO_OUTPUT_RELAIS_RESET_Pin GPIO_PIN_8 +#define GPIO_OUTPUT_RELAIS_RESET_GPIO_Port GPIOA +#define GPIO_OUTPUT_BUZZER_Pin GPIO_PIN_11 +#define GPIO_OUTPUT_BUZZER_GPIO_Port GPIOA +#define GPIO_INPUT_BMS_Pin GPIO_PIN_12 +#define GPIO_INPUT_BMS_GPIO_Port GPIOA +#define GPIO_INPUT_MODE_B2_Pin GPIO_PIN_6 +#define GPIO_INPUT_MODE_B2_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ Index: /trunk/firmware_v3/STM32CubeIDE/inc/mode_mainswitch.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/mode_mainswitch.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/mode_mainswitch.h (revision 41) @@ -0,0 +1,10 @@ +#ifndef __MODE_MAINSWITCH_H +#define __MODE_MAINSWITCH_H + + +void MODE_MAINSWITCH_Exec(void); + + +#endif + + Index: /trunk/firmware_v3/STM32CubeIDE/inc/mode_secondaryprotection.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/mode_secondaryprotection.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/mode_secondaryprotection.h (revision 41) @@ -0,0 +1,9 @@ +#ifndef __MODE_SECONDARYPROTECTION_H +#define __MODE_SECONDARYPROTECTION_H + +void MODE_SECONDARYPROTECTION_Exec(void); + + +#endif + + Index: /trunk/firmware_v3/STM32CubeIDE/inc/modeswitch.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/modeswitch.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/modeswitch.h (revision 41) @@ -0,0 +1,25 @@ +#ifndef __MODESWITCH_H +#define __MODESWITCH_H + + + + +typedef enum MODESWITCH_mode_enum +{ + MODE_MAINSWITCH = 0, + MODE_MAINSWITCH_SECONDARYPROTECTION, + MODE_MAINSWITCH_OVP_LVP, + MODE_MAINSWITCH_OVP, + MODE_MAINSWITCH_LVP, +} MODESWITCH_mode_t; + + +MODESWITCH_mode_t MODESWITCH_ReadMode(void); +MODESWITCH_mode_t MODESWITCH_GetMode(void); + + + + + + +#endif Index: /trunk/firmware_v3/STM32CubeIDE/inc/relais.h =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/inc/relais.h (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/inc/relais.h (revision 41) @@ -0,0 +1,15 @@ +#ifndef __RELAIS_H +#define __RELAIS_H + + +void RELAIS_Exec(void); +void RELAIS_SetPuls(void); +void RELAIS_ResetPuls(void); +unsigned int RELAIS_GetState(void); + + + +#endif + + + Index: /trunk/firmware_v3/STM32CubeIDE/src/button.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/button.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/button.c (revision 41) @@ -0,0 +1,84 @@ +#include +#include "button.h" +#include "main.h" + +#define LONG_PRESS_TIME 5000 +#define MIN_PRESS_TIME 10 + +button_state_t buttonState; +uint32_t longPressCounterButtonOn; +uint32_t longPressCounterButtonOff; + + +// Diese funktion muss regelmäßig aufgerufen werden um die Taster abzufragen. +// 1ms +button_state_t BUTTON_Exec(void) +{ + + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_SET) + { + //Taste On wird gedrückt + longPressCounterButtonOn++; + } + + + if (longPressCounterButtonOn > LONG_PRESS_TIME) + { + + if (buttonState != BUTTON_MANUAL_ON) + { + printf("BUTTON: Auto Mode Manual On\n"); + buttonState = BUTTON_MANUAL_ON; + } + } + else if ( (longPressCounterButtonOn > MIN_PRESS_TIME) && (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET)) + { + //Taste On wurde for 10m gesdrückt und losgelassen + if (buttonState != BUTTON_AUTO) + { + printf("BUTTON: Auto Mode\n"); + buttonState = BUTTON_AUTO; + } + } + + + + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_ON_GPIO_Port, GPIO_INPUT_BTN_ON_Pin) == GPIO_PIN_RESET) + { + longPressCounterButtonOn = 0; + } + + + // ------ Taste OFF ----- + if (HAL_GPIO_ReadPin(GPIO_INPUT_BTN_OFF_GPIO_Port, GPIO_INPUT_BTN_OFF_Pin) == GPIO_PIN_SET) + { + //Taste Off wird gedrückt + longPressCounterButtonOff++; + if (longPressCounterButtonOff > MIN_PRESS_TIME) + { + if (buttonState != BUTTON_OFF) + { + printf("BUTTON: Off Mode\n"); + buttonState = BUTTON_OFF; + } + } + } + else + { + longPressCounterButtonOff = 0; + } + + return buttonState; + +} + + +button_state_t BUTTON_GetMode(void) +{ + return buttonState; +} + +void BUTTON_SetModeOff(void) +{ + buttonState = BUTTON_OFF; +} Index: /trunk/firmware_v3/STM32CubeIDE/src/buzzer.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/buzzer.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/buzzer.c (revision 41) @@ -0,0 +1,64 @@ +#include "main.h" +#include "buzzer.h" + +unsigned int onTimeCounter; +unsigned int offTimeCounter; +unsigned int onTime; +unsigned int offTime; +unsigned int alarmMode; + + + +void BUZZER_Exec(void) +{ + + if (onTimeCounter > 0) + { + onTimeCounter--; + if (onTimeCounter == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + + if (alarmMode == 1) offTimeCounter = offTime; + } + } + + if (offTimeCounter > 0) + { + offTimeCounter--; + if (offTimeCounter == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = onTime; + } + } +} + + + +void BUZZER_Beep(unsigned int time) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = time; + +} + +void BUZZER_Alarm_Start(unsigned int on, unsigned int off ) +{ + onTime = on; + offTime = off; + alarmMode = 1; + + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + onTimeCounter = on; + +} + +void BUZZER_Alarm_Stop(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + alarmMode = 0; + offTimeCounter = 0; + onTimeCounter = 0; + +} Index: /trunk/firmware_v3/STM32CubeIDE/src/leds.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/leds.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/leds.c (revision 41) @@ -0,0 +1,137 @@ +#include "main.h" +#include "leds.h" + +unsigned int onTimeCounterGN; +unsigned int offTimeCounterGN; +unsigned int onTimeGN; +unsigned int offTimeGN; +unsigned int blinkModeGN; + + +unsigned int onTimeCounterRT; +unsigned int offTimeCounterRT; +unsigned int onTimeRT; +unsigned int offTimeRT; +unsigned int blinkModeRT; + +void LEDS_Exec(void) +{ + + if (onTimeCounterGN > 0) + { + onTimeCounterGN--; + if (onTimeCounterGN == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + + if (blinkModeGN == 1) offTimeCounterGN = offTimeGN; + } + } + + if (offTimeCounterGN > 0) + { + offTimeCounterGN--; + if (offTimeCounterGN == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = onTimeGN; + } + } + + + // --- LED ROT --- + if (onTimeCounterRT > 0) + { + onTimeCounterRT--; + if (onTimeCounterRT == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + + if (blinkModeRT == 1) offTimeCounterRT = offTimeRT; + } + } + + if (offTimeCounterRT > 0) + { + offTimeCounterRT--; + if (offTimeCounterRT == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = onTimeRT; + } + } +} + +// --- Steuerfunktionen LED grün ------------ +void LEDS_GN_On(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + + blinkModeGN = 0; // Blinkmode zurücksetzen, falls es eingeschaltet war + onTimeCounterGN = 0; + offTimeCounterGN = 0; +} + + + +void LEDS_GN_Flash(unsigned int time) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = time; +} + +void LEDS_GN_Blink_Start(unsigned int on, unsigned int off ) +{ + onTimeGN = on; + offTimeGN = off; + blinkModeGN = 1; + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + onTimeCounterGN = on; +} + +void LEDS_GN_Off(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + blinkModeGN = 0; + offTimeCounterGN = 0; + onTimeCounterGN = 0; +} + + + +// --- Steuerfunktionen LED rot ------------ +void LEDS_RT_On(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + + blinkModeRT = 0; // Blinkmode zurücksetzen, falls es eingeschaltet war + onTimeCounterRT = 0; + offTimeCounterRT = 0; +} + + + +void LEDS_RT_Flash(unsigned int time) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = time; +} + +void LEDS_RT_Blink_Start(unsigned int on, unsigned int off ) +{ + onTimeRT = on; + offTimeRT = off; + blinkModeRT = 1; + + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + onTimeCounterRT = on; +} + +void LEDS_RT_Off(void) +{ + HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); + blinkModeRT = 0; + offTimeCounterRT = 0; + onTimeCounterRT = 0; +} Index: /trunk/firmware_v3/STM32CubeIDE/src/main.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/main.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/main.c (revision 41) @@ -0,0 +1,287 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include "button.h" +#include "buzzer.h" +#include "relais.h" +#include "leds.h" +#include "modeswitch.h" +#include "mode_mainswitch.h" +#include "mode_secondaryprotection.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +int oldTimeMSTick; +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ + //Selbsttest + // HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_SET); + // HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_SET); + // HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_SET); + // HAL_Delay(1000); +// HAL_GPIO_WritePin(GPIO_OUTPUT_BUZZER_GPIO_Port, GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); +// HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ERROR_GPIO_Port, GPIO_OUTPUT_LED_ERROR_Pin, GPIO_PIN_RESET); +// HAL_GPIO_WritePin(GPIO_OUTPUT_LED_ON_GPIO_Port, GPIO_OUTPUT_LED_ON_Pin, GPIO_PIN_RESET); + + //--- RELAIS ZURÜCKSETZEN, damit es definitiv aus ist --- + //Sicherstellen das nicht noch die Set Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_SET); + HAL_Delay(50); + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + //--- RELAIS ZURÜCKSETZEN ENDE ---- + + + + MODESWITCH_ReadMode(); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + if (oldTimeMSTick != HAL_GetTick()) + { + BUTTON_Exec(); + BUZZER_Exec(); + RELAIS_Exec(); + LEDS_Exec(); + oldTimeMSTick = HAL_GetTick(); + } + + + switch (MODESWITCH_GetMode()) + { + case MODE_MAINSWITCH: + MODE_MAINSWITCH_Exec(); + break; + + case MODE_MAINSWITCH_SECONDARYPROTECTION: + MODE_SECONDARYPROTECTION_Exec(); + break; + + default: + printf("mode not yet implemented\n"); + + } + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_0); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV4; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_OUTPUT_LED_ON_Pin|GPIO_OUTPUT_LED_ERROR_Pin|GPIO_OUTPUT_RELAIS_SET_Pin|GPIO_OUTPUT_RELAIS_RESET_Pin + |GPIO_OUTPUT_BUZZER_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : GPIO_INPUT_MODE_B3_Pin GPIO_INPUT_MODE_B2_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_MODE_B3_Pin|GPIO_INPUT_MODE_B2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_INPUT_MODE_B1_Pin GPIO_INPUT_MODE_B0_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_MODE_B1_Pin|GPIO_INPUT_MODE_B0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_INPUT_LVP_Pin GPIO_INPUT_OVP_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_LVP_Pin|GPIO_INPUT_OVP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_INPUT_BTN_ON_Pin GPIO_INPUT_BTN_OFF_Pin GPIO_INPUT_FAULT_Pin GPIO_INPUT_BMS_Pin */ + GPIO_InitStruct.Pin = GPIO_INPUT_BTN_ON_Pin|GPIO_INPUT_BTN_OFF_Pin|GPIO_INPUT_FAULT_Pin|GPIO_INPUT_BMS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : GPIO_OUTPUT_LED_ON_Pin GPIO_OUTPUT_LED_ERROR_Pin GPIO_OUTPUT_RELAIS_SET_Pin GPIO_OUTPUT_RELAIS_RESET_Pin + GPIO_OUTPUT_BUZZER_Pin */ + GPIO_InitStruct.Pin = GPIO_OUTPUT_LED_ON_Pin|GPIO_OUTPUT_LED_ERROR_Pin|GPIO_OUTPUT_RELAIS_SET_Pin|GPIO_OUTPUT_RELAIS_RESET_Pin + |GPIO_OUTPUT_BUZZER_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ Index: /trunk/firmware_v3/STM32CubeIDE/src/mode_mainswitch.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/mode_mainswitch.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/mode_mainswitch.c (revision 41) @@ -0,0 +1,235 @@ +// Keine LVP und OVP Überwachung aber Fault wird geprüft! +// Falls nicht benötigt, nicht anschließen ?! Ist Low active mit PullUp + + +// Dieser Modus ist als Hauptschaltermodus ohne BMS gedacht. Z.B. für Bleibatterien +// Oder als Hauptschalter mit Fremd BMS + + + +#include "stdio.h" +#include "mode_mainswitch.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" + +#define LED_RT_OFF_TIME 1000 +#define LED_RT_ON_TIME_WARN_MANUAL_MODE 200 +#define LED_RT_ON_TIME_WARN_FAULT_INPUT 500 + +#define LED_GN_OFF_TIME 1000 +#define LED_GN_ON_TIME_ON_MODE 200 + +#define BUZZER_OFF_TIME 1000 +#define BUZZER_ON_TIME_CONFIRM 200 +#define BUZZER_ON_TIME_REJECT 500 +#define BUZZER_ON_TIME_ALARM_MANUAL_MODE 200 + +typedef enum MAINSWITCH_State_enum +{ + MAINSWITCH_OFF, + MAINSWITCH_ON, + MAINSWITCH_MANUAL_ON, + MAINSWITCH_ERROR +} MAINSWITCH_state_t; + + +static MAINSWITCH_state_t smState; + + +void MAINSWITCH_SM_Off(void) +{ + int faultInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: MAINSWITCH_ON\n"); + smState = MAINSWITCH_ON; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + smState = MAINSWITCH_ERROR; + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: MAINSWITCH_MANUAL_ON\n"); + smState = MAINSWITCH_MANUAL_ON; + } + + + +} + +void MAINSWITCH_SM_On(void) +{ + int faultInput; + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: MAINSWITCH_OFF\n"); + smState = MAINSWITCH_OFF; + } + + //Prüfe auf Fehlermode + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME); //Fehlercode fault + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("NEW_STATE: MAINSWITCH_ERROR\n"); + smState = MAINSWITCH_ERROR; + } + + +} + +void MAINSWITCH_SM_ManualOn(void) +{ + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: MAINSWITCH_OFF\n"); + smState = MAINSWITCH_OFF; + } + +} + +void MAINSWITCH_SM_Error(void) +{ + int faultInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: MAINSWITCH_ON\n"); + smState = MAINSWITCH_ON; + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME); + printf("NEW_STATE: MAINSWITCH_MANUAL_ON\n"); + smState = MAINSWITCH_MANUAL_ON; + } + + + +} + + + +void MODE_MAINSWITCH_Exec(void) +{ + + + + switch (smState) + { + case MAINSWITCH_OFF: + MAINSWITCH_SM_Off(); + break; + + case MAINSWITCH_ON: + MAINSWITCH_SM_On(); + break; + + case MAINSWITCH_MANUAL_ON: + MAINSWITCH_SM_ManualOn(); + break; + + case MAINSWITCH_ERROR: + MAINSWITCH_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/STM32CubeIDE/src/mode_secondaryprotection.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/mode_secondaryprotection.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/mode_secondaryprotection.c (revision 41) @@ -0,0 +1,283 @@ + +// Dieser Modus ist ein Hauptschaltermodus mit Secondary Protection +// Secondary Protection lööst aus, wenn OVP und LVP wegfällt. +// Ansonsten wie Modus 0 + + + +#include "stdio.h" +#include "mode_secondaryprotection.h" +#include "button.h" +#include "relais.h" +#include "main.h" +#include "leds.h" +#include "buzzer.h" + +#define LED_RT_OFF_TIME 1000 +#define LED_RT_ON_TIME_WARN_MANUAL_MODE 200 +#define LED_RT_ON_TIME_WARN_FAULT_INPUT 500 +#define LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT 1000 + +#define LED_GN_OFF_TIME 1000 +#define LED_GN_ON_TIME_ON_MODE 200 + +#define BUZZER_OFF_TIME 1000 +#define BUZZER_ON_TIME_CONFIRM 200 +#define BUZZER_ON_TIME_REJECT 500 +#define BUZZER_ON_TIME_ALARM_MANUAL_MODE 200 + +typedef enum SECONDARYPROTECTION_State_enum +{ + SECONDARYPROTECTION_OFF, + SECONDARYPROTECTION_ON, + SECONDARYPROTECTION_MANUAL_ON, + SECONDARYPROTECTION_ERROR +} SECONDARYPROTECTION_state_t; + + +static SECONDARYPROTECTION_state_t smState; + + +void SECONDARYPROTECTION_SM_Off(void) +{ + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + lvpAndOvpInput = 1; + }else { + lvpAndOvpInput = 0; + } + + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + smState = SECONDARYPROTECTION_ON; + + } + else + { + //Wechsel nicht möglich. Fehler Eingang aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_GN_OFF_TIME); //Fehler Anzeigen + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState =SECONDARYPROTECTION_ERROR; + } + } + + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_GN_OFF_TIME); + printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + smState = SECONDARYPROTECTION_MANUAL_ON; + } + + + +} + +void SECONDARYPROTECTION_SM_On(void) +{ + int faultInput = 0; + int lvpAndOvpInput = 0; + static int lvpAndOvpInputTimeCounter = 0; + static int oldtime; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + if ((HAL_GPIO_ReadPin(GPIO_INPUT_LVP_GPIO_Port, GPIO_INPUT_LVP_Pin) == GPIO_PIN_SET) && (HAL_GPIO_ReadPin(GPIO_INPUT_OVP_GPIO_Port, GPIO_INPUT_OVP_Pin) == GPIO_PIN_SET)) + { + if (HAL_GetTick() != oldtime) + { + lvpAndOvpInputTimeCounter++; + if (lvpAndOvpInputTimeCounter > 30000) + { + lvpAndOvpInput = 1; + lvpAndOvpInputTimeCounter=0; + } + oldtime = HAL_GetTick(); + } + } + else + { + lvpAndOvpInputTimeCounter = 0; + lvpAndOvpInput = 0; + } + + + + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); //Bestätigung + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + } + + //Prüfe auf Fehlermode + if (faultInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_FAULT_INPUT, LED_RT_OFF_TIME); //Fehlercode fault + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("FAULT INPUT EVENT DETECTED!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + } + + if (lvpAndOvpInput == 1) + { + RELAIS_ResetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_REJECT); //Warnung + LEDS_GN_Off(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_OVP_AND_LVP_INPUT, LED_RT_OFF_TIME); //Fehlercode fault + BUTTON_SetModeOff(); //Damit nicht von alleine wieder eingeschaltet wird + printf("BMS SECONDARY PROTECTION FAULT EVENT DETECTED (LVP & OVP )!\n"); + printf("NEW_STATE: SECONDARYPROTECTION_ERROR\n"); + smState = SECONDARYPROTECTION_ERROR; + } + + +} + +void SECONDARYPROTECTION_SM_ManualOn(void) +{ + // Prüfe Wechsel in off mode + if (BUTTON_GetMode() == BUTTON_OFF) + { + //Ausschalten muss immer möglich sein + RELAIS_ResetPuls(); + BUZZER_Alarm_Stop(); + LEDS_GN_Off(); + LEDS_RT_Off(); + printf("NEW_STATE: SECONDARYPROTECTION_OFF\n"); + smState = SECONDARYPROTECTION_OFF; + } + +} + +void SECONDARYPROTECTION_SM_Error(void) +{ + int faultInput; + int lvpAndOvpInput; + + if (HAL_GPIO_ReadPin(GPIO_INPUT_FAULT_GPIO_Port, GPIO_INPUT_FAULT_Pin) == GPIO_PIN_RESET) + { + faultInput = 1; + } + else + { + faultInput = 0; + } + + + + //Prüfe auf Wechsel des Modus AUTO / SM ON + if (BUTTON_GetMode() == BUTTON_AUTO) + { + if (faultInput == 0) + { + RELAIS_SetPuls(); + BUZZER_Beep(BUZZER_ON_TIME_CONFIRM); + LEDS_GN_Blink_Start(LED_GN_ON_TIME_ON_MODE, LED_GN_OFF_TIME); + LEDS_RT_Off(); //Fehler löschen + printf("NEW_STATE: SECONDARYPROTECTION_ON\n"); + smState = SECONDARYPROTECTION_ON; + } + else + { + //Wechsel nicht möglich. Fehler Eingang weiterhin aktiv + BUZZER_Beep(BUZZER_ON_TIME_REJECT); + BUTTON_SetModeOff(); + } + } + + //Prüfe auf Wechsel in MANUAL ON Mode + //Keine Fehlerüberprüfungen. In diesem Modus werdem alle Alarme ignoriert. + if (BUTTON_GetMode() == BUTTON_MANUAL_ON) + { + + RELAIS_SetPuls(); + BUZZER_Alarm_Start(BUZZER_ON_TIME_ALARM_MANUAL_MODE, BUZZER_OFF_TIME); + LEDS_GN_On(); + LEDS_RT_Off(); + LEDS_RT_Blink_Start(LED_RT_ON_TIME_WARN_MANUAL_MODE, LED_RT_OFF_TIME); + printf("NEW_STATE: SECONDARYPROTECTION_MANUAL_ON\n"); + smState = SECONDARYPROTECTION_MANUAL_ON; + } + + + +} + + + +void MODE_SECONDARYPROTECTION_Exec(void) +{ + + + + switch (smState) + { + case SECONDARYPROTECTION_OFF: + SECONDARYPROTECTION_SM_Off(); + break; + + case SECONDARYPROTECTION_ON: + SECONDARYPROTECTION_SM_On(); + break; + + case SECONDARYPROTECTION_MANUAL_ON: + SECONDARYPROTECTION_SM_ManualOn(); + break; + + case SECONDARYPROTECTION_ERROR: + SECONDARYPROTECTION_SM_Error(); + break; + + default: + break; + } +} + + Index: /trunk/firmware_v3/STM32CubeIDE/src/modeswitch.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/modeswitch.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/modeswitch.c (revision 41) @@ -0,0 +1,31 @@ +#include +#include "modeswitch.h" +#include "main.h" + + +MODESWITCH_mode_t mode; + +MODESWITCH_mode_t MODESWITCH_ReadMode(void) +{ + + + int m0 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B0_GPIO_Port, GPIO_INPUT_MODE_B0_Pin) << 0); + int m1 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B1_GPIO_Port, GPIO_INPUT_MODE_B1_Pin) << 1); + int m2 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B2_GPIO_Port, GPIO_INPUT_MODE_B2_Pin) << 2); + int m3 = (HAL_GPIO_ReadPin(GPIO_INPUT_MODE_B3_GPIO_Port, GPIO_INPUT_MODE_B3_Pin) << 3); + + + + mode = m0 | m1 | m2 | m3; + mode = 0x0f &~mode; + printf("mode=%i\n",mode); + + return mode; +} + + +MODESWITCH_mode_t MODESWITCH_GetMode(void) +{ + return mode; +} + Index: /trunk/firmware_v3/STM32CubeIDE/src/relais.c =================================================================== --- /trunk/firmware_v3/STM32CubeIDE/src/relais.c (revision 41) +++ /trunk/firmware_v3/STM32CubeIDE/src/relais.c (revision 41) @@ -0,0 +1,69 @@ +#include "relais.h" +#include "main.h" + + +#define PULS_TIME 50 + + + +unsigned int onTimeCounterSET; //Set Coil +unsigned int onTimeCounterRESET; //Reset Coil +unsigned int relaisState; + + +void RELAIS_Exec(void) +{ + + if (onTimeCounterSET > 0) + { + onTimeCounterSET--; + if (onTimeCounterSET == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + } + } + + + +if (onTimeCounterRESET > 0) + { + onTimeCounterRESET--; + if (onTimeCounterRESET == 0) + { + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + } + } + +} + +void RELAIS_SetPuls(void) +{ + + //Sicherstellen das nicht noch die Reset Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_RESET); + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_SET); + onTimeCounterSET = PULS_TIME; + relaisState = 1; + +} + +void RELAIS_ResetPuls(void) +{ + + //Sicherstellen das nicht noch die Set Spule aktiv geschaltet ist + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_SET_GPIO_Port, GPIO_OUTPUT_RELAIS_SET_Pin, GPIO_PIN_RESET); + + //Puls starten + HAL_GPIO_WritePin(GPIO_OUTPUT_RELAIS_RESET_GPIO_Port, GPIO_OUTPUT_RELAIS_RESET_Pin, GPIO_PIN_SET); + onTimeCounterRESET = PULS_TIME; + relaisState = 0; + +} + + +unsigned int RELAIS_GetState(void) +{ + return relaisState; +} Index: /trunk/firmware_v3/firmware_v3.ioc =================================================================== --- /trunk/firmware_v3/firmware_v3.ioc (revision 41) +++ /trunk/firmware_v3/firmware_v3.ioc (revision 41) @@ -0,0 +1,359 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 +ADC1.ContinuousConvMode=ENABLE +ADC1.DMAContinuousRequests=ENABLE +ADC1.DiscontinuousConvMode=DISABLE +ADC1.EOCSelection=ADC_EOC_SEQ_CONV +ADC1.IPParameters=NbrOfConversionFlag,master,SelectedChannel,DiscontinuousConvMode,DMAContinuousRequests,LowPowerAutoWait,OversamplingMode,Ratio,Sequencer,SamplingTimeCommon1,ContinuousConvMode,EOCSelection,Resolution,ClockPrescaler,RightBitShift +ADC1.LowPowerAutoWait=DISABLE +ADC1.NbrOfConversionFlag=0 +ADC1.OversamplingMode=ENABLE +ADC1.Ratio=ADC_OVERSAMPLING_RATIO_256 +ADC1.Resolution=ADC_RESOLUTION_12B +ADC1.RightBitShift=ADC_RIGHTBITSHIFT_4 +ADC1.SamplingTimeCommon1=ADC_SAMPLETIME_160CYCLES_5 +ADC1.SelectedChannel=ADC_CHANNEL_2|ADC_CHANNEL_3|ADC_CHANNEL_4|ADC_CHANNEL_5|ADC_CHANNEL_TEMPSENSOR +ADC1.Sequencer=NOT_FULLY_CONFIGURABLE +ADC1.master=1 +CAD.formats= +CAD.pinconfig= +CAD.provider= +Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC1.0.EventEnable=DISABLE +Dma.ADC1.0.Instance=DMA1_Channel1 +Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.ADC1.0.MemInc=DMA_MINC_ENABLE +Dma.ADC1.0.Mode=DMA_CIRCULAR +Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE +Dma.ADC1.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.ADC1.0.Priority=DMA_PRIORITY_LOW +Dma.ADC1.0.RequestNumber=1 +Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.ADC1.0.SignalID=NONE +Dma.ADC1.0.SyncEnable=DISABLE +Dma.ADC1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.ADC1.0.SyncRequestNumber=1 +Dma.ADC1.0.SyncSignalID=NONE +Dma.Request0=ADC1 +Dma.Request1=USART1_RX +Dma.Request2=USART1_TX +Dma.RequestsNb=3 +Dma.USART1_RX.1.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART1_RX.1.EventEnable=DISABLE +Dma.USART1_RX.1.Instance=DMA1_Channel2 +Dma.USART1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART1_RX.1.MemInc=DMA_MINC_ENABLE +Dma.USART1_RX.1.Mode=DMA_NORMAL +Dma.USART1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART1_RX.1.PeriphInc=DMA_PINC_DISABLE +Dma.USART1_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART1_RX.1.Priority=DMA_PRIORITY_LOW +Dma.USART1_RX.1.RequestNumber=1 +Dma.USART1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.USART1_RX.1.SignalID=NONE +Dma.USART1_RX.1.SyncEnable=DISABLE +Dma.USART1_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART1_RX.1.SyncRequestNumber=1 +Dma.USART1_RX.1.SyncSignalID=NONE +Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART1_TX.2.EventEnable=DISABLE +Dma.USART1_TX.2.Instance=DMA1_Channel3 +Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE +Dma.USART1_TX.2.Mode=DMA_NORMAL +Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE +Dma.USART1_TX.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART1_TX.2.Priority=DMA_PRIORITY_LOW +Dma.USART1_TX.2.RequestNumber=1 +Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.USART1_TX.2.SignalID=NONE +Dma.USART1_TX.2.SyncEnable=DISABLE +Dma.USART1_TX.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART1_TX.2.SyncRequestNumber=1 +Dma.USART1_TX.2.SyncSignalID=NONE +File.Version=6 +GPIO.groupedBy=Group By Peripherals +IWDG.IPParameters=Prescaler,Window,Reload +IWDG.Prescaler=IWDG_PRESCALER_32 +IWDG.Reload=1000 +IWDG.Window=1000 +KeepUserPlacement=false +Mcu.CPN=STM32C031K4T6 +Mcu.Family=STM32C0 +Mcu.IP0=ADC1 +Mcu.IP1=CORTEX_M0+ +Mcu.IP10=USART1 +Mcu.IP2=DEBUG +Mcu.IP3=DMA +Mcu.IP4=IWDG +Mcu.IP5=NVIC +Mcu.IP6=RCC +Mcu.IP7=SYS +Mcu.IP8=TIM16 +Mcu.IP9=TIM17 +Mcu.IPNb=11 +Mcu.Name=STM32C031K(4-6)Tx +Mcu.Package=LQFP32 +Mcu.Pin0=PB9 +Mcu.Pin1=PC14-OSCX_IN (PC14) +Mcu.Pin10=PA7 +Mcu.Pin11=PB0 +Mcu.Pin12=PB1 +Mcu.Pin13=PB2 +Mcu.Pin14=PA8 +Mcu.Pin15=PA9 +Mcu.Pin16=PC6 +Mcu.Pin17=PA10 +Mcu.Pin18=PA12 [PA10] +Mcu.Pin19=PA13 +Mcu.Pin2=PC15-OSCX_OUT (PC15) +Mcu.Pin20=PA14-BOOT0 +Mcu.Pin21=PA15 +Mcu.Pin22=PB3 +Mcu.Pin23=PB4 +Mcu.Pin24=PB5 +Mcu.Pin25=PB6 +Mcu.Pin26=PB7 +Mcu.Pin27=PB8 +Mcu.Pin28=VP_ADC1_TempSens_Input +Mcu.Pin29=VP_IWDG_VS_IWDG +Mcu.Pin3=PA0 +Mcu.Pin30=VP_SYS_VS_Systick +Mcu.Pin31=VP_TIM16_VS_ClockSourceINT +Mcu.Pin32=VP_TIM17_VS_ClockSourceINT +Mcu.Pin4=PA1 +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PA4 +Mcu.Pin8=PA5 +Mcu.Pin9=PA6 +Mcu.PinsNb=33 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32C031K4Tx +MxCube.Version=6.17.0 +MxDb.Version=DB.6.0.170 +NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Channel2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true\:false +NVIC.TIM16_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +PA0.GPIOParameters=GPIO_PuPd,GPIO_Label +PA0.GPIO_Label=GPIO_INPUT_LVP +PA0.GPIO_PuPd=GPIO_PULLUP +PA0.Locked=true +PA0.Signal=GPIO_Input +PA1.GPIOParameters=GPIO_PuPd,GPIO_Label +PA1.GPIO_Label=GPIO_INPUT_OVP +PA1.GPIO_PuPd=GPIO_PULLUP +PA1.Locked=true +PA1.Signal=GPIO_Input +PA10.Locked=true +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA12\ [PA10].GPIOParameters=GPIO_Label +PA12\ [PA10].GPIO_Label=R1 +PA12\ [PA10].Locked=true +PA12\ [PA10].Signal=GPIO_Input +PA13.Mode=Serial_Wire +PA13.Signal=DEBUG_SWDIO +PA14-BOOT0.Mode=Serial_Wire +PA14-BOOT0.Signal=DEBUG_SWCLK +PA15.GPIOParameters=GPIO_Label +PA15.GPIO_Label=R2 +PA15.Locked=true +PA15.Signal=GPIO_Input +PA2.GPIOParameters=GPIO_Label +PA2.GPIO_Label=ADC1_IN2_TEMP_SENSOR +PA2.Mode=IN2 +PA2.Signal=ADC1_IN2 +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=ADC1_IN3_U_IN +PA3.Mode=IN3 +PA3.Signal=ADC1_IN3 +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=ADC1_IN4_U_OUT +PA4.Mode=IN4 +PA4.Signal=ADC1_IN4 +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=ADC1_IN5_RES1 +PA5.Mode=IN5 +PA5.Signal=ADC1_IN5 +PA6.GPIOParameters=GPIO_PuPd,GPIO_Label +PA6.GPIO_Label=FAN_TACHO +PA6.GPIO_PuPd=GPIO_PULLUP +PA6.Locked=true +PA6.Signal=S_TIM16_CH1 +PA7.GPIOParameters=GPIO_Label +PA7.GPIO_Label=FAN_PWM +PA7.Locked=true +PA7.Signal=S_TIM17_CH1 +PA8.GPIOParameters=GPIO_Label +PA8.GPIO_Label=GPIO_OUTPUT_10V_EN +PA8.Locked=true +PA8.Signal=GPIO_Output +PA9.Locked=true +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB0.GPIOParameters=GPIO_PuPd,GPIO_Label +PB0.GPIO_Label=GPIO_INPUT_BTN_ON +PB0.GPIO_PuPd=GPIO_PULLUP +PB0.Locked=true +PB0.Signal=GPIO_Input +PB1.GPIOParameters=GPIO_PuPd,GPIO_Label +PB1.GPIO_Label=GPIO_INPUT_BTN_OFF +PB1.GPIO_PuPd=GPIO_PULLUP +PB1.Locked=true +PB1.Signal=GPIO_Input +PB2.GPIOParameters=GPIO_PuPd,GPIO_Label +PB2.GPIO_Label=GPIO_INPUT_FAULT +PB2.GPIO_PuPd=GPIO_PULLUP +PB2.Locked=true +PB2.Signal=GPIO_Input +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=GPIO_OUTPUT_RELAIS_SET +PB3.Locked=true +PB3.Signal=GPIO_Output +PB4.GPIOParameters=GPIO_Label +PB4.GPIO_Label=GPIO_OUTPUT_RELAIS_RESET +PB4.Locked=true +PB4.Signal=GPIO_Output +PB5.GPIOParameters=GPIO_Label +PB5.GPIO_Label=GPIO_OUTPUT_BUZZER +PB5.Locked=true +PB5.Signal=GPIO_Output +PB6.GPIOParameters=GPIO_PuPd,GPIO_Label +PB6.GPIO_Label=GPIO_INPUT_MODE_B0 +PB6.GPIO_PuPd=GPIO_PULLUP +PB6.Locked=true +PB6.Signal=GPIO_Input +PB7.GPIOParameters=GPIO_PuPd,GPIO_Label +PB7.GPIO_Label=GPIO_INPUT_MODE_B1 +PB7.GPIO_PuPd=GPIO_PULLUP +PB7.Locked=true +PB7.Signal=GPIO_Input +PB8.GPIOParameters=GPIO_PuPd,GPIO_Label +PB8.GPIO_Label=GPIO_INPUT_MODE_B2 +PB8.GPIO_PuPd=GPIO_PULLUP +PB8.Locked=true +PB8.Signal=GPIO_Input +PB9.GPIOParameters=GPIO_PuPd,GPIO_Label +PB9.GPIO_Label=GPIO_INPUT_MODE_B3 +PB9.GPIO_PuPd=GPIO_PULLUP +PB9.Locked=true +PB9.Signal=GPIO_Input +PC14-OSCX_IN\ (PC14).GPIOParameters=GPIO_Label +PC14-OSCX_IN\ (PC14).GPIO_Label=GPIO_OUTPUT_LED_ON +PC14-OSCX_IN\ (PC14).Locked=true +PC14-OSCX_IN\ (PC14).Signal=GPIO_Output +PC15-OSCX_OUT\ (PC15).GPIOParameters=GPIO_Label +PC15-OSCX_OUT\ (PC15).GPIO_Label=GPIO_OUTPUT_LED_ERROR +PC15-OSCX_OUT\ (PC15).Locked=true +PC15-OSCX_OUT\ (PC15).Signal=GPIO_Output +PC6.GPIOParameters=GPIO_Label +PC6.GPIO_Label=GPIO_INPUT_BMS +PC6.Locked=true +PC6.Signal=GPIO_Input +PCC.Checker=false +PCC.Display=Plot\: All Steps +PCC.Line=STM32C0x1 +PCC.MCU=STM32C031K(4-6)Tx +PCC.PartNumber=STM32C031K4Tx +PCC.Series=STM32C0 +PCC.Temperature=25 +PCC.Vdd=3.0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32C031K4Tx +ProjectManager.FirmwarePackage=STM32Cube FW_C0 V1.4.0 +ProjectManager.FreePins=false +ProjectManager.FreePinsContext= +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=firmware_v3.ioc +ProjectManager.ProjectName=firmware_v3 +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_TIM17_Init-TIM17-false-HAL-true,6-MX_USART1_UART_Init-USART1-false-HAL-true,7-MX_TIM16_Init-TIM16-false-HAL-true,8-MX_IWDG_Init-IWDG-false-HAL-true,0-MX_CORTEX_M0+_Init-CORTEX_M0+-false-HAL-true +RCC.ADCFreq_Value=12000000 +RCC.AHBFreq_Value=12000000 +RCC.APBFreq_Value=12000000 +RCC.APBTimFreq_Value=12000000 +RCC.CortexFreq_Value=12000000 +RCC.EXTERNAL_CLOCK_VALUE=12288000 +RCC.FCLKCortexFreq_Value=12000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=12000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=48000000 +RCC.I2C1Freq_Value=12000000 +RCC.I2S1Freq_Value=12000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,PWRFreq_Value,SYSCLKFreq_VALUE,USART1Freq_Value +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=12000000 +RCC.MCO2PinFreq_Value=12000000 +RCC.PWRFreq_Value=12000000 +RCC.SYSCLKFreq_VALUE=12000000 +RCC.USART1Freq_Value=12000000 +SH.S_TIM16_CH1.0=TIM16_CH1,Input_Capture1_from_TI1 +SH.S_TIM16_CH1.ConfNb=1 +SH.S_TIM17_CH1.0=TIM17_CH1,PWM Generation1 CH1 +SH.S_TIM17_CH1.ConfNb=1 +TIM16.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE +TIM16.Channel=TIM_CHANNEL_1 +TIM16.ICPolarity_CH1=TIM_INPUTCHANNELPOLARITY_FALLING +TIM16.IPParameters=Channel,Prescaler,AutoReloadPreload,ICPolarity_CH1 +TIM16.Prescaler=119 +TIM17.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE +TIM17.Channel=TIM_CHANNEL_1 +TIM17.IPParameters=Channel,Period,AutoReloadPreload,OCPolarity_1,Pulse +TIM17.OCPolarity_1=TIM_OCPOLARITY_LOW +TIM17.Period=479 +TIM17.Pulse=0 +USART1.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE +USART1.BaudRate=19200 +USART1.IPParameters=VirtualMode-Asynchronous,WordLength,Parity,AutoBaudRateEnableParam,BaudRate +USART1.Parity=PARITY_EVEN +USART1.VirtualMode-Asynchronous=VM_ASYNC +USART1.WordLength=WORDLENGTH_9B +VP_ADC1_TempSens_Input.Mode=IN-TempSens +VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT +VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT +board=custom